* Re: Linux 2.6.x on 8xx status
From: Guillaume Autran @ 2005-03-21 21:45 UTC (permalink / raw)
To: linux-ppc-embedded; +Cc: Smith, Craig
In-Reply-To: <20050210170859.GB20153@logos.cnet>
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Hi,
Was there any progress made about this issue or is it still pending ?
I'm running 2.6.11 and still see the problem...
Regards,
Guillaume.
Marcelo Tosatti wrote:
>On Thu, Feb 10, 2005 at 03:06:58PM -0200, Marcelo Tosatti wrote:
>
>
>>On Thu, Feb 10, 2005 at 02:26:52PM -0500, Dan Malek wrote:
>>
>>
>>>On Feb 10, 2005, at 10:04 AM, Marcelo Tosatti wrote:
>>>
>>>
>>>
>>>>Does anyone have a clue of what is/can be wrong with the TLB entry for
>>>>the
>>>>address being flushed at __flush_dcache_icache()?
>>>>
>>>>
>>>Not sure. The problem is that the __flush_dcache_icache is passed a
>>>user space virtual address that doesn't look like it is mapped for
>>>writing
>>>or something. I don't know, as an ooops isn't sufficient to debug the
>>>problem.
>>>You have to catch it here and track down the current state of the TLB
>>>and
>>>the page tables. Of course, when I do this everything looks OK,
>>>
>>>
>>How do you do track down the current TLB state? With a BDI?
>>
>>
>>
>>>so what I've been trying to do is catch the TLBmiss reload that actually causes
>>>this
>>>to happen to see what it really tried to load into the tlb.
>>>
>>>
>>Shouldnt it be loading the TLB entry which "seem to be OK" accordingly to your
>>analysis ??
>>
>>
>
>So this assumption which you have made sometime ago is wrong, given that now you
>know TLB entry is not stale ?
>
>"The symptom is we appear to have a stale TLB entry,
>so at least one of the callouts from the generic VM
>code isn't doing the right thing for us. I'm still
>puzzled as to why it doesn't affect other PPC processor."
>
>_______________________________________________
>Linuxppc-embedded mailing list
>Linuxppc-embedded@ozlabs.org
>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
>
--
=======================================
Guillaume Autran
Senior Software Engineer
MRV Communications, Inc.
Tel: (978) 952-4932 office
E-mail: gautran@mrv.com
=======================================
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^ permalink raw reply
* Re: Linux 2.6.x on 8xx status
From: Robert P. J. Day @ 2005-03-21 21:53 UTC (permalink / raw)
To: Guillaume Autran; +Cc: Smith, Craig, linux-ppc-embedded
In-Reply-To: <423F4071.1000001@mrv.com>
On Mon, 21 Mar 2005, Guillaume Autran wrote:
> Hi,
>
> Was there any progress made about this issue or is it still pending
> ? I'm running 2.6.11 and still see the problem...
when you say "2.6.11", does this mean you're building from a stock
kernel release? these days, where's the canonical source for
2.6.x-based kernels for embedded ppc? as i recall, it was bkbits,
linuxppc-2.5, but it's been a while since i've messed around with
that.
rday
^ permalink raw reply
* [PATCH] ppc32: Report chipset version in common /proc/cpuinfo handling
From: Kumar Gala @ 2005-03-21 22:30 UTC (permalink / raw)
To: Andrew Morton; +Cc: linux-kernel, linuxppc-embedded
Andrew,
Moved reporting of chipset revision from board specific to common handing
of /proc/cpuinfo. In light of numerous PPC system-on-chip devices, we
report both the cpu version (reflects the core version) and the chipset
version (reflects the system-on-chip or bridge version).
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
diff -Nru a/arch/ppc/kernel/setup.c b/arch/ppc/kernel/setup.c
--- a/arch/ppc/kernel/setup.c 2005-03-21 16:20:24 -06:00
+++ b/arch/ppc/kernel/setup.c 2005-03-21 16:20:24 -06:00
@@ -40,6 +40,7 @@
#include <asm/nvram.h>
#include <asm/xmon.h>
#include <asm/ocp.h>
+#include <asm/ppc_sys.h>
#if defined CONFIG_KGDB
#include <asm/kgdb.h>
@@ -245,6 +246,12 @@
seq_printf(m, "bogomips\t: %lu.%02lu\n",
lpj / (500000/HZ), (lpj / (5000/HZ)) % 100);
+
+#if defined (CONFIG_85xx) || defined (CONFIG_83xx)
+ if (cur_ppc_sys_spec->ppc_sys_name)
+ seq_printf(m, "chipset\t\t: %s\n",
+ cur_ppc_sys_spec->ppc_sys_name);
+#endif
#ifdef CONFIG_SMP
seq_printf(m, "\n");
diff -Nru a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c
--- a/arch/ppc/platforms/83xx/mpc834x_sys.c 2005-03-21 16:20:24 -06:00
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.c 2005-03-21 16:20:24 -06:00
@@ -143,7 +143,6 @@
pvid = mfspr(SPRN_PVR);
svid = mfspr(SPRN_SVR);
- seq_printf(m, "chip\t\t: MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "Vendor\t\t: Freescale Inc.\n");
seq_printf(m, "Machine\t\t: mpc%s sys\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "core clock\t: %d MHz\n"
diff -Nru a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c 2005-03-21 16:20:24 -06:00
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c 2005-03-21 16:20:24 -06:00
@@ -129,7 +129,6 @@
pvid = mfspr(SPRN_PVR);
svid = mfspr(SPRN_SVR);
- seq_printf(m, "chip\t\t: MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
seq_printf(m, "Machine\t\t: mpc%sads\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
diff -Nru a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c 2005-03-21 16:20:24 -06:00
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c 2005-03-21 16:20:24 -06:00
@@ -146,7 +146,6 @@
pvid = mfspr(SPRN_PVR);
svid = mfspr(SPRN_SVR);
- seq_printf(m, "chip\t\t: MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
diff -Nru a/arch/ppc/platforms/85xx/sbc85xx.c b/arch/ppc/platforms/85xx/sbc85xx.c
--- a/arch/ppc/platforms/85xx/sbc85xx.c 2005-03-21 16:20:24 -06:00
+++ b/arch/ppc/platforms/85xx/sbc85xx.c 2005-03-21 16:20:24 -06:00
@@ -129,7 +129,6 @@
pvid = mfspr(SPRN_PVR);
svid = mfspr(SPRN_SVR);
- seq_printf(m, "chip\t\t: MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "Vendor\t\t: Wind River\n");
seq_printf(m, "Machine\t\t: SBC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
diff -Nru a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
--- a/arch/ppc/platforms/85xx/stx_gp3.c 2005-03-21 16:20:24 -06:00
+++ b/arch/ppc/platforms/85xx/stx_gp3.c 2005-03-21 16:20:24 -06:00
@@ -268,7 +268,6 @@
memsize = total_memory;
- seq_printf(m, "chip\t\t: MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
^ permalink raw reply
* [PATCH 0/6] [RFC] Change MPC52xx to platform bus / ppc_sys model
From: Sylvain Munaut @ 2005-03-21 23:06 UTC (permalink / raw)
To: ML linuxppc-embedded
Hi all,
This series of patch changes all the MPC52xx related code
to use platform bus and ppc_sys instead of OCP. It's
divided in several patches that represents "steps" in
the conversion. However the intermediate states might
not be functionnal.
This is the first try, comments and suggestions are
welcomed.
Sylvain
^ permalink raw reply
* [PATCH 1/6] ppc32: Remove unnecessary test in MPC52xx reset code
From: Sylvain Munaut @ 2005-03-21 23:07 UTC (permalink / raw)
To: ML linuxppc-embedded
In-Reply-To: <0.20050322_000905.tnt@patchsend.246tNt.com>
ppc32: Remove unnecessary test in MPC52xx reset code
That test is part of an old version of the code and
erroneously made it to mainstream.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
diff -Nru a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c
--- a/arch/ppc/syslib/mpc52xx_setup.c 2005-03-21 20:09:24 +01:00
+++ b/arch/ppc/syslib/mpc52xx_setup.c 2005-03-21 20:09:24 +01:00
@@ -46,11 +46,8 @@
/* Turn on the watchdog and wait for it to expire. It effectively
does a reset */
- if (gpt0 != NULL) {
- out_be32(&gpt0->count, 0x000000ff);
- out_be32(&gpt0->mode, 0x00009004);
- } else
- printk(KERN_ERR "mpc52xx_restart: Unable to ioremap GPT0 registers, -> looping ...");
+ out_be32(&gpt0->count, 0x000000ff);
+ out_be32(&gpt0->mode, 0x00009004);
while (1);
}
^ permalink raw reply
* [PATCH 2/6] ppc32: Remove the OCP system from the Freescale MPC52xx support
From: Sylvain Munaut @ 2005-03-21 23:07 UTC (permalink / raw)
To: ML linuxppc-embedded
In-Reply-To: <0.20050322_000905.tnt@patchsend.246tNt.com>
ppc32: Remove the OCP system from the Freescale MPC52xx support
We remove all usage of the OCP system as preparation to switch
to the platform bus model / ppc_sys model.
This is only for 'generic' support, drivers are adapted separatly,
afterwards.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
diff -Nru a/arch/ppc/Kconfig b/arch/ppc/Kconfig
--- a/arch/ppc/Kconfig 2005-03-21 20:09:47 +01:00
+++ b/arch/ppc/Kconfig 2005-03-21 20:09:47 +01:00
@@ -822,7 +822,7 @@
config FSL_OCP
bool
- depends on MPC10X_BRIDGE || PPC_MPC52xx
+ depends on MPC10X_BRIDGE
default y
config MPC10X_OPENPIC
diff -Nru a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
--- a/arch/ppc/platforms/Makefile 2005-03-21 20:09:47 +01:00
+++ b/arch/ppc/platforms/Makefile 2005-03-21 20:09:47 +01:00
@@ -45,7 +45,7 @@
obj-$(CONFIG_SANDPOINT) += sandpoint.o
obj-$(CONFIG_SBC82xx) += sbc82xx.o
obj-$(CONFIG_SPRUCE) += spruce.o
-obj-$(CONFIG_LITE5200) += lite5200.o mpc5200.o
+obj-$(CONFIG_LITE5200) += lite5200.o
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_PPC_PMAC) += pmac_smp.o
diff -Nru a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
--- a/arch/ppc/platforms/lite5200.c 2005-03-21 20:09:47 +01:00
+++ b/arch/ppc/platforms/lite5200.c 2005-03-21 20:09:47 +01:00
@@ -13,7 +13,7 @@
* Dale Farnsworth <dale.farnsworth@mvista.com> and
* Wolfgang Denk <wd@denx.de>
*
- * Copyright 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright 2004-2005 Sylvain Munaut <tnt@246tNt.com>
* Copyright 2003 Motorola Inc.
* Copyright 2003 MontaVista Software Inc.
* Copyright 2003 DENX Software Engineering (wd@denx.de)
@@ -29,10 +29,10 @@
#include <linux/kdev_t.h>
#include <linux/root_dev.h>
#include <linux/console.h>
+#include <linux/module.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
-#include <asm/ocp.h>
#include <asm/mpc52xx.h>
#include <syslib/mpc52xx_pci.h>
@@ -46,31 +46,6 @@
/* ======================================================================== */
-/* OCP device definition */
-/* For board/shared resources like PSCs */
-/* ======================================================================== */
-/* Be sure not to load conficting devices : e.g. loading the UART drivers for
- * PSC1 and then also loading a AC97 for this same PSC.
- * For details about how to create an entry, look in the doc of the concerned
- * driver ( eg drivers/serial/mpc52xx_uart.c for the PSC in uart mode )
- */
-
-static struct ocp_def board_ocp[] = {
- {
- .vendor = OCP_VENDOR_FREESCALE,
- .function = OCP_FUNC_PSC_UART,
- .index = 0,
- .paddr = MPC52xx_PSC1,
- .irq = MPC52xx_PSC1_IRQ,
- .pm = OCP_CPM_NA,
- },
- { /* Terminating entry */
- .vendor = OCP_VENDOR_INVALID
- }
-};
-
-
-/* ======================================================================== */
/* Platform specific code */
/* ======================================================================== */
@@ -131,9 +106,6 @@
static void __init
lite5200_setup_arch(void)
{
- /* Add board OCP definitions */
- mpc52xx_add_board_devices(board_ocp);
-
/* CPU & Port mux setup */
lite5200_setup_cpu();
diff -Nru a/arch/ppc/platforms/mpc5200.c b/arch/ppc/platforms/mpc5200.c
--- a/arch/ppc/platforms/mpc5200.c 2005-03-21 20:09:47 +01:00
+++ /dev/null Wed Dec 31 16:00:00 196900
@@ -1,53 +0,0 @@
-/*
- * arch/ppc/platforms/mpc5200.c
- *
- * OCP Definitions for the boards based on MPC5200 processor. Contains
- * definitions for every common peripherals. (Mostly all but PSCs)
- *
- * Maintainer : Sylvain Munaut <tnt@246tNt.com>
- *
- * Copyright 2004 Sylvain Munaut <tnt@246tNt.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <asm/ocp.h>
-#include <asm/mpc52xx.h>
-
-
-static struct ocp_fs_i2c_data mpc5200_i2c_def = {
- .flags = FS_I2C_CLOCK_5200,
-};
-
-
-/* Here is the core_ocp struct.
- * With all the devices common to all board. Even if port multiplexing is
- * not setup for them (if the user don't want them, just don't select the
- * config option). The potentially conflicting devices (like PSCs) goes in
- * board specific file.
- */
-struct ocp_def core_ocp[] = {
- {
- .vendor = OCP_VENDOR_FREESCALE,
- .function = OCP_FUNC_IIC,
- .index = 0,
- .paddr = MPC52xx_I2C1,
- .irq = OCP_IRQ_NA, /* MPC52xx_IRQ_I2C1 - Buggy */
- .pm = OCP_CPM_NA,
- .additions = &mpc5200_i2c_def,
- },
- {
- .vendor = OCP_VENDOR_FREESCALE,
- .function = OCP_FUNC_IIC,
- .index = 1,
- .paddr = MPC52xx_I2C2,
- .irq = OCP_IRQ_NA, /* MPC52xx_IRQ_I2C2 - Buggy */
- .pm = OCP_CPM_NA,
- .additions = &mpc5200_i2c_def,
- },
- { /* Terminating entry */
- .vendor = OCP_VENDOR_INVALID
- }
-};
diff -Nru a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c
--- a/arch/ppc/syslib/mpc52xx_setup.c 2005-03-21 20:09:47 +01:00
+++ b/arch/ppc/syslib/mpc52xx_setup.c 2005-03-21 20:09:47 +01:00
@@ -23,7 +23,6 @@
#include <asm/time.h>
#include <asm/mpc52xx.h>
#include <asm/mpc52xx_psc.h>
-#include <asm/ocp.h>
#include <asm/pgtable.h>
#include <asm/ppcboot.h>
@@ -218,12 +217,3 @@
tb_ticks_per_jiffy = xlbfreq / HZ / divisor;
tb_to_us = mulhwu_scale_factor(xlbfreq / divisor, 1000000);
}
-
-
-void __init
-mpc52xx_add_board_devices(struct ocp_def board_ocp[]) {
- while (board_ocp->vendor != OCP_VENDOR_INVALID)
- if(ocp_add_one_device(board_ocp++))
- printk("mpc5200-ocp: Failed to add board device !\n");
-}
-
diff -Nru a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
--- a/include/asm-ppc/mpc52xx.h 2005-03-21 20:09:47 +01:00
+++ b/include/asm-ppc/mpc52xx.h 2005-03-21 20:09:47 +01:00
@@ -26,7 +26,6 @@
#include <asm/types.h>
struct pt_regs;
-struct ocp_def;
#endif /* __ASSEMBLY__ */
@@ -391,7 +390,6 @@
extern void mpc52xx_power_off(void);
extern void mpc52xx_progress(char *s, unsigned short hex);
extern void mpc52xx_calibrate_decr(void);
-extern void mpc52xx_add_board_devices(struct ocp_def board_ocp[]);
extern void mpc52xx_find_bridges(void);
^ permalink raw reply
* [PATCH 3/6] ppc32: Change constants style in Freescale MPC52xx related code
From: Sylvain Munaut @ 2005-03-21 23:08 UTC (permalink / raw)
To: ML linuxppc-embedded
In-Reply-To: <0.20050322_000905.tnt@patchsend.246tNt.com>
ppc32: Change constants style in Freescale MPC52xx related code
This patch changes the way the constants used for register block
address are defined/used. This is a preparation for the use of
the platform bus / ppc_sys model.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
diff -Nru a/arch/ppc/boot/simple/mpc52xx_tty.c b/arch/ppc/boot/simple/mpc52xx_tty.c
--- a/arch/ppc/boot/simple/mpc52xx_tty.c 2005-03-21 20:10:10 +01:00
+++ b/arch/ppc/boot/simple/mpc52xx_tty.c 2005-03-21 20:10:10 +01:00
@@ -20,32 +20,31 @@
#include <asm/io.h>
#include <asm/time.h>
-#if MPC52xx_PF_CONSOLE_PORT == 0
-#define MPC52xx_CONSOLE MPC52xx_PSC1
-#define MPC52xx_PSC_CONFIG_SHIFT 0
-#elif MPC52xx_PF_CONSOLE_PORT == 1
-#define MPC52xx_CONSOLE MPC52xx_PSC2
-#define MPC52xx_PSC_CONFIG_SHIFT 4
-#elif MPC52xx_PF_CONSOLE_PORT == 2
-#define MPC52xx_CONSOLE MPC52xx_PSC3
-#define MPC52xx_PSC_CONFIG_SHIFT 8
+
+#ifdef MPC52xx_PF_CONSOLE_PORT
+#define MPC52xx_CONSOLE MPC52xx_PSCx_OFFSET(MPC52xx_PF_CONSOLE_PORT)
+#define MPC52xx_PSC_CONFIG_SHIFT ((MPC52xx_PF_CONSOLE_PORT-1)<<2)
#else
#error "MPC52xx_PF_CONSOLE_PORT not defined"
#endif
static struct mpc52xx_psc __iomem *psc =
- (struct mpc52xx_psc __iomem *) MPC52xx_CONSOLE;
+ (struct mpc52xx_psc __iomem *) MPC52xx_PA(MPC52xx_CONSOLE);
/* The decrementer counts at the system bus clock frequency
* divided by four. The most accurate time base is connected to the
- * rtc. We read the decrementer change during one rtc tick (one second)
- * and multiply by 4 to get the system bus clock frequency.
+ * rtc. We read the decrementer change during one rtc tick
+ * and multiply by 4 to get the system bus clock frequency. Since a
+ * rtc tick is one seconds, and that's pretty long, we change the rtc
+ * dividers temporarly to set them 64x faster ;)
*/
static int
mpc52xx_ipbfreq(void)
{
- struct mpc52xx_rtc __iomem *rtc = (struct mpc52xx_rtc __iomem *)MPC52xx_RTC;
- struct mpc52xx_cdm __iomem *cdm = (struct mpc52xx_cdm __iomem *)MPC52xx_CDM;
+ struct mpc52xx_rtc __iomem *rtc =
+ (struct mpc52xx_rtc __iomem *) MPC52xx_PA(MPC52xx_RTC_OFFSET);
+ struct mpc52xx_cdm __iomem *cdm =
+ (struct mpc52xx_cdm __iomem *) MPC52xx_PA(MPC52xx_CDM_OFFSET);
int current_time, previous_time;
int tbl_start, tbl_end;
int xlbfreq, ipbfreq;
@@ -68,7 +67,8 @@
unsigned long
serial_init(int ignored, void *ignored2)
{
- struct mpc52xx_gpio __iomem *gpio = (struct mpc52xx_gpio __iomem *)MPC52xx_GPIO;
+ struct mpc52xx_gpio __iomem *gpio =
+ (struct mpc52xx_gpio __iomem *) MPC52xx_PA(MPC52xx_GPIO_OFFSET);
int divisor;
int mode1;
int mode2;
diff -Nru a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
--- a/arch/ppc/platforms/lite5200.c 2005-03-21 20:10:10 +01:00
+++ b/arch/ppc/platforms/lite5200.c 2005-03-21 20:10:10 +01:00
@@ -73,8 +73,8 @@
u32 intr_ctrl;
/* Map zones */
- xlb = ioremap(MPC52xx_XLB,sizeof(struct mpc52xx_xlb));
- intr = ioremap(MPC52xx_INTR,sizeof(struct mpc52xx_intr));
+ xlb = ioremap(MPC52xx_PA(MPC52xx_XLB_OFFSET), MPC52xx_XLB_SIZE);
+ intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
if (!xlb || !intr) {
printk("lite5200.c: Error while mapping XLB/INTR during "
diff -Nru a/arch/ppc/platforms/lite5200.h b/arch/ppc/platforms/lite5200.h
--- a/arch/ppc/platforms/lite5200.h 2005-03-21 20:10:10 +01:00
+++ b/arch/ppc/platforms/lite5200.h 2005-03-21 20:10:10 +01:00
@@ -17,7 +17,7 @@
#define __PLATFORMS_LITE5200_H__
/* Serial port used for low-level debug */
-#define MPC52xx_PF_CONSOLE_PORT 0 /* PSC1 */
+#define MPC52xx_PF_CONSOLE_PORT 1 /* PSC1 */
#endif /* __PLATFORMS_LITE5200_H__ */
diff -Nru a/arch/ppc/syslib/mpc52xx_pci.c b/arch/ppc/syslib/mpc52xx_pci.c
--- a/arch/ppc/syslib/mpc52xx_pci.c 2005-03-21 20:10:10 +01:00
+++ b/arch/ppc/syslib/mpc52xx_pci.c 2005-03-21 20:10:10 +01:00
@@ -183,7 +183,7 @@
pci_assign_all_busses = 1;
- pci_regs = ioremap(MPC52xx_PCI, sizeof(struct mpc52xx_pci));
+ pci_regs = ioremap(MPC52xx_PA(MPC52xx_PCI_OFFSET), MPC52xx_PCI_SIZE);
if (!pci_regs)
return;
diff -Nru a/arch/ppc/syslib/mpc52xx_pic.c b/arch/ppc/syslib/mpc52xx_pic.c
--- a/arch/ppc/syslib/mpc52xx_pic.c 2005-03-21 20:10:10 +01:00
+++ b/arch/ppc/syslib/mpc52xx_pic.c 2005-03-21 20:10:10 +01:00
@@ -180,8 +180,8 @@
u32 intr_ctrl;
/* Remap the necessary zones */
- intr = ioremap(MPC52xx_INTR, sizeof(struct mpc52xx_intr));
- sdma = ioremap(MPC52xx_SDMA, sizeof(struct mpc52xx_sdma));
+ intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
+ sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE);
if ((intr==NULL) || (sdma==NULL))
panic("Can't ioremap PIC/SDMA register for init_irq !");
diff -Nru a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c
--- a/arch/ppc/syslib/mpc52xx_setup.c 2005-03-21 20:10:10 +01:00
+++ b/arch/ppc/syslib/mpc52xx_setup.c 2005-03-21 20:10:10 +01:00
@@ -38,8 +38,7 @@
void
mpc52xx_restart(char *cmd)
{
- struct mpc52xx_gpt __iomem *gpt0 =
- (struct mpc52xx_gpt __iomem *) MPC52xx_GPTx(0);
+ struct mpc52xx_gpt __iomem *gpt0 = MPC52xx_VA(MPC52xx_GPTx_OFFSET(0));
local_irq_disable();
@@ -92,9 +91,7 @@
#ifdef CONFIG_SERIAL_TEXT_DEBUG
-#ifdef MPC52xx_PF_CONSOLE_PORT
-#define MPC52xx_CONSOLE MPC52xx_PSCx(MPC52xx_PF_CONSOLE_PORT)
-#else
+#ifndef MPC52xx_PF_CONSOLE_PORT
#error "mpc52xx PSC for console not selected"
#endif
@@ -110,8 +107,9 @@
mpc52xx_progress(char *s, unsigned short hex)
{
char c;
- struct mpc52xx_psc __iomem *psc =
- (struct mpc52xx_psc __iomem *)MPC52xx_CONSOLE;
+ struct mpc52xx_psc __iomem *psc;
+
+ psc = MPC52xx_VA(MPC52xx_PSCx_OFFSET(MPC52xx_PF_CONSOLE_PORT));
while ((c = *s++) != 0) {
if (c == '\n')
@@ -140,7 +138,7 @@
u32 sdram_config_0, sdram_config_1;
/* Temp BAT2 mapping active when this is called ! */
- mmap_ctl = (struct mpc52xx_mmap_ctl __iomem *) MPC52xx_MMAP_CTL;
+ mmap_ctl = MPC52xx_VA(MPC52xx_MMAP_CTL_OFFSET);
sdram_config_0 = in_be32(&mmap_ctl->sdram0);
sdram_config_1 = in_be32(&mmap_ctl->sdram1);
@@ -170,8 +168,8 @@
struct mpc52xx_rtc __iomem *rtc;
struct mpc52xx_cdm __iomem *cdm;
- rtc = ioremap(MPC52xx_RTC, sizeof(struct mpc52xx_rtc));
- cdm = ioremap(MPC52xx_CDM, sizeof(struct mpc52xx_cdm));
+ rtc = ioremap(MPC52xx_PA(MPC52xx_RTC_OFFSET), MPC52xx_RTC_SIZE);
+ cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE);
if ((rtc==NULL) || (cdm==NULL))
panic("Can't ioremap RTC/CDM while computing bus freq");
diff -Nru a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
--- a/include/asm-ppc/mpc52xx.h 2005-03-21 20:10:10 +01:00
+++ b/include/asm-ppc/mpc52xx.h 2005-03-21 20:10:10 +01:00
@@ -10,7 +10,7 @@
* Originally written by Dale Farnsworth <dfarnsworth@mvista.com>
* for the 2.4 kernel.
*
- * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
* Copyright (C) 2003 MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public License
@@ -32,46 +32,67 @@
/* ======================================================================== */
/* Main registers/struct addresses */
/* ======================================================================== */
-/* Theses are PHYSICAL addresses ! */
-/* TODO : There should be no static mapping, but it's not yet the case, so */
-/* we require a 1:1 mapping */
+/* MBAR position */
#define MPC52xx_MBAR 0xf0000000 /* Phys address */
-#define MPC52xx_MBAR_SIZE 0x00010000
#define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */
+#define MPC52xx_MBAR_SIZE 0x00010000
+
+#define MPC52xx_PA(x) ((phys_addr_t)(MPC52xx_MBAR + (x)))
+#define MPC52xx_VA(x) ((void __iomem *)(MPC52xx_MBAR_VIRT + (x)))
-#define MPC52xx_MMAP_CTL (MPC52xx_MBAR + 0x0000)
-#define MPC52xx_SDRAM (MPC52xx_MBAR + 0x0100)
-#define MPC52xx_CDM (MPC52xx_MBAR + 0x0200)
-#define MPC52xx_SFTRST (MPC52xx_MBAR + 0x0220)
-#define MPC52xx_SFTRST_BIT 0x01000000
-#define MPC52xx_INTR (MPC52xx_MBAR + 0x0500)
-#define MPC52xx_GPTx(x) (MPC52xx_MBAR + 0x0600 + ((x)<<4))
-#define MPC52xx_RTC (MPC52xx_MBAR + 0x0800)
-#define MPC52xx_MSCAN1 (MPC52xx_MBAR + 0x0900)
-#define MPC52xx_MSCAN2 (MPC52xx_MBAR + 0x0980)
-#define MPC52xx_GPIO (MPC52xx_MBAR + 0x0b00)
-#define MPC52xx_GPIO_WKUP (MPC52xx_MBAR + 0x0c00)
-#define MPC52xx_PCI (MPC52xx_MBAR + 0x0d00)
-#define MPC52xx_USB_OHCI (MPC52xx_MBAR + 0x1000)
-#define MPC52xx_SDMA (MPC52xx_MBAR + 0x1200)
-#define MPC52xx_XLB (MPC52xx_MBAR + 0x1f00)
-#define MPC52xx_PSCx(x) (MPC52xx_MBAR + 0x2000 + ((x)<<9))
-#define MPC52xx_PSC1 (MPC52xx_MBAR + 0x2000)
-#define MPC52xx_PSC2 (MPC52xx_MBAR + 0x2200)
-#define MPC52xx_PSC3 (MPC52xx_MBAR + 0x2400)
-#define MPC52xx_PSC4 (MPC52xx_MBAR + 0x2600)
-#define MPC52xx_PSC5 (MPC52xx_MBAR + 0x2800)
-#define MPC52xx_PSC6 (MPC52xx_MBAR + 0x2C00)
-#define MPC52xx_FEC (MPC52xx_MBAR + 0x3000)
-#define MPC52xx_ATA (MPC52xx_MBAR + 0x3a00)
-#define MPC52xx_I2C1 (MPC52xx_MBAR + 0x3d00)
-#define MPC52xx_I2C_MICR (MPC52xx_MBAR + 0x3d20)
-#define MPC52xx_I2C2 (MPC52xx_MBAR + 0x3d40)
+/* Registers zone offset/size */
+#define MPC52xx_MMAP_CTL_OFFSET 0x0000
+#define MPC52xx_MMAP_CTL_SIZE 0x068
+#define MPC52xx_SDRAM_OFFSET 0x0100
+#define MPC52xx_SDRAM_SIZE 0x010
+#define MPC52xx_CDM_OFFSET 0x0200
+#define MPC52xx_CDM_SIZE 0x038
+#define MPC52xx_INTR_OFFSET 0x0500
+#define MPC52xx_INTR_SIZE 0x04c
+#define MPC52xx_GPTx_OFFSET(x) (0x0600 + ((x)<<4))
+#define MPC52xx_GPT_SIZE 0x010
+#define MPC52xx_RTC_OFFSET 0x0800
+#define MPC52xx_RTC_SIZE 0x024
+#define MPC52xx_MSCAN1_OFFSET 0x0900
+#define MPC52xx_MSCAN2_OFFSET 0x0980
+#define MPC52xx_MSCAN_SIZE 0x080
+#define MPC52xx_GPIO_OFFSET 0x0b00
+#define MPC52xx_GPIO_SIZE 0x040
+#define MPC52xx_GPIO_WKUP_OFFSET 0x0c00
+#define MPC52xx_GPIO_WKUP_SIZE 0x028
+#define MPC52xx_PCI_OFFSET 0x0d00
+#define MPC52xx_PCI_SIZE 0x100
+#define MPC52xx_SPI_OFFSET 0x0f00
+#define MPC52xx_SPI_SIZE 0x020
+#define MPC52xx_USB_OFFSET 0x1000
+#define MPC52xx_USB_SIZE 0x0a0
+#define MPC52xx_SDMA_OFFSET 0x1200
+#define MPC52xx_SDMA_SIZE 0x100
+#define MPC52xx_BDLC_OFFSET 0x1300
+#define MPC52xx_BDLC_SIZE 0x010
+#define MPC52xx_XLB_OFFSET 0x1f00
+#define MPC52xx_XLB_SIZE 0x100
+#define MPC52xx_PSC1_OFFSET 0x2000
+#define MPC52xx_PSC2_OFFSET 0x2200
+#define MPC52xx_PSC3_OFFSET 0x2400
+#define MPC52xx_PSC4_OFFSET 0x2600
+#define MPC52xx_PSC5_OFFSET 0x2800
+#define MPC52xx_PSC6_OFFSET 0x2c00
+#define MPC52xx_PSCx_OFFSET(x) (((x)!=6)?(0x1e00+((x)<<9)):0x2c00)
+#define MPC52xx_PSC_SIZE 0x0a0
+#define MPC52xx_FEC_OFFSET 0x3000
+#define MPC52xx_FEC_SIZE 0x400
+#define MPC52xx_ATA_OFFSET 0x3a00
+#define MPC52xx_ATA_SIZE 0x080
+#define MPC52xx_I2C1_OFFSET 0x3d00
+#define MPC52xx_I2C_MICR 0x3d20
+#define MPC52xx_I2C2_OFFSET 0x3d40
+#define MPC52xx_I2C_SIZE 0x020
/* SRAM used for SDMA */
-#define MPC52xx_SRAM (MPC52xx_MBAR + 0x8000)
-#define MPC52xx_SRAM_SIZE (16*1024)
+#define MPC52xx_SRAM_OFFSET 0x8000
+#define MPC52xx_SRAM_SIZE 0x4000
/* ======================================================================== */
@@ -118,11 +139,12 @@
#define MPC52xx_SPI_SPIF_IRQ (MPC52xx_PERP_IRQ_BASE + 14)
#define MPC52xx_I2C1_IRQ (MPC52xx_PERP_IRQ_BASE + 15)
#define MPC52xx_I2C2_IRQ (MPC52xx_PERP_IRQ_BASE + 16)
-#define MPC52xx_CAN1_IRQ (MPC52xx_PERP_IRQ_BASE + 17)
-#define MPC52xx_CAN2_IRQ (MPC52xx_PERP_IRQ_BASE + 18)
+#define MPC52xx_MSCAN1_IRQ (MPC52xx_PERP_IRQ_BASE + 17)
+#define MPC52xx_MSCAN2_IRQ (MPC52xx_PERP_IRQ_BASE + 18)
#define MPC52xx_IR_RX_IRQ (MPC52xx_PERP_IRQ_BASE + 19)
#define MPC52xx_IR_TX_IRQ (MPC52xx_PERP_IRQ_BASE + 20)
#define MPC52xx_XLB_ARB_IRQ (MPC52xx_PERP_IRQ_BASE + 21)
+#define MPC52xx_BDLC_IRQ (MPC52xx_PERP_IRQ_BASE + 22)
@@ -162,7 +184,7 @@
u32 cs6_start; /* MMAP_CTRL + 0x58 */
u32 cs6_stop; /* MMAP_CTRL + 0x5c */
u32 cs7_start; /* MMAP_CTRL + 0x60 */
- u32 cs7_stop; /* MMAP_CTRL + 0x60 */
+ u32 cs7_stop; /* MMAP_CTRL + 0x64 */
};
/* SDRAM control */
^ permalink raw reply
* [PATCH 4/6] ppc32: Add platform bus / ppc_sys model to Freescale MPC52xx
From: Sylvain Munaut @ 2005-03-21 23:08 UTC (permalink / raw)
To: ML linuxppc-embedded
In-Reply-To: <0.20050322_000905.tnt@patchsend.246tNt.com>
ppc32: Add platform bus / ppc_sys model to Freescale MPC52xx
This patch makes all platform based around the Freescale MPC52xx use
the platform bus and more precisly the ppc_sys model put in
place by Kumar Gala.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
diff -Nru a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
--- a/arch/ppc/platforms/lite5200.c 2005-03-21 20:10:34 +01:00
+++ b/arch/ppc/platforms/lite5200.c 2005-03-21 20:10:34 +01:00
@@ -34,6 +34,7 @@
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/mpc52xx.h>
+#include <asm/ppc_sys.h>
#include <syslib/mpc52xx_pci.h>
@@ -49,6 +50,17 @@
/* Platform specific code */
/* ======================================================================== */
+/* Supported PSC function in "preference" order */
+struct mpc52xx_psc_func mpc52xx_psc_functions[] = {
+ { .id = 0,
+ .func = "uart",
+ },
+ { .id = -1, /* End entry */
+ .func = NULL,
+ }
+ };
+
+
static int
lite5200_show_cpuinfo(struct seq_file *m)
{
@@ -147,6 +159,9 @@
strcpy(cmd_line, (char *)(r6+KERNELBASE));
}
}
+
+ /* PPC Sys identification */
+ identify_ppc_sys_by_id(mfspr(SPRN_SVR));
/* BAT setup */
mpc52xx_set_bat();
diff -Nru a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
--- a/arch/ppc/syslib/Makefile 2005-03-21 20:10:34 +01:00
+++ b/arch/ppc/syslib/Makefile 2005-03-21 20:10:34 +01:00
@@ -106,7 +106,8 @@
obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
endif
obj-$(CONFIG_MPC8555_CDS) += todc_time.o
-obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o
+obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \
+ mpc52xx_sys.o mpc52xx_devices.o ppc_sys.o
ifeq ($(CONFIG_PPC_MPC52xx),y)
obj-$(CONFIG_PCI) += mpc52xx_pci.o
endif
diff -Nru a/arch/ppc/syslib/mpc52xx_devices.c b/arch/ppc/syslib/mpc52xx_devices.c
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/mpc52xx_devices.c 2005-03-21 20:10:34 +01:00
@@ -0,0 +1,333 @@
+/*
+ * arch/ppc/syslib/mpc52xx_devices.c
+ *
+ * Freescale MPC52xx device descriptions
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Copyright (C) 2005 Sylvain Munaut <tnt@246tNt.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/fsl_devices.h>
+#include <linux/resource.h>
+#include <asm/mpc52xx.h>
+#include <asm/ppc_sys.h>
+
+
+static u64 mpc52xx_dma_mask = 0xffffffffULL;
+
+static struct fsl_i2c_platform_data mpc52xx_fsl_i2c_pdata = {
+ .device_flags = FSL_I2C_DEV_CLOCK_5200,
+};
+
+
+/* We use relative offsets for IORESOURCE_MEM to be independent from the
+ * MBAR location at compile time
+ */
+
+/* TODO Add the BestComm initiator channel to the device definitions,
+ possibly using IORESOURCE_DMA. But that's when BestComm is ready ... */
+
+struct platform_device ppc_sys_platform_devices[] = {
+ [MPC52xx_MSCAN1] = {
+ .name = "mpc52xx-mscan",
+ .id = 0,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_MSCAN1_OFFSET,
+ .end = MPC52xx_MSCAN1_OFFSET +
+ MPC52xx_MSCAN_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_MSCAN1_IRQ,
+ .end = MPC52xx_MSCAN1_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_MSCAN2] = {
+ .name = "mpc52xx-mscan",
+ .id = 1,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_MSCAN2_OFFSET,
+ .end = MPC52xx_MSCAN2_OFFSET +
+ MPC52xx_MSCAN_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_MSCAN2_IRQ,
+ .end = MPC52xx_MSCAN2_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_SPI] = {
+ .name = "mpc52xx-spi",
+ .id = -1,
+ .num_resources = 3,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_SPI_OFFSET,
+ .end = MPC52xx_SPI_OFFSET +
+ MPC52xx_SPI_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "modf",
+ .start = MPC52xx_SPI_MODF_IRQ,
+ .end = MPC52xx_SPI_MODF_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "spif",
+ .start = MPC52xx_SPI_SPIF_IRQ,
+ .end = MPC52xx_SPI_SPIF_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_USB] = {
+ .name = "ppc-soc-ohci",
+ .id = -1,
+ .num_resources = 2,
+ .dev.dma_mask = &mpc52xx_dma_mask,
+ .dev.coherent_dma_mask = 0xffffffffULL,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_USB_OFFSET,
+ .end = MPC52xx_USB_OFFSET +
+ MPC52xx_USB_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_USB_IRQ,
+ .end = MPC52xx_USB_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_BDLC] = {
+ .name = "mpc52xx-bdlc",
+ .id = -1,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_BDLC_OFFSET,
+ .end = MPC52xx_BDLC_OFFSET +
+ MPC52xx_BDLC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_BDLC_IRQ,
+ .end = MPC52xx_BDLC_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_PSC1] = {
+ .name = "mpc52xx-psc",
+ .id = 0,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_PSC1_OFFSET,
+ .end = MPC52xx_PSC1_OFFSET +
+ MPC52xx_PSC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_PSC1_IRQ,
+ .end = MPC52xx_PSC1_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_PSC2] = {
+ .name = "mpc52xx-psc",
+ .id = 1,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_PSC2_OFFSET,
+ .end = MPC52xx_PSC2_OFFSET +
+ MPC52xx_PSC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_PSC2_IRQ,
+ .end = MPC52xx_PSC2_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_PSC3] = {
+ .name = "mpc52xx-psc",
+ .id = 2,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_PSC3_OFFSET,
+ .end = MPC52xx_PSC3_OFFSET +
+ MPC52xx_PSC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_PSC3_IRQ,
+ .end = MPC52xx_PSC3_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_PSC4] = {
+ .name = "mpc52xx-psc",
+ .id = 3,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_PSC4_OFFSET,
+ .end = MPC52xx_PSC4_OFFSET +
+ MPC52xx_PSC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_PSC4_IRQ,
+ .end = MPC52xx_PSC4_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_PSC5] = {
+ .name = "mpc52xx-psc",
+ .id = 4,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_PSC5_OFFSET,
+ .end = MPC52xx_PSC5_OFFSET +
+ MPC52xx_PSC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_PSC5_IRQ,
+ .end = MPC52xx_PSC5_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_PSC6] = {
+ .name = "mpc52xx-psc",
+ .id = 5,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_PSC6_OFFSET,
+ .end = MPC52xx_PSC6_OFFSET +
+ MPC52xx_PSC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_PSC6_IRQ,
+ .end = MPC52xx_PSC6_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_FEC] = {
+ .name = "mpc52xx-fec",
+ .id = -1,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_FEC_OFFSET,
+ .end = MPC52xx_FEC_OFFSET +
+ MPC52xx_FEC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_FEC_IRQ,
+ .end = MPC52xx_FEC_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_ATA] = {
+ .name = "mpc52xx-ata",
+ .id = -1,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_ATA_OFFSET,
+ .end = MPC52xx_ATA_OFFSET +
+ MPC52xx_ATA_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_ATA_IRQ,
+ .end = MPC52xx_ATA_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_I2C1] = {
+ .name = "fsl-i2c",
+ .id = 0,
+ .dev.platform_data = &mpc52xx_fsl_i2c_pdata,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_I2C1_OFFSET,
+ .end = MPC52xx_I2C1_OFFSET +
+ MPC52xx_I2C_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_I2C1_IRQ,
+ .end = MPC52xx_I2C1_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC52xx_I2C2] = {
+ .name = "fsl-i2c",
+ .id = 1,
+ .dev.platform_data = &mpc52xx_fsl_i2c_pdata,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .start = MPC52xx_I2C2_OFFSET,
+ .end = MPC52xx_I2C2_OFFSET +
+ MPC52xx_I2C_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MPC52xx_I2C2_IRQ,
+ .end = MPC52xx_I2C2_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+};
+
+
+static int __init mach_mpc52xx_fixup(struct platform_device *pdev)
+{
+ ppc_sys_fixup_mem_resource(pdev, MPC52xx_MBAR);
+ return 0;
+}
+
+static int __init mach_mpc52xx_init(void)
+{
+ ppc_sys_device_fixup = mach_mpc52xx_fixup;
+ return 0;
+}
+
+postcore_initcall(mach_mpc52xx_init);
diff -Nru a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c
--- a/arch/ppc/syslib/mpc52xx_setup.c 2005-03-21 20:10:34 +01:00
+++ b/arch/ppc/syslib/mpc52xx_setup.c 2005-03-21 20:10:34 +01:00
@@ -215,3 +215,16 @@
tb_ticks_per_jiffy = xlbfreq / HZ / divisor;
tb_to_us = mulhwu_scale_factor(xlbfreq / divisor, 1000000);
}
+
+int mpc52xx_match_psc_function(int psc_idx, const char *func)
+{
+ struct mpc52xx_psc_func *cf = mpc52xx_psc_functions;
+
+ while ((cf->id != -1) && (cf->func != NULL)) {
+ if ((cf->id == psc_idx) && !strcmp(cf->func,func))
+ return 1;
+ cf++;
+ }
+
+ return 0;
+}
diff -Nru a/arch/ppc/syslib/mpc52xx_sys.c b/arch/ppc/syslib/mpc52xx_sys.c
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/mpc52xx_sys.c 2005-03-21 20:10:34 +01:00
@@ -0,0 +1,38 @@
+/*
+ * arch/ppc/syslib/mpc52xx_sys.c
+ *
+ * Freescale MPC52xx system descriptions
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Copyright (C) 2005 Sylvain Munaut <tnt@246tNt.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <asm/ppc_sys.h>
+
+struct ppc_sys_spec *cur_ppc_sys_spec;
+struct ppc_sys_spec ppc_sys_specs[] = {
+ {
+ .ppc_sys_name = "5200",
+ .mask = 0xffff0000,
+ .value = 0x80110000,
+ .num_devices = 15,
+ .device_list = (enum ppc_sys_devices[])
+ {
+ MPC52xx_MSCAN1, MPC52xx_MSCAN2, MPC52xx_SPI,
+ MPC52xx_USB, MPC52xx_BDLC, MPC52xx_PSC1, MPC52xx_PSC2,
+ MPC52xx_PSC3, MPC52xx_PSC4, MPC52xx_PSC5, MPC52xx_PSC6,
+ MPC52xx_FEC, MPC52xx_ATA, MPC52xx_I2C1, MPC52xx_I2C2,
+ },
+ },
+ { /* default match */
+ .ppc_sys_name = "",
+ .mask = 0x00000000,
+ .value = 0x00000000,
+ },
+};
diff -Nru a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
--- a/include/asm-ppc/mpc52xx.h 2005-03-21 20:10:34 +01:00
+++ b/include/asm-ppc/mpc52xx.h 2005-03-21 20:10:34 +01:00
@@ -30,6 +30,29 @@
/* ======================================================================== */
+/* PPC Sys devices definition */
+/* ======================================================================== */
+
+enum ppc_sys_devices {
+ MPC52xx_MSCAN1,
+ MPC52xx_MSCAN2,
+ MPC52xx_SPI,
+ MPC52xx_USB,
+ MPC52xx_BDLC,
+ MPC52xx_PSC1,
+ MPC52xx_PSC2,
+ MPC52xx_PSC3,
+ MPC52xx_PSC4,
+ MPC52xx_PSC5,
+ MPC52xx_PSC6,
+ MPC52xx_FEC,
+ MPC52xx_ATA,
+ MPC52xx_I2C1,
+ MPC52xx_I2C2,
+};
+
+
+/* ======================================================================== */
/* Main registers/struct addresses */
/* ======================================================================== */
@@ -414,6 +437,17 @@
extern void mpc52xx_calibrate_decr(void);
extern void mpc52xx_find_bridges(void);
+
+
+ /* Matching of PSC function */
+struct mpc52xx_psc_func {
+ int id;
+ char *func;
+};
+
+extern int mpc52xx_match_psc_function(int psc_idx, const char *func);
+extern struct mpc52xx_psc_func mpc52xx_psc_functions[];
+ /* This array is to be defined in platform file */
#endif /* __ASSEMBLY__ */
diff -Nru a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
--- a/include/asm-ppc/ppc_sys.h 2005-03-21 20:10:34 +01:00
+++ b/include/asm-ppc/ppc_sys.h 2005-03-21 20:10:34 +01:00
@@ -25,6 +25,8 @@
#include <asm/mpc83xx.h>
#elif defined(CONFIG_85xx)
#include <asm/mpc85xx.h>
+#elif defined(CONFIG_PPC_MPC52xx)
+#include <asm/mpc52xx.h>
#else
#error "need definition of ppc_sys_devices"
#endif
^ permalink raw reply
* [PATCH 5/6] serial: Update mpc52xx_uart.c to use platform bus
From: Sylvain Munaut @ 2005-03-21 23:09 UTC (permalink / raw)
To: ML linuxppc-embedded
In-Reply-To: <0.20050322_000905.tnt@patchsend.246tNt.com>
serial: Update mpc52xx_uart.c to use platform bus
All Freescale MPC52xx related code now use new constants and
the platform bus for it's driver. This patch makes this driver
make use of that.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
diff -Nru a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
--- a/drivers/serial/mpc52xx_uart.c 2005-03-21 20:11:00 +01:00
+++ b/drivers/serial/mpc52xx_uart.c 2005-03-21 20:11:00 +01:00
@@ -18,7 +18,7 @@
* Some of the code has been inspired/copied from the 2.4 code written
* by Dale Farnsworth <dfarnsworth@mvista.com>.
*
- * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
* Copyright (C) 2003 MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public License
@@ -26,33 +26,26 @@
* kind, whether express or implied.
*/
-/* OCP Usage :
+/* Platform device Usage :
*
- * This drivers uses the OCP model. To load the serial driver for one of the
- * PSCs, just add this to the core_ocp table :
+ * Since PSCs can have multiple function, the correct driver for each one
+ * is selected by calling mpc52xx_match_psc_function(...). The function
+ * handled by this driver is "uart".
*
- * {
- * .vendor = OCP_VENDOR_FREESCALE,
- * .function = OCP_FUNC_PSC_UART,
- * .index = 0,
- * .paddr = MPC52xx_PSC1,
- * .irq = MPC52xx_PSC1_IRQ,
- * .pm = OCP_CPM_NA,
- * },
- *
- * This is for PSC1, replace the paddr and irq according to the PSC you want to
- * use. The driver all necessary registers to place the PSC in uart mode without
+ * The driver init all necessary registers to place the PSC in uart mode without
* DCD. However, the pin multiplexing aren't changed and should be set either
* by the bootloader or in the platform init code.
- * The index field must be equal to the PSC index ( e.g. 0 for PSC1, 1 for PSC2,
+ *
+ * The idx field must be equal to the PSC index ( e.g. 0 for PSC1, 1 for PSC2,
* and so on). So the PSC1 is mapped to /dev/ttyS0, PSC2 to /dev/ttyS1 and so
* on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly for
* the console code : without this 1:1 mapping, at early boot time, when we are
* parsing the kernel args console=ttyS?, we wouldn't know wich PSC it will be
- * mapped to because OCP stuff is not yet initialized.
+ * mapped to.
*/
#include <linux/config.h>
+#include <linux/device.h>
#include <linux/module.h>
#include <linux/tty.h>
#include <linux/serial.h>
@@ -61,7 +54,6 @@
#include <asm/delay.h>
#include <asm/io.h>
-#include <asm/ocp.h>
#include <asm/mpc52xx.h>
#include <asm/mpc52xx_psc.h>
@@ -191,6 +183,13 @@
mpc52xx_uart_startup(struct uart_port *port)
{
struct mpc52xx_psc __iomem *psc = PSC(port);
+ int ret;
+
+ /* Request IRQ */
+ ret = request_irq(port->irq, mpc52xx_uart_int,
+ SA_INTERRUPT | SA_SAMPLE_RANDOM, "mpc52xx_psc_uart", port);
+ if (ret)
+ return ret;
/* Reset/activate the port, clear and enable interrupts */
out_8(&psc->command,MPC52xx_PSC_RST_RX);
@@ -225,6 +224,9 @@
port->read_status_mask = 0;
out_be16(&psc->mpc52xx_psc_imr,port->read_status_mask);
+
+ /* Release interrupt */
+ free_irq(port->irq, port);
}
static void
@@ -326,15 +328,21 @@
iounmap(port->membase);
port->membase = NULL;
}
+
+ release_mem_region(port->mapbase, MPC52xx_PSC_SIZE);
}
static int
mpc52xx_uart_request_port(struct uart_port *port)
{
if (port->flags & UPF_IOREMAP) /* Need to remap ? */
- port->membase = ioremap(port->mapbase, sizeof(struct mpc52xx_psc));
-
- return port->membase != NULL ? 0 : -EBUSY;
+ port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE);
+
+ if (!port->membase)
+ return -EINVAL;
+
+ return request_mem_region(port->mapbase, MPC52xx_PSC_SIZE,
+ "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
}
static void
@@ -354,7 +362,7 @@
if ( (ser->irq != port->irq) ||
(ser->io_type != SERIAL_IO_MEM) ||
(ser->baud_base != port->uartclk) ||
- // FIXME Should check addresses/irq as well ?
+ (ser->iomem_base != (void*)port->mapbase) ||
(ser->hub6 != 0 ) )
return -EINVAL;
@@ -630,7 +638,7 @@
{
struct uart_port *port = &mpc52xx_uart_ports[co->index];
- int baud = 9600;
+ int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
int bits = 8;
int parity = 'n';
int flow = 'n';
@@ -643,14 +651,12 @@
spin_lock_init(&port->lock);
port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */
port->ops = &mpc52xx_uart_ops;
- port->mapbase = MPC52xx_PSCx(co->index);
+ port->mapbase = MPC52xx_PA(MPC52xx_PSCx_OFFSET(co->index+1));
- /* We ioremap ourself */
- port->membase = ioremap(port->mapbase, sizeof(struct mpc52xx_psc));
- if (port->membase == NULL) {
- release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
- return -EBUSY;
- }
+ /* We ioremap ourself */
+ port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE);
+ if (port->membase == NULL)
+ return -EINVAL;
/* Setup the port parameters accoding to options */
if (options)
@@ -707,26 +713,32 @@
/* ======================================================================== */
-/* OCP Driver */
+/* Platform Driver */
/* ======================================================================== */
static int __devinit
-mpc52xx_uart_probe(struct ocp_device *ocp)
+mpc52xx_uart_probe(struct device *dev)
{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct resource *res = pdev->resource;
+
struct uart_port *port = NULL;
- int idx, ret;
+ int i, idx, ret;
- /* Get the corresponding port struct */
- idx = ocp->def->index;
+ /* Check validity & presence */
+ idx = pdev->id;
if (idx < 0 || idx >= MPC52xx_PSC_MAXNUM)
return -EINVAL;
-
- port = &mpc52xx_uart_ports[idx];
+
+ if (!mpc52xx_match_psc_function(idx,"uart"))
+ return -ENODEV;
/* Init the port structure */
+ port = &mpc52xx_uart_ports[idx];
+
+ memset(port, 0x00, sizeof(struct uart_port));
+
spin_lock_init(&port->lock);
- port->mapbase = ocp->def->paddr;
- port->irq = ocp->def->irq;
port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */
port->fifosize = 255; /* Should be 512 ! But it can't be */
/* stored in a unsigned char */
@@ -735,95 +747,65 @@
( uart_console(port) ? 0 : UPF_IOREMAP );
port->line = idx;
port->ops = &mpc52xx_uart_ops;
- port->read_status_mask = 0;
-
- /* Requests the mem & irqs */
- /* Unlike other serial drivers, we reserve the resources here, so we
- * can detect early if multiple drivers uses the same PSC. Special
- * care must be taken with the console PSC
- */
- ret = request_irq(
- port->irq, mpc52xx_uart_int,
- SA_INTERRUPT | SA_SAMPLE_RANDOM, "mpc52xx_psc_uart", port);
- if (ret)
- goto error;
- ret = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
- "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
- if (ret)
- goto free_irq;
+ /* Search for IRQ and mapbase */
+ for (i=0 ; i<pdev->num_resources ; i++, res++) {
+ if (res->flags & IORESOURCE_MEM)
+ port->mapbase = res->start;
+ else if (res->flags & IORESOURCE_IRQ)
+ port->irq = res->start;
+ }
+ if (!port->irq || !port->mapbase)
+ return -EINVAL;
/* Add the port to the uart sub-system */
ret = uart_add_one_port(&mpc52xx_uart_driver, port);
- if (ret)
- goto release_mem;
-
- ocp_set_drvdata(ocp, (void*)port);
-
- return 0;
-
-
-free_irq:
- free_irq(port->irq, mpc52xx_uart_int);
-
-release_mem:
- release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
-
-error:
- if (uart_console(port))
- printk( "mpc52xx_uart.c: Error during resource alloction for "
- "the console port !!! Check that the console PSC is "
- "not used by another OCP driver !!!\n" );
+ if (!ret)
+ dev_set_drvdata(dev, (void*)port);
return ret;
}
-static void
-mpc52xx_uart_remove(struct ocp_device *ocp)
+static int
+mpc52xx_uart_remove(struct device *dev)
{
- struct uart_port *port = (struct uart_port *) ocp_get_drvdata(ocp);
+ struct uart_port *port = (struct uart_port *) dev_get_drvdata(dev);
- ocp_set_drvdata(ocp, NULL);
+ dev_set_drvdata(dev, NULL);
- if (port) {
+ if (port)
uart_remove_one_port(&mpc52xx_uart_driver, port);
- release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
- free_irq(port->irq, mpc52xx_uart_int);
- }
+
+ return 0;
}
#ifdef CONFIG_PM
static int
-mpc52xx_uart_suspend(struct ocp_device *ocp, u32 state)
+mpc52xx_uart_suspend(struct device *dev, u32 state, u32 level)
{
- struct uart_port *port = (struct uart_port *) ocp_get_drvdata(ocp);
+ struct uart_port *port = (struct uart_port *) dev_get_drvdata(dev);
- uart_suspend_port(&mpc52xx_uart_driver, port);
+ if (sport && level == SUSPEND_DISABLE)
+ uart_suspend_port(&mpc52xx_uart_driver, port);
return 0;
}
static int
-mpc52xx_uart_resume(struct ocp_device *ocp)
+mpc52xx_uart_resume(struct device *dev, u32 level)
{
- struct uart_port *port = (struct uart_port *) ocp_get_drvdata(ocp);
+ struct uart_port *port = (struct uart_port *) dev_get_drvdata(dev);
- uart_resume_port(&mpc52xx_uart_driver, port);
+ if (port && level == RESUME_ENABLE)
+ uart_resume_port(&mpc52xx_uart_driver, port);
return 0;
}
#endif
-static struct ocp_device_id mpc52xx_uart_ids[] __devinitdata = {
- { .vendor = OCP_VENDOR_FREESCALE, .function = OCP_FUNC_PSC_UART },
- { .vendor = OCP_VENDOR_INVALID /* Terminating entry */ }
-};
-
-MODULE_DEVICE_TABLE(ocp, mpc52xx_uart_ids);
-
-static struct ocp_driver mpc52xx_uart_ocp_driver = {
- .name = "mpc52xx_psc_uart",
- .id_table = mpc52xx_uart_ids,
+static struct device_driver mpc52xx_uart_platform_driver = {
+ .name = "mpc52xx-psc",
+ .bus = &platform_bus_type,
.probe = mpc52xx_uart_probe,
.remove = mpc52xx_uart_remove,
#ifdef CONFIG_PM
@@ -845,10 +827,11 @@
printk(KERN_INFO "Serial: MPC52xx PSC driver\n");
ret = uart_register_driver(&mpc52xx_uart_driver);
- if (ret)
- return ret;
-
- ret = ocp_register_driver(&mpc52xx_uart_ocp_driver);
+ if (ret == 0) {
+ ret = driver_register(&mpc52xx_uart_platform_driver);
+ if (ret)
+ uart_unregister_driver(&mpc52xx_uart_driver);
+ }
return ret;
}
@@ -856,7 +839,7 @@
static void __exit
mpc52xx_uart_exit(void)
{
- ocp_unregister_driver(&mpc52xx_uart_ocp_driver);
+ driver_unregister(&mpc52xx_uart_platform_driver);
uart_unregister_driver(&mpc52xx_uart_driver);
}
^ permalink raw reply
* [PATCH 6/6] ppc32: Adds necessary cpu init to use USB on LITE5200 Platform
From: Sylvain Munaut @ 2005-03-21 23:09 UTC (permalink / raw)
To: ML linuxppc-embedded
In-Reply-To: <0.20050322_000905.tnt@patchsend.246tNt.com>
ppc32: Adds necessary cpu init to use USB on LITE5200 Platform
To use external peripheral on MPC5200, some clocking registers
and port-muxing must be done. Since this is platform specific,
it's placed the platform support file. This particular patch
is for USB support on the LITE5200.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
diff -Nru a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
--- a/arch/ppc/platforms/lite5200.c 2005-03-21 20:11:23 +01:00
+++ b/arch/ppc/platforms/lite5200.c 2005-03-21 20:11:23 +01:00
@@ -79,21 +79,47 @@
static void __init
lite5200_setup_cpu(void)
{
+ struct mpc52xx_cdm __iomem *cdm;
+ struct mpc52xx_gpio __iomem *gpio;
struct mpc52xx_intr __iomem *intr;
struct mpc52xx_xlb __iomem *xlb;
+ u32 port_config;
u32 intr_ctrl;
/* Map zones */
+ cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE);
+ gpio = ioremap(MPC52xx_PA(MPC52xx_GPIO_OFFSET), MPC52xx_GPIO_SIZE);
xlb = ioremap(MPC52xx_PA(MPC52xx_XLB_OFFSET), MPC52xx_XLB_SIZE);
intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
- if (!xlb || !intr) {
- printk("lite5200.c: Error while mapping XLB/INTR during "
+ if (!cdm || !gpio || !xlb || !intr) {
+ printk("lite5200.c: Error while mapping CDM/GPIO/XLB/INTR during"
"lite5200_setup_cpu\n");
goto unmap_regs;
}
+ /* Use internal 48 Mhz */
+ out_8(&cdm->ext_48mhz_en, 0x00);
+ out_8(&cdm->fd_enable, 0x01);
+ if (in_be32(&cdm->rstcfg) & 0x40) /* Assumes 33Mhz clock */
+ out_be16(&cdm->fd_counters, 0x0001);
+ else
+ out_be16(&cdm->fd_counters, 0x5555);
+
+ /* Get port mux config */
+ port_config = in_be32(&gpio->port_config);
+
+ /* 48Mhz internal, pin is GPIO */
+ port_config &= ~0x00800000;
+
+ /* USB port */
+ port_config &= ~0x00007000; /* Differential mode - USB1 only */
+ port_config |= 0x00001000;
+
+ /* Commit port config */
+ out_be32(&gpio->port_config, port_config);
+
/* Configure the XLB Arbiter */
out_be32(&xlb->master_pri_enable, 0xff);
out_be32(&xlb->master_priority, 0x11111111);
@@ -111,6 +137,8 @@
/* Unmap reg zone */
unmap_regs:
+ if (cdm) iounmap(cdm);
+ if (gpio) iounmap(gpio);
if (xlb) iounmap(xlb);
if (intr) iounmap(intr);
}
@@ -171,7 +199,11 @@
isa_mem_base = 0;
/* Powersave */
- powersave_nap = 1; /* We allow this platform to NAP */
+ /* This is provided as an example on how to do it. But you
+ need to be aware that NAP disable bus snoop and that may
+ be required for some devices to work properly, like USB ... */
+ /* powersave_nap = 1; */
+
/* Setup the ppc_md struct */
ppc_md.setup_arch = lite5200_setup_arch;
^ permalink raw reply
* Re: Wakeup broken on iBook G3
From: Benjamin Herrenschmidt @ 2005-03-21 23:23 UTC (permalink / raw)
To: Andreas Schwab; +Cc: linuxppc-dev list
In-Reply-To: <je8y4g7m6h.fsf@sykes.suse.de>
On Mon, 2005-03-21 at 21:56 +0100, Andreas Schwab wrote:
> Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
>
> > Can you try playing with pmac_sleep.S and pmac_cache.S, basically
> > reverting those including the calls to set_L2CR in via-pmu.c ?
>
> That makes it even worse (it apparently crashes almost immediately after
> wakeup).
Hrm... Ok...
At this point, I don't know for sure what's up, there have been several
reports but nobody physically close to me has any of these machines for
me to test with.
Have you tried with very latest bk which contains by workarounds for
radeon erratas ? The M7 has smore bugs that might have been triggered by
the moving of code around that I did in the latest readeonfb.
Also, in pmac_cache.S, try locating that bit:
/* disp-flush L1 */
li r4,0x4000
mtctr r4
lis r4,0xfff0
1: lwzx r0,r0,r4
addi r4,r4,32
bdnz 1b
sync
isync
And turn the li r4,0x4000 into lis r4,2 and let me know if that makes
any difference... Same a little bit later, there is:
lis r4,2
mtctr r4
lis r4,0xfff0
1: lwzx r0,r0,r4
addi r4,r4,32
bdnz 1b
sync
isync
Here, try turning the lis r4,2 into lis r4,0x20
And let me know if any of these help.
Finally, what happens if you boot without any framebuffer in the kernel
(no fbdev at all, no fbcon, just no console), ssh into the box, and put
it to sleep ? Does it wake up ?
Ben.
^ permalink raw reply
* Re: Wakeup broken on iBook G3
From: Andreas Schwab @ 2005-03-22 0:42 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list
In-Reply-To: <1111447381.1236.295.camel@gaston>
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
> Have you tried with very latest bk which contains by workarounds for
> radeon erratas ? The M7 has smore bugs that might have been triggered by
> the moving of code around that I did in the latest readeonfb.
Correction: it's actually an M6.
> Also, in pmac_cache.S, try locating that bit:
>
> /* disp-flush L1 */
> li r4,0x4000
> mtctr r4
> lis r4,0xfff0
> 1: lwzx r0,r0,r4
> addi r4,r4,32
> bdnz 1b
> sync
> isync
>
> And turn the li r4,0x4000 into lis r4,2 and let me know if that makes
> any difference...
This did help.
> Same a little bit later, there is:
>
>
> lis r4,2
> mtctr r4
> lis r4,0xfff0
> 1: lwzx r0,r0,r4
> addi r4,r4,32
> bdnz 1b
> sync
> isync
>
> Here, try turning the lis r4,2 into lis r4,0x20
This didn't, got crash in __flush_dcache_icache when called from
update_mmu_cache. (I tested both changes separately.)
> Finally, what happens if you boot without any framebuffer in the kernel
> (no fbdev at all, no fbcon, just no console), ssh into the box, and put
> it to sleep ?
I have no idea how to put it into sleep in this configuration. The
pbbuttonsd says that sleep is not supported.
Andreas.
--
Andreas Schwab, SuSE Labs, schwab@suse.de
SuSE Linux Products GmbH, Maxfeldstraße 5, 90409 Nürnberg, Germany
Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
^ permalink raw reply
* Re: [PATCH 0/6] [RFC] Change MPC52xx to platform bus / ppc_sys model
From: Kumar Gala @ 2005-03-22 1:11 UTC (permalink / raw)
To: Sylvain Munaut; +Cc: ML linuxppc-embedded
In-Reply-To: <0.20050322_000905.tnt@patchsend.246tNt.com>
Sylvain,
Took a quick glance at the patches and they look good. Do you have a=20
bk tree available with all these changes in them?
I think a might have a few minor comments, but might be easier to see=20
the bk tree.
- kumar
On Mar 21, 2005, at 5:06 PM, Sylvain Munaut wrote:
> Hi all,
>
> This series of patch changes all the MPC52xx related code
> to use platform bus and ppc_sys instead of OCP. It's
> divided in several patches that represents "steps" in
> the conversion. However the intermediate states might
> not be functionnal.
>
> This is the first try, comments and suggestions are
> welcomed.
>
>
>
> =A0=A0=A0=A0=A0=A0=A0 Sylvain
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: Wakeup broken on iBook G3
From: Benjamin Herrenschmidt @ 2005-03-22 2:01 UTC (permalink / raw)
To: Andreas Schwab; +Cc: linuxppc-dev list
In-Reply-To: <je64zk5x56.fsf@sykes.suse.de>
On Tue, 2005-03-22 at 01:42 +0100, Andreas Schwab wrote:
> I have no idea how to put it into sleep in this configuration. The
> pbbuttonsd says that sleep is not supported.
You need "snooze" and do "snooze -f", but I think the L1 cache flush is
the culprit, I'll try to find a solution.
Ben.
^ permalink raw reply
* Need help.
From: Naveen Kumar Atmakuri @ 2005-03-22 5:15 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 362 bytes --]
Hi everybody,
Could any one suggest the toolchain and kernel versions that are compatible with the MPC7448 processor ( It's a motorola processor based on power PC architecture ). Is there any site from where we can download the precompiled binaries for the same processor.
With Regards& Thanks,
A.Naveen Kumar,
Design Engineer,
Mistral Software Pvt Ltd.
[-- Attachment #2: Type: text/html, Size: 885 bytes --]
^ permalink raw reply
* Re: [PATCH 0/6] [RFC] Change MPC52xx to platform bus / ppc_sys model
From: Sylvain Munaut @ 2005-03-22 7:12 UTC (permalink / raw)
To: Kumar Gala; +Cc: ML linuxppc-embedded
In-Reply-To: <556f5ce38ca914dce63ca24277af4b3e@freescale.com>
Hi Kumar,
Kumar Gala wrote:
> Took a quick glance at the patches and they look good. Do you have a bk
> tree available with all these changes in them?
>
> I think a might have a few minor comments, but might be easier to see
> the bk tree.
Sure, bk://tnt.bkbits.net/linux-2.5-mpc52xx-pending
The only difference between that tree and the patch is a few trailing
white space that are in BK but not in the patch.
Note that now, I should also add CONFIG_PPC_MPC52xx to the change of
/proc/cpuinfo. What about a CONFIG_PPC_SYS that would include ppc_sys.o
in the kernel and activate the /proc/cpuinfo chipset line ?
Sylvain
^ permalink raw reply
* Future of OCP
From: Lawrence E. Bakst @ 2005-03-22 7:04 UTC (permalink / raw)
To: ML linuxppc-embedded
In-Reply-To: <0.20050322_000905.tnt@patchsend.246tNt.com>
I apologize up front for my ignorance.
At 12:06 AM +0100 3/22/05, Sylvain Munaut wrote:
>Hi all,
>
>This series of patch changes all the MPC52xx related code
>to use platform bus and ppc_sys instead of OCP. It's
>divided in several patches that represents "steps" in
>the conversion. However the intermediate states might
>not be functionnal.
>
>This is the first try, comments and suggestions are
>welcomed.
At 9:35 AM -0600 1/18/05, Kumar Gala wrote:
>System platform_device description, discovery and management:
>
>On most embedded PPC systems we either have a core CPU and chipset
>(MPC10x, TSI10x, Marvell, etc.) or a system-on-chip device (4xx, 8xx,
>82xx, 85xx, etc.). Some of these sub-archs have been using the On Chip
>Peripheral (OCP) driver model. The functionality that OCP provide has
>been replaced by the generic driver model and platform_device. Also, some
>of these device may exist across a number of architectures (PPC, MIPS,
>ARM) such that some information that is shared between the architecture
>and driver needs to exist outside of either.
>
>The ppc_sys changes add a standard way for PowerPC systems to describe the
>devices and systems that exist in the sub-arch. Additionally, we are able
>to discover which system we are and manage which devices are actually
>registered and any platform specific fixups that may be needed.
>
>Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Q1: OK, so I gather the OCP system which until recently used to be in a separate OCP tree and was recently integrated into 2.6 is going away?
I had just started to do a 405 EP port of 2.6.11-rc4 based off of the bubinga config.
Q2: Assuming yes, to Q1, any advice on how I should proceed, continue on with an OCP port or wait for this new stuff?
Q3: How does one stay in the loop on this stuff? With only about 3 messages posted in this group and none in linuxppc-dev I am clearly in the wrong place. I feel like I missed the conversation. Where was it?
Best,
leb
^ permalink raw reply
* Re: Future of OCP
From: Eugene Surovegin @ 2005-03-22 7:48 UTC (permalink / raw)
To: Lawrence E. Bakst; +Cc: ML linuxppc-embedded
In-Reply-To: <p0621020ebe656d463a67@mail.iridescent.org>
On Mon, Mar 21, 2005 at 11:04:44PM -0800, Lawrence E. Bakst wrote:
> Q1: OK, so I gather the OCP system which until recently used to be
> in a separate OCP tree and was recently integrated into 2.6 is going
> away?
There is a trend use platform device instead of OCP. There are no
conceptual differences though, just a more convenient way from cross
platform POV - OCP is PPC specific, platform device - generic
solution.
IMHO there is little gain from converting 4xx from OCP platform device
(except being just like other PPC subarchs :). That's the main reason
it hasn't been done yet. Matt seems to be busy these days, I don't see
a point, frankly, so we just waiting for a patch :).
> I had just started to do a 405 EP port of 2.6.11-rc4 based off of
> the bubinga config.
>
> Q2: Assuming yes, to Q1, any advice on how I should proceed,
> continue on with an OCP port or wait for this new stuff?
Well, I wouldn't worry much. These changes will affect mostly device
drivers and some platform stuff. Board code (which I assume you are
working on) won't be changed significantly if any. As I said, platform
device stuff is conceptually similar to OCP, so changes will be mostly
cosmetic.
> Q3: How does one stay in the loop on this stuff? With only about 3
> messages posted in this group and none in linuxppc-dev I am clearly
> in the wrong place. I feel like I missed the conversation. Where was
> it?
Most discussions happen on IRC (for more info see
http://www.penguinppc.org). Some people think it's a kind of "elitist
circle" which requires some special invitation :), which is not true,
obviously.
--
Eugene
^ permalink raw reply
* Help Regarding DEVFS
From: Vijesh VH @ 2005-03-22 8:21 UTC (permalink / raw)
To: linuxppc-embedded
Hi,
I faced a problem when i was doing Netboot on linux 2.4.29 on IBM
PowerPC 4xx Processor. I am using filesystem develped for 2.4.18. Can
anyone help me to sort out the problem.
*************************************************************************************
IP-Config: Got BOOTP answer from 192.168.48.143, my address is 192.168.48.3
eth0:smc_set_multicast_list
LAN91C111:smc_setmulticast
IP-Config: Complete:
device=eth0, addr=192.168.48.3, mask=255.255.255.0, gw=255.255.255.255,
host=192.168.48.3, domain=mylinux.org, nis-domain=macindia.org,
bootserver=192.168.48.143, rootserver=192.168.48.143, rootpath=/stb
arp_tables: (C) 2002 David S. Miller
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
Looking up port of RPC 100003/2 on 192.168.48.143
Looking up port of RPC 100005/1 on 192.168.48.143
nfs: server 192.168.48.143 not responding, still trying
nfs: server 192.168.48.143 OK
VFS: Mounted root (nfs filesystem).
Freeing unused kernel memory: 80k init
Warning: unable to open an initial console.
Kernel panic: No init found. Try passing init= option to kernel.
<0>Rebooting in 180 seconds..
***********************************************************************************
--
Thanks and Regards,
Vijesh V H
^ permalink raw reply
* Re: Linux 2.6.x on 8xx status
From: Marcelo Tosatti @ 2005-03-22 13:04 UTC (permalink / raw)
To: Guillaume Autran; +Cc: Smith, Craig, paulus, linux-ppc-embedded
In-Reply-To: <423F4071.1000001@mrv.com>
On Mon, Mar 21, 2005 at 04:45:21PM -0500, Guillaume Autran wrote:
> Hi,
>
> Was there any progress made about this issue or is it still pending ?
That one is still pending.
There are other issues in 8xx which are probably related to it, as follows.
> I'm running 2.6.11 and still see the problem...
I'm currently trying to understand 8xx cache structure and VM semantics to
find out why I'm seeing the following numbers.
Test application is: copy 16M from /dev/zero to file-on-RAMDISK, using:
# dd if=/dev/zero of=file bs=4k count=3840
v2.6:
I-TLB userspace misses: 141264
I-TLB kernel misses: 117455
D-TLB userspace misses: 217590
D-TLB kernel misses: 202677
tlbie: 260
I-TLB userspace misses: 143455
I-TLB kernel misses: 119189
D-TLB userspace misses: 212828
D-TLB kernel misses: 197883
tlbie: 260
I-TLB userspace misses: 142248
I-TLB kernel misses: 118195
D-TLB userspace misses: 217576
D-TLB kernel misses: 202663
tlbie: 260
v2.4:
I-TLB userspace misses: 266
I-TLB kernel misses: 5170
D-TLB userspace misses: 3661
D-TLB kernel misses: 177004
tlbie: 162599
I-TLB userspace misses: 266
I-TLB kernel misses: 3183
D-TLB userspace misses: 2024
D-TLB kernel misses: 180178
tlbie: 165675
I'm quite puzzled. Why v2.6 calls the "tlbie" instruction 100-or-so
less times than v2.4 ?
Paul, Ben?
>
> Regards,
> Guillaume.
>
>
>
> Marcelo Tosatti wrote:
>
> >On Thu, Feb 10, 2005 at 03:06:58PM -0200, Marcelo Tosatti wrote:
> >
> >
> >>On Thu, Feb 10, 2005 at 02:26:52PM -0500, Dan Malek wrote:
> >>
> >>
> >>>On Feb 10, 2005, at 10:04 AM, Marcelo Tosatti wrote:
> >>>
> >>>
> >>>
> >>>>Does anyone have a clue of what is/can be wrong with the TLB entry for
> >>>>the
> >>>>address being flushed at __flush_dcache_icache()?
> >>>>
> >>>>
> >>>Not sure. The problem is that the __flush_dcache_icache is passed a
> >>>user space virtual address that doesn't look like it is mapped for
> >>>writing
> >>>or something. I don't know, as an ooops isn't sufficient to debug the
> >>>problem.
> >>>You have to catch it here and track down the current state of the TLB
> >>>and
> >>>the page tables. Of course, when I do this everything looks OK,
> >>>
> >>>
> >>How do you do track down the current TLB state? With a BDI?
> >>
> >>
> >>
> >>>so what I've been trying to do is catch the TLBmiss reload that actually
> >>>causes this
> >>>to happen to see what it really tried to load into the tlb.
> >>>
> >>>
> >>Shouldnt it be loading the TLB entry which "seem to be OK" accordingly to
> >>your
> >>analysis ??
> >>
> >>
> >
> >So this assumption which you have made sometime ago is wrong, given that
> >now you know TLB entry is not stale ?
> >
> >"The symptom is we appear to have a stale TLB entry,
> >so at least one of the callouts from the generic VM
> >code isn't doing the right thing for us. I'm still
> >puzzled as to why it doesn't affect other PPC processor."
> >
> >_______________________________________________
> >Linuxppc-embedded mailing list
> >Linuxppc-embedded@ozlabs.org
> >https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >
> >
> >
>
> --
> =======================================
> Guillaume Autran
> Senior Software Engineer
> MRV Communications, Inc.
> Tel: (978) 952-4932 office
> E-mail: gautran@mrv.com
> =======================================
>
^ permalink raw reply
* [PATCH] CPM2 cleanups
From: Jason McMullan @ 2005-03-22 20:27 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1.1: Type: text/plain, Size: 208 bytes --]
This patch cleans up CPM2 interrupt controller usage in the
mpc8260/mpc8560, and adds the cpm_cp_command() convenience function.
--
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation
[-- Attachment #1.2: cpu-ppc-cpm2.patch --]
[-- Type: text/x-patch, Size: 11744 bytes --]
#### Auto-generated patch ####
Date: Tue, 22 Mar 2005 15:23:34 -0500
Maintainer: Jason McMullan <jmcmullan@timesys.com>
Summary: Freescale CPM2 device I/O processor, on MPC8xx and MPC8xxx CPUs
Description: Freescale CPM2 device I/O processor, on MPC8xx and MPC8xxx CPUs
###############################
Index of changes:
arch/ppc/platforms/85xx/mpc8560_ads.c | 4 -
arch/ppc/syslib/cpm2_common.c | 4 -
arch/ppc/syslib/cpm2_pic.c | 69 ++++++++++++++++++----
arch/ppc/syslib/cpm2_pic.h | 3
arch/ppc/syslib/m8260_setup.c | 5 -
include/asm-ppc/cpm2.h | 23 ++++++-
include/asm-ppc/irq.h | 105 +++++++++++++++++-----------------
7 files changed, 138 insertions(+), 75 deletions(-)
--- linux-orig/arch/ppc/platforms/85xx/mpc8560_ads.c
+++ linux/arch/ppc/platforms/85xx/mpc8560_ads.c
@@ -135,7 +135,6 @@
static void __init
mpc8560_ads_init_IRQ(void)
{
- int i;
volatile cpm2_map_t *immap = cpm2_immr;
/* Setup OpenPIC */
@@ -145,8 +144,7 @@
immap->im_intctl.ic_simrh = 0x0;
immap->im_intctl.ic_simrl = 0x0;
- for (i = CPM_IRQ_OFFSET; i < (NR_CPM_INTS + CPM_IRQ_OFFSET); i++)
- irq_desc[i].handler = &cpm2_pic;
+ cpm2_init_IRQ();
/* Initialize the default interrupt mapping priorities,
* in case the boot rom changed something on us.
--- linux-orig/arch/ppc/syslib/cpm2_common.c
+++ linux/arch/ppc/syslib/cpm2_common.c
@@ -32,12 +32,12 @@
#include <asm/rheap.h>
static void cpm2_dpinit(void);
-cpm_cpm2_t *cpmp; /* Pointer to comm processor space */
+volatile cpm_cpm2_t *cpmp; /* Pointer to comm processor space */
/* We allocate this here because it is used almost exclusively for
* the communication processor devices.
*/
-cpm2_map_t *cpm2_immr;
+volatile cpm2_map_t *cpm2_immr;
#define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
of space for CPM as it is larger
--- linux-orig/arch/ppc/syslib/cpm2_pic.c
+++ linux/arch/ppc/syslib/cpm2_pic.c
@@ -100,20 +100,29 @@
}
}
-struct hw_interrupt_type cpm2_pic = {
- " CPM2 SIU ",
- NULL,
- NULL,
- cpm2_unmask_irq,
- cpm2_mask_irq,
- cpm2_mask_and_ack,
- cpm2_end_irq,
- 0
+static unsigned int cpm2_startup_irq(unsigned int irq)
+{
+ cpm2_unmask_irq(irq);
+ return 0;
+}
+
+static void cpm2_shutdown_irq(unsigned int irq)
+{
+ cpm2_mask_irq(irq);
+}
+
+
+static struct hw_interrupt_type cpm2_pic = {
+ .typename = "CPM2 SIU",
+ .startup = cpm2_startup_irq,
+ .shutdown = cpm2_shutdown_irq,
+ .enable = cpm2_unmask_irq,
+ .disable = cpm2_mask_irq,
+ .ack = cpm2_mask_and_ack,
+ .end = cpm2_end_irq,
};
-
-int
-cpm2_get_irq(struct pt_regs *regs)
+int cpm2_get_irq(struct pt_regs *regs)
{
int irq;
unsigned long bits;
@@ -125,5 +134,39 @@
if (irq == 0)
return(-1);
- return irq;
+ return irq+CPM_IRQ_OFFSET;
+}
+
+#ifndef SA_NOTHREAD
+#define SA_NOTHREAD 0
+#endif
+
+void cpm2_init_IRQ(void)
+{
+ int i;
+
+ /* Clear the CPM IRQ controller, in case it has any bits set
+ * from the bootloader
+ */
+
+ /* Mask out everything */
+ cpm2_immr->im_intctl.ic_simrh = 0x00000000;
+ cpm2_immr->im_intctl.ic_simrl = 0x00000000;
+ wmb();
+
+ /* Ack everything */
+ cpm2_immr->im_intctl.ic_sipnrh = 0xffffffff;
+ cpm2_immr->im_intctl.ic_sipnrl = 0xffffffff;
+ wmb();
+
+ /* Dummy read of the vector */
+ i = cpm2_immr->im_intctl.ic_sivec;
+ rmb();
+
+ /* Enable chaining to OpenPIC, and make everything level
+ */
+ for (i = 0; i < NR_CPM_INTS; i++) {
+ irq_desc[i+CPM_IRQ_OFFSET].handler = &cpm2_pic;
+ irq_desc[i+CPM_IRQ_OFFSET].status |= IRQ_LEVEL;
+ }
}
--- linux-orig/arch/ppc/syslib/cpm2_pic.h
+++ linux/arch/ppc/syslib/cpm2_pic.h
@@ -1,7 +1,8 @@
#ifndef _PPC_KERNEL_CPM2_H
#define _PPC_KERNEL_CPM2_H
-extern struct hw_interrupt_type cpm2_pic;
extern int cpm2_get_irq(struct pt_regs *regs);
+extern void cpm2_init_IRQ(void);
+
#endif /* _PPC_KERNEL_CPM2_H */
--- linux-orig/arch/ppc/syslib/m8260_setup.c
+++ linux/arch/ppc/syslib/m8260_setup.c
@@ -168,10 +168,7 @@
static void __init
m8260_init_IRQ(void)
{
- int i;
-
- for ( i = 0 ; i < NR_SIU_INTS ; i++ )
- irq_desc[i].handler = &cpm2_pic;
+ cpm2_init_IRQ();
/* Initialize the default interrupt mapping priorities,
* in case the boot rom changed something on us.
--- linux-orig/include/asm-ppc/cpm2.h
+++ linux/include/asm-ppc/cpm2.h
@@ -69,13 +69,14 @@
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
+#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define CPM_CR_START_IDMA ((ushort)0x0009)
#define CPM_CR_STOP_IDMA ((ushort)0x000b)
#define mk_cr_cmd(PG, SBC, MCN, OP) \
- ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
+ (((PG) << 26) | ((SBC) << 21) | ((MCN) << 6) | (OP))
/* Dual Port RAM addresses. The first 16K is available for almost
* any CPM use, so we put the BDs there. The first 128 bytes are
@@ -107,7 +108,7 @@
/* Export the base address of the communication processor registers
* and dual port ram.
*/
-extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */
+extern volatile cpm_cpm2_t *cpmp; /* Pointer to comm processor */
extern uint cpm_dpalloc(uint size, uint align);
extern int cpm_dpfree(uint offset);
extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
@@ -115,7 +116,24 @@
extern void *cpm_dpram_addr(uint offset);
extern void cpm_setbrg(uint brg, uint rate);
extern void cpm2_fastbrg(uint brg, uint rate, int div16);
+extern void cpm2_reset(void);
+
+#ifdef CONFIG_CPM2
+#define CPM_CP_FCC(line, mcn) mk_cr_cmd(CPM_CR_FCC1_PAGE+(line),CPM_CR_FCC1_SBLOCK+(line), mcn, 0)
+#define CPM_CP_SCC(line) mk_cr_cmd(CPM_CR_SCC1_PAGE+(line),CPM_CR_SCC1_SBLOCK+(line), 0, 0)
+#define CPM_CP_SMC(line) mk_cr_cmd(CPM_CR_SMC1_PAGE+(line),CPM_CR_SMC1_SBLOCK+(line), 0, 0)
+#define CPM_CP_I2C mk_cr_cmd(CPM_CR_I2C_PAGE,CPM_CR_I2C_SBLOCK, 0, 0)
+static inline void cpm_cp_command(uint32_t id, int op)
+{
+ cpmp->cp_cpcr = id | op | CPM_CR_FLG;
+
+ while (cpmp->cp_cpcr & CPM_CR_FLG);
+}
+#else
+#error Please define cpm_cp_command and the CPM_CP_* ids you will need.
+#endif
+
/* Buffer descriptors used by many of the CPM protocols.
*/
typedef struct cpm_buf_desc {
@@ -135,6 +153,7 @@
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
+#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_CD ((ushort)0x0001) /* ?? */
--- linux-orig/include/asm-ppc/irq.h
+++ linux/include/asm-ppc/irq.h
@@ -257,57 +257,62 @@
* (Document errata updates have fixed this...make sure you have up to
* date processor documentation -- Dan).
*/
-#define NR_SIU_INTS 64
+
+#ifndef CPM_IRQ_OFFSET
+#define CPM_IRQ_OFFSET 0
+#endif
+
+#define NR_CPM_INTS 64
-#define SIU_INT_ERROR ((uint)0x00)
-#define SIU_INT_I2C ((uint)0x01)
-#define SIU_INT_SPI ((uint)0x02)
-#define SIU_INT_RISC ((uint)0x03)
-#define SIU_INT_SMC1 ((uint)0x04)
-#define SIU_INT_SMC2 ((uint)0x05)
-#define SIU_INT_IDMA1 ((uint)0x06)
-#define SIU_INT_IDMA2 ((uint)0x07)
-#define SIU_INT_IDMA3 ((uint)0x08)
-#define SIU_INT_IDMA4 ((uint)0x09)
-#define SIU_INT_SDMA ((uint)0x0a)
-#define SIU_INT_TIMER1 ((uint)0x0c)
-#define SIU_INT_TIMER2 ((uint)0x0d)
-#define SIU_INT_TIMER3 ((uint)0x0e)
-#define SIU_INT_TIMER4 ((uint)0x0f)
-#define SIU_INT_TMCNT ((uint)0x10)
-#define SIU_INT_PIT ((uint)0x11)
-#define SIU_INT_IRQ1 ((uint)0x13)
-#define SIU_INT_IRQ2 ((uint)0x14)
-#define SIU_INT_IRQ3 ((uint)0x15)
-#define SIU_INT_IRQ4 ((uint)0x16)
-#define SIU_INT_IRQ5 ((uint)0x17)
-#define SIU_INT_IRQ6 ((uint)0x18)
-#define SIU_INT_IRQ7 ((uint)0x19)
-#define SIU_INT_FCC1 ((uint)0x20)
-#define SIU_INT_FCC2 ((uint)0x21)
-#define SIU_INT_FCC3 ((uint)0x22)
-#define SIU_INT_MCC1 ((uint)0x24)
-#define SIU_INT_MCC2 ((uint)0x25)
-#define SIU_INT_SCC1 ((uint)0x28)
-#define SIU_INT_SCC2 ((uint)0x29)
-#define SIU_INT_SCC3 ((uint)0x2a)
-#define SIU_INT_SCC4 ((uint)0x2b)
-#define SIU_INT_PC15 ((uint)0x30)
-#define SIU_INT_PC14 ((uint)0x31)
-#define SIU_INT_PC13 ((uint)0x32)
-#define SIU_INT_PC12 ((uint)0x33)
-#define SIU_INT_PC11 ((uint)0x34)
-#define SIU_INT_PC10 ((uint)0x35)
-#define SIU_INT_PC9 ((uint)0x36)
-#define SIU_INT_PC8 ((uint)0x37)
-#define SIU_INT_PC7 ((uint)0x38)
-#define SIU_INT_PC6 ((uint)0x39)
-#define SIU_INT_PC5 ((uint)0x3a)
-#define SIU_INT_PC4 ((uint)0x3b)
-#define SIU_INT_PC3 ((uint)0x3c)
-#define SIU_INT_PC2 ((uint)0x3d)
-#define SIU_INT_PC1 ((uint)0x3e)
-#define SIU_INT_PC0 ((uint)0x3f)
+#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
+#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
+#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
+#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
+#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
+#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
+#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
+#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
+#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
+#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
+#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
+#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
+#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
+#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
+#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
+#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
+#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
+#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
+#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
+#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
+#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
+#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
+#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
+#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
+#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
+#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
+#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
+#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
#endif /* CONFIG_8260 */
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* [PATCH] CPM2 I2C (SDMA and Bit-Banger)
From: Jason McMullan @ 2005-03-22 20:33 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1.1: Type: text/plain, Size: 217 bytes --]
This patch adds CPM2 I2C support, both in bit-bang and CPM SDMA modes.
Lightly tested, and should be easily ported to the MPC8xx's CPM.
--
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation
[-- Attachment #1.2: driver-i2c-cpm.patch --]
[-- Type: text/x-patch, Size: 24305 bytes --]
#### Auto-generated patch ####
Date: Tue, 22 Mar 2005 15:23:27 -0500
Maintainer: Jason McMullan <jmcmullan@timesys.com>
Summary: CPM/CPM2 I2C driver for Freescale SoC devices
Description: CPM/CPM2 I2C driver for Freescale SoC devices
Depends:
###############################
Index of changes:
drivers/i2c/algos/Kconfig | 4
drivers/i2c/algos/Makefile | 1
drivers/i2c/busses/Kconfig | 25 +
drivers/i2c/busses/Makefile | 1
include/linux/i2c-id.h | 4
linux/drivers/i2c/algos/i2c-algo-cpm.c | 477 +++++++++++++++++++++++++++++++++
linux/drivers/i2c/busses/i2c-cpm.c | 215 ++++++++++++++
linux/include/linux/i2c-algo-cpm.h | 64 ++++
8 files changed, 787 insertions(+), 4 deletions(-)
--- linux-orig/drivers/i2c/algos/Kconfig
+++ linux/drivers/i2c/algos/Kconfig
@@ -16,6 +16,10 @@
This support is also available as a module. If so, the module
will be called i2c-algo-bit.
+config I2C_ALGO_CPM
+ tristate "MPC (8xx and 8xxx) CPM I2C interface"
+ depends on (8xx || 85xx ) && I2C
+
config I2C_ALGOPCF
tristate "I2C PCF 8584 interfaces"
depends on I2C
--- linux-orig/drivers/i2c/algos/Makefile
+++ linux/drivers/i2c/algos/Makefile
@@ -3,6 +3,7 @@
#
obj-$(CONFIG_I2C_ALGOBIT) += i2c-algo-bit.o
+obj-$(CONFIG_I2C_ALGO_CPM) += i2c-algo-cpm.o
obj-$(CONFIG_I2C_ALGOPCF) += i2c-algo-pcf.o
obj-$(CONFIG_I2C_ALGOPCA) += i2c-algo-pca.o
obj-$(CONFIG_I2C_ALGOITE) += i2c-algo-ite.o
--- /dev/null
+++ linux/drivers/i2c/algos/i2c-algo-cpm.c
@@ -0,0 +1,477 @@
+/*
+ * i2c-algo-cpm.c i2x driver algorithms for Motorola MPC CPM
+ * Copyright (c) 2004 Jason McMullan (jason.mcmullan@timesys.com)
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * based on i2c-algo-cpm.c
+ */
+
+/* $Id$ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+#include <linux/ioport.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-algo-cpm.h>
+
+#include <asm/io.h>
+
+#define I2C_VERSION "0.1"
+#define I2C_DATE "Mar 22, 2005"
+
+#define CPM_MAX_READ 513
+/* #define I2C_CHIP_ERRATA */ /* Try uncomment this if you have an older CPU(earlier than rev D4) */
+
+#undef DEBUG
+
+#ifdef DEBUG
+int cpm_debug = 0;
+MODULE_PARM(cpm_debug, "i");
+#define static /**/
+#define DPRINTK(fmt, args...) printk(KERN_INFO fmt ,##args)
+#else
+#define DPRINTK(args...) do { } while (0)
+#endif
+
+static void cpm_i2c_param_reset(struct i2c_algo_cpm_data *cpm_adap)
+{
+ volatile cpm_iic_t *iip = cpm_adap->iip;
+
+ /* Set up the IIC parameters in the parameter ram.
+ */
+ iip->iic_rbase = cpm_adap->dp_offset;
+ iip->iic_tbase = cpm_adap->dp_offset + sizeof(cbd_t)*2;
+
+ /* Initialize the parameter ram.
+ * We need to make sure many things are initialized to zero,
+ * especially in the case of a microcode patch.
+ */
+ iip->iic_rstate = 0;
+ iip->iic_rdp = 0;
+ iip->iic_rbptr = 0;
+ iip->iic_rbc = 0;
+ iip->iic_rxtmp = 0;
+ iip->iic_tstate = 0;
+ iip->iic_tdp = 0;
+ iip->iic_tbptr = 0;
+ iip->iic_tbc = 0;
+ iip->iic_txtmp = 0;
+
+ iip->iic_tfcr = CPMFCR_EB | CPMFCR_GBL;
+ iip->iic_rfcr = CPMFCR_EB | CPMFCR_GBL;
+
+ /* Set maximum receive size.
+ */
+ iip->iic_mrblr = CPM_MAX_READ;
+
+}
+
+static int i2c_cpm_start(struct i2c_algo_cpm_data *cpm)
+{
+ volatile cpm_i2c_t *i2c = cpm->i2c;
+
+ DPRINTK("i2c_cpm_start: Ready (i2cmr=%.2x, i2cer=%.2x, i2com=%.2x, i2mod=%.2x)\n", i2c->i2c_i2cmr,i2c->i2c_i2cer,i2c->i2c_i2com,i2c->i2c_i2mod);
+
+ /* Wait for IIC transfer */
+ cpm->status = -EBUSY;
+ i2c->i2c_i2mod &= ~I2MOD_EN;
+
+ /* Chip bug, set enable here */
+ i2c->i2c_i2cmr = I2CER_MASK; /* Enable interupts */
+ i2c->i2c_i2cer = I2CER_MASK;
+ i2c->i2c_i2mod = I2MOD_EN; /* Enable */
+ i2c->i2c_i2com = I2COM_STR | I2COM_MS; /* Begin transmission */
+ interruptible_sleep_on(&cpm->wait);
+
+ DPRINTK("i2c_cpm_start: Done (i2cmr=%.2x, i2cer=%.2x, i2com=%.2x, i2mod=%.2x)\n", i2c->i2c_i2cmr,i2c->i2c_i2cer,i2c->i2c_i2com,i2c->i2c_i2mod);
+
+ DPRINTK("i2c_cpm_start: result=%d\n",cpm->status);
+ return cpm->status;
+}
+
+static irqreturn_t i2c_cpm_interrupt(int unused, void *dev_id, struct pt_regs *regs)
+ {
+ struct i2c_algo_cpm_data *cpm_adap = dev_id;
+ uint8_t events;
+
+#ifdef I2C_CHIP_ERRATA
+ /* Chip errata, clear enable.
+ * This seems to not be needed on rev D4 or newer CPUs.
+ * Someone with an older CPU needs to verify this.
+ */
+ cpm_adap->i2c->i2c_i2mod &= ~I2MOD_EN; wmb();
+#endif
+
+ events = cpm_adap->i2c->i2c_i2cer;
+ DPRINTK("i2c_cpm_interrupt: dev_id=0x%p, i2cer=0x%.2x\n", dev_id,events);
+
+
+ if (events & I2CER_TXE) {
+ cpm_adap->status = -ENODEV;
+ } else if (events & I2CER_BSY) {
+ cpm_adap->status = -EAGAIN;
+ } else if (events & (I2CER_RXB | I2CER_TXB)) {
+ cpm_adap->status = 0;
+ }
+
+ /* Clear interrupt.
+ */
+ cpm_adap->i2c->i2c_i2cer = events; wmb();
+
+ /* Get 'em going again.
+ */
+ wake_up_interruptible(&cpm_adap->wait);
+
+ return IRQ_HANDLED;
+}
+
+/* Read from IIC...
+ * abyte = address byte, with r/w flag already set
+ */
+static int i2c_cpm_read(struct i2c_algo_cpm_data *cpm, uint8_t abyte, char *buf, int count)
+{
+ volatile cbd_t *tbdf, *rbdf;
+ uint8_t *tb;
+ dma_addr_t tb_dma[2];
+ int err;
+
+ DPRINTK("i2c_cpm_read: abyte=0x%x(%c)\n", abyte>>1, "wr"[abyte&1]);
+
+ if (count >= CPM_MAX_READ)
+ return -EINVAL;
+
+ /* If we are relocated, we must reset the params */
+ if (cpm->reloc)
+ cpm_i2c_param_reset(cpm);
+
+ rbdf = (void *)cpm_dpram_addr(cpm->iip->iic_rbase);
+ tbdf = (void *)cpm_dpram_addr(cpm->iip->iic_tbase);
+
+ /* To read, we need an empty buffer of the proper length.
+ * All that is used is the first byte for address, the remainder
+ * is just used for timing (and doesn't really have to exist).
+ */
+ tb = cpm->temp;
+ tb[0] = abyte; /* Device address byte w/rw flag */
+
+
+ tb_dma[0] = dma_map_single(cpm->device, tb, 1, DMA_TO_DEVICE);
+ tbdf->cbd_bufaddr = tb_dma[0];
+ tbdf->cbd_datlen = 1;
+ tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP | BD_IIC_START;
+
+ cpm->iip->iic_mrblr = count + 1;
+
+ tb_dma[1] = dma_map_single(cpm->device, buf, count, DMA_FROM_DEVICE);
+ rbdf->cbd_datlen = 0;
+ rbdf->cbd_bufaddr = tb_dma[1];
+ rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP| BD_SC_INTRPT;
+
+ DPRINTK("tbdf->cbd_sc(0x%p) = 0x%.4x\n",&tbdf->cbd_sc,tbdf->cbd_sc);
+ DPRINTK("rbdf->cbd_sc(0x%p) = 0x%.4x\n",&rbdf->cbd_sc,rbdf->cbd_sc);
+ err = i2c_cpm_start(cpm);
+ dma_unmap_single(cpm->device, tb_dma[1], count, DMA_FROM_DEVICE);
+ dma_unmap_single(cpm->device, tb_dma[0], 1, DMA_TO_DEVICE);
+ DPRINTK("tbdf->cbd_sc(0x%p) = 0x%.4x\n",&tbdf->cbd_sc,tbdf->cbd_sc);
+ DPRINTK("rbdf->cbd_sc(0x%p) = 0x%.4x\n",&rbdf->cbd_sc,rbdf->cbd_sc);
+ if (err)
+ return err;
+
+ if (tbdf->cbd_sc & BD_SC_READY) {
+ DPRINTK("i2c_cpm_read: complete but tbuf ready\n");
+ DPRINTK("\ttx sc %04x, rx sc %04x\n", tbdf->cbd_sc, rbdf->cbd_sc);
+ return -EREMOTEIO;
+ }
+
+ if (tbdf->cbd_sc & BD_SC_NAK) {
+ DPRINTK("i2c_cpm_read: no ack\n");
+ return -EREMOTEIO;
+ }
+
+ if (rbdf->cbd_sc & BD_SC_EMPTY) {
+ DPRINTK("i2c_cpm_read: complete but rbuf empty\n");
+ DPRINTK("\ttx sc %04x, rx sc %04x\n", tbdf->cbd_sc, rbdf->cbd_sc);
+ return -EREMOTEIO;
+ }
+
+ if (rbdf->cbd_sc & BD_SC_OV) {
+ DPRINTK("i2c_cpm_read: Overrun\n");
+ return -EREMOTEIO;
+ }
+
+ DPRINTK("i2c_cpm_read: read %d bytes\n", rbdf->cbd_datlen);
+
+ if (rbdf->cbd_datlen < count) {
+ DPRINTK("i2c_cpm_read: short, wanted %d got %d\n", count, rbdf->cbd_datlen);
+ }
+
+ return count;
+}
+
+/* Write to IIC...
+ * addr = address byte, with r/w flag already set
+ */
+static int
+i2c_cpm_write(struct i2c_algo_cpm_data *cpm, uint8_t abyte, char *buf,int count)
+{
+ volatile cbd_t *tbdf, *rbdf;
+ uint8_t *tb;
+ dma_addr_t tb_dma[2];
+ int err;
+
+ DPRINTK("i2c_cpm_write: abyte=0x%x(%c)\n", abyte>>1, "wr"[abyte&1]);
+
+ /* If we are relocated, we must reset the params */
+ if (cpm->reloc)
+ cpm_i2c_param_reset(cpm);
+
+ tb = cpm->temp;
+ tb[0] = abyte; /* Device address byte w/rw flag */
+
+ /* set up 2 descriptors */
+ tbdf = (void *)cpm_dpram_addr(cpm->iip->iic_tbase);
+ rbdf = (void *)cpm_dpram_addr(cpm->iip->iic_rbase);
+
+ tb_dma[0] = dma_map_single(cpm->device, tb, 1, DMA_TO_DEVICE);
+ tbdf[0].cbd_bufaddr = tb_dma[0];
+ tbdf[0].cbd_datlen = 1;
+ tbdf[0].cbd_sc = BD_SC_READY | BD_SC_INTRPT | BD_IIC_START;
+
+ if (count > 0) {
+ tb_dma[1] = dma_map_single(cpm->device, buf, count, DMA_TO_DEVICE);
+ tbdf[1].cbd_bufaddr = tb_dma[1];
+ tbdf[1].cbd_datlen = count;
+ tbdf[1].cbd_sc = BD_SC_READY | BD_SC_INTRPT | BD_SC_LAST | BD_SC_WRAP;
+ } else {
+ tbdf[0].cbd_sc |= BD_SC_INTRPT | BD_SC_LAST | BD_SC_WRAP;
+ tb_dma[1] = 0;
+ }
+
+ rbdf[0].cbd_sc = BD_SC_WRAP;
+
+ DPRINTK("tbdf->cbd_sc(0x%p) = 0x%.4x(%d),0x%.4x(%d)\n",&tbdf->cbd_sc,tbdf[0].cbd_sc,tbdf[0].cbd_datlen,tbdf[1].cbd_sc,tbdf[1].cbd_datlen);
+ err = i2c_cpm_start(cpm);
+
+ if (tb_dma[1])
+ dma_unmap_single(cpm->device, tb_dma[1], count, DMA_TO_DEVICE);
+ dma_unmap_single(cpm->device, tb_dma[0], 1, DMA_TO_DEVICE);
+
+ DPRINTK("tbdf->cbd_sc(0x%p) = 0x%.4x(%d),0x%.4x(%d)\n",&tbdf->cbd_sc,tbdf[0].cbd_sc,tbdf[0].cbd_datlen,tbdf[1].cbd_sc,tbdf[1].cbd_datlen);
+ if (err < 0)
+ return err;
+
+
+ if (tbdf->cbd_sc & BD_SC_NAK) {
+ DPRINTK("i2c_cpm_write; no ack\n");
+ return -ENODEV;
+ }
+
+ if (tbdf->cbd_sc & BD_SC_READY) {
+ DPRINTK("i2c_cpm_write: complete but tbuf ready\n");
+ return -EREMOTEIO;
+ }
+
+ return count;
+}
+
+static int cpm_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg msgs[],
+ int num)
+{
+ struct i2c_algo_cpm_data *adap = i2c_adap->algo_data;
+ struct i2c_msg *pmsg;
+ int i, ret;
+ uint8_t addr;
+
+ for (i = 0; i < num; i++) {
+ pmsg = &msgs[i];
+
+ DPRINTK("i2c-algo-cpm: #%d addr=0x%x flags=0x%x len=%d\n buf=%lx\n", i, pmsg->addr, pmsg->flags, pmsg->len, (unsigned long)pmsg->buf);
+
+ addr = pmsg->addr << 1;
+ if (pmsg->flags & I2C_M_RD )
+ addr |= 1;
+ if (pmsg->flags & I2C_M_REV_DIR_ADDR )
+ addr ^= 1;
+
+ if (!(pmsg->flags & I2C_M_NOSTART)) {
+ }
+ if (pmsg->flags & I2C_M_RD ) {
+ /* read bytes into buffer*/
+ ret = i2c_cpm_read(adap, addr, pmsg->buf, pmsg->len);
+ DPRINTK("i2c-algo-cpm: read %d bytes\n", ret);
+ if (ret < pmsg->len ) {
+ return (ret<0)? ret : -EREMOTEIO;
+ }
+ } else {
+ /* write bytes from buffer */
+ ret = i2c_cpm_write(adap, addr, pmsg->buf, pmsg->len);
+ DPRINTK("i2c-algo-cpm: wrote %d\n", ret);
+ if (ret < pmsg->len ) {
+ return (ret<0) ? ret : -EREMOTEIO;
+ }
+ }
+ }
+ return (num);
+}
+
+static int algo_control(struct i2c_adapter *adapter,
+ unsigned int cmd, unsigned long arg)
+{
+ return 0;
+}
+
+static u32 cpm_func(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
+}
+
+/* -----exported algorithm data: ------------------------------------- */
+
+static struct i2c_algorithm cpm_algo = {
+ "CPM2 algorithm",
+ I2C_ALGO_CPM2,
+ cpm_xfer,
+ NULL,
+ NULL, /* slave_xmit */
+ NULL, /* slave_recv */
+ algo_control, /* ioctl */
+ cpm_func, /* functionality */
+};
+
+static int i2c_cpm_init(struct i2c_algo_cpm_data *cpm_adap)
+{
+ volatile cpm_i2c_t *i2c = cpm_adap->i2c;
+ unsigned char brg;
+
+ DPRINTK("i2c_cpm_init() - iip=%p\n",cpm_adap->iip);
+
+ cpm_adap->dp_offset = cpm_dpalloc(sizeof(cbd_t)*4+1, 16);
+ cpm_adap->temp = cpm_dpram_addr(cpm_adap->dp_offset+sizeof(cbd_t)*4);
+
+ cpm_i2c_param_reset(cpm_adap);
+
+ /* Initialize Tx/Rx parameters.
+ */
+ if (! cpm_adap->reloc)
+ cpm_cp_command(CPM_CP_I2C, CPM_CR_INIT_TRX);
+
+ /* Select an arbitrary address. Just make sure it is unique.
+ */
+ i2c->i2c_i2add = 0xfc; wmb();
+
+ /* Make clock run at 60 KHz.
+ */
+ brg = (unsigned char) (cpm_adap->intfreq/(32*2*60000) -3);
+ i2c->i2c_i2brg = brg;
+
+ i2c->i2c_i2mod = I2MOD_FLT; /* Enable filter */
+
+ /* Disable interrupts.
+ */
+ i2c->i2c_i2cmr = 0;
+ i2c->i2c_i2cer = 0xff;
+
+ init_waitqueue_head(&cpm_adap->wait);
+
+ /* Install interrupt handler.
+ */
+ DPRINTK("%s[%d] Install ISR for IRQ %d\n", __func__,__LINE__, cpm_adap->irq);
+ return request_irq(cpm_adap->irq, i2c_cpm_interrupt, 0, "i2c-algo-cpm", cpm_adap);
+}
+
+
+static int
+i2c_cpm_shutdown(struct i2c_algo_cpm_data *cpm_adap)
+{
+ volatile cpm_i2c_t *i2c = cpm_adap->i2c;
+
+ /* Shut down IIC.
+ */
+ i2c->i2c_i2mod &= ~I2MOD_EN;
+ i2c->i2c_i2cmr = 0;
+ i2c->i2c_i2cer = I2CER_MASK;
+ free_irq(cpm_adap->irq,cpm_adap);
+ cpm_dpfree(cpm_adap->dp_offset);
+
+ return(0);
+}
+
+/*
+ * registering functions to load algorithms at runtime
+ */
+int i2c_cpm_add_bus(struct i2c_adapter *adap)
+{
+ struct i2c_algo_cpm_data *cpm_adap = adap->algo_data;
+
+ DPRINTK("i2c-algo-cpm: hw routines for %s registered.\n", adap->name);
+
+ /* register new adapter to i2c module... */
+
+ adap->id |= cpm_algo.id;
+ adap->algo = &cpm_algo;
+
+ i2c_add_adapter(adap);
+ i2c_cpm_init(cpm_adap);
+
+ return 0;
+}
+
+int i2c_cpm_del_bus(struct i2c_adapter *adap)
+{
+ int res;
+ struct i2c_algo_cpm_data *cpm_adap = adap->algo_data;
+
+ i2c_cpm_shutdown(cpm_adap);
+
+ if ((res = i2c_del_adapter(adap)) < 0)
+ return res;
+
+ printk("i2c-algo-cpm: adapter unregistered: %s\n",adap->name);
+
+ return 0;
+}
+
+MODULE_LICENSE("GPL");
+EXPORT_SYMBOL(i2c_cpm_add_bus);
+EXPORT_SYMBOL(i2c_cpm_del_bus);
+
+int __init i2c_algo_cpm_init (void)
+{
+ printk("i2c-algo-cpm: CPM2 I2C algorithm module version %s (%s)\n", I2C_VERSION, I2C_DATE);
+ return 0;
+}
+
+
+MODULE_AUTHOR("Jason McMullan <jason.mcmullan@timesys.com>");
+MODULE_DESCRIPTION("I2C-Bus CPM2 algorithm");
+
+static void i2c_algo_cpm_exit(void)
+{
+}
+
+module_init(i2c_algo_cpm_init);
+module_exit(i2c_algo_cpm_exit);
--- linux-orig/drivers/i2c/busses/Kconfig
+++ linux/drivers/i2c/busses/Kconfig
@@ -229,6 +229,21 @@
This driver can also be built as a module. If so, the module
will be called i2c-mpc.
+config I2C_CPM
+ tristate "Motorola MPC8xx and MPC85xx CPM I2C"
+ depends on (8xx || 85xx) && I2C
+ help
+ This supports the use of the I2C interface in the Motorola
+ MPC8xx and MPC85xx series embedded processors on the CPM
+ I2C macrocell.
+
+config I2C_CPM_BIT
+ bool "Bit-Bang only?"
+ depends on I2C_CPM
+ help
+ Only use the CPM parallel port bit-banging interface, not the
+ SDMA CPM device.
+
config I2C_NFORCE2
tristate "Nvidia Nforce2"
depends on I2C && PCI && EXPERIMENTAL
@@ -317,10 +332,12 @@
This support is also available as a module. If so, the module
will be called i2c-prosavage.
-config I2C_RPXLITE
- tristate "Embedded Planet RPX Lite/Classic support"
- depends on (RPXLITE || RPXCLASSIC) && I2C
- select I2C_ALGO8XX
+# This appears to be broken...
+#
+#config I2C_RPXLITE
+# tristate "Embedded Planet RPX Lite/Classic support"
+# depends on (RPXLITE || RPXCLASSIC) && I2C
+# select I2C_ALGO8XX
config I2C_S3C2410
tristate "S3C2410 I2C Driver"
--- linux-orig/drivers/i2c/busses/Makefile
+++ linux/drivers/i2c/busses/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_I2C_AMD756) += i2c-amd756.o
obj-$(CONFIG_I2C_AMD756_S4882) += i2c-amd756-s4882.o
obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o
+obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o
--- /dev/null
+++ linux/drivers/i2c/busses/i2c-cpm.c
@@ -0,0 +1,215 @@
+/*
+ * CPM I2C interface.
+ * Copyright (c) 2004 Jason McMullan (jason.mcmullan@timesys.com)
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
+ *
+ * On-Chip Peripheral version of the Motorola CPM I2C macrocell driver,
+ * used on the MPC8xx and MPC85xx series processors.
+ */
+
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/stddef.h>
+#include <linux/device.h>
+
+#include <linux/i2c.h>
+
+#include <asm/io.h>
+#ifdef CONFIG_CPM2
+#include <asm/cpm2.h>
+#else
+#include <asm/commproc.h>
+#endif
+
+#ifdef CONFIG_I2C_CPM_BIT
+#include <linux/i2c-algo-bit.h>
+
+#define CYCLE_DELAY 10
+#define TIMEOUT (HZ / 2)
+#endif /* CONFIG_I2C_CPM_BIT */
+
+#ifdef CONFIG_CPM2
+/* SDA and SCL bits on port D */
+#define BIT_SDA (1<<16)
+#define BIT_SCL (1<<17)
+#endif /* CONFIG_CPM2 */
+
+#ifdef CONFIG_I2C_CPM_BIT
+static void bit_cpm_setsda(void *data, int state)
+{
+ if (state)
+ cpm2_immr->im_ioport.iop_pdatd |= BIT_SDA;
+ else
+ cpm2_immr->im_ioport.iop_pdatd &= ~BIT_SDA;
+}
+
+static void bit_cpm_setscl(void *data, int state)
+{
+ if (state)
+ cpm2_immr->im_ioport.iop_pdatd |= BIT_SCL;
+ else
+ cpm2_immr->im_ioport.iop_pdatd &= ~BIT_SCL;
+}
+
+static int bit_cpm_getsda(void *data)
+{
+ return (cpm2_immr->im_ioport.iop_pdatd & BIT_SDA) ? 1 : 0;
+}
+
+static int bit_cpm_getscl(void *data)
+{
+ return (cpm2_immr->im_ioport.iop_pdatd & BIT_SCL) ? 1 : 0;
+}
+
+
+static struct i2c_algo_bit_data cpm_data = {
+ .setsda = bit_cpm_setsda,
+ .setscl = bit_cpm_setscl,
+ .getsda = bit_cpm_getsda,
+ .getscl = bit_cpm_getscl,
+ .udelay = CYCLE_DELAY,
+ .mdelay = CYCLE_DELAY,
+ .timeout = TIMEOUT
+};
+#else /* !CONFIG_I2C_CPM_BIT */
+#include <linux/i2c-algo-cpm.h>
+
+static struct i2c_algo_cpm_data cpm_data = { .irq = -1 };
+#endif /* !CONFIG_I2C_CPM_BIT */
+
+static struct i2c_adapter cpm_ops = {
+ .owner = THIS_MODULE,
+ .name = "cpm-i2c",
+ .id = I2C_HW_CPM2,
+ .algo_data = &cpm_data,
+};
+
+#ifdef CONFIG_I2C_CPM_BIT
+static int __devinit cpm_i2c_probe_bitbang(struct device *dev)
+{
+#ifdef CONFIG_CPM2
+ if (cpm2_immr->im_ioport.iop_ppard & (BIT_SCL | BIT_SDA)) {
+ printk(KERN_INFO "%s: CPM I/O Port D is not configured for I2C bit-bang mode.\n", pdev->bus_id);
+ return -ENODEV;
+ }
+
+ /* Configure as open drain... */
+ cpm2_immr->im_ioport.iop_podrd |= (BIT_SCL | BIT_SDA);
+
+ /* Inputs... */
+ cpm2_immr->im_ioport.iop_pdird &= ~(BIT_SCL | BIT_SDA);
+#endif
+
+ return i2c_bit_add_bus(&cpm_ops);
+}
+#else
+static int __devinit cpm_i2c_probe_cpm(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct resource *res;
+ int err;
+ struct i2c_algo_cpm_data *data = &cpm_data;
+ bd_t *binfo = (bd_t *)__res;
+
+ if (data->irq != -1)
+ return -EBUSY;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL)
+ return -EINVAL;
+
+ data->i2c = (cpm_i2c_t *)ioremap(res->start,sizeof(cpm_i2c_t));
+ if (data->i2c == NULL) {
+ iounmap((void *)data->iip);
+ return -ENOMEM;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (res == NULL)
+ return -EINVAL;
+
+ data->iip = (iic_t *)ioremap(res->start,sizeof(iic_t));
+ if (data->iip == NULL) {
+ return -ENOMEM;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (res == NULL)
+ return -EINVAL;
+
+#ifdef CONFIG_CPM2
+ /* Configure as peripheral... */
+ cpm2_immr->im_ioport.iop_ppard |= (BIT_SCL | BIT_SDA);
+ cpm2_immr->im_ioport.iop_psord |= (BIT_SCL | BIT_SDA);
+
+ /* Inputs... */
+ cpm2_immr->im_ioport.iop_pdird &= ~(BIT_SCL | BIT_SDA);
+#endif
+
+ data->irq = res->start;
+
+ data->device = dev;
+ data->intfreq = binfo->bi_intfreq;
+
+ err = i2c_cpm_add_bus(&cpm_ops);
+ if (err < 0) {
+ data->irq=-1;
+ iounmap((void *)data->iip);
+ iounmap((void *)data->i2c);
+ return err;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_I2C_CPM_BIT
+static void __devexit cpm_i2c_remove_bitbang(struct device *dev)
+{
+ i2c_bit_del_bus(&cpm_ops);
+}
+#else
+static void __devexit cpm_i2c_remove_cpm(struct device *dev)
+{
+ struct i2c_algo_cpm_data *data = &cpm_data;
+
+ i2c_cpm_del_bus(&cpm_ops);
+
+ iounmap((void *)data->iip);
+ iounmap((void *)data->i2c);
+}
+#endif
+
+static struct device_driver cpm_i2c_driver = {
+ .name = "fsl-cpm-i2c",
+ .bus = &platform_bus_type,
+#ifdef CONFIG_I2C_CPM_BIT
+ .probe = cpm_i2c_probe_bitbang,
+ .remove = __devexit_p(cpm_i2c_remove_bitbang),
+#else
+ .probe = cpm_i2c_probe_cpm,
+ .remove = __devexit_p(cpm_i2c_remove_cpm),
+#endif
+};
+
+int __init cpm_i2c_init(void)
+{
+ printk(KERN_INFO "%s: CPM2 i2c driver\n",cpm_i2c_driver.name);
+
+ return driver_register(&cpm_i2c_driver);
+}
+
+void __exit cpm_i2c_exit(void)
+{
+ driver_unregister(&cpm_i2c_driver);
+}
+
+MODULE_LICENSE("GPL");
+
+MODULE_AUTHOR("Jason McMullan <jason.mcmullan@timesys.com>");
+MODULE_DESCRIPTION("I2C-Bus (on CPM) adapter routines for MPC8xx and MPC85xx boards");
+
+module_init(cpm_i2c_init);
+module_exit(cpm_i2c_exit);
--- /dev/null
+++ linux/include/linux/i2c-algo-cpm.h
@@ -0,0 +1,64 @@
+/* ------------------------------------------------------------------------- */
+/* i2c-algo-mpc.h i2c driver algorithms for MPC CPMs */
+/* ------------------------------------------------------------------------- */
+
+/* $Id$ */
+
+#ifndef I2C_ALGO_MPC_H
+#define I2C_ALGO_MPC_H 1
+
+#include <linux/i2c.h>
+
+#ifdef CONFIG_85xx
+#include <asm/mpc85xx.h>
+#include <asm/cpm2.h>
+#include <asm/immap_85xx.h>
+
+typedef i2c_cpm2_t cpm_i2c_t;
+typedef iic_t cpm_iic_t;
+
+#elif defined(CONFIG_8xx)
+#include <asm/mpc8xx.h>
+#include <asm/commproc.h>
+
+typedef i2c8xx_t cpm_i2c_t;
+typedef iic_t cpm_iic_t;
+#endif
+
+#define I2MOD_EN 0x01
+#define I2MOD_PDIV_MASK 0x06
+#define I2MOD_PDIV_4 0x06
+#define I2MOD_PDIV_8 0x04
+#define I2MOD_PDIV_16 0x02
+#define I2MOD_PDIV_32 0x00
+#define I2MOD_FLT 0x08
+#define I2MOD_GCD 0x10
+#define I2MOD_REVD 0x20
+
+#define I2COM_MS 0x01
+#define I2COM_STR 0x80
+
+#define I2CER_MASK 0x17
+#define I2CER_TXE 0x10
+#define I2CER_BSY 0x04
+#define I2CER_TXB 0x02
+#define I2CER_RXB 0x01
+
+struct i2c_algo_cpm_data {
+ struct device *device;
+ dma_addr_t dp_offset;
+ int reloc;
+ volatile cpm_i2c_t *i2c;
+ volatile cpm_iic_t *iip;
+ int irq;
+ int intfreq;
+ uint8_t *temp;
+
+ wait_queue_head_t wait;
+ int status;
+};
+
+int i2c_cpm_add_bus(struct i2c_adapter *);
+int i2c_cpm_del_bus(struct i2c_adapter *);
+
+#endif /* I2C_ALGO_CPM_H */
--- linux-orig/include/linux/i2c-id.h
+++ linux/include/linux/i2c-id.h
@@ -201,6 +201,7 @@
#define I2C_ALGO_SIBYTE 0x150000 /* Broadcom SiByte SOCs */
#define I2C_ALGO_SGI 0x160000 /* SGI algorithm */
#define I2C_ALGO_AU1550 0x170000 /* Au1550 PSC algorithm */
+#define I2C_ALGO_CPM2 0x180000 /* MPC8xxx and MPC8xx CPM I2C */
#define I2C_ALGO_EXP 0x800000 /* experimental */
@@ -253,6 +254,9 @@
/* --- ACPI Embedded controller algorithms */
#define I2C_HW_ACPI_EC 0x00
+/* --- Motorola MPC CPM2 I2C adapters -- */
+#define I2C_HW_CPM2 0x00
+
/* --- MPC824x PowerPC adapters */
#define I2C_HW_MPC824X 0x00 /* Motorola 8240 / 8245 */
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* "Viosoft adds adds Abatron JTAG debug probe, PowerPC to toolsuite"
From: Robert P. J. Day @ 2005-03-22 20:39 UTC (permalink / raw)
To: Embedded PPC Linux list
disclaimer: i have no connection with the company above, i just
thought some folks might want to know about this.
http://linuxdevices.com/news/NS3861500285.html
rday
^ permalink raw reply
* [PATCH] MPC85xx FCC and I2C platform device support
From: Jason McMullan @ 2005-03-22 20:41 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1.1: Type: text/plain, Size: 167 bytes --]
Adds platform support for default FCC mac addresses/phy information, and
I2C param info
--
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation
[-- Attachment #1.2: cpu-ppc-mpc85xx.patch --]
[-- Type: text/x-patch, Size: 6370 bytes --]
#### Auto-generated patch ####
Date: Tue, 22 Mar 2005 15:23:37 -0500
Maintainer: Jason McMullan <jmcmullan@timesys.com>
Summary: MPC85xx series CPU support
Description: MPC85xx series CPU support
###############################
--- linux-orig/arch/ppc/platforms/85xx/mpc85xx_devices.c
+++ linux/arch/ppc/platforms/85xx/mpc85xx_devices.c
@@ -19,6 +19,8 @@
#include <linux/serial_8250.h>
#include <linux/fsl_devices.h>
#include <asm/mpc85xx.h>
+#include <asm/cpm2.h>
+#include <asm/immap_cpm2.h>
#include <asm/irq.h>
#include <asm/ppc_sys.h>
@@ -61,8 +63,26 @@
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
},
+ [2] = {
+ .flags = 0
+ }
};
+static struct fcc_platform_data fcc_platform_data[] = {
+ [0] = {
+ .mac_addr = { 0x90, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ },
+ [1] = {
+ .mac_addr = { 0x90, 0x00, 0x00, 0x00, 0x00, 0x01 },
+ },
+ [2] = {
+ .mac_addr = { 0x90, 0x00, 0x00, 0x00, 0x00, 0x02 },
+ }
+};
+
+#define CPM2_OFFSET(t) ((void *)(&((cpm2_map_t *)NULL)->t)-NULL)
+#define CPM2_END(t) (CPM2_OFFSET(t)+(sizeof(((cpm2_map_t *)NULL)->t))-1)
+
struct platform_device ppc_sys_platform_devices[] = {
[MPC85xx_TSEC1] = {
.name = "fsl-gianfar",
@@ -284,16 +304,22 @@
[MPC85xx_CPM_FCC1] = {
.name = "fsl-cpm-fcc",
.id = 1,
- .num_resources = 3,
+ .num_resources = 4,
+ .dev.platform_data = &fcc_platform_data[0],
.resource = (struct resource[]) {
{
- .start = 0x91300,
- .end = 0x9131F,
+ .start = CPM2_OFFSET(im_fcc[0]),
+ .end = CPM2_END(im_fcc[0]),
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = CPM2_OFFSET(im_fcc_c[0]),
+ .end = CPM2_END(im_fcc_c[0]),
.flags = IORESOURCE_MEM,
},
{
- .start = 0x91380,
- .end = 0x9139F,
+ .start = CPM2_OFFSET(im_dprambase[PROFF_FCC1+0x000]),
+ .end = CPM2_OFFSET(im_dprambase[PROFF_FCC1+0x000])+0xff,
.flags = IORESOURCE_MEM,
},
{
@@ -306,16 +332,22 @@
[MPC85xx_CPM_FCC2] = {
.name = "fsl-cpm-fcc",
.id = 2,
- .num_resources = 3,
+ .num_resources = 4,
+ .dev.platform_data = &fcc_platform_data[1],
.resource = (struct resource[]) {
{
- .start = 0x91320,
- .end = 0x9133F,
+ .start = CPM2_OFFSET(im_fcc[1]),
+ .end = CPM2_END(im_fcc[1]),
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = CPM2_OFFSET(im_fcc_c[1]),
+ .end = CPM2_END(im_fcc_c[1]),
.flags = IORESOURCE_MEM,
},
{
- .start = 0x913A0,
- .end = 0x913CF,
+ .start = CPM2_OFFSET(im_dprambase[PROFF_FCC1+0x100]),
+ .end = CPM2_OFFSET(im_dprambase[PROFF_FCC1+0x100])+0xff,
.flags = IORESOURCE_MEM,
},
{
@@ -328,16 +360,22 @@
[MPC85xx_CPM_FCC3] = {
.name = "fsl-cpm-fcc",
.id = 3,
- .num_resources = 3,
+ .num_resources = 4,
+ .dev.platform_data = &fcc_platform_data[2],
.resource = (struct resource[]) {
{
- .start = 0x91340,
- .end = 0x9135F,
+ .start = CPM2_OFFSET(im_fcc[2]),
+ .end = CPM2_END(im_fcc[2]),
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = CPM2_OFFSET(im_fcc_c[2]),
+ .end = CPM2_END(im_fcc_c[2]),
.flags = IORESOURCE_MEM,
},
{
- .start = 0x913D0,
- .end = 0x913FF,
+ .start = CPM2_OFFSET(im_dprambase[PROFF_FCC1+0x200]),
+ .end = CPM2_OFFSET(im_dprambase[PROFF_FCC1+0x200])+0xff,
.flags = IORESOURCE_MEM,
},
{
@@ -350,14 +388,21 @@
[MPC85xx_CPM_I2C] = {
.name = "fsl-cpm-i2c",
.id = 1,
- .num_resources = 2,
+ .num_resources = 3,
.resource = (struct resource[]) {
{
+ .name = "i2c",
.start = 0x91860,
.end = 0x918BF,
.flags = IORESOURCE_MEM,
},
{
+ .name = "iic",
+ .start = 0,
+ .end = 0,
+ .flags = 0,
+ },
+ {
.start = SIU_INT_I2C,
.end = SIU_INT_I2C,
.flags = IORESOURCE_IRQ,
@@ -539,6 +584,13 @@
static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
{
+ if (strcmp(pdev->name,"fsl-cpm-i2c")==0) {
+ uint16_t i2c_dpram = *(uint16_t *)cpm_dpram_addr(PROFF_I2C_BASE);
+ printk(KERN_INFO "%s: Relocated to 0x%.4x\n",pdev->name,i2c_dpram);
+ pdev->resource[1].start = CPM2_OFFSET(im_dprambase[i2c_dpram]);
+ pdev->resource[1].end = CPM2_OFFSET(im_dprambase[i2c_dpram])+sizeof(iic_t)-1;
+ pdev->resource[1].flags = IORESOURCE_MEM;
+ }
ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
return 0;
}
--- linux-orig/arch/ppc/platforms/85xx/mpc85xx_sys.c
+++ linux/arch/ppc/platforms/85xx/mpc85xx_sys.c
@@ -80,7 +80,7 @@
.ppc_sys_name = "MPC8555",
.mask = 0xFFFF0000,
.value = 0x80710000,
- .num_devices = 20,
+ .num_devices = 19,
.device_list = (enum ppc_sys_devices[])
{
MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -88,7 +88,7 @@
MPC85xx_PERFMON, MPC85xx_DUART,
MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3,
- MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3,
+ MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
MPC85xx_CPM_USB,
},
@@ -97,7 +97,7 @@
.ppc_sys_name = "MPC8555E",
.mask = 0xFFFF0000,
.value = 0x80790000,
- .num_devices = 21,
+ .num_devices = 20,
.device_list = (enum ppc_sys_devices[])
{
MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -105,7 +105,7 @@
MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3,
- MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3,
+ MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
MPC85xx_CPM_USB,
},
--- linux-orig/include/linux/fsl_devices.h
+++ linux/include/linux/fsl_devices.h
@@ -65,6 +65,21 @@
/* Flags in gianfar_platform_data */
#define FSL_GIANFAR_BRD_HAS_PHY_INTR 0x00000001 /* if not set use a timer */
+struct fcc_platform_data {
+ /* device specific information */
+
+ /* board speficfic flags */
+ u32 mode;
+ u32 flags;
+ u32 phyid;
+ u8 mac_addr[6];
+};
+
+#define FSL_FCC_BRD_MODE_DISABLED 0
+#define FSL_FCC_BRD_MODE_ETHERNET 1
+
+#define FSL_FCC_BRD_FLAGS_HAS_PHY 0x00000001
+
struct fsl_i2c_platform_data {
/* device specific information */
u32 device_flags;
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* [PATCH] MPC85xx CDS - Time Of Day, Cache settings, CPM IRQs
From: Jason McMullan @ 2005-03-22 20:47 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1.1: Type: text/plain, Size: 223 bytes --]
Some minor fixes for:
MPC85xx CDS Time of Day Clock
/proc/cpuinfo shows cache settings
CPM IRQs are allocated more sanely.
--
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation
[-- Attachment #1.2: board-ppc-mpc85xx-cds.patch --]
[-- Type: text/x-patch, Size: 7872 bytes --]
#### Auto-generated patch ####
Date: Tue, 22 Mar 2005 15:44:01 -0500
Maintainer: Jason McMullan <jmcmullan@timesys.com>
Summary: Freescale MPC85xx CDS series eval boards
###############################
--- linux-orig/arch/ppc/platforms/85xx/Kconfig
+++ linux/arch/ppc/platforms/85xx/Kconfig
@@ -22,9 +22,10 @@
This option enables support for the MPC 8540 ADS evaluation board.
config MPC8555_CDS
- bool "Freescale MPC8555 CDS"
+ bool "Freescale MPC8555/MPC8541 CDS"
help
- This option enablese support for the MPC8555 CDS evaluation board.
+ This option enables support for the MPC8555/MPC8541 CDS
+ evaluation boards.
config MPC8560_ADS
bool "Freescale MPC8560 ADS"
--- linux-orig/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -39,6 +39,7 @@
#include <asm/page.h>
#include <asm/atomic.h>
#include <asm/time.h>
+#include <asm/todc.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/prom.h>
@@ -63,6 +64,10 @@
unsigned long isa_mem_base = 0;
#endif
+#ifdef CONFIG_CPM2
+extern void cpm2_reset(void);
+#endif
+
extern unsigned long total_memory; /* in mm/init */
unsigned char __res[sizeof (bd_t)];
@@ -158,31 +163,27 @@
/* Display the amount of memory */
seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+ /* Display the cache settings */
+ seq_printf(m, "L1 D-cache\t: %s\n",(mfspr(SPRN_L1CSR0)&1) ? "on" : "off");
+ seq_printf(m, "L1 I-cache\t: %s\n",(mfspr(SPRN_L1CSR1)&1) ? "on" : "off");
+ {
+ struct ccsr_l2cache *l2cache;
+ l2cache = ioremap(CCSRBAR+0x20000, sizeof(struct ccsr_l2cache));
+
+ seq_printf(m, "L2 cache\t: %s\n",(l2cache->l2ctl & 0x80000000) ? "on" : "off");
+ iounmap(l2cache);
+ }
+ seq_printf(m, "BPU cache\t: %s\n",(mfspr(SPRN_BUCSR)&1) ? "on" : "off");
+
return 0;
}
-#ifdef CONFIG_CPM2
-static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
-{
- while((irq = cpm2_get_irq(regs)) >= 0)
- __do_IRQ(irq, regs);
-}
-
-static struct irqaction cpm2_irqaction = {
- .handler = cpm2_cascade,
- .flags = SA_INTERRUPT,
- .mask = CPU_MASK_NONE,
- .name = "cpm2_cascade",
-};
-#endif /* CONFIG_CPM2 */
-
void __init
mpc85xx_cds_init_IRQ(void)
{
bd_t *binfo = (bd_t *) __res;
#ifdef CONFIG_CPM2
volatile cpm2_map_t *immap = cpm2_immr;
- int i;
#endif
/* Determine the Physical Address of the OpenPIC regs */
@@ -202,12 +203,7 @@
openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
#ifdef CONFIG_CPM2
- /* disable all CPM interupts */
- immap->im_intctl.ic_simrh = 0x0;
- immap->im_intctl.ic_simrl = 0x0;
-
- for (i = CPM_IRQ_OFFSET; i < (NR_CPM_INTS + CPM_IRQ_OFFSET); i++)
- irq_desc[i].handler = &cpm2_pic;
+ cpm2_init_IRQ();
/* Initialize the default interrupt mapping priorities,
* in case the boot rom changed something on us.
@@ -216,7 +212,7 @@
immap->im_intctl.ic_scprrh = 0x05309770;
immap->im_intctl.ic_scprrl = 0x05309770;
- setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
+ openpic_hookup_cascade(MPC85xx_IRQ_CPM, "CPM Cascade", cpm2_get_irq);
#endif
return;
@@ -303,6 +299,8 @@
}
#endif /* CONFIG_PCI */
+TODC_ALLOC();
+
/* ************************************************************************
*
* Setup the architecture
@@ -328,6 +326,13 @@
cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
+ /* Setup TODC access */
+ TODC_INIT(TODC_TYPE_DS1743,
+ 0,
+ 0,
+ ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
+ 8);
+
/* Set loops_per_jiffy to a half-way reasonable value,
for use until calibrate_delay gets called. */
loops_per_jiffy = freq / HZ;
@@ -364,7 +369,6 @@
pdata->phy_reg_addr += binfo->bi_immr_base;
memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
-
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
@@ -452,11 +456,15 @@
ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
- ppc_md.time_init = NULL;
- ppc_md.set_rtc_time = NULL;
- ppc_md.get_rtc_time = NULL;
ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
+ ppc_md.time_init = todc_time_init;
+ ppc_md.set_rtc_time = todc_set_rtc_time;
+ ppc_md.get_rtc_time = todc_get_rtc_time;
+
+ ppc_md.nvram_read_val = todc_direct_read_val;
+ ppc_md.nvram_write_val = todc_direct_write_val;
+
#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
ppc_md.progress = gen550_progress;
#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
--- linux-orig/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
+++ linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
@@ -33,6 +33,10 @@
#define CM_CSR (1)
#define CM_RST (2)
+/* CDS NVRAM/RTC */
+#define CDS_RTC_ADDR (0xf8000000)
+#define CDS_RTC_SIZE (8 * 1024)
+
/* PCI config */
#define PCI1_CFG_ADDR_OFFSET (0x8000)
#define PCI1_CFG_DATA_OFFSET (0x8004)
--- linux-orig/arch/ppc/syslib/Makefile
+++ linux/arch/ppc/syslib/Makefile
@@ -98,5 +98,6 @@
ppc_sys.o
ifeq ($(CONFIG_85xx),y)
obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
+obj-$(CONFIG_MPC8555_CDS) += todc_time.o
endif
obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o
--- linux-orig/include/asm-ppc/immap_85xx.h
+++ linux/include/asm-ppc/immap_85xx.h
@@ -122,5 +122,49 @@
char res13[61916];
} ccsr_guts_t;
+/* L2 Cache Registers(0x2_0000-0x2_1000) */
+
+typedef struct ccsr_l2cache {
+ uint32_t l2ctl; /* 0x.0000 - L2 configuration register 0 */
+ uint8_t res1[12];
+ uint32_t l2cewar0; /* 0x.0010 - L2 cache external write address register 0 */
+ uint8_t res2[4];
+ uint32_t l2cewcr0; /* 0x.0018 - L2 cache external write control register 0 */
+ uint8_t res3[4];
+ uint32_t l2cewar1; /* 0x.0020 - L2 cache external write address register 1 */
+ uint8_t res4[4];
+ uint32_t l2cewcr1; /* 0x.0028 - L2 cache external write control register 1 */
+ uint8_t res5[4];
+ uint32_t l2cewar2; /* 0x.0030 - L2 cache external write address register 2 */
+ uint8_t res6[4];
+ uint32_t l2cewcr2; /* 0x.0038 - L2 cache external write control register 2 */
+ uint8_t res7[4];
+ uint32_t l2cewar3; /* 0x.0040 - L2 cache external write address register 3 */
+ uint8_t res8[4];
+ uint32_t l2cewcr3; /* 0x.0048 - L2 cache external write control register 3 */
+ uint8_t res9[180];
+ uint32_t l2srbar0; /* 0x.0100 - L2 memory-mapped SRAM base address register 0 */
+ uint8_t res10[4];
+ uint32_t l2srbar1; /* 0x.0108 - L2 memory-mapped SRAM base address register 1 */
+ uint8_t res11[3316];
+ uint32_t l2errinjhi; /* 0x.0e00 - L2 error injection mask high register */
+ uint32_t l2errinjlo; /* 0x.0e04 - L2 error injection mask low register */
+ uint32_t l2errinjctl; /* 0x.0e08 - L2 error injection tag/ECC control register */
+ uint8_t res12[20];
+ uint32_t l2captdatahi; /* 0x.0e20 - L2 error data high capture register */
+ uint32_t l2captdatalo; /* 0x.0e24 - L2 error data low capture register */
+ uint32_t l2captecc; /* 0x.0e28 - L2 error ECC capture register */
+ uint8_t res13[20];
+ uint32_t l2errdet; /* 0x.0e40 - L2 error detect register */
+ uint32_t l2errdis; /* 0x.0e44 - L2 error disable register */
+ uint32_t l2errinten; /* 0x.0e48 - L2 error interrupt enable register */
+ uint32_t l2errattr; /* 0x.0e4c - L2 error attributes capture register */
+ uint32_t l2erraddr; /* 0x.0e50 - L2 error address capture register */
+ uint8_t res14[4];
+ uint32_t l2errctl; /* 0x.0e58 - L2 error control register */
+ uint8_t res15[420];
+} ccsr_l2cache_t;
+
+
#endif /* __ASM_IMMAP_85XX_H__ */
#endif /* __KERNEL__ */
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