* mpc8260 Multi channel controller howto and kernel driver code
From: Mike Ford @ 2005-04-06 17:11 UTC (permalink / raw)
To: 'linuxppc-embedded@ozlabs.org'
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Hello Om,
Did you ever publish your MPC8260 MCC driver code??
Thanks,
Mike Ford
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^ permalink raw reply
* Re: [PATCH 2/3] PPC440EP: IBM EMAC support for the Bamboo board
From: Wade Farnsworth @ 2005-04-06 17:34 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <1112808669.24673.304.camel@rhino.az.mvista.com>
Oops, this should be Patch 2/3.
-Wade
^ permalink raw reply
* Re: [PATCH 3/3] PPC440EP: MTD support for the Bamboo Board
From: Wade Farnsworth @ 2005-04-06 17:33 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <1112808669.24673.304.camel@rhino.az.mvista.com>
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This adds MTD support for the Bamboo board.
-Wade Farnsworth
[-- Attachment #2: ibm440ep-mtd.patch --]
[-- Type: text/x-patch, Size: 21155 bytes --]
diff -uprN linux-2.5-orig/drivers/mtd/maps/Kconfig linux-2.5-440ep/drivers/mtd/maps/Kconfig
--- linux-2.5-orig/drivers/mtd/maps/Kconfig 2005-04-05 15:31:12.000000000 -0700
+++ linux-2.5-440ep/drivers/mtd/maps/Kconfig 2005-04-05 15:37:05.000000000 -0700
@@ -397,6 +397,14 @@ config MTD_OCOTEA
Ocotea board. If you have one of these boards and would like to
use the flash chips on it, say 'Y'.
+config MTD_BAMBOO
+ tristate "Flash devices mapped on IBM 440EP Bamboo"
+ depends on MTD_CFI && PPC32 && 44x && BAMBOO
+ help
+ This enables access routined for the flash chips on the IBM 440EP
+ Bamboo board. If you have one of these boards and would like to
+ use the flash chips on it, say 'Y'.
+
config MTD_REDWOOD
tristate "CFI Flash devices mapped on IBM Redwood"
depends on MTD_CFI && PPC32 && 4xx && 40x && ( REDWOOD_4 || REDWOOD_5 || REDWOOD_6 )
diff -uprN linux-2.5-orig/drivers/mtd/maps/Makefile linux-2.5-440ep/drivers/mtd/maps/Makefile
--- linux-2.5-orig/drivers/mtd/maps/Makefile 2005-04-05 15:31:12.000000000 -0700
+++ linux-2.5-440ep/drivers/mtd/maps/Makefile 2005-04-05 15:37:06.000000000 -0700
@@ -59,6 +59,7 @@ obj-$(CONFIG_MTD_NETtel) += nettel.o
obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o
obj-$(CONFIG_MTD_EBONY) += ebony.o
obj-$(CONFIG_MTD_OCOTEA) += ocotea.o
+obj-$(CONFIG_MTD_BAMBOO) += bamboo.o
obj-$(CONFIG_MTD_BEECH) += beech-mtd.o
obj-$(CONFIG_MTD_ARCTIC) += arctic-mtd.o
obj-$(CONFIG_MTD_WALNUT) += walnut.o
diff -uprN linux-2.5-orig/drivers/mtd/maps/bamboo.c linux-2.5-440ep/drivers/mtd/maps/bamboo.c
--- linux-2.5-orig/drivers/mtd/maps/bamboo.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.5-440ep/drivers/mtd/maps/bamboo.c 2005-04-05 15:37:06.000000000 -0700
@@ -0,0 +1,245 @@
+/*
+ * Mapping for Bamboo user flash
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/config.h>
+#include <asm/io.h>
+#include <asm/ibm44x.h>
+#include <platforms/4xx/bamboo.h>
+
+static struct mtd_info *small_flash, *large_flash, *sram;
+
+static struct map_info bamboo_small_map = {
+ .name = "Bamboo small flash",
+ .size = BAMBOO_SMALL_FLASH_SIZE,
+ .bankwidth = 1,
+};
+
+static struct map_info bamboo_large_map = {
+ .name = "Bamboo large flash",
+ .size = BAMBOO_LARGE_FLASH_SIZE,
+ .bankwidth = 2,
+};
+
+static struct map_info bamboo_sram_map = {
+ .name = "Bamboo SRAM",
+ .size = BAMBOO_SRAM_SIZE,
+ .bankwidth = 2,
+};
+
+static struct mtd_partition bamboo_small_partitions[] = {
+ {
+ .name = "pibs",
+ .offset = 0x0,
+ .size = 0x100000,
+ .mask_flags = MTD_WRITEABLE,
+ }
+};
+
+static struct mtd_partition bamboo_large_partitions[] = {
+ {
+ .name = "filesystem",
+ .offset = 0x0,
+ .size = 0x400000,
+ }
+};
+
+static struct mtd_partition bamboo_sram_partitions[] = {
+ {
+ .name = "sram",
+ .offset = 0x0,
+ .size = 0x100000,
+ }
+};
+
+int __init
+init_bamboo(void)
+{
+ u8 setting_reg;
+ u8 *setting_adr;
+ unsigned long small_flash_base, large_flash_base, sram_base;
+ unsigned long *gpio_base;
+
+ setting_adr = ioremap64(BAMBOO_FPGA_SETTING_REG_ADDR, 8);
+ if (!setting_adr)
+ return -ENOMEM;
+ setting_reg = readb(setting_adr);
+ iounmap(setting_adr);
+
+ /*
+ * Some versions of PIBS don't set up the GPIO controller
+ * for the devices on chip select 4 (large flash and sram).
+ */
+ gpio_base = ioremap64(0x0EF600B00ULL, 0x80);
+ if (!gpio_base) {
+ printk("Failed to ioremap GPIO\n");
+ return -ENOMEM;
+ }
+ * (gpio_base + 0x02) |= 0x00001000;
+ * (gpio_base + 0x04) |= 0x00001000;
+ iounmap((void *) gpio_base);
+
+ /*
+ * Use the values in the FPGA Setting Register to determine where
+ * each flash bank is located.
+ */
+ if (!BAMBOO_BOOT_NAND_FLASH(setting_reg)) {
+ if (BAMBOO_BOOT_SMALL_FLASH(setting_reg)) {
+ small_flash_base = BAMBOO_SMALL_FLASH_HIGH;
+ } else {
+ small_flash_base = BAMBOO_SMALL_FLASH_LOW;
+ }
+
+ bamboo_small_map.phys = small_flash_base;
+ bamboo_small_map.virt =
+ (ulong *) ioremap64(small_flash_base,
+ bamboo_small_map.size);
+ if (!bamboo_small_map.virt) {
+ printk("Failed to ioremap flash\n");
+ return -EIO;
+ }
+
+ simple_map_init(&bamboo_small_map);
+
+ small_flash = do_map_probe("map_rom", &bamboo_small_map);
+ if (small_flash) {
+ small_flash->owner = THIS_MODULE;
+ add_mtd_partitions(small_flash, bamboo_small_partitions,
+ ARRAY_SIZE(bamboo_small_partitions));
+ } else {
+ printk(KERN_INFO
+ "small flash disabled: Probe failed due to probable hardware issue\n");
+ iounmap((void *) bamboo_small_map.virt);
+ bamboo_small_map.virt = 0;
+ }
+ } else
+ bamboo_small_map.virt = 0;
+
+ /*
+ * Wiring to the large flash on the Rev 0 Bamboo is incorrect, so
+ * this should fail.
+ *
+ * This has been fixed on the Rev 1.
+ */
+ if (BAMBOO_BOOT_NAND_FLASH(setting_reg) ||
+ BAMBOO_BOOT_SMALL_FLASH(setting_reg))
+ large_flash_base = BAMBOO_LARGE_FLASH_LOW;
+ else if (BAMBOO_LARGE_FLASH_EN(setting_reg))
+ large_flash_base = BAMBOO_LARGE_FLASH_HIGH1;
+ else
+ large_flash_base = BAMBOO_LARGE_FLASH_HIGH2;
+ bamboo_large_map.phys = large_flash_base;
+ bamboo_large_map.virt = (ulong *) ioremap64(large_flash_base,
+ bamboo_large_map.size);
+ if (!bamboo_large_map.virt) {
+ printk("Failed to ioremap flash\n");
+ return -EIO;
+ }
+
+ simple_map_init(&bamboo_large_map);
+ large_flash = do_map_probe("cfi_probe", &bamboo_large_map);
+ if (large_flash) {
+ large_flash->owner = THIS_MODULE;
+ add_mtd_partitions(large_flash, bamboo_large_partitions,
+ ARRAY_SIZE(bamboo_large_partitions));
+ } else {
+ printk(KERN_INFO
+ "large flash disabled: Probe failed due to probable hardware issue\n");
+ iounmap((void *) bamboo_large_map.virt);
+ bamboo_large_map.virt = 0;
+ }
+
+ if (BAMBOO_BOOT_NAND_FLASH(setting_reg) ||
+ BAMBOO_BOOT_SMALL_FLASH(setting_reg))
+ sram_base = BAMBOO_SRAM_LOW;
+ else if (BAMBOO_LARGE_FLASH_EN(setting_reg))
+ sram_base = BAMBOO_SRAM_HIGH2;
+ else
+ sram_base = BAMBOO_SRAM_HIGH1;
+
+ bamboo_sram_map.phys = sram_base;
+ bamboo_sram_map.virt = (ulong *) ioremap64(sram_base,
+ bamboo_sram_map.size);
+ if (!bamboo_sram_map.virt) {
+ printk("Failed to ioremap flash \n");
+ return -EIO;
+ }
+
+ simple_map_init(&bamboo_sram_map);
+
+ sram = do_map_probe("map_ram", &bamboo_sram_map);
+ if (sram) {
+ sram->owner = THIS_MODULE;
+ sram->erasesize = 0x10;
+ add_mtd_partitions(sram, bamboo_sram_partitions,
+ ARRAY_SIZE(bamboo_sram_partitions));
+ } else {
+ printk(KERN_INFO
+ "sram disabled: Probe failed due to probable hardware issue\n");
+ iounmap((void *) bamboo_sram_map.virt);
+ bamboo_sram_map.virt = 0;
+ }
+
+ if (!(small_flash || large_flash || sram))
+ return -ENXIO;
+
+ return 0;
+}
+
+static void __exit
+cleanup_bamboo(void)
+{
+ if (small_flash) {
+ del_mtd_partitions(small_flash);
+ map_destroy(small_flash);
+ }
+
+ if (large_flash) {
+ del_mtd_partitions(large_flash);
+ map_destroy(large_flash);
+ }
+
+ if (sram) {
+ del_mtd_partitions(sram);
+ map_destroy(sram);
+ }
+
+ if (bamboo_small_map.virt) {
+ iounmap((void *) bamboo_small_map.virt);
+ bamboo_small_map.virt = 0;
+ }
+
+ if (bamboo_large_map.virt) {
+ iounmap((void *) bamboo_large_map.virt);
+ bamboo_large_map.virt = 0;
+ }
+
+ if (bamboo_sram_map.virt) {
+ iounmap((void *) bamboo_sram_map.virt);
+ bamboo_sram_map.virt = 0;
+ }
+}
+
+module_init(init_bamboo);
+module_exit(cleanup_bamboo);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Wade Farnsworth <wfarnsworth@mvista.com>");
+MODULE_DESCRIPTION("MTD map and partitions for IBM 440EP Bamboo boards");
diff -uprN linux-2.5-orig/drivers/mtd/nand/Kconfig linux-2.5-440ep/drivers/mtd/nand/Kconfig
--- linux-2.5-orig/drivers/mtd/nand/Kconfig 2005-04-05 15:31:12.000000000 -0700
+++ linux-2.5-440ep/drivers/mtd/nand/Kconfig 2005-04-05 15:37:07.000000000 -0700
@@ -122,6 +122,13 @@ config MTD_NAND_S3C2410_HWECC
currently not be able to switch to software, as there is no
implementation for ECC method used by the S3C2410
+config MTD_NAND_BAMBOO
+ tristate "NAND flash support on IBM/AMCC 440EP Eval Board (Bamboo)"
+ depends on BAMBOO && MTD_NAND
+ help
+ This enables the NAND flash driver on the IBM/AMCC 440EP Eval Board
+ (Bamboo).
+
config MTD_NAND_DISKONCHIP
tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)"
depends on MTD_NAND && EXPERIMENTAL
diff -uprN linux-2.5-orig/drivers/mtd/nand/Makefile linux-2.5-440ep/drivers/mtd/nand/Makefile
--- linux-2.5-orig/drivers/mtd/nand/Makefile 2005-04-05 15:31:12.000000000 -0700
+++ linux-2.5-440ep/drivers/mtd/nand/Makefile 2005-04-05 15:37:08.000000000 -0700
@@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_NAND_TX4938NDFMC) += tx
obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB) += ppchameleonevb.o
obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
+obj-$(CONFIG_MTD_NAND_BAMBOO) += bamboo_nand.o
obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
obj-$(CONFIG_MTD_NAND_H1900) += h1910.o
obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o
diff -uprN linux-2.5-orig/drivers/mtd/nand/bamboo_nand.c linux-2.5-440ep/drivers/mtd/nand/bamboo_nand.c
--- linux-2.5-orig/drivers/mtd/nand/bamboo_nand.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.5-440ep/drivers/mtd/nand/bamboo_nand.c 2005-04-06 09:11:52.000000000 -0700
@@ -0,0 +1,467 @@
+/*
+ * drivers/mtd/bamboo_nand.c
+ *
+ * Overview:
+ * This is a device driver for the NAND flash devices found on the
+ * IBM 440EP Evaluation Board (Bamboo).
+ *
+ * Author: Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/config.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <asm/io.h>
+#include <asm/ibm44x.h>
+#include <platforms/4xx/bamboo.h>
+
+struct ppc440ep_ndfc_regs {
+ uint cmd;
+ uint addr;
+ uint data;
+ uint reserved1;
+ uint ecc0;
+ uint ecc1;
+ uint ecc2;
+ uint ecc3;
+ uint ecc4;
+ uint ecc5;
+ uint ecc6;
+ uint ecc7;
+ uint b0cr;
+ uint b1cr;
+ uint b2cr;
+ uint b3cr;
+ uint cr;
+ uint sr;
+ uint hwctl;
+ uint reserved2;
+ uint revid;
+};
+
+static struct mtd_info *bamboo_nand0_mtd;
+static struct mtd_info *bamboo_nand1_mtd;
+static u8 hwctl;
+static struct ppc440ep_ndfc_regs *bamboo_ndfc;
+
+#define NAND0_NUM_PARTITIONS 1
+static struct mtd_partition nand0_partition_info[] = {
+ {
+ .name = "filesystem",
+ .offset = 0x0,
+ .size = 0x4000000,
+ },
+};
+
+#define NAND1_NUM_PARTITIONS 1
+static struct mtd_partition nand1_partition_info[] = {
+ {
+ .name = "filesystem",
+ .offset = 0x0,
+ .size = 0x10000000,
+ }
+};
+
+/*
+ * The 440EP has a NAND Flash Controller (NDFC) that handles all accesses to
+ * the NAND devices. The NDFC has command, address and data registers that
+ * when accessed will set up the NAND flash pins appropriately. We'll use the
+ * hwcontrol function to save the configuration in a global variable.
+ * We can then use this information in the read and write functions to
+ * determine which NDFC register to access. For the NCE commands, we'll just
+ * set or clear the Bank Enable bit in the NDFC Bank Config registers.
+ *
+ * There are 2 NAND devices on the board, a Samsung K9F1208U0A (64 MB) and a
+ * Samsung K9K2G08U0M (256 MB).
+ */
+static void
+bamboo_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ switch (cmd) {
+ case NAND_CTL_SETCLE:
+ hwctl |= 0x1;
+ break;
+ case NAND_CTL_CLRCLE:
+ hwctl &= ~0x1;
+ break;
+ case NAND_CTL_SETALE:
+ hwctl |= 0x2;
+ break;
+ case NAND_CTL_CLRALE:
+ hwctl &= ~0x2;
+ break;
+ }
+}
+
+static void
+bamboo_nand0_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ switch(cmd) {
+ case NAND_CTL_SETNCE:
+ bamboo_ndfc->b1cr |= 0x80000000;
+ break;
+ case NAND_CTL_CLRNCE:
+ bamboo_ndfc->b1cr &= ~0x80000000;
+ break;
+ default:
+ bamboo_hwcontrol(mtd, cmd);
+ }
+}
+
+static void
+bamboo_nand1_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ switch(cmd) {
+ case NAND_CTL_SETNCE:
+ bamboo_ndfc->b2cr |= 0x80000000;
+ break;
+ case NAND_CTL_CLRNCE:
+ bamboo_ndfc->b2cr &= ~0x80000000;
+ break;
+ default:
+ bamboo_hwcontrol(mtd, cmd);
+ }
+}
+
+static void
+bamboo_nand0_enable(void)
+{
+ bamboo_ndfc->cr = 0x01001000;
+}
+
+static void
+bamboo_nand1_enable(void)
+{
+ bamboo_ndfc->cr = 0x02003000;
+}
+
+static void
+bamboo_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ if (hwctl & 0x1)
+ writeb(byte, &(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ writeb(byte, &(bamboo_ndfc->addr));
+ else
+ writeb(byte, &(bamboo_ndfc->data));
+}
+
+static void
+bamboo_nand0_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ bamboo_nand0_enable();
+ bamboo_write_byte(mtd, byte);
+}
+
+static void
+bamboo_nand1_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ bamboo_nand1_enable();
+ bamboo_write_byte(mtd,byte);
+}
+
+static u_char
+bamboo_read_byte(struct mtd_info *mtd)
+{
+ u_char retval;
+ if (hwctl & 0x1)
+ retval = readb(&(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ retval = readb(&(bamboo_ndfc->addr));
+ else
+ retval = readb(&(bamboo_ndfc->data));
+ return retval;
+}
+
+static u_char
+bamboo_nand0_read_byte(struct mtd_info *mtd)
+{
+ bamboo_nand0_enable();
+ return bamboo_read_byte(mtd);
+}
+
+static u_char
+bamboo_nand1_read_byte(struct mtd_info *mtd)
+{
+ bamboo_nand1_enable();
+ return bamboo_read_byte(mtd);
+}
+
+static void
+bamboo_nand_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ int i;
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1)
+ writeb(buf[i], &(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ writeb(buf[i], &(bamboo_ndfc->addr));
+ else
+ writeb(buf[i], &(bamboo_ndfc->data));
+ }
+}
+
+static void
+bamboo_nand0_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ bamboo_nand0_enable();
+ bamboo_nand_write_buf(mtd, buf, len);
+}
+
+static void
+bamboo_nand1_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ bamboo_nand1_enable();
+ bamboo_nand_write_buf(mtd, buf, len);
+}
+
+static void
+bamboo_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1)
+ buf[i] = readb(&(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ buf[i] = readb(&(bamboo_ndfc->addr));
+ else
+ buf[i] = readb(&(bamboo_ndfc->data));
+ }
+}
+
+static void
+bamboo_nand0_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+ bamboo_nand0_enable();
+ bamboo_nand_read_buf(mtd, buf, len);
+}
+
+static void
+bamboo_nand1_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+ bamboo_nand1_enable();
+ bamboo_nand_read_buf(mtd, buf, len);
+}
+
+static int
+bamboo_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1) {
+ if (buf[i] != readb(&(bamboo_ndfc->cmd)))
+ return i;
+ } else if (hwctl & 0x2) {
+ if (buf[i] != readb(&(bamboo_ndfc->addr)))
+ return i;
+ } else {
+ if (buf[i] != readb(&(bamboo_ndfc->data)))
+ return i;
+ }
+
+ }
+
+ return 0;
+}
+
+static int
+bamboo_nand0_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ bamboo_nand0_enable();
+ return bamboo_nand_verify_buf(mtd, buf, len);
+}
+
+static int
+bamboo_nand1_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ bamboo_nand1_enable();
+ return bamboo_nand_verify_buf(mtd, buf, len);
+}
+
+static int
+bamboo_dev_ready(struct mtd_info *mtd)
+{
+ return ((bamboo_ndfc->sr) & 0x01000000) ? 1 : 0;
+}
+
+int __init
+bamboo_init(void)
+{
+ struct nand_chip *this;
+ uint * selection1_base, * gpio_base;
+ u8 selection1_val;
+ int err = 0;
+
+ hwctl = 0;
+
+ /*
+ * Bank 0 was set up by the firmware already. Bank 1 wasn't, so set it
+ * up now.
+ */
+
+ selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 8);
+ if(!selection1_base){
+ printk("Ioremap to access FPGA Selection Register 1 failed \n");
+ err = -EIO;
+ goto out;
+ }
+ selection1_val = readb(selection1_base);
+ selection1_val |= 0x02;
+ writeb(selection1_val, selection1_base);
+ iounmap((void *)(selection1_base));
+
+ SDR_WRITE(DCRN_SDR_CUST0, SDR_READ(DCRN_SDR_CUST0) | 0x2);
+
+ gpio_base = ioremap64(0x0EF600B00ULL, 0x80);
+ if(!gpio_base) {
+ printk("Ioremap to access GPIO Registers failed \n");
+ err = -EIO;
+ goto out;
+ }
+ *(uint *) (gpio_base + 0x2) |= 0x00010000;
+ *(uint *) (gpio_base + 0x4) |= 0x00010000;
+ iounmap((void *) gpio_base);
+
+ bamboo_nand0_mtd = kmalloc(sizeof(struct mtd_info) +
+ sizeof(struct nand_chip),
+ GFP_KERNEL);
+
+ bamboo_nand1_mtd = kmalloc(sizeof (struct mtd_info) +
+ sizeof (struct nand_chip),
+ GFP_KERNEL);
+ if (!bamboo_nand1_mtd) {
+ printk("Unable to allocate NAND 1 MTD device structure.\n");
+ err = -ENOMEM;
+ goto out_mtd0;
+ }
+
+ bamboo_ndfc = ioremap64(BAMBOO_NAND_FLASH_REG_ADDR,
+ BAMBOO_NAND_FLASH_REG_SIZE);
+ if (!bamboo_ndfc) {
+ printk("Ioremap to access NDFC Registers failed \n");
+ err = -EIO;
+ goto out_mtd1;
+ }
+ bamboo_ndfc->b2cr = 0xC0007777;
+
+ /* Initialize structures */
+ memset((char *) bamboo_nand0_mtd, 0,
+ sizeof (struct mtd_info) + sizeof (struct nand_chip));
+
+ memset((char *) bamboo_nand1_mtd, 0,
+ sizeof (struct mtd_info) + sizeof (struct nand_chip));
+
+ /* Get pointer to private data */
+ this = (struct nand_chip *) (&bamboo_nand0_mtd[1]);
+ /* Link the private data with the MTD structure */
+ bamboo_nand0_mtd->priv = this;
+
+ /* Set address of NAND IO lines (Using Linear Data Access Region) */
+ this->IO_ADDR_R = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ this->IO_ADDR_W = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ /* Reference hardware control function */
+ this->hwcontrol = bamboo_nand0_hwcontrol;
+ /* Set command delay time */
+ this->chip_delay = 12;
+ this->eccmode = NAND_ECC_SOFT;
+ this->write_byte = bamboo_nand0_write_byte;
+ this->read_byte = bamboo_nand0_read_byte;
+ this->write_buf = bamboo_nand0_write_buf;
+ this->read_buf = bamboo_nand0_read_buf;
+ this->verify_buf = bamboo_nand0_verify_buf;
+ this->dev_ready = bamboo_dev_ready;
+
+ /* Scan to find existance of the device */
+ if (nand_scan(bamboo_nand0_mtd, 1)) {
+ err = -ENXIO;
+ goto out_ior;
+ }
+
+ /* Get pointer to private data */
+ this = (struct nand_chip *) (&bamboo_nand1_mtd[1]);
+ /* Link the private data with the MTD structure */
+ bamboo_nand1_mtd->priv = this;
+
+ /* Set address of NAND IO lines (Using Linear Data Access Region) */
+ this->IO_ADDR_R = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ this->IO_ADDR_W = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ /* Reference hardware control function */
+ this->hwcontrol = bamboo_nand1_hwcontrol;
+ /* Set command delay time */
+ this->chip_delay = 25;
+ this->eccmode = NAND_ECC_SOFT;
+ this->write_byte = bamboo_nand1_write_byte;
+ this->read_byte = bamboo_nand1_read_byte;
+ this->write_buf = bamboo_nand1_write_buf;
+ this->read_buf = bamboo_nand1_read_buf;
+ this->verify_buf = bamboo_nand1_verify_buf;
+ this->dev_ready = NULL;
+
+ /* Scan to find existance of the device */
+ if (nand_scan(bamboo_nand1_mtd, 1)) {
+ err = -ENXIO;
+ goto out_ior;
+ }
+
+
+ add_mtd_partitions(bamboo_nand0_mtd, nand0_partition_info,
+ NAND0_NUM_PARTITIONS);
+
+ add_mtd_partitions(bamboo_nand1_mtd, nand1_partition_info,
+ NAND1_NUM_PARTITIONS);
+ goto out;
+
+out_ior:
+ iounmap((void *)bamboo_ndfc);
+out_mtd1:
+ kfree(bamboo_nand1_mtd);
+out_mtd0:
+ kfree(bamboo_nand0_mtd);
+out:
+ return err;
+}
+
+static void __exit
+bamboo_cleanup(void)
+{
+ /* Unregister partitions */
+ del_mtd_partitions(bamboo_nand0_mtd);
+ del_mtd_partitions(bamboo_nand1_mtd);
+
+ /* Release resources, unregister device */
+ del_mtd_device(bamboo_nand0_mtd);
+ del_mtd_device(bamboo_nand1_mtd);
+
+ /* unmap physical address */
+ iounmap((void *) bamboo_ndfc);
+
+ /* Free the MTD device structure */
+ kfree(bamboo_nand0_mtd);
+ kfree(bamboo_nand1_mtd);
+}
+
+module_init(bamboo_init);
+module_exit(bamboo_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Wade Farnsworth <wfarnsworth@mvista.com>");
+MODULE_DESCRIPTION
+ ("Board-specific glue layer for NAND flash on IBM 440EP eval board");
^ permalink raw reply
* Re: [PATCH 1/3] PPC440EP: IBM EMAC support for the Bamboo board
From: Wade Farnsworth @ 2005-04-06 17:31 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <1112808085.24527.296.camel@rhino.az.mvista.com>
[-- Attachment #1: Type: text/plain, Size: 414 bytes --]
This adds support for the Bamboo board in the EMAC driver.
Jason McMullan pointed out to me that for the Bamboo Rev. 0 to boot from
ethernet, the ANEG pin on SW2 needs to be turned off. If we use this,
we can avoid using the PVR to determine which board rev, we're running
on. This patch addresses this.
Comments would be appreciated.
-Wade Farnsworth
Signed-off by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: ibm440ep-ibm_emac.patch --]
[-- Type: text/x-patch, Size: 2782 bytes --]
diff -uprN linux-2.5-orig/drivers/net/ibm_emac/ibm_emac_phy.c linux-2.5-440ep/drivers/net/ibm_emac/ibm_emac_phy.c
--- linux-2.5-orig/drivers/net/ibm_emac/ibm_emac_phy.c 2005-04-05 15:31:14.000000000 -0700
+++ linux-2.5-440ep/drivers/net/ibm_emac/ibm_emac_phy.c 2005-04-05 15:36:58.000000000 -0700
@@ -24,6 +24,7 @@
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/delay.h>
+#include <linux/vmalloc.h>
#include "ibm_emac_phy.h"
@@ -78,6 +79,45 @@ static int cis8201_init(struct mii_phy *
return 0;
}
+#ifdef CONFIG_BAMBOO
+static int ac104_init(struct mii_phy *phy)
+{
+ /*
+ * SW2 on the Bamboo is used for ethernet configuration and is accessed
+ * via the CONFIG2 register in the FPGA. If the ANEG pin is set,
+ * overwrite the supported features with the settings in SW2.
+ */
+ u8 *config2_addr, config2_val;
+ config2_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 0x8);
+ config2_val = * config2_addr;
+ iounmap(*config2_addr);
+ if (BAMBOO_AUTONEGOTIATE(config2_val))
+ return 0;
+ phy->def->features = SUPPORTED_TP | SUPPORTED_MII;
+ if (BAMBOO_FORCE_100Mbps(config2_val)) {
+ phy->speed = SPEED_100;
+ if (BAMBOO_FULL_DUPLEX_EN(config2_val)) {
+ phy->def->features |= SUPPORTED_100baseT_Full;
+ phy->duplex = DUPLEX_FULL;
+ } else {
+ phy->def->features |= SUPPORTED_100baseT_Half;
+ phy->duplex = DUPLEX_HALF;
+ }
+ } else {
+ phy->speed = SPEED_10;
+ if (BAMBOO_FULL_DUPLEX_EN(config2_val)) {
+ phy->def->features |= SUPPORTED_10baseT_Full;
+ phy->duplex = DUPLEX_FULL;
+ } else {
+ phy->def->features |= SUPPORTED_10baseT_Half;
+ phy->duplex = DUPLEX_HALF;
+ }
+ }
+
+ return 0;
+}
+#endif
+
static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
{
u16 ctl, adv;
@@ -226,6 +266,17 @@ static struct mii_phy_ops cis8201_phy_op
read_link:cis8201_read_link
};
+/* AC104 phy ops */
+static struct mii_phy_ops ac104_phy_ops = {
+#ifdef CONFIG_BAMBOO
+ init:ac104_init,
+#endif
+ setup_aneg:genmii_setup_aneg,
+ setup_forced:genmii_setup_forced,
+ poll_link:genmii_poll_link,
+ read_link:genmii_read_link
+};
+
/* Generic implementation for most 10/100 PHYs */
static struct mii_phy_ops generic_phy_ops = {
setup_aneg:genmii_setup_aneg,
@@ -243,6 +294,15 @@ static struct mii_phy_def cis8201_phy_de
ops:&cis8201_phy_ops
};
+static struct mii_phy_def ac104_phy_def = {
+ phy_id:0x00225540,
+ phy_id_mask:0x00fffff0,
+ name:"AC104 Ethernet",
+ features:MII_BASIC_FEATURES,
+ magic_aneg:0,
+ ops:&ac104_phy_ops
+};
+
static struct mii_phy_def genmii_phy_def = {
phy_id:0x00000000,
phy_id_mask:0x00000000,
@@ -254,6 +314,7 @@ static struct mii_phy_def genmii_phy_def
static struct mii_phy_def *mii_phy_table[] = {
&cis8201_phy_def,
+ &ac104_phy_def,
&genmii_phy_def,
NULL
};
^ permalink raw reply
* [PATCH 1/3] PPC440EP SoC and Bamboo board support
From: Wade Farnsworth @ 2005-04-06 17:21 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 170 bytes --]
Hi all,
This patch adds support for the IBM/AMCC PPC440EP SoC and the Bamboo
reference board.
-Wade Farnsworth
Signed-off by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: ibm440ep-ppc.patch --]
[-- Type: text/x-patch, Size: 61322 bytes --]
diff -uprN linux-2.5-orig/arch/ppc/boot/simple/Makefile linux-2.5-440ep/arch/ppc/boot/simple/Makefile
--- linux-2.5-orig/arch/ppc/boot/simple/Makefile 2005-04-05 15:30:46.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/boot/simple/Makefile 2005-04-05 15:36:19.000000000 -0700
@@ -61,6 +61,12 @@ zimageinitrd-$(CONFIG_IBM_OPENBIOS) := z
end-$(CONFIG_EMBEDDEDBOOT) := embedded
misc-$(CONFIG_EMBEDDEDBOOT) := misc-embedded.o
+ zimage-$(CONFIG_BAMBOO) := zImage-TREE
+zimageinitrd-$(CONFIG_BAMBOO) := zImage.initrd-TREE
+ end-$(CONFIG_BAMBOO) := bamboo
+ entrypoint-$(CONFIG_BAMBOO) := 0x01000000
+ extra.o-$(CONFIG_BAMBOO) := pibs.o
+
zimage-$(CONFIG_EBONY) := zImage-TREE
zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE
end-$(CONFIG_EBONY) := ebony
diff -uprN linux-2.5-orig/arch/ppc/boot/simple/pibs.c linux-2.5-440ep/arch/ppc/boot/simple/pibs.c
--- linux-2.5-orig/arch/ppc/boot/simple/pibs.c 2005-04-05 15:30:46.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/boot/simple/pibs.c 2005-04-05 15:36:20.000000000 -0700
@@ -91,9 +91,11 @@ load_kernel(unsigned long load_addr, int
mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16);
memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6);
-#ifdef CONFIG_440GX
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP)
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16);
memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6);
+#endif
+#ifdef CONFIG_440GX
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16);
memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6);
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16);
diff -uprN linux-2.5-orig/arch/ppc/configs/bamboo_defconfig linux-2.5-440ep/arch/ppc/configs/bamboo_defconfig
--- linux-2.5-orig/arch/ppc/configs/bamboo_defconfig 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/configs/bamboo_defconfig 2005-04-05 15:36:20.000000000 -0700
@@ -0,0 +1,910 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.11-rc5
+# Wed Mar 2 16:46:31 2005
+#
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Processor
+#
+# CONFIG_6xx is not set
+# CONFIG_40x is not set
+CONFIG_44x=y
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+# CONFIG_8xx is not set
+# CONFIG_E500 is not set
+CONFIG_BOOKE=y
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_4xx=y
+
+#
+# IBM 4xx options
+#
+# CONFIG_EBONY is not set
+# CONFIG_LUAN is not set
+# CONFIG_OCOTEA is not set
+CONFIG_BAMBOO=y
+CONFIG_440EP=y
+CONFIG_PPC_FPU=y
+CONFIG_IBM440EP_ERR42=y
+CONFIG_IBM_OCP=y
+# CONFIG_PPC4xx_DMA is not set
+CONFIG_PPC_GEN550=y
+# CONFIG_PM is not set
+CONFIG_NOT_COHERENT_CACHE=y
+
+#
+# Platform options
+#
+# CONFIG_PC_KEYBOARD is not set
+# CONFIG_SMP is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="ip=on"
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCI_LEGACY_PROC is not set
+# CONFIG_PCI_NAMES is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x01000000
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+# CONFIG_IDEDMA_PCI_AUTO is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+CONFIG_BLK_DEV_CMD64X=y
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+# CONFIG_BLK_DEV_SD is not set
+CONFIG_CHR_DEV_ST=y
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+CONFIG_SCSI_QLA2XXX=y
+# CONFIG_SCSI_QLA21XX is not set
+# CONFIG_SCSI_QLA22XX is not set
+# CONFIG_SCSI_QLA2300 is not set
+# CONFIG_SCSI_QLA2322 is not set
+# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_CONNTRACK_MARK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_EMAC=y
+# CONFIG_IBM_EMAC_ERRMSG is not set
+CONFIG_IBM_EMAC_RXB=128
+CONFIG_IBM_EMAC_TXB=128
+CONFIG_IBM_EMAC_FGAP=8
+CONFIG_IBM_EMAC_SKBRES=0
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=y
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+CONFIG_NATSEMI=y
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+# CONFIG_E1000_NAPI is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_BLUETOOTH_TTY is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_STORAGE is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_EGALAX is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB Multimedia devices
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+CONFIG_USB_PEGASUS=y
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGETKIT is not set
+# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_IDMOUSE is not set
+
+#
+# USB ATM/DSL drivers
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_FS is not set
+# CONFIG_KGDB is not set
+# CONFIG_XMON is not set
+CONFIG_BDI_SWITCH=y
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+CONFIG_PPC_OCP=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
diff -uprN linux-2.5-orig/arch/ppc/kernel/cputable.c linux-2.5-440ep/arch/ppc/kernel/cputable.c
--- linux-2.5-orig/arch/ppc/kernel/cputable.c 2005-04-05 15:30:46.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/kernel/cputable.c 2005-04-05 15:36:21.000000000 -0700
@@ -841,6 +841,26 @@ struct cpu_spec cpu_specs[] = {
#endif /* CONFIG_40x */
#ifdef CONFIG_44x
+ { /* 440EP Rev. A */
+ .pvr_mask = 0xf0000fff,
+ .pvr_value = 0x40000850,
+ .cpu_name = "440EP Rev. A",
+ .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB,
+ .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ },
+ { /* 440EP Rev. B */
+ .pvr_mask = 0xf0000fff,
+ .pvr_value = 0x400008d3,
+ .cpu_name = "440EP Rev. B",
+ .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB,
+ .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ },
{ /* 440GP Rev. B */
.pvr_mask = 0xf0000fff,
.pvr_value = 0x40000440,
diff -uprN linux-2.5-orig/arch/ppc/kernel/entry.S linux-2.5-440ep/arch/ppc/kernel/entry.S
--- linux-2.5-orig/arch/ppc/kernel/entry.S 2005-04-05 15:30:46.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/kernel/entry.S 2005-04-05 15:36:22.000000000 -0700
@@ -213,6 +213,7 @@ syscall_dotrace_cont:
lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
mtlr r10
addi r9,r1,STACK_FRAME_OVERHEAD
+ PPC440EP_ERR42
blrl /* Call handler */
.globl ret_from_syscall
ret_from_syscall:
diff -uprN linux-2.5-orig/arch/ppc/kernel/head_44x.S linux-2.5-440ep/arch/ppc/kernel/head_44x.S
--- linux-2.5-orig/arch/ppc/kernel/head_44x.S 2005-04-05 15:30:46.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/kernel/head_44x.S 2005-04-05 15:36:23.000000000 -0700
@@ -228,6 +228,16 @@ skpinv: addi r4,r4,1 /* Increment */
lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
mtspr SPRN_IVPR,r4
+#ifdef CONFIG_440_FPU
+ /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */
+ mfspr r2,SPRN_CCR0
+ lis r3,0xffef
+ ori r3,r3,0xffff
+ and r2,r2,r3
+ mtspr SPRN_CCR0,r2
+ isync
+#endif /* CONFIG_440_FPU */
+
/*
* This is where the main kernel code starts.
*/
@@ -426,7 +436,16 @@ interrupt_base:
PROGRAM_EXCEPTION
/* Floating Point Unavailable Interrupt */
+#ifdef CONFIG_440_FPU
+ /* FPU code from arch/ppc/kernel/head.S */
+ START_EXCEPTION(FloatingPointUnavailable)
+ NORMAL_EXCEPTION_PROLOG
+ bne load_up_fpu
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ EXC_XFER_EE_LITE(0x2010, KernelFP)
+#else
EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
+#endif /* CONFIG_440_FPU */
/* System Call Interrupt */
START_EXCEPTION(SystemCall)
@@ -669,6 +688,85 @@ finish_tlb_load:
mfspr r10, SPRN_SPRG0
rfi /* Force context change */
+#ifdef CONFIG_440_FPU
+/*
+ * This task wants to use the FPU now.
+ * On UP, disable FP for the task which had the FPU previously,
+ * and save its floating-point registers in its thread_struct.
+ * Load up this task's FP registers from its thread_struct,
+ * enable the FPU for the current task and return to the task.
+ */
+load_up_fpu:
+ mfmsr r5
+ ori r5,r5,MSR_FP
+ sync
+ mtmsr r5 /* enable use of fpu now */
+ isync
+
+ addi r6,0,0
+ addis r3,r6,last_task_used_math@ha
+ lwz r4,last_task_used_math@l(r3)
+ cmpwi 0,r4,0
+ beq 1f
+ add r4,r4,r6
+ addi r4,r4,THREAD /* want last_task_used_math->thread */
+ SAVE_32FPRS(0, r4)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r4)
+ lwz r5,PT_REGS(r4)
+ add r5,r5,r6
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r10,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r10 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+ /* enable use of FP after return */
+ mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
+ lwz r4,THREAD_FPEXC_MODE(r5)
+ ori r9,r9,MSR_FP /* enable FP for current */
+ or r9,r9,r4
+ lfd fr0,THREAD_FPSCR-4(r5)
+ mtfsf 0xff,fr0
+ REST_32FPRS(0, r5)
+ subi r4,r5,THREAD
+ sub r4,r4,r6
+ stw r4,last_task_used_math@l(r3)
+
+ /* restore registers and return */
+ /* we haven't used ctr or xer or lr */
+ REST_4GPRS(3, r11)
+ lwz r10,_CCR(r11)
+ REST_GPR(1, r11)
+ mtcrf 0xff,r10
+ lwz r10,_LINK(r11)
+ mtlr r10
+ REST_GPR(10, r11)
+ mtspr SPRN_SRR1,r9
+ mtspr SPRN_SRR0,r12
+ REST_GPR(9, r11)
+ REST_GPR(12, r11)
+ lwz r11,GPR11(r11)
+ sync
+ rfi
+
+/*
+ * FP unavailable trap from kernel - print a message, but let
+ * the task use FP in the kernel until it returns to user mode.
+ */
+KernelFP:
+ lwz r3,_MSR(r1)
+ ori r3,r3,MSR_FP
+ stw r3,_MSR(r1) /* enable use of FP after return */
+ lis r3,86f@h
+ ori r3,r3,86f@l
+ mr r4,r2 /* current */
+ lwz r5,_NIP(r1)
+ bl printk
+ b ret_from_except
+86: .string "floating point used in kernel (task=%p, pc=%x)\n"
+ .align 4,0
+#endif /* CONFIG_440_FPU */
+
/*
* Global functions
*/
@@ -684,10 +782,37 @@ _GLOBAL(giveup_altivec)
/*
* extern void giveup_fpu(struct task_struct *prev)
*
- * The 44x core does not have an FPU.
+ * Disable FP for the task given as the argument,
+ * and save the floating-point registers in its thread_struct.
+ * Enables the FPU for use in the kernel on return.
*/
_GLOBAL(giveup_fpu)
+#ifdef CONFIG_440_FPU
+ mfmsr r5
+ ori r5,r5,MSR_FP
+ mtmsr r5 /* enable use of fpu now */
+ isync
+ cmpwi 0,r3,0
+ beqlr- /* if no previous owner, done */
+ addi r3,r3,THREAD /* want THREAD of task */
+ lwz r5,PT_REGS(r3)
+ cmpwi 0,r5,0
+ SAVE_32FPRS(0, r3)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r3)
+ beq 1f
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r3,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r3 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+ li r5,0
+ lis r4,last_task_used_math@ha
+ stw r5,last_task_used_math@l(r4)
+ blr
+#else
blr
+#endif /* CONFIG_440_FPU */
/*
* extern void abort(void)
diff -uprN linux-2.5-orig/arch/ppc/kernel/misc.S linux-2.5-440ep/arch/ppc/kernel/misc.S
--- linux-2.5-orig/arch/ppc/kernel/misc.S 2005-04-05 15:30:46.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/kernel/misc.S 2005-04-05 15:36:23.000000000 -0700
@@ -1147,6 +1147,7 @@ _GLOBAL(kernel_thread)
stwu r0,-16(r1)
mtlr r30 /* fn addr in lr */
mr r3,r31 /* load arg and call fn */
+ PPC440EP_ERR42
blrl
li r0,__NR_exit /* exit if function returns */
li r3,0
Binary files linux-2.5-orig/arch/ppc/platforms/4xx/.bamboo.h.swp and linux-2.5-440ep/arch/ppc/platforms/4xx/.bamboo.h.swp differ
diff -uprN linux-2.5-orig/arch/ppc/platforms/4xx/Kconfig linux-2.5-440ep/arch/ppc/platforms/4xx/Kconfig
--- linux-2.5-orig/arch/ppc/platforms/4xx/Kconfig 2005-04-05 15:30:47.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/platforms/4xx/Kconfig 2005-04-05 15:36:24.000000000 -0700
@@ -83,6 +83,11 @@ config OCOTEA
help
This option enables support for the IBM PPC440GX evaluation board.
+config BAMBOO
+ bool "Bamboo"
+ help
+ This option enables support for the IBM PPC440EP evaluation board.
+
endchoice
config EP405PC
@@ -113,6 +118,11 @@ config 440SP
depends on LUAN
default y
+config 440EP
+ bool
+ depends on BAMBOO
+ default y
+
config 440
bool
depends on 440GP || 440SP
@@ -123,6 +133,16 @@ config 440A
depends on 440GX
default y
+config 440_FPU
+ bool
+ depends on 440EP
+ default y
+
+config IBM440EP_ERR42
+ bool
+ depends on 440EP
+ default y
+
# All 405-based cores up until the 405GPR and 405EP have this errata.
config IBM405_ERR77
bool
@@ -142,7 +162,7 @@ config BOOKE
config IBM_OCP
bool
- depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
+ depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT || BAMBOO
default y
config XILINX_OCP
diff -uprN linux-2.5-orig/arch/ppc/platforms/4xx/Makefile linux-2.5-440ep/arch/ppc/platforms/4xx/Makefile
--- linux-2.5-orig/arch/ppc/platforms/4xx/Makefile 2005-04-05 15:30:47.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/platforms/4xx/Makefile 2005-04-05 15:36:25.000000000 -0700
@@ -2,6 +2,7 @@
# Makefile for the PowerPC 4xx linux kernel.
obj-$(CONFIG_ASH) += ash.o
+obj-$(CONFIG_BAMBOO) += bamboo.o
obj-$(CONFIG_CPCI405) += cpci405.o
obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_EP405) += ep405.o
@@ -22,6 +23,7 @@ obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
obj-$(CONFIG_440GP) += ibm440gp.o
obj-$(CONFIG_440GX) += ibm440gx.o
obj-$(CONFIG_440SP) += ibm440sp.o
+obj-$(CONFIG_440EP) += ibm440ep.o
obj-$(CONFIG_405EP) += ibm405ep.o
obj-$(CONFIG_405GPR) += ibm405gpr.o
obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o
diff -uprN linux-2.5-orig/arch/ppc/platforms/4xx/bamboo.c linux-2.5-440ep/arch/ppc/platforms/4xx/bamboo.c
--- linux-2.5-orig/arch/ppc/platforms/4xx/bamboo.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/platforms/4xx/bamboo.c 2005-04-05 15:36:25.000000000 -0700
@@ -0,0 +1,435 @@
+/*
+ * arch/ppc/platforms/4xx/bamboo.c
+ *
+ * Bamboo board specific routines
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/major.h>
+#include <linux/blkdev.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/initrd.h>
+#include <linux/irq.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/ethtool.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ocp.h>
+#include <asm/pci-bridge.h>
+#include <asm/time.h>
+#include <asm/todc.h>
+#include <asm/bootinfo.h>
+#include <asm/ppc4xx_pic.h>
+#include <asm/ppcboot.h>
+
+#include <syslib/gen550.h>
+#include <syslib/ibm440gx_common.h>
+
+/*
+ * This is a horrible kludge, we eventually need to abstract this
+ * generic PHY stuff, so the standard phy mode defines can be
+ * easily used from arch code.
+ */
+#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
+
+bd_t __res;
+
+static struct ibm44x_clocks clocks __initdata;
+
+/*
+ * Bamboo external IRQ triggering/polarity settings
+ */
+unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
+};
+
+static void __init
+bamboo_calibrate_decr(void)
+{
+ unsigned int freq;
+
+ if (mfspr(SPRN_CCR1) & CCR1_TCS)
+ freq = BAMBOO_TMRCLK;
+ else
+ freq = clocks.cpu;
+
+ ibm44x_calibrate_decr(freq);
+
+}
+
+static int
+bamboo_show_cpuinfo(struct seq_file *m)
+{
+ seq_printf(m, "vendor\t\t: IBM\n");
+ seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
+
+ return 0;
+}
+
+static inline int
+bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ { 28, 28, 28, 28 }, /* IDSEL 1 - PCI Slot 0 */
+ { 27, 27, 27, 27 }, /* IDSEL 2 - PCI Slot 1 */
+ { 26, 26, 26, 26 }, /* IDSEL 3 - PCI Slot 2 */
+ { 25, 25, 25, 25 }, /* IDSEL 4 - PCI Slot 3 */
+ };
+
+ const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void __init bamboo_set_emacdata(void)
+{
+ unsigned char * selection1_base;
+ struct ocp_def *def;
+ struct ocp_func_emac_data *emacdata;
+ u8 selection1_val;
+ int mode;
+
+ selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
+ selection1_val = readb(selection1_base);
+ iounmap((void *) selection1_base);
+ if (BAMBOO_SEL_MII(selection1_val))
+ mode = PHY_MODE_MII;
+ else if (BAMBOO_SEL_RMII(selection1_val))
+ mode = PHY_MODE_RMII;
+ else
+ mode = PHY_MODE_SMII;
+
+ /* Set mac_addr and phy mode for each EMAC */
+
+ def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
+ emacdata = def->additions;
+ memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
+ emacdata->phy_mode = mode;
+
+ def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
+ emacdata = def->additions;
+ memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
+ emacdata->phy_mode = mode;
+}
+
+static int
+bamboo_exclude_device(unsigned char bus, unsigned char devfn)
+{
+ return (bus == 0 && devfn == 0);
+}
+
+#define PCI_READW(offset) \
+ (readw((void *)((u32)pci_reg_base+offset)))
+
+#define PCI_WRITEW(value, offset) \
+ (writew(value, (void *)((u32)pci_reg_base+offset)))
+
+#define PCI_WRITEL(value, offset) \
+ (writel(value, (void *)((u32)pci_reg_base+offset)))
+
+static void __init
+bamboo_setup_pci(void)
+{
+ void *pci_reg_base;
+ unsigned long memory_size;
+ memory_size = ppc_md.find_end_of_memory();
+
+ pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
+
+ /* Enable PCI I/O, Mem, and Busmaster cycles */
+ PCI_WRITEW(PCI_READW(PCI_COMMAND) |
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER, PCI_COMMAND);
+
+ /* Disable region first */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
+
+ /* PLB starting addr: 0x00000000A0000000 */
+ PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
+
+ /* PCI start addr, 0xA0000000 (PCI Address) */
+ PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
+
+ /* Enable no pre-fetch, enable region */
+ PCI_WRITEL(((0xffffffff -
+ (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
+ BAMBOO_PCIL0_PMM0MA);
+
+ /* Disable region one */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
+
+ /* Disable region two */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
+
+ /* Now configure the PCI->PLB windows, we only use PTM1
+ *
+ * For Inbound flow, set the window size to all available memory
+ * This is required because if size is smaller,
+ * then Eth/PCI DD would fail as PCI card not able to access
+ * the memory allocated by DD.
+ */
+
+ PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS); /* disabled region 1 */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA); /* begin of address map */
+
+ memory_size = 1 << fls(memory_size - 1);
+
+ /* Size low + Enabled */
+ PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
+
+ eieio();
+ iounmap(pci_reg_base);
+}
+
+static void __init
+bamboo_setup_hose(void)
+{
+ unsigned int bar_response, bar;
+ struct pci_controller *hose;
+
+ bamboo_setup_pci();
+
+ hose = pcibios_alloc_controller();
+
+ if (!hose)
+ return;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
+
+ pci_init_resource(&hose->io_resource,
+ BAMBOO_PCI_LOWER_IO,
+ BAMBOO_PCI_UPPER_IO,
+ IORESOURCE_IO,
+ "PCI host bridge");
+
+ pci_init_resource(&hose->mem_resources[0],
+ BAMBOO_PCI_LOWER_MEM,
+ BAMBOO_PCI_UPPER_MEM,
+ IORESOURCE_MEM,
+ "PCI host bridge");
+
+ ppc_md.pci_exclude_device = bamboo_exclude_device;
+
+ hose->io_space.start = BAMBOO_PCI_LOWER_IO;
+ hose->io_space.end = BAMBOO_PCI_UPPER_IO;
+ hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
+ hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
+ isa_io_base =
+ (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
+ hose->io_base_virt = (void *)isa_io_base;
+
+ setup_indirect_pci(hose,
+ BAMBOO_PCI_CFGA_PLB32,
+ BAMBOO_PCI_CFGD_PLB32);
+ hose->set_cfg_type = 1;
+
+ /* Zero config bars */
+ for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
+ early_write_config_dword(hose, hose->first_busno,
+ PCI_FUNC(hose->first_busno), bar,
+ 0x00000000);
+ early_read_config_dword(hose, hose->first_busno,
+ PCI_FUNC(hose->first_busno), bar,
+ &bar_response);
+ }
+
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = bamboo_map_irq;
+}
+
+TODC_ALLOC();
+
+static void __init
+bamboo_early_serial_map(void)
+{
+ struct uart_port port;
+
+ /* Setup ioremapped serial port access */
+ memset(&port, 0, sizeof(port));
+ port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
+ port.irq = 0;
+ port.uartclk = clocks.uart0;
+ port.regshift = 0;
+ port.iotype = SERIAL_IO_MEM;
+ port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.line = 0;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 0 failed\n");
+ }
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+ /* Configure debug serial access */
+ gen550_init(0, &port);
+#endif
+
+ port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
+ port.irq = 1;
+ port.uartclk = clocks.uart1;
+ port.line = 1;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 1 failed\n");
+ }
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+ /* Configure debug serial access */
+ gen550_init(1, &port);
+#endif
+
+ port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
+ port.irq = 3;
+ port.uartclk = clocks.uart2;
+ port.line = 2;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 2 failed\n");
+ }
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+ /* Configure debug serial access */
+ gen550_init(2, &port);
+#endif
+
+ port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
+ port.irq = 4;
+ port.uartclk = clocks.uart3;
+ port.line = 3;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 3 failed\n");
+ }
+}
+
+static void __init
+bamboo_setup_arch(void)
+{
+
+ bamboo_set_emacdata();
+
+ /*
+ * Determine various clocks.
+ * To be completely correct we should get SysClk
+ * from FPGA, because it can be changed by on-board switches
+ * --ebs
+ */
+ ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+ ocp_sys_info.opb_bus_freq = clocks.opb;
+
+ /* Setup TODC access */
+ TODC_INIT(TODC_TYPE_DS1743,
+ 0,
+ 0,
+ ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
+ 8);
+
+ /* init to some ~sane value until calibrate_delay() runs */
+ loops_per_jiffy = 50000000/HZ;
+
+ /* Setup PCI host bridge */
+ bamboo_setup_hose();
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
+#endif
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_HDA1;
+#endif
+
+ bamboo_early_serial_map();
+
+ /* Identify the system */
+ printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
+}
+
+void __init platform_init(unsigned long r3, unsigned long r4,
+ unsigned long r5, unsigned long r6, unsigned long r7)
+{
+ parse_bootinfo(find_bootinfo());
+
+ /*
+ * If we were passed in a board information, copy it into the
+ * residual data area.
+ */
+ if (r3)
+ __res = *(bd_t *)(r3 + KERNELBASE);
+
+ ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+ ocp_sys_info.opb_bus_freq = clocks.opb;
+
+ ibm44x_platform_init();
+
+ ppc_md.setup_arch = bamboo_setup_arch;
+ ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
+ ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
+
+ ppc_md.calibrate_decr = bamboo_calibrate_decr;
+ ppc_md.time_init = todc_time_init;
+ ppc_md.set_rtc_time = todc_set_rtc_time;
+ ppc_md.get_rtc_time = todc_get_rtc_time;
+
+ ppc_md.nvram_read_val = todc_direct_read_val;
+ ppc_md.nvram_write_val = todc_direct_write_val;
+#ifdef CONFIG_KGDB
+ ppc_md.early_serial_map = bamboo_early_serial_map;
+#endif
+}
+
diff -uprN linux-2.5-orig/arch/ppc/platforms/4xx/bamboo.h linux-2.5-440ep/arch/ppc/platforms/4xx/bamboo.h
--- linux-2.5-orig/arch/ppc/platforms/4xx/bamboo.h 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/platforms/4xx/bamboo.h 2005-04-06 09:11:40.000000000 -0700
@@ -0,0 +1,136 @@
+/*
+ * arch/ppc/platforms/bamboo.h
+ *
+ * Bamboo board definitions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_BAMBOO_H__
+#define __ASM_BAMBOO_H__
+
+#include <linux/config.h>
+#include <platforms/4xx/ibm440ep.h>
+
+/* F/W TLB mapping used in bootloader glue to reset EMAC */
+#define PPC44x_EMAC0_MR0 0x0EF600E00
+
+/* Location of MAC addresses in PIBS image */
+#define PIBS_FLASH_BASE 0xfff00000
+#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xc0400)
+#define PIBS_MAC_SIZE 0x200
+#define PIBS_MAC_OFFSET 0x100
+
+/* Default clock rate */
+#define BAMBOO_TMRCLK 25000000
+
+/* RTC/NVRAM location */
+#define BAMBOO_RTC_ADDR 0x080000000ULL
+#define BAMBOO_RTC_SIZE 0x2000
+
+/* FPGA Registers */
+#define BAMBOO_FPGA_ADDR 0x080002000ULL
+
+#define BAMBOO_FPGA_CONFIG2_REG_ADDR (BAMBOO_FPGA_ADDR + 0x1)
+#define BAMBOO_FULL_DUPLEX_EN(x) (x & 0x08)
+#define BAMBOO_FORCE_100Mbps(x) (x & 0x04)
+#define BAMBOO_AUTONEGOTIATE(x) (x & 0x02)
+
+#define BAMBOO_FPGA_SETTING_REG_ADDR (BAMBOO_FPGA_ADDR + 0x3)
+#define BAMBOO_BOOT_SMALL_FLASH(x) (!(x & 0x80))
+#define BAMBOO_LARGE_FLASH_EN(x) (!(x & 0x40))
+#define BAMBOO_BOOT_NAND_FLASH(x) (!(x & 0x20))
+
+#define BAMBOO_FPGA_SELECTION1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x4)
+#define BAMBOO_SEL_MII(x) (x & 0x80)
+#define BAMBOO_SEL_RMII(x) (x & 0x40)
+#define BAMBOO_SEL_SMII(x) (x & 0x20)
+
+/* Flash */
+#define BAMBOO_SMALL_FLASH_LOW 0x087f00000ULL
+#define BAMBOO_SMALL_FLASH_HIGH 0x0fff00000ULL
+#define BAMBOO_SMALL_FLASH_SIZE 0x100000
+#define BAMBOO_LARGE_FLASH_LOW 0x087800000ULL
+#define BAMBOO_LARGE_FLASH_HIGH1 0x0ff800000ULL
+#define BAMBOO_LARGE_FLASH_HIGH2 0x0ffc00000ULL
+#define BAMBOO_LARGE_FLASH_SIZE 0x400000
+#define BAMBOO_SRAM_LOW 0x087f00000ULL
+#define BAMBOO_SRAM_HIGH1 0x0fff00000ULL
+#define BAMBOO_SRAM_HIGH2 0x0ff800000ULL
+#define BAMBOO_SRAM_SIZE 0x100000
+#define BAMBOO_NAND_FLASH_REG_ADDR 0x090000000ULL
+#define BAMBOO_NAND_FLASH_REG_SIZE 0x2000
+
+/*
+ * Serial port defines
+ */
+#define RS_TABLE_SIZE 4
+
+#define UART0_IO_BASE 0xEF600300
+#define UART1_IO_BASE 0xEF600400
+#define UART2_IO_BASE 0xEF600500
+#define UART3_IO_BASE 0xEF600600
+
+#define BASE_BAUD 33177600/3/16
+#define UART0_INT 0
+#define UART1_INT 1
+#define UART2_INT 3
+#define UART3_INT 4
+
+#define STD_UART_OP(num) \
+ { 0, BASE_BAUD, 0, UART##num##_INT, \
+ (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
+ iomem_base: UART##num##_IO_BASE, \
+ io_type: SERIAL_IO_MEM},
+
+#define SERIAL_PORT_DFNS \
+ STD_UART_OP(0) \
+ STD_UART_OP(1) \
+ STD_UART_OP(2) \
+ STD_UART_OP(3)
+
+/* PCI support */
+#define BAMBOO_PCI_CFGA_PLB32 0xeec00000
+#define BAMBOO_PCI_CFGD_PLB32 0xeec00004
+
+#define BAMBOO_PCI_IO_BASE 0x00000000e8000000ULL
+#define BAMBOO_PCI_IO_SIZE 0x00010000
+#define BAMBOO_PCI_MEM_OFFSET 0x00000000
+#define BAMBOO_PCI_PHY_MEM_BASE 0x00000000a0000000ULL
+
+#define BAMBOO_PCI_LOWER_IO 0x00000000
+#define BAMBOO_PCI_UPPER_IO 0x0000ffff
+#define BAMBOO_PCI_LOWER_MEM 0xa0000000
+#define BAMBOO_PCI_UPPER_MEM 0xafffffff
+#define BAMBOO_PCI_MEM_BASE 0xa0000000
+
+#define BAMBOO_PCIL0_BASE 0x00000000ef400000ULL
+#define BAMBOO_PCIL0_SIZE 0x40
+
+#define BAMBOO_PCIL0_PMM0LA 0x000
+#define BAMBOO_PCIL0_PMM0MA 0x004
+#define BAMBOO_PCIL0_PMM0PCILA 0x008
+#define BAMBOO_PCIL0_PMM0PCIHA 0x00C
+#define BAMBOO_PCIL0_PMM1LA 0x010
+#define BAMBOO_PCIL0_PMM1MA 0x014
+#define BAMBOO_PCIL0_PMM1PCILA 0x018
+#define BAMBOO_PCIL0_PMM1PCIHA 0x01C
+#define BAMBOO_PCIL0_PMM2LA 0x020
+#define BAMBOO_PCIL0_PMM2MA 0x024
+#define BAMBOO_PCIL0_PMM2PCILA 0x028
+#define BAMBOO_PCIL0_PMM2PCIHA 0x02C
+#define BAMBOO_PCIL0_PTM1MS 0x030
+#define BAMBOO_PCIL0_PTM1LA 0x034
+#define BAMBOO_PCIL0_PTM2MS 0x038
+#define BAMBOO_PCIL0_PTM2LA 0x03C
+
+#endif /* __ASM_BAMBOO_H__ */
+#endif /* __KERNEL__ */
diff -uprN linux-2.5-orig/arch/ppc/platforms/4xx/ibm440ep.c linux-2.5-440ep/arch/ppc/platforms/4xx/ibm440ep.c
--- linux-2.5-orig/arch/ppc/platforms/4xx/ibm440ep.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/platforms/4xx/ibm440ep.c 2005-04-05 15:36:25.000000000 -0700
@@ -0,0 +1,176 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440ep.c
+ *
+ * PPC440EP I/O descriptions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <platforms/4xx/ibm440ep.h>
+#include <asm/ocp.h>
+
+static struct ocp_func_emac_data ibm440ep_emac0_def = {
+ .rgmii_idx = -1, /* No RGMII */
+ .rgmii_mux = -1, /* No RGMII */
+ .zmii_idx = 0, /* ZMII device index */
+ .zmii_mux = 0, /* ZMII input of this EMAC */
+ .mal_idx = 0, /* MAL device index */
+ .mal_rx_chan = 0, /* MAL rx channel number */
+ .mal_tx_chan = 0, /* MAL tx channel number */
+ .wol_irq = 61, /* WOL interrupt number */
+ .mdio_idx = -1, /* No shared MDIO */
+ .tah_idx = -1, /* No TAH */
+};
+
+static struct ocp_func_emac_data ibm440ep_emac1_def = {
+ .rgmii_idx = -1, /* No RGMII */
+ .rgmii_mux = -1, /* No RGMII */
+ .zmii_idx = 0, /* ZMII device index */
+ .zmii_mux = 1, /* ZMII input of this EMAC */
+ .mal_idx = 0, /* MAL device index */
+ .mal_rx_chan = 1, /* MAL rx channel number */
+ .mal_tx_chan = 2, /* MAL tx channel number */
+ .wol_irq = 63, /* WOL interrupt number */
+ .mdio_idx = -1, /* No shared MDIO */
+ .tah_idx = -1, /* No TAH */
+};
+OCP_SYSFS_EMAC_DATA()
+
+static struct ocp_func_mal_data ibm440ep_mal0_def = {
+ .num_tx_chans = 4, /* Number of TX channels */
+ .num_rx_chans = 2, /* Number of RX channels */
+ .txeob_irq = 10, /* TX End Of Buffer IRQ */
+ .rxeob_irq = 11, /* RX End Of Buffer IRQ */
+ .txde_irq = 33, /* TX Descriptor Error IRQ */
+ .rxde_irq = 34, /* RX Descriptor Error IRQ */
+ .serr_irq = 32, /* MAL System Error IRQ */
+};
+OCP_SYSFS_MAL_DATA()
+
+static struct ocp_func_iic_data ibm440ep_iic0_def = {
+ .fast_mode = 0, /* Use standad mode (100Khz) */
+};
+
+static struct ocp_func_iic_data ibm440ep_iic1_def = {
+ .fast_mode = 0, /* Use standad mode (100Khz) */
+};
+OCP_SYSFS_IIC_DATA()
+
+struct ocp_def core_ocp[] = {
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_OPB,
+ .index = 0,
+ .paddr = 0x0EF600000ULL,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 0,
+ .paddr = PPC440EP_UART0_ADDR,
+ .irq = UART0_INT,
+ .pm = IBM_CPM_UART0,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 1,
+ .paddr = PPC440EP_UART1_ADDR,
+ .irq = UART1_INT,
+ .pm = IBM_CPM_UART1,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 2,
+ .paddr = PPC440EP_UART2_ADDR,
+ .irq = UART2_INT,
+ .pm = IBM_CPM_UART2,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 3,
+ .paddr = PPC440EP_UART3_ADDR,
+ .irq = UART3_INT,
+ .pm = IBM_CPM_UART3,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_IIC,
+ .index = 0,
+ .paddr = 0x0EF600700ULL,
+ .irq = 2,
+ .pm = IBM_CPM_IIC0,
+ .additions = &ibm440ep_iic0_def,
+ .show = &ocp_show_iic_data
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_IIC,
+ .index = 1,
+ .paddr = 0x0EF600800ULL,
+ .irq = 7,
+ .pm = IBM_CPM_IIC1,
+ .additions = &ibm440ep_iic1_def,
+ .show = &ocp_show_iic_data
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_GPIO,
+ .index = 0,
+ .paddr = 0x0EF600B00ULL,
+ .irq = OCP_IRQ_NA,
+ .pm = IBM_CPM_GPIO0,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_GPIO,
+ .index = 1,
+ .paddr = 0x0EF600C00ULL,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_MAL,
+ .paddr = OCP_PADDR_NA,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ .additions = &ibm440ep_mal0_def,
+ .show = &ocp_show_mal_data,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_EMAC,
+ .index = 0,
+ .paddr = 0x0EF600E00ULL,
+ .irq = 60,
+ .pm = OCP_CPM_NA,
+ .additions = &ibm440ep_emac0_def,
+ .show = &ocp_show_emac_data,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_EMAC,
+ .index = 1,
+ .paddr = 0xEF600F00ULL,
+ .irq = 62,
+ .pm = OCP_CPM_NA,
+ .additions = &ibm440ep_emac1_def,
+ .show = &ocp_show_emac_data,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_ZMII,
+ .paddr = 0x0EF600D00ULL,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_USB,
+ .paddr = 0x0EF601000ULL,
+ .irq = 40,
+ .pm = IBM_CPM_USB1H,
+ },
+ { .vendor = OCP_VENDOR_INVALID
+ }
+};
+
diff -uprN linux-2.5-orig/arch/ppc/platforms/4xx/ibm440ep.h linux-2.5-440ep/arch/ppc/platforms/4xx/ibm440ep.h
--- linux-2.5-orig/arch/ppc/platforms/4xx/ibm440ep.h 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/platforms/4xx/ibm440ep.h 2005-04-05 15:36:25.000000000 -0700
@@ -0,0 +1,76 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440ep.h
+ *
+ * PPC440EP definitions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2002 Roland Dreier
+ * Copyright 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __PPC_PLATFORMS_IBM440EP_H
+#define __PPC_PLATFORMS_IBM440EP_H
+
+#include <linux/config.h>
+#include <asm/ibm44x.h>
+
+/* UART */
+#define PPC440EP_UART0_ADDR 0x0EF600300
+#define PPC440EP_UART1_ADDR 0x0EF600400
+#define PPC440EP_UART2_ADDR 0x0EF600500
+#define PPC440EP_UART3_ADDR 0x0EF600600
+#define UART0_INT 0
+#define UART1_INT 1
+#define UART2_INT 3
+#define UART3_INT 4
+
+/* Clock and Power Management */
+#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
+#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
+#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
+#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */
+#define IBM_CPM_FPU 0x04000000 /* floating point unit */
+#define IBM_CPM_CPU 0x02000000 /* processor core */
+#define IBM_CPM_DMA 0x01000000 /* DMA controller */
+#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
+#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
+#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */
+#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
+#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
+#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */
+#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */
+#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */
+#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */
+#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
+#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
+#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
+#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
+#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
+#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
+#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
+#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
+#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */
+#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */
+#define IBM_CPM_UART2 0x00000008 /* serial port 2 */
+#define IBM_CPM_UART3 0x00000004 /* serial port 3 */
+#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */
+#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */
+
+#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
+ | IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
+ | IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
+ | IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
+ | IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
+ | IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
+
+
+#endif /* __PPC_PLATFORMS_IBM440EP_H */
+#endif /* __KERNEL__ */
diff -uprN linux-2.5-orig/arch/ppc/syslib/Makefile linux-2.5-440ep/arch/ppc/syslib/Makefile
--- linux-2.5-orig/arch/ppc/syslib/Makefile 2005-04-05 15:30:47.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/syslib/Makefile 2005-04-05 15:36:26.000000000 -0700
@@ -11,6 +11,7 @@ obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram
obj-$(CONFIG_PPC_OCP) += ocp.o
obj-$(CONFIG_IBM_OCP) += ibm_ocp.o
obj-$(CONFIG_44x) += ibm44x_common.o
+obj-$(CONFIG_440EP) += ibm440gx_common.o
obj-$(CONFIG_440GP) += ibm440gp_common.o
obj-$(CONFIG_440GX) += ibm440gx_common.o
obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
@@ -44,6 +45,7 @@ obj-$(CONFIG_PPC_CHRP) += open_pic.o in
obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
todc_time.o
+obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
diff -uprN linux-2.5-orig/arch/ppc/syslib/ibm440gx_common.c linux-2.5-440ep/arch/ppc/syslib/ibm440gx_common.c
--- linux-2.5-orig/arch/ppc/syslib/ibm440gx_common.c 2005-04-05 15:30:47.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/syslib/ibm440gx_common.c 2005-04-05 15:36:27.000000000 -0700
@@ -34,6 +34,10 @@ void __init ibm440gx_get_clocks(struct i
u32 plld = CPR_READ(DCRN_CPR_PLLD);
u32 uart0 = SDR_READ(DCRN_SDR_UART0);
u32 uart1 = SDR_READ(DCRN_SDR_UART1);
+#ifdef CONFIG_440EP
+ u32 uart2 = SDR_READ(DCRN_SDR_UART2);
+ u32 uart3 = SDR_READ(DCRN_SDR_UART3);
+#endif
/* Dividers */
u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
@@ -96,6 +100,19 @@ bypass:
p->uart1 = ser_clk;
else
p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+
+#ifdef CONFIG_440EP
+ if (uart2 & 0x00800000)
+ p->uart1 = ser_clk;
+ else
+ p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+
+ if (uart3 & 0x00800000)
+ p->uart1 = ser_clk;
+ else
+ p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+#endif
+
}
/* Issue L2C diagnostic command */
diff -uprN linux-2.5-orig/arch/ppc/syslib/ibm44x_common.h linux-2.5-440ep/arch/ppc/syslib/ibm44x_common.h
--- linux-2.5-orig/arch/ppc/syslib/ibm44x_common.h 2005-04-05 15:30:47.000000000 -0700
+++ linux-2.5-440ep/arch/ppc/syslib/ibm44x_common.h 2005-04-05 15:36:28.000000000 -0700
@@ -29,6 +29,11 @@ struct ibm44x_clocks {
unsigned int ebc; /* PerClk */
unsigned int uart0;
unsigned int uart1;
+#ifdef CONFIG_440EP
+ /* The IBM 440EP eval board has four uarts */
+ unsigned int uart2;
+ unsigned int uart3;
+#endif
};
/* common 44x platform init */
diff -uprN linux-2.5-orig/include/asm-ppc/ibm44x.h linux-2.5-440ep/include/asm-ppc/ibm44x.h
--- linux-2.5-orig/include/asm-ppc/ibm44x.h 2005-04-05 15:31:49.000000000 -0700
+++ linux-2.5-440ep/include/asm-ppc/ibm44x.h 2005-04-06 09:08:48.000000000 -0700
@@ -35,8 +35,10 @@
#define PPC44x_LOW_SLOT 63
/* LS 32-bits of UART0 physical address location for early serial text debug */
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
#define UART0_PHYS_IO_BASE 0xf0000200
+#elif defined(CONFIG_440EP)
+#define UART0_PHYS_IO_BASE 0xe0000000
#else
#define UART0_PHYS_IO_BASE 0x40000200
#endif
@@ -49,11 +51,16 @@
/*
* Standard 4GB "page" definitions
*/
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
#define PPC44x_IO_PAGE 0x0000000100000000ULL
#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_PAGE 0x0000000000000000ULL
+#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
+#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
+#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
#else
#define PPC44x_IO_PAGE 0x0000000100000000ULL
#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
@@ -64,7 +71,7 @@
/*
* 36-bit trap ranges
*/
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
#define PPC44x_IO_LO 0xf0000000UL
#define PPC44x_IO_HI 0xf0000fffUL
#define PPC44x_PCI0CFG_LO 0x0ec00000UL
@@ -75,6 +82,13 @@
#define PPC44x_PCI2CFG_HI 0x2ec00007UL
#define PPC44x_PCIMEM_LO 0x80000000UL
#define PPC44x_PCIMEM_HI 0xdfffffffUL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_LO 0xef500000UL
+#define PPC44x_IO_HI 0xefffffffUL
+#define PPC44x_PCI0CFG_LO 0xeec00000UL
+#define PPC44x_PCI0CFG_HI 0xeecfffffUL
+#define PPC44x_PCIMEM_LO 0xa0000000UL
+#define PPC44x_PCIMEM_HI 0xdfffffffUL
#else
#define PPC44x_IO_LO 0x40000000UL
#define PPC44x_IO_HI 0x40000fffUL
@@ -152,6 +166,12 @@
#define DCRN_SDR_UART0 0x0120
#define DCRN_SDR_UART1 0x0121
+#ifdef CONFIG_440EP
+#define DCRN_SDR_UART2 0x0122
+#define DCRN_SDR_UART3 0x0123
+#define DCRN_SDR_CUST0 0x4000
+#endif
+
/* SDR read/write helper macros */
#define SDR_READ(offset) ({\
mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
@@ -169,6 +189,14 @@
#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
#define DCRN_MAL_BASE 0x180
+#ifdef CONFIG_440EP
+#define DCRN_DMA2P40_BASE 0x300
+#define DCRN_DMA2P41_BASE 0x308
+#define DCRN_DMA2P42_BASE 0x310
+#define DCRN_DMA2P43_BASE 0x318
+#define DCRN_DMA2P4SR_BASE 0x320
+#endif
+
/* UIC */
#define DCRN_UIC0_BASE 0xc0
#define DCRN_UIC1_BASE 0xd0
diff -uprN linux-2.5-orig/include/asm-ppc/ibm4xx.h linux-2.5-440ep/include/asm-ppc/ibm4xx.h
--- linux-2.5-orig/include/asm-ppc/ibm4xx.h 2005-04-05 15:31:49.000000000 -0700
+++ linux-2.5-440ep/include/asm-ppc/ibm4xx.h 2005-04-05 15:36:29.000000000 -0700
@@ -109,6 +109,10 @@ void ppc4xx_init(unsigned long r3, unsig
#include <platforms/4xx/ocotea.h>
#endif
+#if defined(CONFIG_BAMBOO)
+#include <platforms/4xx/bamboo.h>
+#endif
+
#ifndef __ASSEMBLY__
#ifdef CONFIG_40x
/*
diff -uprN linux-2.5-orig/include/asm-ppc/ppc_asm.h linux-2.5-440ep/include/asm-ppc/ppc_asm.h
--- linux-2.5-orig/include/asm-ppc/ppc_asm.h 2005-04-05 15:31:49.000000000 -0700
+++ linux-2.5-440ep/include/asm-ppc/ppc_asm.h 2005-04-05 15:36:30.000000000 -0700
@@ -184,6 +184,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
#define PPC405_ERR77_SYNC
#endif
+#ifdef CONFIG_IBM440EP_ERR42
+#define PPC440EP_ERR42 isync
+#else
+#define PPC440EP_ERR42
+#endif
+
/* The boring bits... */
/* Condition Register Bit Fields */
^ permalink raw reply
* Re: pte_update and 64-bit PTEs on PPC32?
From: Chris Friesen @ 2005-04-06 17:20 UTC (permalink / raw)
To: Kumar Gala; +Cc: linux-ppc-embedded list, Paul Mackerras, linuxppc-dev list
In-Reply-To: <c689550a30a3129f8576f78eaa6f7af4@freescale.com>
Kumar Gala wrote:
> static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned
> long addr,
> pte_t *ptep)
> {
> pte_t tmp = *ptep;
> pte_update(ptep, ~_PAGE_HASHPTE, 0);
> return tmp;
> }
Doesn't work. The update and storing of the old value must be atomic.
The value of the pte can change between storing the tmp value and
calling pte_update().
Chris
^ permalink raw reply
* mpc8248: how to map SEC
From: Vikas Aggarwal @ 2005-04-06 16:46 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: kernelnewbies
freescale's mpc8248: how to map SEC ?
I am trying to map SEC(Security Engine). The linux-kernel i have from
embeddedplanet.com already works great for CPM on this mpc8248.
In my first approach i tried to run this block-of-code at the end of
fec_enet_init/fcc_enet.c
{
unsigned long coremask1;
unsigned long IOBaseAddress1;
bd_t *bd;
bd = (bd_t *)__res;
#define IDENTIFICATION_OFFSET1 0x1020
#define SEC_BASE_ADDRESS 0x00040000
#define SEC2_BASE_SIZE1 0x10000
IOBaseAddress1=(unsigned long)
ioremap((phys_addr_t)(bd->bi_immr+SEC_BASE_ADDRESS), SEC_BASE_SIZE);
coremask1=*((volatile unsigned long *)(IOBaseAddress1 +
IDENTIFICATION_OFFSET1) +1);
printk(KERN_EMERG"SEC1.0 ID=%lu",coremask1);
}
But it will OOPS complaining 0x00040000 was passed to ioremap, that means
bd->bi_immr is NULL. Why is it so? This approach works well for mpc8555E
SEC engine.
Second approach , i am trying to immitate based on how CPM is accessed on
mpc8248, here CPM_MAP_ADDR is #defined to ((uint)0xf0000000). Can i make a
similar #define for SEC_MAP_ADDR ? How the above value for CPM_MAP_ADDR
was chosen in arch/ppc/platforms/ep8248.h:line 42 ?
Will appreciate the help? I am struck here right now
^ permalink raw reply
* Re: pte_update and 64-bit PTEs on PPC32?
From: Kumar Gala @ 2005-04-06 16:44 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev list, Paul Mackerras, linux-ppc-embedded list
In-Reply-To: <1112770418.9567.137.camel@gaston>
On Apr 6, 2005, at 1:53 AM, Benjamin Herrenschmidt wrote:
> On Wed, 2005-04-06 at 01:51 -0500, Kumar Gala wrote:
> > Paul,
> >
> > I've tracked down a bug I've been having to the fact that pte_update
> > assumes a pte is a unsigned long.=A0 I need to look into what the =
exact
> > implications this has.=A0 I was wondering what the thoughts were =
with
> > respect to how this is suppose to work properly on 440 with its=20
> 64-bit
> > pte?=A0 I'm looking at a 64-bit pte for some Freescale book-e parts =
as=20
> we
> > move to 36-bit physical address support.
> >
> > The problem I found was ptep_get_and_clear() would return back only =
a
> > 32-bit value and thus we loose any information in the upper=20
> 32-bits.=A0 I
> > found the call in sys_mprotect ... -> change_pte_range ->
> > ptep_get_and_clear()
> >
> > Will provide some update on this tomorrow.
>
> It's quite important for the flags to all be together in a single 32
> bits entity so that atomic operations can be done on them. The RPN
> should be able to extend beyond the initial 32 bits provided we are
> careful about the way we manipulate the PTEs. When setting a PTE, we
> should always first set the "other" part, then the PTE present bit=20
> last
> or a CPU would possibly get a stale PTE. The problem with that scheme=20=
> is
> that I can see possible races on dual page faults trying to fill in =
the
> same PTE if we drop the page table lock (christoph lameter stuff) but=20=
> it
> should work for us now.
Ben, I agree with you about having the flags in a single word so we can=20=
lock them properly. In the short term it appears that the issue I'm=20
running into is explicit with ptep_get_and_clear():
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned=20
long addr,
pte_t *ptep)
{
return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
}
It appears that we should be returning the pte that was passed in,=20
before its modified? (seems a little silly to me, why bother, the=20
caller could do this -- i've posted to lkml on the issue?). Anyways,=20
since pte_update only returns the lower 32-bits the wrong thing=20
happens. The following seems to be a better implementation of=20
ptep_get_and_clear() for ppc32 which resolves my issue:
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned=20
long addr,
pte_t *ptep)
{
pte_t tmp =3D *ptep;
pte_update(ptep, ~_PAGE_HASHPTE, 0);
return tmp;
}
If we are ok with this I'll send a patch upstream for it. I'd like to=20=
still discuss how to make this all proper long term. Currently,=20
ptep_get_and_clear was the only user of pte_update that used the return=20=
value for anything but flags. One change would be for it to return=20
just the flags portion of the pte it was given. Another would be for=20
us to implement a proper 64-bit pte version of pte_update.
- kumar
^ permalink raw reply
* Re: Status of Linux 2.6 for 40x and 44x CPUs
From: Eugene Surovegin @ 2005-04-06 16:12 UTC (permalink / raw)
To: llandre; +Cc: linuxppc-embedded
In-Reply-To: <6.0.1.1.0.20050406093338.01eb9d48@192.168.2.1>
On Wed, Apr 06, 2005 at 09:41:27AM +0200, llandre wrote:
> I found some messages about the status of 2.6 kernel for MPC8xx-based
> machines but
> I found nothing about 40x and 44x CPU.
So what? Absence of such messages doesn't mean 4xx doesn't work, I'd
say quite the opposite.
> Anybody can tell me something about
> it? Did it
> get production stable? If not, which are the areas that are under heavy
> development?
4xx is quite stable, although I'm not sure many people use 2.6 in
production.
--
Eugene
^ permalink raw reply
* [PATCH] [RFC] workaround buggy dcbX instructions in 8xx
From: Joakim Tjernlund @ 2005-04-06 15:22 UTC (permalink / raw)
To: Linuxppc-Embedded@Ozlabs. Org
All cache instructions in 8xx are somewhat buggy as they
do not update the DAR register when causing a DTLB Miss/Error
This is a forward port of my workaround from 2.4 to 2.6 to fix this problem.
The patch tags DAR with a known value which is tested for in the DTLB Error handler.
If DAR matches the tag, a instruction decode routine is invoked for calculate the
faulting address. There are two verisons of the decode procedure which is controlled
by a #define. Read the patch and try different versions.
I have not tested this on 2.6 since I haven't ported our board
from 2.4 yet.
Jocke
===== head_8xx.S 1.21 vs edited =====
--- 1.21/arch/ppc/kernel/head_8xx.S 2005-03-29 00:21:20 +02:00
+++ edited/head_8xx.S 2005-04-06 17:01:51 +02:00
@@ -32,6 +32,8 @@
#include <asm/ppc_asm.h>
#include <asm/offsets.h>
+#define CONFIG_8xx_DCBxFIXED
+
/* Macro to make the code more readable. */
#ifdef CONFIG_8xx_CPU6
#define DO_8xx_CPU6(val, reg) \
@@ -41,6 +43,20 @@
#else
#define DO_8xx_CPU6(val, reg)
#endif
+
+#ifdef CONFIG_8xx_DCBxFIXED
+/* These macros are used to tag DAR with a known value so that the
+ * DataTLBError can recognize a buggy dcbx instruction and workaround
+ * the problem.
+ */
+#define TAG_VAL 0x00f0 /* -1 may also be used */
+#define TAG_DAR_R10 \
+ li r10, TAG_VAL;\
+ mtspr SPRN_DAR, r10;
+#else
+#define TAG_DAR_R10
+#endif
+
.text
.globl _stext
_stext:
@@ -174,6 +190,7 @@
xfer(n, hdlr)
#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
+ TAG_DAR_R10; \
li r10,trap; \
stw r10,TRAP(r11); \
li r10,MSR_KERNEL; \
@@ -214,6 +231,7 @@
mfspr r5,SPRN_DSISR
stw r5,_DSISR(r11)
addi r3,r1,STACK_FRAME_OVERHEAD
+ TAG_DAR_R10
EXC_XFER_STD(0x200, MachineCheckException)
/* Data access exception.
@@ -227,6 +245,7 @@
stw r10,_DSISR(r11)
mr r5,r10
mfspr r4,SPRN_DAR
+ TAG_DAR_R10
EXC_XFER_EE_LITE(0x300, handle_page_fault)
/* Instruction access exception.
@@ -252,6 +271,7 @@
mfspr r5,SPRN_DSISR
stw r5,_DSISR(r11)
addi r3,r1,STACK_FRAME_OVERHEAD
+ TAG_DAR_R10
EXC_XFER_EE(0x600, AlignmentException)
/* Program check exception */
@@ -414,7 +434,13 @@
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3)
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
-
+#ifdef CONFIG_8xx_DCBxFIXED
+ #if TAG_VAL == 0x00f0 /* Save 1 instr. by reusing the val loaded in r11 above */
+ mtspr SPRN_DAR, r11
+ #else
+ TAG_DAR_R10
+ #endif
+#endif
mfspr r10, SPRN_M_TW /* Restore registers */
lwz r11, 0(r0)
mtcr r11
@@ -450,11 +476,20 @@
mfcr r10
stw r10, 0(r0)
stw r11, 4(r0)
+ mfspr r10, SPRN_DAR
+#ifdef CONFIG_8xx_DCBxFIXED
+ /* If DAR contains TAG_VAL implies a buggy dcbx instruction
+ * that did not set DAR.
+ */
+ cmpwi cr0, r10, TAG_VAL
+ beq- 100f /* Branch if TAG_VAL to dcbx workaround procedure */
+101: /* return from dcbx instruction bug workaround, r10 holds value of DAR */
+#endif
/* First, make sure this was a store operation.
*/
- mfspr r10, SPRN_DSISR
- andis. r11, r10, 0x0200 /* If set, indicates store op */
+ mfspr r11, SPRN_DSISR
+ andis. r11, r11, 0x0200 /* If set, indicates store op */
beq 2f
/* The EA of a data TLB miss is automatically stored in the MD_EPN
@@ -473,7 +508,7 @@
* are initialized in mapin_ram(). This will avoid the problem,
* assuming we only use the dcbi instruction on kernel addresses.
*/
- mfspr r10, SPRN_DAR
+ /* DAR is in r10 already */
rlwinm r11, r10, 0, 0, 19
ori r11, r11, MD_EVALID
mfspr r10, SPRN_M_CASID
@@ -523,7 +558,13 @@
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3)
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
-
+#ifdef CONFIG_8xx_DCBxFIXED
+ #if TAG_VAL == 0x00f0 /* Save 1 instr. by reusing the val loaded in r11 above */
+ mtspr SPRN_DAR, r11
+ #else
+ TAG_DAR_R10
+ #endif
+#endif
mfspr r10, SPRN_M_TW /* Restore registers */
lwz r11, 0(r0)
mtcr r11
@@ -561,6 +602,185 @@
. = 0x2000
+#ifdef CONFIG_8xx_DCBxFIXED
+/* This is the workaround procedure to calculate the data EA for buggy dcbx,dcbi instructions
+ * by decoding the registers used by the dcbx instruction and adding them.
+ * DAR is set to the calculated address and r10 also holds the EA on exit.
+ */
+//#define INSTR_CHECK /* define to verify if it is a dcbx instr. Should not be needed. */
+//#define NO_SELF_MODIFYING_CODE /* define if you don't want to use self modifying code */
+//#define DEBUG_DCBX_INSTRUCTIONS /* for debugging only. Needs INSTR_CHECK defined as well. */
+//#define KERNEL_SPACE_ONLY /* define if user space do NOT contain dcbx instructions. */
+
+#ifndef KERNEL_SPACE_ONLY
+ nop /* A few nops to make the modified_instr: space below cache line aligned */
+ nop
+139: /* fetch instruction from userspace memory */
+ DO_8xx_CPU6(0x3780, r3)
+ mtspr SPRN_MD_EPN, r10
+ mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */
+ lwz r11, 0(r11) /* Get the level 1 entry */
+ DO_8xx_CPU6(0x3b80, r3)
+ mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
+ mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
+ lwz r11, 0(r11) /* Get the pte */
+ /* concat physical page address(r11) and page offset(r10) */
+ rlwimi r11, r10, 0, 20, 31
+ b 140f
+#endif
+100: /* Entry point for dcbx workaround. */
+ /* fetch instruction from memory. */
+ mfspr r10,SPRN_SRR0
+#ifndef KERNEL_SPACE_ONLY
+ andis. r11, r10, 0x8000
+ tophys (r11, r10)
+ beq- 139b /* Branch if user space address */
+#else
+ tophys (r11, r10)
+#endif
+140: lwz r11,0(r11)
+#ifdef INSTR_CHECK
+/* Check if it really is a dcbx instruction. This is not needed as far as I can tell */
+/* dcbt and dcbtst does not generate DTLB Misses/Errors, no need to include them here */
+ rlwinm r10, r11, 0, 21, 30
+ cmpwi cr0, r10, 2028 /* Is dcbz? */
+ beq+ 142f
+ cmpwi cr0, r10, 940 /* Is dcbi? */
+ beq+ 142f
+ cmpwi cr0, r10, 108 /* Is dcbst? */
+ beq+ 142f
+ cmpwi cr0, r10, 172 /* Is dcbf? */
+ beq+ 142f
+ cmpwi cr0, r10, 1964 /* Is icbi? */
+ beq+ 142f
+#ifdef DEBUG_DCBX_INSTRUCTIONS
+141: b 141b /* Stop here if no dcbx instruction */
+#endif
+ mfspr r10, SPRN_DAR /* r10 must hold DAR at exit */
+ b 101b /* None of the above, go back to normal TLB processing */
+142: /* continue, it was a dcbx instruction. */
+#endif
+#ifdef CONFIG_8xx_CPU6
+ lwz r3, 8(r0) /* restore r3 from memory */
+#endif
+#ifndef NO_SELF_MODIFYING_CODE
+ andis. r10,r11,0x1f /* test if reg RA is r0 */
+ li r10,modified_instr@l
+ dcbtst r0,r10 /* touch for store */
+ rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
+ oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
+ ori r11,r11,532
+ stw r11,0(r10) /* store add/and instruction */
+ dcbf 0,r10 /* flush new instr. to memory. */
+ icbi 0,r10 /* invalidate instr. cache line */
+ lwz r11, 4(r0) /* restore r11 from memory */
+ mfspr r10, SPRN_M_TW /* restore r10 from M_TW */
+ isync /* Wait until new instr is loaded from memory */
+modified_instr:
+ .space 4 /* this is where the add/and instr. is stored */
+#ifdef DEBUG_DCBX_INSTRUCTIONS
+ /* fill with some garbage */
+ li r11,0xffff
+ stw r11,0(r11)
+#endif
+ bne+ 143f
+ subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
+143: mtdar r10 /* store faulting EA in DAR */
+ b 101b /* Go back to normal TLB handling */
+#else
+ mfctr r10
+ mtdar r10 /* save ctr reg in DAR */
+ rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
+ addi r10, r10, 150f@l /* add start of table */
+ mtctr r10 /* load ctr with jump address */
+ xor r10, r10, r10 /* sum starts at zero */
+ bctr /* jump into table */
+150:
+ add r10, r10, r0
+ b 151f
+ add r10, r10, r1
+ b 151f
+ add r10, r10, r2
+ b 151f
+ add r10, r10, r3
+ b 151f
+ add r10, r10, r4
+ b 151f
+ add r10, r10, r5
+ b 151f
+ add r10, r10, r6
+ b 151f
+ add r10, r10, r7
+ b 151f
+ add r10, r10, r8
+ b 151f
+ add r10, r10, r9
+ b 151f
+ mtctr r11 /* reg 10 needs special handling */
+ b 154f
+ mtctr r11 /* reg 11 needs special handling */
+ b 153f
+ add r10, r10, r12
+ b 151f
+ add r10, r10, r13
+ b 151f
+ add r10, r10, r14
+ b 151f
+ add r10, r10, r15
+ b 151f
+ add r10, r10, r16
+ b 151f
+ add r10, r10, r17
+ b 151f
+ add r10, r10, r18
+ b 151f
+ add r10, r10, r19
+ b 151f
+ add r10, r10, r20
+ b 151f
+ add r10, r10, r21
+ b 151f
+ add r10, r10, r22
+ b 151f
+ add r10, r10, r23
+ b 151f
+ add r10, r10, r24
+ b 151f
+ add r10, r10, r25
+ b 151f
+ add r10, r10, r25
+ b 151f
+ add r10, r10, r27
+ b 151f
+ add r10, r10, r28
+ b 151f
+ add r10, r10, r29
+ b 151f
+ add r10, r10, r30
+ b 151f
+ add r10, r10, r31
+151:
+ rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
+ beq 152f /* if reg RA is zero, don't add it */
+ addi r11, r11, 150b@l /* add start of table */
+ mtctr r11 /* load ctr with jump address */
+ rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
+ bctr /* jump into table */
+152:
+ mfdar r11
+ mtctr r11 /* restore ctr reg from DAR */
+ mtdar r10 /* save fault EA to DAR */
+ b 101b /* Go back to normal TLB handling */
+
+ /* special handling for r10,r11 since these are modified already */
+153: lwz r11, 4(r0) /* load r11 from memory */
+ b 155f
+154: mfspr r11, SPRN_M_TW /* load r10 from M_TW */
+155: add r10, r10, r11 /* add it */
+ mfctr r11 /* restore r11 */
+ b 151b
+#endif
+#endif
.globl giveup_fpu
giveup_fpu:
blr
^ permalink raw reply
* Re: USB on 8250 PCI
From: Jaap-Jan Boor @ 2005-04-06 12:12 UTC (permalink / raw)
To: Wojciech Kromer; +Cc: linuxppc-embedded
In-Reply-To: <4253CB3B.7040009@dgt.com.pl>
On 6-apr-05, at 13:42, Wojciech Kromer wrote:
> anyone have tested USB host controller on pci with mpc8250
> i have NEC PD720101 ohci/ehci device
yes, mpc8270 with Philips 1561
(I found the CPM USB host controller with 1 ms SOF
under software control too risky)
the 1561 is OHCI/EHCI compliant, the standard linux drivers
can be used
>
> i have no response from usb devices
> any hints?
>
>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* MPC870, PCMCIA and IDE
From: Markus Westergren @ 2005-04-06 14:38 UTC (permalink / raw)
To: linuxppc-embedded
Hi
I'm trying to get IDE working via PCMCIA on a custom board wih a MPC870 CPU. I
have a SanDisk 128MB CF card and a CF to PCMCIA adapter. I have it partly
working. The bootloader (RedBoot) dont configure the PCMCIA registers so I took
the initialization code from U-Boot and added it to m8xx_ide_init. The card is
identified but no IDE device is found. I have run out of options to try and
would be greatful for any ideas.
Relevant kernel messages:
Uncompressing Linux...done.
Now booting the kernel
hardware_enable: Slot A
<6>PIPR(fa2000f0)=0x4600ff00
PIPR: 0x4600ff00 ==> VS1=off, VS2=on
3.3V card found: <6>Enable PCMCIA buffers and stop RESET
# hardware_enable done
Win 0: BR: d0000000 OR: b8024491
Win 1: BR: d4000000 OR: 780244d9
Win 2: BR: d8000000 OR: 78024499
Win 3: BR: dc000000 OR: b8024491
Win 4: BR: 00000000 OR: 00000000
Win 5: BR: e0000000 OR: 780244d9
Win 6: BR: e4000000 OR: 78024499
Win 7: BR: 00000000 OR: 00000000
<snip>
Uniform Multi-Platform E-IDE driver Revision: 7.00beta4-2.4
ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx
PCMCIA slot A: phys mem d0000000...e8000000 (size 18000000)
PCMCIA virt base: c20f7000
PIPR = 0x4700C000 slot A ==> mask = 0x18000000
PCMCIA MEM: C20F7000
Card ID: SanDisk SDP 5/3 0.6
Fixed Disk Card
IDE interface
[silicon] [unique] [single] [sleep] [standby] [idle] [low power]
base: c20f7000 + 00000000 = c20f7000
port[0]: c20f7000 + 04000320 = 00000000
port[1]: c20f7000 + 08000321 = 00000001
port[2]: c20f7000 + 08000322 = 00000002
port[3]: c20f7000 + 08000323 = 00000003
port[4]: c20f7000 + 08000324 = 00000004
port[5]: c20f7000 + 08000325 = 00000005
port[6]: c20f7000 + 08000326 = 00000006
port[7]: c20f7000 + 08000327 = 00000007
port[8]: c20f7000 + 00000106 = 00000008
port[9]: c20f7000 + 0000000a = 00000009
Probing IDE interface ide0...
probing for hda: present=0, media=32, probetype=ATA
probing for hda: present=0, media=32, probetype=ATAPI
probing for hdb: present=0, media=32, probetype=ATA
probing for hdb: present=0, media=32, probetype=ATAPI
<snip>
Thanks
/Markus
^ permalink raw reply
* RE: Bogomips?
From: Rune Torgersen @ 2005-04-06 13:53 UTC (permalink / raw)
To: David Frascone, linuxppc-dev
It's way low...
(output from a 8560 on 2.6.11):
cpu : e500
revision : 2.0 (pvr 8020 0020)
bogomips : 823.29
Vendor : Freescale Semiconductor
Machine : mpc8560ads
clock : 825MHz
PVR : 0x80200020
SVR : 0x80700020
PLL setting : 0x5
Memory : 256 MB=20
The 8260 one seems correct
cpu : 82xx
revision : 16.20 (pvr 8081 1014)
bogomips : 191.48
core clock : 289 MHz
CPM clock : 206 MHz
bus clock : 82 MHz
> -----Original Message-----
> From: linuxppc-dev-bounces@ozlabs.org=20
> [mailto:linuxppc-dev-bounces@ozlabs.org] On Behalf Of David Frascone
> Sent: Wednesday, April 06, 2005 08:12
> To: linuxppc-dev@ozlabs.org
> Subject: Bogomips?
>=20
>=20
> Can this be right? I'm getting This from a MPC-8260 (/proc/cpuinfo):
>=20
> ------------------------------------------------
> cpu : 82xx
> core clock : 199 MHz
> CPM clock : 133 MHz
> bus clock : 33 MHz
> revision : 1.1 (pvr 0081 0101)
> bogomips : 133.12
> ------------------------------------------------
>=20
> And this from a MPC-8540
> ------------------------------------------------
> cpu : e500
> revision : 2.0 (pvr 8020 0020)
> bogomips : 190.05
> Vendor : Motorola SPS
> Machine : mpc8540ads
> bus freq : 666.666660 MHz
> PVR : 0x80200020
> SVR : 0x80300020
> PLL setting : 0x4
> Memory : 512 MB
> ------------------------------------------------
>=20
>=20
> The second one looks way low . . . any ideas?
>=20
> -Dave
>=20
> --=20
> David Frascone
>=20
> Gimme back my face! You're getting it ugly.
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>=20
>=20
^ permalink raw reply
* Re: Bogomips?
From: Greg Weeks @ 2005-04-06 13:53 UTC (permalink / raw)
To: David Frascone; +Cc: linuxppc-dev
In-Reply-To: <20050406081201.07b9bdce@greenlantern.frascone.com>
David Frascone wrote:
>Can this be right? I'm getting This from a MPC-8260 (/proc/cpuinfo):
>
>------------------------------------------------
>cpu : 82xx
>core clock : 199 MHz
>CPM clock : 133 MHz
>bus clock : 33 MHz
>revision : 1.1 (pvr 0081 0101)
>bogomips : 133.12
>------------------------------------------------
>
>And this from a MPC-8540
>------------------------------------------------
>cpu : e500
>revision : 2.0 (pvr 8020 0020)
>bogomips : 190.05
>Vendor : Motorola SPS
>Machine : mpc8540ads
>bus freq : 666.666660 MHz
>PVR : 0x80200020
>SVR : 0x80300020
>PLL setting : 0x4
>Memory : 512 MB
>------------------------------------------------
>
>
>The second one looks way low . . . any ideas?
>
>
Do you have cache turned on? Do you have branch prediction turned on?
Branch prediction would be my guess as it's easy to miss.
Greg Weeks
^ permalink raw reply
* Bogomips?
From: David Frascone @ 2005-04-06 13:12 UTC (permalink / raw)
To: linuxppc-dev
Can this be right? I'm getting This from a MPC-8260 (/proc/cpuinfo):
------------------------------------------------
cpu : 82xx
core clock : 199 MHz
CPM clock : 133 MHz
bus clock : 33 MHz
revision : 1.1 (pvr 0081 0101)
bogomips : 133.12
------------------------------------------------
And this from a MPC-8540
------------------------------------------------
cpu : e500
revision : 2.0 (pvr 8020 0020)
bogomips : 190.05
Vendor : Motorola SPS
Machine : mpc8540ads
bus freq : 666.666660 MHz
PVR : 0x80200020
SVR : 0x80300020
PLL setting : 0x4
Memory : 512 MB
------------------------------------------------
The second one looks way low . . . any ideas?
-Dave
--
David Frascone
Gimme back my face! You're getting it ugly.
^ permalink raw reply
* USB on 8250 PCI
From: Wojciech Kromer @ 2005-04-06 11:42 UTC (permalink / raw)
To: linuxppc-embedded
anyone have tested USB host controller on pci with mpc8250
i have NEC PD720101 ohci/ehci device
i have no response from usb devices
any hints?
^ permalink raw reply
* USB on 8250 PCI
From: Wojciech Kromer @ 2005-04-06 11:39 UTC (permalink / raw)
anyone have tested USB host controller on pci with mpc8250
i have NEC PD720101 ohci/ehci device
i have no response from usb devices
any hints?
^ permalink raw reply
* Re: Linux port for MPC5200.
From: Andrey Volkov @ 2005-04-06 10:41 UTC (permalink / raw)
To: surendra.yadav; +Cc: linuxppc-dev
In-Reply-To: <BPEMKMADCCCPHPEDDKOOKEALCEAA.surendra.yadav@softdel.com>
http://www.denx.de
Surendra Yadav wrote:
> Hi All,
>
> Can anyone suggest me which linux port I can use for MPC5200.
> I tried linux 2.4.7 but it is not working. I am new to the linux porting.
> If any one gives links to the working port that will be nice to me.
>
> Thanks.
>
> Regards,
> Surendra
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
--
Regards
Andrey Volkov
^ permalink raw reply
* Status of Linux 2.6 for 40x and 44x CPUs
From: llandre @ 2005-04-06 7:41 UTC (permalink / raw)
To: linuxppc-embedded
Hi all,
I found some messages about the status of 2.6 kernel for MPC8xx-based
machines but
I found nothing about 40x and 44x CPU. Anybody can tell me something about
it? Did it
get production stable? If not, which are the areas that are under heavy
development?
Many thanks in advance,
llandre
DAVE Electronics System House - R&D Department
web: http://www.dave-tech.it
email: r&d2@dave-tech.it
^ permalink raw reply
* Re: pte_update and 64-bit PTEs on PPC32?
From: Benjamin Herrenschmidt @ 2005-04-06 6:53 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev list, Paul Mackerras, linux-ppc-embedded list
In-Reply-To: <93f533baba2b2f73ac9ec46b5401747e@freescale.com>
On Wed, 2005-04-06 at 01:51 -0500, Kumar Gala wrote:
> Paul,
>
> I've tracked down a bug I've been having to the fact that pte_update
> assumes a pte is a unsigned long. I need to look into what the exact
> implications this has. I was wondering what the thoughts were with
> respect to how this is suppose to work properly on 440 with its 64-bit
> pte? I'm looking at a 64-bit pte for some Freescale book-e parts as we
> move to 36-bit physical address support.
>
> The problem I found was ptep_get_and_clear() would return back only a
> 32-bit value and thus we loose any information in the upper 32-bits. I
> found the call in sys_mprotect ... -> change_pte_range ->
> ptep_get_and_clear()
>
> Will provide some update on this tomorrow.
It's quite important for the flags to all be together in a single 32
bits entity so that atomic operations can be done on them. The RPN
should be able to extend beyond the initial 32 bits provided we are
careful about the way we manipulate the PTEs. When setting a PTE, we
should always first set the "other" part, then the PTE present bit last
or a CPU would possibly get a stale PTE. The problem with that scheme is
that I can see possible races on dual page faults trying to fill in the
same PTE if we drop the page table lock (christoph lameter stuff) but it
should work for us now.
Ben.
^ permalink raw reply
* pte_update and 64-bit PTEs on PPC32?
From: Kumar Gala @ 2005-04-06 6:51 UTC (permalink / raw)
To: Paul Mackerras, Matt Porter, Benjamin Herrenschmidt
Cc: linuxppc-dev list, linux-ppc-embedded list
Paul,
I've tracked down a bug I've been having to the fact that pte_update
assumes a pte is a unsigned long. I need to look into what the exact
implications this has. I was wondering what the thoughts were with
respect to how this is suppose to work properly on 440 with its 64-bit
pte? I'm looking at a 64-bit pte for some Freescale book-e parts as we
move to 36-bit physical address support.
The problem I found was ptep_get_and_clear() would return back only a
32-bit value and thus we loose any information in the upper 32-bits. I
found the call in sys_mprotect ... -> change_pte_range ->
ptep_get_and_clear()
Will provide some update on this tomorrow.
- kumar
^ permalink raw reply
* Re: FCC Ethernet startup crash
From: Pantelis Antoniou @ 2005-04-06 6:03 UTC (permalink / raw)
To: Rune Torgersen; +Cc: linuxppc-embedded
In-Reply-To: <DCEAAC0833DD314AB0B58112AD99B93B85933A@ismail.innsys.innovsys.com>
Rune Torgersen wrote:
>>From: Dan Malek [mailto:dan@embeddededge.com]
>>On Apr 5, 2005, at 12:41 PM, Rune Torgersen wrote:
>>
>>
>>>Without calling fcc_restart in the start, I get lots of
>>
>>"eth0: tx queue
>>
>>>full!." messages.
>>
>>Do you tftp boot your kernel using the boot rom? Does the
>>boot rom disable the Ethernet before calling the kernel?
>
>
> Yes, I tftp the kernel, using U-Boot (1.1.2 CVS Head as of 11-20-04).
> Haven't looked at the code, but I think it disablesd the FCC Ethernets
> (Have seen discussions about htat on u-boot mailing list before)
>
U-boot definately disables the ethernets. Or at least it must.
> The patch Stefan Nickl gave to me works perfectly, and all it does is
> basically move the fcc_restart.
> The kernel was still calling fcc_restart twiche per FCC at startup (one
> time on init_fcc_startup, and then again in fcc_open), now it just calls
> it twice in fcc_open. Seems to work.
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
>
Regards
Pantelis
^ permalink raw reply
* Re: 8xx v2.6 TLB problems and suggested workaround
From: Pantelis Antoniou @ 2005-04-06 6:00 UTC (permalink / raw)
To: Dan Malek; +Cc: Paul Mackerras, linux-ppc-embedded
In-Reply-To: <ba633c3356ff1ec71f53d4a0998132ff@embeddededge.com>
Dan Malek wrote:
>
> On Apr 4, 2005, at 3:17 PM, Marcelo Tosatti wrote:
>
>> Problem is that the "dcbst" instruction will, _sometimes_ (the
>> failure/success rate is about 1/4
>> with my test application) fault as a _write_ operation on the data.
>
>
> Oh, geeze .... It's all coming back to me now ....
>
> The 8xx cache operations don't always operate as defined in the PEM.
> There are likely to be some archive discussions within the Freescale
> knowledge data base that describe the different behaviors I've seen
> with the chip variants and revisions. I can't find any of those e-mail
> discussions, so I'll try to recall from memory.
>
> The PEM cache instructions are all implemented in a microcode that
> uses the 8xx unique cache control SPRs. Depending upon the state
> of the cache and MMU, it seems in some cases the EA translation is
> subject to a "normal" protection match instead of a load operation match.
>
OK, maybe we should make 8xx specifics cache flushing functions, that
use the SPR, and forget about this mess.
However is this problem also triggered by user space? If it is we should
try to maintain compatibility...
> The behavior of these operations isn't consistent across all of the 8xx
> processor revisions, especially with early silicon if people are still
> using those. During conversations with Freescale engineers, it seems
> the only guaranteed operation was to use the 8xx unique SPRs, but
> I think I only did that in 8xx specific functions.
>
> We have way too much code in the TLB exception handlers already,
> so let's just try a tlbia of the EA in the update_mmu_cache, with an #ifdef
> for the 8xx. It seems if the dcbst causes a TLB miss during execution,
> it does the right thing. We may want to make the dcbxxx instructions some
> kind of macro, so on 8xx we can include such operations in otherwise
> "standard" software.
>
> Thanks for the great work!
>
>
> -- Dan
>
>
>
Regards
Pantelis
^ permalink raw reply
* Linux port for MPC5200.
From: Surendra Yadav @ 2005-04-06 4:48 UTC (permalink / raw)
To: linuxppc-dev
Hi All,
Can anyone suggest me which linux port I can use for MPC5200.
I tried linux 2.4.7 but it is not working. I am new to the linux porting.
If any one gives links to the working port that will be nice to me.
Thanks.
Regards,
Surendra
^ permalink raw reply
* Re: PREP sym53c8xx sym53c8xx brokeness due to 2.6.9-rc1-bk1 introduced residual data patch ...
From: Christian @ 2005-04-06 1:58 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Tom Rini
In-Reply-To: <42533FA1.1070001@gmx.net>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Christian wrote:
> i booted vanilla 2.6.11.6 with noresidual (and "nopresidual" too, as Sven
> sugggested), but the scsi errors did not went away :(
um, no, worse that that: the scsi error kicks in for sym0:0:0:
sym0:0:0: DEVICE RESET operation started.
(...then it would continue until sym0:15:0, see [1])
then the machine locked up completely, not even SYSRQ works any more.
that happened when booting with "noresidual" and even with PREP_RESIDUAL=n
(in the .config).
thanks,
Christian.
[1] http://nerdbynature.de/bits/hal/2.6.11-rc5/dmesg
- --
BOFH excuse #48:
bad ether in the cables
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^ permalink raw reply
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