* Re: [PATCH 2.6.12-rc2] Freescale 8272ADS PCI bridge support to thestock linux-2.5 (updated)
From: Vitaly Bordug @ 2005-04-29 11:28 UTC (permalink / raw)
To: Kumar Gala; +Cc: Tom Rini, linuxppc-embedded list
In-Reply-To: <7c4c26a737f9d366040482e49f3ca004@freescale.com>
[-- Attachment #1: Type: text/plain, Size: 758 bytes --]
Kumar,
This is what currently intended to represent on-chip PCI bridge support
for PQ2 family.
It's approved working on my 8272 and have a very good probably of the
same on the PQ2FADS-VR board. It contains low-level (SIUMCR & CPLD IC
chip select ) setup only for 8272 and PQ2FADS, considering that u-boot
does this stuff for 8266 boards. The actual source files are renamed to
m82xx_pci.[ch].
Rune, can you test this for m8266/8265 ? I guess while IRQ stuff is
nearly the same, this _should_ work as is or with minimum effort. Note
that you'll need to define PCI_INT_TO_SIU in platforms/pq2ads.h (I
suppose it's the same as PQ2FADS - SIU_INT_IRQ6, but I'm not sure).
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--
Sincerely,
Vitaly
[-- Attachment #2: PQII_pci.patch --]
[-- Type: text/x-patch, Size: 32879 bytes --]
diff -Nru a/arch/ppc/Kconfig b/arch/ppc/Kconfig
--- a/arch/ppc/Kconfig 2005-04-29 15:26:43 +04:00
+++ b/arch/ppc/Kconfig 2005-04-29 15:26:43 +04:00
@@ -1123,7 +1123,7 @@
config PCI_8260
bool
- depends on PCI && 8260 && !8272
+ depends on PCI && 8260
default y
config 8260_PCI9
diff -Nru a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
--- a/arch/ppc/platforms/pq2ads.h 2005-04-29 15:26:43 +04:00
+++ b/arch/ppc/platforms/pq2ads.h 2005-04-29 15:26:43 +04:00
@@ -49,10 +49,10 @@
/* PCI interrupt controller */
#define PCI_INT_STAT_REG 0xF8200000
#define PCI_INT_MASK_REG 0xF8200004
-#define PIRQA (NR_SIU_INTS + 0)
-#define PIRQB (NR_SIU_INTS + 1)
-#define PIRQC (NR_SIU_INTS + 2)
-#define PIRQD (NR_SIU_INTS + 3)
+#define PIRQA (NR_CPM_INTS + 0)
+#define PIRQB (NR_CPM_INTS + 1)
+#define PIRQC (NR_CPM_INTS + 2)
+#define PIRQD (NR_CPM_INTS + 3)
/*
* PCI memory map definitions for MPC8266ADS-PCI.
@@ -68,28 +68,23 @@
* 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
*/
-/* window for a PCI master to access MPC8266 memory */
-#define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */
-#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
+/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
+ Here we should redefine what is unique for this board */
+#define M82xx_PCI_SLAVE_MEM_LOCAL 0x00000000 /* Local base */
+#define M82xx_PCI_SLAVE_MEM_BUS 0x00000000 /* PCI base */
+#define M82xx_PCI_SLAVE_MEM_SIZE 0x10000000 /* 256 Mb */
+
+#define M82xx_PCI_SLAVE_SEC_WND_SIZE ~(0x40000000 - 1U) /* 2 x 512Mb */
+#define M82xx_PCI_SLAVE_SEC_WND_BASE 0x80000000 /* PCI Memory base */
+
+#if defined(CONFIG_ADS8272)
+#define PCI_INT_TO_SIU SIU_INT_IRQ2
+#elif defined(CONFIG_PQ2FADS)
+#define PCI_INT_TO_SIU SIU_INT_IRQ6
+#else
+#warning PCI Bridge will be without interrupts support
+#endif
-/* window for the processor to access PCI memory with prefetching */
-#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
-#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
-#define PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
-
-/* window for the processor to access PCI memory without prefetching */
-#define PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
-#define PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
-#define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
-
-/* window for the processor to access PCI I/O */
-#define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
-#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
-#define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
-
-#define _IO_BASE PCI_MSTR_IO_LOCAL
-#define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL
-#define PCI_DRAM_OFFSET PCI_SLV_MEM_BUS
#endif /* CONFIG_PCI */
#endif /* __MACH_ADS8260_DEFS */
diff -Nru a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
--- a/arch/ppc/syslib/Makefile 2005-04-29 15:26:43 +04:00
+++ b/arch/ppc/syslib/Makefile 2005-04-29 15:26:43 +04:00
@@ -81,7 +81,7 @@
obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
todc_time.o
obj-$(CONFIG_8260) += m8260_setup.o
-obj-$(CONFIG_PCI_8260) += m8260_pci.o indirect_pci.o
+obj-$(CONFIG_PCI_8260) += m82xx_pci.o indirect_pci.o pci_auto.o
obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o
obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
ifeq ($(CONFIG_PPC_GEN550),y)
diff -Nru a/arch/ppc/syslib/m8260_pci.c b/arch/ppc/syslib/m8260_pci.c
--- a/arch/ppc/syslib/m8260_pci.c 2005-04-29 15:26:43 +04:00
+++ /dev/null Wed Dec 31 16:00:00 196900
@@ -1,194 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004 Red Hat, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/immap_cpm2.h>
-#include <asm/mpc8260.h>
-
-#include "m8260_pci.h"
-
-
-/* PCI bus configuration registers.
- */
-
-static void __init m8260_setup_pci(struct pci_controller *hose)
-{
- volatile cpm2_map_t *immap = cpm2_immr;
- unsigned long pocmr;
- u16 tempShort;
-
-#ifndef CONFIG_ATC /* already done in U-Boot */
- /*
- * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
- * and local bus for PCI (SIUMCR [LBPC]).
- */
- immap->im_siu_conf.siu_82xx.sc_siumcr = 0x00640000;
-#endif
-
- /* Make PCI lowest priority */
- /* Each 4 bits is a device bus request and the MS 4bits
- is highest priority */
- /* Bus 4bit value
- --- ----------
- CPM high 0b0000
- CPM middle 0b0001
- CPM low 0b0010
- PCI reguest 0b0011
- Reserved 0b0100
- Reserved 0b0101
- Internal Core 0b0110
- External Master 1 0b0111
- External Master 2 0b1000
- External Master 3 0b1001
- The rest are reserved */
- immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
-
- /* Park bus on core while modifying PCI Bus accesses */
- immap->im_siu_conf.siu_82xx.sc_ppc_acr = 0x6;
-
- /*
- * Set up master window that allows the CPU to access PCI space. This
- * window is set up using the first SIU PCIBR registers.
- */
- immap->im_memctl.memc_pcimsk0 = MPC826x_PCI_MASK;
- immap->im_memctl.memc_pcibr0 = MPC826x_PCI_BASE | PCIBR_ENABLE;
-
- /* Disable machine check on no response or target abort */
- immap->im_pci.pci_emr = cpu_to_le32(0x1fe7);
- /* Release PCI RST (by default the PCI RST signal is held low) */
- immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
-
- /* give it some time */
- mdelay(1);
-
- /*
- * Set up master window that allows the CPU to access PCI Memory (prefetch)
- * space. This window is set up using the first set of Outbound ATU registers.
- */
- immap->im_pci.pci_potar0 = cpu_to_le32(MPC826x_PCI_LOWER_MEM >> 12);
- immap->im_pci.pci_pobar0 = cpu_to_le32((MPC826x_PCI_LOWER_MEM - MPC826x_PCI_MEM_OFFSET) >> 12);
- pocmr = ((MPC826x_PCI_UPPER_MEM - MPC826x_PCI_LOWER_MEM) >> 12) ^ 0xfffff;
- immap->im_pci.pci_pocmr0 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PREFETCH_EN);
-
- /*
- * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
- * space. This window is set up using the second set of Outbound ATU registers.
- */
- immap->im_pci.pci_potar1 = cpu_to_le32(MPC826x_PCI_LOWER_MMIO >> 12);
- immap->im_pci.pci_pobar1 = cpu_to_le32((MPC826x_PCI_LOWER_MMIO - MPC826x_PCI_MMIO_OFFSET) >> 12);
- pocmr = ((MPC826x_PCI_UPPER_MMIO - MPC826x_PCI_LOWER_MMIO) >> 12) ^ 0xfffff;
- immap->im_pci.pci_pocmr1 = cpu_to_le32(pocmr | POCMR_ENABLE);
-
- /*
- * Set up master window that allows the CPU to access PCI IO space. This window
- * is set up using the third set of Outbound ATU registers.
- */
- immap->im_pci.pci_potar2 = cpu_to_le32(MPC826x_PCI_IO_BASE >> 12);
- immap->im_pci.pci_pobar2 = cpu_to_le32(MPC826x_PCI_LOWER_IO >> 12);
- pocmr = ((MPC826x_PCI_UPPER_IO - MPC826x_PCI_LOWER_IO) >> 12) ^ 0xfffff;
- immap->im_pci.pci_pocmr2 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PCI_IO);
-
- /*
- * Set up slave window that allows PCI masters to access MPC826x local memory.
- * This window is set up using the first set of Inbound ATU registers
- */
-
- immap->im_pci.pci_pitar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_LOCAL >> 12);
- immap->im_pci.pci_pibar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_BUS >> 12);
- pocmr = ((MPC826x_PCI_SLAVE_MEM_SIZE-1) >> 12) ^ 0xfffff;
- immap->im_pci.pci_picmr0 = cpu_to_le32(pocmr | PICMR_ENABLE | PICMR_PREFETCH_EN);
-
- /* See above for description - puts PCI request as highest priority */
- immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
-
- /* Park the bus on the PCI */
- immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
-
- /* Host mode - specify the bridge as a host-PCI bridge */
- early_write_config_word(hose, 0, 0, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_HOST);
-
- /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
- early_read_config_word(hose, 0, 0, PCI_COMMAND, &tempShort);
- early_write_config_word(hose, 0, 0, PCI_COMMAND,
- tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-}
-
-void __init m8260_find_bridges(void)
-{
- extern int pci_assign_all_busses;
- struct pci_controller * hose;
-
- pci_assign_all_busses = 1;
-
- hose = pcibios_alloc_controller();
-
- if (!hose)
- return;
-
- ppc_md.pci_swizzle = common_swizzle;
-
- hose->first_busno = 0;
- hose->bus_offset = 0;
- hose->last_busno = 0xff;
-
- setup_m8260_indirect_pci(hose,
- (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
- (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
-
- m8260_setup_pci(hose);
- hose->pci_mem_offset = MPC826x_PCI_MEM_OFFSET;
-
- isa_io_base =
- (unsigned long) ioremap(MPC826x_PCI_IO_BASE,
- MPC826x_PCI_IO_SIZE);
- hose->io_base_virt = (void *) isa_io_base;
-
- /* setup resources */
- pci_init_resource(&hose->mem_resources[0],
- MPC826x_PCI_LOWER_MEM,
- MPC826x_PCI_UPPER_MEM,
- IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
-
- pci_init_resource(&hose->mem_resources[1],
- MPC826x_PCI_LOWER_MMIO,
- MPC826x_PCI_UPPER_MMIO,
- IORESOURCE_MEM, "PCI memory");
-
- pci_init_resource(&hose->io_resource,
- MPC826x_PCI_LOWER_IO,
- MPC826x_PCI_UPPER_IO,
- IORESOURCE_IO, "PCI I/O");
-}
diff -Nru a/arch/ppc/syslib/m8260_pci.h b/arch/ppc/syslib/m8260_pci.h
--- a/arch/ppc/syslib/m8260_pci.h 2005-04-29 15:26:43 +04:00
+++ /dev/null Wed Dec 31 16:00:00 196900
@@ -1,76 +0,0 @@
-
-#ifndef _PPC_KERNEL_M8260_PCI_H
-#define _PPC_KERNEL_M8260_PCI_H
-
-#include <asm/m8260_pci.h>
-
-/*
- * Local->PCI map (from CPU) controlled by
- * MPC826x master window
- *
- * 0x80000000 - 0xBFFFFFFF Total CPU2PCI space PCIBR0
- *
- * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
- * 0xA0000000 - 0xAFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
- * 0xB0000000 - 0xB0FFFFFF 32-bit PCI IO (Outbound ATU #3)
- *
- * PCI->Local map (from PCI)
- * MPC826x slave window controlled by
- *
- * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
- */
-
-/*
- * Slave window that allows PCI masters to access MPC826x local memory.
- * This window is set up using the first set of Inbound ATU registers
- */
-
-#ifndef MPC826x_PCI_SLAVE_MEM_LOCAL
-#define MPC826x_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart)
-#define MPC826x_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart)
-#define MPC826x_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize)
-#endif
-
-/*
- * This is the window that allows the CPU to access PCI address space.
- * It will be setup with the SIU PCIBR0 register. All three PCI master
- * windows, which allow the CPU to access PCI prefetch, non prefetch,
- * and IO space (see below), must all fit within this window.
- */
-#ifndef MPC826x_PCI_BASE
-#define MPC826x_PCI_BASE 0x80000000
-#define MPC826x_PCI_MASK 0xc0000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_MEM
-#define MPC826x_PCI_LOWER_MEM 0x80000000
-#define MPC826x_PCI_UPPER_MEM 0x9fffffff
-#define MPC826x_PCI_MEM_OFFSET 0x00000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_MMIO
-#define MPC826x_PCI_LOWER_MMIO 0xa0000000
-#define MPC826x_PCI_UPPER_MMIO 0xafffffff
-#define MPC826x_PCI_MMIO_OFFSET 0x00000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_IO
-#define MPC826x_PCI_LOWER_IO 0x00000000
-#define MPC826x_PCI_UPPER_IO 0x00ffffff
-#define MPC826x_PCI_IO_BASE 0xb0000000
-#define MPC826x_PCI_IO_SIZE 0x01000000
-#endif
-
-#ifndef _IO_BASE
-#define _IO_BASE isa_io_base
-#endif
-
-#ifdef CONFIG_8260_PCI9
-struct pci_controller;
-extern void setup_m8260_indirect_pci(struct pci_controller* hose,
- u32 cfg_addr, u32 cfg_data);
-#else
-#define setup_m8260_indirect_pci setup_indirect_pci
-#endif
-
-#endif /* _PPC_KERNEL_M8260_PCI_H */
diff -Nru a/arch/ppc/syslib/m8260_pci_erratum9.c b/arch/ppc/syslib/m8260_pci_erratum9.c
--- a/arch/ppc/syslib/m8260_pci_erratum9.c 2005-04-29 15:26:43 +04:00
+++ b/arch/ppc/syslib/m8260_pci_erratum9.c 2005-04-29 15:26:43 +04:00
@@ -248,11 +248,11 @@
static inline int is_pci_mem(unsigned long addr)
{
- if (addr >= MPC826x_PCI_LOWER_MMIO &&
- addr <= MPC826x_PCI_UPPER_MMIO)
+ if (addr >= M82xx_PCI_LOWER_MMIO &&
+ addr <= M82xx_PCI_UPPER_MMIO)
return 1;
- if (addr >= MPC826x_PCI_LOWER_MEM &&
- addr <= MPC826x_PCI_UPPER_MEM)
+ if (addr >= M82xx_PCI_LOWER_MEM &&
+ addr <= M82xx_PCI_UPPER_MEM)
return 1;
return 0;
}
diff -Nru a/arch/ppc/syslib/m8260_setup.c b/arch/ppc/syslib/m8260_setup.c
--- a/arch/ppc/syslib/m8260_setup.c 2005-04-29 15:26:43 +04:00
+++ b/arch/ppc/syslib/m8260_setup.c 2005-04-29 15:26:43 +04:00
@@ -34,7 +34,8 @@
unsigned char __res[sizeof(bd_t)];
extern void cpm2_reset(void);
-extern void m8260_find_bridges(void);
+extern void pq2_find_bridges(void);
+extern void pq2pci_init_irq(void);
extern void idma_pci9_init(void);
/* Place-holder for board-specific init */
@@ -56,7 +57,7 @@
idma_pci9_init();
#endif
#ifdef CONFIG_PCI_8260
- m8260_find_bridges();
+ pq2_find_bridges();
#endif
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
@@ -173,6 +174,12 @@
* in case the boot rom changed something on us.
*/
cpm2_immr->im_intctl.ic_siprr = 0x05309770;
+
+#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS))
+ /* Initialize stuff for the 82xx CPLD IC and install demux */
+ pq2pci_init_irq();
+#endif
+
}
/*
diff -Nru a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/m82xx_pci.c 2005-04-29 15:26:43 +04:00
@@ -0,0 +1,383 @@
+/*
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004 Red Hat, Inc.
+ *
+ * 2005 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/immap_cpm2.h>
+#include <asm/mpc8260.h>
+#include <asm/cpm2.h>
+
+#include "m82xx_pci.h"
+
+/*
+ * Interrupt routing
+ */
+
+static inline int
+pq2pci_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */
+ { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */
+ { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */
+ };
+
+ const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void
+pq2pci_mask_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_unmask_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_mask_and_ack(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_end_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+struct hw_interrupt_type pq2pci_ic = {
+ "PQ2 PCI",
+ NULL,
+ NULL,
+ pq2pci_unmask_irq,
+ pq2pci_mask_irq,
+ pq2pci_mask_and_ack,
+ pq2pci_end_irq,
+ 0
+};
+
+static irqreturn_t
+pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
+{
+ unsigned long stat, mask, pend;
+ int bit;
+
+ for(;;) {
+ stat = *(volatile unsigned long *) PCI_INT_STAT_REG;
+ mask = *(volatile unsigned long *) PCI_INT_MASK_REG;
+ pend = stat & ~mask & 0xf0000000;
+ if (!pend)
+ break;
+ for (bit = 0; pend != 0; ++bit, pend <<= 1) {
+ if (pend & 0x80000000)
+ __do_IRQ(NR_CPM_INTS + bit, regs);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction pq2pci_irqaction = {
+ .handler = pq2pci_irq_demux,
+ .flags = SA_INTERRUPT,
+ .mask = CPU_MASK_NONE,
+ .name = "PQ2 PCI cascade",
+};
+
+
+void
+pq2pci_init_irq(void)
+{
+ int irq;
+ volatile cpm2_map_t *immap = cpm2_immr;
+#ifdef CONFIG_ADS8272
+ /* configure chip select for PCI interrupt controller */
+ immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or3 = 0xffff8010;
+#elif defined CONFIG_PQ2FADS
+ immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or8 = 0xffff8010;
+#endif
+ for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
+ irq_desc[irq].handler = &pq2pci_ic;
+
+ /* make PCI IRQ level sensitive */
+ immap->im_intctl.ic_siexr &=
+ ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1)));
+
+ /* mask all PCI interrupts */
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
+
+ /* install the demultiplexer for the PCI cascade interrupt */
+ setup_irq(PCI_INT_TO_SIU, &pq2pci_irqaction);
+ return;
+}
+
+static int
+pq2pci_exclude_device(u_char bus, u_char devfn)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/* PCI bus configuration registers.
+ */
+static void
+pq2ads_setup_pci(struct pci_controller *hose)
+{
+ __u32 val;
+ volatile cpm2_map_t *immap = cpm2_immr;
+ bd_t* binfo = (bd_t*) __res;
+ u32 sccr = immap->im_clkrst.car_sccr;
+ uint pci_div,freq,time;
+ /* PCI int lowest prio */
+ /* Each 4 bits is a device bus request and the MS 4bits
+ is highest priority */
+ /* Bus 4bit value
+ --- ----------
+ CPM high 0b0000
+ CPM middle 0b0001
+ CPM low 0b0010
+ PCI reguest 0b0011
+ Reserved 0b0100
+ Reserved 0b0101
+ Internal Core 0b0110
+ External Master 1 0b0111
+ External Master 2 0b1000
+ External Master 3 0b1001
+ The rest are reserved
+ */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
+ /* park bus on core */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;
+ /*
+ * Set up master windows that allow the CPU to access PCI space. These
+ * windows are set up using the two SIU PCIBR registers.
+ */
+
+ immap->im_memctl.memc_pcimsk0 = M82xx_PCI_PRIM_WND_SIZE;
+ immap->im_memctl.memc_pcibr0 = M82xx_PCI_PRIM_WND_BASE | PCIBR_ENABLE;
+
+#ifdef M82xx_PCI_SEC_WND_SIZE
+ immap->im_memctl.memc_pcimsk1 = M82xx_PCI_SEC_WND_SIZE;
+ immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE;
+#endif
+
+#ifdef CONFIG_ADS8272
+ immap->im_siu_conf.siu_82xx.sc_siumcr =
+ (immap->im_siu_conf.siu_82xx.sc_siumcr &
+ ~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE |
+ SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 |
+ SIUMCR_LBPC11 | SIUMCR_APPC11 |
+ SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) |
+ SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 |
+ SIUMCR_APPC10 | SIUMCR_CS10PC00 |
+ SIUMCR_BCTLC00 | SIUMCR_MMR11 ;
+
+#elif defined CONFIG_PQ2FADS
+ /*
+ * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
+ * and local bus for PCI (SIUMCR [LBPC]).
+ */
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
+ SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10;
+#endif
+ /* Enable PCI */
+ immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
+
+ pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
+ ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
+ freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div));
+ time = (int)666666/freq;
+ /* due to PCI Local Bus spec, some devices needs to wait such a long
+ time after RST deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */
+ printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq,
+ (time==1) ? "0.5 seconds":"1 second" );
+
+ {
+ int i;
+ for(i=0;i<(500*time);i++)
+ udelay(1000);
+ }
+
+ /* setup ATU registers */
+ immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |
+ ((~(M82xx_PCI_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar0 = cpu_to_le32(M82xx_PCI_LOWER_IO >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar0 = cpu_to_le32(M82xx_PCI_IO_BASE >> POTA_ADDR_SHIFT);
+
+ /* Set-up non-prefetchable window */
+ immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(M82xx_PCI_MMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar1 = cpu_to_le32(M82xx_PCI_LOWER_MMIO >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar1 = cpu_to_le32((M82xx_PCI_LOWER_MMIO - M82xx_PCI_MMIO_OFFSET) >> POTA_ADDR_SHIFT);
+
+ /* Set-up prefetchable window */
+ immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |
+ (~(M82xx_PCI_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar2 = cpu_to_le32(M82xx_PCI_LOWER_MEM >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar2 = cpu_to_le32((M82xx_PCI_LOWER_MEM - M82xx_PCI_MEM_OFFSET) >> POTA_ADDR_SHIFT);
+
+ /* Inbound transactions from PCI memory space */
+ immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN |
+ ((~(M82xx_PCI_SLAVE_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT));
+ immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT);
+ immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT);
+
+#if defined CONFIG_ADS8272
+ /* PCI int highest prio */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
+#elif defined CONFIG_PQ2FADS
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
+#endif
+ /* park bus on PCI */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
+
+ /* Enable bus mastering and inbound memory transactions */
+ early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);
+ val &= 0xffff0000;
+ val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
+ early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);
+
+}
+
+void __init pq2_find_bridges(void)
+{
+ extern int pci_assign_all_busses;
+ struct pci_controller * hose;
+ int host_bridge;
+
+ pci_assign_all_busses = 1;
+
+ hose = pcibios_alloc_controller();
+
+ if (!hose)
+ return;
+
+ ppc_md.pci_swizzle = common_swizzle;
+
+ hose->first_busno = 0;
+ hose->bus_offset = 0;
+ hose->last_busno = 0xff;
+
+#ifdef CONFIG_ADS8272
+ hose->set_cfg_type = 1;
+#endif
+
+ setup_m8260_indirect_pci(hose,
+ (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
+ (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
+
+ /* Make sure it is a supported bridge */
+ early_read_config_dword(hose,
+ 0,
+ PCI_DEVFN(0,0),
+ PCI_VENDOR_ID,
+ &host_bridge);
+ switch (host_bridge) {
+ case PCI_DEVICE_ID_MPC8265:
+ break;
+ case PCI_DEVICE_ID_MPC8272:
+ break;
+ default:
+ printk("Attempting to use unrecognized host bridge ID"
+ " 0x%08x.\n", host_bridge);
+ break;
+ }
+
+ pq2ads_setup_pci(hose);
+
+ hose->io_space.start = M82xx_PCI_LOWER_IO;
+ hose->io_space.end = M82xx_PCI_UPPER_IO;
+ hose->mem_space.start = M82xx_PCI_LOWER_MEM;
+ hose->mem_space.end = M82xx_PCI_UPPER_MMIO;
+ hose->pci_mem_offset = M82xx_PCI_MEM_OFFSET;
+
+ isa_io_base =
+ (unsigned long) ioremap(M82xx_PCI_IO_BASE,
+ M82xx_PCI_IO_SIZE);
+ hose->io_base_virt = (void *) isa_io_base;
+
+ /* setup resources */
+ pci_init_resource(&hose->mem_resources[0],
+ M82xx_PCI_LOWER_MEM,
+ M82xx_PCI_UPPER_MEM,
+ IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
+
+ pci_init_resource(&hose->mem_resources[1],
+ M82xx_PCI_LOWER_MMIO,
+ M82xx_PCI_UPPER_MMIO,
+ IORESOURCE_MEM, "PCI memory");
+
+ pci_init_resource(&hose->io_resource,
+ M82xx_PCI_LOWER_IO,
+ M82xx_PCI_UPPER_IO,
+ IORESOURCE_IO | 1, "PCI I/O");
+
+ ppc_md.pci_exclude_device = pq2pci_exclude_device;
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+ ppc_md.pci_map_irq = pq2pci_map_irq;
+ ppc_md.pcibios_fixup = NULL;
+ ppc_md.pcibios_fixup_bus = NULL;
+
+}
diff -Nru a/arch/ppc/syslib/m82xx_pci.h b/arch/ppc/syslib/m82xx_pci.h
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/m82xx_pci.h 2005-04-29 15:26:43 +04:00
@@ -0,0 +1,92 @@
+
+#ifndef _PPC_KERNEL_M82XX_PCI_H
+#define _PPC_KERNEL_M82XX_PCI_H
+
+#include <asm/m8260_pci.h>
+/*
+ * Local->PCI map (from CPU) controlled by
+ * MPC826x master window
+ *
+ * 0xF6000000 - 0xF7FFFFFF IO space
+ * 0x80000000 - 0xBFFFFFFF CPU2PCI memory space PCIBR0
+ *
+ * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
+ * 0xA0000000 - 0xBFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
+ * 0xF6000000 - 0xF7FFFFFF 32-bit PCI IO (Outbound ATU #3)
+ *
+ * PCI->Local map (from PCI)
+ * MPC826x slave window controlled by
+ *
+ * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
+ */
+
+/*
+ * Slave window that allows PCI masters to access MPC826x local memory.
+ * This window is set up using the first set of Inbound ATU registers
+ */
+
+#ifndef M82xx_PCI_SLAVE_MEM_LOCAL
+#define M82xx_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart)
+#define M82xx_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart)
+#define M82xx_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize)
+#endif
+
+/*
+ * This is the window that allows the CPU to access PCI address space.
+ * It will be setup with the SIU PCIBR0 register. All three PCI master
+ * windows, which allow the CPU to access PCI prefetch, non prefetch,
+ * and IO space (see below), must all fit within this window.
+ */
+
+#ifndef M82xx_PCI_LOWER_MEM
+#define M82xx_PCI_LOWER_MEM 0x80000000
+#define M82xx_PCI_UPPER_MEM 0x9fffffff
+#define M82xx_PCI_MEM_OFFSET 0x00000000
+#define M82xx_PCI_MEM_SIZE 0x20000000
+#endif
+
+#ifndef M82xx_PCI_LOWER_MMIO
+#define M82xx_PCI_LOWER_MMIO 0xa0000000
+#define M82xx_PCI_UPPER_MMIO 0xafffffff
+#define M82xx_PCI_MMIO_OFFSET 0x00000000
+#define M82xx_PCI_MMIO_SIZE 0x20000000
+#endif
+
+#ifndef M82xx_PCI_LOWER_IO
+#define M82xx_PCI_LOWER_IO 0x00000000
+#define M82xx_PCI_UPPER_IO 0x01ffffff
+#define M82xx_PCI_IO_BASE 0xf6000000
+#define M82xx_PCI_IO_SIZE 0x02000000
+#endif
+
+#ifndef M82xx_PCI_PRIM_WND_SIZE
+#define M82xx_PCI_PRIM_WND_SIZE ~(M82xx_PCI_IO_SIZE - 1U)
+#define M82xx_PCI_PRIM_WND_BASE (M82xx_PCI_IO_BASE)
+#endif
+
+#ifndef M82xx_PCI_SEC_WND_SIZE
+#define M82xx_PCI_SEC_WND_SIZE ~(M82xx_PCI_MEM_SIZE + M82xx_PCI_MMIO_SIZE - 1U)
+#define M82xx_PCI_SEC_WND_BASE (M82xx_PCI_LOWER_MEM)
+#endif
+
+#ifndef POTA_ADDR_SHIFT
+#define POTA_ADDR_SHIFT 12
+#endif
+
+#ifndef PITA_ADDR_SHIFT
+#define PITA_ADDR_SHIFT 12
+#endif
+
+#ifndef _IO_BASE
+#define _IO_BASE isa_io_base
+#endif
+
+#ifdef CONFIG_8260_PCI9
+struct pci_controller;
+extern void setup_m8260_indirect_pci(struct pci_controller* hose,
+ u32 cfg_addr, u32 cfg_data);
+#else
+#define setup_m8260_indirect_pci setup_indirect_pci
+#endif
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */
diff -Nru a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
--- a/include/asm-ppc/cpm2.h 2005-04-29 15:26:43 +04:00
+++ b/include/asm-ppc/cpm2.h 2005-04-29 15:26:43 +04:00
@@ -1039,6 +1039,52 @@
#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register 4-31
+ */
+#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
+#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
+#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
+#define SIUMCR_CDIS 0x10000000 /* Core Disable */
+#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01 0x04000000 /* - " - */
+#define SIUMCR_DPPC10 0x08000000 /* - " - */
+#define SIUMCR_DPPC11 0x0c000000 /* - " - */
+#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
+#define SIUMCR_L2CPC01 0x01000000 /* - " - */
+#define SIUMCR_L2CPC10 0x02000000 /* - " - */
+#define SIUMCR_L2CPC11 0x03000000 /* - " - */
+#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
+#define SIUMCR_LBPC01 0x00400000 /* - " - */
+#define SIUMCR_LBPC10 0x00800000 /* - " - */
+#define SIUMCR_LBPC11 0x00c00000 /* - " - */
+#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01 0x00100000 /* - " - */
+#define SIUMCR_APPC10 0x00200000 /* - " - */
+#define SIUMCR_APPC11 0x00300000 /* - " - */
+#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
+#define SIUMCR_CS10PC01 0x00040000 /* - " - */
+#define SIUMCR_CS10PC10 0x00080000 /* - " - */
+#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
+#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
+#define SIUMCR_BCTLC01 0x00010000 /* - " - */
+#define SIUMCR_BCTLC10 0x00020000 /* - " - */
+#define SIUMCR_BCTLC11 0x00030000 /* - " - */
+#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
+#define SIUMCR_MMR01 0x00004000 /* - " - */
+#define SIUMCR_MMR10 0x00008000 /* - " - */
+#define SIUMCR_MMR11 0x0000c000 /* - " - */
+#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control Register 9-8
+ */
+#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
+#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
+#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
+#define SCCR_PCIDF_SHIFT 3
+
+
#endif /* __CPM2__ */
#endif /* __KERNEL__ */
diff -Nru a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
--- a/include/asm-ppc/m8260_pci.h 2005-04-29 15:26:43 +04:00
+++ b/include/asm-ppc/m8260_pci.h 2005-04-29 15:26:43 +04:00
@@ -19,6 +19,7 @@
* Define the vendor/device ID for the MPC8265.
*/
#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
#define M8265_PCIBR0 0x101ac
#define M8265_PCIBR1 0x101b0
diff -Nru a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
--- a/include/asm-ppc/mpc8260.h 2005-04-29 15:26:43 +04:00
+++ b/include/asm-ppc/mpc8260.h 2005-04-29 15:26:43 +04:00
@@ -41,7 +41,7 @@
#endif
#ifdef CONFIG_PCI_8260
-#include <syslib/m8260_pci.h>
+#include <syslib/m82xx_pci.h>
#endif
/* Make sure the memory translation stuff is there if PCI not used.
^ permalink raw reply
* Re: porting linux on power pc mpc8xx
From: David Jander @ 2005-04-29 11:40 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <BAY17-F312F5680735EFB466C3993BE240@phx.gbl>
Hi Prinson,
On Friday 29 April 2005 12:32, prinson varghese wrote:
> I am new to the embedded system development .How i can port linux kenel to
> power pc MPC 8XX
It is already ported to most known mpc8xx devices. You should start off, going
through the archives of this mailing-list, and visit this site:
http://www.denx.de
There you can download actual sources of linux-2.4 kernels. My advice, use
linux_2_4_devel cvs tree if you have no particular reason to use another
tree.
What processor do you use? What board? Is it a custom design or an existing
board?
You might be interested in u-boot also (the most commonly used bootloader for
these kind of embedded processors).
> and where i can get the kernel for the same?
www.denx.de, but probably also from www.mvista.com, and many others.
> awaiting rpaly ASAP
I am OK with this, but "ASAP" does not sound as polite as you should be
addressing a mailing list ;-)
Sincerely,
--
David Jander
Protonic Holland.
^ permalink raw reply
* Embedded Linux on PQ III
From: Steven Russ @ 2005-04-29 12:45 UTC (permalink / raw)
To: linuxppc-embedded
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=us-ascii, Size: 672 bytes --]
I came across this site that has a PowerQUICC III with embedded linux, online so you can test it out. You are able to access a remote desktop that has the eval board set-up in a way that you can control the hardware, write code and download it to the board. They even have a licensed version of CodeWarrior to use. They don’t even charge you to use it. I’ve been on it for hours since I broke my MPC8260ADS ECOM board. Has anyone else seen these? http://www.techonline.com/community/ed_resource/virtualab/37245
__________________________________________________
Do You Yahoo!?
Tired of spam? Yahoo! Mail has the best spam protection around
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[-- Attachment #2: Type: text/html, Size: 1063 bytes --]
^ permalink raw reply
* Performance issue - VoIP application on Linux 2.4.22
From: bobys @ 2005-04-29 15:01 UTC (permalink / raw)
To: linuxppc-embedded
Hello everybody,
I have a multithreaded VoIP application in user space and a kernel driver
module on MPC 8248 based board.
During media data transfer( Video Call) I have observed one strange behavior
that at specific interval, cpu utilization is reaching to 100 % and then
rolls back to 0 %. This behavior repeats at regular intervals of time
during the call.
During this time, data rate and memory utilization is constant throughout
the Call. Also number of interrupts received and processed in the kernel
driver is constant. We have checked the code many times, but couldn't find
any of the threads/driver hogging the processor time.
We are using Linux kernel 2.4.22 with kernel preemption enabled and low
latency patch added. Please let me know anybody have seen same behavior and
how to sort this out.
Thanks and Regards
Boby
^ permalink raw reply
* problem compiling linux with ELDK: `bd_t' undeclared
From: Peter Asemann @ 2005-04-29 15:47 UTC (permalink / raw)
To: linuxppc-embedded
Hi there!
I'm having a problem compiling Linux 2.4.25 as included in ELDK version
3.1 / Build 2004-11-10.
When trying to compile ppc_8xx/usr/src/linux-2.4.25/drivers/char/flash.c
it throws an error:
ppc_8xx-gcc -D__KERNEL__
-I/opt/asemann/eldk/ppc_8xx/usr/src/linux-2.4.25/include -Wall
-Wstrict-prototypes -Wno-trigraphs -O2 -fno-strict-aliasing -fno-common
-fomit-frame-pointer
-I/opt/asemann/eldk/ppc_8xx/usr/src/linux-2.4.25/arch/ppc -fsigned-char
-msoft-float -pipe -ffixed-r2 -Wno-uninitialized -mmultiple -mstring
-nostdinc -I /opt/asemann/eldk/usr/lib/gcc-lib/ppc-linux/3.3.3/include
-DKBUILD_BASENAME=flash -c -o flash.o flash.c
flash.c: In function `flash_init':
flash.c:446: error: `bd_t' undeclared (first use in this function)
flash.c:446: error: (Each undeclared identifier is reported only once
flash.c:446: error: for each function it appears in.)
flash.c:446: error: `bd' undeclared (first use in this function)
flash.c:446: error: parse error before ')' token
make[3]: *** [flash.o] Error 1
It looks like it misses ppcboot.h or something. Is there something I
need to select in the kernel configuration to get rid of that error?
Thanks for reading,
Peter Asemann
^ permalink raw reply
* Re: rsync mirrors of linuxppc-* on source.mvista.com
From: David Woodhouse @ 2005-04-29 17:44 UTC (permalink / raw)
To: Tom Rini; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <20050428153733.GD1221@smtp.west.cox.net>
On Thu, 2005-04-28 at 08:37 -0700, Tom Rini wrote:
> With the shift away from BitKeeper, and with PowerPC work having long
> shifted away from the linuxppc-* bitkeeper trees and towards a more
> direct relationship with Andrew / et al, is there any value in keeping
> the rsync mirrors of the last state of the linuxppc-* trees available?
>
> As there's no metadata, my slant is towards no. But it wouldn't be hard
> to have these still exist, if people speak up.
You could just convert them to git format?
--
dwmw2
^ permalink raw reply
* Re: rsync mirrors of linuxppc-* on source.mvista.com
From: Tom Rini @ 2005-04-29 17:57 UTC (permalink / raw)
To: David Woodhouse; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <1114796691.27227.224.camel@hades.cambridge.redhat.com>
On Fri, Apr 29, 2005 at 06:44:50PM +0100, David Woodhouse wrote:
> On Thu, 2005-04-28 at 08:37 -0700, Tom Rini wrote:
> > With the shift away from BitKeeper, and with PowerPC work having long
> > shifted away from the linuxppc-* bitkeeper trees and towards a more
> > direct relationship with Andrew / et al, is there any value in keeping
> > the rsync mirrors of the last state of the linuxppc-* trees available?
> >
> > As there's no metadata, my slant is towards no. But it wouldn't be hard
> > to have these still exist, if people speak up.
>
> You could just convert them to git format?
The linuxppc-* trees? They really aren't useful nowadays. Maybe the
linuxppc-2.4 tree should be, assuming Marcelo switches to git, and
there's some desire to continue the practice of letting work that's done
vs 2.4 exist somewhere in the community and added to.
But for 2.6, thankfully, folks are either using quilt (or similar) to
track their own work, or a project-specific tree, which I fully expect
to become git trees. I think we can finally kill the notion of a
'master' PPC tree that's not Linus' tree, via Andrew's tree.
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply
* Re: [PATCH] ppc32: backport Book-E decrementer handling fix from 2.6
From: Marcelo Tosatti @ 2005-04-29 13:56 UTC (permalink / raw)
To: Matt Porter, Paul Mackerras, Kumar Gala, linuxppc-embedded
In-Reply-To: <20050426184828.GA22714@gate.ebshome.net>
On Tue, Apr 26, 2005 at 11:48:28AM -0700, Eugene Surovegin wrote:
> Marcelo,
>
> this is backport of Matt Porter's patch for Book-E decrementer
> handling in timer_interrupt.
>
> The fix has been in 2.6 from August but never made it to 2.4, and I
> re-discovered this fix last week :)
>
> Original Matt's post to linuxppc-dev with explanation can be found at:
> http://ozlabs.org/pipermail/linuxppc-dev/2004-August/017458.html
Applied, thanks.
> Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
>
> ===== arch/ppc/kernel/time.c 1.16 vs edited =====
> --- 1.16/arch/ppc/kernel/time.c 2003-07-03 09:56:34 -07:00
> +++ edited/arch/ppc/kernel/time.c 2005-04-26 11:37:58 -07:00
> @@ -150,7 +150,7 @@
>
> hardirq_enter(cpu);
>
> - while ((next_dec = tb_ticks_per_jiffy - tb_delta(&jiffy_stamp)) < 0) {
> + while ((next_dec = tb_ticks_per_jiffy - tb_delta(&jiffy_stamp)) <= 0) {
> jiffy_stamp += tb_ticks_per_jiffy;
> if (!user_mode(regs))
> ppc_do_profile(instruction_pointer(regs));
^ permalink raw reply
* RE: gcc 3.4.3 on e500 (was Linux Kernel Issue: MPC8540 Errata (CPU29))
From: Chiradeep Vittal @ 2005-04-29 19:16 UTC (permalink / raw)
To: Kumar Gala, kylo; +Cc: linuxppc-embedded
We're planning to drop back to gcc-3.2.3 (built for 8245) for now.=20
Do you think there will be a substantial performance penalty for this?
Thanks
--
Chiradeep
-----Original Message-----
From: Kumar Gala [mailto:kumar.gala@freescale.com]=20
Sent: Thursday, April 28, 2005 4:19 PM
To: kylo@kylo.net
Cc: linuxppc-embedded@ozlabs.org; Chiradeep Vittal
Subject: Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
All of the suggestions are good ones.. Also, in 2.6 I've recently =20
submitted patches that add emulation of these instructions in the =20
kernel.
Its odd, but I would have expected a GCC configured for e500 not to =20
generate the ld/st string instructions by default, but the -mno-string =20
is what we do in the kernel to ensure that.
- kumar
On Apr 28, 2005, at 5:21 PM, Kylo Ginsberg wrote:
> Chiradeep,
>
> I have the same issue with gcc3.4.3 and an e500 target.=A0 You can =
give
> gcc the -mno-string to inhibit generation of those load/store string
> instructions.=A0 I don't know if gcc can be configured such that its
> default is not to generate those instructions.
>
> Cheers,
> Kylo
>
> On 4/28/05, Chiradeep Vittal <chiradeep@matissenetworks.com> wrote:
> > It turns out to be a compiler issue.
> > We're using gcc 3.4.3 with optimization level -Os. The following =20
> program will generate the illegal instruction with -Os but not with =20
> -O2
>
> >=A0=A0=A0=A0=A0=A0=A0=A0 int main (int argc, char** argv)
> >=A0=A0=A0=A0=A0=A0=A0=A0 {
> >=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 int seq[] =3D {0, 1, 2};
> >=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return 0;
> >=A0=A0=A0=A0=A0=A0=A0=A0 }
> > The reason is that the compiler generates code with the stswi =20
> instruction which is not supported by the e500. Here's our compiler =20
> configuration:
>
> > Configured with: =20
> /home/steve/perforce/sw/opt/crosstool/build/powerpc-8540-linux-gnu/=20
> gcc-3.4.3-glibc-2.3.2/gcc-3.4.3/configure =20
> --target=3Dpowerpc-8540-linux-gnu --host=3Di686-host_pc-linux-gnu =20
> =
--prefix=3D/home/steve/perforce/sw/opt/cross-compile/powerpc-8540-linux- =
> gnu/gcc-3.4.3-glibc-2.3.2 --with-cpu=3D8540 =20
> --enable-cxx-flags=3D-mcpu=3D8540 =20
> =
--with-headers=3D/home/steve/perforce/sw/opt/cross-compile/powerpc-8540- =
> linux-gnu/gcc-3.4.3-glibc-2.3.2/powerpc-8540-linux-gnu/include =20
> =
--with-local-prefix=3D/home/steve/perforce/sw/opt/cross-compile/powerpc=20
> -8540-linux-gnu/gcc-3.4.3-glibc-2.3.2/powerpc-8540-linux-gnu =20
> --disable-nls --enable-threads=3Dposix --enable-symvers=3Dgnu =20
> --enable-__cxa_atexit --enable-languages=3Dc,c++ --enable-shared =20
> --enable-c99 --enable-long-long
>
> >
> > Any recommendations?
> >
> > Thanks
> > --
> > Chiradeep
> >
> > -----Original Message-----
> > From: Kumar Gala [mailto:kumar.gala@freescale.com]
> > Sent: Wednesday, April 27, 2005 11:37 AM
> > To: Chiradeep Vittal
> > Cc: linuxppc-embedded@ozlabs.org
> > Subject: Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
> >
> > On Apr 27, 2005, at 12:46 PM, Chiradeep Vittal wrote:
> >
> > > We're running Linux Kernel 2.4.26 on an 8540 ADS derivative. We're
> > >=A0 seeing an
> > > "illegal instruction" (SIGILL) exception under some circumstances
> > > (during a pthread_create call). We were wondering if this could =20
> be a
> > > symptom of
> > > CPU29 and if there is a patch available for CPU29.
> > >
> > > "CPU29 L1 instruction cache gets multiple entries for same line =20
> after
> > >=A0 change
> > > in MSR[IS] bit "
> > >
> > > www.freescale.com/files/32bit/doc/errata/MPC8540CE.pdf
> >
> > The way the Linux kernel manages the MMU on e500 it doesn't actually
> > ever modify MSR[IS] or MSR[DS].=A0 They are always zero so I dont =20
> believe
> > you are hitting this errata.
> >
> > Are you running with math emulation turned on?=A0 Do you know what =
the
> > instruction is that causes the SIGILL?
> >
> > - kumar
> >
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >
^ permalink raw reply
* gdb with pthreads on MPC8540
From: Chiradeep Vittal @ 2005-04-29 19:25 UTC (permalink / raw)
To: linuxppc-embedded
Has anybody got gdb 6.x working with the e500 (MPC85xx) to do
multithreaded debugging?
gdb gets a SIGTRAP upon a pthread_create, but doesn't seem to know what
to do with it. Seems like a simple configuration issue...
Configuration tested: Linux 2.4.26 on MPC8540 ADS derivative,
powerpc-8540-linux-gnu-gcc-3.4.3, libc-2.3.2 (libc.so.6), gdb (native)
6.2
Thanks
--
Chiradeep
^ permalink raw reply
* Re: MPC8245 custom board, Linux 2.4 kernel hangs after uncompressing
From: Kishore Devireddy @ 2005-04-29 20:54 UTC (permalink / raw)
To: Sam Song; +Cc: Atit_Shah, linuxppc-embedded
In-Reply-To: <20050422053530.43298.qmail@web15805.mail.cnb.yahoo.com>
SGkKCldoYXQgc2hvdWxkIEkgY2hhbmdlIHJlbGF0ZWQgdG8gTUNDUiB0byBkaXNhYmxlIFNEUkFN
IGJ1cnN0IG1vZGU/CgpUaGFua3MKS2lzaG9yZQoKT24gNC8yMS8wNSwgU2FtIFNvbmcgPHNhbWxp
bnV4cHBjQHlhaG9vLmNvbS5jbj4gd3JvdGU6Cj4gQXRpdF9TaGFoIDxBdGl0X1NoYWhAc2F0eWFt
LmNvbT4gd3JvdGWjugo+ID4gV2hhdCB3ZSBkaWQgd2FzIHZlcmlmaWVkIHRoZSB2YWx1ZSBvZiBQ
U0RNUiByZWdpc3Rlcgo+ID4gdmFsdWUgZm91bmQgaW4geW91ciBib2FyZCBzcGVjaWZpYyBoZWFk
ZXIgZmlsZSBpbgo+ID4gaW5jbHVkZS9jb25maWdzLzxib2FyZG5hbWUuaD4KPiAKPiBVbW1tLCBQ
U0RNUiByZWdpc3RlciBpcyBmb3IgODI2MCBwZXJoYXBzPyBJIGV2ZW4KPiBkaWRuJ3QgZmluZCBp
dCBpbiA4MjQ1VU0uIERvIHlvdSBtZWFuIE1DQ1Igb2YgODI0NT8KPiAKPiBUaGFua3MsCj4gCj4g
U2FtCj4gCj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fCj4gRG8gWW91IFlhaG9vIT8KPiAxNTDN8sf6TVAzt+i/8cvRo6y0+MT6tLPI69L0
wNa17szDCj4gaHR0cDovL211c2ljLnlpc291LmNvbS8KPiDDwMWuw/fQx9Om09C+odPQo6zL0bHp
w8DNvKGi0d7NvLrNv+HNvAo+IGh0dHA6Ly9pbWFnZS55aXNvdS5jb20KPiAxR77NyscxMDAw1dej
rNHFu6K159PK19TW+sCpyN2joQo+IGh0dHA6Ly9jbi5yZC55YWhvby5jb20vbWFpbF9jbi90YWcv
MWcvKmh0dHA6Ly9jbi5tYWlsLnlhaG9vLmNvbS9ldmVudC9tYWlsXzFnLwo+Cg==
^ permalink raw reply
* Re: problem compiling linux with ELDK: `bd_t' undeclared
From: Wolfgang Denk @ 2005-04-29 20:55 UTC (permalink / raw)
To: Peter Asemann; +Cc: linuxppc-embedded
In-Reply-To: <427256F5.8080903@web.de>
In message <427256F5.8080903@web.de> you wrote:
>
> I'm having a problem compiling Linux 2.4.25 as included in ELDK version
> 3.1 / Build 2004-11-10.
>
> When trying to compile ppc_8xx/usr/src/linux-2.4.25/drivers/char/flash.c
> it throws an error:
You are using an inappropriate configuration of the Linux kernel.
> It looks like it misses ppcboot.h or something. Is there something I
> need to select in the kernel configuration to get rid of that error?
Not to select, but to unselect: don't try enabling the CONFIG_FLASH
option if (1) you don't know exactly what you're doing *and* (2) you
are really using on of the boards supported by this driver (which is
obsolete und unsupported, btw.).
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
A failure will not appear until a unit has passed final inspection.
^ permalink raw reply
* RE: [PATCH 2.6.12-rc2] Freescale 8272ADS PCI bridge support to thestock linux-2.5 (updated)
From: Rune Torgersen @ 2005-04-29 22:23 UTC (permalink / raw)
To: Vitaly Bordug, Kumar Gala; +Cc: Tom Rini, linuxppc-embedded list
The patch works on MPC8266ADS board using PQ2FADS setup with a couple of
hacks to disable some stuff the PQ2 has that the 8266ADS doesn't
> -----Original Message-----
> From: Vitaly Bordug [mailto:vbordug@ru.mvista.com]=20
> Sent: Friday, April 29, 2005 06:29
> To: Kumar Gala
> Cc: Rune Torgersen; Wolfgang Denk; Tom Rini; linuxppc-embedded list
> Subject: Re: [PATCH 2.6.12-rc2] Freescale 8272ADS PCI bridge=20
> support to thestock linux-2.5 (updated)
>=20
> Kumar,
>=20
> This is what currently intended to represent on-chip PCI=20
> bridge support=20
> for PQ2 family.
> It's approved working on my 8272 and have a very good probably of the=20
> same on the PQ2FADS-VR board. It contains low-level (SIUMCR & CPLD IC=20
> chip select ) setup only for 8272 and PQ2FADS, considering=20
> that u-boot=20
> does this stuff for 8266 boards. The actual source files are=20
> renamed to=20
> m82xx_pci.[ch].
>=20
> Rune, can you test this for m8266/8265 ? I guess while IRQ stuff is=20
> nearly the same, this _should_ work as is or with minimum=20
> effort. Note=20
> that you'll need to define PCI_INT_TO_SIU in platforms/pq2ads.h (I=20
> suppose it's the same as PQ2FADS - SIU_INT_IRQ6, but I'm not sure).
>=20
> Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
>=20
> --=20
> Sincerely,=20
> Vitaly
>=20
>=20
^ permalink raw reply
* Re: 824x sandpoint and 2.6.x
From: Sam Song @ 2005-04-30 5:33 UTC (permalink / raw)
To: Mark A. Greer; +Cc: linuxppc-embedded
"Mark A. Greer" <mgreer@mvista.com> wrote:
[snip]
> Here is the output of a 7457 sandpoint on a very old
> root filesystem.
> Output for any other processor will be the same.
Thanks. Some useful hints inside.
[snip]
> ttyS0 at MMIO 0x0 (irq = 4) is a NS16550A
Mine is "ttyS0 at MMIO 0xfdfce500 (irq = 5) is a
16450". Have some ideas to try but I am on vacation:)
> ttyS1 at MMIO 0x0 (irq = 3) is a NS16550A
I masked ttyS1 manually.
Thanks again,
Have a nice Labor Day:)
Sam
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^ permalink raw reply
* test
From: sen lin @ 2005-04-30 8:47 UTC (permalink / raw)
To: Linuxppc-embedded
test
^ permalink raw reply
* 2.6.12-rc3-mm2: ppc pte_offset_map()
From: Sean Neakums @ 2005-05-01 15:08 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <20050430164303.6538f47c.akpm@osdl.org>
On my Mackertosh (PowerBook5.4), build fails with the following:
fs/proc/task_mmu.c: In function `smaps_pte_range':
fs/proc/task_mmu.c:177: warning: implicit declaration of function `kmap_atomic'
fs/proc/task_mmu.c:177: error: `KM_PTE0' undeclared (first use in this function)
fs/proc/task_mmu.c:177: error: (Each undeclared identifier is reported only once
fs/proc/task_mmu.c:177: error: for each function it appears in.)
fs/proc/task_mmu.c:207: warning: implicit declaration of function `kunmap_atomic'
With the naive patch below, it builds with this warning and everything works.
fs/proc/task_mmu.c: In function `smaps_pte_range':
fs/proc/task_mmu.c:208: warning: passing arg 1 of `kunmap_atomic' makes pointer from integer without a cast
I tried including linux/highmem.h in asm-ppc/pgtable.h
(smaps_pte_range() -> pte_offset_map() -> kmap_atomic()), but that
doesn't work.
--- S12-rc3-mm2/fs/proc/task_mmu.c~ 2005-05-01 15:52:55.000000000 +0100
+++ S12-rc3-mm2/fs/proc/task_mmu.c 2005-05-01 15:23:22.000000000 +0100
@@ -1,4 +1,5 @@
#include <linux/mm.h>
+#include <linux/highmem.h>
#include <linux/hugetlb.h>
#include <linux/mount.h>
#include <linux/seq_file.h>
--
Dag vijandelijk luchtschip de huismeester is dood
^ permalink raw reply
* Re: 2.6.12-rc3-mm2: ppc pte_offset_map()
From: Jesper Juhl @ 2005-05-01 15:50 UTC (permalink / raw)
To: Sean Neakums; +Cc: Andrew Morton, linuxppc-dev, linux-kernel
In-Reply-To: <6uu0lnf0gm.fsf@zork.zork.net>
On Sun, 1 May 2005, Sean Neakums wrote:
> On my Mackertosh (PowerBook5.4), build fails with the following:
>
> fs/proc/task_mmu.c: In function `smaps_pte_range':
> fs/proc/task_mmu.c:177: warning: implicit declaration of function `kmap_atomic'
> fs/proc/task_mmu.c:177: error: `KM_PTE0' undeclared (first use in this function)
> fs/proc/task_mmu.c:177: error: (Each undeclared identifier is reported only once
> fs/proc/task_mmu.c:177: error: for each function it appears in.)
> fs/proc/task_mmu.c:207: warning: implicit declaration of function `kunmap_atomic'
>
> With the naive patch below, it builds with this warning and everything works.
>
> fs/proc/task_mmu.c: In function `smaps_pte_range':
> fs/proc/task_mmu.c:208: warning: passing arg 1 of `kunmap_atomic' makes pointer from integer without a cast
>
Try this patch :
Signed-off-by: Jesper Juhl <juhl-lkml@dif.dk>
--- linux-2.6.12-rc3-mm2-orig/fs/proc/task_mmu.c 2005-05-01 04:04:25.000000000 +0200
+++ linux-2.6.12-rc3-mm2/fs/proc/task_mmu.c 2005-05-01 17:49:14.000000000 +0200
@@ -2,6 +2,7 @@
#include <linux/hugetlb.h>
#include <linux/mount.h>
#include <linux/seq_file.h>
+#include <linux/highmem.h>
#include <asm/elf.h>
#include <asm/uaccess.h>
@@ -204,7 +205,7 @@ static void smaps_pte_range(pmd_t *pmd,
}
}
} while (address < end);
- pte_unmap(pte);
+ pte_unmap((void *)pte);
}
static void smaps_pmd_range(pud_t *pud,
^ permalink raw reply
* Re: 2.6.12-rc3-mm2: ppc pte_offset_map()
From: Andrew Morton @ 2005-05-01 22:46 UTC (permalink / raw)
To: Jesper Juhl; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <Pine.LNX.4.62.0505011749280.2488@dragon.hyggekrogen.localhost>
Jesper Juhl <juhl-lkml@dif.dk> wrote:
>
> On Sun, 1 May 2005, Sean Neakums wrote:
>
> > On my Mackertosh (PowerBook5.4), build fails with the following:
> >
> > fs/proc/task_mmu.c: In function `smaps_pte_range':
> > fs/proc/task_mmu.c:177: warning: implicit declaration of function `kmap_atomic'
> > fs/proc/task_mmu.c:177: error: `KM_PTE0' undeclared (first use in this function)
> > fs/proc/task_mmu.c:177: error: (Each undeclared identifier is reported only once
> > fs/proc/task_mmu.c:177: error: for each function it appears in.)
> > fs/proc/task_mmu.c:207: warning: implicit declaration of function `kunmap_atomic'
> >
> > With the naive patch below, it builds with this warning and everything works.
> >
> > fs/proc/task_mmu.c: In function `smaps_pte_range':
> > fs/proc/task_mmu.c:208: warning: passing arg 1 of `kunmap_atomic' makes pointer from integer without a cast
> >
>
> Try this patch :
>
> Signed-off-by: Jesper Juhl <juhl-lkml@dif.dk>
>
> --- linux-2.6.12-rc3-mm2-orig/fs/proc/task_mmu.c 2005-05-01 04:04:25.000000000 +0200
> +++ linux-2.6.12-rc3-mm2/fs/proc/task_mmu.c 2005-05-01 17:49:14.000000000 +0200
> @@ -2,6 +2,7 @@
> #include <linux/hugetlb.h>
> #include <linux/mount.h>
> #include <linux/seq_file.h>
> +#include <linux/highmem.h>
>
> #include <asm/elf.h>
> #include <asm/uaccess.h>
> @@ -204,7 +205,7 @@ static void smaps_pte_range(pmd_t *pmd,
> }
> }
> } while (address < end);
> - pte_unmap(pte);
> + pte_unmap((void *)pte);
> }
Should be
pte_unmap(ptep);
^ permalink raw reply
* Re: 2.6.12-rc3-mm2: ppc pte_offset_map()
From: Jesper Juhl @ 2005-05-01 23:01 UTC (permalink / raw)
To: Andrew Morton; +Cc: Rogério Brito, linuxppc-dev, linux-kernel
In-Reply-To: <20050501154654.2bf7606d.akpm@osdl.org>
On Sun, 1 May 2005, Andrew Morton wrote:
> Jesper Juhl <juhl-lkml@dif.dk> wrote:
> >
> > On Sun, 1 May 2005, Sean Neakums wrote:
> >
> > > On my Mackertosh (PowerBook5.4), build fails with the following:
> > >
> > > fs/proc/task_mmu.c: In function `smaps_pte_range':
> > > fs/proc/task_mmu.c:177: warning: implicit declaration of function `kmap_atomic'
> > > fs/proc/task_mmu.c:177: error: `KM_PTE0' undeclared (first use in this function)
> > > fs/proc/task_mmu.c:177: error: (Each undeclared identifier is reported only once
> > > fs/proc/task_mmu.c:177: error: for each function it appears in.)
> > > fs/proc/task_mmu.c:207: warning: implicit declaration of function `kunmap_atomic'
> > >
> > > With the naive patch below, it builds with this warning and everything works.
> > >
> > > fs/proc/task_mmu.c: In function `smaps_pte_range':
> > > fs/proc/task_mmu.c:208: warning: passing arg 1 of `kunmap_atomic' makes pointer from integer without a cast
> > >
> >
> > Try this patch :
> >
> > Signed-off-by: Jesper Juhl <juhl-lkml@dif.dk>
> >
> > --- linux-2.6.12-rc3-mm2-orig/fs/proc/task_mmu.c 2005-05-01 04:04:25.000000000 +0200
> > +++ linux-2.6.12-rc3-mm2/fs/proc/task_mmu.c 2005-05-01 17:49:14.000000000 +0200
> > @@ -2,6 +2,7 @@
> > #include <linux/hugetlb.h>
> > #include <linux/mount.h>
> > #include <linux/seq_file.h>
> > +#include <linux/highmem.h>
> >
> > #include <asm/elf.h>
> > #include <asm/uaccess.h>
> > @@ -204,7 +205,7 @@ static void smaps_pte_range(pmd_t *pmd,
> > }
> > }
> > } while (address < end);
> > - pte_unmap(pte);
> > + pte_unmap((void *)pte);
> > }
>
> Should be
>
> pte_unmap(ptep);
>
Of course, stupid me. I should have seen the
[...]
ptep = pte_offset_map(pmd, address);
[...]
pte = *ptep;
address += PAGE_SIZE;
ptep++;
[...]
bit a few lines above. Guess I should have spend more than 2min creating
the patch.
Thanks.
Here's an updated patch.
Signed-off-by: Jesper Juhl <juhl-lkml@dif.dk>
--- linux-2.6.12-rc3-mm2-orig/fs/proc/task_mmu.c 2005-05-01 04:04:25.000000000 +0200
+++ linux-2.6.12-rc3-mm2/fs/proc/task_mmu.c 2005-05-02 00:59:11.000000000 +0200
@@ -2,6 +2,7 @@
#include <linux/hugetlb.h>
#include <linux/mount.h>
#include <linux/seq_file.h>
+#include <linux/highmem.h>
#include <asm/elf.h>
#include <asm/uaccess.h>
@@ -204,7 +205,7 @@ static void smaps_pte_range(pmd_t *pmd,
}
}
} while (address < end);
- pte_unmap(pte);
+ pte_unmap(ptep);
}
static void smaps_pmd_range(pud_t *pud,
^ permalink raw reply
* [PATCH] ppc32: Workaround a cache flush issue on sleep
From: Benjamin Herrenschmidt @ 2005-05-02 1:07 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev list, Linus Torvalds
Hi !
We are experiencing a problem when flushing the CPU caches before sleep
on some laptop models using the 750FX CPU rev 1.X. While I haven't been
able to figure out a proper explanation for what's going on, I do have a
workaround that seem to work reliably and allows those machine to sleep
and wakeup properly again. This should be applied for 2.6.12. I'll
re-update that code if/when I ever find exactly what is happening with
those CPU revisions.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Index: linux-work/arch/ppc/platforms/pmac_cache.S
===================================================================
--- linux-work.orig/arch/ppc/platforms/pmac_cache.S 2005-04-24 11:37:38.000000000 +1000
+++ linux-work/arch/ppc/platforms/pmac_cache.S 2005-04-24 12:00:46.000000000 +1000
@@ -64,27 +64,39 @@
mtspr SPRN_HID0,r4 /* Disable DPM */
sync
- /* disp-flush L1 */
- li r4,0x4000
- mtctr r4
+ /* Disp-flush L1. We have a weird problem here that I never
+ * totally figured out. On 750FX, using the ROM for the flush
+ * results in a non-working flush. We use that workaround for
+ * now until I finally understand what's going on. --BenH
+ */
+
+ /* ROM base by default */
lis r4,0xfff0
-1: lwzx r0,r0,r4
+ mfpvr r3
+ srwi r3,r3,16
+ cmplwi cr0,r3,0x7000
+ bne+ 1f
+ /* RAM base on 750FX */
+ li r4,0
+1: li r4,0x4000
+ mtctr r4
+1: lwz r0,0(r4)
addi r4,r4,32
bdnz 1b
sync
isync
- /* disable / invalidate / enable L1 data */
+ /* Disable / invalidate / enable L1 data */
mfspr r3,SPRN_HID0
- rlwinm r0,r0,0,~HID0_DCE
+ rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE)
mtspr SPRN_HID0,r3
sync
isync
- ori r3,r3,HID0_DCE|HID0_DCI
+ ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI)
sync
isync
mtspr SPRN_HID0,r3
- xori r3,r3,HID0_DCI
+ xori r3,r3,(HID0_DCI|HID0_ICFI)
mtspr SPRN_HID0,r3
sync
@@ -110,11 +122,20 @@
lis r4,2
mtctr r4
lis r4,0xfff0
-1: lwzx r0,r0,r4
+1: lwz r0,0(r4)
+ addi r4,r4,32
+ bdnz 1b
+ sync
+ isync
+ lis r4,2
+ mtctr r4
+ lis r4,0xfff0
+1: dcbf 0,r4
addi r4,r4,32
bdnz 1b
sync
isync
+
/* now disable L2 */
rlwinm r5,r5,0,~L2CR_L2E
b 2f
@@ -135,6 +156,13 @@
mtspr SPRN_L2CR,r4
sync
isync
+
+ /* Wait for the invalidation to complete */
+1: mfspr r3,SPRN_L2CR
+ rlwinm. r0,r3,0,31,31
+ bne 1b
+
+ /* Clear L2I */
xoris r4,r4,L2CR_L2I@h
sync
mtspr SPRN_L2CR,r4
@@ -142,16 +170,18 @@
/* now disable the L1 data cache */
mfspr r0,SPRN_HID0
- rlwinm r0,r0,0,~HID0_DCE
+ rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
mtspr SPRN_HID0,r0
sync
isync
/* Restore HID0[DPM] to whatever it was before */
sync
- mtspr SPRN_HID0,r8
+ mfspr r0,SPRN_HID0
+ rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */
+ mtspr SPRN_HID0,r0
sync
-
+
/* restore DR and EE */
sync
mtmsr r11
@@ -201,7 +231,7 @@
mtctr r4
li r4,0
1:
- lwzx r0,r0,r4
+ lwz r0,0(r4)
addi r4,r4,32 /* Go to start of next cache line */
bdnz 1b
isync
^ permalink raw reply
* [PATCH] ppc32: More fixlet for pmac sound
From: Benjamin Herrenschmidt @ 2005-05-02 4:45 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev list, Linus Torvalds
Hi !
As Al Viro noticed, my previous fix missed one instance of "device" in
the driver local debug code. Harmless unless you tweak the #define's in
there but still work fixing.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Index: linux-work/sound/ppc/toonie.c
===================================================================
--- linux-work.orig/sound/ppc/toonie.c 2005-05-02 12:14:14.000000000 +1000
+++ linux-work/sound/ppc/toonie.c 2005-05-02 14:01:01.000000000 +1000
@@ -320,7 +320,7 @@
}
DBG("(I) GPIO device %s found, offset: %x, active state: %d !\n",
- device, gp->addr, gp->active_state);
+ name, gp->addr, gp->active_state);
return (np->n_intrs > 0) ? np->intrs[0].line : 0;
}
^ permalink raw reply
* [PATCH] ppc32: Fix might_sleep() warning with clock spreading
From: Benjamin Herrenschmidt @ 2005-05-02 6:12 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev list, Linus Torvalds
Hi !
The clock spreading disable/enable code was called to late/early during
the suspend/resume code on some laptops and would trigger a
might_sleep() warning due to the down() call in the low level i2c code.
This fixes it by calling those functions earlier/later when interrupts
are still enabled.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Index: linux-work/include/asm-ppc/pmac_feature.h
===================================================================
--- linux-work.orig/include/asm-ppc/pmac_feature.h 2005-05-02 10:49:57.000000000 +1000
+++ linux-work/include/asm-ppc/pmac_feature.h 2005-05-02 15:43:08.000000000 +1000
@@ -316,6 +316,9 @@
extern void pmac_suspend_agp_for_card(struct pci_dev *dev);
extern void pmac_resume_agp_for_card(struct pci_dev *dev);
+/* Used by the via-pmu driver for suspend/resume
+ */
+extern void pmac_tweak_clock_spreading(int enable);
/*
* The part below is for use by macio_asic.c only, do not rely
Index: linux-work/arch/ppc/platforms/pmac_feature.c
===================================================================
--- linux-work.orig/arch/ppc/platforms/pmac_feature.c 2005-05-02 13:16:22.000000000 +1000
+++ linux-work/arch/ppc/platforms/pmac_feature.c 2005-05-02 15:43:55.000000000 +1000
@@ -1591,8 +1591,10 @@
}
-static void __pmac pmac_tweak_clock_spreading(struct macio_chip* macio, int enable)
+void __pmac pmac_tweak_clock_spreading(int enable)
{
+ struct macio_chip* macio = &macio_chips[0];
+
/* Hack for doing clock spreading on some machines PowerBooks and
* iBooks. This implements the "platform-do-clockspreading" OF
* property as decoded manually on various models. For safety, we also
@@ -1707,9 +1709,6 @@
macio->type != macio_intrepid)
return -ENODEV;
- /* Disable clock spreading */
- pmac_tweak_clock_spreading(macio, 0);
-
/* We power off the wireless slot in case it was not done
* by the driver. We don't power it on automatically however
*/
@@ -1852,9 +1851,6 @@
UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
udelay(100);
- /* Enable clock spreading */
- pmac_tweak_clock_spreading(macio, 1);
-
return 0;
}
@@ -2822,7 +2818,7 @@
* clock spreading now. This should be a platform function but we
* don't do these at the moment
*/
- pmac_tweak_clock_spreading(&macio_chips[0], 1);
+ pmac_tweak_clock_spreading(1);
#endif /* CONFIG_POWER4 */
Index: linux-work/drivers/macintosh/via-pmu.c
===================================================================
--- linux-work.orig/drivers/macintosh/via-pmu.c 2005-05-02 10:48:11.000000000 +1000
+++ linux-work/drivers/macintosh/via-pmu.c 2005-05-02 15:45:49.000000000 +1000
@@ -2351,6 +2351,10 @@
return -EBUSY;
}
+ /* Disable clock spreading on some machines */
+ pmac_tweak_clock_spreading(0);
+
+ /* Stop preemption */
preempt_disable();
/* Make sure the decrementer won't interrupt us */
@@ -2417,11 +2421,12 @@
/* Re-enable local CPU interrupts */
local_irq_enable();
-
mdelay(100);
-
preempt_enable();
+ /* Re-enable clock spreading on some machines */
+ pmac_tweak_clock_spreading(1);
+
/* Resume devices */
device_resume();
^ permalink raw reply
* [PATCH] ppc/fcc_enet: replace schedule_timeout() with ssleep()
From: Nishanth Aravamudan @ 2005-05-02 6:26 UTC (permalink / raw)
To: dmalek; +Cc: Kernel-Janitors, linuxppc-embedded
In-Reply-To: <20050502061446.GB10173@us.ibm.com>
I couldn't find an appropriate entry in MAINTAINERS for this patch.
Use ssleep() instead of schedule_timeout() to guarantee the task delays
as expected.
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
--- 2.6.12-rc3/arch/ppc/8260_io/fcc_enet.c 2005-04-29 11:03:03.000000000 -0700
+++ 2.6.12-rc3-dev/arch/ppc/8260_io/fcc_enet.c 2005-05-01 19:10:58.000000000 -0700
@@ -1305,12 +1305,11 @@ static void mii_parse_dm9161_scsr(uint m
static void mii_dm9161_wait(uint mii_reg, struct net_device *dev)
{
- int timeout = HZ;
+ int timeout_secs = 1;
/* Davicom takes a bit to come up after a reset,
* so wait here for a bit */
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(timeout);
+ ssleep(timeout_secs);
}
static phy_info_t phy_info_dm9161 = {
^ permalink raw reply
* Memory Usage Growth in File access
From: s.deepak @ 2005-05-02 6:52 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1.1: Type: text/plain, Size: 1224 bytes --]
Hi All,
I am facing an issue in file operation, when we read/write continuously to a large file in our ppc 405 based device , memory usage shown in /proc/meminfo increases by the number of bytes accessed.And after closing the application also the memory used is not released and it goes to cached memory .
We are using 2.4.20 kernel in our device.We are not sure whether the /proc/meminfo shows the erroneous output or the file read/write routines got any problem.
Can anyone suggest me some idea how to trace out the problem.
I have given the sample code below.
The memory consumption grows and it takes about 10 MB memory space [10000 * 1024] when i run the below given code.
When i look into /proc/meminfo the free memory is reduced by 10 MB and Cache Memory & Used memory is increased by 10 mb after running this application.
When i run the below given code first time the memory grows,when i run succesively it doesn't grow again , may be using the already taken memory.
int main()
{
FILE *fp;
unsigned long int i;
unsigned char data[1024];
fp=fopen("test.txt","r");
for(i=0;i<10000;i++)
{
fread(data,1024,1,fp);
}
fclose(fp);
}
With Thanks & Regards,
Deepak S
[-- Attachment #1.2: Type: text/html, Size: 2246 bytes --]
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[-- Type: text/plain, Size: 824 bytes --]
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^ permalink raw reply
* [PATCH] ppc32: platform-specific functions missing from kallsyms.
From: David Woodhouse @ 2005-05-02 7:57 UTC (permalink / raw)
To: akpm, linuxppc-dev
The PPC32 kernel puts platform-specific functions into separate sections
so that unneeded parts of it can be freed when we've booted and actually
worked out what we're running on today.
This makes kallsyms ignore those functions, because they're not between
_[se]text or _[se]inittext. Rather than teaching kallsyms about the
various pmac/chrp/etc sections, this patch adds '_[se]extratext' markers
for kallsyms.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
--- linux-2.6.11/arch/ppc/kernel/vmlinux.lds~ 2005-05-01 10:43:10.000000000 +0100
+++ linux-2.6.11/arch/ppc/kernel/vmlinux.lds 2005-05-02 08:06:52.000000000 +0100
@@ -147,6 +147,7 @@ SECTIONS
__init_end = .;
. = ALIGN(4096);
+ _sextratext = .;
__pmac_begin = .;
.pmac.text : { *(.pmac.text) }
.pmac.data : { *(.pmac.data) }
@@ -173,6 +174,7 @@ SECTIONS
.openfirmware.data : { *(.openfirmware.data) }
. = ALIGN(4096);
__openfirmware_end = .;
+ _eextratext = .;
__bss_start = .;
.bss :
--- linux-2.6.11/include/asm-generic/sections.h~ 2005-03-02 07:37:31.000000000 +0000
+++ linux-2.6.11/include/asm-generic/sections.h 2005-05-02 08:43:04.000000000 +0100
@@ -8,6 +8,8 @@ extern char _data[], _sdata[], _edata[];
extern char __bss_start[], __bss_stop[];
extern char __init_begin[], __init_end[];
extern char _sinittext[], _einittext[];
+extern char _sextratext[] __attribute__((weak));
+extern char _eextratext[] __attribute__((weak));
extern char _end[];
#endif /* _ASM_GENERIC_SECTIONS_H_ */
--- linux-2.6.11/scripts/kallsyms.c~ 2005-03-02 07:38:33.000000000 +0000
+++ linux-2.6.11/scripts/kallsyms.c 2005-05-02 08:09:11.000000000 +0100
@@ -67,7 +67,7 @@ struct sym_entry {
static struct sym_entry *table;
static int size, cnt;
-static unsigned long long _stext, _etext, _sinittext, _einittext;
+static unsigned long long _stext, _etext, _sinittext, _einittext, _sextratext, _eextratext;
static int all_symbols = 0;
struct token {
@@ -132,6 +132,10 @@ read_symbol(FILE *in, struct sym_entry *
_sinittext = s->addr;
else if (strcmp(str, "_einittext") == 0)
_einittext = s->addr;
+ else if (strcmp(str, "_sextratext") == 0)
+ _sextratext = s->addr;
+ else if (strcmp(str, "_eextratext") == 0)
+ _eextratext = s->addr;
else if (toupper(s->type) == 'A')
{
/* Keep these useful absolute symbols */
@@ -182,16 +186,18 @@ symbol_valid(struct sym_entry *s)
* and inittext sections are discarded */
if (!all_symbols) {
if ((s->addr < _stext || s->addr > _etext)
- && (s->addr < _sinittext || s->addr > _einittext))
+ && (s->addr < _sinittext || s->addr > _einittext)
+ && (s->addr < _sextratext || s->addr > _eextratext))
return 0;
/* Corner case. Discard any symbols with the same value as
- * _etext or _einittext, they can move between pass 1 and 2
- * when the kallsyms data is added. If these symbols move then
- * they may get dropped in pass 2, which breaks the kallsyms
- * rules.
+ * _etext _einittext or _eextratext; they can move between pass
+ * 1 and 2 when the kallsyms data is added. If these symbols
+ * move then they may get dropped in pass 2, which breaks the
+ * kallsyms rules.
*/
if ((s->addr == _etext && strcmp(s->sym + 1, "_etext")) ||
- (s->addr == _einittext && strcmp(s->sym + 1, "_einittext")))
+ (s->addr == _einittext && strcmp(s->sym + 1, "_einittext")) ||
+ (s->addr == _eextratext && strcmp(s->sym + 1, "_eextratext")))
return 0;
}
--- linux-2.6.11/kernel/kallsyms.c~ 2005-05-01 10:37:45.000000000 +0100
+++ linux-2.6.11/kernel/kallsyms.c 2005-05-02 08:42:59.000000000 +0100
@@ -46,6 +46,14 @@ static inline int is_kernel_inittext(uns
return 0;
}
+static inline int is_kernel_extratext(unsigned long addr)
+{
+ if (addr >= (unsigned long)_sextratext
+ && addr <= (unsigned long)_eextratext)
+ return 1;
+ return 0;
+}
+
static inline int is_kernel_text(unsigned long addr)
{
if (addr >= (unsigned long)_stext && addr <= (unsigned long)_etext)
@@ -169,7 +177,7 @@ const char *kallsyms_lookup(unsigned lon
namebuf[0] = 0;
if ((all_var && is_kernel(addr)) ||
- (!all_var && (is_kernel_text(addr) || is_kernel_inittext(addr)))) {
+ (!all_var && (is_kernel_text(addr) || is_kernel_inittext(addr) || is_kernel_extratext(addr)))) {
unsigned long symbol_end=0;
/* do a binary search on the sorted kallsyms_addresses array */
--
dwmw2
^ permalink raw reply
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