* Re: [PATCH] ppc32: fix cpm_uart_int() missing interrupts
From: Guillaume Autran @ 2005-05-19 19:34 UTC (permalink / raw)
To: Dan Malek; +Cc: linuxppc-embedded
In-Reply-To: <2376d87e3df664106a6cf626f9575d90@embeddededge.com>
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Is it better like this ?
Dan Malek wrote:
>
> On May 19, 2005, at 1:59 PM, Guillaume Autran wrote:
>
>> Any comment ?
>
>
> The idea is fine. Read Documentation/CodingStyle and try again .....
>
> Thanks.
>
>
> -- Dan
>
--
=======================================
Guillaume Autran
Senior Software Engineer
MRV Communications, Inc.
Tel: (978) 952-4932 office
E-mail: gautran@mrv.com
=======================================
[-- Attachment #2: cpm_uart_core.patch --]
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diff -Nru linux-2.6.12-rc4.org/drivers/serial/cpm_uart/cpm_uart_core.c linux-2.6.12-rc4.new/drivers/serial/cpm_uart/cpm_uart_core.c
--- linux-2.6.12-rc4.org/drivers/serial/cpm_uart/cpm_uart_core.c 2005-05-07 01:20:31.000000000 -0400
+++ linux-2.6.12-rc4.new/drivers/serial/cpm_uart/cpm_uart_core.c 2005-05-19 15:31:03.000000000 -0400
@@ -335,23 +335,25 @@
pr_debug("CPM uart[%d]:IRQ\n", port->line);
if (IS_SMC(pinfo)) {
- events = smcp->smc_smce;
- if (events & SMCM_BRKE)
- uart_handle_break(port);
- if (events & SMCM_RX)
- cpm_uart_int_rx(port, regs);
- if (events & SMCM_TX)
- cpm_uart_int_tx(port, regs);
- smcp->smc_smce = events;
+ while ((events = smcp->smc_smce) & (SMCM_BRKE | SMCM_RX | SMCM_TX)) {
+ smcp->smc_smce = events;
+ if (events & SMCM_BRKE)
+ uart_handle_break(port);
+ if (events & SMCM_RX)
+ cpm_uart_int_rx(port, regs);
+ if (events & SMCM_TX)
+ cpm_uart_int_tx(port, regs);
+ }
} else {
- events = sccp->scc_scce;
- if (events & UART_SCCM_BRKE)
- uart_handle_break(port);
- if (events & UART_SCCM_RX)
- cpm_uart_int_rx(port, regs);
- if (events & UART_SCCM_TX)
- cpm_uart_int_tx(port, regs);
- sccp->scc_scce = events;
+ while ((events = sccp->scc_scce) & (UART_SCCM_BRKE | UART_SCCM_RX | UART_SCCM_TX)) {
+ sccp->scc_scce = events;
+ if (events & UART_SCCM_BRKE)
+ uart_handle_break(port);
+ if (events & UART_SCCM_RX)
+ cpm_uart_int_rx(port, regs);
+ if (events & UART_SCCM_TX)
+ cpm_uart_int_tx(port, regs);
+ }
}
return (events) ? IRQ_HANDLED : IRQ_NONE;
}
^ permalink raw reply
* Re: tah reset?
From: Eugene Surovegin @ 2005-05-19 18:23 UTC (permalink / raw)
To: Sanjay Bajaj; +Cc: linuxppc-embedded
In-Reply-To: <0007F077BB3476449151699150E8FEA21A7B9D@exchange.tsi-telsys.com>
On Thu, May 19, 2005 at 02:14:20PM -0400, Sanjay Bajaj wrote:
> While trying to reset the TAH on emac2 of PPC440GX, the Soft Reset
> (SR) bit never resets itself to 0. Does anybody know the reason for
> it?
Did you enable TAH0 in SDR0_MFR register?
Also, I don't remember for sure, but TAH may have the same problem as
EMAC, namely, it won't go out of reset if there is no RX clock from
PHY.
--
Eugene
^ permalink raw reply
* tah reset?
From: Sanjay Bajaj @ 2005-05-19 18:14 UTC (permalink / raw)
To: linuxppc-embedded
While trying to reset the TAH on emac2 of PPC440GX, the Soft Reset (SR) =
bit never resets itself to 0. Does anybody know the reason for it?
Sanjay
^ permalink raw reply
* Re: [PATCH] ppc32: fix cpm_uart_int() missing interrupts
From: Dan Malek @ 2005-05-19 18:11 UTC (permalink / raw)
To: Guillaume Autran; +Cc: linuxppc-embedded
In-Reply-To: <428CD40C.201@mrv.com>
On May 19, 2005, at 1:59 PM, Guillaume Autran wrote:
> Any comment ?
The idea is fine. Read Documentation/CodingStyle and try again .....
Thanks.
-- Dan
^ permalink raw reply
* Re: OF flat device tree for ppc32...
From: Dan Malek @ 2005-05-19 18:04 UTC (permalink / raw)
To: Jon Loeliger; +Cc: Jakob Viketoft, Linux PPC Embedded list
In-Reply-To: <1116517058.24754.10.camel@gleep>
On May 19, 2005, at 11:37 AM, Jon Loeliger wrote:
> So, there were two positive comments that I received
> as feedback on my initial suggestion, and no negative
> comments. (Minor patch deltas not withstanding.)
I have the same negative comments as Wolfgang.
This boot rom to kernel interface is continually discussed,
has been for years, and it just gets a little tiring :-)
The main reason for the original work done to create
the "boot wrapper" functions was to accommodate as
many boot roms as possible, distilled into a minimal
amount of common information.
We still have people (more and more, actually) that want
to run Linux and associated applications in minimal
flash and ram space. Solutions that require more and
more code get to the point where they simply don't
fit into these systems.
There are also many embedded systems that don't
run something like U-Boot, and even if they did they
are not likely to perform field upgrades just to use
something that adds no value to their product. We
must be able to accommodate these systems, as
the existing code does today.
Real embedded devices have minimalist requirements.
Minimal flash, minimal ram, minimal boot up time. Even
today, Linux is too big and too slow for many of these
devices, making other alternatives more attractive. If
we want to continue with success in this embedded
space, we have to address minimal requirement and
stop changing things to make them look like workstations.
We get spoiled by the few evaluation or demo boards we
see, because they are likely on the resource rich side.
Fine for development, but not something that will
see production.
We have embedded design wins today because of
the code we had years ago. I'm afraid if we continue
with the code bloat and the performance challenges
we see with 2.6, we are going to lose many of the
new embedded products in the future.
If you consider yourself to be an embedded engineer,
you have to place "minimal resource use" at the top
of your list. They have to boot and be useful "instantly."
Thanks.
-- Dan
^ permalink raw reply
* Re: [PATCH] ppc32: fix cpm_uart_int() missing interrupts
From: Guillaume Autran @ 2005-05-19 17:59 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20050518170949.GA6766@gate.ebshome.net>
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This is a patch to fix a problem that occurs at high baud rates in the
cpm uart interrupt handling.
In cpm_uart_int(), the existing code reads the event register, processes
the events, and then clears bits in the event register before returning.
The problem here is that sometimes event processing generates new events
quite quickly (i.e. at higher baud rates, the transmit interrupt handler
puts another character into an SCC's transmit buffer and the SCC clears
the READY bit almost immediately). In this case, the second interrupt
can be missed because the scc_scce event register gets cleared after
processing the first. The port can get hung.
The fix adds a while loop. It reads the event register saving its value
in the local variable 'events' (as before) then clears the event
register in the device immediately. It processes the events and tests
the event register again handling new events that might get generated
during handling.
Any comment ?
Guillaume.
--
=======================================
Guillaume Autran
Senior Software Engineer
MRV Communications, Inc.
Tel: (978) 952-4932 office
E-mail: gautran@mrv.com
=======================================
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[-- Attachment #2: cpm_uart_core.patch --]
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diff -Nru linux-2.6.12-rc4.org/drivers/serial/cpm_uart/cpm_uart_core.c linux-2.6.12-rc4.new/drivers/serial/cpm_uart/cpm_uart_core.c
--- linux-2.6.12-rc4.org/drivers/serial/cpm_uart/cpm_uart_core.c 2005-05-07 01:20:31.000000000 -0400
+++ linux-2.6.12-rc4.new/drivers/serial/cpm_uart/cpm_uart_core.c 2005-05-19 13:48:58.000000000 -0400
@@ -335,23 +335,25 @@
pr_debug("CPM uart[%d]:IRQ\n", port->line);
if (IS_SMC(pinfo)) {
- events = smcp->smc_smce;
+ while ((events = smcp->smc_smce) & (SMCM_BRKE | SMCM_RX | SMCM_TX)) {
+ smcp->smc_smce = events;
if (events & SMCM_BRKE)
- uart_handle_break(port);
+ uart_handle_break(port);
if (events & SMCM_RX)
- cpm_uart_int_rx(port, regs);
+ cpm_uart_int_rx(port, regs);
if (events & SMCM_TX)
- cpm_uart_int_tx(port, regs);
- smcp->smc_smce = events;
+ cpm_uart_int_tx(port, regs);
+ }
} else {
- events = sccp->scc_scce;
+ while ((events = sccp->scc_scce) & (UART_SCCM_BRKE | UART_SCCM_RX | UART_SCCM_TX)) {
+ sccp->scc_scce = events;
if (events & UART_SCCM_BRKE)
- uart_handle_break(port);
+ uart_handle_break(port);
if (events & UART_SCCM_RX)
- cpm_uart_int_rx(port, regs);
+ cpm_uart_int_rx(port, regs);
if (events & UART_SCCM_TX)
- cpm_uart_int_tx(port, regs);
- sccp->scc_scce = events;
+ cpm_uart_int_tx(port, regs);
+ }
}
return (events) ? IRQ_HANDLED : IRQ_NONE;
}
^ permalink raw reply
* RE: Arabella Resource Manager
From: Jonathan Masel @ 2005-05-19 16:37 UTC (permalink / raw)
To: 'McMullan, Jason'; +Cc: 'PPC_LINUX'
In-Reply-To: <1116509554.9050.127.camel@jmcmullan.timesys>
Hi Jason,
The code is actually much more flexible than that. I only sent a sample
yesterday (you got down to the nitty-gritty a little quicker than I had
thought!). I've uploaded all RM source code to our FTP server
(ftp.arabellasw.com - user ft.rm, passwd arabella). There's no real
documentation (outside source/comments) on the internals - sorry.
Chip-specific code registers the resource types, etc something like you
suggest. API's can be at the very generic RM level (see resmgr.h) but a chip
driver would usually operate at the more convenient chip-level interface.
So, the chip-specific RM code decides which types of resources can be
alloc/freed by the RM (for PQ's that's usually xcc, clocks, pins and dpram)
and the parameters necessary in each case.
We've never used it (yet) outside PQ family, though I don't see any reason
why it can't be.
The files in the tar file (misnamed resmsg.gz.tar!) are
pq1brddef.h - PQ1-specific board definitions
pq1defs.h - PQ1-specific chip definitions
pqrm.c - PQ1-specific RM code (should be called pq1rm.c!)
pq1rm.h - PQ1-specific RM definitions
pq2brddef.h - PQ2-specific board definitions
pq2defs.h - PQ2-specific chip definitions
pq2rm.c - PQ2-specific RM code
pq2rm.h - PQ2-specific RM definitions
pq3brddef.h - PQ3-specific board definitions
pq3defs.h - PQ3-specific chip definitions
pq3rm.c - PQ3-specific RM code
pq3rm.h - PQ3-specific RM definitions
pqbrddef.h - PQ family board-specific information
pqdefs.h - PQ family chip definitions
pqrm.h - PQ family RM code
resmgr.c - generic RM code
resmgr.h - generic RM definitions
Jonathan
Jason wrote:
>
> Interesting code, but not generic enough.
> What would be nicer would be an API like the following, that can be
> easily extended, and work for more than just PQ (and ppc, for that
> matter)
>
> enum bres_type {
> BRES_TYPE_CLOCK = 0,
> BRES_TYPE_PIN,
> BRES_TYPE_CPM_SRAM,
> ...
> BRES_TYPE_MAX,
> }
>
> struct bres_pool {
> struct resource *pool;
> int (*set)(int id, ...);
> int (*clear)(int id);
> };
>
> /* Board setup will set up the available regions
> * into this array, similar as to how the PCI
> * system sets up the iomem areas.
> */
> struct bres_pool *board_resource[BRES_TYPE_MAX];
>
> /* Request a resource out of the available pools
> */
> int bres_request(enum bres_type type, const struct resource *req);
>
> /* Free a requested resource
> * This also calls the 'clear' function of the pool.
> */
> int bres_release(enum bres_type type, const struct resource *res);
>
>
> /* After request completes, you can 'instance'
> * the resource.
> */
>
> /* Wire a pin
> * pin is the same as you requested in the resource
> * pin type is defined in either the board or SoC CPU headers
> * (ie CPM_PB17_SDL)
> */
> static inline int bres_pin_wire_as(int pin, int pin_type)
> { return board_resource[BRES_TYPE_PIN].instance(pin, pin_type); }
>
> /* Wire a clock
> */
> static inline int bres_clock_wire_as(int clock, int clock_target,
> int multiplier, int divider)
> { return board_resource[BRES_TYPE_CLOCK].instance(pin, pin_type); }
>
> ...etc....
>
>
>
> --
> Jason McMullan <jason.mcmullan@timesys.com>
> TimeSys Corporation
^ permalink raw reply
* Re: OF flat device tree for ppc32...
From: Jon Loeliger @ 2005-05-19 15:37 UTC (permalink / raw)
To: Jakob Viketoft; +Cc: Linux PPC Embedded list
In-Reply-To: <428C352E.1050002@bitsim.se>
On Thu, 2005-05-19 at 01:41, Jakob Viketoft wrote:
> Hello Jon!
>
> Any news on the port of the OF-layer to ppc32? I'd love to hear some
> more and it would be great be able to help out, even though I have some
> heavy deadlines hanging over me for the next 2 months. From what I can
> see on the list, there wasn't many comments on your first preparatory
> code, but I for one thinks it's time to move it forward anyway.
>
> What do you say?
>
> /Jakob
So, there were two positive comments that I received
as feedback on my initial suggestion, and no negative
comments. (Minor patch deltas not withstanding.)
I am _almost_ actively back to working on this issue.
Right now, I am in the process of re-grabbing a new
tree from GIT-land and reconstructing my tree and patch
based on current top-of-GIT.
My desire will then be to re-submit the patch for real
and have it applied to the tree in an effort to isolate
the __res and friends to one localized area with a
well-defined interface.
I will then read Ben's proposal in detail and move
forward from there.
HTH!
jdl
^ permalink raw reply
* Re: Arabella Resource Manager
From: Pantelis Antoniou @ 2005-05-19 13:23 UTC (permalink / raw)
To: jmasel; +Cc: 'PPC_LINUX'
In-Reply-To: <E1DYPVW-0000vS-00@gold.webfusion.co.uk>
Jonathan Masel wrote:
> Hi all,
> Several people have expressed an interest in seeing some more of our
> Resource Manager - a kernel library for allocating/releasing on-chip
> resources of all PQ processors. We currently have PQ1, PQ2 and PQ3 for 2.4
> and 2.6 kernels.
>
[snip]
>
>
Jonathan, I see that you use a proc interface for status.
You could use the seq_file abstraction and clean up the code there.
Also could you just list the categories of the thing you manage
on the list so that we can comment per category?
Regards
Pantelis
^ permalink raw reply
* Re: Arabella Resource Manager
From: McMullan, Jason @ 2005-05-19 13:32 UTC (permalink / raw)
To: jmasel; +Cc: PPC_LINUX
In-Reply-To: <E1DYPVW-0000vS-00@gold.webfusion.co.uk>
[-- Attachment #1: Type: text/plain, Size: 1525 bytes --]
Interesting code, but not generic enough.
What would be nicer would be an API like the following, that can be
easily extended, and work for more than just PQ (and ppc, for that
matter)
enum bres_type {
BRES_TYPE_CLOCK = 0,
BRES_TYPE_PIN,
BRES_TYPE_CPM_SRAM,
...
BRES_TYPE_MAX,
}
struct bres_pool {
struct resource *pool;
int (*set)(int id, ...);
int (*clear)(int id);
};
/* Board setup will set up the available regions
* into this array, similar as to how the PCI
* system sets up the iomem areas.
*/
struct bres_pool *board_resource[BRES_TYPE_MAX];
/* Request a resource out of the available pools
*/
int bres_request(enum bres_type type, const struct resource *req);
/* Free a requested resource
* This also calls the 'clear' function of the pool.
*/
int bres_release(enum bres_type type, const struct resource *res);
/* After request completes, you can 'instance'
* the resource.
*/
/* Wire a pin
* pin is the same as you requested in the resource
* pin type is defined in either the board or SoC CPU headers
* (ie CPM_PB17_SDL)
*/
static inline int bres_pin_wire_as(int pin, int pin_type)
{ return board_resource[BRES_TYPE_PIN].instance(pin, pin_type); }
/* Wire a clock
*/
static inline int bres_clock_wire_as(int clock, int clock_target,
int multiplier, int divider)
{ return board_resource[BRES_TYPE_CLOCK].instance(pin, pin_type); }
...etc....
--
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation
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[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [U-Boot-Users] RFC: Booting the Linux/ppc64 kernel without Open Firmware HOWTO (#2)
From: Wolfgang Denk @ 2005-05-19 13:18 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, linuxppc64-dev, linuxppc-embedded, u-boot-users
In-Reply-To: <1116478614.918.75.camel@gaston>
Dear Ben,
in message <1116478614.918.75.camel@gaston> you wrote:
>
> And here is a second draft with more infos.
>
> Booting the Linux/ppc64 kernel without Open Firmware
Thanks a lot for taking the initiative to come to an agreement about
the kernel boot interface.
I have some concerns about the memory foot print and increased boot
time that will result from the proposed solution. There are many
embedded systems where resources are tight and requirements are aven
tighter. It would be probably a good idea to also ask for feedback
from these folks - for example by posting your RFC on the celinux-dev
mailing list.
But my biggest concern is that we should try to come up with a
solution that has a wider acceptance. Especially from the U-Boot
point of view it is not exactly nice that each of PowerPC, ARM and
MIPS use their very own, completely incompatible way of passing in-
formation from the boot loader to the kernel.
As is, your proposal will add just another incompatible way of doing
the same thing (of course we will have to stay backward compatible
with U-Boot to allow booting older kernels, too).
Why don't we try to come up with a solution that is acceptable to the
other architectures as well?
Maybe you want to post the RFC to lkml, or at least to the
linux-arm-kernel and linux-mips mailing lists?
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Real computer scientists don't comment their code. The identifiers
are so long they can't afford the disk space.
^ permalink raw reply
* Re: [U-Boot-Users] RFC: Booting the Linux/ppc64 kernel without Open Firmware HOWTO (#2)
From: Pantelis Antoniou @ 2005-05-19 13:16 UTC (permalink / raw)
To: Wolfgang Denk
Cc: linuxppc64-dev, linuxppc-embedded, u-boot-users, linuxppc-dev
In-Reply-To: <20050519131844.7D707C1512@atlas.denx.de>
Wolfgang Denk wrote:
> Dear Ben,
>
> in message <1116478614.918.75.camel@gaston> you wrote:
>
>>And here is a second draft with more infos.
>>
>> Booting the Linux/ppc64 kernel without Open Firmware
>
>
> Thanks a lot for taking the initiative to come to an agreement about
> the kernel boot interface.
>
> I have some concerns about the memory foot print and increased boot
> time that will result from the proposed solution. There are many
> embedded systems where resources are tight and requirements are aven
> tighter. It would be probably a good idea to also ask for feedback
> from these folks - for example by posting your RFC on the celinux-dev
> mailing list.
>
> But my biggest concern is that we should try to come up with a
> solution that has a wider acceptance. Especially from the U-Boot
> point of view it is not exactly nice that each of PowerPC, ARM and
> MIPS use their very own, completely incompatible way of passing in-
> formation from the boot loader to the kernel.
>
> As is, your proposal will add just another incompatible way of doing
> the same thing (of course we will have to stay backward compatible
> with U-Boot to allow booting older kernels, too).
>
>
> Why don't we try to come up with a solution that is acceptable to the
> other architectures as well?
>
> Maybe you want to post the RFC to lkml, or at least to the
> linux-arm-kernel and linux-mips mailing lists?
>
I'm really interested in having this discussion.
I'm forced to maintain my own u-boot based solution for doing this and
I'd be very interested in whatever gets chosen.
IMHO the current mess is considerable, and at this point I wouldn't
really care if the resulting solution is less than optimal, as long
as there is one.
> Best regards,
>
> Wolfgang Denk
>
Regards
Pantelis
^ permalink raw reply
* Re: Linux 2.6 and mpc823 compile error
From: Pantelis Antoniou @ 2005-05-19 12:09 UTC (permalink / raw)
To: Björn Östby; +Cc: linuxppc-embedded
In-Reply-To: <004B1D7A5257174C9044A1B7BD0E60ED0178CC0C@ratatosk.combitechsystems.com>
Björn Östby wrote:
> Hi,
> I'm trying to get Linux 2.6.11 up and running on mpc823e. I'm using the cross compiler
> Supplied in ELDK (3.0) and u-boot. The problem is when enabling:
>
> [ ] CPM SCC/SMC serial port support
> and/or
> [ ] CPM SCC Ethernet
>
> The kernel compiles fine having these option disabled, but otherwise..see below
>
> make arch=ppc CROSS_COMPILE=${CROSS_COMPILE}
> .
[snip]
>
>
> There it is. Any ideas?
>
> Regards,
> Bjorn Ostby
>
Don't use this driver. Use the one in drivers/serial/cpm_uart.
Regards
Pantelis
^ permalink raw reply
* [PATCH] ppc32: Support for 82xx PQII on-chip PCI bridge
From: Vitaly Bordug @ 2005-05-19 12:24 UTC (permalink / raw)
To: Andrew Morton; +Cc: Tom Rini, linux-kernel, Kumar Gala, linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 405 bytes --]
This patch adds on-chip PCI bridge support for the PQ2 family. The
incomplete existent code is updated with interrupt handling stuff and
board-specific bits for 8272ADS and PQ2FADS; the related files were
renamed (from m8260_pci to m82xx_pci) to be of more generic fashion.
This is tested with 8266ADS and 8272ADS, should work on PQ2FADS as well.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
[-- Attachment #2: current.patch --]
[-- Type: text/x-patch, Size: 35187 bytes --]
support for PCI bridge on Freescale 8272ADS
---
commit fd47b8335113abcfb34553a83e641cd5ee5e8637
tree 874039bc658fe59955b149328a70521a56744a27
parent 88d7bd8cb9eb8d64bf7997600b0d64f7834047c5
author Vitaly Bordug <vvv@localhost.localdomain> 1116425444 +0400
committer Vitaly Bordug <vvv@localhost.localdomain> 1116425444 +0400
Index: arch/ppc/Kconfig
===================================================================
--- eed337ef5e9ae7d62caa84b7974a11fddc7f06e0/arch/ppc/Kconfig (mode:100644 sha1:600f23d7fd33aae9e5115875ada43a289e075b5d)
+++ 874039bc658fe59955b149328a70521a56744a27/arch/ppc/Kconfig (mode:100644 sha1:6e6377a69d5bc58c16de9f12013b377b3af7d17e)
@@ -1143,12 +1143,12 @@
config PCI_8260
bool
- depends on PCI && 8260 && !8272
+ depends on PCI && 8260
default y
config 8260_PCI9
bool " Enable workaround for MPC826x erratum PCI 9"
- depends on PCI_8260
+ depends on PCI_8260 && !ADS8272
default y
choice
Index: arch/ppc/platforms/pq2ads.h
===================================================================
--- eed337ef5e9ae7d62caa84b7974a11fddc7f06e0/arch/ppc/platforms/pq2ads.h (mode:100644 sha1:cf5e5dd06d6300d7733b20f4e5b21c31a1bdda48)
+++ 874039bc658fe59955b149328a70521a56744a27/arch/ppc/platforms/pq2ads.h (mode:100644 sha1:067d9a5aebc108f7301913e74d3d218161c23ea7)
@@ -49,10 +49,10 @@
/* PCI interrupt controller */
#define PCI_INT_STAT_REG 0xF8200000
#define PCI_INT_MASK_REG 0xF8200004
-#define PIRQA (NR_SIU_INTS + 0)
-#define PIRQB (NR_SIU_INTS + 1)
-#define PIRQC (NR_SIU_INTS + 2)
-#define PIRQD (NR_SIU_INTS + 3)
+#define PIRQA (NR_CPM_INTS + 0)
+#define PIRQB (NR_CPM_INTS + 1)
+#define PIRQC (NR_CPM_INTS + 2)
+#define PIRQD (NR_CPM_INTS + 3)
/*
* PCI memory map definitions for MPC8266ADS-PCI.
@@ -68,28 +68,23 @@
* 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
*/
-/* window for a PCI master to access MPC8266 memory */
-#define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */
-#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
-
-/* window for the processor to access PCI memory with prefetching */
-#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
-#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
-#define PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
-
-/* window for the processor to access PCI memory without prefetching */
-#define PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
-#define PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
-#define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
-
-/* window for the processor to access PCI I/O */
-#define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
-#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
-#define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
-
-#define _IO_BASE PCI_MSTR_IO_LOCAL
-#define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL
-#define PCI_DRAM_OFFSET PCI_SLV_MEM_BUS
+/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
+ Here we should redefine what is unique for this board */
+#define M82xx_PCI_SLAVE_MEM_LOCAL 0x00000000 /* Local base */
+#define M82xx_PCI_SLAVE_MEM_BUS 0x00000000 /* PCI base */
+#define M82xx_PCI_SLAVE_MEM_SIZE 0x10000000 /* 256 Mb */
+
+#define M82xx_PCI_SLAVE_SEC_WND_SIZE ~(0x40000000 - 1U) /* 2 x 512Mb */
+#define M82xx_PCI_SLAVE_SEC_WND_BASE 0x80000000 /* PCI Memory base */
+
+#if defined(CONFIG_ADS8272)
+#define PCI_INT_TO_SIU SIU_INT_IRQ2
+#elif defined(CONFIG_PQ2FADS)
+#define PCI_INT_TO_SIU SIU_INT_IRQ6
+#else
+#warning PCI Bridge will be without interrupts support
+#endif
+
#endif /* CONFIG_PCI */
#endif /* __MACH_ADS8260_DEFS */
Index: arch/ppc/syslib/Makefile
===================================================================
--- eed337ef5e9ae7d62caa84b7974a11fddc7f06e0/arch/ppc/syslib/Makefile (mode:100644 sha1:dd418ea3426c70a4ed065986e464967fce8122fb)
+++ 874039bc658fe59955b149328a70521a56744a27/arch/ppc/syslib/Makefile (mode:100644 sha1:14c90119c2802283d6e96f71d990365170e89eb7)
@@ -81,7 +81,7 @@
obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
todc_time.o
obj-$(CONFIG_8260) += m8260_setup.o
-obj-$(CONFIG_PCI_8260) += m8260_pci.o indirect_pci.o
+obj-$(CONFIG_PCI_8260) += m82xx_pci.o indirect_pci.o pci_auto.o
obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o
obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
ifeq ($(CONFIG_PPC_GEN550),y)
Index: arch/ppc/syslib/m8260_pci.c
===================================================================
--- eed337ef5e9ae7d62caa84b7974a11fddc7f06e0/arch/ppc/syslib/m8260_pci.c (mode:100644 sha1:057cc3f8ff378c0de881482d55b47255e3c5ea72)
+++ /dev/null (tree:874039bc658fe59955b149328a70521a56744a27)
@@ -1,193 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004 Red Hat, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/immap_cpm2.h>
-#include <asm/mpc8260.h>
-
-#include "m8260_pci.h"
-
-
-/* PCI bus configuration registers.
- */
-
-static void __init m8260_setup_pci(struct pci_controller *hose)
-{
- volatile cpm2_map_t *immap = cpm2_immr;
- unsigned long pocmr;
- u16 tempShort;
-
-#ifndef CONFIG_ATC /* already done in U-Boot */
- /*
- * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
- * and local bus for PCI (SIUMCR [LBPC]).
- */
- immap->im_siu_conf.siu_82xx.sc_siumcr = 0x00640000;
-#endif
-
- /* Make PCI lowest priority */
- /* Each 4 bits is a device bus request and the MS 4bits
- is highest priority */
- /* Bus 4bit value
- --- ----------
- CPM high 0b0000
- CPM middle 0b0001
- CPM low 0b0010
- PCI reguest 0b0011
- Reserved 0b0100
- Reserved 0b0101
- Internal Core 0b0110
- External Master 1 0b0111
- External Master 2 0b1000
- External Master 3 0b1001
- The rest are reserved */
- immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
-
- /* Park bus on core while modifying PCI Bus accesses */
- immap->im_siu_conf.siu_82xx.sc_ppc_acr = 0x6;
-
- /*
- * Set up master window that allows the CPU to access PCI space. This
- * window is set up using the first SIU PCIBR registers.
- */
- immap->im_memctl.memc_pcimsk0 = MPC826x_PCI_MASK;
- immap->im_memctl.memc_pcibr0 = MPC826x_PCI_BASE | PCIBR_ENABLE;
-
- /* Disable machine check on no response or target abort */
- immap->im_pci.pci_emr = cpu_to_le32(0x1fe7);
- /* Release PCI RST (by default the PCI RST signal is held low) */
- immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
-
- /* give it some time */
- mdelay(1);
-
- /*
- * Set up master window that allows the CPU to access PCI Memory (prefetch)
- * space. This window is set up using the first set of Outbound ATU registers.
- */
- immap->im_pci.pci_potar0 = cpu_to_le32(MPC826x_PCI_LOWER_MEM >> 12);
- immap->im_pci.pci_pobar0 = cpu_to_le32((MPC826x_PCI_LOWER_MEM - MPC826x_PCI_MEM_OFFSET) >> 12);
- pocmr = ((MPC826x_PCI_UPPER_MEM - MPC826x_PCI_LOWER_MEM) >> 12) ^ 0xfffff;
- immap->im_pci.pci_pocmr0 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PREFETCH_EN);
-
- /*
- * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
- * space. This window is set up using the second set of Outbound ATU registers.
- */
- immap->im_pci.pci_potar1 = cpu_to_le32(MPC826x_PCI_LOWER_MMIO >> 12);
- immap->im_pci.pci_pobar1 = cpu_to_le32((MPC826x_PCI_LOWER_MMIO - MPC826x_PCI_MMIO_OFFSET) >> 12);
- pocmr = ((MPC826x_PCI_UPPER_MMIO - MPC826x_PCI_LOWER_MMIO) >> 12) ^ 0xfffff;
- immap->im_pci.pci_pocmr1 = cpu_to_le32(pocmr | POCMR_ENABLE);
-
- /*
- * Set up master window that allows the CPU to access PCI IO space. This window
- * is set up using the third set of Outbound ATU registers.
- */
- immap->im_pci.pci_potar2 = cpu_to_le32(MPC826x_PCI_IO_BASE >> 12);
- immap->im_pci.pci_pobar2 = cpu_to_le32(MPC826x_PCI_LOWER_IO >> 12);
- pocmr = ((MPC826x_PCI_UPPER_IO - MPC826x_PCI_LOWER_IO) >> 12) ^ 0xfffff;
- immap->im_pci.pci_pocmr2 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PCI_IO);
-
- /*
- * Set up slave window that allows PCI masters to access MPC826x local memory.
- * This window is set up using the first set of Inbound ATU registers
- */
-
- immap->im_pci.pci_pitar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_LOCAL >> 12);
- immap->im_pci.pci_pibar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_BUS >> 12);
- pocmr = ((MPC826x_PCI_SLAVE_MEM_SIZE-1) >> 12) ^ 0xfffff;
- immap->im_pci.pci_picmr0 = cpu_to_le32(pocmr | PICMR_ENABLE | PICMR_PREFETCH_EN);
-
- /* See above for description - puts PCI request as highest priority */
- immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
-
- /* Park the bus on the PCI */
- immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
-
- /* Host mode - specify the bridge as a host-PCI bridge */
- early_write_config_word(hose, 0, 0, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_HOST);
-
- /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
- early_read_config_word(hose, 0, 0, PCI_COMMAND, &tempShort);
- early_write_config_word(hose, 0, 0, PCI_COMMAND,
- tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-}
-
-void __init m8260_find_bridges(void)
-{
- extern int pci_assign_all_busses;
- struct pci_controller * hose;
-
- pci_assign_all_busses = 1;
-
- hose = pcibios_alloc_controller();
-
- if (!hose)
- return;
-
- ppc_md.pci_swizzle = common_swizzle;
-
- hose->first_busno = 0;
- hose->bus_offset = 0;
- hose->last_busno = 0xff;
-
- setup_m8260_indirect_pci(hose,
- (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
- (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
-
- m8260_setup_pci(hose);
- hose->pci_mem_offset = MPC826x_PCI_MEM_OFFSET;
-
- hose->io_base_virt = ioremap(MPC826x_PCI_IO_BASE,
- MPC826x_PCI_IO_SIZE);
- isa_io_base = (unsigned long) hose->io_base_virt;
-
- /* setup resources */
- pci_init_resource(&hose->mem_resources[0],
- MPC826x_PCI_LOWER_MEM,
- MPC826x_PCI_UPPER_MEM,
- IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
-
- pci_init_resource(&hose->mem_resources[1],
- MPC826x_PCI_LOWER_MMIO,
- MPC826x_PCI_UPPER_MMIO,
- IORESOURCE_MEM, "PCI memory");
-
- pci_init_resource(&hose->io_resource,
- MPC826x_PCI_LOWER_IO,
- MPC826x_PCI_UPPER_IO,
- IORESOURCE_IO, "PCI I/O");
-}
Index: arch/ppc/syslib/m8260_pci.h
===================================================================
--- eed337ef5e9ae7d62caa84b7974a11fddc7f06e0/arch/ppc/syslib/m8260_pci.h (mode:100644 sha1:d1352120acd7ef7853041098bf12ae79a8ac1e0a)
+++ /dev/null (tree:874039bc658fe59955b149328a70521a56744a27)
@@ -1,76 +0,0 @@
-
-#ifndef _PPC_KERNEL_M8260_PCI_H
-#define _PPC_KERNEL_M8260_PCI_H
-
-#include <asm/m8260_pci.h>
-
-/*
- * Local->PCI map (from CPU) controlled by
- * MPC826x master window
- *
- * 0x80000000 - 0xBFFFFFFF Total CPU2PCI space PCIBR0
- *
- * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
- * 0xA0000000 - 0xAFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
- * 0xB0000000 - 0xB0FFFFFF 32-bit PCI IO (Outbound ATU #3)
- *
- * PCI->Local map (from PCI)
- * MPC826x slave window controlled by
- *
- * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
- */
-
-/*
- * Slave window that allows PCI masters to access MPC826x local memory.
- * This window is set up using the first set of Inbound ATU registers
- */
-
-#ifndef MPC826x_PCI_SLAVE_MEM_LOCAL
-#define MPC826x_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart)
-#define MPC826x_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart)
-#define MPC826x_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize)
-#endif
-
-/*
- * This is the window that allows the CPU to access PCI address space.
- * It will be setup with the SIU PCIBR0 register. All three PCI master
- * windows, which allow the CPU to access PCI prefetch, non prefetch,
- * and IO space (see below), must all fit within this window.
- */
-#ifndef MPC826x_PCI_BASE
-#define MPC826x_PCI_BASE 0x80000000
-#define MPC826x_PCI_MASK 0xc0000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_MEM
-#define MPC826x_PCI_LOWER_MEM 0x80000000
-#define MPC826x_PCI_UPPER_MEM 0x9fffffff
-#define MPC826x_PCI_MEM_OFFSET 0x00000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_MMIO
-#define MPC826x_PCI_LOWER_MMIO 0xa0000000
-#define MPC826x_PCI_UPPER_MMIO 0xafffffff
-#define MPC826x_PCI_MMIO_OFFSET 0x00000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_IO
-#define MPC826x_PCI_LOWER_IO 0x00000000
-#define MPC826x_PCI_UPPER_IO 0x00ffffff
-#define MPC826x_PCI_IO_BASE 0xb0000000
-#define MPC826x_PCI_IO_SIZE 0x01000000
-#endif
-
-#ifndef _IO_BASE
-#define _IO_BASE isa_io_base
-#endif
-
-#ifdef CONFIG_8260_PCI9
-struct pci_controller;
-extern void setup_m8260_indirect_pci(struct pci_controller* hose,
- u32 cfg_addr, u32 cfg_data);
-#else
-#define setup_m8260_indirect_pci setup_indirect_pci
-#endif
-
-#endif /* _PPC_KERNEL_M8260_PCI_H */
Index: arch/ppc/syslib/m8260_pci_erratum9.c
===================================================================
--- eed337ef5e9ae7d62caa84b7974a11fddc7f06e0/arch/ppc/syslib/m8260_pci_erratum9.c (mode:100644 sha1:9c0582d639e051ccba4d213044045bf99211550c)
+++ 874039bc658fe59955b149328a70521a56744a27/arch/ppc/syslib/m8260_pci_erratum9.c (mode:100644 sha1:1dc7e4e1d4914ed5d11f583b944de475092436d7)
@@ -31,7 +31,7 @@
#include <asm/immap_cpm2.h>
#include <asm/cpm2.h>
-#include "m8260_pci.h"
+#include "m82xx_pci.h"
#ifdef CONFIG_8260_PCI9
/*#include <asm/mpc8260_pci9.h>*/ /* included in asm/io.h */
@@ -248,11 +248,11 @@
static inline int is_pci_mem(unsigned long addr)
{
- if (addr >= MPC826x_PCI_LOWER_MMIO &&
- addr <= MPC826x_PCI_UPPER_MMIO)
+ if (addr >= M82xx_PCI_LOWER_MMIO &&
+ addr <= M82xx_PCI_UPPER_MMIO)
return 1;
- if (addr >= MPC826x_PCI_LOWER_MEM &&
- addr <= MPC826x_PCI_UPPER_MEM)
+ if (addr >= M82xx_PCI_LOWER_MEM &&
+ addr <= M82xx_PCI_UPPER_MEM)
return 1;
return 0;
}
Index: arch/ppc/syslib/m8260_setup.c
===================================================================
--- eed337ef5e9ae7d62caa84b7974a11fddc7f06e0/arch/ppc/syslib/m8260_setup.c (mode:100644 sha1:23ea3f694de2066ec5b324ebedb38b1c027415ce)
+++ 874039bc658fe59955b149328a70521a56744a27/arch/ppc/syslib/m8260_setup.c (mode:100644 sha1:fda75d79050c3e9201ce7033193645bd74609aec)
@@ -34,7 +34,8 @@
unsigned char __res[sizeof(bd_t)];
extern void cpm2_reset(void);
-extern void m8260_find_bridges(void);
+extern void pq2_find_bridges(void);
+extern void pq2pci_init_irq(void);
extern void idma_pci9_init(void);
/* Place-holder for board-specific init */
@@ -56,7 +57,7 @@
idma_pci9_init();
#endif
#ifdef CONFIG_PCI_8260
- m8260_find_bridges();
+ pq2_find_bridges();
#endif
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
@@ -173,6 +174,12 @@
* in case the boot rom changed something on us.
*/
cpm2_immr->im_intctl.ic_siprr = 0x05309770;
+
+#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS))
+ /* Initialize stuff for the 82xx CPLD IC and install demux */
+ pq2pci_init_irq();
+#endif
+
}
/*
Index: arch/ppc/syslib/m82xx_pci.c
===================================================================
--- /dev/null (tree:eed337ef5e9ae7d62caa84b7974a11fddc7f06e0)
+++ 874039bc658fe59955b149328a70521a56744a27/arch/ppc/syslib/m82xx_pci.c (mode:100644 sha1:0e56792a88b73ee42b3496caeaaf94015baaa752)
@@ -0,0 +1,383 @@
+/*
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004 Red Hat, Inc.
+ *
+ * 2005 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/immap_cpm2.h>
+#include <asm/mpc8260.h>
+#include <asm/cpm2.h>
+
+#include "m82xx_pci.h"
+
+/*
+ * Interrupt routing
+ */
+
+static inline int
+pq2pci_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */
+ { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */
+ { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */
+ };
+
+ const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void
+pq2pci_mask_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_unmask_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_mask_and_ack(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_end_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+struct hw_interrupt_type pq2pci_ic = {
+ "PQ2 PCI",
+ NULL,
+ NULL,
+ pq2pci_unmask_irq,
+ pq2pci_mask_irq,
+ pq2pci_mask_and_ack,
+ pq2pci_end_irq,
+ 0
+};
+
+static irqreturn_t
+pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
+{
+ unsigned long stat, mask, pend;
+ int bit;
+
+ for(;;) {
+ stat = *(volatile unsigned long *) PCI_INT_STAT_REG;
+ mask = *(volatile unsigned long *) PCI_INT_MASK_REG;
+ pend = stat & ~mask & 0xf0000000;
+ if (!pend)
+ break;
+ for (bit = 0; pend != 0; ++bit, pend <<= 1) {
+ if (pend & 0x80000000)
+ __do_IRQ(NR_CPM_INTS + bit, regs);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction pq2pci_irqaction = {
+ .handler = pq2pci_irq_demux,
+ .flags = SA_INTERRUPT,
+ .mask = CPU_MASK_NONE,
+ .name = "PQ2 PCI cascade",
+};
+
+
+void
+pq2pci_init_irq(void)
+{
+ int irq;
+ volatile cpm2_map_t *immap = cpm2_immr;
+#if defined CONFIG_ADS8272
+ /* configure chip select for PCI interrupt controller */
+ immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or3 = 0xffff8010;
+#elif defined CONFIG_PQ2FADS
+ immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or8 = 0xffff8010;
+#endif
+ for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
+ irq_desc[irq].handler = &pq2pci_ic;
+
+ /* make PCI IRQ level sensitive */
+ immap->im_intctl.ic_siexr &=
+ ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1)));
+
+ /* mask all PCI interrupts */
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
+
+ /* install the demultiplexer for the PCI cascade interrupt */
+ setup_irq(PCI_INT_TO_SIU, &pq2pci_irqaction);
+ return;
+}
+
+static int
+pq2pci_exclude_device(u_char bus, u_char devfn)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/* PCI bus configuration registers.
+ */
+static void
+pq2ads_setup_pci(struct pci_controller *hose)
+{
+ __u32 val;
+ volatile cpm2_map_t *immap = cpm2_immr;
+ bd_t* binfo = (bd_t*) __res;
+ u32 sccr = immap->im_clkrst.car_sccr;
+ uint pci_div,freq,time;
+ /* PCI int lowest prio */
+ /* Each 4 bits is a device bus request and the MS 4bits
+ is highest priority */
+ /* Bus 4bit value
+ --- ----------
+ CPM high 0b0000
+ CPM middle 0b0001
+ CPM low 0b0010
+ PCI reguest 0b0011
+ Reserved 0b0100
+ Reserved 0b0101
+ Internal Core 0b0110
+ External Master 1 0b0111
+ External Master 2 0b1000
+ External Master 3 0b1001
+ The rest are reserved
+ */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
+ /* park bus on core */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;
+ /*
+ * Set up master windows that allow the CPU to access PCI space. These
+ * windows are set up using the two SIU PCIBR registers.
+ */
+
+ immap->im_memctl.memc_pcimsk0 = M82xx_PCI_PRIM_WND_SIZE;
+ immap->im_memctl.memc_pcibr0 = M82xx_PCI_PRIM_WND_BASE | PCIBR_ENABLE;
+
+#ifdef M82xx_PCI_SEC_WND_SIZE
+ immap->im_memctl.memc_pcimsk1 = M82xx_PCI_SEC_WND_SIZE;
+ immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE;
+#endif
+
+#if defined CONFIG_ADS8272
+ immap->im_siu_conf.siu_82xx.sc_siumcr =
+ (immap->im_siu_conf.siu_82xx.sc_siumcr &
+ ~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE |
+ SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 |
+ SIUMCR_LBPC11 | SIUMCR_APPC11 |
+ SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) |
+ SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 |
+ SIUMCR_APPC10 | SIUMCR_CS10PC00 |
+ SIUMCR_BCTLC00 | SIUMCR_MMR11 ;
+
+#elif defined CONFIG_PQ2FADS
+ /*
+ * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
+ * and local bus for PCI (SIUMCR [LBPC]).
+ */
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
+ SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10;
+#endif
+ /* Enable PCI */
+ immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
+
+ pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
+ ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
+ freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div));
+ time = (int)666666/freq;
+ /* due to PCI Local Bus spec, some devices needs to wait such a long
+ time after RST deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */
+ printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq,
+ (time==1) ? "0.5 seconds":"1 second" );
+
+ {
+ int i;
+ for(i=0;i<(500*time);i++)
+ udelay(1000);
+ }
+
+ /* setup ATU registers */
+ immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |
+ ((~(M82xx_PCI_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar0 = cpu_to_le32(M82xx_PCI_LOWER_IO >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar0 = cpu_to_le32(M82xx_PCI_IO_BASE >> POTA_ADDR_SHIFT);
+
+ /* Set-up non-prefetchable window */
+ immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(M82xx_PCI_MMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar1 = cpu_to_le32(M82xx_PCI_LOWER_MMIO >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar1 = cpu_to_le32((M82xx_PCI_LOWER_MMIO - M82xx_PCI_MMIO_OFFSET) >> POTA_ADDR_SHIFT);
+
+ /* Set-up prefetchable window */
+ immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |
+ (~(M82xx_PCI_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar2 = cpu_to_le32(M82xx_PCI_LOWER_MEM >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar2 = cpu_to_le32((M82xx_PCI_LOWER_MEM - M82xx_PCI_MEM_OFFSET) >> POTA_ADDR_SHIFT);
+
+ /* Inbound transactions from PCI memory space */
+ immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN |
+ ((~(M82xx_PCI_SLAVE_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT));
+ immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT);
+ immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT);
+
+#if defined CONFIG_ADS8272
+ /* PCI int highest prio */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
+#elif defined CONFIG_PQ2FADS
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
+#endif
+ /* park bus on PCI */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
+
+ /* Enable bus mastering and inbound memory transactions */
+ early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);
+ val &= 0xffff0000;
+ val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
+ early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);
+
+}
+
+void __init pq2_find_bridges(void)
+{
+ extern int pci_assign_all_busses;
+ struct pci_controller * hose;
+ int host_bridge;
+
+ pci_assign_all_busses = 1;
+
+ hose = pcibios_alloc_controller();
+
+ if (!hose)
+ return;
+
+ ppc_md.pci_swizzle = common_swizzle;
+
+ hose->first_busno = 0;
+ hose->bus_offset = 0;
+ hose->last_busno = 0xff;
+
+#ifdef CONFIG_ADS8272
+ hose->set_cfg_type = 1;
+#endif
+
+ setup_m8260_indirect_pci(hose,
+ (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
+ (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
+
+ /* Make sure it is a supported bridge */
+ early_read_config_dword(hose,
+ 0,
+ PCI_DEVFN(0,0),
+ PCI_VENDOR_ID,
+ &host_bridge);
+ switch (host_bridge) {
+ case PCI_DEVICE_ID_MPC8265:
+ break;
+ case PCI_DEVICE_ID_MPC8272:
+ break;
+ default:
+ printk("Attempting to use unrecognized host bridge ID"
+ " 0x%08x.\n", host_bridge);
+ break;
+ }
+
+ pq2ads_setup_pci(hose);
+
+ hose->io_space.start = M82xx_PCI_LOWER_IO;
+ hose->io_space.end = M82xx_PCI_UPPER_IO;
+ hose->mem_space.start = M82xx_PCI_LOWER_MEM;
+ hose->mem_space.end = M82xx_PCI_UPPER_MMIO;
+ hose->pci_mem_offset = M82xx_PCI_MEM_OFFSET;
+
+ isa_io_base =
+ (unsigned long) ioremap(M82xx_PCI_IO_BASE,
+ M82xx_PCI_IO_SIZE);
+ hose->io_base_virt = (void *) isa_io_base;
+
+ /* setup resources */
+ pci_init_resource(&hose->mem_resources[0],
+ M82xx_PCI_LOWER_MEM,
+ M82xx_PCI_UPPER_MEM,
+ IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
+
+ pci_init_resource(&hose->mem_resources[1],
+ M82xx_PCI_LOWER_MMIO,
+ M82xx_PCI_UPPER_MMIO,
+ IORESOURCE_MEM, "PCI memory");
+
+ pci_init_resource(&hose->io_resource,
+ M82xx_PCI_LOWER_IO,
+ M82xx_PCI_UPPER_IO,
+ IORESOURCE_IO | 1, "PCI I/O");
+
+ ppc_md.pci_exclude_device = pq2pci_exclude_device;
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+ ppc_md.pci_map_irq = pq2pci_map_irq;
+ ppc_md.pcibios_fixup = NULL;
+ ppc_md.pcibios_fixup_bus = NULL;
+
+}
Index: arch/ppc/syslib/m82xx_pci.h
===================================================================
--- /dev/null (tree:eed337ef5e9ae7d62caa84b7974a11fddc7f06e0)
+++ 874039bc658fe59955b149328a70521a56744a27/arch/ppc/syslib/m82xx_pci.h (mode:100644 sha1:0e95bf6a73b0be65ee5dcc36374f4e8870f82c37)
@@ -0,0 +1,92 @@
+
+#ifndef _PPC_KERNEL_M82XX_PCI_H
+#define _PPC_KERNEL_M82XX_PCI_H
+
+#include <asm/m8260_pci.h>
+/*
+ * Local->PCI map (from CPU) controlled by
+ * MPC826x master window
+ *
+ * 0xF6000000 - 0xF7FFFFFF IO space
+ * 0x80000000 - 0xBFFFFFFF CPU2PCI memory space PCIBR0
+ *
+ * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
+ * 0xA0000000 - 0xBFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
+ * 0xF6000000 - 0xF7FFFFFF 32-bit PCI IO (Outbound ATU #3)
+ *
+ * PCI->Local map (from PCI)
+ * MPC826x slave window controlled by
+ *
+ * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
+ */
+
+/*
+ * Slave window that allows PCI masters to access MPC826x local memory.
+ * This window is set up using the first set of Inbound ATU registers
+ */
+
+#ifndef M82xx_PCI_SLAVE_MEM_LOCAL
+#define M82xx_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart)
+#define M82xx_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart)
+#define M82xx_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize)
+#endif
+
+/*
+ * This is the window that allows the CPU to access PCI address space.
+ * It will be setup with the SIU PCIBR0 register. All three PCI master
+ * windows, which allow the CPU to access PCI prefetch, non prefetch,
+ * and IO space (see below), must all fit within this window.
+ */
+
+#ifndef M82xx_PCI_LOWER_MEM
+#define M82xx_PCI_LOWER_MEM 0x80000000
+#define M82xx_PCI_UPPER_MEM 0x9fffffff
+#define M82xx_PCI_MEM_OFFSET 0x00000000
+#define M82xx_PCI_MEM_SIZE 0x20000000
+#endif
+
+#ifndef M82xx_PCI_LOWER_MMIO
+#define M82xx_PCI_LOWER_MMIO 0xa0000000
+#define M82xx_PCI_UPPER_MMIO 0xafffffff
+#define M82xx_PCI_MMIO_OFFSET 0x00000000
+#define M82xx_PCI_MMIO_SIZE 0x20000000
+#endif
+
+#ifndef M82xx_PCI_LOWER_IO
+#define M82xx_PCI_LOWER_IO 0x00000000
+#define M82xx_PCI_UPPER_IO 0x01ffffff
+#define M82xx_PCI_IO_BASE 0xf6000000
+#define M82xx_PCI_IO_SIZE 0x02000000
+#endif
+
+#ifndef M82xx_PCI_PRIM_WND_SIZE
+#define M82xx_PCI_PRIM_WND_SIZE ~(M82xx_PCI_IO_SIZE - 1U)
+#define M82xx_PCI_PRIM_WND_BASE (M82xx_PCI_IO_BASE)
+#endif
+
+#ifndef M82xx_PCI_SEC_WND_SIZE
+#define M82xx_PCI_SEC_WND_SIZE ~(M82xx_PCI_MEM_SIZE + M82xx_PCI_MMIO_SIZE - 1U)
+#define M82xx_PCI_SEC_WND_BASE (M82xx_PCI_LOWER_MEM)
+#endif
+
+#ifndef POTA_ADDR_SHIFT
+#define POTA_ADDR_SHIFT 12
+#endif
+
+#ifndef PITA_ADDR_SHIFT
+#define PITA_ADDR_SHIFT 12
+#endif
+
+#ifndef _IO_BASE
+#define _IO_BASE isa_io_base
+#endif
+
+#ifdef CONFIG_8260_PCI9
+struct pci_controller;
+extern void setup_m8260_indirect_pci(struct pci_controller* hose,
+ u32 cfg_addr, u32 cfg_data);
+#else
+#define setup_m8260_indirect_pci setup_indirect_pci
+#endif
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */
Index: include/asm-ppc/cpm2.h
===================================================================
--- eed337ef5e9ae7d62caa84b7974a11fddc7f06e0/include/asm-ppc/cpm2.h (mode:100644 sha1:42fd1068cf2a4100f468f439f69c2da3c0fe5b38)
+++ 874039bc658fe59955b149328a70521a56744a27/include/asm-ppc/cpm2.h (mode:100644 sha1:c5883dbed63f8bbf84d8d1eeb11d6f77a93a62ac)
@@ -1039,6 +1039,52 @@
#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register 4-31
+ */
+#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
+#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
+#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
+#define SIUMCR_CDIS 0x10000000 /* Core Disable */
+#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01 0x04000000 /* - " - */
+#define SIUMCR_DPPC10 0x08000000 /* - " - */
+#define SIUMCR_DPPC11 0x0c000000 /* - " - */
+#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
+#define SIUMCR_L2CPC01 0x01000000 /* - " - */
+#define SIUMCR_L2CPC10 0x02000000 /* - " - */
+#define SIUMCR_L2CPC11 0x03000000 /* - " - */
+#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
+#define SIUMCR_LBPC01 0x00400000 /* - " - */
+#define SIUMCR_LBPC10 0x00800000 /* - " - */
+#define SIUMCR_LBPC11 0x00c00000 /* - " - */
+#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01 0x00100000 /* - " - */
+#define SIUMCR_APPC10 0x00200000 /* - " - */
+#define SIUMCR_APPC11 0x00300000 /* - " - */
+#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
+#define SIUMCR_CS10PC01 0x00040000 /* - " - */
+#define SIUMCR_CS10PC10 0x00080000 /* - " - */
+#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
+#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
+#define SIUMCR_BCTLC01 0x00010000 /* - " - */
+#define SIUMCR_BCTLC10 0x00020000 /* - " - */
+#define SIUMCR_BCTLC11 0x00030000 /* - " - */
+#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
+#define SIUMCR_MMR01 0x00004000 /* - " - */
+#define SIUMCR_MMR10 0x00008000 /* - " - */
+#define SIUMCR_MMR11 0x0000c000 /* - " - */
+#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control Register 9-8
+*/
+#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
+#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
+#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
+#define SCCR_PCIDF_SHIFT 3
+
+
#endif /* __CPM2__ */
#endif /* __KERNEL__ */
Index: include/asm-ppc/m8260_pci.h
===================================================================
--- eed337ef5e9ae7d62caa84b7974a11fddc7f06e0/include/asm-ppc/m8260_pci.h (mode:100644 sha1:163a6b91d5b2ffe0c49f9d9814a65a5bc23d0cd0)
+++ 874039bc658fe59955b149328a70521a56744a27/include/asm-ppc/m8260_pci.h (mode:100644 sha1:bf9e05dd54b5243d256f12c5e5df70f6b5a6c128)
@@ -19,6 +19,7 @@
* Define the vendor/device ID for the MPC8265.
*/
#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
#define M8265_PCIBR0 0x101ac
#define M8265_PCIBR1 0x101b0
Index: include/asm-ppc/mpc8260.h
===================================================================
--- eed337ef5e9ae7d62caa84b7974a11fddc7f06e0/include/asm-ppc/mpc8260.h (mode:100644 sha1:d820894e59916a4c491b8bdd0312830acec228a9)
+++ 874039bc658fe59955b149328a70521a56744a27/include/asm-ppc/mpc8260.h (mode:100644 sha1:89eb8a2ac6934552eeaf74d5ed222690ed504732)
@@ -41,7 +41,7 @@
#endif
#ifdef CONFIG_PCI_8260
-#include <syslib/m8260_pci.h>
+#include <syslib/m82xx_pci.h>
#endif
/* Make sure the memory translation stuff is there if PCI not used.
^ permalink raw reply
* Linux 2.6 and mpc823 compile error
From: Björn Östby @ 2005-05-19 12:23 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 3388 bytes --]
Hi,
I'm trying to get Linux 2.6.11 up and running on mpc823e. I'm using the cross compiler
Supplied in ELDK (3.0) and u-boot. The problem is when enabling:
[ ] CPM SCC/SMC serial port support
and/or
[ ] CPM SCC Ethernet
The kernel compiles fine having these option disabled, but otherwise..see below
make arch=ppc CROSS_COMPILE=${CROSS_COMPILE}
.
.
.
CC drivers/serial/serial_core.o
CC drivers/serial/cpm_uart/cpm_uart_core.o
In file included from drivers/serial/cpm_uart/cpm_uart_cpm1.h:13,
from drivers/serial/cpm_uart/cpm_uart.h:17,
from drivers/serial/cpm_uart/cpm_uart_core.c:55:
include/asm/commproc.h:564:1: warning: "PA_ENET_RCLK" redefined In file included from include/asm/mpc8xx.h:36,
from include/asm/processor.h:16,
from include/linux/spinlock.h:16,
from include/linux/capability.h:45,
from include/linux/sched.h:7,
from include/linux/module.h:10,
from drivers/serial/cpm_uart/cpm_uart_core.c:33:
arch/ppc/platforms/tqm8xx.h:91:1: warning: this is the location of the
previous definition
In file included from drivers/serial/cpm_uart/cpm_uart_cpm1.h:13,
from drivers/serial/cpm_uart/cpm_uart.h:17,
from drivers/serial/cpm_uart/cpm_uart_core.c:55:
include/asm/commproc.h:576:1: warning: "SICR_ENET_CLKRT" redefined In file included from include/asm/mpc8xx.h:36,
from include/asm/processor.h:16,
from include/linux/spinlock.h:16,
from include/linux/capability.h:45,
from include/linux/sched.h:7,
from include/linux/module.h:10,
from drivers/serial/cpm_uart/cpm_uart_core.c:33:
arch/ppc/platforms/tqm8xx.h:103:1: warning: this is the location of the
previous definition
In file included from drivers/serial/cpm_uart/cpm_uart.h:17,
from drivers/serial/cpm_uart/cpm_uart_core.c:55:
drivers/serial/cpm_uart/cpm_uart_cpm1.h: In function `cpm_set_brg':
drivers/serial/cpm_uart/cpm_uart_cpm1.h:28: warning: implicit declaration
of function `cpm_setbrg'
drivers/serial/cpm_uart/cpm_uart_core.c: In function `cpm_uart_set_termios':
drivers/serial/cpm_uart/cpm_uart_core.c:460: `SCU_PSMR_SL' undeclared
(first use in this function)
drivers/serial/cpm_uart/cpm_uart_core.c:460: (Each undeclared identifier is reported only once
drivers/serial/cpm_uart/cpm_uart_core.c:460: for each function it appears in.)
drivers/serial/cpm_uart/cpm_uart_core.c:466: `SCU_PSMR_PEN' undeclared
(first use in this function)
drivers/serial/cpm_uart/cpm_uart_core.c:470: `SCU_PSMR_REVP' undeclared
(first use in this function)
drivers/serial/cpm_uart/cpm_uart_core.c:470: `SCU_PSMR_TEVP' undeclared
(first use in this function)
drivers/serial/cpm_uart/cpm_uart_cpm1.h: At top level:
drivers/serial/cpm_uart/cpm_uart_core.c:732: warning: `cpm_uart_init_smc'
defined but not used
drivers/serial/cpm_uart/cpm_uart_core.c:671: warning: `cpm_uart_init_scc'
defined but not used
make[3]: *** [drivers/serial/cpm_uart/cpm_uart_core.o] Error 1
make[2]: *** [drivers/serial/cpm_uart] Error 2
make[1]: *** [drivers/serial] Error 2
make: *** [drivers] Error 2
There it is. Any ideas?
Regards,
Bjorn Ostby
[-- Attachment #2: Type: text/html, Size: 8207 bytes --]
^ permalink raw reply
* QMC HDLC driver
From: LIU.ANDY @ 2005-05-19 11:30 UTC (permalink / raw)
To: linuxppc-embedded
Hello,
We need to use the MPC8247 QMC for multiple HDLC channels. Could anybody give me the related code or a reference? I have two HDLC driver, one for 8260 MCC, and the other for 850 of SCC3. Both are not the QMC hdlc driver.
Any help would be appreciated.
Best Regards
Kamn
----------------------------------------------
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^ permalink raw reply
* experimental kernel patch for FORTIFY_SOURCE in kernel space
From: Arjan van de Ven @ 2005-05-19 9:56 UTC (permalink / raw)
To: linuxppc-dev
Hi,
There is a gcc patch in development (posted to the patches list several
times now and getting close to done) that allows gcc to track the size of
objects at compile time. The idea is that for code like
void func(char *str)
{
char buf[20];
strcpy(buf, str);
}
gcc keeps track of "buf" being 20 bytes in size and then (together with
glibc) cause that strcpy() to be replaced by a special strcpy that gets "20"
as extra parameter and will cause an abort rather than a buffer overflow if
more than 20 bytes get copied.
This works great in Fedora Core 4 for userland (the technology is there in
RHEL4 and FC3 as well but not used for everything), and recently I started
"porting" this to the kernel.
There is somewhat of an architecture impact so before submitting it on lkml
I'd want to ask feedback from more arches than just x86...
Greetings,
Arjan van de Ven
diff -purN linux-2.6.12-rc4/Makefile linux-fortify/Makefile
--- linux-2.6.12-rc4/Makefile 2005-05-14 14:41:18.000000000 +0200
+++ linux-fortify/Makefile 2005-05-15 15:26:33.000000000 +0200
@@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 12
-EXTRAVERSION =-rc4
+EXTRAVERSION =-rc4-fortify
NAME=Woozy Numbat
# *DOCUMENTATION*
diff -purN linux-2.6.12-rc4/arch/i386/Kconfig.debug linux-fortify/arch/i386/Kconfig.debug
--- linux-2.6.12-rc4/arch/i386/Kconfig.debug 2005-05-14 14:41:19.000000000 +0200
+++ linux-fortify/arch/i386/Kconfig.debug 2005-05-15 15:26:33.000000000 +0200
@@ -59,6 +59,14 @@ config 4KSTACKS
on the VM subsystem for higher order allocations. This option
will also use IRQ stacks to compensate for the reduced stackspace.
+config FORTIFY_SOURCE
+ bool "Enable limited buffer overflow checking"
+ help
+ If you say Y here the kernel will use a recent gcc feature that
+ allows several key kernel primitives to check for buffer overflows
+ when dealing with static buffers. Do not enable this feature unless
+ you have a very recent gcc (version 4.1 or gccs from FC3, FC4, RHEL4)
+
config X86_FIND_SMP_CONFIG
bool
depends on X86_LOCAL_APIC || X86_VOYAGER
diff -purN linux-2.6.12-rc4/include/asm-i386/string.h linux-fortify/include/asm-i386/string.h
--- linux-2.6.12-rc4/include/asm-i386/string.h 2005-05-14 14:41:21.000000000 +0200
+++ linux-fortify/include/asm-i386/string.h 2005-05-15 17:03:06.000000000 +0200
@@ -23,11 +23,14 @@
* consider these trivial functions to be PD.
*/
+
/* AK: in fact I bet it would be better to move this stuff all out of line.
+ * Arjan: .. or just straight use the gcc built-in versions
*/
+
#define __HAVE_ARCH_STRCPY
-static inline char * strcpy(char * dest,const char *src)
+extern inline char * strcpy(char * dest,const char *src)
{
int d0, d1, d2;
__asm__ __volatile__(
@@ -41,7 +44,7 @@ return dest;
}
#define __HAVE_ARCH_STRNCPY
-static inline char * strncpy(char * dest,const char *src,size_t count)
+extern inline char * strncpy(char * dest,const char *src,size_t count)
{
int d0, d1, d2, d3;
__asm__ __volatile__(
@@ -60,7 +63,7 @@ return dest;
}
#define __HAVE_ARCH_STRCAT
-static inline char * strcat(char * dest,const char * src)
+extern inline char * strcat(char * dest,const char * src)
{
int d0, d1, d2, d3;
__asm__ __volatile__(
@@ -77,7 +80,7 @@ return dest;
}
#define __HAVE_ARCH_STRNCAT
-static inline char * strncat(char * dest,const char * src,size_t count)
+extern inline char * strncat(char * dest,const char * src,size_t count)
{
int d0, d1, d2, d3;
__asm__ __volatile__(
diff -purN linux-2.6.12-rc4/include/asm-i386/uaccess.h linux-fortify/include/asm-i386/uaccess.h
--- linux-2.6.12-rc4/include/asm-i386/uaccess.h 2005-05-14 14:41:21.000000000 +0200
+++ linux-fortify/include/asm-i386/uaccess.h 2005-05-15 15:26:33.000000000 +0200
@@ -9,6 +9,7 @@
#include <linux/thread_info.h>
#include <linux/prefetch.h>
#include <linux/string.h>
+#include <linux/compiler.h>
#include <asm/page.h>
#define VERIFY_READ 0
@@ -507,10 +508,6 @@ __copy_from_user(void *to, const void __
might_sleep();
return __copy_from_user_inatomic(to, from, n);
}
-unsigned long __must_check copy_to_user(void __user *to,
- const void *from, unsigned long n);
-unsigned long __must_check copy_from_user(void *to,
- const void __user *from, unsigned long n);
long __must_check strncpy_from_user(char *dst, const char __user *src,
long count);
long __must_check __strncpy_from_user(char *dst,
@@ -536,4 +533,40 @@ long strnlen_user(const char __user *str
unsigned long __must_check clear_user(void __user *mem, unsigned long len);
unsigned long __must_check __clear_user(void __user *mem, unsigned long len);
+
+unsigned long __must_check copy_to_user(void __user *to,
+ const void *from, unsigned long n);
+
+#ifdef CONFIG_FORTIFY_SOURCE
+
+extern void __chk_fail(void);
+
+/*
+ * the inline function with the check wants to call the non-inlined function
+ * with the same name for the actual work. The easiest way to do this is to make
+ * an alias of the real function and just call this alias from the inline.
+ */
+extern int __c_f_u_alias(void *to, const void __user *from, unsigned long __nbytes) __asm__ ("" "copy_from_user");
+
+
+extern unsigned long __always_inline __must_check
+copy_from_user (void *to, const void __user *from, unsigned long __nbytes)
+{
+ /*
+ * if we know the size of "to" then we can validate that we don't overrun the buffer.
+ * note that if __nbytes is known at compiletime this check is nicely optimized out
+ */
+ if (__bos0 (to) != (size_t) -1 && __nbytes > __bos0 (to))
+ __chk_fail();
+ return __c_f_u_alias (to, from, __nbytes);
+}
+
+#else
+
+unsigned long __must_check copy_to_user(void __user *to,
+ const void *from, unsigned long n);
+
+#endif
+
+
#endif /* __i386_UACCESS_H */
diff -purN linux-2.6.12-rc4/include/linux/compiler-gcc3.h linux-fortify/include/linux/compiler-gcc3.h
--- linux-2.6.12-rc4/include/linux/compiler-gcc3.h 2005-05-14 14:41:21.000000000 +0200
+++ linux-fortify/include/linux/compiler-gcc3.h 2005-05-15 15:26:33.000000000 +0200
@@ -30,3 +30,8 @@
#define __must_check __attribute__((warn_unused_result))
#endif
+
+#if defined(__GNUC_RH_RELEASE__) && __GNUC_MINOR__ >= 4 && __GNUC_PATCHLEVEL__ >=2
+#define __bos(ptr) __builtin_object_size (ptr, 1)
+#define __bos0(ptr) __builtin_object_size (ptr, 0)
+#endif
diff -purN linux-2.6.12-rc4/include/linux/compiler-gcc4.h linux-fortify/include/linux/compiler-gcc4.h
--- linux-2.6.12-rc4/include/linux/compiler-gcc4.h 2005-05-14 14:41:21.000000000 +0200
+++ linux-fortify/include/linux/compiler-gcc4.h 2005-05-15 15:26:33.000000000 +0200
@@ -14,3 +14,7 @@
#define __must_check __attribute__((warn_unused_result))
#define __compiler_offsetof(a,b) __builtin_offsetof(a,b)
+#if defined(__GNUC_RH_RELEASE__) || __GNUC_MINOR__ >= 1
+#define __bos(ptr) __builtin_object_size (ptr, 1)
+#define __bos0(ptr) __builtin_object_size (ptr, 0)
+#endif
diff -purN linux-2.6.12-rc4/include/linux/compiler.h linux-fortify/include/linux/compiler.h
--- linux-2.6.12-rc4/include/linux/compiler.h 2005-05-14 14:41:21.000000000 +0200
+++ linux-fortify/include/linux/compiler.h 2005-05-15 15:26:33.000000000 +0200
@@ -155,4 +155,13 @@ extern void __chk_io_ptr(void __iomem *)
#define __always_inline inline
#endif
+#ifndef __bos
+#define __bos(x) -1
+#endif
+
+#ifndef __bos0
+#define __bos0(x) -1
+#endif
+
+
#endif /* __LINUX_COMPILER_H */
diff -purN linux-2.6.12-rc4/include/linux/slab.h linux-fortify/include/linux/slab.h
--- linux-2.6.12-rc4/include/linux/slab.h 2005-05-14 14:41:21.000000000 +0200
+++ linux-fortify/include/linux/slab.h 2005-05-15 15:26:33.000000000 +0200
@@ -73,9 +73,9 @@ struct cache_sizes {
kmem_cache_t *cs_dmacachep;
};
extern struct cache_sizes malloc_sizes[];
-extern void *__kmalloc(size_t, unsigned int __nocast);
+extern __attribute__((malloc)) void *__kmalloc(size_t, unsigned int __nocast);
-static inline void *kmalloc(size_t size, unsigned int __nocast flags)
+static inline __attribute__((malloc)) void *kmalloc(size_t size, unsigned int __nocast flags)
{
if (__builtin_constant_p(size)) {
int i = 0;
diff -purN linux-2.6.12-rc4/include/linux/string.h linux-fortify/include/linux/string.h
--- linux-2.6.12-rc4/include/linux/string.h 2005-03-02 08:38:07.000000000 +0100
+++ linux-fortify/include/linux/string.h 2005-05-15 17:12:16.000000000 +0200
@@ -88,6 +88,96 @@ extern int memcmp(const void *,const voi
extern void * memchr(const void *,int,__kernel_size_t);
#endif
+
+#ifdef CONFIG_FORTIFY_SOURCE
+
+/*
+ * "fortified" variants of some of these functions that for certain cases make
+ * gcc emit code that checks for buffer overflows.
+ */
+
+#undef strcpy
+#undef __HAVE_ARCH_STRCPY
+#define strcpy(dest, src) \
+ ((__bos (dest) != (size_t) -1) \
+ ? __builtin___strcpy_chk (dest, src, __bos (dest)) \
+ : __strcpy_ichk (dest, src))
+static __always_inline char *
+__strcpy_ichk (char * __dest, const char * __src)
+{
+ return __builtin___strcpy_chk (__dest, __src, __bos (__dest));
+}
+
+#undef strncpy
+#undef __HAVE_ARCH_STRNCPY
+#define strncpy(dest, src, len) \
+ ((__bos (dest) != (size_t) -1) \
+ ? __builtin___strncpy_chk (dest, src, len, __bos (dest)) \
+ : __strncpy_ichk (dest, src, len))
+static __always_inline char *
+__strncpy_ichk (char * __dest, const char * __src, size_t __len)
+{
+ return __builtin___strncpy_chk (__dest, __src, __len, __bos (__dest));
+}
+
+#undef strcat
+#undef __HAVE_ARCH_STRCAT
+#define strcat(dest, src) \
+ ((__bos (dest) != (size_t) -1) \
+ ? __builtin___strcat_chk (dest, src, __bos (dest)) \
+ : __strcat_ichk (dest, src))
+static __always_inline char *
+__strcat_ichk (char * __dest, const char * __src)
+{
+ return __builtin___strcat_chk (__dest, __src, __bos (__dest));
+}
+
+#undef strncat
+#undef __HAVE_ARCH_STRNCAT
+#define strncat(dest, src, len) \
+ ((__bos (dest) != (size_t) -1) \
+ ? __builtin___strncat_chk (dest, src, len, __bos (dest)) \
+ : __strncat_ichk (dest, src, len))
+static __always_inline char *
+__strncat_ichk (char * __dest, const char * __src, size_t __len)
+{
+ return __builtin___strncat_chk (__dest, __src, __len, __bos (__dest));
+}
+
+#undef memcpy
+#define memcpy(dest, src, len) \
+ ((__bos0 (dest) != (size_t) -1) \
+ ? __builtin___memcpy_chk (dest, src, len, __bos0 (dest)) \
+ : __memcpy_ichk (dest, src, len))
+static __always_inline void *
+__memcpy_ichk (void * __dest, const void *__src, size_t __len)
+{
+ return __builtin___memcpy_chk (__dest, __src, __len, __bos0 (__dest));
+}
+
+/* memset(x,y,0) is a common typo; this dummy non-existent function is
+ * there to create a linker error in that case
+ */
+extern void __warn_memset_zero_len(void);
+
+#undef memset
+#define memset(dest, ch, len) \
+ (__builtin_constant_p (len) && (len) == 0 && (!__builtin_constant_p(ch) || ((ch)!=0)) \
+ ? (__warn_memset_zero_len (), (void) (ch), (void) (len), (void *) (dest)) \
+ : ((__bos0 (dest) != (size_t) -1) \
+ ? __builtin___memset_chk (dest, ch, len, __bos0 (dest)) \
+ : __memset_ichk (dest, ch, len)))
+
+static __always_inline void *
+__memset_ichk (void *__dest, int __ch, size_t __len)
+{
+ return __builtin___memset_chk (__dest, __ch, __len, __bos0 (__dest));
+}
+
+
+#endif
+
+
#ifdef __cplusplus
}
#endif
diff -purN linux-2.6.12-rc4/lib/Makefile linux-fortify/lib/Makefile
--- linux-2.6.12-rc4/lib/Makefile 2005-05-14 14:41:21.000000000 +0200
+++ linux-fortify/lib/Makefile 2005-05-15 15:26:33.000000000 +0200
@@ -18,6 +18,7 @@ endif
lib-$(CONFIG_RWSEM_GENERIC_SPINLOCK) += rwsem-spinlock.o
lib-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem.o
lib-$(CONFIG_GENERIC_FIND_NEXT_BIT) += find_next_bit.o
+lib-$(CONFIG_FORTIFY_SOURCE) += fortify.o
obj-$(CONFIG_LOCK_KERNEL) += kernel_lock.o
ifneq ($(CONFIG_HAVE_DEC_LOCK),y)
diff -purN linux-2.6.12-rc4/lib/fortify.c linux-fortify/lib/fortify.c
--- linux-2.6.12-rc4/lib/fortify.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-fortify/lib/fortify.c 2005-05-15 16:29:15.000000000 +0200
@@ -0,0 +1,292 @@
+/*
+ * Copyright (C) 1991, 1997, 2003, 2004 Free Software Foundation, Inc.
+ * Portions Copyright (C) 2005 Red Hat, Inc.
+ * Portions Copyright (C) 1991, 1992 Linus Torvalds
+ *
+ * (Several of these functions were copied from various FSF projects)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <linux/module.h>
+
+
+void __chk_fail(void)
+{
+ printk("** kernel buffer overflow detected via application %s ***\n", current->comm);
+ panic("Aborting!\n");
+}
+EXPORT_SYMBOL_GPL(__chk_fail);
+
+void * __memcpy_chk (void *dstpp, const void* srcpp, size_t len, size_t dstlen)
+{
+ char *d = (char *) dstpp, *s = (char *) srcpp;
+
+ if (unlikely(dstlen < len))
+ __chk_fail ();
+
+ while (len--)
+ *d++ = *s++;
+
+ return d;
+}
+
+EXPORT_SYMBOL_GPL(__memcpy_chk);
+
+void * __memset_chk (void *dst, const int c, size_t len, size_t dstlen)
+{
+ char *d = (char *) dst;
+
+ if (unlikely(dstlen < len))
+ __chk_fail ();
+
+ while (len--)
+ *d++ = c;
+
+ return d;
+}
+
+EXPORT_SYMBOL_GPL(__memset_chk);
+
+/* Copy SRC to DEST with checking of destination buffer overflow. */
+char * __strcpy_chk (char *dest, const char *src, size_t destlen)
+{
+ char c;
+ char *s = (char *) src;
+ const ptrdiff_t off = dest - s;
+
+ while (__builtin_expect (destlen >= 4, 0))
+ {
+ c = s[0];
+ s[off] = c;
+ if (c == '\0')
+ return dest;
+ c = s[1];
+ s[off + 1] = c;
+ if (c == '\0')
+ return dest;
+ c = s[2];
+ s[off + 2] = c;
+ if (c == '\0')
+ return dest;
+ c = s[3];
+ s[off + 3] = c;
+ if (c == '\0')
+ return dest;
+ destlen -= 4;
+ s += 4;
+ }
+
+ do
+ {
+ if (__builtin_expect (destlen-- == 0, 0))
+ __chk_fail ();
+ c = *s;
+ *(s++ + off) = c;
+ }
+ while (c != '\0');
+
+ return dest;
+}
+
+EXPORT_SYMBOL_GPL(__strcpy_chk);
+
+
+char * __strcat_chk (char *dest, const char *src, size_t destlen)
+{
+ char *s1 = dest;
+ const char *s2 = src;
+ char c;
+
+ /* Find the end of the string. */
+ do
+ {
+ if (__builtin_expect (destlen-- == 0, 0))
+ __chk_fail ();
+ c = *s1++;
+ }
+ while (c != '\0');
+
+ /* Make S1 point before the next character, so we can increment
+ it while memory is read (wins on pipelined cpus). */
+ ++destlen;
+ s1 -= 2;
+
+ do
+ {
+ if (__builtin_expect (destlen-- == 0, 0))
+ __chk_fail ();
+ c = *s2++;
+ *++s1 = c;
+ }
+ while (c != '\0');
+
+ return dest;
+}
+
+EXPORT_SYMBOL_GPL(__strcat_chk);
+
+char * __strncat_chk (char *s1, const char *s2, size_t n, size_t s1len)
+{
+ char c;
+ char *s = s1;
+
+ /* Find the end of S1. */
+ do
+ {
+ if (__builtin_expect (s1len-- == 0, 0))
+ __chk_fail ();
+ c = *s1++;
+ }
+ while (c != '\0');
+
+ /* Make S1 point before next character, so we can increment
+ it while memory is read (wins on pipelined cpus). */
+ ++s1len;
+ s1 -= 2;
+
+ if (n >= 4)
+ {
+ size_t n4 = n >> 2;
+ do
+ {
+ if (__builtin_expect (s1len-- == 0, 0))
+ __chk_fail ();
+ c = *s2++;
+ *++s1 = c;
+ if (c == '\0')
+ return s;
+ if (__builtin_expect (s1len-- == 0, 0))
+ __chk_fail ();
+ c = *s2++;
+ *++s1 = c;
+ if (c == '\0')
+ return s;
+ if (__builtin_expect (s1len-- == 0, 0))
+ __chk_fail ();
+ c = *s2++;
+ *++s1 = c;
+ if (c == '\0')
+ return s;
+ if (__builtin_expect (s1len-- == 0, 0))
+ __chk_fail ();
+ c = *s2++;
+ *++s1 = c;
+ if (c == '\0')
+ return s;
+ } while (--n4 > 0);
+ n &= 3;
+ }
+
+ while (n > 0)
+ {
+ if (__builtin_expect (s1len-- == 0, 0))
+ __chk_fail ();
+ c = *s2++;
+ *++s1 = c;
+ if (c == '\0')
+ return s;
+ n--;
+ }
+
+ if (c != '\0')
+ {
+ if (__builtin_expect (s1len-- == 0, 0))
+ __chk_fail ();
+ *++s1 = '\0';
+ }
+
+ return s;
+}
+
+EXPORT_SYMBOL_GPL(__strncat_chk);
+
+
+char * __strncpy_chk (char *s1, const char *s2, size_t n, size_t s1len)
+{
+ char c;
+ char *s = s1;
+
+ if (__builtin_expect (s1len < n, 0))
+ __chk_fail ();
+
+ --s1;
+
+ if (n >= 4)
+ {
+ size_t n4 = n >> 2;
+
+ for (;;)
+ {
+ c = *s2++;
+ *++s1 = c;
+ if (c == '\0')
+ break;
+ c = *s2++;
+ *++s1 = c;
+ if (c == '\0')
+ break;
+ c = *s2++;
+ *++s1 = c;
+ if (c == '\0')
+ break;
+ c = *s2++;
+ *++s1 = c;
+ if (c == '\0')
+ break;
+ if (--n4 == 0)
+ goto last_chars;
+ }
+ n = n - (s1 - s) - 1;
+ if (n == 0)
+ return s;
+ goto zero_fill;
+ }
+
+ last_chars:
+ n &= 3;
+ if (n == 0)
+ return s;
+
+ do
+ {
+ c = *s2++;
+ *++s1 = c;
+ if (--n == 0)
+ return s;
+ }
+ while (c != '\0');
+
+ zero_fill:
+ do
+ *++s1 = '\0';
+ while (--n > 0);
+
+ return s;
+}
+
+EXPORT_SYMBOL_GPL(__strncpy_chk);
+
+
+void dummy(int n)
+{
+ char buf1[20];
+ char buf2[30];
+ memcpy(buf1, buf2, 30);
+ memcpy(buf1, buf2, n);
+}
diff -purN linux-2.6.12-rc4/lib/string.c linux-fortify/lib/string.c
--- linux-2.6.12-rc4/lib/string.c 2005-05-14 14:41:21.000000000 +0200
+++ linux-fortify/lib/string.c 2005-05-15 16:46:05.000000000 +0200
@@ -91,6 +91,7 @@ EXPORT_SYMBOL(strcpy);
* count, the remainder of @dest will be padded with %NUL.
*
*/
+#undef strncpy
char * strncpy(char * dest,const char *src,size_t count)
{
char *tmp = dest;
@@ -162,6 +163,7 @@ EXPORT_SYMBOL(strcat);
* Note that in contrast to strncpy, strncat ensures the result is
* terminated.
*/
+#undef strncat
char * strncat(char *dest, const char *src, size_t count)
{
char *tmp = dest;
@@ -449,6 +451,7 @@ EXPORT_SYMBOL(strsep);
*
* Do not use memset() to access IO space, use memset_io() instead.
*/
+#undef memset
void * memset(void * s,int c,size_t count)
{
char *xs = (char *) s;
@@ -471,6 +474,7 @@ EXPORT_SYMBOL(memset);
* You should not use this function to access IO space, use memcpy_toio()
* or memcpy_fromio() instead.
*/
+#undef memcpy
void * memcpy(void * dest,const void *src,size_t count)
{
char *tmp = (char *) dest, *s = (char *) src;
^ permalink raw reply
* OF flat device tree for ppc32...
From: Jakob Viketoft @ 2005-05-19 6:41 UTC (permalink / raw)
To: Jon Loeliger; +Cc: Linux PPC Embedded list
Hello Jon!
Any news on the port of the OF-layer to ppc32? I'd love to hear some
more and it would be great be able to help out, even though I have some
heavy deadlines hanging over me for the next 2 months. From what I can
see on the list, there wasn't many comments on your first preparatory
code, but I for one thinks it's time to move it forward anyway.
What do you say?
/Jakob
^ permalink raw reply
* Re: DMA consistent allocation is limited to 2MB on 2.6.11 for ppc440?
From: Eugene Surovegin @ 2005-05-19 2:09 UTC (permalink / raw)
To: Shawn Jin; +Cc: ppcembed
In-Reply-To: <c3d0340b05051818524c647e61@mail.gmail.com>
On Wed, May 18, 2005 at 06:52:52PM -0700, Shawn Jin wrote:
> Then what's your recommendation to allocate a big chunk of memory for
> pci device?
My recommendation - don't do this. Why do you need to allocate this
big chunk of consistent memory in the first place? You can do DMA
_without_ allocating "consistent" memory. In fact, this is how
virtually all devices work in Linux. For more info about DMA API -
look at Documentation/DMA-API.txt.
Technically, you can make consistent pool bigger, if you really insist
on using this approach.
--
Eugene
^ permalink raw reply
* Re: DMA consistent allocation is limited to 2MB on 2.6.11 for ppc440?
From: Shawn Jin @ 2005-05-19 1:52 UTC (permalink / raw)
To: Shawn Jin, ppcembed
In-Reply-To: <20050519012404.GA11587@gate.ebshome.net>
> No, _all_ physical memory is available for DMA. "consistent" pool is
> used for small non-cached allocations, e.g. buffer descriptors, etc.
> Don't use it for actual data buffers.
We used to pci_alloc_consistent() to allocate DMA buffers on 2.4.
There was no problem to allocate more than 2MB buffer. The
implementation of pci_alloc_consistent() on 2.6 differs from that on
2.4, which calls dma_alloc_coherent(). Following this, I traced down
to 'consistent_pte', which is the root cause of 2MB limitation.
Then what's your recommendation to allocate a big chunk of memory for
pci device? From this perspective, 2.6 is not compatible with 2.4,
which I think, is pretty bad.
Thanks,
-Shawn.
^ permalink raw reply
* Re: DMA consistent allocation is limited to 2MB on 2.6.11 for ppc440?
From: Eugene Surovegin @ 2005-05-19 1:24 UTC (permalink / raw)
To: Shawn Jin; +Cc: ppcembed
In-Reply-To: <c3d0340b050518175411c484e3@mail.gmail.com>
On Wed, May 18, 2005 at 05:54:39PM -0700, Shawn Jin wrote:
> The page table 'consistent_pte' covers the uncached DMA consistent
> allocation space. Its size is only one page, each page has 512 PTEs.
> That means only 2MB memory are available for DMA. For some
> applications this is not enough. So how to eliminate this limitation?
No, _all_ physical memory is available for DMA. "consistent" pool is
used for small non-cached allocations, e.g. buffer descriptors, etc.
Don't use it for actual data buffers.
--
Eugene
^ permalink raw reply
* DMA consistent allocation is limited to 2MB on 2.6.11 for ppc440?
From: Shawn Jin @ 2005-05-19 0:54 UTC (permalink / raw)
To: ppcembed
Hi,
The page table 'consistent_pte' covers the uncached DMA consistent
allocation space. Its size is only one page, each page has 512 PTEs.
That means only 2MB memory are available for DMA. For some
applications this is not enough. So how to eliminate this limitation?
I noticed that there are two configuration macros related to this
issue: CONFIG_CONSISTENT_START and CONFIG_CONSISTENT_SIZE. The current
value for CONFIG_CONSISTENT_SIZE is 2MB, which is exactly able to be
covered by one page. I guess that's why consistent_pte is initialized
to just one page. So simply changing CONFIG_CONSISTENT_SIZE cannot
remove the 2MB limitation. dma_alloc_init() has to be modified to
initialize consisten_pte to some pages which are enough to cover
CONFIG_CONSISTENT_SIZE memory space. Right?
Does increasing CONSISTENT_SIZE have any side effects?
Thanks,
-Shawn.
^ permalink raw reply
* [PATCH] ppc32: Add VIA IDE support to MPC8555 CDS platform
From: Kumar Gala @ 2005-05-18 19:57 UTC (permalink / raw)
To: Andrew Morton; +Cc: shall, linux-kernel, linuxppc-embedded
Add support for the VIA IDE controller that exists on the MPC8555 CDS system.
Updated the config for the system to enable support by default.
Signed-off-by: Scott Hall <shall@mvista.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
commit 0fb96253fc9ba2b9b348a2cc3c848334aa1643a2
tree b9da5c64c03fa695686baaa34e15cf0ca1bc48fd
parent ff96b3d4b840e8aa126e0a60fd743417ffdee178
author Kumar K. Gala <kumar.gala@freescale.com> Wed, 18 May 2005 14:55:44 -0500
committer Kumar K. Gala <kumar.gala@freescale.com> Wed, 18 May 2005 14:55:44 -0500
ppc/configs/mpc8555_cds_defconfig | 117 +++++++++++++++++++++------
ppc/platforms/85xx/mpc85xx_cds_common.c | 138 +++++++++++++++++++++++++++++++-
ppc/platforms/85xx/mpc85xx_cds_common.h | 3
ppc/syslib/Makefile | 2
ppc/syslib/ppc85xx_setup.c | 16 +++
5 files changed, 248 insertions(+), 28 deletions(-)
Index: arch/ppc/configs/mpc8555_cds_defconfig
===================================================================
--- bf16c711040aa5a00e5a6d6675869526b4dbfbb5/arch/ppc/configs/mpc8555_cds_defconfig (mode:100644)
+++ b9da5c64c03fa695686baaa34e15cf0ca1bc48fd/arch/ppc/configs/mpc8555_cds_defconfig (mode:100644)
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11-rc1
-# Thu Jan 20 01:25:35 2005
+# Linux kernel version: 2.6.12-rc4
+# Tue May 17 11:56:01 2005
#
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
@@ -11,6 +11,7 @@
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
#
# Code maturity level options
@@ -18,6 +19,7 @@
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
@@ -29,12 +31,14 @@
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
-CONFIG_LOG_BUF_SHIFT=14
# CONFIG_HOTPLUG is not set
CONFIG_KOBJECT_UEVENT=y
# CONFIG_IKCONFIG is not set
CONFIG_EMBEDDED=y
# CONFIG_KALLSYMS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
# CONFIG_EPOLL is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -44,6 +48,7 @@
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
#
# Loadable module support
@@ -62,10 +67,12 @@
CONFIG_E500=y
CONFIG_BOOKE=y
CONFIG_FSL_BOOKE=y
+# CONFIG_PHYS_64BIT is not set
CONFIG_SPE=y
CONFIG_MATH_EMULATION=y
# CONFIG_CPU_FREQ is not set
CONFIG_PPC_GEN550=y
+# CONFIG_PM is not set
CONFIG_85xx=y
CONFIG_PPC_INDIRECT_PCI_BE=y
@@ -76,6 +83,7 @@
CONFIG_MPC8555_CDS=y
# CONFIG_MPC8560_ADS is not set
# CONFIG_SBC8560 is not set
+# CONFIG_STX_GP3 is not set
CONFIG_MPC8555=y
CONFIG_85xx_PCI2=y
@@ -90,6 +98,7 @@
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_CMDLINE_BOOL is not set
+CONFIG_ISA_DMA_API=y
#
# Bus options
@@ -105,10 +114,6 @@
# CONFIG_PCCARD is not set
#
-# PC-card bridges
-#
-
-#
# Advanced setup
#
# CONFIG_ADVANCED_OPTIONS is not set
@@ -180,7 +185,59 @@
#
# ATA/ATAPI/MFM/RLL support
#
-# CONFIG_IDE is not set
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_IDEPCI=y
+CONFIG_IDEPCI_SHARE_IRQ=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+CONFIG_IDEDMA_PCI_AUTO=y
+# CONFIG_IDEDMA_ONLYDISK is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+CONFIG_BLK_DEV_VIA82CXXX=y
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+CONFIG_IDEDMA_AUTO=y
+# CONFIG_BLK_DEV_HD is not set
#
# SCSI device support
@@ -220,7 +277,6 @@
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@@ -370,14 +426,6 @@
# CONFIG_INPUT_EVBUG is not set
#
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-# CONFIG_SERIO is not set
-# CONFIG_SERIO_I8042 is not set
-
-#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
@@ -387,6 +435,13 @@
# CONFIG_INPUT_MISC is not set
#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+
+#
# Character devices
#
# CONFIG_VT is not set
@@ -406,6 +461,7 @@
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_CPM is not set
+# CONFIG_SERIAL_JSM is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
@@ -434,6 +490,11 @@
# CONFIG_RAW_DRIVER is not set
#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
# I2C support
#
CONFIG_I2C=y
@@ -456,11 +517,11 @@
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_ISA is not set
CONFIG_I2C_MPC=y
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_PROSAVAGE is not set
# CONFIG_I2C_SAVAGE4 is not set
# CONFIG_SCx200_ACB is not set
@@ -483,7 +544,9 @@
# CONFIG_SENSORS_ASB100 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM75 is not set
@@ -494,9 +557,11 @@
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_W83781D is not set
@@ -506,10 +571,12 @@
#
# Other I2C Chip support
#
+# CONFIG_SENSORS_DS1337 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_M41T00 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
@@ -538,7 +605,6 @@
# Graphics support
#
# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Sound
@@ -548,13 +614,9 @@
#
# USB support
#
-# CONFIG_USB is not set
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
-#
+# CONFIG_USB is not set
#
# USB Gadget Support
@@ -585,6 +647,10 @@
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
@@ -646,7 +712,6 @@
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
-# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -698,7 +763,9 @@
#
# Kernel hacking
#
+# CONFIG_PRINTK_TIME is not set
# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
# CONFIG_KGDB_CONSOLE is not set
# CONFIG_SERIAL_TEXT_DEBUG is not set
Index: arch/ppc/platforms/85xx/mpc85xx_cds_common.c
===================================================================
--- bf16c711040aa5a00e5a6d6675869526b4dbfbb5/arch/ppc/platforms/85xx/mpc85xx_cds_common.c (mode:100644)
+++ b9da5c64c03fa695686baaa34e15cf0ca1bc48fd/arch/ppc/platforms/85xx/mpc85xx_cds_common.c (mode:100644)
@@ -44,6 +44,7 @@
#include <asm/machdep.h>
#include <asm/prom.h>
#include <asm/open_pic.h>
+#include <asm/i8259.h>
#include <asm/bootinfo.h>
#include <asm/pci-bridge.h>
#include <asm/mpc85xx.h>
@@ -181,6 +182,7 @@
mpc85xx_cds_init_IRQ(void)
{
bd_t *binfo = (bd_t *) __res;
+ int i;
/* Determine the Physical Address of the OpenPIC regs */
phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
@@ -198,6 +200,13 @@
*/
openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
+ openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
+
+ for (i = 0; i < NUM_8259_INTERRUPTS; i++)
+ irq_desc[i].handler = &i8259_pic;
+
+ i8259_init(0);
+
#ifdef CONFIG_CPM2
/* Setup CPM2 PIC */
cpm2_init_IRQ();
@@ -231,7 +240,7 @@
* interrupt on slot */
{
{ 0, 1, 2, 3 }, /* 16 - PMC */
- { 3, 0, 0, 0 }, /* 17 P2P (Tsi320) */
+ { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
{ 0, 1, 2, 3 }, /* 18 - Slot 1 */
{ 1, 2, 3, 0 }, /* 19 - Slot 2 */
{ 2, 3, 0, 1 }, /* 20 - Slot 3 */
@@ -280,13 +289,135 @@
return PCIBIOS_DEVICE_NOT_FOUND;
#endif
/* We explicitly do not go past the Tundra 320 Bridge */
- if (bus == 1)
+ if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
return PCIBIOS_DEVICE_NOT_FOUND;
if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
return PCIBIOS_DEVICE_NOT_FOUND;
else
return PCIBIOS_SUCCESSFUL;
}
+
+void __init
+mpc85xx_cds_enable_via(struct pci_controller *hose)
+{
+ u32 pci_class;
+ u16 vid, did;
+
+ early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
+ if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
+ return;
+
+ /* Configure P2P so that we can reach bus 1 */
+ early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
+ early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
+ early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
+
+ early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
+ early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
+
+ if ((vid != PCI_VENDOR_ID_VIA) ||
+ (did != PCI_DEVICE_ID_VIA_82C686))
+ return;
+
+ /* Enable USB and IDE functions */
+ early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
+}
+
+void __init
+mpc85xx_cds_fixup_via(struct pci_controller *hose)
+{
+ u32 pci_class;
+ u16 vid, did;
+
+ early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
+ if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
+ return;
+
+ /*
+ * Force the backplane P2P bridge to have a window
+ * open from 0x00000000-0x00001fff in PCI I/O space.
+ * This allows legacy I/O (i8259, etc) on the VIA
+ * southbridge to be accessed.
+ */
+ early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
+ early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
+ early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
+ early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
+
+ early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
+ early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
+ if ((vid != PCI_VENDOR_ID_VIA) ||
+ (did != PCI_DEVICE_ID_VIA_82C686))
+ return;
+
+ /*
+ * Since the P2P window was forced to cover the fixed
+ * legacy I/O addresses, it is necessary to manually
+ * place the base addresses for the IDE and USB functions
+ * within this window.
+ */
+ /* Function 1, IDE */
+ early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
+ early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
+ early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
+ early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
+ early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
+
+ /* Function 2, USB ports 0-1 */
+ early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
+
+ /* Function 3, USB ports 2-3 */
+ early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
+
+ /* Function 5, Power Management */
+ early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
+ early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
+ early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
+
+ /* Function 6, AC97 Interface */
+ early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
+}
+
+void __init
+mpc85xx_cds_pcibios_fixup(void)
+{
+ struct pci_dev *dev = NULL;
+ u_char c;
+
+ if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
+ /*
+ * U-Boot does not set the enable bits
+ * for the IDE device. Force them on here.
+ */
+ pci_read_config_byte(dev, 0x40, &c);
+ c |= 0x03; /* IDE: Chip Enable Bits */
+ pci_write_config_byte(dev, 0x40, c);
+
+ /*
+ * Since only primary interface works, force the
+ * IDE function to standard primary IDE interrupt
+ * w/ 8259 offset
+ */
+ dev->irq = 14;
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+ }
+
+ /*
+ * Force legacy USB interrupt routing
+ */
+ if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
+ dev->irq = 10;
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
+ }
+
+ if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_82C586_2, dev))) {
+ dev->irq = 11;
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
+ }
+}
#endif /* CONFIG_PCI */
TODC_ALLOC();
@@ -307,6 +438,9 @@
freq = binfo->bi_intfreq;
printk("mpc85xx_cds_setup_arch\n");
+
+ /* VIA IDE configuration */
+ ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
#ifdef CONFIG_CPM2
cpm2_reset();
Index: arch/ppc/platforms/85xx/mpc85xx_cds_common.h
===================================================================
--- bf16c711040aa5a00e5a6d6675869526b4dbfbb5/arch/ppc/platforms/85xx/mpc85xx_cds_common.h (mode:100644)
+++ b9da5c64c03fa695686baaa34e15cf0ca1bc48fd/arch/ppc/platforms/85xx/mpc85xx_cds_common.h (mode:100644)
@@ -77,4 +77,7 @@
#define MPC85XX_PCI2_IO_SIZE 0x01000000
+#define NR_8259_INTS 16
+#define CPM_IRQ_OFFSET NR_8259_INTS
+
#endif /* __MACH_MPC85XX_CDS_H__ */
Index: arch/ppc/syslib/Makefile
===================================================================
--- bf16c711040aa5a00e5a6d6675869526b4dbfbb5/arch/ppc/syslib/Makefile (mode:100644)
+++ b9da5c64c03fa695686baaa34e15cf0ca1bc48fd/arch/ppc/syslib/Makefile (mode:100644)
@@ -97,7 +97,7 @@
obj-$(CONFIG_40x) += dcr.o
obj-$(CONFIG_BOOKE) += dcr.o
obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \
- ppc_sys.o mpc85xx_sys.o \
+ ppc_sys.o i8259.o mpc85xx_sys.o \
mpc85xx_devices.o
ifeq ($(CONFIG_85xx),y)
obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
Index: arch/ppc/syslib/ppc85xx_setup.c
===================================================================
--- bf16c711040aa5a00e5a6d6675869526b4dbfbb5/arch/ppc/syslib/ppc85xx_setup.c (mode:100644)
+++ b9da5c64c03fa695686baaa34e15cf0ca1bc48fd/arch/ppc/syslib/ppc85xx_setup.c (mode:100644)
@@ -132,6 +132,12 @@
}
#ifdef CONFIG_PCI
+
+#if defined(CONFIG_MPC8555_CDS)
+extern void mpc85xx_cds_enable_via(struct pci_controller *hose);
+extern void mpc85xx_cds_fixup_via(struct pci_controller *hose);
+#endif
+
static void __init
mpc85xx_setup_pci1(struct pci_controller *hose)
{
@@ -302,7 +308,17 @@
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
+#if defined(CONFIG_MPC8555_CDS)
+ /* Pre pciauto_bus_scan VIA init */
+ mpc85xx_cds_enable_via(hose_a);
+#endif
+
hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
+
+#if defined(CONFIG_MPC8555_CDS)
+ /* Post pciauto_bus_scan VIA fixup */
+ mpc85xx_cds_fixup_via(hose_a);
+#endif
#ifdef CONFIG_85xx_PCI2
hose_b = pcibios_alloc_controller();
^ permalink raw reply
* Re: USB-host driver for 440ep (bamboo)?
From: Sylvain Munaut @ 2005-05-18 18:31 UTC (permalink / raw)
To: Steven Blakeslee; +Cc: linuxppc-embedded
In-Reply-To: <1628E43D99629C46988BE46087A3FBB9247587@ep-01.EmbeddedPlanet.local>
> U-boot 1.1.3 has a usb_ohci.c driver for the MPC5200. That driver with just a few changes worked like a champ on the 440EP.
If it's just a big endian OHCI, ohci-ppc.c that's currently in the
mainstream tree should work, just add the proper definition in the
platform devices.
Sylvain
^ permalink raw reply
* [PATCH] ppc32: fix CONFIG_TASK_SIZE handling on 40x
From: Eugene Surovegin @ 2005-05-18 17:09 UTC (permalink / raw)
To: linuxppc-embedded
Hi!
This patch is virtually identical to my previous 44x one. It removes
0x8000'0000 TASK_SIZE hardcoded assumption from head_4xx.S.
I don't have any 40x board which runs 2.6, so this one is untested,
bit it compiles :).
Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Index: arch/ppc/kernel/head_4xx.S
===================================================================
--- 59c3218467807e1793fb4fc5d90141e072ab2212/arch/ppc/kernel/head_4xx.S (mode:100644)
+++ uncommitted/arch/ppc/kernel/head_4xx.S (mode:100644)
@@ -291,8 +291,9 @@
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
- andis. r11, r10, 0x8000
- beq 3f
+ lis r11, TASK_SIZE@h
+ cmplw r10, r11
+ blt+ 3f
lis r11, swapper_pg_dir@h
ori r11, r11, swapper_pg_dir@l
li r9, 0
@@ -479,8 +480,9 @@
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
- andis. r11, r10, 0x8000
- beq 3f
+ lis r11, TASK_SIZE@h
+ cmplw r10, r11
+ blt+ 3f
lis r11, swapper_pg_dir@h
ori r11, r11, swapper_pg_dir@l
li r9, 0
@@ -578,8 +580,9 @@
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
- andis. r11, r10, 0x8000
- beq 3f
+ lis r11, TASK_SIZE@h
+ cmplw r10, r11
+ blt+ 3f
lis r11, swapper_pg_dir@h
ori r11, r11, swapper_pg_dir@l
li r9, 0
^ permalink raw reply
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