* Re: [Edson.Seabra@cyclades.com: Re: BDI and 85xx]
From: Kumar Gala @ 2005-11-14 22:50 UTC (permalink / raw)
To: Dan Malek; +Cc: linux-ppc-embedded
In-Reply-To: <608ff4f57a546901e9193ebbbe368053@embeddededge.com>
On Nov 14, 2005, at 4:43 PM, Dan Malek wrote:
>
> On Nov 14, 2005, at 10:53 AM, Marcelo Tosatti wrote:
>
>> Doh my bad. Attached it is.
>>
>>
>> <8xx_gdb.diff>
>
> Well, this probably works for you but have you
> considered how it affects others?
>
> I'm not going to get into the -ggdb flags discussion,
> since I know we've had that in the past. Why is
> this needed and should it be done for everyone?
>
> Your update of MSR_KERNEL will work for you,
> but won't work on anything that isn't a Book E processor.
> You can't make this a generic update to all processors.
> It will fail on everything that really wants to use the
> BDI_SWITCH configuration option as it was intended.
> The DE in Book E conflicts with BE in traditional PPC.
We should but this in asm-ppc/reg_booke.h since book-e has its own
MSR_* defines.
> This also doesn't do anything to address my real concern,
> we shouldn't have to create a special kernel configuration
> just to attach a debugger .........
I'm not 100% sure this is even possible on some of the book-e variants.
- kumar
^ permalink raw reply
* Re: [Edson.Seabra@cyclades.com: Re: BDI and 85xx]
From: Dan Malek @ 2005-11-14 22:43 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: linux-ppc-embedded
In-Reply-To: <20051114155313.GA29411@logos.cnet>
On Nov 14, 2005, at 10:53 AM, Marcelo Tosatti wrote:
> Doh my bad. Attached it is.
>
>
> <8xx_gdb.diff>
Well, this probably works for you but have you
considered how it affects others?
I'm not going to get into the -ggdb flags discussion,
since I know we've had that in the past. Why is
this needed and should it be done for everyone?
Your update of MSR_KERNEL will work for you,
but won't work on anything that isn't a Book E processor.
You can't make this a generic update to all processors.
It will fail on everything that really wants to use the
BDI_SWITCH configuration option as it was intended.
The DE in Book E conflicts with BE in traditional PPC.
This also doesn't do anything to address my real concern,
we shouldn't have to create a special kernel configuration
just to attach a debugger .........
Thanks.
-- Dan
^ permalink raw reply
* Re: [PATCH] m8xx_wdt: software watchdog reset/interrupt select\
From: Kumar Gala @ 2005-11-14 21:14 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: Florian Schirmer, obi, carjay, linux-ppc-embedded
In-Reply-To: <20051114160302.GC29411@logos.cnet>
On Nov 14, 2005, at 10:03 AM, Marcelo Tosatti wrote:
> On Mon, Nov 14, 2005 at 01:57:37PM -0200, Marcelo Tosatti wrote:
>> Hi Kumar,
>>
>> On Mon, Nov 14, 2005 at 02:55:24PM -0600, Kumar Gala wrote:
>>> Can we put the WDT for 8xx in drivers/char/watchdog/?
>>
>> The userspace interface is already there at
>> drivers/char/watchdog/mpc8xx_wdt.c. I don't any reason for having two
>> files, will try to merge them into drivers/.
>
> Actually, drivers/char/watchdog/mpc8xx_wdt.c is a module, while
> some of the initialization code must reside in the kernel image.
>
> Thats the reason for the split - not sure if merging the two
> files is worth?
Fair enough.
- kumar
^ permalink raw reply
* Re: [PATCH] m8xx_wdt: software watchdog reset/interrupt select\
From: Marcelo Tosatti @ 2005-11-14 16:03 UTC (permalink / raw)
To: Kumar Gala; +Cc: Florian Schirmer, obi, carjay, linux-ppc-embedded
In-Reply-To: <20051114155736.GB29411@logos.cnet>
On Mon, Nov 14, 2005 at 01:57:37PM -0200, Marcelo Tosatti wrote:
> Hi Kumar,
>
> On Mon, Nov 14, 2005 at 02:55:24PM -0600, Kumar Gala wrote:
> > Can we put the WDT for 8xx in drivers/char/watchdog/?
>
> The userspace interface is already there at
> drivers/char/watchdog/mpc8xx_wdt.c. I don't any reason for having two
> files, will try to merge them into drivers/.
Actually, drivers/char/watchdog/mpc8xx_wdt.c is a module, while
some of the initialization code must reside in the kernel image.
Thats the reason for the split - not sure if merging the two
files is worth?
^ permalink raw reply
* Re: [PATCH] m8xx_wdt: software watchdog reset/interrupt select\
From: Marcelo Tosatti @ 2005-11-14 15:57 UTC (permalink / raw)
To: Kumar Gala; +Cc: Florian Schirmer, obi, carjay, linux-ppc-embedded
In-Reply-To: <9E7D3814-47AB-4601-A565-2530C3A4BEE0@kernel.crashing.org>
Hi Kumar,
On Mon, Nov 14, 2005 at 02:55:24PM -0600, Kumar Gala wrote:
> Can we put the WDT for 8xx in drivers/char/watchdog/?
The userspace interface is already there at
drivers/char/watchdog/mpc8xx_wdt.c. I don't any reason for having two
files, will try to merge them into drivers/.
Thanks.
^ permalink raw reply
* Re: [Edson.Seabra@cyclades.com: Re: BDI and 85xx]
From: Kumar Gala @ 2005-11-14 20:45 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: linux-ppc-embedded
In-Reply-To: <20051114152024.GA29314@logos.cnet>
It doesn't look very good since nothing appears to be attached :)
- kumar
On Nov 14, 2005, at 9:20 AM, Marcelo Tosatti wrote:
> FYI - how does it look now?
>
>
> ----- Forwarded message from Edson Seabra
> <Edson.Seabra@cyclades.com> -----
>
> From: Edson Seabra <Edson.Seabra@cyclades.com>
> Date: Mon, 14 Nov 2005 12:11:19 -0800
> To: "marcelo.tosatti" <Marcelo.Tosatti@cyclades.com>
> Subject: Re: BDI and 85xx
>
>
> Hi, Marcelo.
>
> I re-make the changes following the Dan suggestion.
>
> Can you check if he will accept them this time ?
>
> Thanks,
> -Edson.
>
>
>
>
> (See attached file: 8xx_gdb.diff)
>
> Dan Malek <dan@embeddededge.com> wrote on 11/07/2005 09:17:46 AM:
>
>>
>> On Nov 7, 2005, at 6:24 AM, Marcelo Tosatti wrote:
>>
>>> Edson had to patch this in to get BDI to work on 85xx with 2.6.14.
>>
>> How about we just change MSR_KERNEL and MSR_USER
>> in the include file #define instead of all of this run-time code?
>> Or, change the code so it preserves DE in general, so we don't
>> need a special kernel configuration just for the BDI?
>>
>> The original reason I did the BDI_SWITCH was due to the
>> overhead of tracking user PTE switches in the context switch
>> code. I don't like the way this has been overloaded to mean
>> "BDI general operation." We should be able to attach a BDI2000
>> to any kernel configuration and always get kernel debugging
>> capability. The BDI_SWITCH was to enable the extra feature
>> (with some overhead) of debugging into user applications,
>> it never should have affected any kernel debug operation.
>>
>> It's unfortunate that Book-E is such a PITA for debuggers,
>> but let's please find a better way of using these features.
>> Separate kernel configurations to enable hardware
>> debugging isn't acceptable.
>>
>> Thanks.
>>
>> -- Dan
>>
>
>
> ----- End forwarded message -----
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: 2.6.15-rc1 fails to boot on eMac
From: Benjamin Herrenschmidt @ 2005-11-14 21:03 UTC (permalink / raw)
To: Mikael Pettersson; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <17272.46529.847423.310952@alkaid.it.uu.se>
On Mon, 2005-11-14 at 17:05 +0100, Mikael Pettersson wrote:
> Linux kernel 2.6.15-rc1 (vanilla, not patched, compiled with
> gcc-3.4.4) refuses to boot on my Apple eMac (1.25GHz G4). After
> yaboot has loaded the kernel the output on the console is:
Yup, there is something wrong, I'm still investigating.
Ben.
^ permalink raw reply
* Re: [Edson.Seabra@cyclades.com: Re: BDI and 85xx]
From: Marcelo Tosatti @ 2005-11-14 15:53 UTC (permalink / raw)
To: Kumar Gala; +Cc: linux-ppc-embedded
In-Reply-To: <5F8A6977-E33A-4E84-B029-D1B49716DC82@kernel.crashing.org>
[-- Attachment #1: Type: text/plain, Size: 159 bytes --]
On Mon, Nov 14, 2005 at 02:45:46PM -0600, Kumar Gala wrote:
> It doesn't look very good since nothing appears to be attached :)
Doh my bad. Attached it is.
[-- Attachment #2: 8xx_gdb.diff --]
[-- Type: text/plain, Size: 705 bytes --]
--- /opt/montavista/pro/devkit/lsp/linux-2.6.14/Makefile 2005-10-27 17:02:08.000000000 -0700
+++ Makefile 2005-11-10 11:32:10.000000000 -0800
@@ -524,7 +524,7 @@
endif
ifdef CONFIG_DEBUG_INFO
-CFLAGS += -g
+CFLAGS += -g -ggdb
endif
include $(srctree)/arch/$(ARCH)/Makefile
--- /opt/montavista/pro/devkit/lsp/linux-2.6.14/include/asm-ppc/reg.h 2005-10-27 17:02:08.000000000 -0700
+++ include/asm-ppc/reg.h 2005-11-10 11:32:10.000000000 -0800
@@ -49,8 +49,12 @@
#endif
#ifndef MSR_KERNEL
+#ifdef CONFIG_BDI_SWITCH
+#define MSR_KERNEL (MSR_DE|MSR_ME|MSR_RI|MSR_IR|MSR_DR)
+#else
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
#endif
+#endif
#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
^ permalink raw reply
* Re: [PATCH] powerpc: Merge align.c
From: Benjamin Herrenschmidt @ 2005-11-14 20:55 UTC (permalink / raw)
To: Becky Bruce; +Cc: linuxppc64-dev, linuxppc-dev list
In-Reply-To: <daaff9f9782443f3d943c2853fb9a476@freescale.com>
On Mon, 2005-11-14 at 13:53 -0600, Becky Bruce wrote:
> Ben,
>
> I talked to Kumar about this a little bit (I had started a merge of
> this file, but got distracted!) and he doesn't have any test cases.
> I'll put something together and test this out on some of the 32-bit
> systems I have here in my lab. It won't be complete, but it will be
> something.......
Thanks,
Ben.
^ permalink raw reply
* Re: [PATCH] m8xx_wdt: software watchdog reset/interrupt select
From: Kumar Gala @ 2005-11-14 20:55 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: Florian Schirmer, obi, carjay, linux-ppc-embedded
In-Reply-To: <20051114143821.GA28852@logos.cnet>
Can we put the WDT for 8xx in drivers/char/watchdog/?
- kumar
On Nov 14, 2005, at 8:38 AM, Marcelo Tosatti wrote:
> Hi,
>
> Currently the mpc8xx_wdt driver installs an IRQ handler for
> PIT_INTERRUPT (SIU_LEVEL0, irq 1) to service the WDT until a userspace
> watchdog daemon takes over after boot.
>
> However, if the "software watchdog reset/interrupt select" (SWRI)
> bit of
> SYPCR register is set, no interrupt is generated. In that
> configuration
> (the default) HRESET signal is generated if the WDT timeout expires,
> without kernel notification.
>
> The following patch creates a kernel timer to service the WDT and
> rearm
> itself in case this configuration is detected, making it possible to
> boot the system with the watchdog turned on. The timer is shutdown
> once the userspace daemon open's the device.
>
> Note: From my reading of the documentation, even if the SWRI bit is
> unset (interrupt select mode), an NMI at IRQ0 should cause the
> system to
> jump to exception vector 0x100, resetting the system.
>
> So I'm wondering if the interrupt mode ever worked?
>
>
> --- ../git/linux-2.6/arch/ppc/syslib/m8xx_wdt.c 2005-11-08
> 11:38:39.000000000 -0600
> +++ linux-2.6-git-wednov02/arch/ppc/syslib/m8xx_wdt.c 2005-11-14
> 10:36:53.000000000 -0600
> @@ -45,35 +45,18 @@
> return IRQ_HANDLED;
> }
>
> -void __init m8xx_wdt_handler_install(bd_t * binfo)
> +#define SYPCR_SWP 0x1
> +#define SYPCR_SWRI 0x2
> +#define SYPCR_SWE 0x4
> +
> +/* software watchdog reset/interrupt select */
> +int m8xx_wdt_keepalive_mode = 0;
> +
> +void __init m8xx_wdt_install_irq(volatile immap_t *imap, bd_t *binfo)
> {
> - volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
> u32 pitc;
> - u32 sypcr;
> u32 pitrtclk;
>
> - sypcr = in_be32(&imap->im_siu_conf.sc_sypcr);
> -
> - if (!(sypcr & 0x04)) {
> - printk(KERN_NOTICE "m8xx_wdt: wdt disabled (SYPCR: 0x%08X)\n",
> - sypcr);
> - return;
> - }
> -
> - m8xx_wdt_reset();
> -
> - printk(KERN_NOTICE
> - "m8xx_wdt: active wdt found (SWTC: 0x%04X, SWP: 0x%01X)\n",
> - (sypcr >> 16), sypcr & 0x01);
> -
> - wdt_timeout = (sypcr >> 16) & 0xFFFF;
> -
> - if (!wdt_timeout)
> - wdt_timeout = 0xFFFF;
> -
> - if (sypcr & 0x01)
> - wdt_timeout *= 2048;
> -
> /*
> * Fire trigger if half of the wdt ticked down
> */
> @@ -98,6 +81,66 @@
> printk(KERN_NOTICE
> "m8xx_wdt: keep-alive trigger installed (PITC: 0x%04X)\n",
> pitc);
>
> +}
> +
> +static void m8xx_wdt_timer_func(unsigned long data);
> +
> +static struct timer_list m8xx_wdt_timer =
> + TIMER_INITIALIZER(m8xx_wdt_timer_func, 0, 0);
> +
> +void m8xx_wdt_stop_timer(void)
> +{
> + del_timer(&m8xx_wdt_timer);
> +}
> +
> +static void m8xx_wdt_timer_func(unsigned long data)
> +{
> + m8xx_wdt_reset();
> + m8xx_wdt_timer.expires = jiffies + 25;
> + add_timer(&m8xx_wdt_timer);
> +}
> +
> +void m8xx_wdt_install_timer(volatile immap_t *imap)
> +{
> + m8xx_wdt_timer.expires = jiffies + 25;
> + add_timer(&m8xx_wdt_timer);
> +}
> +
> +void __init m8xx_wdt_handler_install(bd_t * binfo)
> +{
> + volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
> + u32 sypcr;
> +
> + sypcr = in_be32(&imap->im_siu_conf.sc_sypcr);
> +
> + printk(KERN_NOTICE "m8xx_wdt SYPCR: 0x%08X)\n", sypcr);
> +
> + if (!(sypcr & SYPCR_SWE)) {
> + printk(KERN_NOTICE "m8xx_wdt: wdt disabled (SYPCR: 0x%08X)\n",
> + sypcr);
> + return;
> + }
> +
> + m8xx_wdt_reset();
> +
> + printk(KERN_NOTICE
> + "m8xx_wdt: active wdt found (SWTC: 0x%04X, SWP: 0x%01X)\n",
> + (sypcr >> 16), sypcr & SYPCR_SWP);
> +
> + wdt_timeout = (sypcr >> 16) & 0xFFFF;
> +
> + if (!wdt_timeout)
> + wdt_timeout = 0xFFFF;
> +
> + if (sypcr & SYPCR_SWP)
> + wdt_timeout *= 2048;
> +
> + m8xx_wdt_keepalive_mode = sypcr & SYPCR_SWRI;
> + if (m8xx_wdt_keepalive_mode)
> + m8xx_wdt_install_timer(imap);
> + else
> + m8xx_wdt_install_irq(imap, binfo);
> +
> wdt_timeout /= binfo->bi_intfreq;
> }
>
> --- ../git/linux-2.6/arch/ppc/syslib/m8xx_wdt.h 2005-10-10
> 18:06:12.000000000 -0500
> +++ linux-2.6-git-wednov02/arch/ppc/syslib/m8xx_wdt.h 2005-11-14
> 10:37:39.000000000 -0600
> @@ -9,8 +9,12 @@
> #ifndef _PPC_SYSLIB_M8XX_WDT_H
> #define _PPC_SYSLIB_M8XX_WDT_H
>
> +extern int m8xx_wdt_keepalive_mode;
> +
> extern void m8xx_wdt_handler_install(bd_t * binfo);
> extern int m8xx_wdt_get_timeout(void);
> extern void m8xx_wdt_reset(void);
> +extern void m8xx_wdt_install_timer(volatile immap_t *imap);
> +extern void m8xx_wdt_stop_timer(void);
>
> #endif /* _PPC_SYSLIB_M8XX_WDT_H */
> --- ../git/linux-2.6/drivers/char/watchdog/mpc8xx_wdt.c 2005-10-10
> 18:06:15.000000000 -0500
> +++ linux-2.6-git-wednov02/drivers/char/watchdog/mpc8xx_wdt.c
> 2005-11-14 10:37:15.000000000 -0600
> @@ -27,7 +27,10 @@
> {
> volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
>
> - imap->im_sit.sit_piscr &= ~(PISCR_PIE | PISCR_PTE);
> + if (m8xx_wdt_keepalive_mode)
> + m8xx_wdt_stop_timer();
> + else
> + imap->im_sit.sit_piscr &= ~(PISCR_PIE | PISCR_PTE);
>
> printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler deactivated\n");
> }
> @@ -36,7 +39,10 @@
> {
> volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
>
> - imap->im_sit.sit_piscr |= PISCR_PIE | PISCR_PTE;
> + if (m8xx_wdt_keepalive_mode)
> + m8xx_wdt_install_timer(imap);
> + else
> + imap->im_sit.sit_piscr |= PISCR_PIE | PISCR_PTE;
>
> printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler activated\n");
> }
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* [Edson.Seabra@cyclades.com: Re: BDI and 85xx]
From: Marcelo Tosatti @ 2005-11-14 15:20 UTC (permalink / raw)
To: dan, linux-ppc-embedded
FYI - how does it look now?
----- Forwarded message from Edson Seabra <Edson.Seabra@cyclades.com> -----
From: Edson Seabra <Edson.Seabra@cyclades.com>
Date: Mon, 14 Nov 2005 12:11:19 -0800
To: "marcelo.tosatti" <Marcelo.Tosatti@cyclades.com>
Subject: Re: BDI and 85xx
Hi, Marcelo.
I re-make the changes following the Dan suggestion.
Can you check if he will accept them this time ?
Thanks,
-Edson.
(See attached file: 8xx_gdb.diff)
Dan Malek <dan@embeddededge.com> wrote on 11/07/2005 09:17:46 AM:
>
> On Nov 7, 2005, at 6:24 AM, Marcelo Tosatti wrote:
>
> > Edson had to patch this in to get BDI to work on 85xx with 2.6.14.
>
> How about we just change MSR_KERNEL and MSR_USER
> in the include file #define instead of all of this run-time code?
> Or, change the code so it preserves DE in general, so we don't
> need a special kernel configuration just for the BDI?
>
> The original reason I did the BDI_SWITCH was due to the
> overhead of tracking user PTE switches in the context switch
> code. I don't like the way this has been overloaded to mean
> "BDI general operation." We should be able to attach a BDI2000
> to any kernel configuration and always get kernel debugging
> capability. The BDI_SWITCH was to enable the extra feature
> (with some overhead) of debugging into user applications,
> it never should have affected any kernel debug operation.
>
> It's unfortunate that Book-E is such a PITA for debuggers,
> but let's please find a better way of using these features.
> Separate kernel configurations to enable hardware
> debugging isn't acceptable.
>
> Thanks.
>
> -- Dan
>
----- End forwarded message -----
^ permalink raw reply
* Re: MPC8260 fcc_enet transmit timed out
From: Ricardo Scop @ 2005-11-14 19:53 UTC (permalink / raw)
To: hubert loewenguth, linuxppc-embedded
In-Reply-To: <4378CAA8.5080808@thales-bm.com>
Hi, Hubert
On Monday 14 November 2005 15:34, hubert loewenguth wrote:
> Hello to the community
>
> After having searched more than a week to correct my problem, I have
> finally decided to try to find some help :
>
> - I have a board with a MPC8260 (HIP 3 C.2), with three PHY chipset :
> LXT971A from intel
> - The MII lines MDC and MDIO are present, but I have no PHY interrupt =
line
> =3D> so I have to configure my PHY and the fcc_enet.c drivers to be in
> half-duplex mode
> - I use the 2.4.20 linux kernel
^^
You could try a newer version, maybe the problem is alr=
eady=20
gone.
HTH,
--=20
Ricardo Scop.
\|/
___ -*-
(@ @)/|\
/ V \| R SCOP Consult.
/( )\ Linux-based communications
--^^---^^+------------------------------
rscop@matrix.com.br
+55 51 999-36-777
Porto Alegre, RS - BRazil
--
P. S.: "If you don't have time to do it right, when will you have time
to do it over?" -- Penny Hines =20
^ permalink raw reply
* Re: [RFC] Attempt to clean up sigsuspend et al
From: David Woodhouse @ 2005-11-14 20:05 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <17272.5610.562107.359574@cargo.ozlabs.ibm.com>
On Mon, 2005-11-14 at 15:43 +1100, Paul Mackerras wrote:
> Ah ok, I see now, that sounds all right.
I've also changed force_successful_syscall_return() to use a TIF flag,
so we don't have to clear ti->syscall_noerror in the syscall entry path
and that can shrink too.
The syscall exit path now checks ti->flags only once in the fast path,
instead of checking it twice as it did before. All the interesting stuff
is done in the slow path.
We lose the assembly wrappers for the signal-related functions, and
clean up the syscall table to call them directly.
It looks a bit like this... I still need to test it a little harder than
"Yes, it boots", and I need to sync up the 32-bit version. Then we can
have syscall entry/exit paths that actually look similar to each other.
What do you think?
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index b757572..e3e6081 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -92,9 +92,9 @@ int main(void)
DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
- DEFINE(TI_SC_NOERR, offsetof(struct thread_info, syscall_noerror));
-#ifdef CONFIG_PPC32
+ DEFINE(TI_SIGFRAME, offsetof(struct thread_info, nvgprs_frame));
DEFINE(TI_TASK, offsetof(struct thread_info, task));
+#ifdef CONFIG_PPC32
DEFINE(TI_EXECDOMAIN, offsetof(struct thread_info, exec_domain));
DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
#endif /* CONFIG_PPC32 */
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 2d22bf0..564452b 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -113,9 +113,7 @@ system_call_common:
addi r9,r1,STACK_FRAME_OVERHEAD
#endif
clrrdi r11,r1,THREAD_SHIFT
- li r12,0
ld r10,TI_FLAGS(r11)
- stb r12,TI_SC_NOERR(r11)
andi. r11,r10,_TIF_SYSCALL_T_OR_A
bne- syscall_dotrace
syscall_dotrace_cont:
@@ -145,23 +143,11 @@ system_call: /* label this so stack tr
syscall_exit:
#ifdef SHOW_SYSCALLS
- std r3,GPR3(r1)
+ std r3,RESULT(r1)
bl .do_show_syscall_exit
- ld r3,GPR3(r1)
+ ld r3,RESULT(r1)
#endif
- std r3,RESULT(r1)
- ld r5,_CCR(r1)
- li r10,-_LAST_ERRNO
- cmpld r3,r10
clrrdi r12,r1,THREAD_SHIFT
- bge- syscall_error
-syscall_error_cont:
-
- /* check for syscall tracing or audit */
- ld r9,TI_FLAGS(r12)
- andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
- bne- syscall_exit_trace
-syscall_exit_trace_cont:
/* disable interrupts so current_thread_info()->flags can't change,
and so that we don't get interrupted after loading SRR0/1. */
@@ -173,8 +159,14 @@ syscall_exit_trace_cont:
rotldi r10,r10,16
mtmsrd r10,1
ld r9,TI_FLAGS(r12)
- andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SIGPENDING|_TIF_NEED_RESCHED)
+ li r11,-_LAST_ERRNO
+ andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_RESTOREALL|_TIF_SAVE_NVGPRS|_TIF_NOERROR)
bne- syscall_exit_work
+ std r3,RESULT(r1)
+ cmpld r3,r11
+ ld r5,_CCR(r1)
+ bge- syscall_error
+syscall_error_cont:
ld r7,_NIP(r1)
stdcx. r0,0,r1 /* to clear the reservation */
andi. r6,r8,MSR_PR
@@ -193,21 +185,13 @@ syscall_exit_trace_cont:
rfid
b . /* prevent speculative execution */
-syscall_enosys:
- li r3,-ENOSYS
- std r3,RESULT(r1)
- clrrdi r12,r1,THREAD_SHIFT
- ld r5,_CCR(r1)
-
-syscall_error:
- lbz r11,TI_SC_NOERR(r12)
- cmpwi 0,r11,0
- bne- syscall_error_cont
+syscall_error:
neg r3,r3
oris r5,r5,0x1000 /* Set SO bit in CR */
+ std r3,RESULT(r1)
std r5,_CCR(r1)
b syscall_error_cont
-
+
/* Traced system call support */
syscall_dotrace:
bl .save_nvgprs
@@ -225,21 +209,72 @@ syscall_dotrace:
ld r10,TI_FLAGS(r10)
b syscall_dotrace_cont
-syscall_exit_trace:
+syscall_enosys:
+ li r3,-ENOSYS
+ b syscall_exit
+
+syscall_exit_work:
+ /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
+ If TIF_NOERROR is set, just save r3 as it is. */
+
+ andi. r0,r9,_TIF_RESTOREALL
+ bne- 2f
+ cmpld r3,r11 /* r10 is -LAST_ERRNO */
+ blt- 1f
+ andi. r0,r9,_TIF_NOERROR
+ bne- 1f
+ ld r5,_CCR(r1)
+ neg r3,r3
+ oris r5,r5,0x1000 /* Set SO bit in CR */
+ std r5,_CCR(r1)
+1:
+ std r3,RESULT(r1)
std r3,GPR3(r1)
- bl .save_nvgprs
+
+2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
+ beq 4f
+
+ /* Clear per-syscall TIF flags if any are set, but _leave_
+ _TIF_SAVE_NVGPRS set in r9 since we haven't dealt with that
+ yet. */
+
+ li r11,_TIF_PERSYSCALL_MASK
+ addi r12,r12,TI_FLAGS
+3: ldarx r10,0,r12
+ andc r10,r10,r11
+ stdcx. r10,0,r12
+ bne- 3b
+ subi r12,r12,TI_FLAGS
+
+4: bl save_nvgprs
+ /* Anything else left to do? */
+ andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_SAVE_NVGPRS)
+ beq .ret_from_except_lite
+
+ /* Re-enable interrupts */
+ mfmsr r10
+ ori r10,r10,MSR_EE
+ mtmsrd r10,1
+
+ andi. r0,r9,_TIF_SAVE_NVGPRS
+ bne save_user_nvgprs
+
+ /* If tracing, re-enable interrupts and do it */
+save_user_nvgprs_cont:
+ andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
+ beq 5f
+
addi r3,r1,STACK_FRAME_OVERHEAD
bl .do_syscall_trace_leave
REST_NVGPRS(r1)
- ld r3,GPR3(r1)
- ld r5,_CCR(r1)
clrrdi r12,r1,THREAD_SHIFT
- b syscall_exit_trace_cont
-/* Stuff to do on exit from a system call. */
-syscall_exit_work:
- std r3,GPR3(r1)
- std r5,_CCR(r1)
+ /* Disable interrupts again and handle other work if any */
+5: mfmsr r10
+ rldicl r10,r10,48,1
+ rotldi r10,r10,16
+ mtmsrd r10,1
+
b .ret_from_except_lite
/* Save non-volatile GPRs, if not already saved. */
@@ -252,6 +288,109 @@ _GLOBAL(save_nvgprs)
std r0,_TRAP(r1)
blr
+
+save_user_nvgprs:
+ /* Re-enable interrupts before copying to user */
+ mfmsr r10
+ ori r10,r10,MSR_EE
+ mtmsrd r10,1
+
+ ld r10,TI_SIGFRAME(r9)
+ andi. r0,r9,_TIF_32BIT
+ beq- save_user_nvgprs_64
+
+ /* 32-bit save to userspace */
+101: stw r14,56(r10)
+102: stw r15,60(r10)
+103: stw r16,64(r10)
+104: stw r17,68(r10)
+105: stw r18,72(r10)
+106: stw r19,76(r10)
+107: stw r20,80(r10)
+108: stw r21,84(r10)
+109: stw r22,88(r10)
+110: stw r23,92(r10)
+111: stw r24,96(r10)
+112: stw r25,100(r10)
+113: stw r26,104(r10)
+114: stw r27,108(r10)
+115: stw r28,112(r10)
+116: stw r29,116(r10)
+117: stw r30,120(r10)
+118: stw r31,124(r10)
+ b save_user_nvgprs_cont
+
+save_user_nvgprs_64:
+ /* 64-bit save to userspace */
+119: std r14,112(r10)
+120: std r15,120(r10)
+121: std r16,128(r10)
+122: std r17,136(r10)
+123: std r18,144(r10)
+124: std r19,152(r10)
+125: std r20,160(r10)
+126: std r21,168(r10)
+127: std r22,176(r10)
+128: std r23,184(r10)
+129: std r24,192(r10)
+130: std r25,200(r10)
+131: std r26,208(r10)
+132: std r27,216(r10)
+133: std r28,224(r10)
+134: std r28,232(r10)
+135: std r28,240(r10)
+136: std r28,248(r10)
+ b save_user_nvgprs_cont
+
+ .section __ex_table,"a"
+ .align 3
+ .llong 101b,save_user_nvgprs_fault
+ .llong 102b,save_user_nvgprs_fault
+ .llong 103b,save_user_nvgprs_fault
+ .llong 104b,save_user_nvgprs_fault
+ .llong 105b,save_user_nvgprs_fault
+ .llong 106b,save_user_nvgprs_fault
+ .llong 107b,save_user_nvgprs_fault
+ .llong 108b,save_user_nvgprs_fault
+ .llong 109b,save_user_nvgprs_fault
+ .llong 110b,save_user_nvgprs_fault
+ .llong 111b,save_user_nvgprs_fault
+ .llong 112b,save_user_nvgprs_fault
+ .llong 113b,save_user_nvgprs_fault
+ .llong 114b,save_user_nvgprs_fault
+ .llong 115b,save_user_nvgprs_fault
+ .llong 116b,save_user_nvgprs_fault
+ .llong 117b,save_user_nvgprs_fault
+ .llong 118b,save_user_nvgprs_fault
+ .llong 119b,save_user_nvgprs_fault
+ .llong 120b,save_user_nvgprs_fault
+ .llong 121b,save_user_nvgprs_fault
+ .llong 122b,save_user_nvgprs_fault
+ .llong 123b,save_user_nvgprs_fault
+ .llong 124b,save_user_nvgprs_fault
+ .llong 125b,save_user_nvgprs_fault
+ .llong 126b,save_user_nvgprs_fault
+ .llong 127b,save_user_nvgprs_fault
+ .llong 128b,save_user_nvgprs_fault
+ .llong 129b,save_user_nvgprs_fault
+ .llong 130b,save_user_nvgprs_fault
+ .llong 131b,save_user_nvgprs_fault
+ .llong 132b,save_user_nvgprs_fault
+ .llong 133b,save_user_nvgprs_fault
+ .llong 134b,save_user_nvgprs_fault
+ .llong 135b,save_user_nvgprs_fault
+ .llong 136b,save_user_nvgprs_fault
+ .previous
+
+save_user_nvgprs_fault:
+ li r3,9 // SIGSEGV
+ ld r4,TI_TASK(r9)
+ bl .force_sigsegv
+
+ clrrdi r12,r1,THREAD_SHIFT
+ ld r9,TI_FLAGS(r12)
+ b save_user_nvgprs_cont
+
/*
* The sigsuspend and rt_sigsuspend system calls can call do_signal
* and thus put the process into the stopped state where we might
@@ -260,35 +399,6 @@ _GLOBAL(save_nvgprs)
* the C code. Similarly, fork, vfork and clone need the full
* register state on the stack so that it can be copied to the child.
*/
-_GLOBAL(ppc32_sigsuspend)
- bl .save_nvgprs
- bl .compat_sys_sigsuspend
- b 70f
-
-_GLOBAL(ppc64_rt_sigsuspend)
- bl .save_nvgprs
- bl .sys_rt_sigsuspend
- b 70f
-
-_GLOBAL(ppc32_rt_sigsuspend)
- bl .save_nvgprs
- bl .compat_sys_rt_sigsuspend
-70: cmpdi 0,r3,0
- /* If it returned an error, we need to return via syscall_exit to set
- the SO bit in cr0 and potentially stop for ptrace. */
- bne syscall_exit
- /* If sigsuspend() returns zero, we are going into a signal handler. We
- may need to call audit_syscall_exit() to mark the exit from sigsuspend() */
-#ifdef CONFIG_AUDITSYSCALL
- ld r3,PACACURRENT(r13)
- ld r4,AUDITCONTEXT(r3)
- cmpdi 0,r4,0
- beq .ret_from_except /* No audit_context: Leave immediately. */
- li r4, 2 /* AUDITSC_FAILURE */
- li r5,-4 /* It's always -EINTR */
- bl .audit_syscall_exit
-#endif
- b .ret_from_except
_GLOBAL(ppc_fork)
bl .save_nvgprs
@@ -305,37 +415,6 @@ _GLOBAL(ppc_clone)
bl .sys_clone
b syscall_exit
-_GLOBAL(ppc32_swapcontext)
- bl .save_nvgprs
- bl .compat_sys_swapcontext
- b 80f
-
-_GLOBAL(ppc64_swapcontext)
- bl .save_nvgprs
- bl .sys_swapcontext
- b 80f
-
-_GLOBAL(ppc32_sigreturn)
- bl .compat_sys_sigreturn
- b 80f
-
-_GLOBAL(ppc32_rt_sigreturn)
- bl .compat_sys_rt_sigreturn
- b 80f
-
-_GLOBAL(ppc64_rt_sigreturn)
- bl .sys_rt_sigreturn
-
-80: cmpdi 0,r3,0
- blt syscall_exit
- clrrdi r4,r1,THREAD_SHIFT
- ld r4,TI_FLAGS(r4)
- andi. r4,r4,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
- beq+ 81f
- addi r3,r1,STACK_FRAME_OVERHEAD
- bl .do_syscall_trace_leave
-81: b .ret_from_except
-
_GLOBAL(ret_from_fork)
bl .schedule_tail
REST_NVGPRS(r1)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 081d931..88b86ac 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -75,7 +75,6 @@
* registers from *regs. This is what we need
* to do when a signal has been delivered.
*/
-#define sigreturn_exit(regs) return 0
#define GP_REGS_SIZE min(sizeof(elf_gregset_t32), sizeof(struct pt_regs32))
#undef __SIGNAL_FRAMESIZE
@@ -155,9 +154,18 @@ static inline int save_general_regs(stru
elf_greg_t64 *gregs = (elf_greg_t64 *)regs;
int i;
- for (i = 0; i <= PT_RESULT; i ++)
+ if (!FULL_REGS(regs)) {
+ printk("Save NVGPRS at %lx\n", (unsigned long)frame->mc_gregs);
+ set_thread_flag(TIF_SAVE_NVGPRS);
+ current_thread_info()->nvgprs_frame = frame->mc_gregs;
+ }
+
+ for (i = 0; i <= PT_RESULT; i ++) {
+ if (i == 14 && !FULL_REGS(regs))
+ i = 32;
if (__put_user((unsigned int)gregs[i], &frame->mc_gregs[i]))
return -EFAULT;
+ }
return 0;
}
@@ -178,8 +186,6 @@ static inline int restore_general_regs(s
#else /* CONFIG_PPC64 */
-extern void sigreturn_exit(struct pt_regs *);
-
#define GP_REGS_SIZE min(sizeof(elf_gregset_t), sizeof(struct pt_regs))
static inline int put_sigset_t(sigset_t __user *uset, sigset_t *set)
@@ -255,8 +261,10 @@ long sys_sigsuspend(old_sigset_t mask, i
while (1) {
current->state = TASK_INTERRUPTIBLE;
schedule();
- if (do_signal(&saveset, regs))
- sigreturn_exit(regs);
+ if (do_signal(&saveset, regs)) {
+ set_thread_flag(TIF_RESTOREALL);
+ return 0;
+ }
}
}
@@ -291,8 +299,10 @@ long sys_rt_sigsuspend(
while (1) {
current->state = TASK_INTERRUPTIBLE;
schedule();
- if (do_signal(&saveset, regs))
- sigreturn_exit(regs);
+ if (do_signal(&saveset, regs)) {
+ set_thread_flag(TIF_RESTOREALL);
+ return 0;
+ }
}
}
@@ -829,12 +839,6 @@ static int handle_rt_signal(unsigned lon
regs->gpr[6] = (unsigned long) rt_sf;
regs->nip = (unsigned long) ka->sa.sa_handler;
regs->trap = 0;
-#ifdef CONFIG_PPC64
- regs->result = 0;
-
- if (test_thread_flag(TIF_SINGLESTEP))
- ptrace_notify(SIGTRAP);
-#endif
return 1;
badframe:
@@ -912,8 +916,8 @@ long sys_swapcontext(struct ucontext __u
*/
if (do_setcontext(new_ctx, regs, 0))
do_exit(SIGSEGV);
- sigreturn_exit(regs);
- /* doesn't actually return back to here */
+
+ set_thread_flag(TIF_RESTOREALL);
return 0;
}
@@ -946,12 +950,11 @@ long sys_rt_sigreturn(int r3, int r4, in
* nobody does any...
*/
compat_sys_sigaltstack((u32)(u64)&rt_sf->uc.uc_stack, 0, 0, 0, 0, 0, regs);
- return (int)regs->result;
#else
do_sigaltstack(&rt_sf->uc.uc_stack, NULL, regs->gpr[1]);
- sigreturn_exit(regs); /* doesn't return here */
- return 0;
#endif
+ set_thread_flag(TIF_RESTOREALL);
+ return 0;
bad:
force_sig(SIGSEGV, current);
@@ -1042,9 +1045,7 @@ int sys_debug_setcontext(struct ucontext
*/
do_sigaltstack(&ctx->uc_stack, NULL, regs->gpr[1]);
- sigreturn_exit(regs);
- /* doesn't actually return back to here */
-
+ set_thread_flag(TIF_RESTOREALL);
out:
return 0;
}
@@ -1109,12 +1110,6 @@ static int handle_signal(unsigned long s
regs->gpr[4] = (unsigned long) sc;
regs->nip = (unsigned long) ka->sa.sa_handler;
regs->trap = 0;
-#ifdef CONFIG_PPC64
- regs->result = 0;
-
- if (test_thread_flag(TIF_SINGLESTEP))
- ptrace_notify(SIGTRAP);
-#endif
return 1;
@@ -1162,12 +1157,8 @@ long sys_sigreturn(int r3, int r4, int r
|| restore_user_regs(regs, sr, 1))
goto badframe;
-#ifdef CONFIG_PPC64
- return (int)regs->result;
-#else
- sigreturn_exit(regs); /* doesn't return */
+ set_thread_flag(TIF_RESTOREALL);
return 0;
-#endif
badframe:
force_sig(SIGSEGV, current);
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index 58194e1..e071e95 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -96,8 +96,10 @@ long sys_rt_sigsuspend(sigset_t __user *
while (1) {
current->state = TASK_INTERRUPTIBLE;
schedule();
- if (do_signal(&saveset, regs))
+ if (do_signal(&saveset, regs)) {
+ set_thread_flag(TIF_RESTOREALL);
return 0;
+ }
}
}
@@ -155,6 +157,14 @@ static long setup_sigcontext(struct sigc
err |= __put_user(0, &sc->v_regs);
#endif /* CONFIG_ALTIVEC */
err |= __put_user(&sc->gp_regs, &sc->regs);
+ if (!FULL_REGS(regs)) {
+ /* Zero out the unsaved GPRs to avoid information
+ leak, and set TIF_SAVE_NVGPRS to ensure that the
+ registers do actually get saved later. */
+ memset(®s->gpr[14], 0, 18 * sizeof(unsigned long));
+ set_thread_flag(TIF_SAVE_NVGPRS);
+ current_thread_info()->nvgprs_frame = &sc->gp_regs;
+ }
err |= __copy_to_user(&sc->gp_regs, regs, GP_REGS_SIZE);
err |= __copy_to_user(&sc->fp_regs, ¤t->thread.fpr, FP_REGS_SIZE);
err |= __put_user(signr, &sc->signal);
@@ -343,6 +353,7 @@ int sys_swapcontext(struct ucontext __us
do_exit(SIGSEGV);
/* This returns like rt_sigreturn */
+ set_thread_flag(TIF_RESTOREALL);
return 0;
}
@@ -375,7 +386,8 @@ int sys_rt_sigreturn(unsigned long r3, u
*/
do_sigaltstack(&uc->uc_stack, NULL, regs->gpr[1]);
- return regs->result;
+ set_thread_flag(TIF_RESTOREALL);
+ return 0;
badframe:
#if DEBUG_SIG
@@ -454,9 +466,6 @@ static int setup_rt_frame(int signr, str
if (err)
goto badframe;
- if (test_thread_flag(TIF_SINGLESTEP))
- ptrace_notify(SIGTRAP);
-
return 1;
badframe:
diff --git a/arch/powerpc/kernel/systbl.S b/arch/powerpc/kernel/systbl.S
index 65eaea9..4bb3650 100644
--- a/arch/powerpc/kernel/systbl.S
+++ b/arch/powerpc/kernel/systbl.S
@@ -113,7 +113,7 @@ SYSCALL(sgetmask)
COMPAT_SYS(ssetmask)
SYSCALL(setreuid)
SYSCALL(setregid)
-SYSX(sys_ni_syscall,ppc32_sigsuspend,ppc_sigsuspend)
+SYS32ONLY(sigsuspend)
COMPAT_SYS(sigpending)
COMPAT_SYS(sethostname)
COMPAT_SYS(setrlimit)
@@ -160,7 +160,7 @@ SYSCALL(swapoff)
COMPAT_SYS(sysinfo)
COMPAT_SYS(ipc)
SYSCALL(fsync)
-SYSX(sys_ni_syscall,ppc32_sigreturn,sys_sigreturn)
+SYS32ONLY(sigreturn)
PPC_SYS(clone)
COMPAT_SYS(setdomainname)
PPC_SYS(newuname)
@@ -213,13 +213,13 @@ COMPAT_SYS(nfsservctl)
SYSCALL(setresgid)
SYSCALL(getresgid)
COMPAT_SYS(prctl)
-SYSX(ppc64_rt_sigreturn,ppc32_rt_sigreturn,sys_rt_sigreturn)
+COMPAT_SYS(rt_sigreturn)
COMPAT_SYS(rt_sigaction)
COMPAT_SYS(rt_sigprocmask)
COMPAT_SYS(rt_sigpending)
COMPAT_SYS(rt_sigtimedwait)
COMPAT_SYS(rt_sigqueueinfo)
-SYSX(ppc64_rt_sigsuspend,ppc32_rt_sigsuspend,ppc_rt_sigsuspend)
+COMPAT_SYS(rt_sigsuspend)
COMPAT_SYS(pread64)
COMPAT_SYS(pwrite64)
SYSCALL(chown)
@@ -290,7 +290,7 @@ COMPAT_SYS(clock_settime)
COMPAT_SYS(clock_gettime)
COMPAT_SYS(clock_getres)
COMPAT_SYS(clock_nanosleep)
-SYSX(ppc64_swapcontext,ppc32_swapcontext,ppc_swapcontext)
+COMPAT_SYS(swapcontext)
COMPAT_SYS(tgkill)
COMPAT_SYS(utimes)
COMPAT_SYS(statfs64)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 32f2158..2010d35 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -205,8 +205,8 @@ void _exception(int signr, struct pt_reg
if (handler == SIG_DFL) {
/* init has generated a synchronous exception
and it doesn't have a handler for the signal */
- printk(KERN_CRIT "init has generated signal %d "
- "but has no handler for it\n", signr);
+ die("init has generated signal %d "
+ "but has no handler for it\n", regs, signr);
do_exit(signr);
}
}
diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h
index 1f7ecdb..9c550b3 100644
--- a/include/asm-powerpc/ptrace.h
+++ b/include/asm-powerpc/ptrace.h
@@ -87,7 +87,7 @@ extern unsigned long profile_pc(struct p
#define force_successful_syscall_return() \
do { \
- current_thread_info()->syscall_noerror = 1; \
+ set_thread_flag(TIF_NOERROR); \
} while(0)
/*
diff --git a/include/asm-powerpc/thread_info.h b/include/asm-powerpc/thread_info.h
index e525f49..ac1e80e 100644
--- a/include/asm-powerpc/thread_info.h
+++ b/include/asm-powerpc/thread_info.h
@@ -37,8 +37,7 @@ struct thread_info {
int preempt_count; /* 0 => preemptable,
<0 => BUG */
struct restart_block restart_block;
- /* set by force_successful_syscall_return */
- unsigned char syscall_noerror;
+ void *nvgprs_frame;
/* low level flags - has atomic operations done on it */
unsigned long flags ____cacheline_aligned_in_smp;
};
@@ -123,6 +122,9 @@ static inline struct thread_info *curren
#define TIF_SINGLESTEP 9 /* singlestepping active */
#define TIF_MEMDIE 10
#define TIF_SECCOMP 11 /* secure computing */
+#define TIF_RESTOREALL 12 /* Restore all regs (implies NOERROR) */
+#define TIF_SAVE_NVGPRS 13 /* Save r14-r31 in signal frame */
+#define TIF_NOERROR 14 /* Force successful syscall return */
/* as above, but as bit values */
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -136,10 +138,14 @@ static inline struct thread_info *curren
#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
#define _TIF_SECCOMP (1<<TIF_SECCOMP)
+#define _TIF_RESTOREALL (1<<TIF_RESTOREALL)
+#define _TIF_SAVE_NVGPRS (1<<TIF_SAVE_NVGPRS)
+#define _TIF_NOERROR (1<<TIF_NOERROR)
#define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
#define _TIF_USER_WORK_MASK (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | \
- _TIF_NEED_RESCHED)
+ _TIF_NEED_RESCHED | _TIF_RESTOREALL)
+#define _TIF_PERSYSCALL_MASK (_TIF_RESTOREALL|_TIF_NOERROR|_TIF_SAVE_NVGPRS)
#endif /* __KERNEL__ */
--
dwmw2
^ permalink raw reply related
* Re: Linuv 2.6.15-rc1
From: Tom Rini @ 2005-11-14 19:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Linux Kernel Mailing List, Adrian Bunk, linuxppc-dev,
Linus Torvalds, Michael Buesch
In-Reply-To: <1131834667.7406.49.camel@gaston>
On Sun, Nov 13, 2005 at 09:31:06AM +1100, Benjamin Herrenschmidt wrote:
>
> > ucSystemType is a variable that is EXPORT_SYMBOL'ed but never used in
> > any way.
> >
> > _prep_type is a variable that is needlessly EXPORT_SYMBOL'ed.
>
> Therse are old PREP stuffs
>
> > But prep_init points to the real problem:
> >
> > CONFIG_PPC_PREP requires code from arch/ppc/platforms/, but this
> > directory is never visited.
> >
> > What is the correct fix?
> > Migrate the code from arch/ppc/platforms/ to arch/powerpc/platforms/ ?
>
> Yes, PREP need to be migrated, but that includes adding some minimum
> device-tree support for it among others. And few people still have PREP
> machines, I'm not even sure we have access to one here in ozlabs... I
> think for 2.6.15, we'd better just disable it in .config for
> ARCH=powerpc.
I think we really should just drop _prep_type from being exported. the
uc* stuff doesn't look to be used, but we can clean that up as its
converted to arch/powerpc. But I don't think anything out of tree uses
_prep_type (it's used at a very low level, it really couldn't be used at
the modular level).
As an occasional PReP monkey,
Acked-by: Tom Rini <trini@kernel.crashing.org>
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply
* Re: [PATCH] powerpc: Merge align.c
From: Becky Bruce @ 2005-11-14 19:53 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc64-dev, linuxppc-dev list
In-Reply-To: <1131955237.5504.148.camel@gaston>
Ben,
I talked to Kumar about this a little bit (I had started a merge of=20
this file, but got distracted!) and he doesn't have any test cases. =20
I'll put something together and test this out on some of the 32-bit=20
systems I have here in my lab. It won't be complete, but it will be=20
something.......
Cheers,
B
On Nov 14, 2005, at 2:00 AM, Benjamin Herrenschmidt wrote:
> Need testing !!!
>
> This patch merges align.c, the result isn't quite what was in ppc64 =
nor
> what was in ppc32 :) It should implement all the functionalities of=20
> both
> though. Kumar, since you played with that in the past, I suppose you
> have some test cases for verifying that it works properly before I dig
> out the 601 machine ? :)
>
> Since it's likely that I won't be able to test all scenario, code
> inspection is much welcome.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
>
> Index: linux-work/arch/powerpc/kernel/Makefile
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> --- linux-work.orig/arch/powerpc/kernel/Makefile=A0=A0=A0=A0=A0=A0=A0 =
2005-11-14=20
> 15:17:57.000000000 +1100
> +++ linux-work/arch/powerpc/kernel/Makefile=A0=A0=A0=A0 2005-11-14=20
> 17:18:14.000000000 +1100
> @@ -12,7 +12,7 @@
> =A0endif
> =A0
> =A0obj-y=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=
=A0 :=3D semaphore.o cputable.o ptrace.o=20
> syscalls.o \
> -=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 =A0=A0 irq.o signal_32.o pmc.o vdso.o
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 =A0=A0 irq.o align.o signal_32.o pmc.o=20
> vdso.o
> =A0obj-y=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=
=A0 +=3D vdso32/
> =A0obj-$(CONFIG_PPC64)=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 +=3D setup_64.o =
binfmt_elf32.o=20
> sys_ppc32.o \
> =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 =A0=A0 signal_64.o ptrace32.o systbl.o \
> Index: linux-work/arch/powerpc/kernel/align.c
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> --- /dev/null=A0=A0 1970-01-01 00:00:00.000000000 +0000
> +++ linux-work/arch/powerpc/kernel/align.c=A0=A0=A0=A0=A0 2005-11-14=20=
> 18:41:22.000000000 +1100
> @@ -0,0 +1,513 @@
> +/* align.c - handle alignment exceptions for the Power PC.
> + *
> + * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
> + * Copyright (c) 1998-1999 TiVo, Inc.
> + *=A0=A0 PowerPC 403GCX modifications.
> + * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
> + *=A0=A0 PowerPC 403GCX/405GP modifications.
> + * Copyright (c) 2001-2002 PPC64 team, IBM Corp
> + *=A0=A0 64-bit and Power4 support
> + * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
> + *=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
<benh@kernel.crashing.org>
> + *=A0=A0 Merge ppc32 and ppc64 implementations
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/mm.h>
> +#include <asm/processor.h>
> +#include <asm/uaccess.h>
> +#include <asm/system.h>
> +#include <asm/cache.h>
> +#include <asm/cputable.h>
> +
> +struct aligninfo {
> +=A0=A0=A0=A0=A0=A0 unsigned char len;
> +=A0=A0=A0=A0=A0=A0 unsigned char flags;
> +};
> +
> +#define IS_XFORM(inst) (((inst) >> 26) =3D=3D 31)
> +#define IS_DSFORM(inst)=A0=A0=A0=A0=A0=A0=A0 (((inst) >> 26) >=3D 56)
> +
> +#define INVALID=A0=A0=A0=A0=A0=A0=A0 { 0, 0 }
> +
> +#define LD=A0=A0=A0=A0 1=A0=A0=A0=A0=A0=A0 /* load */
> +#define ST=A0=A0=A0=A0 2=A0=A0=A0=A0=A0=A0 /* store */
> +#define=A0=A0=A0=A0=A0=A0=A0 SE=A0=A0=A0=A0=A0 4=A0=A0=A0=A0=A0=A0 /* =
sign-extend value */
> +#define F=A0=A0=A0=A0=A0 8=A0=A0=A0=A0=A0=A0 /* to/from fp regs */
> +#define U=A0=A0=A0=A0=A0 0x10=A0=A0=A0 /* update index register */
> +#define M=A0=A0=A0=A0=A0 0x20=A0=A0=A0 /* multiple load/store */
> +#define SW=A0=A0=A0=A0 0x40=A0=A0=A0 /* byte swap int or ... */
> +#define S=A0=A0=A0=A0=A0 0x40=A0=A0=A0 /* ... single-precision fp */
> +#define SX=A0=A0=A0=A0 0x40=A0=A0=A0 /* byte count in XER */
> +#define HARD=A0=A0 0x80=A0=A0=A0 /* string, stwcx. */
> +
> +#define DCBZ=A0=A0 0x5f=A0=A0=A0 /* 8xx/82xx dcbz faults when cache =
not enabled=20
> */
> +
> +#define SWAP(a, b)=A0=A0=A0=A0 (t =3D (a), (a) =3D (b), (b) =3D t)
> +
> +/*
> + * The PowerPC stores certain bits of the instruction that caused the
> + * alignment exception in the DSISR register.=A0 This array maps =
those
> + * bits to information about the operand length and what the
> + * instruction would do.
> + */
> +static struct aligninfo aligninfo[128] =3D {
> +=A0=A0=A0=A0=A0=A0 { 4, LD },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
00 0 0000: lwz / lwarx */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 00 0 0001 */
> +=A0=A0=A0=A0=A0=A0 { 4, ST },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
00 0 0010: stw */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 00 0 0011 */
> +=A0=A0=A0=A0=A0=A0 { 2, LD },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
00 0 0100: lhz */
> +=A0=A0=A0=A0=A0=A0 { 2, LD+SE },=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 0 =
0101: lha */
> +=A0=A0=A0=A0=A0=A0 { 2, ST },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
00 0 0110: sth */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+M },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 =
0 0111: lmw */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+F+S },=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 0 =
1000: lfs */
> +=A0=A0=A0=A0=A0=A0 { 8, LD+F },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 =
0 1001: lfd */
> +=A0=A0=A0=A0=A0=A0 { 4, ST+F+S },=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 0 =
1010: stfs */
> +=A0=A0=A0=A0=A0=A0 { 8, ST+F },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 =
0 1011: stfd */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 00 0 1100 */
> +=A0=A0=A0=A0=A0=A0 { 8, LD },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
00 0 1101: ld/ldu/lwa */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 00 0 1110 */
> +=A0=A0=A0=A0=A0=A0 { 8, ST },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
00 0 1111: std/stdu */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 =
1 0000: lwzu */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 00 1 0001 */
> +=A0=A0=A0=A0=A0=A0 { 4, ST+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 =
1 0010: stwu */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 00 1 0011 */
> +=A0=A0=A0=A0=A0=A0 { 2, LD+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 =
1 0100: lhzu */
> +=A0=A0=A0=A0=A0=A0 { 2, LD+SE+U }, =A0=A0=A0=A0=A0=A0=A0 /* 00 1 =
0101: lhau */
> +=A0=A0=A0=A0=A0=A0 { 2, ST+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 =
1 0110: sthu */
> +=A0=A0=A0=A0=A0=A0 { 4, ST+M },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 =
1 0111: stmw */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+F+S+U },=A0=A0=A0=A0=A0=A0=A0 /* 00 1 =
1000: lfsu */
> +=A0=A0=A0=A0=A0=A0 { 8, LD+F+U },=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 1 =
1001: lfdu */
> +=A0=A0=A0=A0=A0=A0 { 4, ST+F+S+U },=A0=A0=A0=A0=A0=A0=A0 /* 00 1 =
1010: stfsu */
> +=A0=A0=A0=A0=A0=A0 { 8, ST+F+U },=A0 =A0=A0=A0=A0=A0=A0=A0 /* 00 1 =
1011: stfdu */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 00 1 1100 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 00 1 1101 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 00 1 1110 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 00 1 1111 */
> +=A0=A0=A0=A0=A0=A0 { 8, LD },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
01 0 0000: ldx */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 0 0001 */
> +=A0=A0=A0=A0=A0=A0 { 8, ST },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
01 0 0010: stdx */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 0 0011 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 0 0100 */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+SE },=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 01 0 =
0101: lwax */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 0 0110 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 0 0111 */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+M+HARD+SX },=A0=A0=A0 /* 01 0 1000: lswx =
*/
> +=A0=A0=A0=A0=A0=A0 { 4, LD+M+HARD },=A0=A0=A0=A0=A0=A0 /* 01 0 1001: =
lswi */
> +=A0=A0=A0=A0=A0=A0 { 4, ST+M+HARD+SX },=A0=A0=A0 /* 01 0 1010: stswx =
*/
> +=A0=A0=A0=A0=A0=A0 { 4, ST+M+HARD },=A0=A0=A0=A0=A0=A0 /* 01 0 1011: =
stswi */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 0 1100 */
> +=A0=A0=A0=A0=A0=A0 { 8, LD+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 01 =
0 1101: ldu */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 0 1110 */
> +=A0=A0=A0=A0=A0=A0 { 8, ST+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 01 =
0 1111: stdu */
> +=A0=A0=A0=A0=A0=A0 { 8, LD+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 01 =
1 0000: ldux */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 0001 */
> +=A0=A0=A0=A0=A0=A0 { 8, ST+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 01 =
1 0010: stdux */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 0011 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 0100 */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+SE+U }, =A0=A0=A0=A0=A0=A0=A0 /* 01 1 =
0101: lwaux */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 0110 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 0111 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 1000 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 1001 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 1010 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 1011 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 1100 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 1101 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 1110 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 01 1 1111 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 0 0000 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 0 0001 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 0 0010: stwcx. */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 0 0011 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 0 0100 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 0 0101 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 0 0110 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 0 0111 */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+SW },=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 10 0 =
1000: lwbrx */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 0 1001 */
> +=A0=A0=A0=A0=A0=A0 { 4, ST+SW },=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 10 0 =
1010: stwbrx */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 0 1011 */
> +=A0=A0=A0=A0=A0=A0 { 2, LD+SW },=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 10 0 =
1100: lhbrx */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+SE },=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 10 0 =
1101=A0 lwa */
> +=A0=A0=A0=A0=A0=A0 { 2, ST+SW },=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 10 0 =
1110: sthbrx */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 0 1111 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 0000 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 0001 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 0010 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 0011 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 0100 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 0101 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 0110 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 0111 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 1000 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 1001 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 1010 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 1011 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 1100 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 1101 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 10 1 1110 */
> +=A0=A0=A0=A0=A0=A0 { 0, ST+HARD }, =A0=A0=A0=A0=A0=A0=A0 /* 10 1 =
1111: dcbz */
> +=A0=A0=A0=A0=A0=A0 { 4, LD },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
11 0 0000: lwzx */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 0 0001 */
> +=A0=A0=A0=A0=A0=A0 { 4, ST },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
11 0 0010: stwx */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 0 0011 */
> +=A0=A0=A0=A0=A0=A0 { 2, LD },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
11 0 0100: lhzx */
> +=A0=A0=A0=A0=A0=A0 { 2, LD+SE },=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 0 =
0101: lhax */
> +=A0=A0=A0=A0=A0=A0 { 2, ST },=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* =
11 0 0110: sthx */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 0 0111 */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+F+S },=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 0 =
1000: lfsx */
> +=A0=A0=A0=A0=A0=A0 { 8, LD+F },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 =
0 1001: lfdx */
> +=A0=A0=A0=A0=A0=A0 { 4, ST+F+S },=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 0 =
1010: stfsx */
> +=A0=A0=A0=A0=A0=A0 { 8, ST+F },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 =
0 1011: stfdx */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 0 1100 */
> +=A0=A0=A0=A0=A0=A0 { 8, LD+M },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 =
0 1101: lmd */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 0 1110 */
> +=A0=A0=A0=A0=A0=A0 { 8, ST+M },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 =
0 1111: stmd */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 =
1 0000: lwzux */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 1 0001 */
> +=A0=A0=A0=A0=A0=A0 { 4, ST+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 =
1 0010: stwux */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 1 0011 */
> +=A0=A0=A0=A0=A0=A0 { 2, LD+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 =
1 0100: lhzux */
> +=A0=A0=A0=A0=A0=A0 { 2, LD+SE+U }, =A0=A0=A0=A0=A0=A0=A0 /* 11 1 =
0101: lhaux */
> +=A0=A0=A0=A0=A0=A0 { 2, ST+U },=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 =
1 0110: sthux */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 1 0111 */
> +=A0=A0=A0=A0=A0=A0 { 4, LD+F+S+U },=A0=A0=A0=A0=A0=A0=A0 /* 11 1 =
1000: lfsux */
> +=A0=A0=A0=A0=A0=A0 { 8, LD+F+U },=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 1 =
1001: lfdux */
> +=A0=A0=A0=A0=A0=A0 { 4, ST+F+S+U },=A0=A0=A0=A0=A0=A0=A0 /* 11 1 =
1010: stfsux */
> +=A0=A0=A0=A0=A0=A0 { 8, ST+F+U },=A0 =A0=A0=A0=A0=A0=A0=A0 /* 11 1 =
1011: stfdux */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 1 1100 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 1 1101 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 1 1110 */
> +=A0=A0=A0=A0=A0=A0 INVALID,=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
/* 11 1 1111 */
> +};
> +
> +/*
> + * Create a DSISR value from the instruction
> + */
> +static inline unsigned make_dsisr(unsigned instr)
> +{
> +=A0=A0=A0=A0=A0=A0 unsigned dsisr;
> +
> +
> +=A0=A0=A0=A0=A0=A0 /* bits=A0 6:15 --> 22:31 */
> +=A0=A0=A0=A0=A0=A0 dsisr =3D (instr & 0x03ff0000) >> 16;
> +
> +=A0=A0=A0=A0=A0=A0 if ( IS_XFORM(instr) ) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* bits 29:30 --> 15:16 */
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 dsisr |=3D (instr & =
0x00000006) << 14;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* bit=A0=A0=A0=A0 25 -->=A0=A0=
=A0 17 */
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 dsisr |=3D (instr & =
0x00000040) << 8;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* bits 21:24 --> 18:21 */
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 dsisr |=3D (instr & =
0x00000780) << 3;
> +=A0=A0=A0=A0=A0=A0 }
> +=A0=A0=A0=A0=A0=A0 else {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* bit=A0=A0=A0=A0=A0 5 =
-->=A0=A0=A0 17 */
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 dsisr |=3D (instr & =
0x04000000) >> 12;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* bits=A0 1: 4 --> 18:21 */
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 dsisr |=3D (instr & =
0x78000000) >> 17;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* bits 30:31 --> 12:13 */
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if ( IS_DSFORM(instr) )
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 dsisr =
|=3D (instr & 0x00000003) << 18;
> +=A0=A0=A0=A0=A0=A0 }
> +
> +=A0=A0=A0=A0=A0=A0 return dsisr;
> +}
> +
> +/*
> + * The dcbz (data cache block zero) instruction
> + * gives an alignment fault if used on non-cacheable
> + * memory.=A0 We handle the fault mainly for the
> + * case when we are running with the cache disabled
> + * for debugging.
> + */
> +static int emulate_dcbz(struct pt_regs *regs, unsigned char __user=20
> *addr)
> +{
> +=A0=A0=A0=A0=A0=A0 long __user *p;
> +=A0=A0=A0=A0=A0=A0 int i, size;
> +
> +#ifdef __powerpc64__
> +=A0=A0=A0=A0=A0=A0 size =3D ppc64_caches.dline_size;
> +#else
> +=A0=A0=A0=A0=A0=A0 size =3D L1_CACHE_BYTES;
> +#endif
> +=A0=A0=A0=A0=A0=A0 p =3D (long __user *) (regs->dar & -size);
> +=A0=A0=A0=A0=A0=A0 if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, =
size))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return -EFAULT;
> +=A0=A0=A0=A0=A0=A0 for (i =3D 0; i < size / sizeof(long); ++i)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if (__put_user(0, p+i))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return =
-EFAULT;
> +=A0=A0=A0=A0=A0=A0 return 1;
> +}
> +
> +/*
> + * Emulate load & store multiple instructions
> + */
> +static int emulate_multiple(struct pt_regs *regs, unsigned char=20
> __user *addr,
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=
unsigned int reg, unsigned int nb,
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=
unsigned int flags, unsigned int instr)
> +{
> +=A0=A0=A0=A0=A0=A0 unsigned char *rptr;
> +=A0=A0=A0=A0=A0=A0 int nb0, i;
> +
> +=A0=A0=A0=A0=A0=A0 /*
> +=A0=A0=A0=A0=A0=A0=A0 * We do not try to emulate 8 bytes multiple as =
they aren't=20
> really
> +=A0=A0=A0=A0=A0=A0=A0 * available in our operating environments and =
we don't try to
> +=A0=A0=A0=A0=A0=A0=A0 * emulate multiples operations in kernel land =
as they should=20
> never
> +=A0=A0=A0=A0=A0=A0=A0 * be used/generated there at least not on =
unaligned boundaries
> +=A0=A0=A0=A0=A0=A0=A0 */
> +=A0=A0=A0=A0=A0=A0 if (unlikely((nb > 4) || !user_mode(regs)))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return 0;
> +
> +=A0=A0=A0=A0=A0=A0 /* lmw, stmw, lswi/x, stswi/x */
> +=A0=A0=A0=A0=A0=A0 nb0 =3D 0;
> +=A0=A0=A0=A0=A0=A0 if (flags & HARD) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if (flags & SX) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 nb =3D =
regs->xer & 127;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if (nb =
=3D=3D 0)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 return 1;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 } else {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if =
(__get_user(instr,
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0 (unsigned int __user=20
> *)regs->nip))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 return -EFAULT;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 nb =3D =
(instr >> 11) & 0x1f;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if (nb =
=3D=3D 0)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 nb =3D 32;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 }
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if (nb + reg * 4 > 128) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 nb0 =3D =
nb + reg * 4 - 128;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 nb =3D =
128 - reg * 4;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 }
> +=A0=A0=A0=A0=A0=A0 } else {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* lwm, stmw */
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 nb =3D (32 - reg) * 4;
> +=A0=A0=A0=A0=A0=A0 }
> +
> +=A0=A0=A0=A0=A0=A0 if (!access_ok((flags & ST ? VERIFY_WRITE: =
VERIFY_READ), addr,=20
> nb+nb0))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return -EFAULT; /* bad =
address */
> +
> +=A0=A0=A0=A0=A0=A0 rptr =3D (unsigned char *) ®s->gpr[reg];
> +=A0=A0=A0=A0=A0=A0 if (flags & LD) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 for (i =3D 0; i < nb; ++i)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if =
(__get_user(rptr[i], addr + i))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 return -EFAULT;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if (nb0 > 0) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 rptr =3D=
(unsigned char *) ®s->gpr[0];
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 addr =
+=3D nb;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 for (i =
=3D 0; i < nb0; ++i)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 if (__get_user(rptr[i], addr + i))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return -EFAULT;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 }
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 for (; (i & 3) !=3D 0; ++i)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
rptr[i] =3D 0;
> +=A0=A0=A0=A0=A0=A0 } else {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 for (i =3D 0; i < nb; ++i)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if =
(__put_user(rptr[i], addr + i))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 return -EFAULT;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if (nb0 > 0) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 rptr =3D=
(unsigned char *) ®s->gpr[0];
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 addr =
+=3D nb;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 for (i =
=3D 0; i < nb0; ++i)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 if (__put_user(rptr[i], addr + i))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return -EFAULT;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 }
> +=A0=A0=A0=A0=A0=A0 }
> +=A0=A0=A0=A0=A0=A0 return 1;
> +}
> +
> +
> +/*
> + * Called on alignment exception. Attempts to fixup
> + *
> + * Return 1 on success
> + * Return 0 if unable to handle the interrupt
> + * Return -EFAULT if data address is bad
> + */
> +
> +int fix_alignment(struct pt_regs *regs)
> +{
> +=A0=A0=A0=A0=A0=A0 unsigned int instr, nb, flags;
> +=A0=A0=A0=A0=A0=A0 unsigned int reg, areg;
> +=A0=A0=A0=A0=A0=A0 unsigned int dsisr;
> +=A0=A0=A0=A0=A0=A0 unsigned char __user *addr;
> +=A0=A0=A0=A0=A0=A0 unsigned char __user *p;
> +=A0=A0=A0=A0=A0=A0 int ret, t;
> +=A0=A0=A0=A0=A0=A0 union {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 long ll;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 double dd;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 unsigned char v[8];
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 struct {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
unsigned hi32;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
int=A0=A0=A0=A0=A0 low32;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 } x32;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 struct {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
unsigned char hi48[6];
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
short=A0=A0 =A0=A0=A0=A0=A0 low16;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 } x16;
> +=A0=A0=A0=A0=A0=A0 } data;
> +
> +=A0=A0=A0=A0=A0=A0 /*
> +=A0=A0=A0=A0=A0=A0=A0 * We require a complete register set, if not, =
then our=20
> assembly
> +=A0=A0=A0=A0=A0=A0=A0 * is broken
> +=A0=A0=A0=A0=A0=A0=A0 */
> +=A0=A0=A0=A0=A0=A0 CHECK_FULL_REGS(regs);
> +
> +=A0=A0=A0=A0=A0=A0 dsisr =3D regs->dsisr;
> +
> +=A0=A0=A0=A0=A0=A0 /* Some processors don't provide us with a DSISR =
we can use=20
> here,
> +=A0=A0=A0=A0=A0=A0=A0 * let's make one up from the instruction
> +=A0=A0=A0=A0=A0=A0=A0 */
> +=A0=A0=A0=A0=A0=A0 if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 unsigned int real_instr;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if =
(unlikely(__get_user(real_instr,
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 (unsigned int __user=20
> *)regs->nip)))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return =
-EFAULT;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 dsisr =3D =
make_dsisr(real_instr);
> +=A0=A0=A0=A0=A0=A0 }
> +
> +=A0=A0=A0=A0=A0=A0 /* extract the operation and registers from the =
dsisr */
> +=A0=A0=A0=A0=A0=A0 reg =3D (dsisr >> 5) & 0x1f;=A0=A0=A0=A0=A0 /* =
source/dest register */
> +=A0=A0=A0=A0=A0=A0 areg =3D dsisr & 0x1f;=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0=
/* register to update */
> +=A0=A0=A0=A0=A0=A0 instr =3D (dsisr >> 10) & 0x7f;
> +=A0=A0=A0=A0=A0=A0 instr |=3D (dsisr >> 13) & 0x60;
> +
> +=A0=A0=A0=A0=A0=A0 /* Lookup the operation in our table */
> +=A0=A0=A0=A0=A0=A0 nb =3D aligninfo[instr].len;
> +=A0=A0=A0=A0=A0=A0 flags =3D aligninfo[instr].flags;
> +
> +=A0=A0=A0=A0=A0=A0 /* DAR has the operand effective address */
> +=A0=A0=A0=A0=A0=A0 addr =3D (unsigned char __user *)regs->dar;
> +
> +=A0=A0=A0=A0=A0=A0 /* A size of 0 indicates an instruction we don't =
support, with
> +=A0=A0=A0=A0=A0=A0=A0 * the exception of DCBZ which is handled as a =
special case=20
> here
> +=A0=A0=A0=A0=A0=A0=A0 */
> +=A0=A0=A0=A0=A0=A0 if (instr =3D=3D DCBZ)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return emulate_dcbz(regs, =
addr);
> +=A0=A0=A0=A0=A0=A0 if (unlikely(nb =3D=3D 0))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return 0;
> +
> +=A0=A0=A0=A0=A0=A0 /* Load/Store Multiple instructions are handled in =
their own
> +=A0=A0=A0=A0=A0=A0=A0 * function
> +=A0=A0=A0=A0=A0=A0=A0 */
> +=A0=A0=A0=A0=A0=A0 if (flags & M)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return =
emulate_multiple(regs, addr, reg, nb, flags,=20
> instr);
> +
> +=A0=A0=A0=A0=A0=A0 /* Verify the address of the operand */
> +=A0=A0=A0=A0=A0=A0 if (unlikely(user_mode(regs) &&
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0 =
!access_ok((flags & ST ? VERIFY_WRITE :=20
> VERIFY_READ),
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 addr, nb)))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return -EFAULT;
> +
> +=A0=A0=A0=A0=A0=A0 /* Force the fprs into the save area so we can =
reference them=20
> */
> +=A0=A0=A0=A0=A0=A0 if (flags & F) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 /* userland only */
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if =
(unlikely(!user_mode(regs)))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return =
0;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 flush_fp_to_thread(current);
> +=A0=A0=A0=A0=A0=A0 }
> +
> +=A0=A0=A0=A0=A0=A0 /* If we are loading, get the data from user =
space, else
> +=A0=A0=A0=A0=A0=A0=A0 * get it from register values
> +=A0=A0=A0=A0=A0=A0=A0 */
> +=A0=A0=A0=A0=A0=A0 if (flags & LD) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 data.ll =3D 0;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret =3D 0;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 p =3D addr;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 switch (nb) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 case 8:
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__get_user(data.v[0], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__get_user(data.v[1], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__get_user(data.v[2], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__get_user(data.v[3], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 case 4:
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__get_user(data.v[4], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__get_user(data.v[5], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 case 2:
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__get_user(data.v[6], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__get_user(data.v[7], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if =
(unlikely(ret))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 return -EFAULT;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 }
> +=A0=A0=A0=A0=A0=A0 } else if (flags & F)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 data.dd =3D =
current->thread.fpr[reg];
> +=A0=A0=A0=A0=A0=A0 else
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 data.ll =3D regs->gpr[reg];
> +
> +=A0=A0=A0=A0=A0=A0 /* Perform other misc operations like sign =
extension, byteswap,
> +=A0=A0=A0=A0=A0=A0=A0 * or floating point single precision conversion
> +=A0=A0=A0=A0=A0=A0=A0 */
> +=A0=A0=A0=A0=A0=A0 switch (flags & ~U) {
> +=A0=A0=A0=A0=A0=A0 case LD+SE:=A0=A0=A0=A0 /* sign extend */
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if ( nb =3D=3D 2 )
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
data.ll =3D data.x16.low16;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 else=A0=A0=A0 /* nb must be =
4 */
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
data.ll =3D data.x32.low32;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 break;
> +=A0=A0=A0=A0=A0=A0 case LD+S:=A0=A0=A0=A0=A0 /* byte-swap */
> +=A0=A0=A0=A0=A0=A0 case ST+S:
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if (nb =3D=3D 2) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
SWAP(data.v[6], data.v[7]);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 } else {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
SWAP(data.v[4], data.v[7]);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
SWAP(data.v[5], data.v[6]);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 }
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 break;
> +
> +=A0=A0=A0=A0=A0=A0 /* Single-precision FP load and store require =
conversions... */
> +=A0=A0=A0=A0=A0=A0 case LD+F+S:
> +#ifdef CONFIG_PPC_FPU
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 preempt_disable();
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 enable_kernel_fp();
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 cvt_fd((float *)&data.v[4], =
&data.dd,=20
> ¤t->thread);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 preempt_enable();
> +#else
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return 0;
> +#endif
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 break;
> +=A0=A0=A0=A0=A0=A0 case ST+F+S:
> +#ifdef CONFIG_PPC_FPU
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 preempt_disable();
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 enable_kernel_fp();
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 cvt_df(&data.dd, (float =
*)&data.v[4],=20
> ¤t->thread);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 preempt_enable();
> +#else
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return 0;
> +#endif
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 break;
> +=A0=A0=A0=A0=A0=A0 }
> +
> +=A0=A0=A0=A0=A0=A0 /* Store result to memory or update registers */
> +=A0=A0=A0=A0=A0=A0 if (flags & ST) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret =3D 0;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 p =3D addr;
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 switch (nb) {
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 case 8:
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__put_user(data.v[0], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__put_user(data.v[1], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__put_user(data.v[2], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__put_user(data.v[3], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 case 4:
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__put_user(data.v[4], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__put_user(data.v[5], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 case 2:
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__put_user(data.v[6], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ret |=3D=
__put_user(data.v[7], p++);
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 }
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 if (unlikely(ret))
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 return =
-EFAULT;
> +=A0=A0=A0=A0=A0=A0 } else if (flags & F)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 current->thread.fpr[reg] =3D =
data.dd;
> +=A0=A0=A0=A0=A0=A0 else
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 regs->gpr[reg] =3D data.ll;
> +
> +=A0=A0=A0=A0=A0=A0 /* Update RA as needed */
> +=A0=A0=A0=A0=A0=A0 if (flags & U)
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 regs->gpr[areg] =3D =
regs->dar;
> +
> +=A0=A0=A0=A0=A0=A0 return 1;
> +}
> Index: linux-work/arch/ppc/kernel/Makefile
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> --- linux-work.orig/arch/ppc/kernel/Makefile=A0=A0=A0 2005-11-11=20
> 10:14:48.000000000 +1100
> +++ linux-work/arch/ppc/kernel/Makefile 2005-11-14 18:42:30.000000000=20=
> +1100
> @@ -13,7 +13,7 @@
> =A0extra-y=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=
=A0 =A0=A0=A0=A0=A0=A0=A0 +=3D vmlinux.lds
> =A0
> =A0obj-y=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=
=A0 :=3D entry.o traps.o idle.o time.o=20
> misc.o \
> -=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 process.o align.o \
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 process.o \
> =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 setup.o \
> =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 ppc_htab.o
> =A0obj-$(CONFIG_6xx)=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 +=3D l2cr.o =
cpu_setup_6xx.o
> Index: linux-work/arch/ppc64/kernel/Makefile
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> --- linux-work.orig/arch/ppc64/kernel/Makefile=A0 2005-11-14=20
> 15:20:05.000000000 +1100
> +++ linux-work/arch/ppc64/kernel/Makefile=A0=A0=A0=A0=A0=A0 2005-11-14=20=
> 18:42:12.000000000 +1100
> @@ -11,9 +11,7 @@
> =A0
> =A0endif
> =A0
> -obj-y=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 +=3D idle.o dma.o \
> -=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
align.o \
> -=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
iommu.o
> +obj-y=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 +=3D idle.o dma.o =
iommu.o
> =A0
> =A0pci-obj-$(CONFIG_PPC_MULTIPLATFORM)=A0=A0=A0 +=3D pci_dn.o =
pci_direct_iommu.o
> =A0
> Index: linux-work/include/asm-powerpc/cputable.h
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> --- linux-work.orig/include/asm-powerpc/cputable.h=A0=A0=A0=A0=A0 =
2005-11-11=20
> 10:14:49.000000000 +1100
> +++ linux-work/include/asm-powerpc/cputable.h=A0=A0 2005-11-14=20
> 18:33:42.000000000 +1100
> @@ -90,6 +90,7 @@
> =A0#define CPU_FTR_NEED_COHERENT=A0 =A0=A0=A0=A0=A0=A0=A0 =
ASM_CONST(0x0000000000020000)
> =A0#define CPU_FTR_NO_BTIC=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0=20
> ASM_CONST(0x0000000000040000)
> =A0#define CPU_FTR_BIG_PHYS=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
ASM_CONST(0x0000000000080000)
> +#define CPU_FTR_NODSISRALIGN=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
ASM_CONST(0x0000000000100000)
> =A0
> =A0#ifdef __powerpc64__
> =A0/* Add the 64b processor unique features in the top half of the =
word=20
> */
> @@ -97,7 +98,6 @@
> =A0#define CPU_FTR_16M_PAGE=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
ASM_CONST(0x0000000200000000)
> =A0#define CPU_FTR_TLBIEL=A0=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0=20
> ASM_CONST(0x0000000400000000)
> =A0#define CPU_FTR_NOEXECUTE=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
ASM_CONST(0x0000000800000000)
> -#define CPU_FTR_NODSISRALIGN=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
ASM_CONST(0x0000001000000000)
> =A0#define CPU_FTR_IABR=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0=
ASM_CONST(0x0000002000000000)
> =A0#define CPU_FTR_MMCRA=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0=20
> ASM_CONST(0x0000004000000000)
> =A0#define CPU_FTR_CTRL=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0=
ASM_CONST(0x0000008000000000)
> @@ -113,7 +113,6 @@
> =A0#define CPU_FTR_16M_PAGE=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
ASM_CONST(0x0)
> =A0#define CPU_FTR_TLBIEL=A0=A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 ASM_CONST(0x0)
> =A0#define CPU_FTR_NOEXECUTE=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
ASM_CONST(0x0)
> -#define CPU_FTR_NODSISRALIGN=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
ASM_CONST(0x0)
> =A0#define CPU_FTR_IABR=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0=
ASM_CONST(0x0)
> =A0#define CPU_FTR_MMCRA=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0 ASM_CONST(0x0)
> =A0#define CPU_FTR_CTRL=A0=A0 =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0=A0=A0=A0=A0=
ASM_CONST(0x0)
> @@ -273,18 +272,21 @@
> =A0=A0=A0=A0=A0=A0=A0 CPU_FTRS_POWER3_32 =3D CPU_FTR_COMMON | =
CPU_FTR_SPLIT_ID_CACHE |
> =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
> =A0=A0=A0=A0=A0=A0=A0 CPU_FTRS_POWER4_32 =3D CPU_FTR_COMMON | =
CPU_FTR_SPLIT_ID_CACHE |
> -=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | =
CPU_FTR_NODSISRALIGN,
> =A0=A0=A0=A0=A0=A0=A0 CPU_FTRS_970_32 =3D CPU_FTR_COMMON | =
CPU_FTR_SPLIT_ID_CACHE |
> =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | =
CPU_FTR_ALTIVEC_COMP=20
> |
> -=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_MAYBE_CAN_NAP,
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_MAYBE_CAN_NAP | =
CPU_FTR_NODSISRALIGN,
> =A0=A0=A0=A0=A0=A0=A0 CPU_FTRS_8XX =3D CPU_FTR_SPLIT_ID_CACHE | =
CPU_FTR_USE_TB,
> -=A0=A0=A0=A0=A0=A0 CPU_FTRS_40X =3D CPU_FTR_SPLIT_ID_CACHE | =
CPU_FTR_USE_TB,
> -=A0=A0=A0=A0=A0=A0 CPU_FTRS_44X =3D CPU_FTR_SPLIT_ID_CACHE | =
CPU_FTR_USE_TB,
> -=A0=A0=A0=A0=A0=A0 CPU_FTRS_E200 =3D CPU_FTR_USE_TB,
> -=A0=A0=A0=A0=A0=A0 CPU_FTRS_E500 =3D CPU_FTR_SPLIT_ID_CACHE | =
CPU_FTR_USE_TB,
> +=A0=A0=A0=A0=A0=A0 CPU_FTRS_40X =3D CPU_FTR_SPLIT_ID_CACHE | =
CPU_FTR_USE_TB |
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_NODSISRALIGN,
> +=A0=A0=A0=A0=A0=A0 CPU_FTRS_44X =3D CPU_FTR_SPLIT_ID_CACHE | =
CPU_FTR_USE_TB |
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_NODSISRALIGN,
> +=A0=A0=A0=A0=A0=A0 CPU_FTRS_E200 =3D CPU_FTR_USE_TB | =
CPU_FTR_NODSISRALIGN,
> +=A0=A0=A0=A0=A0=A0 CPU_FTRS_E500 =3D CPU_FTR_SPLIT_ID_CACHE | =
CPU_FTR_USE_TB |
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_NODSISRALIGN,
> =A0=A0=A0=A0=A0=A0=A0 CPU_FTRS_E500_2 =3D CPU_FTR_SPLIT_ID_CACHE | =
CPU_FTR_USE_TB |
> -=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_BIG_PHYS,
> -=A0=A0=A0=A0=A0=A0 CPU_FTRS_GENERIC_32 =3D CPU_FTR_COMMON,
> +=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN,
> +=A0=A0=A0=A0=A0=A0 CPU_FTRS_GENERIC_32 =3D CPU_FTR_COMMON | =
CPU_FTR_NODSISRALIGN,
> =A0#ifdef __powerpc64__
> =A0=A0=A0=A0=A0=A0=A0 CPU_FTRS_POWER3 =3D CPU_FTR_SPLIT_ID_CACHE | =
CPU_FTR_USE_TB |
> =A0=A0=A0=A0=A0=A0=A0 =A0=A0=A0 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* [PATCH] m8xx_wdt: software watchdog reset/interrupt select
From: Marcelo Tosatti @ 2005-11-14 14:38 UTC (permalink / raw)
To: linux-ppc-embedded; +Cc: obi, Florian Schirmer, carjay
Hi,
Currently the mpc8xx_wdt driver installs an IRQ handler for
PIT_INTERRUPT (SIU_LEVEL0, irq 1) to service the WDT until a userspace
watchdog daemon takes over after boot.
However, if the "software watchdog reset/interrupt select" (SWRI) bit of
SYPCR register is set, no interrupt is generated. In that configuration
(the default) HRESET signal is generated if the WDT timeout expires,
without kernel notification.
The following patch creates a kernel timer to service the WDT and rearm
itself in case this configuration is detected, making it possible to
boot the system with the watchdog turned on. The timer is shutdown
once the userspace daemon open's the device.
Note: From my reading of the documentation, even if the SWRI bit is
unset (interrupt select mode), an NMI at IRQ0 should cause the system to
jump to exception vector 0x100, resetting the system.
So I'm wondering if the interrupt mode ever worked?
--- ../git/linux-2.6/arch/ppc/syslib/m8xx_wdt.c 2005-11-08 11:38:39.000000000 -0600
+++ linux-2.6-git-wednov02/arch/ppc/syslib/m8xx_wdt.c 2005-11-14 10:36:53.000000000 -0600
@@ -45,35 +45,18 @@
return IRQ_HANDLED;
}
-void __init m8xx_wdt_handler_install(bd_t * binfo)
+#define SYPCR_SWP 0x1
+#define SYPCR_SWRI 0x2
+#define SYPCR_SWE 0x4
+
+/* software watchdog reset/interrupt select */
+int m8xx_wdt_keepalive_mode = 0;
+
+void __init m8xx_wdt_install_irq(volatile immap_t *imap, bd_t *binfo)
{
- volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
u32 pitc;
- u32 sypcr;
u32 pitrtclk;
- sypcr = in_be32(&imap->im_siu_conf.sc_sypcr);
-
- if (!(sypcr & 0x04)) {
- printk(KERN_NOTICE "m8xx_wdt: wdt disabled (SYPCR: 0x%08X)\n",
- sypcr);
- return;
- }
-
- m8xx_wdt_reset();
-
- printk(KERN_NOTICE
- "m8xx_wdt: active wdt found (SWTC: 0x%04X, SWP: 0x%01X)\n",
- (sypcr >> 16), sypcr & 0x01);
-
- wdt_timeout = (sypcr >> 16) & 0xFFFF;
-
- if (!wdt_timeout)
- wdt_timeout = 0xFFFF;
-
- if (sypcr & 0x01)
- wdt_timeout *= 2048;
-
/*
* Fire trigger if half of the wdt ticked down
*/
@@ -98,6 +81,66 @@
printk(KERN_NOTICE
"m8xx_wdt: keep-alive trigger installed (PITC: 0x%04X)\n", pitc);
+}
+
+static void m8xx_wdt_timer_func(unsigned long data);
+
+static struct timer_list m8xx_wdt_timer =
+ TIMER_INITIALIZER(m8xx_wdt_timer_func, 0, 0);
+
+void m8xx_wdt_stop_timer(void)
+{
+ del_timer(&m8xx_wdt_timer);
+}
+
+static void m8xx_wdt_timer_func(unsigned long data)
+{
+ m8xx_wdt_reset();
+ m8xx_wdt_timer.expires = jiffies + 25;
+ add_timer(&m8xx_wdt_timer);
+}
+
+void m8xx_wdt_install_timer(volatile immap_t *imap)
+{
+ m8xx_wdt_timer.expires = jiffies + 25;
+ add_timer(&m8xx_wdt_timer);
+}
+
+void __init m8xx_wdt_handler_install(bd_t * binfo)
+{
+ volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
+ u32 sypcr;
+
+ sypcr = in_be32(&imap->im_siu_conf.sc_sypcr);
+
+ printk(KERN_NOTICE "m8xx_wdt SYPCR: 0x%08X)\n", sypcr);
+
+ if (!(sypcr & SYPCR_SWE)) {
+ printk(KERN_NOTICE "m8xx_wdt: wdt disabled (SYPCR: 0x%08X)\n",
+ sypcr);
+ return;
+ }
+
+ m8xx_wdt_reset();
+
+ printk(KERN_NOTICE
+ "m8xx_wdt: active wdt found (SWTC: 0x%04X, SWP: 0x%01X)\n",
+ (sypcr >> 16), sypcr & SYPCR_SWP);
+
+ wdt_timeout = (sypcr >> 16) & 0xFFFF;
+
+ if (!wdt_timeout)
+ wdt_timeout = 0xFFFF;
+
+ if (sypcr & SYPCR_SWP)
+ wdt_timeout *= 2048;
+
+ m8xx_wdt_keepalive_mode = sypcr & SYPCR_SWRI;
+ if (m8xx_wdt_keepalive_mode)
+ m8xx_wdt_install_timer(imap);
+ else
+ m8xx_wdt_install_irq(imap, binfo);
+
wdt_timeout /= binfo->bi_intfreq;
}
--- ../git/linux-2.6/arch/ppc/syslib/m8xx_wdt.h 2005-10-10 18:06:12.000000000 -0500
+++ linux-2.6-git-wednov02/arch/ppc/syslib/m8xx_wdt.h 2005-11-14 10:37:39.000000000 -0600
@@ -9,8 +9,12 @@
#ifndef _PPC_SYSLIB_M8XX_WDT_H
#define _PPC_SYSLIB_M8XX_WDT_H
+extern int m8xx_wdt_keepalive_mode;
+
extern void m8xx_wdt_handler_install(bd_t * binfo);
extern int m8xx_wdt_get_timeout(void);
extern void m8xx_wdt_reset(void);
+extern void m8xx_wdt_install_timer(volatile immap_t *imap);
+extern void m8xx_wdt_stop_timer(void);
#endif /* _PPC_SYSLIB_M8XX_WDT_H */
--- ../git/linux-2.6/drivers/char/watchdog/mpc8xx_wdt.c 2005-10-10 18:06:15.000000000 -0500
+++ linux-2.6-git-wednov02/drivers/char/watchdog/mpc8xx_wdt.c 2005-11-14 10:37:15.000000000 -0600
@@ -27,7 +27,10 @@
{
volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
- imap->im_sit.sit_piscr &= ~(PISCR_PIE | PISCR_PTE);
+ if (m8xx_wdt_keepalive_mode)
+ m8xx_wdt_stop_timer();
+ else
+ imap->im_sit.sit_piscr &= ~(PISCR_PIE | PISCR_PTE);
printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler deactivated\n");
}
@@ -36,7 +39,10 @@
{
volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
- imap->im_sit.sit_piscr |= PISCR_PIE | PISCR_PTE;
+ if (m8xx_wdt_keepalive_mode)
+ m8xx_wdt_install_timer(imap);
+ else
+ imap->im_sit.sit_piscr |= PISCR_PIE | PISCR_PTE;
printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler activated\n");
}
^ permalink raw reply
* Re: [PLEASE REVIEW] ppc32 8xx: core PRxK board family support
From: Dan Malek @ 2005-11-14 19:06 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: linux-ppc-dev, linux-ppc-embedded
In-Reply-To: <20051114124538.GB28633@logos.cnet>
On Nov 14, 2005, at 7:45 AM, Marcelo Tosatti wrote:
> +++ linux-2.6.14-rc4/arch/ppc/boot/include/cyc_banner.h 2005-10-25
> 07:01:57.000000000 -0500
I'm not a big fan of all of these banners, printing, and ascii
text in the kernel, but if you think you must have it ........
> +//XXX: remove? Its unused.
> +#if 0
> +struct type0000 {
> + unsigned char flash_sign[FLASH_SIGN_SIZE]; /* mark initialized
> CMOS */
> + unsigned char version; /* Configure vector version */
> + unsigned char routing_protocol; /* RIP, OSPF, etc */
> + unsigned char save_sw; /* TRUE : the RTBOOT must be
> saved into flash */
> +};
> +#endif
Yes please, remove it.
> + //[GB]May/06/05 Ethernet Receive Rate Limit
> + // unsigned char reserved1[4];
Get rid of trash like this, too, or make it a real C style comment
that explains what is going on here for the rest of us.
> +++ linux-2.6.14-rc4/arch/ppc/boot/simple/embed_config.c 2005-10-25
> 13:55:04.000000000 -0500
This is a pretty big chunk of board specific code beyond just setting
up the board configuration info. Consider making it a separate file.
> +++ linux-2.6.14-rc4/arch/ppc/platforms/cpld.h 2005-10-24
> 15:35:25.000000000 -0500
Would you name this something a little more descriptive, like
perhaps cyc_cpld.h? Makes it easier to understand where the
files are used.
> +struct fpga_pc_regs {
> + unsigned char fpga_pc_misc; // Controls PCMCIA IO's window size
I still don't like // comments ....... :-)
> +// mem_addr = (unsigned long *)(&cpmp->cp_dpmem[dp_addr]);
Just remove it.
> +// dp_addr = m8xx_cpm_dpalloc(32);
Ditto, and anywhere else. If code isn't used, let's just get
rid of it. Or put in a comment why there may be alternative
or if you are testing something.
Thanks!
-- Dan
^ permalink raw reply
* [PATCH] powerpc: moved ipic code to arch/powerpc
From: Kumar Gala @ 2005-11-14 18:54 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, linuxppc-embedded
Moved 83xx and QUICC Engine interrupt handling code into arch/powerpc
as a precursor of getting 83xx sub-arch building in arch/powerpc.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
commit 37ae6e53ffc338b28dc5409f0a6be4d8374cca21
tree 4aa155c3faff04f1c287c7e19fbe38182aa266e1
parent e982b09df1f635eb047e5be9633c89045ba021c2
author Kumar Gala <galak@kernel.crashing.org> Mon, 14 Nov 2005 12:54:33 -0600
committer Kumar Gala <galak@kernel.crashing.org> Mon, 14 Nov 2005 12:54:33 -0600
arch/powerpc/sysdev/Makefile | 1
arch/powerpc/sysdev/ipic.c | 646 ++++++++++++++++++++++++++++++++++++++++++
arch/powerpc/sysdev/ipic.h | 49 +++
arch/ppc/syslib/Makefile | 2
arch/ppc/syslib/ipic.c | 646 ------------------------------------------
arch/ppc/syslib/ipic.h | 49 ---
include/asm-powerpc/ipic.h | 85 ++++++
include/asm-ppc/ipic.h | 85 ------
8 files changed, 782 insertions(+), 781 deletions(-)
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 6b7efcf..b3e3636 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_BOOKE) += dcr.o
obj-$(CONFIG_40x) += dcr.o
obj-$(CONFIG_U3_DART) += u3_iommu.o
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
+obj-$(CONFIG_83xx) += ipic.o
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
new file mode 100644
index 0000000..8f01e0f
--- /dev/null
+++ b/arch/powerpc/sysdev/ipic.c
@@ -0,0 +1,646 @@
+/*
+ * include/asm-ppc/ipic.c
+ *
+ * IPIC routines implementations.
+ *
+ * Copyright 2005 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/sysdev.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/ipic.h>
+#include <asm/mpc83xx.h>
+
+#include "ipic.h"
+
+static struct ipic p_ipic;
+static struct ipic * primary_ipic;
+
+static struct ipic_info ipic_info[] = {
+ [9] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_D,
+ .force = IPIC_SIFCR_H,
+ .bit = 24,
+ .prio_mask = 0,
+ },
+ [10] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_D,
+ .force = IPIC_SIFCR_H,
+ .bit = 25,
+ .prio_mask = 1,
+ },
+ [11] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_D,
+ .force = IPIC_SIFCR_H,
+ .bit = 26,
+ .prio_mask = 2,
+ },
+ [14] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_D,
+ .force = IPIC_SIFCR_H,
+ .bit = 29,
+ .prio_mask = 5,
+ },
+ [15] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_D,
+ .force = IPIC_SIFCR_H,
+ .bit = 30,
+ .prio_mask = 6,
+ },
+ [16] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_D,
+ .force = IPIC_SIFCR_H,
+ .bit = 31,
+ .prio_mask = 7,
+ },
+ [17] = {
+ .pend = IPIC_SEPNR,
+ .mask = IPIC_SEMSR,
+ .prio = IPIC_SMPRR_A,
+ .force = IPIC_SEFCR,
+ .bit = 1,
+ .prio_mask = 5,
+ },
+ [18] = {
+ .pend = IPIC_SEPNR,
+ .mask = IPIC_SEMSR,
+ .prio = IPIC_SMPRR_A,
+ .force = IPIC_SEFCR,
+ .bit = 2,
+ .prio_mask = 6,
+ },
+ [19] = {
+ .pend = IPIC_SEPNR,
+ .mask = IPIC_SEMSR,
+ .prio = IPIC_SMPRR_A,
+ .force = IPIC_SEFCR,
+ .bit = 3,
+ .prio_mask = 7,
+ },
+ [20] = {
+ .pend = IPIC_SEPNR,
+ .mask = IPIC_SEMSR,
+ .prio = IPIC_SMPRR_B,
+ .force = IPIC_SEFCR,
+ .bit = 4,
+ .prio_mask = 4,
+ },
+ [21] = {
+ .pend = IPIC_SEPNR,
+ .mask = IPIC_SEMSR,
+ .prio = IPIC_SMPRR_B,
+ .force = IPIC_SEFCR,
+ .bit = 5,
+ .prio_mask = 5,
+ },
+ [22] = {
+ .pend = IPIC_SEPNR,
+ .mask = IPIC_SEMSR,
+ .prio = IPIC_SMPRR_B,
+ .force = IPIC_SEFCR,
+ .bit = 6,
+ .prio_mask = 6,
+ },
+ [23] = {
+ .pend = IPIC_SEPNR,
+ .mask = IPIC_SEMSR,
+ .prio = IPIC_SMPRR_B,
+ .force = IPIC_SEFCR,
+ .bit = 7,
+ .prio_mask = 7,
+ },
+ [32] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_A,
+ .force = IPIC_SIFCR_H,
+ .bit = 0,
+ .prio_mask = 0,
+ },
+ [33] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_A,
+ .force = IPIC_SIFCR_H,
+ .bit = 1,
+ .prio_mask = 1,
+ },
+ [34] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_A,
+ .force = IPIC_SIFCR_H,
+ .bit = 2,
+ .prio_mask = 2,
+ },
+ [35] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_A,
+ .force = IPIC_SIFCR_H,
+ .bit = 3,
+ .prio_mask = 3,
+ },
+ [36] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_A,
+ .force = IPIC_SIFCR_H,
+ .bit = 4,
+ .prio_mask = 4,
+ },
+ [37] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_A,
+ .force = IPIC_SIFCR_H,
+ .bit = 5,
+ .prio_mask = 5,
+ },
+ [38] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_A,
+ .force = IPIC_SIFCR_H,
+ .bit = 6,
+ .prio_mask = 6,
+ },
+ [39] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_A,
+ .force = IPIC_SIFCR_H,
+ .bit = 7,
+ .prio_mask = 7,
+ },
+ [48] = {
+ .pend = IPIC_SEPNR,
+ .mask = IPIC_SEMSR,
+ .prio = IPIC_SMPRR_A,
+ .force = IPIC_SEFCR,
+ .bit = 0,
+ .prio_mask = 4,
+ },
+ [64] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = IPIC_SMPRR_A,
+ .force = IPIC_SIFCR_L,
+ .bit = 0,
+ .prio_mask = 0,
+ },
+ [65] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = IPIC_SMPRR_A,
+ .force = IPIC_SIFCR_L,
+ .bit = 1,
+ .prio_mask = 1,
+ },
+ [66] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = IPIC_SMPRR_A,
+ .force = IPIC_SIFCR_L,
+ .bit = 2,
+ .prio_mask = 2,
+ },
+ [67] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = IPIC_SMPRR_A,
+ .force = IPIC_SIFCR_L,
+ .bit = 3,
+ .prio_mask = 3,
+ },
+ [68] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = IPIC_SMPRR_B,
+ .force = IPIC_SIFCR_L,
+ .bit = 4,
+ .prio_mask = 0,
+ },
+ [69] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = IPIC_SMPRR_B,
+ .force = IPIC_SIFCR_L,
+ .bit = 5,
+ .prio_mask = 1,
+ },
+ [70] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = IPIC_SMPRR_B,
+ .force = IPIC_SIFCR_L,
+ .bit = 6,
+ .prio_mask = 2,
+ },
+ [71] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = IPIC_SMPRR_B,
+ .force = IPIC_SIFCR_L,
+ .bit = 7,
+ .prio_mask = 3,
+ },
+ [72] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 8,
+ },
+ [73] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 9,
+ },
+ [74] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 10,
+ },
+ [75] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 11,
+ },
+ [76] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 12,
+ },
+ [77] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 13,
+ },
+ [78] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 14,
+ },
+ [79] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 15,
+ },
+ [80] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 16,
+ },
+ [84] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 20,
+ },
+ [85] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 21,
+ },
+ [90] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 26,
+ },
+ [91] = {
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 27,
+ },
+};
+
+static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
+{
+ return in_be32(base + (reg >> 2));
+}
+
+static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
+{
+ out_be32(base + (reg >> 2), value);
+}
+
+static inline struct ipic * ipic_from_irq(unsigned int irq)
+{
+ return primary_ipic;
+}
+
+static void ipic_enable_irq(unsigned int irq)
+{
+ struct ipic *ipic = ipic_from_irq(irq);
+ unsigned int src = irq - ipic->irq_offset;
+ u32 temp;
+
+ temp = ipic_read(ipic->regs, ipic_info[src].mask);
+ temp |= (1 << (31 - ipic_info[src].bit));
+ ipic_write(ipic->regs, ipic_info[src].mask, temp);
+}
+
+static void ipic_disable_irq(unsigned int irq)
+{
+ struct ipic *ipic = ipic_from_irq(irq);
+ unsigned int src = irq - ipic->irq_offset;
+ u32 temp;
+
+ temp = ipic_read(ipic->regs, ipic_info[src].mask);
+ temp &= ~(1 << (31 - ipic_info[src].bit));
+ ipic_write(ipic->regs, ipic_info[src].mask, temp);
+}
+
+static void ipic_disable_irq_and_ack(unsigned int irq)
+{
+ struct ipic *ipic = ipic_from_irq(irq);
+ unsigned int src = irq - ipic->irq_offset;
+ u32 temp;
+
+ ipic_disable_irq(irq);
+
+ temp = ipic_read(ipic->regs, ipic_info[src].pend);
+ temp |= (1 << (31 - ipic_info[src].bit));
+ ipic_write(ipic->regs, ipic_info[src].pend, temp);
+}
+
+static void ipic_end_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ ipic_enable_irq(irq);
+}
+
+struct hw_interrupt_type ipic = {
+ .typename = " IPIC ",
+ .enable = ipic_enable_irq,
+ .disable = ipic_disable_irq,
+ .ack = ipic_disable_irq_and_ack,
+ .end = ipic_end_irq,
+};
+
+void __init ipic_init(phys_addr_t phys_addr,
+ unsigned int flags,
+ unsigned int irq_offset,
+ unsigned char *senses,
+ unsigned int senses_count)
+{
+ u32 i, temp = 0;
+
+ primary_ipic = &p_ipic;
+ primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
+
+ primary_ipic->irq_offset = irq_offset;
+
+ ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0);
+
+ /* default priority scheme is grouped. If spread mode is required
+ * configure SICFR accordingly */
+ if (flags & IPIC_SPREADMODE_GRP_A)
+ temp |= SICFR_IPSA;
+ if (flags & IPIC_SPREADMODE_GRP_D)
+ temp |= SICFR_IPSD;
+ if (flags & IPIC_SPREADMODE_MIX_A)
+ temp |= SICFR_MPSA;
+ if (flags & IPIC_SPREADMODE_MIX_B)
+ temp |= SICFR_MPSB;
+
+ ipic_write(primary_ipic->regs, IPIC_SICNR, temp);
+
+ /* handle MCP route */
+ temp = 0;
+ if (flags & IPIC_DISABLE_MCP_OUT)
+ temp = SERCR_MCPR;
+ ipic_write(primary_ipic->regs, IPIC_SERCR, temp);
+
+ /* handle routing of IRQ0 to MCP */
+ temp = ipic_read(primary_ipic->regs, IPIC_SEMSR);
+
+ if (flags & IPIC_IRQ0_MCP)
+ temp |= SEMSR_SIRQ0;
+ else
+ temp &= ~SEMSR_SIRQ0;
+
+ ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
+
+ for (i = 0 ; i < NR_IPIC_INTS ; i++) {
+ irq_desc[i+irq_offset].handler = &ipic;
+ irq_desc[i+irq_offset].status = IRQ_LEVEL;
+ }
+
+ temp = 0;
+ for (i = 0 ; i < senses_count ; i++) {
+ if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
+ temp |= 1 << (15 - i);
+ if (i != 0)
+ irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
+ else
+ irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
+ }
+ }
+ ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
+
+ printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
+ senses_count, primary_ipic->regs);
+}
+
+int ipic_set_priority(unsigned int irq, unsigned int priority)
+{
+ struct ipic *ipic = ipic_from_irq(irq);
+ unsigned int src = irq - ipic->irq_offset;
+ u32 temp;
+
+ if (priority > 7)
+ return -EINVAL;
+ if (src > 127)
+ return -EINVAL;
+ if (ipic_info[src].prio == 0)
+ return -EINVAL;
+
+ temp = ipic_read(ipic->regs, ipic_info[src].prio);
+
+ if (priority < 4) {
+ temp &= ~(0x7 << (20 + (3 - priority) * 3));
+ temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
+ } else {
+ temp &= ~(0x7 << (4 + (7 - priority) * 3));
+ temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
+ }
+
+ ipic_write(ipic->regs, ipic_info[src].prio, temp);
+
+ return 0;
+}
+
+void ipic_set_highest_priority(unsigned int irq)
+{
+ struct ipic *ipic = ipic_from_irq(irq);
+ unsigned int src = irq - ipic->irq_offset;
+ u32 temp;
+
+ temp = ipic_read(ipic->regs, IPIC_SICFR);
+
+ /* clear and set HPI */
+ temp &= 0x7f000000;
+ temp |= (src & 0x7f) << 24;
+
+ ipic_write(ipic->regs, IPIC_SICFR, temp);
+}
+
+void ipic_set_default_priority(void)
+{
+ ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
+ ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
+ ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
+ ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
+ ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
+ ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
+ ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
+ ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
+
+ ipic_set_priority(MPC83xx_IRQ_UART1, 0);
+ ipic_set_priority(MPC83xx_IRQ_UART2, 1);
+ ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
+ ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
+ ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
+ ipic_set_priority(MPC83xx_IRQ_SPI, 7);
+ ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
+ ipic_set_priority(MPC83xx_IRQ_PIT, 1);
+ ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
+ ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
+ ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
+ ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
+ ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
+ ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
+ ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
+ ipic_set_priority(MPC83xx_IRQ_MU, 1);
+ ipic_set_priority(MPC83xx_IRQ_SBA, 2);
+ ipic_set_priority(MPC83xx_IRQ_DMA, 3);
+ ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
+ ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
+ ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
+ ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
+}
+
+void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
+{
+ struct ipic *ipic = primary_ipic;
+ u32 temp;
+
+ temp = ipic_read(ipic->regs, IPIC_SERMR);
+ temp |= (1 << (31 - mcp_irq));
+ ipic_write(ipic->regs, IPIC_SERMR, temp);
+}
+
+void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
+{
+ struct ipic *ipic = primary_ipic;
+ u32 temp;
+
+ temp = ipic_read(ipic->regs, IPIC_SERMR);
+ temp &= (1 << (31 - mcp_irq));
+ ipic_write(ipic->regs, IPIC_SERMR, temp);
+}
+
+u32 ipic_get_mcp_status(void)
+{
+ return ipic_read(primary_ipic->regs, IPIC_SERMR);
+}
+
+void ipic_clear_mcp_status(u32 mask)
+{
+ ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
+}
+
+/* Return an interrupt vector or -1 if no interrupt is pending. */
+int ipic_get_irq(struct pt_regs *regs)
+{
+ int irq;
+
+ irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f;
+
+ if (irq == 0) /* 0 --> no irq is pending */
+ irq = -1;
+
+ return irq;
+}
+
+static struct sysdev_class ipic_sysclass = {
+ set_kset_name("ipic"),
+};
+
+static struct sys_device device_ipic = {
+ .id = 0,
+ .cls = &ipic_sysclass,
+};
+
+static int __init init_ipic_sysfs(void)
+{
+ int rc;
+
+ if (!primary_ipic->regs)
+ return -ENODEV;
+ printk(KERN_DEBUG "Registering ipic with sysfs...\n");
+
+ rc = sysdev_class_register(&ipic_sysclass);
+ if (rc) {
+ printk(KERN_ERR "Failed registering ipic sys class\n");
+ return -ENODEV;
+ }
+ rc = sysdev_register(&device_ipic);
+ if (rc) {
+ printk(KERN_ERR "Failed registering ipic sys device\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
+subsys_initcall(init_ipic_sysfs);
diff --git a/arch/powerpc/sysdev/ipic.h b/arch/powerpc/sysdev/ipic.h
new file mode 100644
index 0000000..a7ce7da
--- /dev/null
+++ b/arch/powerpc/sysdev/ipic.h
@@ -0,0 +1,49 @@
+/*
+ * arch/ppc/kernel/ipic.h
+ *
+ * IPIC private definitions and structure.
+ *
+ * Maintainer: Kumar Gala <galak@kernel.crashing.org>
+ *
+ * Copyright 2005 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __IPIC_H__
+#define __IPIC_H__
+
+#include <asm/ipic.h>
+
+#define MPC83xx_IPIC_SIZE (0x00100)
+
+/* System Global Interrupt Configuration Register */
+#define SICFR_IPSA 0x00010000
+#define SICFR_IPSD 0x00080000
+#define SICFR_MPSA 0x00200000
+#define SICFR_MPSB 0x00400000
+
+/* System External Interrupt Mask Register */
+#define SEMSR_SIRQ0 0x00008000
+
+/* System Error Control Register */
+#define SERCR_MCPR 0x00000001
+
+struct ipic {
+ volatile u32 __iomem *regs;
+ unsigned int irq_offset;
+};
+
+struct ipic_info {
+ u8 pend; /* pending register offset from base */
+ u8 mask; /* mask register offset from base */
+ u8 prio; /* priority register offset from base */
+ u8 force; /* force register offset from base */
+ u8 bit; /* register bit position (as per doc)
+ bit mask = 1 << (31 - bit) */
+ u8 prio_mask; /* priority mask value */
+};
+
+#endif /* __IPIC_H__ */
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index 5b7f2b8..84ef030 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -96,7 +96,7 @@ ifeq ($(CONFIG_85xx),y)
obj-$(CONFIG_PCI) += pci_auto.o
endif
obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o
-obj-$(CONFIG_83xx) += ipic.o ppc83xx_setup.o ppc_sys.o \
+obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \
mpc83xx_sys.o mpc83xx_devices.o
ifeq ($(CONFIG_83xx),y)
obj-$(CONFIG_PCI) += pci_auto.o
diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c
deleted file mode 100644
index 8f01e0f..0000000
--- a/arch/ppc/syslib/ipic.c
+++ /dev/null
@@ -1,646 +0,0 @@
-/*
- * include/asm-ppc/ipic.c
- *
- * IPIC routines implementations.
- *
- * Copyright 2005 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/slab.h>
-#include <linux/stddef.h>
-#include <linux/sched.h>
-#include <linux/signal.h>
-#include <linux/sysdev.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/ipic.h>
-#include <asm/mpc83xx.h>
-
-#include "ipic.h"
-
-static struct ipic p_ipic;
-static struct ipic * primary_ipic;
-
-static struct ipic_info ipic_info[] = {
- [9] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_D,
- .force = IPIC_SIFCR_H,
- .bit = 24,
- .prio_mask = 0,
- },
- [10] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_D,
- .force = IPIC_SIFCR_H,
- .bit = 25,
- .prio_mask = 1,
- },
- [11] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_D,
- .force = IPIC_SIFCR_H,
- .bit = 26,
- .prio_mask = 2,
- },
- [14] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_D,
- .force = IPIC_SIFCR_H,
- .bit = 29,
- .prio_mask = 5,
- },
- [15] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_D,
- .force = IPIC_SIFCR_H,
- .bit = 30,
- .prio_mask = 6,
- },
- [16] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_D,
- .force = IPIC_SIFCR_H,
- .bit = 31,
- .prio_mask = 7,
- },
- [17] = {
- .pend = IPIC_SEPNR,
- .mask = IPIC_SEMSR,
- .prio = IPIC_SMPRR_A,
- .force = IPIC_SEFCR,
- .bit = 1,
- .prio_mask = 5,
- },
- [18] = {
- .pend = IPIC_SEPNR,
- .mask = IPIC_SEMSR,
- .prio = IPIC_SMPRR_A,
- .force = IPIC_SEFCR,
- .bit = 2,
- .prio_mask = 6,
- },
- [19] = {
- .pend = IPIC_SEPNR,
- .mask = IPIC_SEMSR,
- .prio = IPIC_SMPRR_A,
- .force = IPIC_SEFCR,
- .bit = 3,
- .prio_mask = 7,
- },
- [20] = {
- .pend = IPIC_SEPNR,
- .mask = IPIC_SEMSR,
- .prio = IPIC_SMPRR_B,
- .force = IPIC_SEFCR,
- .bit = 4,
- .prio_mask = 4,
- },
- [21] = {
- .pend = IPIC_SEPNR,
- .mask = IPIC_SEMSR,
- .prio = IPIC_SMPRR_B,
- .force = IPIC_SEFCR,
- .bit = 5,
- .prio_mask = 5,
- },
- [22] = {
- .pend = IPIC_SEPNR,
- .mask = IPIC_SEMSR,
- .prio = IPIC_SMPRR_B,
- .force = IPIC_SEFCR,
- .bit = 6,
- .prio_mask = 6,
- },
- [23] = {
- .pend = IPIC_SEPNR,
- .mask = IPIC_SEMSR,
- .prio = IPIC_SMPRR_B,
- .force = IPIC_SEFCR,
- .bit = 7,
- .prio_mask = 7,
- },
- [32] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_A,
- .force = IPIC_SIFCR_H,
- .bit = 0,
- .prio_mask = 0,
- },
- [33] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_A,
- .force = IPIC_SIFCR_H,
- .bit = 1,
- .prio_mask = 1,
- },
- [34] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_A,
- .force = IPIC_SIFCR_H,
- .bit = 2,
- .prio_mask = 2,
- },
- [35] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_A,
- .force = IPIC_SIFCR_H,
- .bit = 3,
- .prio_mask = 3,
- },
- [36] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_A,
- .force = IPIC_SIFCR_H,
- .bit = 4,
- .prio_mask = 4,
- },
- [37] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_A,
- .force = IPIC_SIFCR_H,
- .bit = 5,
- .prio_mask = 5,
- },
- [38] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_A,
- .force = IPIC_SIFCR_H,
- .bit = 6,
- .prio_mask = 6,
- },
- [39] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_H,
- .prio = IPIC_SIPRR_A,
- .force = IPIC_SIFCR_H,
- .bit = 7,
- .prio_mask = 7,
- },
- [48] = {
- .pend = IPIC_SEPNR,
- .mask = IPIC_SEMSR,
- .prio = IPIC_SMPRR_A,
- .force = IPIC_SEFCR,
- .bit = 0,
- .prio_mask = 4,
- },
- [64] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = IPIC_SMPRR_A,
- .force = IPIC_SIFCR_L,
- .bit = 0,
- .prio_mask = 0,
- },
- [65] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = IPIC_SMPRR_A,
- .force = IPIC_SIFCR_L,
- .bit = 1,
- .prio_mask = 1,
- },
- [66] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = IPIC_SMPRR_A,
- .force = IPIC_SIFCR_L,
- .bit = 2,
- .prio_mask = 2,
- },
- [67] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = IPIC_SMPRR_A,
- .force = IPIC_SIFCR_L,
- .bit = 3,
- .prio_mask = 3,
- },
- [68] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = IPIC_SMPRR_B,
- .force = IPIC_SIFCR_L,
- .bit = 4,
- .prio_mask = 0,
- },
- [69] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = IPIC_SMPRR_B,
- .force = IPIC_SIFCR_L,
- .bit = 5,
- .prio_mask = 1,
- },
- [70] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = IPIC_SMPRR_B,
- .force = IPIC_SIFCR_L,
- .bit = 6,
- .prio_mask = 2,
- },
- [71] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = IPIC_SMPRR_B,
- .force = IPIC_SIFCR_L,
- .bit = 7,
- .prio_mask = 3,
- },
- [72] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 8,
- },
- [73] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 9,
- },
- [74] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 10,
- },
- [75] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 11,
- },
- [76] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 12,
- },
- [77] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 13,
- },
- [78] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 14,
- },
- [79] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 15,
- },
- [80] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 16,
- },
- [84] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 20,
- },
- [85] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 21,
- },
- [90] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 26,
- },
- [91] = {
- .pend = IPIC_SIPNR_H,
- .mask = IPIC_SIMSR_L,
- .prio = 0,
- .force = IPIC_SIFCR_L,
- .bit = 27,
- },
-};
-
-static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
-{
- return in_be32(base + (reg >> 2));
-}
-
-static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
-{
- out_be32(base + (reg >> 2), value);
-}
-
-static inline struct ipic * ipic_from_irq(unsigned int irq)
-{
- return primary_ipic;
-}
-
-static void ipic_enable_irq(unsigned int irq)
-{
- struct ipic *ipic = ipic_from_irq(irq);
- unsigned int src = irq - ipic->irq_offset;
- u32 temp;
-
- temp = ipic_read(ipic->regs, ipic_info[src].mask);
- temp |= (1 << (31 - ipic_info[src].bit));
- ipic_write(ipic->regs, ipic_info[src].mask, temp);
-}
-
-static void ipic_disable_irq(unsigned int irq)
-{
- struct ipic *ipic = ipic_from_irq(irq);
- unsigned int src = irq - ipic->irq_offset;
- u32 temp;
-
- temp = ipic_read(ipic->regs, ipic_info[src].mask);
- temp &= ~(1 << (31 - ipic_info[src].bit));
- ipic_write(ipic->regs, ipic_info[src].mask, temp);
-}
-
-static void ipic_disable_irq_and_ack(unsigned int irq)
-{
- struct ipic *ipic = ipic_from_irq(irq);
- unsigned int src = irq - ipic->irq_offset;
- u32 temp;
-
- ipic_disable_irq(irq);
-
- temp = ipic_read(ipic->regs, ipic_info[src].pend);
- temp |= (1 << (31 - ipic_info[src].bit));
- ipic_write(ipic->regs, ipic_info[src].pend, temp);
-}
-
-static void ipic_end_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- ipic_enable_irq(irq);
-}
-
-struct hw_interrupt_type ipic = {
- .typename = " IPIC ",
- .enable = ipic_enable_irq,
- .disable = ipic_disable_irq,
- .ack = ipic_disable_irq_and_ack,
- .end = ipic_end_irq,
-};
-
-void __init ipic_init(phys_addr_t phys_addr,
- unsigned int flags,
- unsigned int irq_offset,
- unsigned char *senses,
- unsigned int senses_count)
-{
- u32 i, temp = 0;
-
- primary_ipic = &p_ipic;
- primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
-
- primary_ipic->irq_offset = irq_offset;
-
- ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0);
-
- /* default priority scheme is grouped. If spread mode is required
- * configure SICFR accordingly */
- if (flags & IPIC_SPREADMODE_GRP_A)
- temp |= SICFR_IPSA;
- if (flags & IPIC_SPREADMODE_GRP_D)
- temp |= SICFR_IPSD;
- if (flags & IPIC_SPREADMODE_MIX_A)
- temp |= SICFR_MPSA;
- if (flags & IPIC_SPREADMODE_MIX_B)
- temp |= SICFR_MPSB;
-
- ipic_write(primary_ipic->regs, IPIC_SICNR, temp);
-
- /* handle MCP route */
- temp = 0;
- if (flags & IPIC_DISABLE_MCP_OUT)
- temp = SERCR_MCPR;
- ipic_write(primary_ipic->regs, IPIC_SERCR, temp);
-
- /* handle routing of IRQ0 to MCP */
- temp = ipic_read(primary_ipic->regs, IPIC_SEMSR);
-
- if (flags & IPIC_IRQ0_MCP)
- temp |= SEMSR_SIRQ0;
- else
- temp &= ~SEMSR_SIRQ0;
-
- ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
-
- for (i = 0 ; i < NR_IPIC_INTS ; i++) {
- irq_desc[i+irq_offset].handler = &ipic;
- irq_desc[i+irq_offset].status = IRQ_LEVEL;
- }
-
- temp = 0;
- for (i = 0 ; i < senses_count ; i++) {
- if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
- temp |= 1 << (15 - i);
- if (i != 0)
- irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
- else
- irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
- }
- }
- ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
-
- printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
- senses_count, primary_ipic->regs);
-}
-
-int ipic_set_priority(unsigned int irq, unsigned int priority)
-{
- struct ipic *ipic = ipic_from_irq(irq);
- unsigned int src = irq - ipic->irq_offset;
- u32 temp;
-
- if (priority > 7)
- return -EINVAL;
- if (src > 127)
- return -EINVAL;
- if (ipic_info[src].prio == 0)
- return -EINVAL;
-
- temp = ipic_read(ipic->regs, ipic_info[src].prio);
-
- if (priority < 4) {
- temp &= ~(0x7 << (20 + (3 - priority) * 3));
- temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
- } else {
- temp &= ~(0x7 << (4 + (7 - priority) * 3));
- temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
- }
-
- ipic_write(ipic->regs, ipic_info[src].prio, temp);
-
- return 0;
-}
-
-void ipic_set_highest_priority(unsigned int irq)
-{
- struct ipic *ipic = ipic_from_irq(irq);
- unsigned int src = irq - ipic->irq_offset;
- u32 temp;
-
- temp = ipic_read(ipic->regs, IPIC_SICFR);
-
- /* clear and set HPI */
- temp &= 0x7f000000;
- temp |= (src & 0x7f) << 24;
-
- ipic_write(ipic->regs, IPIC_SICFR, temp);
-}
-
-void ipic_set_default_priority(void)
-{
- ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
- ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
- ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
- ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
- ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
- ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
- ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
- ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
-
- ipic_set_priority(MPC83xx_IRQ_UART1, 0);
- ipic_set_priority(MPC83xx_IRQ_UART2, 1);
- ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
- ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
- ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
- ipic_set_priority(MPC83xx_IRQ_SPI, 7);
- ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
- ipic_set_priority(MPC83xx_IRQ_PIT, 1);
- ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
- ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
- ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
- ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
- ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
- ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
- ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
- ipic_set_priority(MPC83xx_IRQ_MU, 1);
- ipic_set_priority(MPC83xx_IRQ_SBA, 2);
- ipic_set_priority(MPC83xx_IRQ_DMA, 3);
- ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
- ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
- ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
- ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
-}
-
-void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
-{
- struct ipic *ipic = primary_ipic;
- u32 temp;
-
- temp = ipic_read(ipic->regs, IPIC_SERMR);
- temp |= (1 << (31 - mcp_irq));
- ipic_write(ipic->regs, IPIC_SERMR, temp);
-}
-
-void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
-{
- struct ipic *ipic = primary_ipic;
- u32 temp;
-
- temp = ipic_read(ipic->regs, IPIC_SERMR);
- temp &= (1 << (31 - mcp_irq));
- ipic_write(ipic->regs, IPIC_SERMR, temp);
-}
-
-u32 ipic_get_mcp_status(void)
-{
- return ipic_read(primary_ipic->regs, IPIC_SERMR);
-}
-
-void ipic_clear_mcp_status(u32 mask)
-{
- ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
-}
-
-/* Return an interrupt vector or -1 if no interrupt is pending. */
-int ipic_get_irq(struct pt_regs *regs)
-{
- int irq;
-
- irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f;
-
- if (irq == 0) /* 0 --> no irq is pending */
- irq = -1;
-
- return irq;
-}
-
-static struct sysdev_class ipic_sysclass = {
- set_kset_name("ipic"),
-};
-
-static struct sys_device device_ipic = {
- .id = 0,
- .cls = &ipic_sysclass,
-};
-
-static int __init init_ipic_sysfs(void)
-{
- int rc;
-
- if (!primary_ipic->regs)
- return -ENODEV;
- printk(KERN_DEBUG "Registering ipic with sysfs...\n");
-
- rc = sysdev_class_register(&ipic_sysclass);
- if (rc) {
- printk(KERN_ERR "Failed registering ipic sys class\n");
- return -ENODEV;
- }
- rc = sysdev_register(&device_ipic);
- if (rc) {
- printk(KERN_ERR "Failed registering ipic sys device\n");
- return -ENODEV;
- }
- return 0;
-}
-
-subsys_initcall(init_ipic_sysfs);
diff --git a/arch/ppc/syslib/ipic.h b/arch/ppc/syslib/ipic.h
deleted file mode 100644
index a7ce7da..0000000
--- a/arch/ppc/syslib/ipic.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * arch/ppc/kernel/ipic.h
- *
- * IPIC private definitions and structure.
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2005 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#ifndef __IPIC_H__
-#define __IPIC_H__
-
-#include <asm/ipic.h>
-
-#define MPC83xx_IPIC_SIZE (0x00100)
-
-/* System Global Interrupt Configuration Register */
-#define SICFR_IPSA 0x00010000
-#define SICFR_IPSD 0x00080000
-#define SICFR_MPSA 0x00200000
-#define SICFR_MPSB 0x00400000
-
-/* System External Interrupt Mask Register */
-#define SEMSR_SIRQ0 0x00008000
-
-/* System Error Control Register */
-#define SERCR_MCPR 0x00000001
-
-struct ipic {
- volatile u32 __iomem *regs;
- unsigned int irq_offset;
-};
-
-struct ipic_info {
- u8 pend; /* pending register offset from base */
- u8 mask; /* mask register offset from base */
- u8 prio; /* priority register offset from base */
- u8 force; /* force register offset from base */
- u8 bit; /* register bit position (as per doc)
- bit mask = 1 << (31 - bit) */
- u8 prio_mask; /* priority mask value */
-};
-
-#endif /* __IPIC_H__ */
diff --git a/include/asm-powerpc/ipic.h b/include/asm-powerpc/ipic.h
new file mode 100644
index 0000000..0fe396a
--- /dev/null
+++ b/include/asm-powerpc/ipic.h
@@ -0,0 +1,85 @@
+/*
+ * include/asm-ppc/ipic.h
+ *
+ * IPIC external definitions and structure.
+ *
+ * Maintainer: Kumar Gala <galak@kernel.crashing.org>
+ *
+ * Copyright 2005 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_IPIC_H__
+#define __ASM_IPIC_H__
+
+#include <linux/irq.h>
+
+/* Flags when we init the IPIC */
+#define IPIC_SPREADMODE_GRP_A 0x00000001
+#define IPIC_SPREADMODE_GRP_D 0x00000002
+#define IPIC_SPREADMODE_MIX_A 0x00000004
+#define IPIC_SPREADMODE_MIX_B 0x00000008
+#define IPIC_DISABLE_MCP_OUT 0x00000010
+#define IPIC_IRQ0_MCP 0x00000020
+
+/* IPIC registers offsets */
+#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
+#define IPIC_SIVCR 0x04 /* System Global Interrupt Vector Register */
+#define IPIC_SIPNR_H 0x08 /* System Internal Interrupt Pending Register (HIGH) */
+#define IPIC_SIPNR_L 0x0C /* System Internal Interrupt Pending Register (LOW) */
+#define IPIC_SIPRR_A 0x10 /* System Internal Interrupt group A Priority Register */
+#define IPIC_SIPRR_B 0x14 /* System Internal Interrupt group B Priority Register */
+#define IPIC_SIPRR_C 0x18 /* System Internal Interrupt group C Priority Register */
+#define IPIC_SIPRR_D 0x1C /* System Internal Interrupt group D Priority Register */
+#define IPIC_SIMSR_H 0x20 /* System Internal Interrupt Mask Register (HIGH) */
+#define IPIC_SIMSR_L 0x24 /* System Internal Interrupt Mask Register (LOW) */
+#define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */
+#define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */
+#define IPIC_SMPRR_A 0x30 /* System Mixed Interrupt group A Priority Register */
+#define IPIC_SMPRR_B 0x34 /* System Mixed Interrupt group B Priority Register */
+#define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */
+#define IPIC_SECNR 0x3C /* System External Interrupt Control Register */
+#define IPIC_SERSR 0x40 /* System Error Status Register */
+#define IPIC_SERMR 0x44 /* System Error Mask Register */
+#define IPIC_SERCR 0x48 /* System Error Control Register */
+#define IPIC_SIFCR_H 0x50 /* System Internal Interrupt Force Register (HIGH) */
+#define IPIC_SIFCR_L 0x54 /* System Internal Interrupt Force Register (LOW) */
+#define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */
+#define IPIC_SERFR 0x5C /* System Error Force Register */
+#define IPIC_SCVCR 0x60 /* System Critical Interrupt Vector Register */
+#define IPIC_SMVCR 0x64 /* System Management Interrupt Vector Register */
+
+enum ipic_prio_grp {
+ IPIC_INT_GRP_A = IPIC_SIPRR_A,
+ IPIC_INT_GRP_D = IPIC_SIPRR_D,
+ IPIC_MIX_GRP_A = IPIC_SMPRR_A,
+ IPIC_MIX_GRP_B = IPIC_SMPRR_B,
+};
+
+enum ipic_mcp_irq {
+ IPIC_MCP_IRQ0 = 0,
+ IPIC_MCP_WDT = 1,
+ IPIC_MCP_SBA = 2,
+ IPIC_MCP_PCI1 = 5,
+ IPIC_MCP_PCI2 = 6,
+ IPIC_MCP_MU = 7,
+};
+
+extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
+ unsigned int irq_offset,
+ unsigned char *senses, unsigned int senses_count);
+extern int ipic_set_priority(unsigned int irq, unsigned int priority);
+extern void ipic_set_highest_priority(unsigned int irq);
+extern void ipic_set_default_priority(void);
+extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
+extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
+extern u32 ipic_get_mcp_status(void);
+extern void ipic_clear_mcp_status(u32 mask);
+extern int ipic_get_irq(struct pt_regs *regs);
+
+#endif /* __ASM_IPIC_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ipic.h b/include/asm-ppc/ipic.h
deleted file mode 100644
index 0fe396a..0000000
--- a/include/asm-ppc/ipic.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * include/asm-ppc/ipic.h
- *
- * IPIC external definitions and structure.
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2005 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_IPIC_H__
-#define __ASM_IPIC_H__
-
-#include <linux/irq.h>
-
-/* Flags when we init the IPIC */
-#define IPIC_SPREADMODE_GRP_A 0x00000001
-#define IPIC_SPREADMODE_GRP_D 0x00000002
-#define IPIC_SPREADMODE_MIX_A 0x00000004
-#define IPIC_SPREADMODE_MIX_B 0x00000008
-#define IPIC_DISABLE_MCP_OUT 0x00000010
-#define IPIC_IRQ0_MCP 0x00000020
-
-/* IPIC registers offsets */
-#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
-#define IPIC_SIVCR 0x04 /* System Global Interrupt Vector Register */
-#define IPIC_SIPNR_H 0x08 /* System Internal Interrupt Pending Register (HIGH) */
-#define IPIC_SIPNR_L 0x0C /* System Internal Interrupt Pending Register (LOW) */
-#define IPIC_SIPRR_A 0x10 /* System Internal Interrupt group A Priority Register */
-#define IPIC_SIPRR_B 0x14 /* System Internal Interrupt group B Priority Register */
-#define IPIC_SIPRR_C 0x18 /* System Internal Interrupt group C Priority Register */
-#define IPIC_SIPRR_D 0x1C /* System Internal Interrupt group D Priority Register */
-#define IPIC_SIMSR_H 0x20 /* System Internal Interrupt Mask Register (HIGH) */
-#define IPIC_SIMSR_L 0x24 /* System Internal Interrupt Mask Register (LOW) */
-#define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */
-#define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */
-#define IPIC_SMPRR_A 0x30 /* System Mixed Interrupt group A Priority Register */
-#define IPIC_SMPRR_B 0x34 /* System Mixed Interrupt group B Priority Register */
-#define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */
-#define IPIC_SECNR 0x3C /* System External Interrupt Control Register */
-#define IPIC_SERSR 0x40 /* System Error Status Register */
-#define IPIC_SERMR 0x44 /* System Error Mask Register */
-#define IPIC_SERCR 0x48 /* System Error Control Register */
-#define IPIC_SIFCR_H 0x50 /* System Internal Interrupt Force Register (HIGH) */
-#define IPIC_SIFCR_L 0x54 /* System Internal Interrupt Force Register (LOW) */
-#define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */
-#define IPIC_SERFR 0x5C /* System Error Force Register */
-#define IPIC_SCVCR 0x60 /* System Critical Interrupt Vector Register */
-#define IPIC_SMVCR 0x64 /* System Management Interrupt Vector Register */
-
-enum ipic_prio_grp {
- IPIC_INT_GRP_A = IPIC_SIPRR_A,
- IPIC_INT_GRP_D = IPIC_SIPRR_D,
- IPIC_MIX_GRP_A = IPIC_SMPRR_A,
- IPIC_MIX_GRP_B = IPIC_SMPRR_B,
-};
-
-enum ipic_mcp_irq {
- IPIC_MCP_IRQ0 = 0,
- IPIC_MCP_WDT = 1,
- IPIC_MCP_SBA = 2,
- IPIC_MCP_PCI1 = 5,
- IPIC_MCP_PCI2 = 6,
- IPIC_MCP_MU = 7,
-};
-
-extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
- unsigned int irq_offset,
- unsigned char *senses, unsigned int senses_count);
-extern int ipic_set_priority(unsigned int irq, unsigned int priority);
-extern void ipic_set_highest_priority(unsigned int irq);
-extern void ipic_set_default_priority(void);
-extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
-extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
-extern u32 ipic_get_mcp_status(void);
-extern void ipic_clear_mcp_status(u32 mask);
-extern int ipic_get_irq(struct pt_regs *regs);
-
-#endif /* __ASM_IPIC_H__ */
-#endif /* __KERNEL__ */
^ permalink raw reply related
* MPC8260 fcc_enet transmit timed out
From: hubert loewenguth @ 2005-11-14 17:34 UTC (permalink / raw)
To: linuxppc-embedded
Hello to the community
After having searched more than a week to correct my problem, I have
finally decided to try to find some help :
- I have a board with a MPC8260 (HIP 3 C.2), with three PHY chipset :
LXT971A from intel
- The MII lines MDC and MDIO are present, but I have no PHY interrupt line
=> so I have to configure my PHY and the fcc_enet.c drivers to be in
half-duplex mode
- I use the 2.4.20 linux kernel
Every thing works very fine, everything is ok and the TCP/IP ethernet
communication works fine (telnet, ftp, udp ....)
BUT if I plug / unplug the ethernet link numerous times during TCP
traffic,the fcc_enet.c driver enter in an "infernal loop" and prints
continuously :
/NETDEV WATCHDOG: eth0: transmit timed out
eth0: transmit timed out.
Ring data dump: cur_tx c02b60b8 (full) cur_rx c02b7098.
Tx @base c02b60a0 :
1c00 05ea 014f786a
1c00 05ea 013ce06a
1c00 05ea 013ce86a
........
/
And never exit from this infernal loop.
I have found some personns in this mailling list who has encounter a
problem wich seems similar:
http://ozlabs.org/pipermail/linuxppc-embedded/2005-January/016539.html
http://ozlabs.org/pipermail/linuxppc-embedded/2001-December/005714.html
I really don't find what can be the origin of my problem:
- I don't succeed to reproduce it in full duplex mode (using a full
duplex link and configuring the drivers and the PHY in full duplex)
- I have verified the pin configuration numerous times, the routing of
clock signals also....
- I have not applied a MPC8260 microcode patch, I will try it but I
don't think there is a patch wich correct it
Is there any personn who has already encounter this matter ?
Thanks to the community for any help
^ permalink raw reply
* 2.6.15-rc1 fails to boot on eMac
From: Mikael Pettersson @ 2005-11-14 16:05 UTC (permalink / raw)
To: paulus, benh; +Cc: linuxppc-dev, linux-kernel
Linux kernel 2.6.15-rc1 (vanilla, not patched, compiled with
gcc-3.4.4) refuses to boot on my Apple eMac (1.25GHz G4). After
yaboot has loaded the kernel the output on the console is:
===snip===
Welcome to Linux, kernel 2.6.15-rc1
linked at : 0xc0000000
frame buffer at : 0x9c008000 (phys), 0xd0008000 (log)
klimit : 0xc0242858
MSR : 0x00003030
HID0 : 0x8410c09c
===snip===
and then the machine hangs. Normally the next line would be
"pmac_init(): exit", but 2.6.15-rc1 never gets that far.
2.6.15-rc1 does boot OK on my Beige G3 (w/ G4 upgrade card).
The build was done on a ppc32 host, so the new-fangled arch/powerpc/
shouldn't be involved except when there's new references to it from
arch/ppc/.
My eMac's .config is below. It's a 'make oldconfig' starting from
my working 2.6.14 .config, plus I've disabled a bunch of stuff that
shouldn't be necessary for booting.
/Mikael
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.15-rc1
# Mon Nov 14 16:38:16 2005
#
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_GENERIC_NVRAM=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
#
# Code maturity level options
#
# CONFIG_EXPERIMENTAL is not set
CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
CONFIG_HOTPLUG=y
# CONFIG_KOBJECT_UEVENT is not set
# CONFIG_IKCONFIG is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_EMBEDDED=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SHMEM=y
CONFIG_CC_ALIGN_FUNCTIONS=0
CONFIG_CC_ALIGN_LABELS=0
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# Block layer
#
# CONFIG_LBD is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# Processor
#
CONFIG_6xx=y
# CONFIG_40x is not set
# CONFIG_44x is not set
# CONFIG_POWER3 is not set
# CONFIG_POWER4 is not set
# CONFIG_8xx is not set
# CONFIG_E200 is not set
# CONFIG_E500 is not set
CONFIG_PPC_FPU=y
CONFIG_ALTIVEC=y
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
# CONFIG_PPC601_SYNC_FIX is not set
# CONFIG_WANT_EARLY_SERIAL is not set
CONFIG_PPC_STD_MMU=y
#
# Platform options
#
CONFIG_PPC_MULTIPLATFORM=y
# CONFIG_APUS is not set
# CONFIG_KATANA is not set
# CONFIG_WILLOW is not set
# CONFIG_CPCI690 is not set
# CONFIG_POWERPMC250 is not set
# CONFIG_CHESTNUT is not set
# CONFIG_SPRUCE is not set
# CONFIG_HDPU is not set
# CONFIG_EV64260 is not set
# CONFIG_LOPEC is not set
# CONFIG_MVME5100 is not set
# CONFIG_PPLUS is not set
# CONFIG_PRPMC750 is not set
# CONFIG_PRPMC800 is not set
# CONFIG_SANDPOINT is not set
# CONFIG_RADSTONE_PPC7D is not set
# CONFIG_PAL4 is not set
# CONFIG_GEMINI is not set
# CONFIG_EST8260 is not set
# CONFIG_SBC82xx is not set
# CONFIG_SBS8260 is not set
# CONFIG_RPX8260 is not set
# CONFIG_TQM8260 is not set
# CONFIG_ADS8272 is not set
# CONFIG_PQ2FADS is not set
# CONFIG_LITE5200 is not set
# CONFIG_MPC834x_SYS is not set
# CONFIG_EV64360 is not set
CONFIG_PPC_CHRP=y
CONFIG_PPC_PMAC=y
CONFIG_PPC_PREP=y
CONFIG_PPC_OF=y
CONFIG_PPCBUG_NVRAM=y
# CONFIG_SMP is not set
# CONFIG_HIGHMEM is not set
CONFIG_HZ_100=y
# CONFIG_HZ_250 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_PROC_DEVICETREE=y
# CONFIG_PREP_RESIDUAL is not set
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_PM is not set
# CONFIG_SOFTWARE_SUSPEND is not set
# CONFIG_SECCOMP is not set
CONFIG_ISA_DMA_API=y
#
# Bus options
#
# CONFIG_ISA is not set
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PPC_I8259=y
CONFIG_PPC_INDIRECT_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PCI_LEGACY_PROC is not set
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# Advanced setup
#
# CONFIG_ADVANCED_OPTIONS is not set
#
# Default settings for advanced configuration options are used
#
CONFIG_HIGHMEM_START=0xfe000000
CONFIG_LOWMEM_SIZE=0x30000000
CONFIG_KERNEL_START=0xc0000000
CONFIG_TASK_SIZE=0x80000000
CONFIG_BOOT_LOAD=0x00800000
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_BIC=y
# CONFIG_IPV6 is not set
# CONFIG_NETFILTER is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
# CONFIG_NET_CLS_ROUTE is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_IEEE80211 is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_MAC_FLOPPY is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_RAM is not set
CONFIG_BLK_DEV_RAM_COUNT=16
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
#
# ATA/ATAPI/MFM/RLL support
#
CONFIG_IDE=y
CONFIG_BLK_DEV_IDE=y
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_IDE_SATA is not set
CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_BLK_DEV_IDECD is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_IDE_TASK_IOCTL is not set
#
# IDE chipset support/bugfixes
#
# CONFIG_IDE_GENERIC is not set
CONFIG_BLK_DEV_IDEPCI=y
# CONFIG_IDEPCI_SHARE_IRQ is not set
# CONFIG_BLK_DEV_OFFBOARD is not set
# CONFIG_BLK_DEV_GENERIC is not set
# CONFIG_BLK_DEV_SL82C105 is not set
CONFIG_BLK_DEV_IDEDMA_PCI=y
# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
CONFIG_IDEDMA_PCI_AUTO=y
# CONFIG_IDEDMA_ONLYDISK is not set
# CONFIG_BLK_DEV_AEC62XX is not set
# CONFIG_BLK_DEV_ALI15X3 is not set
# CONFIG_BLK_DEV_AMD74XX is not set
# CONFIG_BLK_DEV_CMD64X is not set
# CONFIG_BLK_DEV_TRIFLEX is not set
# CONFIG_BLK_DEV_CY82C693 is not set
# CONFIG_BLK_DEV_CS5530 is not set
# CONFIG_BLK_DEV_HPT34X is not set
# CONFIG_BLK_DEV_HPT366 is not set
# CONFIG_BLK_DEV_SC1200 is not set
# CONFIG_BLK_DEV_PIIX is not set
# CONFIG_BLK_DEV_IT821X is not set
# CONFIG_BLK_DEV_NS87415 is not set
# CONFIG_BLK_DEV_PDC202XX_OLD is not set
# CONFIG_BLK_DEV_PDC202XX_NEW is not set
# CONFIG_BLK_DEV_SVWKS is not set
# CONFIG_BLK_DEV_SIIMAGE is not set
# CONFIG_BLK_DEV_SLC90E66 is not set
# CONFIG_BLK_DEV_TRM290 is not set
# CONFIG_BLK_DEV_VIA82CXXX is not set
CONFIG_BLK_DEV_IDE_PMAC=y
CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
CONFIG_BLK_DEV_IDEDMA_PMAC=y
# CONFIG_BLK_DEV_IDE_PMAC_BLINK is not set
# CONFIG_IDE_ARM is not set
CONFIG_BLK_DEV_IDEDMA=y
# CONFIG_IDEDMA_IVB is not set
CONFIG_IDEDMA_AUTO=y
# CONFIG_BLK_DEV_HD is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Macintosh device drivers
#
# CONFIG_ADB is not set
# CONFIG_ADB_CUDA is not set
CONFIG_ADB_PMU=y
# CONFIG_PMAC_MEDIABAY is not set
# CONFIG_PMAC_BACKLIGHT is not set
# CONFIG_THERM_WINDTUNNEL is not set
# CONFIG_THERM_ADT746X is not set
# CONFIG_WINDFARM is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
#
# PHY device support
#
# CONFIG_PHYLIB is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_MII is not set
# CONFIG_MACE is not set
# CONFIG_BMAC is not set
# CONFIG_HAPPYMEAL is not set
CONFIG_SUNGEM=y
# CONFIG_CASSINI is not set
# CONFIG_NET_VENDOR_3COM is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_NET_PCI is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2 is not set
# CONFIG_MV643XX_ETH is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_CHELSIO_T1 is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
#
# Token Ring devices
#
# CONFIG_TR is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
CONFIG_INPUT_MOUSE=y
# CONFIG_MOUSE_PS2 is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_PMACZILOG is not set
# CONFIG_SERIAL_JSM is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
CONFIG_NVRAM=y
CONFIG_GEN_RTC=y
# CONFIG_GEN_RTC_X is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
#
# I2C Algorithms
#
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_I810 is not set
# CONFIG_I2C_PIIX4 is not set
CONFIG_I2C_KEYWEST=y
# CONFIG_I2C_MPC is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_PROSAVAGE is not set
# CONFIG_SCx200_ACB is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIAPRO is not set
# CONFIG_I2C_VOODOO3 is not set
# CONFIG_I2C_PCA_ISA is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_SENSORS_M41T00 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
# CONFIG_HWMON is not set
# CONFIG_HWMON_VID is not set
#
# Misc devices
#
#
# Multimedia Capabilities Port drivers
#
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# Graphics support
#
CONFIG_FB=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_MACMODES=y
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
CONFIG_FB_OF=y
# CONFIG_FB_CONTROL is not set
# CONFIG_FB_PLATINUM is not set
# CONFIG_FB_VALKYRIE is not set
# CONFIG_FB_CT65550 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_VGA16 is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON_OLD is not set
CONFIG_FB_RADEON=y
CONFIG_FB_RADEON_I2C=y
# CONFIG_FB_RADEON_DEBUG is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_CYBLA is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_VIRTUAL is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
#
# Logo configuration
#
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
#
# InfiniBand support
#
# CONFIG_INFINIBAND is not set
#
# SN Devices
#
#
# File systems
#
# CONFIG_EXT2_FS is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_DNOTIFY is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_RELAYFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_HFSPLUS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
# CONFIG_NFS_FS is not set
# CONFIG_NFSD is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
CONFIG_MAC_PARTITION=y
# CONFIG_MSDOS_PARTITION is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Library routines
#
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BOOTX_TEXT=y
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
# Hardware crypto devices
#
^ permalink raw reply
* [PLEASE REVIEW] ppc32 8xx: core PRxK board family support
From: Marcelo Tosatti @ 2005-11-14 12:45 UTC (permalink / raw)
To: linux-ppc-embedded, linux-ppc-dev
Hi,
The following patch adds support for Cyclades's PRxK boards (based on
the 855T processor). These boards are used to build dedicated HW such as
console servers and KVM managers. There are about 15 board configurations
supported.
We would like to merge the support in to the mainline kernel. This would
facilitate our maintenance burden and also allow users to compile their
own kernels more easily.
Any comments (including coding style ones) are welcome.
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/Kconfig linux-2.6.14-rc4/arch/ppc/Kconfig
--- linux-2.6.14-rc4.orig/arch/ppc/Kconfig 2005-10-18 16:59:34.000000000 -0500
+++ linux-2.6.14-rc4/arch/ppc/Kconfig 2005-10-24 12:45:43.000000000 -0500
@@ -455,6 +455,12 @@ config TQM860L
<http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
<http://www.denx.de/embedded-ppc-en.html>.
+config PRxK
+ bool "PRxK"
+ help
+ Say Y here to support Cyclades embedded PowerPC family: console
+ servers, kvm managers, routers, etc.
+
config FPS850L
bool "FPS850L"
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/boot/include/cyc_banner.h linux-2.6.14-rc4/arch/ppc/boot/include/cyc_banner.h
--- linux-2.6.14-rc4.orig/arch/ppc/boot/include/cyc_banner.h 1969-12-31 18:00:00.000000000 -0600
+++ linux-2.6.14-rc4/arch/ppc/boot/include/cyc_banner.h 2005-10-25 07:01:57.000000000 -0500
@@ -0,0 +1,74 @@
+static char PROD_LINE0[] = "Cyclades";
+static char PROD_NAME0[] = " TS";
+
+static char PROD_LINE1[] = "AlterPath";
+static char PROD_NAME1[] = " CS";
+
+#define PROD_LINE3 PROD_LINE1
+static char PROD_NAME3[] = " ACS";
+
+#define PROD_LINE2 PROD_LINE1
+static char PROD_NAME2[] = " SM";
+
+#define PROD_LINE4 PROD_LINE1
+static char PROD_NAME4[] = " KVM";
+
+#define PROD_LINE5 PROD_LINE1
+static char PROD_NAME5[] = " KVM/net";
+
+#define PROD_LINE6 PROD_LINE1
+static char PROD_NAME6[] = " ONS";
+
+#define PROD_LINE7 PROD_LINE1
+static char PROD_NAME7[] = " KVM/net Plus";
+
+static char CYCLADES_TXT[] = "Cyclades";
+static char CYCLADES_BANNER[] = "Linux ";
+static char CYCLADES_WHAT[] = "@(#)V_2.6.0m (Sep/05/2005) #70";
+
+#define CYCLADES_VERSION (CYCLADES_WHAT+4)
+
+static char machine_txt[36][8] = {
+ "PR3000",
+ "PR+000",
+ "PR=000",
+ "PR1000",
+ "TS1000",
+ "TS2000",
+ "TS400",
+ "TS800",
+ "TS3000",
+ "Tx1000",
+ "Tx2000",
+ "PL1000",
+ "TS100",
+ "NL1000",
+ "ACS16",
+ "ACS32",
+ "SM100",
+ "PR3500",
+ "TS110",
+ "ACS48",
+ "ACS4",
+ "ACS8",
+ "ACS1",
+ "PR3000",
+ "KVM16",
+ "KVM32",
+ "KVMN16",
+ "KVMN32",
+ "ONS441",
+ "ONS481",
+ "ONS841",
+ "ONS881",
+ "ONS442",
+ "ONS482",
+ "ONS842",
+ "ONS882"
+};
+
+static char onsite_str[] = "OnSite";
+static char acs_str[] = "ACS";
+static char kvm_str[] = "KVM";
+static char kvmnet_str[] = "KVM/NET";
+static char kvmplus_str[] = "KVM/PLUS";
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/boot/include/cyc_config.h linux-2.6.14-rc4/arch/ppc/boot/include/cyc_config.h
--- linux-2.6.14-rc4.orig/arch/ppc/boot/include/cyc_config.h 1969-12-31 18:00:00.000000000 -0600
+++ linux-2.6.14-rc4/arch/ppc/boot/include/cyc_config.h 2005-10-25 12:19:43.000000000 -0500
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 1996 - CYCLADES Corporation.
+ *
+ * V_1.0.0 08/25/00 Edson A. Seabra Module creation.
+ */
+
+#define IP_ALEN 4
+#define EP_ALEN 6
+#define PATH_LEN 40
+#define FLASH_SIGN_SIZE 8
+
+//XXX: remove? Its unused.
+#if 0
+struct type0000 {
+ unsigned char flash_sign[FLASH_SIGN_SIZE]; /* mark initialized CMOS */
+ unsigned char version; /* Configure vector version */
+ unsigned char routing_protocol; /* RIP, OSPF, etc */
+ unsigned char save_sw; /* TRUE : the RTBOOT must be saved into flash */
+};
+#endif
+
+struct hw_setup {
+ unsigned char boot_option;
+ unsigned char tftp_path[PATH_LEN]; /* path and filename for tftp boot */
+ unsigned char enable_wdt;
+ unsigned char op_code_crc;
+ unsigned char mem_test;
+ //[GB]May/06/05 Ethernet Receive Rate Limit
+ // unsigned char reserved1[4];
+ unsigned int ibytesec;
+/* maximum allowable bytes per second, when checking enabled */
+ unsigned short max_int_work;
+ unsigned char physical_addr[EP_ALEN];
+ unsigned char itf_ip_addr[IP_ALEN];
+ unsigned char itf_subnet_mask[IP_ALEN];
+ unsigned char console_speed;
+ unsigned char lcd_reboot;
+ unsigned char cpu_utilization;
+ unsigned char mii_operation;
+};
+
+struct boot_mask {
+ unsigned char boot_type; /* It can assume Bootp, TFTP or Both */
+ unsigned char intfc; /* Interface where the boot will happen */
+ unsigned char bootserver[IP_ALEN]; /* Server IP address */
+};
+
+struct om_info {
+ unsigned char mac_addr[6];
+ unsigned char banner[100];
+ unsigned char reserved[140];
+};
+
+#define TYPE0000 0
+#define TYPE0015 15
+#define TYPE0068 68
+#define TYPE9000 9000
+
+//[RK]Jun/14/05 - back port from 2.4 kernel
+#define OM_ADDRESS (1024 - 6 - sizeof(struct om_info))
+
+#define OM_ADDRESS1 (0x10000L - 1024 + OM_ADDRESS)
+#define OM_ADDRESS2 (0x20000L - 1024 + OM_ADDRESS)
+
+#define CNF_ADDRESS1 0x30000
+#define CNF_ADDRESS2 0x20000
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/boot/simple/embed_config.c linux-2.6.14-rc4/arch/ppc/boot/simple/embed_config.c
--- linux-2.6.14-rc4.orig/arch/ppc/boot/simple/embed_config.c 2005-10-18 16:59:34.000000000 -0500
+++ linux-2.6.14-rc4/arch/ppc/boot/simple/embed_config.c 2005-10-25 13:55:04.000000000 -0500
@@ -334,6 +334,298 @@ embed_config(bd_t **bdp)
}
#endif /* RPXLITE || RPXCLASSIC */
+#ifdef CONFIG_PRxK
+
+/* Build a board information structure for the PRXK.
+ */
+
+#include <asm/uaccess.h>
+#include <asm/commproc.h>
+#include <platforms/cyc_flash.h>
+#include "cyc_banner.h"
+#include "cyc_config.h"
+#include "nonstdio.h"
+
+static void reset_ports(int board)
+{
+ volatile immap_t *pm = (volatile immap_t *)IMAP_ADDR;
+
+ if (board == BOARD_ACS48 ||
+ board == BOARD_ACS32 ||
+ board == BOARD_ACS16 ||
+ board == BOARD_ACS8 ||
+ board == BOARD_ACS4) {
+ pm->im_ioport.iop_padir |= 0xAFFF;
+ pm->im_ioport.iop_papar &= ~0xEFFF;
+ pm->im_ioport.iop_paodr &= ~0xEFFF;
+ pm->im_ioport.iop_padat &= ~0xEFFF;
+
+ pm->im_cpm.cp_pbdir &= 0x11F00;
+ pm->im_cpm.cp_pbodr &= ~0x11F00;
+ pm->im_cpm.cp_pbpar &= ~0x11F00;
+
+ pm->im_ioport.iop_pcdir &= 0x07F8;
+ pm->im_ioport.iop_pcpar &= ~0x07F8;
+ pm->im_ioport.iop_pcdat &= ~0x07F8;
+ return;
+ }
+
+ if (board == BOARD_ACS1 || board == BOARD_KVM16 ||
+ board == BOARD_KVM32) {
+ pm->im_ioport.iop_padir |= 0xAFFC;
+ pm->im_ioport.iop_papar &= ~0xEFFC;
+ pm->im_ioport.iop_paodr &= ~0xEFFC;
+ pm->im_ioport.iop_padat &= ~0xEFFC;
+
+ pm->im_cpm.cp_pbdir |= 0x17F30;
+ pm->im_cpm.cp_pbodr |= 0x7C30;
+ pm->im_cpm.cp_pbpar |= 0x1030;
+ pm->im_cpm.cp_pbdat |= 0x0001;
+ pm->im_cpm.cp_pbdat &= ~0x1800;
+
+ pm->im_ioport.iop_pcdir |= 0x07C8;
+ pm->im_ioport.iop_pcpar &= ~0x0230;
+ pm->im_ioport.iop_pcso |= 0x0030;
+ return;
+ }
+
+ pm->im_ioport.iop_padir |= 0xAFFF;
+ pm->im_ioport.iop_papar &= ~0xAFFF;
+ pm->im_ioport.iop_paodr &= ~0xAFFF;
+ pm->im_ioport.iop_padat &= ~0xAFFF;
+
+ pm->im_cpm.cp_pbdir &= ~0x1C3E;
+ pm->im_cpm.cp_pbodr &= ~0x1C3E;
+ pm->im_cpm.cp_pbpar &= ~0x1C3E;
+
+ pm->im_ioport.iop_pcdir &= ~0x0728;
+ pm->im_ioport.iop_pcpar &= ~0x0728;
+ pm->im_ioport.iop_pcdat &= ~0x0728;
+
+ return;
+}
+
+static unsigned short calc_crc(unsigned long byte_n, unsigned short crc, char *buffer)
+{
+ int j;
+
+ while (byte_n--) {
+ crc = (((crc >> 8) ^ *buffer++) << 8) | (0xFF & crc) ;
+ for(j = 0; j < 8; j++) {
+ if (crc & 0x8000) {
+ crc <<= 1;
+ crc ^= 0x1021;
+ } else {
+ crc <<= 1;
+ }
+ }
+ }
+ return(crc);
+}
+
+static unsigned char *get_config_vector(unsigned char *pflash, int type, int tries)
+{
+ struct flash_config_vector_header *p;
+ int cnt = 0;
+
+ while(cnt++ < tries) {
+ p = (struct flash_config_vector_header *)pflash;
+
+ if (p->type == 9999) {
+ break;
+ }
+ if ((p->type > 200 && p->type != 9000) || p->size > 10000) {
+ break;
+ }
+ if (p->crc != calc_crc(p->size, 0, p->data)) {
+ break;
+ }
+ if (p->type == type) {
+ return(p->data);
+ }
+ pflash += p->size + 6;
+ }
+ return(NULL);
+}
+
+struct cyc_board_info {
+ int board_id;
+ char *prod_line;
+ char *prod_name;
+ char *card_name;
+ unsigned short num_portsS;
+ unsigned short num_portsK;
+ unsigned short num_portsA;
+ unsigned short num_portsM;
+};
+
+static struct cyc_board_info cyc_boards[] = {
+/* ACS series */
+{ .board_id = BOARD_ACS1, .prod_line = PROD_LINE3, .prod_name = PROD_NAME3,
+ .card_name = acs_str, .num_portsS = 1, .num_portsM = 2 },
+{ .board_id = BOARD_ACS4, .prod_line = PROD_LINE3, .prod_name = PROD_NAME3,
+ .card_name = acs_str, .num_portsS = 4, .num_portsM = 2 },
+{ .board_id = BOARD_ACS8, .prod_line = PROD_LINE3, .prod_name = PROD_NAME3,
+ .card_name = acs_str, .num_portsS = 8, .num_portsM = 2 },
+{ .board_id = BOARD_ACS16, .prod_line = PROD_LINE3, .prod_name = PROD_NAME3,
+ .card_name = acs_str, .num_portsS = 16, .num_portsM = 2 },
+{ .board_id = BOARD_ACS32, .prod_line = PROD_LINE3, .prod_name = PROD_NAME3,
+ .card_name = acs_str, .num_portsS = 32, .num_portsM = 2 },
+/* OnSite series */
+{ .board_id = BOARD_ONS441, .prod_line = PROD_LINE6, .prod_name = PROD_NAME6,
+ .card_name = onsite_str, .num_portsS = 4, .num_portsM = 2, .num_portsK = 4,
+ .num_portsA = 3},
+{ .board_id = BOARD_ONS442, .prod_line = PROD_LINE6, .prod_name = PROD_NAME6,
+ .card_name = onsite_str, .num_portsS = 4, .num_portsM = 2, .num_portsK = 4,
+ .num_portsA = 3},
+{ .board_id = BOARD_ONS481, .prod_line = PROD_LINE6, .prod_name = PROD_NAME6,
+ .card_name = onsite_str, .num_portsS = 4, .num_portsM = 2, .num_portsK = 8,
+ .num_portsA = 3},
+{ .board_id = BOARD_ONS482, .prod_line = PROD_LINE6, .prod_name = PROD_NAME6,
+ .card_name = onsite_str, .num_portsS = 4, .num_portsM = 2, .num_portsK = 8,
+ .num_portsA = 3},
+{ .board_id = BOARD_ONS841, .prod_line = PROD_LINE6, .prod_name = PROD_NAME6,
+ .card_name = onsite_str, .num_portsS = 8, .num_portsM = 2, .num_portsK = 4,
+ .num_portsA = 3},
+{ .board_id = BOARD_ONS842, .prod_line = PROD_LINE6, .prod_name = PROD_NAME6,
+ .card_name = onsite_str, .num_portsS = 8, .num_portsM = 2, .num_portsK = 4,
+ .num_portsA = 3},
+{ .board_id = BOARD_ONS881, .prod_line = PROD_LINE6, .prod_name = PROD_NAME6,
+ .card_name = onsite_str, .num_portsS = 8, .num_portsM = 2, .num_portsK = 8,
+ .num_portsA = 3},
+{ .board_id = BOARD_ONS882, .prod_line = PROD_LINE6, .prod_name = PROD_NAME6,
+ .card_name = onsite_str, .num_portsS = 8, .num_portsM = 2, .num_portsK = 8,
+ .num_portsA = 3},
+/* KVM series */
+{ .board_id = BOARD_KVM16, .prod_line = PROD_LINE4, .prod_name = PROD_NAME4,
+ .card_name = kvm_str, .num_portsA = 1 },
+{ .board_id = BOARD_KVM32, .prod_line = PROD_LINE4, .prod_name = PROD_NAME4,
+ .card_name = kvm_str, .num_portsA = 1 },
+/* KVM/NET series */
+{ .board_id = BOARD_KVMNET16,.prod_line = PROD_LINE5,.prod_name = PROD_NAME5,
+ .card_name = kvmnet_str, .num_portsA = 1 },
+{ .board_id = BOARD_KVMNET32,.prod_line = PROD_LINE5,.prod_name = PROD_NAME5,
+.card_name = kvmnet_str, .num_portsA = 1 },
+/* KVM/PLUS series */
+{ .board_id = BOARD_KVMP16,.prod_line = PROD_LINE5,.prod_name = PROD_NAME5,
+ .card_name = kvmnet_str, .num_portsA = 1 },
+{ .board_id = BOARD_KVMP32,.prod_line = PROD_LINE5,.prod_name = PROD_NAME5,
+ .card_name = kvmnet_str, .num_portsM = 2, .num_portsK = 16, .num_portsA = 2 }
+};
+
+static struct cyc_board_info *cget_board_info(int board_id)
+{
+ struct cyc_board_info *board = NULL;
+ int i;
+
+ for (i=0; i<ARRAY_SIZE(cyc_boards); i++) {
+ if (cyc_boards[i].board_id == board_id) {
+ board = &cyc_boards[i];
+ break;
+ }
+ }
+
+ if (board == NULL)
+ puts("PRxK: board_id does not match any known entry!");
+
+ return board;
+}
+
+/* Build a board information structure for the PRXK.
+ */
+void
+embed_config(bd_t **bdp)
+{
+ unsigned char *pflash, *pf;
+ struct prxk_boot_info *p = (struct prxk_boot_info *)0x00002000;
+ car8xx_t *pcar = &(((immap_t *)IMAP_ADDR)->im_clkrst);
+ struct hw_setup *pcnf;
+ struct om_info *p_om;
+ int speed[6] = {4800, 9600, 19200, 38400, 57600, 115200};
+ bd_t *bd;
+ struct cyc_board_info *cinfo;
+
+ bd = &bdinfo;
+ *bdp = bd;
+
+ memcpy(&bd->hw_info, p, sizeof(struct prxk_boot_info));
+
+ bd->bi_busfreq = ((pcar->car_plprcr >> 20) + 1) * 4; // 4 MHz crystal
+ bd->bi_intfreq = bd->bi_busfreq *= 1000000;
+
+ bd->bi_memsize = p->memory_detected;
+
+ pflash = (unsigned char *)FLASH_ADDR + CNF_ADDRESS1;
+ pf = (unsigned char *)OM_ADDRESS2 + FLASH_ADDR;
+
+ if ((pcnf = (struct hw_setup *)get_config_vector(pflash, TYPE0068, 1000))) {
+ bd->bi_baudrate = speed[pcnf->console_speed];
+ memcpy(bd->bi_enetaddr, pcnf->physical_addr, EP_ALEN);
+ bd->mii_operation = pcnf->mii_operation;
+ bd->max_int_work = pcnf->max_int_work;
+ //[GB]May/06/096 - Ethernet Receive Rate Limit
+ bd->ibytesec = pcnf->ibytesec;
+ } else {
+ bd->mii_operation = 0;
+ bd->bi_baudrate = 9600;
+ }
+
+ /* a value of 2 means WDT inactive */
+ switch (bd->hw_info.wdt_config) {
+ case 0:
+ case 1:
+ bd->wdt = 1;
+ break;
+ default:
+ bd->wdt = 0;
+ break;
+ }
+
+ p_om = (struct om_info *)get_config_vector(pf, TYPE9000, 1);
+
+ if (!bd->bi_enetaddr[1] && !bd->bi_enetaddr[2] && p_om) {
+ memcpy(bd->bi_enetaddr, p_om->mac_addr, EP_ALEN);
+ }
+
+ if (!bd->bi_enetaddr[1] && !bd->bi_enetaddr[2]) {
+ bd->bi_enetaddr[0] = 0x00;
+ bd->bi_enetaddr[1] = 0x60;
+ bd->bi_enetaddr[2] = 0x2e;
+ bd->bi_enetaddr[3] = 0x00;
+ bd->bi_enetaddr[4] = 0x00;
+ bd->bi_enetaddr[5] = 0x01;
+ }
+ cinfo = cget_board_info(p->board_type);
+ if (!cinfo)
+ puts("Cyclades: unknown board id");
+
+ memcpy(bd->cyc_version, CYCLADES_VERSION, sizeof(bd->cyc_version));
+ memcpy(bd->board_name, machine_txt[p->board_type], sizeof(bd->board_name));
+ memcpy(bd->card_name, "UNKNOWN", sizeof(bd->card_name));
+
+ memcpy(bd->prod_line, cinfo->prod_line, sizeof(bd->prod_line));
+ memcpy(bd->prod_name, cinfo->prod_name, sizeof(bd->prod_name));
+ memcpy(bd->vendor_name, CYCLADES_TXT, sizeof(bd->vendor_name));
+
+ bd->num_portsS = cinfo->num_portsS;
+ bd->num_portsA = cinfo->num_portsA;
+ bd->num_portsK = cinfo->num_portsK;
+ bd->num_portsM = cinfo->num_portsM;
+
+ switch(p->board_type) {
+ case BOARD_KVMNET16:
+ case BOARD_KVMNET32:
+ if (p->async_config == 1 || p->async_config == 2)
+ bd->num_portsK = 7;
+ else
+ bd->num_portsK = 6;
+ }
+
+ reset_ports(p->board_type);
+}
+
+#endif /* CONFIG_PRxK */
+
#ifdef CONFIG_BSEIP
/* Build a board information structure for the BSE ip-Engine.
* There is more to come since we will add some environment
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/boot/simple/head.S linux-2.6.14-rc4/arch/ppc/boot/simple/head.S
--- linux-2.6.14-rc4.orig/arch/ppc/boot/simple/head.S 2005-10-18 16:59:34.000000000 -0500
+++ linux-2.6.14-rc4/arch/ppc/boot/simple/head.S 2005-10-24 12:39:28.000000000 -0500
@@ -32,6 +32,17 @@
*
*/
+#ifdef CONFIG_PRxK
+ .globl start1
+start1: .long 0x00002120
+ .ascii "Entry Point\x00"
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+#endif
+
+
.globl start
start:
bl start_
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/configs/prxk_defconfig linux-2.6.14-rc4/arch/ppc/configs/prxk_defconfig
--- linux-2.6.14-rc4.orig/arch/ppc/configs/prxk_defconfig 1969-12-31 18:00:00.000000000 -0600
+++ linux-2.6.14-rc4/arch/ppc/configs/prxk_defconfig 2005-10-24 15:12:54.000000000 -0500
@@ -0,0 +1,756 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.9-rc1
+# Fri Sep 3 00:54:16 2004
+#
+CONFIG_MMU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_HOTPLUG=y
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODULE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+CONFIG_MODVERSIONS=y
+CONFIG_KMOD=y
+
+#
+# Processor
+#
+# CONFIG_6xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+CONFIG_8xx=y
+# CONFIG_E500 is not set
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_EMBEDDEDBOOT=y
+CONFIG_NOT_COHERENT_CACHE=y
+
+#
+# Platform options
+#
+# CONFIG_RPXLITE is not set
+# CONFIG_RPXCLASSIC is not set
+CONFIG_PRxK=y
+# CONFIG_BSEIP is not set
+# CONFIG_FADS is not set
+# CONFIG_TQM823L is not set
+# CONFIG_TQM850L is not set
+# CONFIG_TQM855L is not set
+# CONFIG_TQM860L is not set
+# CONFIG_FPS850L is not set
+# CONFIG_SPD823TS is not set
+# CONFIG_IVMS8 is not set
+# CONFIG_IVML24 is not set
+# CONFIG_SM850 is not set
+# CONFIG_HERMES_PRO is not set
+# CONFIG_IP860 is not set
+# CONFIG_LWMON is not set
+# CONFIG_PCU_E is not set
+# CONFIG_CCM is not set
+# CONFIG_LANTEC is not set
+# CONFIG_MBX is not set
+# CONFIG_WINCEPT is not set
+CONFIG_TSxK=y
+# CONFIG_TS1H is not set
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SMP is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_KERNEL_ELF=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_CMDLINE_BOOL is not set
+
+#
+# Bus options
+#
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_QSPAN is not set
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=m
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_TCIC is not set
+
+#
+# Advanced setup
+#
+CONFIG_ADVANCED_OPTIONS=y
+CONFIG_HIGHMEM_START=0xfe000000
+# CONFIG_LOWMEM_SIZE_BOOL is not set
+CONFIG_LOWMEM_SIZE=0x30000000
+# CONFIG_KERNEL_START_BOOL is not set
+CONFIG_KERNEL_START=0xc0000000
+# CONFIG_TASK_SIZE_BOOL is not set
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_START_BOOL=y
+CONFIG_CONSISTENT_START=0xa0000000
+# CONFIG_CONSISTENT_SIZE_BOOL is not set
+CONFIG_CONSISTENT_SIZE=0x00200000
+# CONFIG_BOOT_LOAD_BOOL is not set
+CONFIG_BOOT_LOAD=0x00400000
+# CONFIG_PIN_TLB is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=20480
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_LBD is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Macintosh device drivers
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_TOS is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=y
+CONFIG_IP_NF_FTP=y
+# CONFIG_IP_NF_IRC is not set
+# CONFIG_IP_NF_TFTP is not set
+# CONFIG_IP_NF_AMANDA is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_LIMIT=y
+# CONFIG_IP_NF_MATCH_IPRANGE is not set
+CONFIG_IP_NF_MATCH_MAC=y
+# CONFIG_IP_NF_MATCH_PKTTYPE is not set
+CONFIG_IP_NF_MATCH_MARK=y
+CONFIG_IP_NF_MATCH_MULTIPORT=y
+CONFIG_IP_NF_MATCH_TOS=y
+# CONFIG_IP_NF_MATCH_RECENT is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_DSCP is not set
+# CONFIG_IP_NF_MATCH_AH_ESP is not set
+CONFIG_IP_NF_MATCH_LENGTH=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_MATCH_TCPMSS=y
+# CONFIG_IP_NF_MATCH_HELPER is not set
+CONFIG_IP_NF_MATCH_STATE=y
+# CONFIG_IP_NF_MATCH_CONNTRACK is not set
+CONFIG_IP_NF_MATCH_OWNER=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+# CONFIG_IP_NF_TARGET_NETMAP is not set
+# CONFIG_IP_NF_TARGET_SAME is not set
+# CONFIG_IP_NF_NAT_LOCAL is not set
+# CONFIG_IP_NF_NAT_SNMP_BASIC is not set
+CONFIG_IP_NF_NAT_FTP=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_TOS=y
+# CONFIG_IP_NF_TARGET_ECN is not set
+# CONFIG_IP_NF_TARGET_DSCP is not set
+CONFIG_IP_NF_TARGET_MARK=y
+# CONFIG_IP_NF_TARGET_CLASSIFY is not set
+CONFIG_IP_NF_TARGET_LOG=y
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_IP_NF_TARGET_TCPMSS=y
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
+# CONFIG_IP_NF_MATCH_REALM is not set
+# CONFIG_IP_NF_CT_ACCT is not set
+# CONFIG_IP_NF_MATCH_SCTP is not set
+# CONFIG_IP_NF_CT_PROTO_SCTP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+CONFIG_NET_RADIO=y
+
+#
+# Obsolete Wireless cards support (pre-802.11)
+#
+# CONFIG_STRIP is not set
+# CONFIG_PCMCIA_WAVELAN is not set
+# CONFIG_PCMCIA_NETWAVE is not set
+
+#
+# Wireless 802.11 Frequency Hopping cards support
+#
+# CONFIG_PCMCIA_RAYCS is not set
+
+#
+# Wireless 802.11b ISA/PCI cards support
+#
+CONFIG_HERMES=m
+# CONFIG_ATMEL is not set
+
+#
+# Wireless 802.11b Pcmcia/Cardbus cards support
+#
+CONFIG_PCMCIA_HERMES=m
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+CONFIG_NET_WIRELESS=y
+
+#
+# PCMCIA network device support
+#
+CONFIG_NET_PCMCIA=y
+CONFIG_PCMCIA_3C589=m
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+CONFIG_PCMCIA_PCNET=m
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+CONFIG_PCMCIA_XIRC2PS=m
+CONFIG_PCMCIA_AXNET=m
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPPOE is not set
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ISDN subsystem
+#
+CONFIG_ISDN=m
+
+#
+# Old ISDN4Linux
+#
+# CONFIG_ISDN_I4L is not set
+
+#
+# CAPI subsystem
+#
+# CONFIG_ISDN_CAPI is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_CPM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=m
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_CYC_FS=y
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=m
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# MPC8xx CPM Options
+#
+# CONFIG_SCC_ENET is not set
+# CONFIG_FEC_ENET is not set
+CONFIG_ENET_BIG_BUFFERS=y
+# CONFIG_8xx_UART is not set
+
+#
+# Generic MPC8xx Options
+#
+CONFIG_8xx_COPYBACK=y
+CONFIG_8xx_CPU6=y
+CONFIG_UCODE_PATCH=y
+
+#
+# Library routines
+#
+CONFIG_CRC_CCITT=m
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_DEBUG_KERNEL is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/platforms/Makefile linux-2.6.14-rc4/arch/ppc/platforms/Makefile
--- linux-2.6.14-rc4.orig/arch/ppc/platforms/Makefile 2005-10-18 16:59:34.000000000 -0500
+++ linux-2.6.14-rc4/arch/ppc/platforms/Makefile 2005-10-24 16:45:24.000000000 -0500
@@ -42,6 +42,7 @@ obj-$(CONFIG_SBC82xx) += sbc82xx.o
obj-$(CONFIG_SPRUCE) += spruce.o
obj-$(CONFIG_LITE5200) += lite5200.o
obj-$(CONFIG_EV64360) += ev64360.o
+obj-$(CONFIG_PRxK) += prxk.o cyc_spi.o
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_PPC_PMAC) += pmac_smp.o
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/platforms/cpld.h linux-2.6.14-rc4/arch/ppc/platforms/cpld.h
--- linux-2.6.14-rc4.orig/arch/ppc/platforms/cpld.h 1969-12-31 18:00:00.000000000 -0600
+++ linux-2.6.14-rc4/arch/ppc/platforms/cpld.h 2005-10-24 15:35:25.000000000 -0500
@@ -0,0 +1,191 @@
+/*-----------------------------------------------------------------------------
+ * Copyright (C) Cyclades Corporation, 1997.
+ * All rights reserved
+ *
+ * TS1000 - RAS
+ *
+ * This file: cpld.h
+ * Description: This file contains the definitions and prototypes
+ * related to the CPLD programming
+ *
+ *
+ * Complies with Cyclades SW Coding Standard rev 1.2.
+ *-----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ * Change History
+ *-----------------------------------------------------------------------------
+ * Oct/25/2000 V 1.0.0 Edson Seabra
+ * Initial Implementation
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+#define DB_UART_ADDR_SIZE 0x1000
+#define DB_CPLD_ADDR_SIZE 0x1000
+#define DB_FPGA_ADDR_SIZE 0x1000
+#define DB_FPGA_PC_ADDR_SIZE 0x1000
+#define DB_SYSFPGA_ADDR_SIZE 0x1000
+#define DB_MUXFPGA_ADDR_SIZE 0x1000
+
+/* Description of bits in fpga_jp field in the cpld.
+*/
+#define FPGA_JP_PCMCIA 0x02 // bit 6 (Big Endian)
+
+
+/* Description of bits in fpga_pc_ctl field in the cpld.
+ Bits 0-3 for slot A, bits 4-7 for slot B.
+*/
+#define PCMCIA_VCC_33 0x20
+#define PCMCIA_VCC_50 0x10
+#define PCMCIA_VPP_12 0x80
+#define PCMCIA_VPP_VCC 0x40
+#define PCMCIA_VCC_MASK 0x30
+#define PCMCIA_VPP_MASK 0xC0
+
+/* Description of bits in fpga_pc_sts field in the cpld.
+*/
+#define FPGA_PCMCIA_ENABLE 0x80 // bit 0
+
+/* CPLD registers */
+struct cpld_regs {
+ unsigned char reset_enable1; // 0x00
+ unsigned char clock_enable1; // 0x01
+ unsigned char clock_source1; // 0x02
+ unsigned char cpld_misc; // 0x03
+ unsigned char intr_enable1; // 0x04
+ unsigned char intr_enable2; // 0x05
+ unsigned char intr_enable3; // 0x06
+ unsigned char intr_enable4; // 0x07
+ unsigned char intr_status1; // 0x08
+ unsigned char intr_status2; // 0x09
+ unsigned char intr_status3; // 0x0A
+ unsigned char intr_status4; // 0x0B
+ unsigned char fpga_id; // 0x0C
+ unsigned char fpga_jp; // 0x0D
+ unsigned char fpga_cfst; // 0x0E
+ unsigned char fpga_led_ctl; // 0x0F
+ unsigned char reset_enable2; // 0x10
+ unsigned char clock_enable2; // 0x11
+ unsigned char clock_source2; // 0x12
+ unsigned char reserve2; // 0x13
+ unsigned char intr_enable5; // 0x14
+ unsigned char intr_enable6; // 0x15
+ unsigned char reserve3[2]; // 0x16
+ unsigned char intr_status5; // 0x18
+ unsigned char intr_status6; // 0x19
+ unsigned char reserve4[6]; // 0x1A
+ unsigned char bsmux; // 0x20
+ unsigned char fpga_pc_ctl; // 0x21
+ unsigned char fpga_pc_sts; // 0x22
+ unsigned char reserve5[4]; // 0x23
+ unsigned char id_cpld; // 0x27
+};
+
+/* Serial Expander UART registers */
+typedef union
+{
+ struct uart_read {
+ unsigned char rhr;
+ unsigned char space;
+ unsigned char isr; // SSE8-V174
+ unsigned char lcr;
+ unsigned char mcr;
+ unsigned char lsr;
+ unsigned char msr;
+ unsigned char spr;
+ } r;
+
+ struct uart_write {
+ unsigned char thr;
+ unsigned char ier;
+ unsigned char fcr;
+ unsigned char lcr;
+ unsigned char mcr;
+ unsigned char space[2];
+ unsigned char spr;
+ } w;
+
+ struct uart_special {
+ unsigned char dll;
+ unsigned char dlm;
+ unsigned char efr;
+ unsigned char space;
+ unsigned char xon1;
+ unsigned char xon2;
+ unsigned char xoff1;
+ unsigned char xoff2;
+ } s;
+} UART_REGS;
+
+struct fpga_regs {
+ unsigned char fpga_async;
+ unsigned char fpga_wan_reg1;
+ unsigned char fpga_wan_reg2;
+ unsigned char reserved1;
+ unsigned char fpga_cf;
+ unsigned char reserved2;
+ unsigned char fpga_int;
+ unsigned char fpga_dimm;
+ unsigned char reserved3;
+ unsigned char fpga_led;
+ unsigned char fpga_jpr;
+ unsigned char fpga_id;
+};
+
+/* PCMCIA registers */
+struct fpga_pc_regs {
+ unsigned char fpga_pc_misc; // Controls PCMCIA IO's window size
+ unsigned char reserved1[7];
+ unsigned char fpga_pc_stat; // Status - read only
+ unsigned char reserved2[6];
+ unsigned char fpga_pc_id; // PCMCIA FPGA ID - read only
+};
+
+/* FPGA MUX register */
+struct muxfpga_regs {
+ unsigned char misc;
+ unsigned char uart_int;
+ unsigned char vid_ctl_1;
+ unsigned char vid_sts_1;
+ unsigned char vid_gain_1;
+ unsigned char vid_eq_1;
+ unsigned char vid_ctl_2;
+ unsigned char vid_sts_2;
+ unsigned char vid_gain_2;
+ unsigned char vid_eq_2;
+ unsigned char kvm_sel_1;
+ unsigned char kvm_sel_2;
+ unsigned char adm_sel;
+ unsigned char osd_1;
+ unsigned char osd_2;
+ unsigned char id;
+ unsigned char hlo_lsb_1;
+ unsigned char hlo_msb_1;
+ unsigned char hhi_lsb_1;
+ unsigned char hhi_msb_1;
+ unsigned char vlo_lsb_1;
+ unsigned char vlo_msb_1;
+ unsigned char vhi_lsb_1;
+ unsigned char vhi_msb_1;
+ unsigned char hlo_lsb_2;
+ unsigned char hlo_msb_2;
+ unsigned char hhi_lsb_2;
+ unsigned char hhi_msb_2;
+ unsigned char vlo_lsb_2;
+ unsigned char vlo_msb_2;
+ unsigned char vhi_lsb_2;
+ unsigned char vhi_msb_2;
+ unsigned char misc_2;
+ unsigned char uart_int_2;
+};
+
+extern volatile struct cpld_regs *cpld;
+
+extern volatile void *uarts;
+
+extern volatile struct fpga_regs *fpga;
+
+extern volatile struct muxfpga_regs *muxfpga;
+
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/platforms/cyc_flash.h linux-2.6.14-rc4/arch/ppc/platforms/cyc_flash.h
--- linux-2.6.14-rc4.orig/arch/ppc/platforms/cyc_flash.h 1969-12-31 18:00:00.000000000 -0600
+++ linux-2.6.14-rc4/arch/ppc/platforms/cyc_flash.h 2005-10-25 12:16:42.000000000 -0500
@@ -0,0 +1,60 @@
+/*-----------------------------------------------------------------------------
+ * Copyright (C) Cyclades Corporation, 1997.
+ * All rights reserved
+ *
+ * PR-3000 Router
+ *
+ * This file: flash.h
+ * Description: This file contains the definitions and the prototypes
+ * related to the flash module
+ *
+ * Licensed under the terms of the GNU GPL License version 2 -- see
+ * COPYING for details.
+ */
+
+/*-----------------------------------------------------------------------------
+ * Change History
+ *-----------------------------------------------------------------------------
+ * 04/25/96 V 1.0.0 Elio Lerner
+ * First Release
+ * 04/23/96 V 1.0.1 Helio Fujimoto
+ * Port to PR-3000 for test
+ * 07/28/96 V 1.0.2 Helio Fujimoto
+ * Port to PR-3000
+ *-----------------------------------------------------------------------------
+ */
+
+/* Values used on dealing with the flash */
+/* The values are flipped because the data lines on the PR-3000 were flipped */
+#define UNLOCK_VALUE_A 0xaa
+#define UNLOCK_VALUE_B 0x55
+#define SETUP_VALUE 0x80
+#define SECTOR_ERASE_VALUE 0x30
+#define CHIP_ERASE_VALUE 0x10
+#define PROGRAM_VALUE 0xa0
+#define RESET_READ_VALUE 0xf0
+#define AUTO_SELECT_VALUE 0x90
+#define DQ7 0x80
+#define DQ6 0x40
+#define DQ5 0x20
+#define DQ3 0x08
+
+/* Configuration Address */
+#define CFG_ADDR 0x5555
+
+/* values returned by the data_polling procedure */
+#define PASS 0x01
+#define FAIL 0x00
+#define IN_PROGRESS 0x03
+
+struct flash_config_vector_header {
+ unsigned short type;
+ unsigned short size;
+ unsigned short crc;
+ unsigned char data[2];
+};
+
+#define FLASH_ADDR ((((immap_t *)IMAP_ADDR)->im_memctl.memc_br0) & 0xffff8000L)
+
+extern unsigned char *cflash_addr, *flash_addr, *flash_boot;
+
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/platforms/cyc_osd.h linux-2.6.14-rc4/arch/ppc/platforms/cyc_osd.h
--- linux-2.6.14-rc4.orig/arch/ppc/platforms/cyc_osd.h 1969-12-31 18:00:00.000000000 -0600
+++ linux-2.6.14-rc4/arch/ppc/platforms/cyc_osd.h 2005-10-24 16:47:11.000000000 -0500
@@ -0,0 +1,39 @@
+#define NUM_OF_OSDS 2
+#define MAX_VIDEO_CHANNELS 6
+
+#define SPI_FROM_RTC 0
+#define SPI_FROM_OSD1 1
+#define SPI_FROM_OSD2 2
+
+#define OSDGETVIDEO 0
+#define OSDSETVIDEOON 1
+#define OSDSETVIDEOOFF 2
+#define OSDSETPORT 3
+#define OSDGETPORT 4
+#define OSDGETOSD 5
+#define OSDSETOSDON 6
+#define OSDSETOSDOFF 7
+#define OSDSETPOLARITY 8
+#define OSDSETBRIGHTNESS 9
+#define OSDGETBRIGHTNESS 10
+#define OSDSETCONTRAST 11
+#define OSDGETCONTRAST 12
+#define OSDAGCON 13
+#define OSDAGCOFF 14
+#define OSDGETAGC 15
+#define OSDSETTRANSPARENTON 16
+#define OSDSETTRANSPARENTOFF 17
+#define OSDSETVIDEOCOLOR 18
+#define OSDGETVERSION 19
+#define OSDGETSCREEN 20
+#define OSDSETLOCAL 21
+#define OSDSETREMOTE 22
+#define OSDSETRAMCHAR 23
+
+#define NUM_RAM_CHARS 8
+
+struct osdreq_ramchar{
+ __u16 index;
+ __u16 data[18];
+};
+
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/platforms/cyc_spi.c linux-2.6.14-rc4/arch/ppc/platforms/cyc_spi.c
--- linux-2.6.14-rc4.orig/arch/ppc/platforms/cyc_spi.c 1969-12-31 18:00:00.000000000 -0600
+++ linux-2.6.14-rc4/arch/ppc/platforms/cyc_spi.c 2005-10-28 13:24:04.000000000 -0500
@@ -0,0 +1,586 @@
+/*
+ * 8/00 - CPM SPI works, so just use that
+ *
+ * Copyright (c) 2000 Montavista Software, Inc <source@mvista.com>
+ * based on the following
+ *
+ */
+
+/*-----------------------------------------------------------------------------
+ *
+ * Copyright (C) Cyclades Corporation, 1997 - 2000
+ * All rights reserved.
+ *
+ * TSx100/NL1000 v1.00 for Linux
+ *
+ * This file : cyc_spi.c
+ *
+ * Description: This file contains the routines to access for SPI protocol
+ *
+ * Complies with Cyclades SW coding Standard rev 1.2
+ *-----------------------------------------------------------------------------
+ */
+
+ /*----------------------------------------------------------------------------
+ * Change History
+ *----------------------------------------------------------------------------
+ * 11/8/01 Arnaldo Zimmermann Initial implementation
+ *----------------------------------------------------------------------------
+ * Aug/09/02 Edson Seabra Port to linux kernel
+ *----------------------------------------------------------------------------
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/poll.h>
+#include <linux/miscdevice.h>
+#include <linux/random.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/timex.h>
+#include <linux/time.h>
+
+#include <asm/uaccess.h>
+#include <asm/mpc8xx.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <platforms/prxk.h>
+
+#include <asm/delay.h>
+#include <asm/commproc.h>
+#include <asm/time.h>
+#include <asm/todc.h>
+
+#include <platforms/cyc_osd.h>
+
+#undef DEBUG_READ_SPI
+#undef DEBUG_WRITE_SPI
+
+#define IS_BOARD_KVMANA (CYC_BOARD_TYPE == BOARD_KVM16 || \
+ CYC_BOARD_TYPE == BOARD_KVM32)
+#define IS_BOARD_KVMNET (CYC_BOARD_TYPE == BOARD_KVMNET16 || \
+ CYC_BOARD_TYPE == BOARD_KVMNET32)
+#define IS_BOARD_KVMNETP (CYC_BOARD_TYPE == BOARD_KVMP16 || \
+ CYC_BOARD_TYPE == BOARD_KVMP32)
+#define IS_BOARD_ONS (CYC_BOARD_TYPE == BOARD_ONS441 || \
+ CYC_BOARD_TYPE == BOARD_ONS481 || \
+ CYC_BOARD_TYPE == BOARD_ONS841 || \
+ CYC_BOARD_TYPE == BOARD_ONS881 || \
+ CYC_BOARD_TYPE == BOARD_ONS442 || \
+ CYC_BOARD_TYPE == BOARD_ONS482 || \
+ CYC_BOARD_TYPE == BOARD_ONS842 || \
+ CYC_BOARD_TYPE == BOARD_ONS882)
+#define IS_BOARD_KVM (IS_BOARD_KVMANA || IS_BOARD_KVMNET || \
+ IS_BOARD_ONS || IS_BOARD_KVMNETP)
+
+
+/* for the KVM */
+static int spiinuse = 0;
+static int spiopened = 0;
+static int spiinitialized = 0;
+
+unsigned long *tbdf_vaddr = 0;
+unsigned long *rbdf_vaddr = 0;
+
+int cyc_cpm_spi_open(char);
+int cyc_cpm_spi_close(unsigned char);
+
+static void
+msdelay(uint t, uint interv)
+{
+ uint i;
+ volatile sysconf8xx_t *psiu = &(((immap_t *)IMAP_ADDR)->im_siu_conf);
+
+ /* delay t miliseconds */
+ for (i=0; i<t; i++) {
+ udelay(interv);
+ psiu->sc_swsr = 0x556c;
+ psiu->sc_swsr = 0xaa39;
+ }
+}
+
+void __init
+cyc_cpm_spi_init(void)
+{
+ unsigned long *mem_addr;
+ unsigned int dp_addr, reloc;
+ cbd_t *rbdf;
+ cbd_t *tbdf;
+ volatile cpm8xx_t *cp;
+ volatile spi_t *spp;
+ volatile immap_t *immap;
+
+ if (IS_BOARD_KVM && spiinitialized) {
+ return;
+ }
+
+ cp = cpmp; /* Get pointer to Communication Processor */
+ immap = (immap_t *)IMAP_ADDR; /* and to internal registers */
+
+ spp = (spi_t *)&cp->cp_dparam[PROFF_SPI];
+
+ /* Check for and use a microcode relocation patch.
+ */
+ if ((reloc = spp->spi_rpbase))
+ spp = (spi_t *)&cp->cp_dpmem[spp->spi_rpbase];
+
+
+ /* Initialize Port B SPI pins.
+ */
+ cp->cp_pbpar &= ~0x00020000;
+ cp->cp_pbpar |= 0x0000000E;
+ cp->cp_pbdir |= 0x0002000F;
+ cp->cp_pbodr &= ~0x0000000E;
+ cp->cp_pbdat |= 0x00000001;
+
+ if (IS_BOARD_KVM) {
+ immap->im_ioport.iop_papar &= ~0x00c0;
+ immap->im_ioport.iop_padir |= 0x00c0;
+ immap->im_ioport.iop_padat &= ~0x00c0;
+ }
+
+ /* Initialize the parameter ram.
+ * We need to make sure many things are initialized to zero,
+ * especially in the case of a microcode patch.
+ */
+ spp->spi_rstate = 0;
+ spp->spi_rdp = 0;
+ spp->spi_rbptr = 0;
+ spp->spi_rbc = 0;
+ spp->spi_rxtmp = 0;
+ spp->spi_tstate = 0;
+ spp->spi_tdp = 0;
+ spp->spi_tbptr = 0;
+ spp->spi_tbc = 0;
+ spp->spi_txtmp = 0;
+
+
+ /* Allocate space for one transmit and one receive buffer
+ * descriptor in the DP ram.
+ */
+ dp_addr = cpm_dpalloc(sizeof(cbd_t) * 2, 8);
+ if (IS_ERR(&dp_addr)) {
+ panic("Warning! Failed to allocate tx/rx buffer on DP ram for SPI");
+ }
+ /* Set up the SPI parameters in the parameter ram.
+ */
+ spp->spi_tbase = dp_addr;
+ spp->spi_rbase = dp_addr + sizeof(cbd_t);
+
+ /*
+ * manually init if using microcode patch
+ */
+ if(reloc)
+ {
+ spp->spi_rbptr = spp->spi_rbase;
+ spp->spi_tbptr = spp->spi_tbase;
+ }
+
+ spp->spi_tfcr = 0x18;
+ spp->spi_rfcr = 0x18;
+
+ /* Set maximum receive size.
+ */
+ spp->spi_mrblr = 32;
+
+ /* Initialize Tx/Rx parameters.
+ */
+ if (reloc == 0) {
+ cp->cp_cpcr =
+ mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+ while (cp->cp_cpcr & CPM_CR_FLG);
+ }
+ /* The notes on the SPI relocation patch indicate the the init rx and
+ tx command doesn't work. It isn't clear if this also includes
+ the individual rx and tx init commands, but at any rate it seems
+ to work fine if we just skip these commands.
+ */
+ else {
+ cp->cp_cpcr =
+ mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TX) | CPM_CR_FLG;
+ while (cp->cp_cpcr & CPM_CR_FLG);
+
+ cp->cp_cpcr =
+ mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_RX) | CPM_CR_FLG;
+ while (cp->cp_cpcr & CPM_CR_FLG);
+ }
+
+ /* Set the buffer address.
+ */
+ dp_addr = cpm_dpalloc(32, 4);
+ if (IS_ERR(&dp_addr)) {
+ panic("Warning! Failed to allocate rx buffer on CPM ram for SPI");
+ }
+// mem_addr = (unsigned long *)(&cpmp->cp_dpmem[dp_addr]);
+ mem_addr = (unsigned long*)cpm_dpram_addr(dp_addr);
+ memset(mem_addr, 0, 32);
+
+ rbdf = (cbd_t *)&cp->cp_dpmem[spp->spi_rbase];
+ rbdf->cbd_bufaddr = iopa((unsigned long)mem_addr);
+ rbdf_vaddr = mem_addr;
+
+// dp_addr = m8xx_cpm_dpalloc(32);
+ dp_addr = cpm_dpalloc(32, 4);
+ if (IS_ERR(&dp_addr)) {
+ panic("Warning! Failed to allocate tx buffer on CPM ram for SPI");
+ }
+// mem_addr = (unsigned long*)(&cpmp->cp_dpmem[dp_addr]);
+ mem_addr = (unsigned long*)cpm_dpram_addr(dp_addr);
+ memset(mem_addr, 0, 32);
+
+ tbdf = (cbd_t *)&cp->cp_dpmem[spp->spi_tbase];
+ tbdf->cbd_bufaddr = iopa((unsigned long)mem_addr);
+ tbdf_vaddr = mem_addr;
+
+ /* Clear event
+ */
+ cp->cp_spie = ~0;
+
+ /* No events
+ */
+ cp->cp_spim = 0;
+
+
+ /*
+ * 62.5KHz clock for the A/D
+ * 8 bit
+ * The datasheet specs for the ADS7843 indicate that it should work
+ * with a clock rate of up to 2MHz, but we don't seem to be able to
+ * get reliable touchpanel samples with a clock much faster than
+ * 62.5KHz. This translates to a sample time of 768 microseconds
+ * to sample both the X and Y coordinates.
+ */
+
+ if (IS_BOARD_KVM) {
+ spiinuse = 0;
+ spiinitialized = 1;
+ spiopened = 0;
+ } else {
+ cp->cp_spmode = SPMODE_CI | SPMODE_CP | SPMODE_REV |
+ SPMODE_MSTR | SPMODE_DIV16 | ((8-1) << 4) | 0xF |
+ SPMODE_EN;
+ }
+ printk("SPI init done.\r\n");
+ //last_reboot();
+
+}
+
+
+/* Read from SPI.
+ * This is a two step process. First, we send the "dummy" write
+ * to set the device offset for the read. Second, we perform
+ * the read operation.
+ */
+
+ssize_t
+cyc_cpm_spi_read(char *buf, size_t count)
+{
+ volatile spi_t *spp;
+ volatile cbd_t *tbdf, *rbdf;
+ volatile cpm8xx_t *cp;
+ unsigned long flags;
+ uint reloc;
+
+ cp = cpmp; /* Get pointer to Communication Processor */
+ spp = (spi_t *)&cp->cp_dparam[PROFF_SPI];
+
+ if (IS_BOARD_KVM) {
+ cyc_cpm_spi_open(SPI_FROM_RTC);
+ }
+
+ /* Check for and use a microcode relocation patch.
+ */
+ if ((reloc = spp->spi_rpbase)) {
+ spp = (spi_t *)&cp->cp_dpmem[spp->spi_rpbase];
+ }
+
+ if (count >= spp->spi_mrblr) {
+ return 0;
+ }
+
+ tbdf = (cbd_t *)&cp->cp_dpmem[spp->spi_tbase];
+ rbdf = (cbd_t *)&cp->cp_dpmem[spp->spi_rbase];
+
+ memset(tbdf_vaddr, 0, count);
+ *(char*)(tbdf_vaddr) &= ~0x80; /* read command */
+ memset(rbdf_vaddr,0,count);
+
+ tbdf->cbd_datlen = count;
+ tbdf->cbd_sc = BD_SC_READY|BD_SC_WRAP|BD_SC_INTRPT|BD_SC_LAST;
+
+ rbdf->cbd_datlen = 0;
+ rbdf->cbd_sc = BD_SC_EMPTY|BD_SC_WRAP|BD_SC_INTRPT;
+
+
+ /* Chip bug, set enable here. */
+
+ cp->cp_pbdat &= ~0x00000001;
+ msdelay(2, 1000);
+
+ local_irq_save(flags);
+
+ cp->cp_spie = ~0;
+ cp->cp_spcom |= 0x80; /* Start Transmit */
+
+ /* Wait for SPI transfer. */
+
+ while(!(cp->cp_spie & 0x35)) {
+ msdelay(1,10);
+ }
+
+ local_irq_restore(flags);
+
+ cp->cp_pbdat |= 0x00000001;
+
+ if (cp->cp_spie != 0x03) {
+ printk("\r\nSPI error on reading RTC. Status = 0x%04x",
+ cp->cp_spie);
+ return 0;
+ }
+
+ if (signal_pending(current))
+ return -ERESTARTSYS;
+
+ if (rbdf->cbd_datlen != count) {
+ printk("cyc_cpm_spi_read %d of %d\n", rbdf->cbd_datlen, count);
+ }
+
+ if (rbdf->cbd_sc & BD_SC_EMPTY) {
+ printk("SPI read complete but rbuf empty\n");
+ }
+
+ memcpy(buf,rbdf_vaddr, count);
+
+#ifdef DEBUG_READ_SPI
+{ size_t i;
+ printk("RTC read: ");
+ for (i = 0; i<count; i++) printk("%02x", (unsigned char)buf[i]);
+ printk("\r\n");
+}
+#endif
+
+ if (IS_BOARD_KVM) {
+ cyc_cpm_spi_close(SPI_FROM_RTC);
+ }
+ return rbdf->cbd_datlen;
+}
+
+
+ssize_t
+cyc_cpm_spi_write(char *buf, size_t count)
+{
+ volatile spi_t *spp;
+ volatile cbd_t *tbdf, *rbdf;
+ volatile cpm8xx_t *cp;
+ unsigned long flags;
+ uint reloc, status;
+
+ cp = cpmp; /* Get pointer to Communication Processor */
+ spp = (spi_t *)&cp->cp_dparam[PROFF_SPI];
+
+ if (IS_BOARD_KVM) {
+ cyc_cpm_spi_open(SPI_FROM_RTC);
+ }
+
+ /* Check for and use a microcode relocation patch.
+ */
+ if ((reloc = spp->spi_rpbase) != 0) {
+ spp = (spi_t *)&cp->cp_dpmem[spp->spi_rpbase];
+ }
+
+ if (count >= spp->spi_mrblr) {
+ return 0;
+ }
+
+ tbdf = (cbd_t *)&cp->cp_dpmem[spp->spi_tbase];
+ rbdf = (cbd_t *)&cp->cp_dpmem[spp->spi_rbase];
+
+#ifdef DEBUG_WRITE_SPI
+{ size_t i;
+ printk("RTC write: ");
+ for (i = 0; i<count; i++) printk("%02x", (unsigned char)buf[i]);
+ printk("\r\n");
+}
+#endif
+
+ memset(tbdf_vaddr, 0, count);
+ *(char*)(tbdf_vaddr) |= 0x80; /* write command */
+ memset(rbdf_vaddr,0,count);
+
+ tbdf->cbd_datlen = count; /* Length */
+ rbdf->cbd_datlen = 0; /* Length */
+
+ tbdf->cbd_sc = BD_SC_READY|BD_SC_WRAP|BD_SC_INTRPT|BD_SC_LAST;
+ rbdf->cbd_sc = BD_SC_EMPTY|BD_SC_WRAP|BD_SC_INTRPT;
+
+ cp->cp_pbdat &= ~0x00000001;
+ msdelay(2, 1000);
+
+ local_irq_save(flags);
+
+ cp->cp_spie = ~0;
+ cp->cp_spcom = 0x80;
+
+ /* Wait for SPI transfer.
+ */
+ while(!(status = (cp->cp_spie & 0x32))) {
+ msdelay(1,10);
+ }
+
+ local_irq_restore(flags);
+
+ cp->cp_pbdat |= 0x00000001;
+
+ if (signal_pending(current))
+ return -ERESTARTSYS;
+
+ if (status != 0x02) { // check if TxB is set w/o other errors
+ printk("\r\nSPI error when reading RTC");
+ return 0;
+ }
+
+ if (tbdf->cbd_sc & BD_SC_READY)
+ printk("SPI ra complete but tbuf ready\n");
+
+ if (IS_BOARD_KVM) {
+ cyc_cpm_spi_close(SPI_FROM_RTC);
+ }
+
+ return count;
+}
+
+int
+cyc_cpm_spi_open(char from)
+{
+#ifdef DEBUG_WRITE_SPI
+ printk("SPI open from = %d, spiinuse = %d, spiopened = %d\n",
+ from, spiinuse, spiopened);
+#endif
+ if (spiinuse) {
+ if (spiinuse == from + 1) {
+ spiopened ++;
+ return 1;
+ } else {
+ return 0;
+ }
+ }
+
+ if (from >= 0 && from <= 2) {
+ volatile cpm8xx_t *cp = cpmp;
+ volatile immap_t *immap = (immap_t *)IMAP_ADDR;
+ if (IS_BOARD_KVMNETP) {
+ switch (from) {
+ case 0:
+ immap->im_ioport.iop_padat &= ~0x00c0;
+ break;
+ case 1:
+ immap->im_ioport.iop_padat |= 0x0080;
+ immap->im_ioport.iop_padat &= ~0x0040;
+ break;
+ case 2:
+ immap->im_ioport.iop_padat |= 0x00c0;
+ break;
+ }
+ } else {
+ immap->im_ioport.iop_padat &= ~0x00c0;
+ immap->im_ioport.iop_padat |= 0x0040 * from;
+ }
+ spiinuse = from + 1;
+ spiopened = 1;
+ if (from == 0) {
+ cp->cp_spmode = SPMODE_CI | SPMODE_CP | SPMODE_REV |
+ SPMODE_MSTR | SPMODE_DIV16 | ((8-1) << 4) |
+ 0xF | SPMODE_EN;
+ } else {
+ cp->cp_spmode = SPMODE_CI | SPMODE_CP |
+ SPMODE_MSTR | ((16-1) << 4) | 5 | SPMODE_EN;
+ }
+ }
+ return 1;
+}
+
+int
+cyc_cpm_spi_close(unsigned char from)
+{
+ volatile cpm8xx_t *cp = cpmp;
+ volatile immap_t *immap = (immap_t *)IMAP_ADDR;
+#ifdef DEBUG_WRITE_SPI
+ printk("SPI close from = %d, spiinuse = %d, spiopened = %d\n",
+ from, spiinuse, spiopened);
+#endif
+ if (!spiopened || (spiinuse && spiinuse != from + 1)) {
+ return 0;
+ }
+ if (--spiopened == 0) {
+ if (IS_BOARD_KVMNETP) {
+ immap->im_ioport.iop_padat &= ~0x00c0;
+ } else {
+ immap->im_ioport.iop_padat |= 0x00c0;
+ }
+ spiinuse = 0;
+ cp->cp_spmode = 0;
+ }
+ return 1;
+}
+
+#define INV(x) (x & 0xff) * 0x100 + (x / 0x100)
+
+ssize_t
+cyc_cpm_spi_osd_write(char from, unsigned short *buffer, int size)
+{
+ volatile spi_t *spp;
+ volatile cbd_t *tbdf, *rbdf;
+ volatile cpm8xx_t *cp;
+ uint reloc, i;
+
+ if (spiinuse != from + 1) {
+ return 0;
+ }
+
+ cp = cpmp; /* Get pointer to Communication Processor */
+ spp = (spi_t *)&cp->cp_dparam[PROFF_SPI];
+
+ /* Check for and use a microcode relocation patch.
+ */
+ if ((reloc = spp->spi_rpbase)) {
+ spp = (spi_t *)&cp->cp_dpmem[spp->spi_rpbase];
+ }
+
+ tbdf = (cbd_t *)&cp->cp_dpmem[spp->spi_tbase];
+ rbdf = (cbd_t *)&cp->cp_dpmem[spp->spi_rbase];
+
+ if (tbdf->cbd_sc & BD_SC_READY) {
+ return 0;
+ }
+ cp->cp_pbdat &= ~0x00000001;
+
+ udelay(1);
+
+ for (i = 0; i < size; i ++) {
+#ifdef DEBUG_WRITE_SPI
+ printk("SPI write: %04x\r\n", buffer[i]);
+#endif
+
+ *(unsigned short *)(tbdf_vaddr) = INV(buffer[i]);
+ tbdf->cbd_datlen = 2; /* Length */
+ tbdf->cbd_sc = BD_SC_READY|BD_SC_WRAP|BD_SC_INTRPT|BD_SC_LAST;
+ rbdf->cbd_sc = BD_SC_EMPTY|BD_SC_WRAP|BD_SC_INTRPT;
+
+ cp->cp_spie = ~0;
+ cp->cp_spcom = 0x80;
+
+ udelay(10);
+ while (tbdf->cbd_sc & BD_SC_READY) {
+ udelay(2);
+ }
+
+ }
+ cp->cp_pbdat |= 0x00000001;
+ udelay(2);
+ return 2 * i;
+}
+
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/platforms/prxk.c linux-2.6.14-rc4/arch/ppc/platforms/prxk.c
--- linux-2.6.14-rc4.orig/arch/ppc/platforms/prxk.c 1969-12-31 18:00:00.000000000 -0600
+++ linux-2.6.14-rc4/arch/ppc/platforms/prxk.c 2005-10-28 14:04:15.000000000 -0500
@@ -0,0 +1,307 @@
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/time.h>
+#include <linux/rtc.h>
+#include <asm/io.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include <platforms/prxk.h>
+#include <platforms/cpld.h>
+
+volatile struct fpga_pc_regs *fpga_pc;
+volatile void *uarts;
+volatile struct cpld_regs *cpld;
+volatile struct fpga_pc_regs *fpga_pc;
+volatile struct muxfpga_regs *muxfpga;
+
+void *get_cpld(void *dummy)
+{
+ return (void *)cpld;
+}
+
+EXPORT_SYMBOL(get_cpld);
+
+
+unsigned char *cflash_addr;
+unsigned char *flash_addr;
+
+void __init prxk_init_memory(void)
+{
+ bd_t *bd = (bd_t *)__res;
+ unsigned int i_uart, i_cpld;
+ unsigned int i_cflash, cflash_size;
+ unsigned int i_flash, flash_size;
+
+ i_cflash = cflash_size = 0;
+
+ switch (CYC_BOARD_TYPE) {
+ case BOARD_ACS48:
+ case BOARD_ACS32:
+ case BOARD_ACS16:
+ case BOARD_ACS8:
+ case BOARD_ACS4:
+ case BOARD_ACS1:
+ case BOARD_KVM16:
+ case BOARD_KVM32:
+ case BOARD_KVMNET16:
+ case BOARD_KVMNET32:
+ i_cflash = (((immap_t *)IMAP_ADDR)->im_memctl.memc_br2 &
+ 0xffff8000L);
+ cflash_size = 0x1000;
+ default:
+ i_cpld = (((immap_t *)IMAP_ADDR)->im_memctl.memc_br3 &
+ 0xffff8000L);
+ i_uart = (((immap_t *)IMAP_ADDR)->im_memctl.memc_br4 &
+ 0xffff8000L);
+ }
+
+ uarts = (void *)ioremap_nocache(i_uart, DB_UART_ADDR_SIZE);
+ cpld = (struct cpld_regs *)ioremap_nocache(i_cpld, DB_CPLD_ADDR_SIZE);
+
+ switch (CYC_BOARD_TYPE) {
+ case BOARD_ACS48:
+ case BOARD_ACS32:
+ case BOARD_ACS16:
+ case BOARD_ACS8:
+ case BOARD_ACS4:
+ case BOARD_ACS1:
+ case BOARD_KVM16:
+ case BOARD_KVM32:
+ case BOARD_KVMNET16:
+ case BOARD_KVMNET32:
+ cflash_addr = ioremap_nocache(i_cflash, cflash_size);
+ break;
+ }
+
+ switch (CYC_BOARD_TYPE) {
+ case BOARD_ACS32:
+ case BOARD_ACS16:
+ case BOARD_ACS8:
+ case BOARD_ACS4:
+ if (!(cpld->fpga_jp & FPGA_JP_PCMCIA)) {
+ // PCMCIA present
+ unsigned int i_fpga_pc;
+ i_fpga_pc = (((immap_t *)IMAP_ADDR)->im_memctl.memc_br5
+ & 0xffff8000L);
+ fpga_pc = (struct fpga_pc_regs *)ioremap_nocache(i_fpga_pc,
+ DB_FPGA_PC_ADDR_SIZE);
+ }
+ break;
+ }
+
+ switch (CYC_BOARD_TYPE) {
+ case BOARD_KVM16:
+ case BOARD_KVM32:
+ case BOARD_KVMNET16:
+ case BOARD_KVMNET32:
+ {
+ unsigned int i_muxfpga;
+ i_muxfpga = (((immap_t *)IMAP_ADDR)->im_memctl.memc_br5
+ & 0xffff8000L);
+ muxfpga = (struct muxfpga_regs *)ioremap_nocache(i_muxfpga,
+ DB_MUXFPGA_ADDR_SIZE);
+ }
+ break;
+ }
+
+ i_flash = (((immap_t *)IMAP_ADDR)->im_memctl.memc_br0 & 0xffff8000L);
+ flash_size = bd->hw_info.flash_size;
+
+ flash_addr = ioremap_nocache(i_flash, flash_size);
+
+ switch (CYC_BOARD_TYPE) {
+ case BOARD_ACS48:
+ case BOARD_ACS16:
+ case BOARD_ACS32:
+ case BOARD_ACS8:
+ case BOARD_ACS4:
+ case BOARD_ACS1:
+ case BOARD_KVM16:
+ case BOARD_KVM32:
+ case BOARD_KVMNET16:
+ case BOARD_KVMNET32:
+ printk("CF+ addr: %x Flash Addr %x, CPLD addr: %x, "
+ "UART Addr: %x\n", (int)cflash_addr, (int)flash_addr,
+ (int)cpld, (int)uarts);
+ break;
+ default:
+ printk("Flash addr: %x, CPLD addr: %x, UART Addr: %x\n",
+ (int)flash_addr, (int)cpld, (int)uarts);
+ break;
+ }
+
+}
+
+void cyc_8xx_restart(char *cmd)
+{
+ switch (CYC_BOARD_TYPE) {
+ case BOARD_ACS48:
+ case BOARD_ACS16:
+ case BOARD_ACS32:
+ case BOARD_ACS8:
+ case BOARD_ACS4:
+ case BOARD_ACS1:
+ case BOARD_KVM16:
+ case BOARD_KVM32:
+ case BOARD_KVMNET16:
+ case BOARD_KVMNET32:
+ case BOARD_KVMP16:
+ case BOARD_KVMP32:
+ /* RTC chip enable pin set to level 1 - pin PB31*/
+ ((volatile immap_t *)IMAP_ADDR)->im_cpm.cp_pbpar &= ~0x0001;
+ ((volatile immap_t *)IMAP_ADDR)->im_cpm.cp_pbdat |= 0x0001;
+ ((volatile immap_t *)IMAP_ADDR)->im_cpm.cp_pbdir |= 0x0001;
+ mdelay(200);
+ /* RTC chip enable pin set to level 0 - pin PB31*/
+ ((volatile immap_t *)IMAP_ADDR)->im_cpm.cp_pbdat &= ~0x0001;
+ mdelay(200);
+ }
+
+ /* reset output set to level 0 - pin PA3 */
+ ((volatile immap_t *)IMAP_ADDR)->im_ioport.iop_padat &= ~0x1000;
+ ((volatile immap_t *)IMAP_ADDR)->im_ioport.iop_padir |= 0x1000;
+ mdelay(200);
+ ((volatile immap_t *)IMAP_ADDR)->im_ioport.iop_padat |= 0x1000;
+
+}
+
+//the routines to access external real time clock via SPI protocol
+#define RTC_GET_BCD_SEC(x) ((x & 0x0f) + (((x & 0x70) >> 4) * 10))
+#define RTC_GET_BCD_MIN(x) ((x & 0x0f) + (((x & 0x70) >> 4) * 10))
+#define RTC_GET_BCD_HR(x) ((x & 0x0f) + (((x & 0x30) >> 4) * 10))
+#define RTC_GET_BCD_MDAY(x) ((x & 0x0f) + (((x & 0x30) >> 4) * 10))
+#define RTC_GET_BCD_MONTH(x) ((x & 0x0f) + (((x & 0x10) >> 4) * 10))
+#define RTC_GET_BCD_YEAR(x) ((x & 0x0f) + (((x & 0xf0) >> 4) * 10))
+
+#define RTC_PUT_BCD_SEC(x,y) ((((x % 10) + ((x / 10) << 4)) & 0x7f) | (y & ~0x7f))
+#define RTC_PUT_BCD_MIN(x,y) ((((x % 10) + ((x / 10) << 4)) & 0x7f) | (y & ~0x7f))
+#define RTC_PUT_BCD_HR(x,y) ((((x % 10) + ((x / 10) << 4)) & 0x3f) | (y & ~0x3f))
+#define RTC_PUT_BCD_MDAY(x,y) ((((x % 10) + ((x / 10) << 4)) & 0x3f) | (y & ~0x3f))
+#define RTC_PUT_BCD_MONTH(x,y) ((((x % 10) + ((x / 10) << 4)) & 0x1f) | (y & ~0x1f))
+#define RTC_PUT_BCD_YEAR(x) (((x % 10) + ((x / 10) << 4)) & 0xff)
+
+extern ssize_t cyc_cpm_spi_read(char *buf, size_t count);
+extern ssize_t cyc_cpm_spi_write(char *buf, size_t count);
+extern void __init cyc_cpm_spi_init(void);
+
+void last_reboot(void)
+{
+ struct rtc_time tm;
+#ifdef CONFIG_UBOOT
+ char buf[32], buf2[32];
+ memset(buf,0, sizeof(buf));
+
+ buf[0] = 0x00;
+ cyc_cpm_spi_read(buf, 16);
+ tm.tm_sec = RTC_GET_BCD_SEC(buf[2]);
+ tm.tm_min = RTC_GET_BCD_MIN(buf[3]);
+ tm.tm_hour= RTC_GET_BCD_HR(buf[4]);
+ tm.tm_mday = RTC_GET_BCD_MDAY(buf[6]);
+ tm.tm_mon = RTC_GET_BCD_MONTH(buf[7]);
+ tm.tm_year= RTC_GET_BCD_YEAR(buf[8]);
+ /* Clear halt bit */
+ buf2[0] = 0x8c;
+ buf2[1] = buf[0x0d] & ~0x40;
+ cyc_cpm_spi_write(buf2, 3);
+ /* Clear stop bit */
+ buf2[0] = 0x81;
+ buf2[1] = buf[2] & ~0x80;
+ cyc_cpm_spi_write(buf2, 3);
+ /* Clear TR bit */
+ buf2[0] = 0x84;
+ buf2[1] = buf[5] & ~0x80;
+ cyc_cpm_spi_write(buf2, 3);
+#else
+ bd_t *binfo = (bd_t *)__res;
+
+ tm.tm_sec = RTC_GET_BCD_SEC(binfo->hw_info.rtc_value[1]);
+ tm.tm_min = RTC_GET_BCD_MIN(binfo->hw_info.rtc_value[2]);
+ tm.tm_hour = RTC_GET_BCD_HR(binfo->hw_info.rtc_value[3]);
+ tm.tm_mday = RTC_GET_BCD_MDAY(binfo->hw_info.rtc_value[5]);
+ tm.tm_mon = RTC_GET_BCD_MONTH(binfo->hw_info.rtc_value[6]);
+ tm.tm_year = RTC_GET_BCD_YEAR(binfo->hw_info.rtc_value[7]);
+
+#endif
+ tm.tm_year = tm.tm_year + 1900;
+ if (tm.tm_year < 1970) {
+ tm.tm_year += 100;
+ }
+ printk("Last reboot was on %d/%d/%04d at %02d:%02d:%02d GST\r\n",
+ tm.tm_mon, tm.tm_mday, tm.tm_year, tm.tm_hour, tm.tm_min, tm.tm_sec);
+}
+
+void m8xx_wdt_reset(void);
+long __init cyc_rtc_init(void)
+{
+ cyc_cpm_spi_init();
+ printk("RTC init done");
+ last_reboot();
+ return 0;
+}
+
+unsigned long cyc_get_rtc_time(void)
+{
+ unsigned int year, mon, day, hour, min, sec;
+ char buf[32];
+
+ memset(buf,0, sizeof(buf));
+
+ buf[0] = 0x00; /* first position should have register addr on the RTC */
+ cyc_cpm_spi_read(buf, 16); /* read 15 bytes + 1 reg addr */
+ /* buf[1-15] are valid returned data */
+ sec = RTC_GET_BCD_SEC(buf[2]);
+ min = RTC_GET_BCD_MIN(buf[3]);
+ hour= RTC_GET_BCD_HR(buf[4]);
+ day = RTC_GET_BCD_MDAY(buf[6]);
+ mon = RTC_GET_BCD_MONTH(buf[7]);
+ year= RTC_GET_BCD_YEAR(buf[8]);
+
+ year = year + 1900;
+ if (year < 1970) {
+ year += 100;
+ }
+
+ return mktime(year, mon, day, hour, min, sec);
+}
+
+int cyc_set_rtc_time(unsigned long nowtime)
+{
+ struct rtc_time tm;
+ char buf[32];
+
+ to_tm(nowtime, &tm);
+
+ tm.tm_year = (tm.tm_year - 1900) % 100;
+
+ memset(buf, 0, sizeof(buf));
+ buf[0] = 0x00; /* first position should have register addr on the RTC */
+ cyc_cpm_spi_read(buf, 16); /* read 15 bytes + 1 red addr */
+
+ buf[2] = RTC_PUT_BCD_SEC(tm.tm_sec, buf[2]);
+ buf[3] = RTC_PUT_BCD_MIN(tm.tm_min, buf[3]);
+ buf[4] = RTC_PUT_BCD_HR(tm.tm_hour, buf[4]);
+ buf[6] = RTC_PUT_BCD_MDAY(tm.tm_mday, buf[6]);
+ buf[7] = RTC_PUT_BCD_MONTH(tm.tm_mon, buf[7]);
+ buf[8] = RTC_PUT_BCD_YEAR(tm.tm_year);
+
+ buf[0] = 0x00; /* first position should have register addr on the RTC */
+ cyc_cpm_spi_write(buf, 10);
+
+ return 0;
+}
+
+void __init
+board_init(void)
+{
+ ppc_md.time_init = cyc_rtc_init;
+ ppc_md.set_rtc_time = cyc_set_rtc_time;
+ ppc_md.get_rtc_time = cyc_get_rtc_time;
+ ppc_md.restart = cyc_8xx_restart;
+}
+
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/platforms/prxk.h linux-2.6.14-rc4/arch/ppc/platforms/prxk.h
--- linux-2.6.14-rc4.orig/arch/ppc/platforms/prxk.h 1969-12-31 18:00:00.000000000 -0600
+++ linux-2.6.14-rc4/arch/ppc/platforms/prxk.h 2005-10-24 15:54:56.000000000 -0500
@@ -0,0 +1,135 @@
+
+/*
+ * A collection of structures, addresses, and values associated with
+ * the PRxK board. Copied from the EST8xx stuff.
+ *
+ * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+ */
+#ifndef __MACH_PRxK_DEFS
+#define __MACH_PRxK_DEFS
+
+#ifndef __ASSEMBLY__
+#define CYC_BOARD_TYPE (((bd_t *)__res)->hw_info.board_type)
+
+#define BOARD_PR3K 0
+#define BOARD_PR2K 1
+#define BOARD_PR4K 2
+#define BOARD_PR1K 3
+#define BOARD_TS1K 4
+#define BOARD_TS2K 5
+#define BOARD_TS4H 6
+#define BOARD_TS8H 7
+#define BOARD_TS3K 8
+#define BOARD_TX1K 9
+#define BOARD_TX2K 10
+#define BOARD_PL1K 11
+#define BOARD_TS1H 12
+#define BOARD_NL1K 13
+#define BOARD_ACS16 14
+#define BOARD_ACS32 15
+#define BOARD_SM100 16
+#define BOARD_PR3500 17
+#define BOARD_TS110 18
+#define BOARD_ACS48 19
+#define BOARD_ACS4 20
+#define BOARD_ACS8 21
+#define BOARD_ACS1 22
+#define BOARD_KVM16 24
+#define BOARD_KVM32 25
+#define BOARD_KVMNET16 26
+#define BOARD_KVMNET32 27
+#define BOARD_ONS441 28
+#define BOARD_ONS481 29
+#define BOARD_ONS841 30
+#define BOARD_ONS881 31
+#define BOARD_ONS442 32
+#define BOARD_ONS482 33
+#define BOARD_ONS842 34
+#define BOARD_ONS882 35
+#define BOARD_KVMP16 36
+#define BOARD_KVMP32 37
+
+
+/* PRxB boot code information data,
+ * they come from FPGA and Dip switchs
+*/
+struct prxk_boot_info {
+ unsigned int mem_test_result;
+ unsigned int memory_detected;
+ unsigned char alt_boot;
+ unsigned char error_status;
+ unsigned char reserved;
+ unsigned char board_type;
+ unsigned int flash_size;
+ unsigned char clock_freq;
+ unsigned char processor;
+ unsigned char manufactor;
+ unsigned char eth_links;
+ unsigned char board_version;
+ unsigned char save_opcode;
+ unsigned char code_legacy;
+ unsigned char flash_chips;
+ unsigned char serial_itf;
+ unsigned char power_supply;
+ unsigned char pcmcia;
+ unsigned char wdt_config;
+ unsigned char rtc_value[20];
+ unsigned int storage_size; //[RK] compact flash size
+ unsigned char device_id[16]; //[RK] router id
+ unsigned char async_config; // KVMNET USER2 profile
+ unsigned char fpga_version; // FPGA version
+ unsigned char ipboard1;
+ unsigned char ipboard2;
+ unsigned char next_available;
+};
+
+/* A Board Information structure that is given to a program when
+ * prom starts it up.
+ */
+typedef struct bd_info {
+ unsigned int bi_memstart; /* Memory start address */
+ unsigned int bi_memsize; /* Memory (end) size in bytes */
+ unsigned int bi_intfreq; /* Internal Freq, in Hz */
+ unsigned int bi_busfreq; /* Bus Freq, in Hz */
+ unsigned char wdt;
+ unsigned char mii_operation;
+ unsigned char bi_enetaddr[6];
+ unsigned int bi_baudrate;
+ unsigned int ibytesec; //[GB]May/06/06 - Ethernet Receive Rate Limit
+ unsigned short max_int_work;
+ unsigned short num_portsS;
+ unsigned short num_portsA;
+ unsigned short num_portsM;
+ unsigned short num_portsK;
+ unsigned char board_name[32];
+ unsigned char vendor_name[32];
+ unsigned char prod_line[32];
+ unsigned char prod_name[32];
+ unsigned char card_name[10];
+ unsigned char cyc_banner[256];
+ unsigned char cyc_version[32];
+ struct prxk_boot_info hw_info;
+} bd_t;
+
+/* Memory map is configured by the PROM startup.
+ * We just map a few things we need.
+ */
+#define IMAP_ADDR ((uint)0xff000000)
+#define IMAP_SIZE ((uint)(64 * 1024))
+
+#define _IO_BASE 0xB0000000
+#define _IO_BASE_SIZE (1024*64)
+
+#endif //__ASSEMBLY__
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS 0
+
+#define FEC_INTERRUPT SIU_LEVEL5
+
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_PRxK)
+
+#endif
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/arch/ppc/syslib/m8xx_setup.c linux-2.6.14-rc4/arch/ppc/syslib/m8xx_setup.c
--- linux-2.6.14-rc4.orig/arch/ppc/syslib/m8xx_setup.c 2005-10-18 16:59:34.000000000 -0500
+++ linux-2.6.14-rc4/arch/ppc/syslib/m8xx_setup.c 2005-10-24 16:16:41.000000000 -0500
@@ -356,12 +356,14 @@ m8xx_map_io(void)
io_block_mapping(PCI_ISA_IO_ADDR, PCI_ISA_IO_ADDR, 0x4000, _PAGE_IO);
io_block_mapping(PCI_IDE_ADDR, PCI_IDE_ADDR, 0x4000, _PAGE_IO);
#endif
-#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
- io_block_mapping(RPX_CSR_ADDR, RPX_CSR_ADDR, RPX_CSR_SIZE, _PAGE_IO);
+#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || defined(CONFIG_PRxK)
#if !defined(CONFIG_PCI)
io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
#endif
#endif
+#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
+ io_block_mapping(RPX_CSR_ADDR, RPX_CSR_ADDR, RPX_CSR_SIZE, _PAGE_IO);
+#endif
#if defined(CONFIG_HTDMSOUND) || defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX)
io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO);
#endif
diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/include/asm-ppc/mpc8xx.h linux-2.6.14-rc4/include/asm-ppc/mpc8xx.h
--- linux-2.6.14-rc4.orig/include/asm-ppc/mpc8xx.h 2005-10-18 17:00:09.000000000 -0500
+++ linux-2.6.14-rc4/include/asm-ppc/mpc8xx.h 2005-10-24 15:49:24.000000000 -0500
@@ -68,6 +68,10 @@
#include <platforms/mpc885ads.h>
#endif
+#if defined (CONFIG_PRxK)
+#include <platforms/prxk.h>
+#endif
+
/* Currently, all 8xx boards that support a processor to PCI/ISA bridge
* use the same memory map.
*/
^ permalink raw reply
* Re: PPCBoot 2.0.0 Errors
From: Wolfgang Denk @ 2005-11-14 11:36 UTC (permalink / raw)
To: Sette Agostino; +Cc: linuxppc-embedded
In-Reply-To: <69DF49BE936F4441980EC1D59F0ADC2F010ADBDD@aqlby02a.siemens.it>
In message <69DF49BE936F4441980EC1D59F0ADC2F010ADBDD@aqlby02a.siemens.it> you wrote:
>
> Now I have the U-Boot for MPC859, but I am not sure this line is
> correct
I will not continue to answer your U-Boot questions on this list,
where they are off topic. Please post on the u-boot-users mailing
list instead.
Also, make sure to use a more appropriate Subject: line.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
You Earth people glorified organized violence for forty centuries.
But you imprison those who employ it privately.
-- Spock, "Dagger of the Mind", stardate 2715.1
^ permalink raw reply
* RE: PPCBoot 2.0.0 Errors
From: Sette Agostino @ 2005-11-14 11:26 UTC (permalink / raw)
To: wd; +Cc: linuxppc-embedded
Hello Wolfgang,
Now I have the U-Boot for MPC859, but I am not sure this line is =
correct
U-Boot 1.1.3 (Nov 11 2005 - 16:38:24)
CPU: MPC859TxxZPnnA at 133 MHz: 16 kB I-Cache 8 kB D-Cache FEC =
present
As far as I know, the I-Cache and the D-Cache of the MPC859 is 4 kB, as
defined in the MPC866UM Appendix F.
Here is the chapter which describe the cache
F.3 Cache Control Registers
The MPC859T bit fields and commands of the cache control and status
registers (IC_CST
and DC_CST) are implemented the same as for the MPC866P. However, the =
bit
fields of
the cache address registers (IC_ADR and DC_ADR) and the cache data port
registers
(IC_DAT and DC_DAT) must be used for the 4-Kbyte instruction and data
caches. See
Chapter 7, "Instruction and Data Caches."
We think that the MPC859 probably has phisically the same cache size as =
the
MPC866, but only 4 kB must be used.
Anyway, my question is, must I worry about the data printed on the =
screen or
can I leave as they are?
I mean, are these information used in other part of the U-Boot or the
Kernel?
Thanks in advance.
Best Regards
Agostino Sette
-----Original Message-----
From: wd@denx.de [mailto:wd@denx.de]=20
Sent: marted=EC 8 novembre 2005 14.38
To: Sette Agostino
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: PPCBoot 2.0.0 Errors=20
In message =
<69DF49BE936F4441980EC1D59F0ADC2F0108C29F@aqlby02a.siemens.it>
you wrote:
>=20
> As I told you, I tried to produce the U-boot, but I am nont confident =
on
the
> version (1.0.0).
No, indeed. This is ancient stuff. Use top of tree from the GIT repo
(or CVS), or download the latest snapshot from our FTP server.
> Could you suggest me the latest stale version I must get?
May I suggest that you start reading the manual? See
http://www.denx.de/wiki/DULG/Manual
Best regards,
Wolfgang Denk
--=20
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
I will not say that women have no character; rather, they have a new
one every day. -- Heine
^ permalink raw reply
* Steps to upgrade a Linux 2.6.7 kernel to 64 bit kernel
From: Vijayakumar Ramalingam @ 2005-11-14 10:08 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 166 bytes --]
Hi all,
I want to build a 64 bit ppc kernel from 32 bit ppc-linux kernel 2.6.7
I want to know how it can be done & what else to be taken care?
Thanks
Vijay
[-- Attachment #2: Type: text/html, Size: 360 bytes --]
^ permalink raw reply
* Re: name created by rpmbuild
From: Wolfgang Denk @ 2005-11-14 9:38 UTC (permalink / raw)
To: debora liu; +Cc: Linuxppc-embedded
In-Reply-To: <200511141320468.SM01124@debora-liu>
In message <200511141320468.SM01124@debora-liu> you wrote:
>
> I'm using rpmbuild, but it creat rpm packet name is "NAME-ppc_8xx-VERSION-RELEASE.ppc.rpm",
> I think it should is "NAME-VERSION-RELEASE.ppc.rpm", true?
> I use native rpmbuild on my board with eldk-3.1.1 PPC8xx NFS root.
You asked the same question just two days ago. Why do you ask again?
I replied:
------- Forwarded Message
Date: Sat, 12 Nov 2005 13:52:56 +0100
From: Wolfgang Denk <wd@denx.de>
To: deboralh@fel.com.cn
Subject: Re: packet name created by rpmbuild
In message <200511121759781.SM00928@RavProxy> you wrote:
> >
> Sorry, this is text
Thanks.
> I'm using rpmbuild, but it creat rpm packet name is "NAME-ppc_8xx-VERSION-REL
EASE.ppc.rpm",
> I think it should is "NAME-VERSION-RELEASE.ppc.rpm", true?
No, wrong. "*.ppc.rpm" indicates a "standard" RPM from some Linux
distribution, like a Fedora Core PowerPC RPM. Such an RPM will NOT
run on your MPC8xx system, and your ppc_8xx created RPM will not run
on a Fedora Core PowerPC system. Differences are caused for example
by support for a FPU and adjustment for different cache line sizes.
To avoid confusion, MPC8xx specific RPMs are created using a special
name which makes clear that they are compatible with the ELDK RPMs,
but not with other PowerPC RPMs.
> I use native rpmbuild on my board with eldk-3.1.1 PPC8xx NFS root.
Native rpmbuild and cross rpmbuild are compatible with each other,
but not with RPMs from other PowerPC Linux distributions.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Where people stand is not as important as which way they face.
- Terry Pratchett & Stephen Briggs, _The Discworld Companion_
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