* [PATCH 6/10 v2] Add 8641 Register space and IRQ definitions.
From: Jon Loeliger @ 2006-06-08 22:00 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Jeff Brown <Jeff.Brown@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
---
include/asm-powerpc/immap_86xx.h | 199 ++++++++++++++++++++++++++++++++++++++
include/asm-powerpc/irq.h | 88 +++++++++++++++++
include/asm-powerpc/mpc86xx.h | 47 +++++++++
3 files changed, 334 insertions(+), 0 deletions(-)
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h
new file mode 100644
index 0000000..d905b66
--- /dev/null
+++ b/include/asm-powerpc/immap_86xx.h
@@ -0,0 +1,199 @@
+/*
+ * MPC86xx Internal Memory Map
+ *
+ * Author: Jeff Brown
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __ASM_POWERPC_IMMAP_86XX_H__
+#define __ASM_POWERPC_IMMAP_86XX_H__
+#ifdef __KERNEL__
+
+/* Eventually this should define all the IO block registers in 86xx */
+
+/* PCI Registers */
+typedef struct ccsr_pci {
+ uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */
+ uint cfg_data; /* 0x.004 - PCI Configuration Data Register */
+ uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
+ char res1[3060];
+ uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */
+ uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */
+ uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */
+ char res2[4];
+ uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */
+ char res3[12];
+ uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */
+ uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */
+ uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */
+ char res4[4];
+ uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */
+ char res5[12];
+ uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */
+ uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */
+ uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */
+ char res6[4];
+ uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */
+ char res7[12];
+ uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */
+ uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */
+ uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */
+ char res8[4];
+ uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */
+ char res9[12];
+ uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */
+ uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */
+ uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */
+ char res10[4];
+ uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */
+ char res11[268];
+ uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */
+ char res12[4];
+ uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */
+ uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */
+ uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */
+ char res13[12];
+ uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */
+ char res14[4];
+ uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */
+ uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */
+ uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */
+ char res15[12];
+ uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */
+ char res16[4];
+ uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */
+ char res17[4];
+ uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */
+ char res18[12];
+ uint err_dr; /* 0x.e00 - PCI Error Detect Register */
+ uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */
+ uint err_en; /* 0x.e08 - PCI Error Enable Register */
+ uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */
+ uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */
+ uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */
+ uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */
+ uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */
+ uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */
+ uint pci_timr; /* 0x.e24 - PCI Timer Register */
+ char res19[472];
+} ccsr_pci_t;
+
+/* PCI Express Registers */
+typedef struct ccsr_pex {
+ uint pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
+ uint pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
+ char res1[4];
+ uint pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
+ uint pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
+ char res2[12];
+ uint pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
+ uint pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
+ uint pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
+ uint pex_pmcr; /* 0x.02c - PCI Express power management command register */
+ char res3[3024];
+ uint pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
+ uint pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
+ char res4[8];
+ uint pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
+ char res5[12];
+ uint pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
+ uint pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
+ uint pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
+ char res6[4];
+ uint pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
+ char res7[12];
+ uint pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
+ uint pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
+ uint pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
+ char res8[4];
+ uint pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
+ char res9[12];
+ uint pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
+ uint pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
+ uint pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
+ char res10[4];
+ uint pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
+ char res11[12];
+ uint pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
+ uint pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
+ uint pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
+ char res12[4];
+ uint pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
+ char res13[12];
+ char res14[256];
+ uint pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
+ char res15[4];
+ uint pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
+ uint pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
+ uint pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
+ char res16[12];
+ uint pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
+ char res17[4];
+ uint pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
+ uint pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
+ uint pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
+ char res18[12];
+ uint pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
+ char res19[4];
+ uint pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
+ uint pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
+ uint pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
+ char res20[12];
+ uint pex_err_dr; /* 0x.e00 - PCI Express error detect register */
+ char res21[4];
+ uint pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
+ char res22[4];
+ uint pex_err_disr; /* 0x.e10 - PCI Express error disable register */
+ char res23[12];
+ uint pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
+ char res24[4];
+ uint pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
+ uint pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
+ uint pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
+ uint pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
+} ccsr_pex_t;
+
+/* Global Utility Registers */
+typedef struct ccsr_guts {
+ uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
+ uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
+ uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
+ uint pordevsr; /* 0x.000c - POR I/O Device Status Register */
+ uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
+ char res1[12];
+ uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */
+ char res2[12];
+ uint gpiocr; /* 0x.0030 - GPIO Control Register */
+ char res3[12];
+ uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
+ char res4[12];
+ uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */
+ char res5[12];
+ uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
+ char res6[12];
+ uint devdisr; /* 0x.0070 - Device Disable Control */
+ char res7[12];
+ uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
+ char res8[12];
+ uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */
+ char res9[12];
+ uint pvr; /* 0x.00a0 - Processor Version Register */
+ uint svr; /* 0x.00a4 - System Version Register */
+ char res10[3416];
+ uint clkocr; /* 0x.0e00 - Clock Out Select Register */
+ char res11[12];
+ uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
+ char res12[12];
+ uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
+ char res13[61916];
+} ccsr_guts_t;
+
+#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index 7bc6d73..997d2e8 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -348,6 +348,94 @@ #define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ
#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
+#elif defined(CONFIG_PPC_86xx)
+#include <asm/mpc86xx.h>
+
+#define NR_EPIC_INTS 48
+#ifndef NR_8259_INTS
+#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
+#endif
+#define NUM_8259_INTERRUPTS NR_8259_INTS
+
+#ifndef I8259_OFFSET
+#define I8259_OFFSET 0
+#endif
+
+#define NR_IRQS 256
+
+/* Internal IRQs on MPC86xx OpenPIC */
+
+#ifndef MPC86xx_OPENPIC_IRQ_OFFSET
+#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
+#endif
+
+/* The 48 internal sources */
+#define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_PEX1 ( 8 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_PEX2 ( 9 + MPC86xx_OPENPIC_IRQ_OFFSET)
+
+/* no 10,11 */
+#define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 25 */
+#define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 29,30,31 */
+#define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 35,36 */
+#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
+
+/* The 12 external interrupt lines */
+#define MPC86xx_IRQ_EXT_BASE 48
+#define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+
#else /* CONFIG_40x + CONFIG_8xx */
/*
* this is the # irq's for all ppc arch's (pmac/chrp/prep)
diff --git a/include/asm-powerpc/mpc86xx.h b/include/asm-powerpc/mpc86xx.h
new file mode 100644
index 0000000..d0a6718
--- /dev/null
+++ b/include/asm-powerpc/mpc86xx.h
@@ -0,0 +1,47 @@
+/*
+ * MPC86xx definitions
+ *
+ * Author: Jeff Brown
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_POWERPC_MPC86xx_H__
+#define __ASM_POWERPC_MPC86xx_H__
+
+#include <linux/config.h>
+#include <asm/mmu.h>
+
+#ifdef CONFIG_PPC_86xx
+
+#ifdef CONFIG_MPC8641_HPCN
+#include <platforms/86xx/mpc8641_hpcn.h>
+#endif
+
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#ifdef CONFIG_PCI
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define PCI_DRAM_OFFSET 0
+#endif
+
+#define CPU0_BOOT_RELEASE 0x01000000
+#define CPU1_BOOT_RELEASE 0x02000000
+#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
+#define MCM_PORT_CONFIG_OFFSET 0x1010
+
+/* Offset from CCSRBAR */
+#define MPC86xx_OPENPIC_OFFSET (0x40000)
+#define MPC86xx_MCM_OFFSET (0x00000)
+#define MPC86xx_MCM_SIZE (0x02000)
+
+#endif /* CONFIG_PPC_86xx */
+#endif /* __ASM_POWERPC_MPC86xx_H__ */
+#endif /* __KERNEL__ */
^ permalink raw reply related
* [PATCH 5/10 v2] Add 8641 CPU and i8259 Setup
From: Jon Loeliger @ 2006-06-08 21:59 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Add 8641 CPU table entry.
Add SMP CPU id determination and clear BATS.
Use level triggers on i8259.
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/kernel/cputable.c | 12 ++++++++++++
arch/powerpc/kernel/head_32.S | 15 +++++++++++++++
arch/powerpc/sysdev/i8259.c | 5 +++++
3 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 0c487ee..2c8ac7e 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -704,6 +704,18 @@ #if CLASSIC_PPC
.oprofile_type = PPC_OPROFILE_G4,
.platform = "ppc7450",
},
+ { /* 8641 */
+ .pvr_mask = 0xffffffff,
+ .pvr_value = 0x80040010,
+ .cpu_name = "8641",
+ .cpu_features = CPU_FTRS_7447A,
+ .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ .num_pmcs = 6,
+ .cpu_setup = __setup_cpu_745x
+ },
+
{ /* 82xx (8240, 8245, 8260 are all 603e cores) */
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00810000,
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index a0579e8..e8f6bfa 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -224,6 +224,10 @@ turn_on_mmu:
li r3,1 /* MTX only has 1 cpu */
.globl __secondary_hold
__secondary_hold:
+#ifdef CONFIG_PPC_86xx
+ /* get the cpu id */
+ mfspr r3, SPRN_PIR
+#endif
/* tell the master we're here */
stw r3,__secondary_hold_acknowledge@l(0)
#ifdef CONFIG_SMP
@@ -348,6 +352,16 @@ #define EXC_XFER_EE_LITE(n, hdlr) \
#if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
. = 0x100
b __secondary_start_gemini
+#endif
+/* we need to ensure that the address translation is disabled */
+#if defined(CONFIG_PPC_86xx) && defined(CONFIG_SMP)
+ . = 0x100
+ mfmsr r3
+ andi. r0, r3, (MSR_IR | MSR_DR)
+ andc r3, r3, r0
+ mtmsr r3
+ isync
+ b __secondary_hold
#else
EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
#endif
@@ -1019,6 +1033,7 @@ #endif /* CONFIG_6xx */
stw r0,0(r3)
/* load up the MMU */
+ bl clear_bats
bl load_up_mmu
/* ptr to phys current thread */
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
index b7ac32f..9b755e1 100644
--- a/arch/powerpc/sysdev/i8259.c
+++ b/arch/powerpc/sysdev/i8259.c
@@ -201,6 +201,11 @@ void __init i8259_init(unsigned long int
outb(0x0B, 0x20);
outb(0x0B, 0xA0);
+#ifdef CONFIG_I8259_LEVEL_TRIGGER
+ outb(0xfa, 0x4d0); /* level triggered */
+ outb(0xde, 0x4d1);
+#endif
+
/* Mask all interrupts */
outb(cached_A1, 0xA1);
outb(cached_21, 0x21);
^ permalink raw reply related
* [PATCH 4/10 v2] Guard L3CR references with CPU_FTR_L3CR.
From: Jon Loeliger @ 2006-06-08 21:58 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/kernel/cpu_setup_6xx.S | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S
index 55ed771..365381f 100644
--- a/arch/powerpc/kernel/cpu_setup_6xx.S
+++ b/arch/powerpc/kernel/cpu_setup_6xx.S
@@ -210,9 +210,11 @@ setup_745x_specifics:
* the firmware. If any, we disable NAP capability as
* it's known to be bogus on rev 2.1 and earlier
*/
+BEGIN_FTR_SECTION
mfspr r11,SPRN_L3CR
andis. r11,r11,L3CR_L3E@h
beq 1f
+END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
lwz r6,CPU_SPEC_FEATURES(r5)
andi. r0,r6,CPU_FTR_L3_DISABLE_NAP
beq 1f
^ permalink raw reply related
* [PATCH 3/10 v2] Add MPC8641 HPCN PCI and PCI-Express files.
From: Jon Loeliger @ 2006-06-08 21:57 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/platforms/86xx/pci.c | 213 +++++++++++++++++++++++++++++++++++++
arch/powerpc/platforms/86xx/pex.c | 173 ++++++++++++++++++++++++++++++
2 files changed, 386 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
new file mode 100644
index 0000000..eff6f28
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -0,0 +1,213 @@
+/*
+ * MPC86XX pci setup code
+ *
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/serial.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/immap_86xx.h>
+#include <asm/pci-bridge.h>
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+
+#ifdef CONFIG_PEX
+static void __init
+mpc86xx_setup_pex(struct pci_controller *hose)
+{
+ volatile struct ccsr_pex *pex;
+ u16 cmd;
+ unsigned int temps;
+ phys_addr_t immr;
+
+ immr = get_immrbase();
+
+ pex = ioremap(immr + MPC86xx_PEX_OFFSET, MPC86xx_PEX_SIZE);
+
+ early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+ | PCI_COMMAND_IO;
+ early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
+
+ early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
+
+ /* PEX Bus, Fix the MPC8641D host bridge's location to bus 0xFF. */
+ early_read_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, &temps);
+ temps = (temps & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
+ early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps);
+
+ /* Disable all windows (except pexowar0 since its ignored) */
+ pex->pexowar1 = 0;
+ pex->pexowar2 = 0;
+ pex->pexowar3 = 0;
+ pex->pexowar4 = 0;
+ pex->pexiwar1 = 0;
+ pex->pexiwar2 = 0;
+ pex->pexiwar3 = 0;
+
+ /* Setup Phys:PEX 1:1 outbound mem window @ MPC86XX_PEX_LOWER_MEM */
+ pex->pexotar1 = (MPC86XX_PEX_LOWER_MEM >> 12) & 0x000fffff;
+ pex->pexotear1 = 0x00000000;
+ pex->pexowbar1 = (MPC86XX_PEX_LOWER_MEM >> 12) & 0x000fffff;
+ /* Enable, Mem R/W */
+ pex->pexowar1 = 0x80044000 |
+ (__ilog2(MPC86XX_PEX_UPPER_MEM - MPC86XX_PEX_LOWER_MEM + 1) - 1);
+
+ /* Setup outboud IO windows @ MPC86XX_PEX_IO_BASE */
+ pex->pexotar2 = (MPC86XX_PEX_LOWER_IO >> 12) & 0x000fffff;
+ pex->pexotear2 = 0x00000000;
+ pex->pexowbar2 = (MPC86XX_PEX_IO_BASE >> 12) & 0x000fffff;
+ /* Enable, IO R/W */
+ pex->pexowar2 = 0x80088000 | (__ilog2(MPC86XX_PEX_IO_SIZE) - 1);
+
+ /* Setup 2G inbound Memory Window @ 0 */
+ pex->pexitar1 = 0x00000000;
+ pex->pexiwbar1 = 0x00000000;
+ /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
+ pex->pexiwar1 = 0xa0f5501e;
+}
+
+int __init add_bridge(struct device_node *dev)
+{
+ int len;
+ struct pci_controller *hose;
+ struct resource rsrc;
+ int *bus_range;
+ int has_address = 0;
+
+ pr_debug("Adding PEX host bridge %s\n", dev->full_name);
+
+ /* Fetch host bridge registers address */
+ has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
+
+ /* Get bus range if any */
+ bus_range = (int *) get_property(dev, "bus-range", &len);
+ if (bus_range == NULL || len < 2 * sizeof(int))
+ printk(KERN_WARNING "Can't get bus-range for %s, assume"
+ " bus 0\n", dev->full_name);
+
+ hose = pcibios_alloc_controller();
+ if (!hose)
+ return -ENOMEM;
+ hose->arch_data = dev;
+ hose->set_cfg_type = 1;
+
+ /* last_busno = 0xfe cause by PEX bug */
+ hose->first_busno = bus_range ? bus_range[0] : 0x0;
+ hose->last_busno = bus_range ? bus_range[1] : 0xfe;
+
+ setup_indirect_pex(hose, rsrc.start, rsrc.start + 0x4);
+
+ /* Setup the first PEX controller. */
+ if ((rsrc.start & 0xfffff) == 0x8000)
+ mpc86xx_setup_pex(hose);
+
+ printk(KERN_INFO "Found MPC86xx PEX host bridge at 0x%08lx. "
+ "Firmware bus number: %d->%d\n",
+ rsrc.start, hose->first_busno, hose->last_busno);
+
+ pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
+ hose, hose->cfg_addr, hose->cfg_data);
+
+ /* Interpret the "ranges" property */
+ /* This also maps the I/O region and sets isa_io/mem_base */
+ pci_process_bridge_OF_ranges(hose, dev, 1);
+
+ return 0;
+}
+#endif /* CONFIG_PEX */
+
+static void __devinit quirk_ali1575(struct pci_dev *dev)
+{
+ /*
+ * ALI1575 interrupts route table setup:
+ *
+ * IRQ pin IRQ#
+ * PIRQA ---- 3
+ * PIRQB ---- 4
+ * PIRQC ---- 5
+ * PIRQD ---- 6
+ * PIRQE ---- 9
+ * PIRQF ---- 10
+ * PIRQG ---- 11
+ * PIRQH ---- 12
+ *
+ * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
+ * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
+ */
+ pci_write_config_dword(dev, 0x48, 0xb9317542);
+
+ /* USB 1.1 OHCI controller 1, interrupt: PIRQE */
+ pci_write_config_byte(dev, 0x86, 0x0c);
+
+ /* USB 1.1 OHCI controller 2, interrupt: PIRQF */
+ pci_write_config_byte(dev, 0x87, 0x0d);
+
+ /* USB 1.1 OHCI controller 3, interrupt: PIRQH */
+ pci_write_config_byte(dev, 0x88, 0x0f);
+
+ /* USB 2.0 controller, interrupt: PIRQ7 */
+ pci_write_config_byte(dev, 0x74, 0x06);
+
+ /* Audio controller, interrupt: PIRQE */
+ pci_write_config_byte(dev, 0x8a, 0x0c);
+
+ /* Modem controller, interrupt: PIRQF */
+ pci_write_config_byte(dev, 0x8b, 0x0d);
+
+ /* HD audio controller, interrupt: PIRQG */
+ pci_write_config_byte(dev, 0x8c, 0x0e);
+
+ /* Serial ATA interrupt: PIRQD */
+ pci_write_config_byte(dev, 0x8d, 0x0b);
+
+ /* SMB interrupt: PIRQH */
+ pci_write_config_byte(dev, 0x8e, 0x0f);
+
+ /* PMU ACPI SCI interrupt: PIRQH */
+ pci_write_config_byte(dev, 0x8f, 0x0f);
+
+}
+
+static void __devinit quirk_uli5288(struct pci_dev *dev)
+{
+ unsigned char c;
+
+ pci_read_config_byte(dev,0x83,&c);
+ c |= 0x80;
+ pci_write_config_byte(dev, 0x83, c);
+
+ pci_write_config_byte(dev, 0x09, 0x01);
+ pci_write_config_byte(dev, 0x0a, 0x06);
+
+ pci_read_config_byte(dev,0x83,&c);
+ c &= 0x7f;
+ pci_write_config_byte(dev, 0x83, c);
+
+ pci_read_config_byte(dev,0x84,&c);
+ c |= 0x01;
+ pci_write_config_byte(dev, 0x84, c);
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
+
diff --git a/arch/powerpc/platforms/86xx/pex.c b/arch/powerpc/platforms/86xx/pex.c
new file mode 100644
index 0000000..2624d3c
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/pex.c
@@ -0,0 +1,173 @@
+/*
+ * Support for indirect PCI bridges.
+ *
+ * Copyright (C) 1998 Gabriel Paubert.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * "Temporary" MPC8548 Errata file -
+ * The standard indirect_pci code should work with future silicon versions.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+
+#include "mpc86xx.h"
+
+#define PCI_CFG_OUT out_be32
+
+/* ERRATA PCI-Ex 14 PEX Controller timeout */
+#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
+
+
+static int
+indirect_read_config_pex(struct pci_bus *bus, unsigned int devfn, int offset,
+ int len, u32 *val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ volatile void __iomem *cfg_data;
+ u32 temp;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ /* Possible artifact of CDCpp50937 needs further investigation */
+ if (devfn != 0x0 && bus->number == 0xff)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ PEX_FIX;
+ if (bus->number == 0xff) {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ } else {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000001 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ }
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+ cfg_data = hose->cfg_data;
+ PEX_FIX;
+ temp = in_le32(cfg_data);
+ switch (len) {
+ case 1:
+ *val = (temp >> (((offset & 3))*8)) & 0xff;
+ break;
+ case 2:
+ *val = (temp >> (((offset & 3))*8)) & 0xffff;
+ break;
+ default:
+ *val = temp;
+ break;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+indirect_write_config_pex(struct pci_bus *bus, unsigned int devfn, int offset,
+ int len, u32 val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ volatile void __iomem *cfg_data;
+ u32 temp;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ /* Possible artifact of CDCpp50937 needs further investigation */
+ if (devfn != 0x0 && bus->number == 0xff)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ PEX_FIX;
+ if (bus->number == 0xff) {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ } else {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000001 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ }
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+ cfg_data = hose->cfg_data;
+ switch (len) {
+ case 1:
+ PEX_FIX;
+ temp = in_le32(cfg_data);
+ temp = (temp & ~(0xff << ((offset & 3) * 8))) |
+ (val << ((offset & 3) * 8));
+ PEX_FIX;
+ out_le32(cfg_data, temp);
+ break;
+ case 2:
+ PEX_FIX;
+ temp = in_le32(cfg_data);
+ temp = (temp & ~(0xffff << ((offset & 3) * 8)));
+ temp |= (val << ((offset & 3) * 8)) ;
+ PEX_FIX;
+ out_le32(cfg_data, temp);
+ break;
+ default:
+ PEX_FIX;
+ out_le32(cfg_data, val);
+ break;
+ }
+ PEX_FIX;
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops indirect_pex_ops = {
+ indirect_read_config_pex,
+ indirect_write_config_pex
+};
+
+void __init
+setup_indirect_pex_nomap(struct pci_controller* hose, void __iomem * cfg_addr,
+ void __iomem * cfg_data)
+{
+ hose->cfg_addr = cfg_addr;
+ hose->cfg_data = cfg_data;
+ hose->ops = &indirect_pex_ops;
+}
+
+void __init
+setup_indirect_pex(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
+{
+ unsigned long base = cfg_addr & PAGE_MASK;
+ void __iomem *mbase, *addr, *data;
+
+ mbase = ioremap(base, PAGE_SIZE);
+ addr = mbase + (cfg_addr & ~PAGE_MASK);
+ if ((cfg_data & PAGE_MASK) != base)
+ mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
+ data = mbase + (cfg_data & ~PAGE_MASK);
+ setup_indirect_pex_nomap(hose, addr, data);
+}
^ permalink raw reply related
* [PATCH 2/10 v2] Add the MPC8641 HPCN platform files.
From: Jon Loeliger @ 2006-06-08 21:57 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/platforms/86xx/misc.c | 51 +++++
arch/powerpc/platforms/86xx/mpc8641_hpcn.c | 52 +++++
arch/powerpc/platforms/86xx/mpc8641_hpcn.h | 54 +++++
arch/powerpc/platforms/86xx/mpc86xx.h | 31 +++
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 304 ++++++++++++++++++++++++++++
5 files changed, 492 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/misc.c b/arch/powerpc/platforms/86xx/misc.c
new file mode 100644
index 0000000..01c5e9b
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/misc.c
@@ -0,0 +1,51 @@
+/*
+ * MPC86XX generic code
+ *
+ * Author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <sysdev/fsl_soc.h>
+
+void
+mpc86xx_restart(char *cmd)
+{
+ void __iomem *rstcr;
+
+ local_irq_disable();
+
+ /* Assert reset request to Reset Control Register */
+ rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
+ out_be32(rstcr, 0x2);
+
+ /* not reached */
+}
+
+
+long __init
+mpc86xx_time_init(void)
+{
+ unsigned int temp;
+
+ /* Set the time base to zero */
+ mtspr(SPRN_TBWL, 0);
+ mtspr(SPRN_TBWU, 0);
+
+ temp = mfspr(SPRN_HID0);
+ temp |= HID0_TBEN;
+ mtspr(SPRN_HID0, temp);
+ asm volatile("isync");
+
+ return 0;
+}
diff --git a/arch/powerpc/platforms/86xx/mpc8641_hpcn.c b/arch/powerpc/platforms/86xx/mpc8641_hpcn.c
new file mode 100644
index 0000000..655e2b8
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc8641_hpcn.c
@@ -0,0 +1,52 @@
+/*
+ * MPC8641 HPCN board specific routines
+ *
+ * Author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/pci-bridge.h>
+#include <asm-powerpc/mpic.h>
+#include <asm/mpc86xx.h>
+
+#include "mpc86xx.h"
+
+
+#ifdef CONFIG_SMP
+static void __init
+smp_8641_kick_cpu(int nr)
+{
+ *(unsigned long *)KERNELBASE = nr;
+ asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
+ printk("CPU%d released, waiting\n",nr);
+}
+
+static void __init
+smp_8641_setup_cpu(int cpu_nr)
+{
+ mpic_setup_this_cpu();
+}
+
+
+struct smp_ops_t smp_8641_ops = {
+ .message_pass = smp_mpic_message_pass,
+ .probe = smp_mpic_probe,
+ .kick_cpu = smp_8641_kick_cpu,
+ .setup_cpu = smp_8641_setup_cpu,
+ .take_timebase = smp_generic_take_timebase,
+ .give_timebase = smp_generic_give_timebase,
+};
+#endif /* CONFIG_SMP */
diff --git a/arch/powerpc/platforms/86xx/mpc8641_hpcn.h b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
new file mode 100644
index 0000000..4ba5b4c
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
@@ -0,0 +1,54 @@
+/*
+ * MPC8641 HPCN board definitions
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Author: Xianghua Xiao <x.xiao@freescale.com>
+ */
+
+#ifndef __MPC8641_HPCN_H__
+#define __MPC8641_HPCN_H__
+
+#include <linux/config.h>
+#include <linux/init.h>
+
+/* PCI interrupt controller */
+#define PIRQA 3
+#define PIRQB 4
+#define PIRQC 5
+#define PIRQD 6
+#define PIRQ7 7
+#define PIRQE 9
+#define PIRQF 10
+#define PIRQG 11
+#define PIRQH 12
+
+/* PEX memory map */
+#define MPC86XX_PEX_LOWER_IO 0x00000000
+#define MPC86XX_PEX_UPPER_IO 0x00ffffff
+
+#define MPC86XX_PEX_LOWER_MEM 0x80000000
+#define MPC86XX_PEX_UPPER_MEM 0x9fffffff
+
+#define MPC86XX_PEX_IO_BASE 0xe2000000
+#define MPC86XX_PEX_MEM_OFFSET 0x00000000
+
+#define MPC86XX_PEX_IO_SIZE 0x01000000
+
+#define PEX1_CFG_ADDR_OFFSET (0x8000)
+#define PEX1_CFG_DATA_OFFSET (0x8004)
+
+#define PEX2_CFG_ADDR_OFFSET (0x9000)
+#define PEX2_CFG_DATA_OFFSET (0x9004)
+
+#define MPC86xx_PEX_OFFSET PEX1_CFG_ADDR_OFFSET
+#define MPC86xx_PEX_SIZE (0x1000)
+
+#define MPC86XX_RSTCR_OFFSET (0xe00b0) /* Reset Control Register */
+
+#endif /* __MPC8641_HPCN_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h b/arch/powerpc/platforms/86xx/mpc86xx.h
new file mode 100644
index 0000000..7cc45d4
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MPC86XX_H__
+#define __MPC86XX_H__
+
+/*
+ * Declaration for the various functions exported by the
+ * mpc86xx_* files. Mostly for use by mpc86xx_setup().
+ */
+
+extern void mpc86xx_restart(char *cmd);
+extern long __init mpc86xx_time_init(void);
+
+extern int __init add_bridge(struct device_node *dev);
+
+extern void __init setup_indirect_pex(struct pci_controller* hose,
+ u32 cfg_addr, u32 cfg_data);
+extern void __init setup_indirect_pex_nomap(struct pci_controller* hose,
+ void __iomem * cfg_addr,
+ void __iomem * cfg_data);
+
+extern struct smp_ops_t smp_8641_ops;
+
+#endif /* __MPC86XX_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
new file mode 100644
index 0000000..d413e95
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -0,0 +1,304 @@
+/*
+ * MPC86xx HPCN board specific routines
+ *
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc86xx.h>
+#include <asm/prom.h>
+#include <mm/mmu_decl.h>
+#include <asm/udbg.h>
+#include <asm/i8259.h>
+
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+unsigned long pci_dram_offset = 0;
+#endif
+
+
+/*
+ * Internal interrupts are all Level Sensitive, and Positive Polarity
+ */
+
+static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: Reserved */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: MCM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PEX1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: PEX2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: Reserved */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: Reserved */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: DUART2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 1 Transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 1 Receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: TSEC 3 transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: TSEC 3 receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: TSEC 3 error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 1 Receive/Transmit Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 2 Transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 2 Receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: TSEC 4 transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: TSEC 4 receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: TSEC 4 error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 2 Receive/Transmit Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32: SRIO error/write-port unit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33: SRIO outbound doorbell */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34: SRIO inbound doorbell */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37: SRIO outbound message unit 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38: SRIO inbound message unit 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39: SRIO outbound message unit 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40: SRIO inbound message unit 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 47: Unused */
+ 0x0, /* External 0: */
+ 0x0, /* External 1: */
+ 0x0, /* External 2: */
+ 0x0, /* External 3: */
+ 0x0, /* External 4: */
+ 0x0, /* External 5: */
+ 0x0, /* External 6: */
+ 0x0, /* External 7: */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: Pixis FPGA */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: ULI 8259 INTR Cascade */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 10: Quad ETH PHY */
+ 0x0, /* External 11: */
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+};
+
+
+void __init
+mpc86xx_hpcn_init_IRQ(void)
+{
+ struct mpic *mpic1;
+ phys_addr_t OpenPIC_PAddr;
+
+ /* Determine the Physical Address of the OpenPIC regs */
+ OpenPIC_PAddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
+
+ /* Alloc mpic structure and per isu has 16 INT entries. */
+ mpic1 = mpic_alloc(OpenPIC_PAddr,
+ MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+ 16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250,
+ mpc86xx_hpcn_openpic_initsenses,
+ sizeof(mpc86xx_hpcn_openpic_initsenses),
+ " MPIC ");
+ BUG_ON(mpic1 == NULL);
+
+ /* 48 Internal Interrupts */
+ mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
+ mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10400);
+ mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10600);
+
+ /* 16 External interrupts */
+ mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10000);
+
+ mpic_init(mpic1);
+
+#ifdef CONFIG_PEX
+ mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL);
+ i8259_init(0, I8259_OFFSET);
+#endif
+}
+
+
+
+#ifdef CONFIG_PCI
+/*
+ * interrupt routing
+ */
+
+int
+mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] = {
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 17 -- PCI Slot 1 */
+ {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 18 -- PCI Slot 2 */
+ {0, 0, 0, 0}, /* IDSEL 19 */
+ {0, 0, 0, 0}, /* IDSEL 20 */
+ {0, 0, 0, 0}, /* IDSEL 21 */
+ {0, 0, 0, 0}, /* IDSEL 22 */
+ {0, 0, 0, 0}, /* IDSEL 23 */
+ {0, 0, 0, 0}, /* IDSEL 24 */
+ {0, 0, 0, 0}, /* IDSEL 25 */
+ {0, 0, 0, 0}, /* IDSEL 26 */
+ {PIRQC, 0, 0, 0}, /* IDSEL 27 -- LAN */
+ {PIRQE, PIRQF, PIRQH, PIRQ7}, /* IDSEL 28 -- USB 1.1 */
+ {PIRQE, PIRQF, PIRQG, 0}, /* IDSEL 29 -- Audio & Modem */
+ {PIRQH, 0, 0, 0}, /* IDSEL 30 -- LPC & PMU*/
+ {PIRQD, 0, 0, 0}, /* IDSEL 31 -- ATA */
+ };
+
+ const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
+}
+
+
+int
+mpc86xx_exclude_device(u_char bus, u_char devfn)
+{
+#if !defined(CONFIG_PEX)
+ if (bus == 0 && PCI_SLOT(devfn) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+#endif
+
+ return PCIBIOS_SUCCESSFUL;
+}
+#endif /* CONFIG_PCI */
+
+
+static void __init
+mpc86xx_hpcn_setup_arch(void)
+{
+ struct device_node *np;
+
+#ifdef CONFIG_SMP
+ phys_addr_t mcm_paddr;
+ void *mcm_vaddr = NULL;
+ unsigned long vaddr;
+#endif
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
+
+ np = of_find_node_by_type(NULL, "cpu");
+ if (np != 0) {
+ unsigned int *fp;
+
+ fp = (int *)get_property(np, "clock-frequency", NULL);
+ if (fp != 0)
+ loops_per_jiffy = *fp / HZ;
+ else
+ loops_per_jiffy = 50000000 / HZ;
+ of_node_put(np);
+ }
+
+#ifdef CONFIG_PEX
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+ add_bridge(np);
+
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = mpc86xx_map_irq;
+ ppc_md.pci_exclude_device = mpc86xx_exclude_device;
+#endif
+
+ printk("HPCN board with 86xx from Freescale Semiconductor\n");
+
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_HDA1;
+#endif
+
+#ifdef CONFIG_SMP
+ /* Release Core 1 in boot holdoff */
+ mcm_paddr = get_immrbase() + MPC86xx_MCM_OFFSET;
+ mcm_vaddr = ioremap(mcm_paddr, MPC86xx_MCM_SIZE);
+
+ vaddr = (unsigned long)mcm_vaddr + MCM_PORT_CONFIG_OFFSET;
+ out_be32((volatile unsigned *)vaddr, CPU_ALL_RELEASED);
+ smp_ops = &smp_8641_ops;
+#endif
+}
+
+
+void
+mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
+{
+ uint pvid, svid, phid1;
+ uint memsize = total_memory;
+
+ pvid = mfspr(SPRN_PVR);
+ svid = mfspr(SPRN_SVR);
+
+ seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
+ seq_printf(m, "Machine\t\t: MPC86xx HPCN Board\n");
+ seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
+ seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+
+ /* Display cpu Pll setting */
+ phid1 = mfspr(SPRN_HID1);
+ seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
+
+ /* Display the amount of memory */
+ seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init mpc86xx_hpcn_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "mpc86xx"))
+ return 1; /* Looks good */
+
+ return 0;
+}
+
+define_machine(mpc86xx_hpcn) {
+ .name = "MPC86xx HPCN",
+ .probe = mpc86xx_hpcn_probe,
+ .setup_arch = mpc86xx_hpcn_setup_arch,
+ .init_IRQ = mpc86xx_hpcn_init_IRQ,
+ .show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
+ .get_irq = mpic_get_irq,
+ .restart = mpc86xx_restart,
+ .time_init = mpc86xx_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
^ permalink raw reply related
* [PATCH 1/10 v2] Add the mpc8641 hpcn Kconfig and Makefiles.
From: Jon Loeliger @ 2006-06-08 21:56 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/Kconfig | 15 ++++++++++-
arch/powerpc/platforms/Makefile | 1 +
arch/powerpc/platforms/86xx/Kconfig | 46 ++++++++++++++++++++++++++++++++++
arch/powerpc/platforms/86xx/Makefile | 7 +++++
4 files changed, 67 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 75ba0ec..2603cd3 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -141,6 +141,15 @@ config PPC_85xx
select FSL_SOC
select 85xx
+config PPC_86xx
+ bool "Freescale 86xx"
+ select 6xx
+ select FSL_SOC
+ select PPC_FPU
+ select ALTIVEC
+ help
+ The Freescale E600 SoCs have 74xx cores.
+
config 40x
bool "AMCC 40x"
@@ -549,6 +558,7 @@ source arch/powerpc/platforms/embedded6x
source arch/powerpc/platforms/4xx/Kconfig
source arch/powerpc/platforms/83xx/Kconfig
source arch/powerpc/platforms/85xx/Kconfig
+source arch/powerpc/platforms/86xx/Kconfig
source arch/powerpc/platforms/8xx/Kconfig
source arch/powerpc/platforms/cell/Kconfig
@@ -780,6 +790,7 @@ config GENERIC_ISA_DMA
config PPC_I8259
bool
+ default y if MPC8641_HPCN
default n
config PPC_INDIRECT_PCI
@@ -802,8 +813,8 @@ config MCA
bool
config PCI
- bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES)
- default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && !PPC_85xx
+ bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx || PPC_86xx || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES)
+ default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && !PPC_85xx && !PPC_86xx
default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
default PCI_QSPAN if !4xx && !CPM2 && 8xx
help
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index c4f6b0d..2928636 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_PPC_CHRP) += chrp/
obj-$(CONFIG_4xx) += 4xx/
obj-$(CONFIG_PPC_83xx) += 83xx/
obj-$(CONFIG_PPC_85xx) += 85xx/
+obj-$(CONFIG_PPC_86xx) += 86xx/
obj-$(CONFIG_PPC_PSERIES) += pseries/
obj-$(CONFIG_PPC_ISERIES) += iseries/
obj-$(CONFIG_PPC_MAPLE) += maple/
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
new file mode 100644
index 0000000..e922406
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -0,0 +1,46 @@
+menu "Platform Support"
+ depends on PPC_86xx
+
+choice
+ prompt "Machine Type"
+ default MPC8641_HPCN
+
+config MPC8641_HPCN
+ bool "Freescale MPC8641 HPCN"
+ help
+ This option enables support for the MPC8641 HPCN board.
+
+endchoice
+
+
+config MPC8641
+ bool
+ select PPC_INDIRECT_PCI
+ select PPC_UDBG_16550
+ default y if MPC8641_HPCN
+
+config MPIC
+ bool
+ default y
+
+config PPC_INDIRECT_PCI_BE
+ bool
+ depends on PPC_86xx
+ default y
+
+config PEX
+ bool "PCI Express support"
+ depends on PCI && PPC_86xx
+ default y
+
+config I8259_LEVEL_TRIGGER
+ bool
+ depends on MPC8641_HPCN
+ default y
+
+config PPC_STD_MMU
+ bool
+ depends on PPC_86xx
+ default y
+
+endmenu
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
new file mode 100644
index 0000000..1bd1f43
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for the PowerPC 86xx linux kernel.
+#
+
+obj-$(CONFIG_PPC_86xx) += misc.o
+obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o mpc8641_hpcn.o
+obj-$(CONFIG_PCI) += pci.o pex.o
^ permalink raw reply related
* [PATCH 0/10] Version 2 -- Add MPC8641 HPCN Platform
From: Jon Loeliger @ 2006-06-08 21:54 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
This is the second posting of a series of patches
that introduces the MPC8641 HPCN platform. This
version corrects all of the suggestions from Kumar,
and shows an ACK from Jeff Garzik for the netdev
related parts.
Please consider this for addition into the 2.6.18 queue.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Jeff Brown <Jeff.Brown@freescale.com>
Signed-off-by: Kriston Carson <KristonCarson@freescale.com>
1)
arch/powerpc/Kconfig | 15
arch/powerpc/platforms/Makefile | 1
arch/powerpc/platforms/86xx/Kconfig | 46 +
arch/powerpc/platforms/86xx/Makefile | 7
2)
arch/powerpc/platforms/86xx/misc.c | 51 +
arch/powerpc/platforms/86xx/mpc8641_hpcn.c | 52 ++
arch/powerpc/platforms/86xx/mpc8641_hpcn.h | 54 ++
arch/powerpc/platforms/86xx/mpc86xx.h | 31 +
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 304 +++++++++
3)
arch/powerpc/platforms/86xx/pci.c | 213 ++++++
arch/powerpc/platforms/86xx/pex.c | 173 +++++
4)
arch/powerpc/kernel/cpu_setup_6xx.S | 2
5)
arch/powerpc/kernel/cputable.c | 12
arch/powerpc/kernel/head_32.S | 15
arch/powerpc/sysdev/i8259.c | 5
6)
include/asm-powerpc/immap_86xx.h | 199 ++++++
include/asm-powerpc/irq.h | 88 +++
include/asm-powerpc/mpc86xx.h | 47 +
7)
arch/powerpc/configs/mpc8641_hpcn_defconfig | 920 +++++++++++++++++++++++++++
8)
drivers/net/Kconfig | 6
drivers/net/phy/Kconfig | 5
drivers/net/phy/Makefile | 1
drivers/net/phy/vitesse.c | 112 +++
9)
arch/powerpc/kernel/prom.c | 13
10)
drivers/i2c/busses/Kconfig | 4
25 files changed, 2367 insertions(+), 9 deletions(-)
^ permalink raw reply
* Re: help with inittab
From: Wolfgang Denk @ 2006-06-08 21:42 UTC (permalink / raw)
To: Chris Dumoulin; +Cc: linuxppc-embedded
In-Reply-To: <44888B92.40409@ics-ltd.com>
In message <44888B92.40409@ics-ltd.com> you wrote:
> I am using the linux kernel 2.6.15 and initrd ramdisk image from ELDK
> 4.0. Currently, I seem to be able to boot without errors, but after the
> root filesystem is mounted, things just stop.
And what's your console device? Are you passing any console=
arguments on the command line? Is the corresponding device entry
present in the /dev/directory?
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Sometimes a feeling is all we humans have to go on.
-- Kirk, "A Taste of Armageddon", stardate 3193.9
^ permalink raw reply
* Re: [PATCH 9/10] Add Vitesse 8244 PHY for MPC8641 HPCN platform.
From: Jeff Garzik @ 2006-06-08 21:01 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev@ozlabs.org, Paul Mackerras, netdev
In-Reply-To: <1149799949.23938.264.camel@cashmere.sps.mot.com>
Jon Loeliger wrote:
> On Thu, 2006-06-08 at 15:46, Jeff Garzik wrote:
>
>> I leave it up to you and Paul to coordinate, then :)
>>
>> I'm fine with the patch, and if its better to merge via linuxppc.git,
>> that's OK with me. If you would prefer to send it via my tree, to go
>> ahead and get it in, that's fine too.
>
> OK, thanks. I need to re-submit 5 of 10 parts for
> other cleanup issues anyway, so I think I will:
>
> - Resubmit the entire patch set,
> - Resubmit netdev parts to Paul, and netdev with
> an added ACK: by you line (OK?),
OK with me. Since we use a specific header to indicate such, that would be:
Acked-by: Jeff Garzik <jeff@garzik.org>
^ permalink raw reply
* Re: [PATCH 9/10] Add Vitesse 8244 PHY for MPC8641 HPCN platform.
From: Jon Loeliger @ 2006-06-08 20:52 UTC (permalink / raw)
To: Jeff Garzik; +Cc: linuxppc-dev@ozlabs.org, Paul Mackerras, netdev
In-Reply-To: <44888CB3.1060507@garzik.org>
On Thu, 2006-06-08 at 15:46, Jeff Garzik wrote:
> I leave it up to you and Paul to coordinate, then :)
>
> I'm fine with the patch, and if its better to merge via linuxppc.git,
> that's OK with me. If you would prefer to send it via my tree, to go
> ahead and get it in, that's fine too.
OK, thanks. I need to re-submit 5 of 10 parts for
other cleanup issues anyway, so I think I will:
- Resubmit the entire patch set,
- Resubmit netdev parts to Paul, and netdev with
an added ACK: by you line (OK?),
- Throw myself on the mercy of "Help us Obi-wan Mackerras"
and see what he says when he wakes up!
Thanks!
jdl
^ permalink raw reply
* Re: help with inittab
From: Steve Iribarne (GMail) @ 2006-06-08 20:49 UTC (permalink / raw)
To: Chris Dumoulin; +Cc: linuxppc-embedded
In-Reply-To: <44888B92.40409@ics-ltd.com>
On 6/8/06, Chris Dumoulin <cdumoulin@ics-ltd.com> wrote:
> I am using the linux kernel 2.6.15 and initrd ramdisk image from ELDK
> 4.0. Currently, I seem to be able to boot without errors, but after the
> root filesystem is mounted, things just stop.
>
> I'm guessing that my problems are related to the setup of the RFS, and
> more specifically, my inittab file. Here is the output I get at boot time:
> Linux version 2.6.15 (cdumoulin@localhost.localdomain) (gcc version
> 4.0.0 (DENX ELDK 4.0 4.0.0)) #167 PREEMPT Thu Jun 8 6Built 1 zonelists
> Kernel command line: console=ttyS0,57600 ip=off
> PID hash table entries: 512 (order: 9, 8192 bytes)
> Console: colour dummy device 80x25
> Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
> Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
> Memory: 62120k available (968k kernel code, 272k data, 76k init, 0k highmem)
> Mount-cache hash table entries: 512
> checking if image is initramfs...it isn't (no cpio magic); looks like an
> initrd
> Freeing initrd memory: 1404k freed
> Linux NoNET1.0 for Linux 2.6
> io scheduler noop registered
> io scheduler anticipatory registered
> io scheduler deadline registered
> io scheduler cfq registered
> Software Watchdog Timer: 0.07 initialized. soft_noboot=0 soft_margin=60
> sec (nowayout= 0)
> ipmi message handler version 38.0
> ipmi device interface
> IPMI Watchdog: driver initialized
> i8042.c: No controller found.
> Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
> serial8250: ttyS0 at MMIO 0x0 (irq = 24) is a 16550A
> RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
> loop: loaded (max 8 devices)
> mice: PS/2 mouse device common for all mice
> RAMDISK: Compressed image found at block 0
> VFS: Mounted root (ext2 filesystem).
>
> And here is my initttab file:
> ::sysinit:/etc/rc.sh
> ::askfirst:/bin/sh
> ::ctrlaltdel:/sbin/reboot
> ::shutdown:/sbin/swapoff -a
> ::shutdown:/bin/umount -a -r
> ::restart:/sbin/init
>
Doesn't seem like you are respawning any login stuff? Where are your
tty's? Change the askfirst to /bin/sh and you should get a shell at
the start assuming you have /bin/sh.
> Any ideas would be appreciated.
>
> Cheers,
> Chris Dumoulin
> --
> *--Christopher Dumoulin--*
> Software Team Leader
>
> <http://ics-ltd.com/>
> <http://ics-ltd.com/>
>
> Interactive Circuits and Systems Ltd.
> 5430 Canotek Road
> Ottawa, ON
> K1J 9G2
> (613)749-9241
> 1-800-267-9794 (USA only)
>
> ------------------------------------------------------------------------
> This e-mail is private and confidential and is for the addressee only.
> If misdirected, please notify us by telephone and confirm that it has
> been deleted from your system and any hard copies destroyed. You are
> strictly prohibited from using, printing, distributing or disseminating
> it or any information contained in it save to the intended recipient.
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
^ permalink raw reply
* Re: [PATCH 9/10] Add Vitesse 8244 PHY for MPC8641 HPCN platform.
From: Jeff Garzik @ 2006-06-08 20:46 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev@ozlabs.org, Paul Mackerras, netdev
In-Reply-To: <1149799209.23938.256.camel@cashmere.sps.mot.com>
Jon Loeliger wrote:
> On Thu, 2006-06-08 at 15:36, Jeff Garzik wrote:
>> Is it dependent on other stuff in Paul's tree?
>
> Yes, very much so. Most of this patch set is an
> entirely new PPC board port against his arch/powerpc
> basis. The new PHY is incidentally on that board,
> but the patches for its introduction could be
> introduced through the netdev tree if needed.
> It would just need to be coordinated some. I am,
> of course, willing to work it either way as needed.
I leave it up to you and Paul to coordinate, then :)
I'm fine with the patch, and if its better to merge via linuxppc.git,
that's OK with me. If you would prefer to send it via my tree, to go
ahead and get it in, that's fine too.
Jeff
^ permalink raw reply
* Re: [PATCH 9/10] Add Vitesse 8244 PHY for MPC8641 HPCN platform.
From: Jon Loeliger @ 2006-06-08 20:40 UTC (permalink / raw)
To: Jeff Garzik; +Cc: linuxppc-dev@ozlabs.org, netdev
In-Reply-To: <44888A37.3090401@garzik.org>
On Thu, 2006-06-08 at 15:36, Jeff Garzik wrote:
> Is it dependent on other stuff in Paul's tree?
Yes, very much so. Most of this patch set is an
entirely new PPC board port against his arch/powerpc
basis. The new PHY is incidentally on that board,
but the patches for its introduction could be
introduced through the netdev tree if needed.
It would just need to be coordinated some. I am,
of course, willing to work it either way as needed.
jdl
^ permalink raw reply
* help with inittab
From: Chris Dumoulin @ 2006-06-08 20:41 UTC (permalink / raw)
To: linuxppc-embedded
I am using the linux kernel 2.6.15 and initrd ramdisk image from ELDK
4.0. Currently, I seem to be able to boot without errors, but after the
root filesystem is mounted, things just stop.
I'm guessing that my problems are related to the setup of the RFS, and
more specifically, my inittab file. Here is the output I get at boot time:
Linux version 2.6.15 (cdumoulin@localhost.localdomain) (gcc version
4.0.0 (DENX ELDK 4.0 4.0.0)) #167 PREEMPT Thu Jun 8 6Built 1 zonelists
Kernel command line: console=ttyS0,57600 ip=off
PID hash table entries: 512 (order: 9, 8192 bytes)
Console: colour dummy device 80x25
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 62120k available (968k kernel code, 272k data, 76k init, 0k highmem)
Mount-cache hash table entries: 512
checking if image is initramfs...it isn't (no cpio magic); looks like an
initrd
Freeing initrd memory: 1404k freed
Linux NoNET1.0 for Linux 2.6
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
Software Watchdog Timer: 0.07 initialized. soft_noboot=0 soft_margin=60
sec (nowayout= 0)
ipmi message handler version 38.0
ipmi device interface
IPMI Watchdog: driver initialized
i8042.c: No controller found.
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
serial8250: ttyS0 at MMIO 0x0 (irq = 24) is a 16550A
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
loop: loaded (max 8 devices)
mice: PS/2 mouse device common for all mice
RAMDISK: Compressed image found at block 0
VFS: Mounted root (ext2 filesystem).
And here is my initttab file:
::sysinit:/etc/rc.sh
::askfirst:/bin/sh
::ctrlaltdel:/sbin/reboot
::shutdown:/sbin/swapoff -a
::shutdown:/bin/umount -a -r
::restart:/sbin/init
Any ideas would be appreciated.
Cheers,
Chris Dumoulin
--
*--Christopher Dumoulin--*
Software Team Leader
<http://ics-ltd.com/>
<http://ics-ltd.com/>
Interactive Circuits and Systems Ltd.
5430 Canotek Road
Ottawa, ON
K1J 9G2
(613)749-9241
1-800-267-9794 (USA only)
------------------------------------------------------------------------
This e-mail is private and confidential and is for the addressee only.
If misdirected, please notify us by telephone and confirm that it has
been deleted from your system and any hard copies destroyed. You are
strictly prohibited from using, printing, distributing or disseminating
it or any information contained in it save to the intended recipient.
^ permalink raw reply
* Re: [PATCH 9/10] Add Vitesse 8244 PHY for MPC8641 HPCN platform.
From: Jeff Garzik @ 2006-06-08 20:36 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev@ozlabs.org, netdev
In-Reply-To: <1149797603.23938.251.camel@cashmere.sps.mot.com>
Jon Loeliger wrote:
> On Thu, 2006-06-08 at 14:34, Jeff Garzik wrote:
>> Jon Loeliger wrote:
>>> Signed-off-by: Kriston Carson <KristonCarson@freescale.com>
>>> Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
>>> Signed-off-by: Jon Loeliger <jdl@freescale.com>
>> ACK, but patch does not apply to netdev-2.6.git#upstream.
>>
>> Jeff
>
> Thanks, Jeff.
>
> Are you willing to take the netdev parts as-is, then?
> Or would you like me to reformat the netdev parts to
> apply against the netdev-2.6.git#upstream branch?
> The patch is currently for the Paul Mackerras powerpc.git
> tree as it stands now. Should we apply it through that
> path now as you have ACK'ed it?
Is it dependent on other stuff in Paul's tree?
Normally this should come through netdev-2.6.git#upstream...
Jeff
^ permalink raw reply
* Re: [PATCH 9/10] Add Vitesse 8244 PHY for MPC8641 HPCN platform.
From: Jon Loeliger @ 2006-06-08 20:13 UTC (permalink / raw)
To: Jeff Garzik; +Cc: linuxppc-dev@ozlabs.org, netdev
In-Reply-To: <44887BD3.7000009@garzik.org>
On Thu, 2006-06-08 at 14:34, Jeff Garzik wrote:
> Jon Loeliger wrote:
> > Signed-off-by: Kriston Carson <KristonCarson@freescale.com>
> > Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
> > Signed-off-by: Jon Loeliger <jdl@freescale.com>
>
> ACK, but patch does not apply to netdev-2.6.git#upstream.
>
> Jeff
Thanks, Jeff.
Are you willing to take the netdev parts as-is, then?
Or would you like me to reformat the netdev parts to
apply against the netdev-2.6.git#upstream branch?
The patch is currently for the Paul Mackerras powerpc.git
tree as it stands now. Should we apply it through that
path now as you have ACK'ed it?
Thanks,
jdl
^ permalink raw reply
* RE: MPC5200B SPI PSC3 Problem
From: Trueskew @ 2006-06-08 19:50 UTC (permalink / raw)
To: 'John Rigby'; +Cc: linuxppc-embedded
In-Reply-To: <4b73d43f0606080911x5607f1fakbeee6a9b6e2cd6f1@mail.gmail.com>
Thanks John. I actually decided not to sleep last night and figured all of
that out, including the documentation conflict, and now I'm working. I
wasn't even sure my post work, I didn't receive it, but maybe the sender is
left out. I should've slept and waited for your reply.
I'm still a little confused though. I re-checked code from Freescale and
references and patches listed or mentioned here, and they all use either
0x06 or 0x07 for the GPIO port config, depending on whether they want MCLK
or not. The included SPI transfer routines use the PSC3 FIFO mechanism to
send and receive data. The biggest light bulb shot for how I figured out
what was going on was because I decided to hang a scope off the codec lines
of the PSC3, and that's where I found the data I was sending out. The
MPC5200B vs. MPC5200 doc from Freescale doesn't mention this area as
changed, so how do so many 5200 SPI solutions go this route? I wondered if
they worked on reference platforms that were using the codec lines to drive
SPI, which looks like it's doable, but some solutions advertise themselves
as MPC5200 SPI drivers. Another possibility is that they weren't tested.
And yet another, the one I'm concerned with, is that I'm still
misunderstanding something... hence the paragraph.
But in any case, thanks again, I appreciate the help.
-----Original Message-----
From: John Rigby [mailto:jcrigby@gmail.com]
Sent: Thursday, June 08, 2006 9:11 AM
To: Trueskew
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: MPC5200B SPI PSC3 Problem
Here's an include file that goes with file in the last email.
On 6/8/06, John Rigby <jcrigby@gmail.com> wrote:
> There seems to be a conflict between two sections of the 5200 User manual.
> In section 7.3 where port_config is documented the PSC3 configuration
> bits (20:23) defined as:
>
> 0000 = All PSC3 pins are GPIOs
> 0001 = USB2 on PSC3, no GPIOs available, see Note 3 001X = Reserved
> 0100 = UART functionality without CD
> 0101 = UARTe functionality with CD
> 0110 = CODEC3 functionality
> 0111 = CODEC3 functionality (with MCLK) 100X = SPI 101X = Reserved
> 1100 = SPI with UART3
> 1101 = SPI with UART3e
> 111X = SPI with CODEC3
>
> but in the psc chapter in table 15-85 it says to set port config to
> 0x00000600 but the description says "Select the Pin-Muxing for PSC3
> Codec mode"
>
> It appears that table 15-85 is wrong.
>
> I have attached some spi code that is embedded in a touchscreen
> driver. It might be helpful.
>
>
>
>
>
> On 6/7/06, Trueskew <trueskew@gmail.com> wrote:
> >
> >
> > We have an AIC26 codec connected to our Lite5200B platform via J21.
> > I've used MPC5200BUG to configure PSC3 as an SPI master, along with
> > some samples I've found online (including here) and some I received from
Freescale.
> > Although the transfers seem to be working as expected (please see
> > the output file at the end of this message), I get only 0xffff back.
> > This occurs whether or not the device is attached to J21. A scope
> > shows that PSC3_8
> > (SPI_SS) and PSC3_9 (SPI_CLK) are low at all times, and I'm
> > concerned I'm still doing something wrong with respect to enabling SPI
over PSC3.
> >
> > I'm including my driver initialization code, my write code, and
> > output showing the write behavior. If someone could comment on it,
> > I would greatly appreciate it... or if someone flat out has code to
> > do this, I'd be happy to take it from you. I've seen a few
> > variations, but whether I use them directly or modify them as I need
> > to, I can't seem to get past this. Of course, any other suggestions are
welcome.
> >
> > Thanks.
> > Sal
> >
> > --------------------------------------------------------------------
> > -------
> > Initialization Code
> > --------------------------------------------------------------------
> > ------- #define GPIO_PSC3_PORT_CONFIG_MASK 0x00000f00 #ifdef
> > SPI_USE_MCLK
> > #define GPIO_PSC3_PORT_CONFIG 0x00000700 /* PSC3 mode with mclk
*/
> > #else /* SPI_USE_MCLK */
> > #define GPIO_PSC3_PORT_CONFIG 0x00000600 /* PSC3 mode */
> > #endif /* SPI_USE_MCLK */
> >
> > #define CDM_PSC3_MCLK_ENABLE 0x00000080
> > #define CDM_PSC3_MCLK_CONFIG 0x8020 /* Divide Fvco ftom 528
to
> > 16Mhz */
> >
> > #define PSC3_SICR_REG_VALUE 0x0280f000 /* 16-bit select Codec
SPI
> > master mode, msb
> > first,
> > UseEOF=1.
> > GenClk=1, SIM,
> > CPOL and CPHA are
> > function input */
> > ...
> > /* Select the Pin-Muxing for PSC3 Codec mode */
> > gpio = (struct mpc52xx_gpio *) ioremap(MPC52xx_GPIO,
> > sizeof(struct mpc52xx_gpio));
> > if(gpio)
> > {
> > port_config = gpio->port_config;
> > port_config &= ~GPIO_PSC3_PORT_CONFIG_MASK;
> > port_config |= GPIO_PSC3_PORT_CONFIG;
> > gpio->port_config = port_config;
> > iounmap(gpio);
> > }
> > else
> > {
> > return(-1);
> > }
> >
> > #ifdef SPI_USE_MCLK
> > /* PSC clock enable */
> > g_pCDM->clk_enables |= CDM_PSC3_MCLK_ENABLE;
> > g_pCDM->mclken_div_psc3 = CDM_PSC3_MCLK_CONFIG; #endif /*
> > SPI_USE_MCLK */
> >
> > /* Disable rx and tx */
> > g_pPSC->command = MPC52xx_PSC_RST_RX;
> > g_pPSC->command = MPC52xx_PSC_RST_TX;
> > g_pPSC->command = MPC52xx_PSC_SEL_MODE_REG_1;
> > g_pPSC->command = MPC52xx_PSC_RST_ERR_STAT;
> > g_pPSC->command = MPC52xx_PSC_RX_DISABLE |
> > MPC52xx_PSC_TX_DISABLE;
> >
> > g_pPSC->mode = 0;
> > g_pPSC->sicr = PSC3_SICR_REG_VALUE;
> >
> > #ifdef SPI_USE_MCLK
> > g_pPSC->ccr=0x0703; /* set SCK and DSCKL delay */
> > #else /* SPI_USE_MCLK */
> > g_pPSC->ccr=0x0003; /* set SCK and DSCKL delay must be > 2 */
> > #endif /* SPI_USE_MCLK */
> >
> > g_pPSC->ctur=0x00; /* Set DTL delay 2us */
> > g_pPSC->ctlr=0x84;
> >
> > g_pPSC->rfalarm=100; /* Alarm values taken from SPI example
sample
> > */
> > g_pPSC->tfalarm=1;
> >
> > g_pPSC->rfcntl &= 0xf8; /* 0 byte granularity */
> > g_pPSC->tfcntl = 1;
> >
> > /* Enable rx & tx */
> > g_pPSC->command = MPC52xx_PSC_RST_RX;
> > g_pPSC->command = MPC52xx_PSC_RST_TX;
> > g_pPSC->command = MPC52xx_PSC_SEL_MODE_REG_1;
> > g_pPSC->command = MPC52xx_PSC_RST_ERR_STAT;
> > g_pPSC->command = MPC52xx_PSC_RX_ENABLE | MPC52xx_PSC_TX_ENABLE;
> >
> > --------------------------------------------------------------------
> > -------
> > Write code
> > --------------------------------------------------------------------
> > ------- static int mpc52xx_spi_transfer(u16 *p_usBuffer, u16
> > p_usCount) {
> > u16 usIndex, usTemp;
> >
> >
> > printk("------------------------------------------------------\n");
> > printk("Entry: psc=%x status=%04x tfstat=%04x rfstat=%04x
> > mode=%02x\n tfnum %3d rfnum %3d\n",
> >
> >
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
> > g_pPSC->tfnum, g_pPSC->rfnum);
> > g_pPSC->command = MPC52xx_PSC_RST_RX;
> > g_pPSC->command = MPC52xx_PSC_RST_TX;
> > g_pPSC->command = MPC52xx_PSC_SEL_MODE_REG_1;
> > g_pPSC->command = MPC52xx_PSC_RST_ERR_STAT;
> > g_pPSC->command = MPC52xx_PSC_RX_ENABLE | MPC52xx_PSC_TX_ENABLE;
> > printk("TX-RX Enable: psc=%x status=%04x tfstat=%04x rfstat=%04x
> > mode=%02x\n tfnum %3d rfnum %3d\n",
> >
> >
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
> > g_pPSC->tfnum, g_pPSC->rfnum);
> >
> > /* Clean out the read FIFO */
> > usIndex = 0;
> > while(g_pPSC->mpc52xx_psc_status & MPC52xx_PSC_SR_RXRDY)
> > {
> > usTemp = g_pPSC->mpc52xx_psc_buffer_16;
> > printk("Flushing Rx FIFO: psc=%x status=%04x tfstat=%04x
rfstat=%04x
> > mode=%02x\n tfnum %3d rfnum %3d\n",
> >
> >
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
> > g_pPSC->tfnum, g_pPSC->rfnum);
> > udelay(100000);
> > udelay(100000);
> > udelay(100000);
> > udelay(100000);
> > udelay(100000);
> > usIndex++;
> > if(usIndex == 10) return(-1);
> > }
> >
> > /* Send out the buffer */
> > g_pPSC->command = MPC52xx_PSC_RX_ENABLE | MPC52xx_PSC_TX_DISABLE;
> > for(usIndex=0; usIndex<p_usCount; usIndex++)
> > {
> > printk("Sending %04x: psc=%x status=%04x tfstat=%04x rfstat=%04x
> > mode=%02x\n tfnum %3d rfnum %3d\n",
> > p_usBuffer[usIndex],
> >
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
> > g_pPSC->tfnum, g_pPSC->rfnum);
> > g_pPSC->mpc52xx_psc_buffer_16 = p_usBuffer[usIndex];
> > printk("Sent: psc=%x status=%04x tfstat=%04x rfstat=%04x
> > mode=%02x\n tfnum %3d rfnum %3d\n",
> >
> >
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
> > g_pPSC->tfnum, g_pPSC->rfnum);
> > }
> > g_pPSC->command = MPC52xx_PSC_RX_ENABLE | MPC52xx_PSC_TX_ENABLE;
> > usTemp = 0;
> > while(g_pPSC->tfnum)
> > {
> > printk("TFNUM Wait: psc=%x status=%04x tfstat=%04x rfstat=%04x
> > mode=%02x\n tfnum %3d rfnum %3d\n",
> >
> >
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
> > g_pPSC->tfnum, g_pPSC->rfnum);
> > udelay(100000);
> > udelay(100000);
> > udelay(100000);
> > udelay(100000);
> > udelay(100000);
> > usTemp++;
> > if(usTemp == 10) return(-1);
> > };
> > printk("TxRDY: psc=%x status=%04x tfstat=%04x rfstat=%04x
> > mode=%02x\n tfnum %3d rfnum %3d\n",
> >
> >
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
> > g_pPSC->tfnum, g_pPSC->rfnum);
> > for(usIndex=0; usIndex<p_usCount; usIndex++)
> > {
> > usTemp = 0;
> > while(!(g_pPSC->mpc52xx_psc_status &
> > MPC52xx_PSC_SR_RXRDY))
> > {
> > printk("RxRDY Wait: psc=%x status=%04x tfstat=%04x
rfstat=%04x
> > mode=%02x\n tfnum %3d rfnum %3d\n",
> >
> >
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
> > g_pPSC->tfnum, g_pPSC->rfnum);
> > udelay(100000);
> > udelay(100000);
> > udelay(100000);
> > udelay(100000);
> > udelay(100000);
> > usTemp++;
> > if(usTemp == 10) return(-1);
> > };
> > printk("RxRDY: psc=%x status=%04x tfstat=%04x rfstat=%04x
> > mode=%02x\n tfnum %3d rfnum %3d\n",
> >
> >
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
> > g_pPSC->tfnum, g_pPSC->rfnum);
> > p_usBuffer[usIndex] = g_pPSC->mpc52xx_psc_buffer_16;
> > printk(" Received %04x\n", p_usBuffer[usIndex]);
> > }
> >
> > printk("EXIT: psc=%x status=%04x tfstat=%04x rfstat=%04x
> > mode=%02x\n tfnum %3d rfnum %3d\n",
> >
> >
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
> > g_pPSC->tfnum, g_pPSC->rfnum);
> > return(usIndex);
> > }
> >
> >
> > --------------------------------------------------------------------
> > -------
> > Output
> > --------------------------------------------------------------------
> > ------- The lines below are a capture of register settings from my
> > driver, along with output lines when trying to write 16 bit words to
> > our device. This output is consistent whether the device is
> > connected or not (via J21). Basic operation, delimited by
> > "------...---":
> >
> > - Disable TX, Enable RX (despite the "TX-RX Enable" heading)
> > - Send word 1
> > - Send word 2
> > - Enable TX, Enable RX
> > - Wait for tfnum == 0
> > - Receive data
> >
> > port_config=91051624 sicr=0280f000 clk_enables=00ffffff
> > div_psc3=800f
> > ------------------------------------------------------
> > Entry: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=33
> > tfnum 0 rfnum 0
> > TX-RX Enable: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=33
> > tfnum 0 rfnum 0
> > Sending 0880: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=07
> > tfnum 0 rfnum 0
> > Sent: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
> > tfnum 2 rfnum 0
> > Sending bb00: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
> > tfnum 2 rfnum 0
> > Sent: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
> > tfnum 4 rfnum 0
> > TFNUM Wait: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
> > tfnum 2 rfnum 0
> > TxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
> > tfnum 0 rfnum 4
> > RxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
> > tfnum 0 rfnum 4
> > Received ffff
> > RxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
> > tfnum 0 rfnum 2
> > Received ffff
> > EXIT: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=07
> > tfnum 0 rfnum 0
> > ------------------------------------------------------
> > Entry: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=07
> > tfnum 0 rfnum 0
> > TX-RX Enable: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=33
> > tfnum 0 rfnum 0
> > Sending 8820: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=07
> > tfnum 0 rfnum 0
> > Sent: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
> > tfnum 2 rfnum 0
> > Sending 0000: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
> > tfnum 2 rfnum 0
> > Sent: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
> > tfnum 4 rfnum 0
> > TFNUM Wait: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
> > tfnum 2 rfnum 0
> > TxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
> > tfnum 0 rfnum 4
> > RxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
> > tfnum 0 rfnum 4
> > Received ffff
> > RxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
> > tfnum 0 rfnum 2
> > Received ffff
> > EXIT: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=07
> > tfnum 0 rfnum 0
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >
> >
>
>
>
^ permalink raw reply
* Re: [PATCH 9/10] Add Vitesse 8244 PHY for MPC8641 HPCN platform.
From: Jeff Garzik @ 2006-06-08 19:34 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev@ozlabs.org, netdev
In-Reply-To: <1149720298.23938.207.camel@cashmere.sps.mot.com>
Jon Loeliger wrote:
> Signed-off-by: Kriston Carson <KristonCarson@freescale.com>
> Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
> Signed-off-by: Jon Loeliger <jdl@freescale.com>
ACK, but patch does not apply to netdev-2.6.git#upstream.
Jeff
^ permalink raw reply
* Re: does Gianfar Ethernet Controller Version 1.1 support MARVELL 88E1111?
From: Andy Fleming @ 2006-06-08 19:25 UTC (permalink / raw)
To: Guo Jaffe; +Cc: Linuxppc-embedded
In-Reply-To: <BAY113-F70D5359537D7DC16B4678988B0@phx.gbl>
On Jun 8, 2006, at 12:51, Guo Jaffe wrote:
> Hi Andy,
>
> Thank you for your information. So the driver is not the issue, but
> better to upgraded.
>
> I will check the board once more. The PHY doesn't work because the
> 8bit bus between MAC and PHY is locked(TX_EN and RX_DV all disabled
> from the scope's view) and also you can't see any signals exist at
> the Magnetic side(nor LED signals). It seems that only MDC/MDIO and
> CLOCK reference pin works. The PHY's ID must be read from MDC/MDIO
> interface and Clocks are right showed on the scope.
But what error are you getting? What are the symptoms of your
problem? The GMII interface (the 8-bit bus) is inconsequential to
PHY configuration and management. Only the MDC/MDIO bus is used.
Therefore the PHY id should be quite readable. What version of Linux
are you using? Please describe what the kernel prints out when you
boot, and when you try to bring up the interface (assuming you don't
do that at boot).
Andy
^ permalink raw reply
* Re: VFS: Cannot open root device ...
From: Steve Iribarne (GMail) @ 2006-06-08 18:39 UTC (permalink / raw)
To: Chris Dumoulin; +Cc: linuxppc-embedded
In-Reply-To: <44885C45.7020009@ics-ltd.com>
On 6/8/06, Chris Dumoulin <cdumoulin@ics-ltd.com> wrote:
> I'm trying to port a 2.6 kernel to a V2Pro-based board that I've got. I
> get the following output when trying to boot:
>
> RAMDISK: Compressed image found at block 0
> VFS: Mounted root (ext2 filesystem).
> VFS: Cannot open root device "<NULL>" or unknown-block(0,0)
> Please append a correct "root=" boot option
> Kernel panic - not syncing: VFS: Unable to mount root fs on
> unknown-block(0,0)
What boot loader are you using? In the boot loader where does it
think the root fs is located? My guess is /dev/ram0 or something like
that?
So I'd check your ramdisk to see that it has a /dev/ram0.
Make sure you have rights to it.
-stv
>
> I'm trying to use an initrd RAMDISK, and I've made sure that RAMDISK and
> initrd support are both enabled in the kernel configuration. Any ideas
> would be appreciated.
>
> Cheers,
> Chris Dumoulin
> --
> *--Christopher Dumoulin--*
> Software Team Leader
>
> <http://ics-ltd.com/>
> <http://ics-ltd.com/>
>
> Interactive Circuits and Systems Ltd.
> 5430 Canotek Road
> Ottawa, ON
> K1J 9G2
> (613)749-9241
> 1-800-267-9794 (USA only)
>
> ------------------------------------------------------------------------
> This e-mail is private and confidential and is for the addressee only.
> If misdirected, please notify us by telephone and confirm that it has
> been deleted from your system and any hard copies destroyed. You are
> strictly prohibited from using, printing, distributing or disseminating
> it or any information contained in it save to the intended recipient.
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
^ permalink raw reply
* Re: does Gianfar Ethernet Controller Version 1.1 support MARVELL 88E1111?
From: Guo Jaffe @ 2006-06-08 17:51 UTC (permalink / raw)
To: afleming; +Cc: Linuxppc-embedded
In-Reply-To: <912A1A11-36AB-4E68-BC29-7F584270C4F0@freescale.com>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=gb2312; format=flowed, Size: 1805 bytes --]
Hi Andy,
Thank you for your information. So the driver is not the issue, but better
to upgraded.
I will check the board once more. The PHY doesn't work because the 8bit bus
between MAC and PHY is locked(TX_EN and RX_DV all disabled from the scope's
view) and also you can't see any signals exist at the Magnetic side(nor LED
signals). It seems that only MDC/MDIO and CLOCK reference pin works. The
PHY's ID must be read from MDC/MDIO interface and Clocks are right showed
on the scope.
Best Regards,
Jaffe
>From: Andy Fleming <afleming@freescale.com>
>To: 郁\x7f 剑非 <jianfei616@hotmail.com>
>CC: Linuxppc-embedded@ozlabs.org
>Subject: Re: does Gianfar Ethernet Controller Version 1.1 support MARVELL
88E1111?
>Date: Thu, 8 Jun 2006 11:15:32 -0500
>
>
>On Jun 8, 2006, at 02:43, 郁\x7f 剑非 wrote:
>
>>Hi all,
>>I'm debugging my board with MPC 8540 and marvell 88e1111 designed
>>on it.
>>I'm sure the hardware connection is correct, and the phy's ID could
>> be read
>>through terminal port. But anyway, phy can not work. I wonder if it
>> is the
>>driver's problem? Since the Gianfar Ethernet Controller Version 1.1
>>surpport 88e1011s, but some 88e1111's registers are different from
>>88e1011s'. Actually I'm a new guy to Linux. Has anybody ever used
>>88e1111
>>phy in Linux envirenmemt? Please
>>give me some points. Thank you!
>>I have read the Gianfar ethernet controller driver, but it's
>>difficult for
>>me to find out the sofware flow.
>
>
>It would be better if you upgraded to the latest kernel. The PHY
>subsystem in the driver has changed significantly since version 1.1
>of the driver. What leads you to believe that the PHY doesn't work?
> What errors do you see? I'm fairly certain the 88e1111 works
>with the 88e1011 driver, but it's been a while.
>
^ permalink raw reply
* VFS: Cannot open root device ...
From: Chris Dumoulin @ 2006-06-08 17:20 UTC (permalink / raw)
To: linuxppc-embedded
I'm trying to port a 2.6 kernel to a V2Pro-based board that I've got. I
get the following output when trying to boot:
RAMDISK: Compressed image found at block 0
VFS: Mounted root (ext2 filesystem).
VFS: Cannot open root device "<NULL>" or unknown-block(0,0)
Please append a correct "root=" boot option
Kernel panic - not syncing: VFS: Unable to mount root fs on
unknown-block(0,0)
I'm trying to use an initrd RAMDISK, and I've made sure that RAMDISK and
initrd support are both enabled in the kernel configuration. Any ideas
would be appreciated.
Cheers,
Chris Dumoulin
--
*--Christopher Dumoulin--*
Software Team Leader
<http://ics-ltd.com/>
<http://ics-ltd.com/>
Interactive Circuits and Systems Ltd.
5430 Canotek Road
Ottawa, ON
K1J 9G2
(613)749-9241
1-800-267-9794 (USA only)
------------------------------------------------------------------------
This e-mail is private and confidential and is for the addressee only.
If misdirected, please notify us by telephone and confirm that it has
been deleted from your system and any hard copies destroyed. You are
strictly prohibited from using, printing, distributing or disseminating
it or any information contained in it save to the intended recipient.
^ permalink raw reply
* Re: A Couple of 2.6/Xilinx Questions
From: Grant Likely @ 2006-06-08 17:17 UTC (permalink / raw)
To: rakirtley@bellsouth.net; +Cc: linuxppc-embedded
In-Reply-To: <20060608144535.RSPS5063.ibm70aec.bellsouth.net@mail.bellsouth.net>
On 6/8/06, rakirtley@bellsouth.net <rakirtley@bellsouth.net> wrote:
> All,
> I've been attempting to get a 2.6 version running on the Xilinx ML403 and only really need the ethernet and compact flash devices at this point. I've tried versions from mvista, kernel.org, etc; all only have the serial8250 device enabled. Obviously adding devices is a lot of work and it appears that you all have already made great progress enabling ethernet.
> Are any of the advanced versions upon which you all work generally available? If so could you please provide a location? Apologies in advance for polluting your emailboxes and thanks in advance for any help/pointers that you can provide. I'll be more than happy to share any mods that I make (if any)
Mvista published patches for a TEMAC driver a month or two ago onto
this mailing list. Last I heard, mvista will be releasing 2.6 support
for the V2/V4 parts by the end of this month.
Cheers,
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH 3/3] RTAS MSI
From: Jake Moilanen @ 2006-06-08 16:13 UTC (permalink / raw)
To: Nathan Lynch; +Cc: linuxppc-dev, paulus
In-Reply-To: <20060607225843.GW8934@localdomain>
Here's a version addressing Nathan's concerns.
Signed-off-by: Jake Moilanen <moilanen@austin.ibm.com>
Index: 2.6/drivers/pci/Makefile
===================================================================
--- 2.6.orig/drivers/pci/Makefile 2006-06-08 10:30:14.000000000 -0500
+++ 2.6/drivers/pci/Makefile 2006-06-08 10:30:21.000000000 -0500
@@ -26,7 +26,14 @@
obj-$(CONFIG_PPC64) += setup-bus.o
obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
obj-$(CONFIG_X86_VISWS) += setup-irq.o
-obj-$(CONFIG_PCI_MSI) += msi.o
+
+msiobj-$(CONFIG_X86) += msi.o msi-apic.o msi-intel.o
+msiobj-$(CONFIG_IA64) += msi.o msi-apic.o msi-intel.o
+msiobj-$(CONFIG_IA64_GENERIC) += msi.o msi-altix.o
+msiobj-$(CONFIG_IA64_SGI_SN2) += msi.o msi-altix.o
+msiobj-$(CONFIG_PPC_PSERIES) += msi-rtas.o
+
+obj-$(CONFIG_PCI_MSI) += $(msiobj-y)
#
# ACPI Related PCI FW Functions
Index: 2.6/drivers/pci/msi-rtas.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ 2.6/drivers/pci/msi-rtas.c 2006-06-08 10:51:13.000000000 -0500
@@ -0,0 +1,150 @@
+/*
+ * Jake Moilanen <moilanen@austin.ibm.com>
+ * Copyright (C) 2006 IBM
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <asm/rtas.h>
+#include <asm/hw_irq.h>
+#include <asm/ppc-pci.h>
+
+int rtas_enable_msi(struct pci_dev* pdev)
+{
+ int seq_num = 1;
+ int i;
+ int rc;
+ int query_token = rtas_token("ibm,query-interrupt-source-number");
+ int devfn;
+ int busno;
+ u32 *reg;
+ int reglen;
+ int ret[3];
+ int dummy;
+ unsigned int virq;
+ unsigned int addr;
+ unsigned long buid = -1;
+ struct device_node * dn;
+
+ BUG_ON(!pdev);
+
+ dn = pci_device_to_OF_node(pdev);
+
+ if (!of_find_property(dn, "ibm,req#msi", &dummy))
+ return -ENOENT;
+
+ reg = (u32 *) get_property(dn, "reg", ®len);
+ if (reg == NULL || reglen < 20)
+ return -ENXIO;
+
+ devfn = (reg[0] >> 8) & 0xff;
+ busno = (reg[0] >> 16) & 0xff;
+
+ buid = get_phb_buid(dn->parent);
+ addr = (busno << 16) | (devfn << 8);
+
+ do {
+ rc = rtas_call(rtas_token("ibm,change-msi"), 6, 3, ret, addr,
+ buid >> 32, buid & 0xffffffff,
+ 0, 0, seq_num);
+
+ seq_num = ret[1];
+ } while (rtas_busy_delay(rc));
+
+ if (rc)
+ {
+ printk(KERN_WARNING "error[%d]: getting the number of "
+ "MSI interrupts for %s\n", rc, dn->name);
+ return -EIO;
+ }
+
+ /* Return if there's no MSI interrupts */
+ if (!ret[0])
+ return -ENOENT;
+
+ dn->n_intrs = ret[0];
+
+ dn->intrs = kmalloc(dn->n_intrs * sizeof(*(dn->intrs)), GFP_KERNEL);
+ if (!dn->intrs) {
+ printk(KERN_WARNING "rtas_enable_msi: can't allocate space\n");
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < dn->n_intrs; i++) {
+ do {
+ rc = rtas_call(query_token, 4, 3, ret, addr,
+ buid >> 32, buid & 0xffffffff, i);
+ } while (rtas_busy_delay(rc));
+
+ if (!rc) {
+ virq = virt_irq_create_mapping(ret[0]);
+
+ dn->intrs[i].line = irq_offset_up(virq);
+ dn->intrs[i].sense = ret[1];
+ } else {
+ printk(KERN_WARNING "error[%d]: query-interrupt-source-number for %s\n",
+ rc, dn->name);
+ }
+ }
+
+ /* Just give the first vector out for now */
+ pdev->irq = dn->intrs[0].line;
+
+ return 0;
+}
+
+void rtas_disable_msi(struct pci_dev* pdev)
+{
+ int seq_num = 1;
+ struct device_node * dn;
+ int rc;
+ int devfn;
+ int busno;
+ u32 *reg;
+ int reglen;
+ int ret[3];
+ int dummy;
+ unsigned int addr;
+ unsigned long buid = -1;
+
+ BUG_ON(!pdev);
+
+ dn = pci_device_to_OF_node(pdev);
+
+ if (!of_find_property(dn, "ibm,req#msi", &dummy))
+ return;
+
+ reg = (u32 *) get_property(dn, "reg", ®len);
+ if (reg == NULL || reglen < 20)
+ return;
+
+ devfn = (reg[0] >> 8) & 0xff;
+ busno = (reg[0] >> 16) & 0xff;
+
+ buid = get_phb_buid(dn->parent);
+ addr = (busno << 16) | (devfn << 8);
+
+ do {
+ rc = rtas_call(rtas_token("ibm,change-msi"), 6, 3, ret, addr,
+ buid >> 32, buid & 0xffffffff,
+ 2, 0, seq_num);
+
+ seq_num = ret[1];
+ } while (rtas_busy_delay(rc));
+
+ if (rc) {
+ printk(KERN_WARNING "error[%d]: setting the number of "
+ "MSI interrupts for %s\n", rc, dn->name);
+ return;
+ }
+
+ dn->n_intrs = 0;
+
+ kfree(dn->intrs);
+}
Index: 2.6/drivers/pci/Kconfig
===================================================================
--- 2.6.orig/drivers/pci/Kconfig 2006-06-08 10:30:14.000000000 -0500
+++ 2.6/drivers/pci/Kconfig 2006-06-08 10:30:21.000000000 -0500
@@ -4,7 +4,7 @@
config PCI_MSI
bool "Message Signaled Interrupts (MSI and MSI-X)"
depends on PCI
- depends on (X86_LOCAL_APIC && X86_IO_APIC) || IA64
+ depends on (X86_LOCAL_APIC && X86_IO_APIC) || IA64 || PPC_PSERIES
help
This allows device drivers to enable MSI (Message Signaled
Interrupts). Message Signaled Interrupts enable a device to
Index: 2.6/arch/powerpc/platforms/pseries/setup.c
===================================================================
--- 2.6.orig/arch/powerpc/platforms/pseries/setup.c 2006-06-08 10:30:14.000000000 -0500
+++ 2.6/arch/powerpc/platforms/pseries/setup.c 2006-06-08 10:30:21.000000000 -0500
@@ -205,6 +205,10 @@
} else {
ppc_md.init_IRQ = xics_init_IRQ;
ppc_md.get_irq = xics_get_irq;
+#ifdef CONFIG_PCI_MSI
+ ppc_md.enable_msi = rtas_enable_msi;
+ ppc_md.disable_msi = rtas_disable_msi;
+#endif
}
#ifdef CONFIG_SMP
Index: 2.6/include/asm-powerpc/rtas.h
===================================================================
--- 2.6.orig/include/asm-powerpc/rtas.h 2006-06-08 10:30:21.000000000 -0500
+++ 2.6/include/asm-powerpc/rtas.h 2006-06-08 10:30:21.000000000 -0500
@@ -4,6 +4,7 @@
#include <linux/spinlock.h>
#include <asm/page.h>
+#include <linux/pci.h>
/*
* Definitions for talking to the RTAS on CHRP machines.
@@ -182,6 +183,9 @@
extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
+extern int rtas_enable_msi(struct pci_dev* pdev);
+extern void rtas_disable_msi(struct pci_dev * pdev);
+
/* Error types logged. */
#define ERR_FLAG_ALREADY_LOGGED 0x0
#define ERR_FLAG_BOOT 0x1 /* log was pulled from NVRAM on boot */
^ permalink raw reply
* Re: does Gianfar Ethernet Controller Version 1.1 support MARVELL 88E1111?
From: Andy Fleming @ 2006-06-08 16:15 UTC (permalink / raw)
To: 郭 剑非; +Cc: Linuxppc-embedded
In-Reply-To: <BAY113-F12840A9A3ACBD5515A1350988B0@phx.gbl>
On Jun 8, 2006, at 02:43, =E9=83=AD =E5=89=91=E9=9D=9E wrote:
> Hi all,
> I'm debugging my board with MPC 8540 and marvell 88e1111 designed =20
> on it.
> I'm sure the hardware connection is correct, and the phy's ID could =20=
> be read
> through terminal port. But anyway, phy can not work. I wonder if it =20=
> is the
> driver's problem? Since the Gianfar Ethernet Controller Version 1.1
> surpport 88e1011s, but some 88e1111's registers are different from
> 88e1011s'. Actually I'm a new guy to Linux. Has anybody ever used =20
> 88e1111
> phy in Linux envirenmemt? Please
> give me some points. Thank you!
> I have read the Gianfar ethernet controller driver, but it's =20
> difficult for
> me to find out the sofware flow.
It would be better if you upgraded to the latest kernel. The PHY =20
subsystem in the driver has changed significantly since version 1.1 =20
of the driver. What leads you to believe that the PHY doesn't work? =20=
What errors do you see? I'm fairly certain the 88e1111 works with =20
the 88e1011 driver, but it's been a while.
^ permalink raw reply
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