* Re: [PATCH 4/11] qe_lib: Add QE I/O ports API
From: Andy Fleming @ 2006-09-21 20:38 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: linuxppc-dev, Li Yang
In-Reply-To: <F6AD7E21CDF4E145A44F61F43EE6D9399B44EF@tmnt04.transmode.se>
>
>> +static int qe_irq_ports[NUM_OF_PAR_IOS][NUM_OF_PINS] = {
>> + /* 0-7 */ /* 8-15 */ /* 16 - 23 */ /*
>> 24 - 31 */
>> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,1, 1,0,0,0,0,0,0,0,
>> 0,0,0,0,0,1,1,0},
>> + {0,0,0,1,0,1,0,0, 0,0,0,0,1,1,0,0, 0,0,0,0,0,0,0,0,
>> 0,0,1,1,0,0,0,0},
>> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,
>> 0,0,0,1,1,1,0,0},
>> + {0,0,0,0,0,0,0,0, 0,0,0,0,1,1,0,0, 1,1,0,0,0,0,0,0,
>> 0,0,1,1,0,0,0,0},
>> + {0,0,0,0,0,0,0,0, 0,0,0,0,1,1,0,0, 0,0,0,0,0,0,0,0,
>> 1,1,1,1,0,0,0,1},
>> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,1,0,0,0,
>> 0,0,0,0,0,0,0,0},
>> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,
>> 0,0,0,0,0,0,0,1}
>> +};
>
> qe_irq_ports is diffrent on 8321 not only the number of rows.
>
> These needs to configuruable based on CPU model and/or type of board.
That sounds like a job for the DTS
^ permalink raw reply
* [PATCH] demacrofy arch/powerpc/platforms/maple/pci.c
From: Nathan Lynch @ 2006-09-21 19:31 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
Noticed that the U3_*CFA macros have some typos:
#define U3_HT_CFA0(devfn, off) \
((((unsigned long)devfn) << 8) | offset)
(refers to offset rather than off)
#define U3_AGP_CFA0(devfn, off) \
((1 << (unsigned long)PCI_SLOT(dev_fn)) \
| (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
(refers to dev_fn rather than devfn)
Things happen to work, but there doesn't seem to be any reason these
shouldn't be functions. Overall behavior should be unchanged.
Signed-off-by: Nathan Lynch <ntl@pobox.com>
--- linux-2.6.git.orig/arch/powerpc/platforms/maple/pci.c
+++ linux-2.6.git/arch/powerpc/platforms/maple/pci.c
@@ -79,16 +79,20 @@ static void __init fixup_bus_range(struc
}
-#define U3_AGP_CFA0(devfn, off) \
- ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
- | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
- | (((unsigned long)(off)) & 0xFCUL))
-
-#define U3_AGP_CFA1(bus, devfn, off) \
- ((((unsigned long)(bus)) << 16) \
- |(((unsigned long)(devfn)) << 8) \
- |(((unsigned long)(off)) & 0xFCUL) \
- |1UL)
+static unsigned long u3_agp_cfa0(u8 devfn, u8 off)
+{
+ return (1 << (unsigned long)PCI_SLOT(devfn)) |
+ ((unsigned long)PCI_FUNC(devfn) << 8) |
+ ((unsigned long)off & 0xFCUL);
+}
+
+static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
+{
+ return ((unsigned long)bus << 16) |
+ ((unsigned long)devfn << 8) |
+ ((unsigned long)off & 0xFCUL) |
+ 1UL;
+}
static unsigned long u3_agp_cfg_access(struct pci_controller* hose,
u8 bus, u8 dev_fn, u8 offset)
@@ -98,9 +102,9 @@ static unsigned long u3_agp_cfg_access(s
if (bus == hose->first_busno) {
if (dev_fn < (11 << 3))
return 0;
- caddr = U3_AGP_CFA0(dev_fn, offset);
+ caddr = u3_agp_cfa0(dev_fn, offset);
} else
- caddr = U3_AGP_CFA1(bus, dev_fn, offset);
+ caddr = u3_agp_cfa1(bus, dev_fn, offset);
/* Uninorth will return garbage if we don't read back the value ! */
do {
@@ -182,13 +186,15 @@ static struct pci_ops u3_agp_pci_ops =
u3_agp_write_config
};
+static unsigned long u3_ht_cfa0(u8 devfn, u8 off)
+{
+ return (devfn << 8) | off;
+}
-#define U3_HT_CFA0(devfn, off) \
- ((((unsigned long)devfn) << 8) | offset)
-#define U3_HT_CFA1(bus, devfn, off) \
- (U3_HT_CFA0(devfn, off) \
- + (((unsigned long)bus) << 16) \
- + 0x01000000UL)
+static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
+{
+ return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
+}
static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
u8 bus, u8 devfn, u8 offset)
@@ -196,9 +202,9 @@ static unsigned long u3_ht_cfg_access(st
if (bus == hose->first_busno) {
if (PCI_SLOT(devfn) == 0)
return 0;
- return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
+ return ((unsigned long)hose->cfg_data) + u3_ht_cfa0(devfn, offset);
} else
- return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
+ return ((unsigned long)hose->cfg_data) + u3_ht_cfa1(bus, devfn, offset);
}
static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
^ permalink raw reply
* [PATCH] maple u3 ht - reject inappropriate config space access
From: Nathan Lynch @ 2006-09-21 19:25 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
When there is a PCI-X mode 2 capable device behind the HT<->PCI-X
bridge, the pci core decides that the device has the extended 4K
config space, even though the bus is not operating in mode 2. This is
because the u3_ht pci ops silently accept offsets greater than 255 but
use only the 8 least significant bits, which means reading at offset
0x100 gets the data at offset 0x0, and causes confusion for lspci.
Reject accesses to configuration space offsets greater than 255.
Signed-off-by: Nathan Lynch <ntl@pobox.com>
--- linux-2.6.git.orig/arch/powerpc/platforms/maple/pci.c
+++ linux-2.6.git/arch/powerpc/platforms/maple/pci.c
@@ -211,6 +211,9 @@ static int u3_ht_read_config(struct pci_
if (hose == NULL)
return PCIBIOS_DEVICE_NOT_FOUND;
+ if (offset > 0xff)
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
if (!addr)
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -243,6 +246,9 @@ static int u3_ht_write_config(struct pci
if (hose == NULL)
return PCIBIOS_DEVICE_NOT_FOUND;
+ if (offset > 0xff)
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
if (!addr)
return PCIBIOS_DEVICE_NOT_FOUND;
^ permalink raw reply
* Re: [RFC/PATCH] Create a "wrapper" script and use it in arch/powerpc/boot
From: Geoff Levand @ 2006-09-21 18:03 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <17682.28743.743974.786724@cargo.ozlabs.ibm.com>
Paul Mackerras wrote:
> Another point to note is that this renames the images: the one for
> pSeries is called zImage.pseries rather than zImage, and the one for
> powermacs is now zImage.pmac rather than zImage.vmode.
zImage.vmode was my name, and I never liked it...
> +if [ -n "$dts" ]; then
> + if [ -z "$dtb" ]; then
> + dtb="$platform.dtb"
> + fi
> + dtc -O dtb -o "$dtb" -b 0 -V 16 "$dts" || exit 1
I'm wondering if this would be better to have built by the
upper level makefile and have quiet_cmd_dtc and cmd_dtc.
Its just a thought. Did you consider it?
-Geoff
^ permalink raw reply
* Re: MPC5200b kernel module memory mapping
From: Markus Klotzbücher @ 2006-09-21 18:10 UTC (permalink / raw)
To: Steven Kaiser; +Cc: linuxppc-embedded
In-Reply-To: <000001c6dd12$417d7a50$6e4ec880@volt>
Hi Steven,
"Steven Kaiser" <skaiser.uci@gmail.com> writes:
> In a kernel module, I am trying to iomemory map or ioport map a range of
> addresses so later I can talk directly to custom external hardware. I have
> tried to follow the advice of Rubini chapter 8. I think I am setting it up
> correctly, but at the precise moment I try to write anything within my
> range, the kernel crashes badly. My board is a Lite5200b, using a 2.4.25
> kernel.
...
> // enable LocalBus Chip Select CS2 to hit on our address range
> *(volatile u32 *)MPC5xxx_MM_IPBI &= ~0x00040000;
> *(volatile u16 *)(MPC5xxx_MM_CS2_START + 2) = MALab_MM_START >> 16;
> *(volatile u16 *)(MPC5xxx_MM_CS2_STOP + 2) = MALab_MM_END >> 16;
> *(volatile u32 *)MPC5xxx_MM_IPBI |= 0x00040000;
>
> // map our physical address into kernal virtual address space
> // do I need this call?
> ioaddr = ioremap(MALab_MM_START,MALab_MM_SIZE);
Yes, you do need this call if you want to access physical addresses.
> return 0;
> }
>
> Later (in a ioctrl routine), I will try and write something to the first
> location in my address range. I tried these three ways:
>
> *(volatile u16 *)MALab_MM_START = 0x5555;
> outw(0x5555,MALab_MM_START);
> outw(0x5555,ioaddr);
>
> Any and all of the these calls crash the kernel so horrendously I have to
> reboot. Sometimes I have to delete and mknod a new /dev entry.
>
> I have tried the io memory map technique instead of the above io port map
> technique, using request_mem_region(), with the same crashing results upon
> any writew() call or direct variants. I tried things without the ioremap()
> call-- I get a segmentation fault in these cases.
>
> The request_region() or request_mem_region() seems to work ok. I can cat
> /proc/iomem or /proc/ioports and see my range in there. I am pretty
This doesn't really tell you anything, it's mere housekeeping.
> sure I am setting up the LocalBus chip select registers ok.
I would guess this is not the case. What kind of device is this?
Regards
Markus
^ permalink raw reply
* [PATCH] Fix IPIC pending register assignments
From: Scott Wood @ 2006-09-21 18:10 UTC (permalink / raw)
To: linuxppc-dev
This patch fixes the assignment of pending registers to IRQ numbers for
the IPIC; the code previously assigned all IRQs to the high pending word
regardless of which word the interrupt belonged to.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
arch/powerpc/sysdev/ipic.c | 42 +++++++++++++++++++++---------------------
1 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 70e7077..0251b7c 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -210,7 +210,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 4,
},
[64] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A,
.force = IPIC_SIFCR_L,
@@ -218,7 +218,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 0,
},
[65] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A,
.force = IPIC_SIFCR_L,
@@ -226,7 +226,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 1,
},
[66] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A,
.force = IPIC_SIFCR_L,
@@ -234,7 +234,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 2,
},
[67] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A,
.force = IPIC_SIFCR_L,
@@ -242,7 +242,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 3,
},
[68] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B,
.force = IPIC_SIFCR_L,
@@ -250,7 +250,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 0,
},
[69] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B,
.force = IPIC_SIFCR_L,
@@ -258,7 +258,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 1,
},
[70] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B,
.force = IPIC_SIFCR_L,
@@ -266,7 +266,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 2,
},
[71] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B,
.force = IPIC_SIFCR_L,
@@ -274,91 +274,91 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 3,
},
[72] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 8,
},
[73] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 9,
},
[74] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 10,
},
[75] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 11,
},
[76] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 12,
},
[77] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 13,
},
[78] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 14,
},
[79] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 15,
},
[80] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 16,
},
[84] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 20,
},
[85] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 21,
},
[90] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 26,
},
[91] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
--
1.4.2.1
^ permalink raw reply related
* Re: [PATCH 2/11] qe_lib: Add common files
From: Olof Johansson @ 2006-09-21 17:24 UTC (permalink / raw)
To: Li Yang; +Cc: linuxppc-dev
In-Reply-To: <45128300.3020801@freescale.com>
On Thu, 21 Sep 2006 20:18:08 +0800 Li Yang <leoli@freescale.com> wrote:
> Signed-off-by: Shlomi Gridish <gridish@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
>
>
> ---
> arch/powerpc/sysdev/Makefile | 1
> arch/powerpc/sysdev/qe_lib/Kconfig | 29 ++
> arch/powerpc/sysdev/qe_lib/Makefile | 8 +
> arch/powerpc/sysdev/qe_lib/qe_common.c | 354 +++++++++++++++++++++++
> include/asm-powerpc/qe.h | 493 ++++++++++++++++++++++++++++++++
> 5 files changed, 885 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
> index e5e999e..c6e5b31 100644
> --- a/arch/powerpc/sysdev/Makefile
> +++ b/arch/powerpc/sysdev/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
> obj-$(CONFIG_FSL_SOC) += fsl_soc.o
> obj-$(CONFIG_PPC_TODC) += todc.o
> obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
> +obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
>
> ifeq ($(CONFIG_PPC_MERGE),y)
> obj-$(CONFIG_PPC_I8259) += i8259.o
> diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
> new file mode 100644
> index 0000000..28487e4
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/Kconfig
> @@ -0,0 +1,29 @@
> +#
> +# QE Communication options
> +#
> +
> +menu "QE Options"
> + depends on QUICC_ENGINE
> +
> +config UCC_SLOW
> + bool "UCC Slow Protocols Support"
> + default n
> + select UCC
> + help
> + This option provides qe_lib support to UCC slow
> + protocols: UART, BISYNC, QMC
> +
> +config UCC_FAST
> + bool "UCC Fast Protocols Support"
> + default n
> + select UCC
> + help
> + This option provides qe_lib support to UCC fast
> + protocols: HDLC, Ethernet, ATM, transparent
[...]
> +obj-$(CONFIG_UCC) += ucc.o
> +obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
> +obj-$(CONFIG_UCC_FAST) += ucc_fast.o ucc_slow.o
Shouldn't you just have UCC_FAST select UCC_SLOW in the Kconfig
instead, then you don't have to specify the same object file twice.
> diff --git a/arch/powerpc/sysdev/qe_lib/qe_common.c b/arch/powerpc/sysdev/qe_lib/qe_common.c
> new file mode 100644
> index 0000000..a4ed18e
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/qe_common.c
> @@ -0,0 +1,354 @@
> +/*
> + * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
> + *
> + * Author: Shlomi Gridish <gridish@freescale.com>
> + * Maintainer: Li Yang <leoli@freescale.com>
> + *
> + * Description:
> + * General Purpose functions for the global management of the
> + * QUICC Engine (QE).
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +#include <linux/errno.h>
> +#include <linux/sched.h>
> +#include <linux/kernel.h>
> +#include <linux/param.h>
> +#include <linux/string.h>
> +#include <linux/mm.h>
> +#include <linux/interrupt.h>
> +#include <linux/bootmem.h>
> +#include <linux/module.h>
> +#include <linux/delay.h>
> +#include <asm/irq.h>
> +#include <asm/page.h>
> +#include <asm/pgtable.h>
> +#include <asm/immap_qe.h>
> +#include <asm/qe.h>
> +#include <asm/prom.h>
> +#include <asm/rheap.h>
> +
> +/* QE snum state
> +*/
> +typedef enum qe_snum_state {
> + QE_SNUM_STATE_USED, /* used */
> + QE_SNUM_STATE_FREE /* free */
> +} qe_snum_state_e;
> +
> +/* QE snum
> +*/
> +typedef struct qe_snum {
> + u8 num; /* snum */
> + qe_snum_state_e state; /* state */
> +} qe_snum_t;
> +
> +/* We allocate this here because it is used almost exclusively for
> + * the communication processor devices.
> + */
> +EXPORT_SYMBOL(qe_immr);
> +qe_map_t *qe_immr = NULL;
> +static qe_snum_t snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
> +
> +static void qe_snums_init(void);
> +static void qe_muram_init(void);
> +static int qe_sdma_init(void);
> +
> +static DEFINE_SPINLOCK(qe_lock);
> +
> +void qe_reset(void)
> +{
> + if (qe_immr == NULL)
> + qe_immr = (qe_map_t *) ioremap(get_qe_base(), QE_IMMAP_SIZE);
> +
> + qe_snums_init();
> +
> + qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
> + (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
> +
> + /* Reclaim the MURAM memory for our use. */
> + qe_muram_init();
> +
> + if (qe_sdma_init())
> + panic("sdma init failed!");
> +}
> +
> +EXPORT_SYMBOL(qe_issue_cmd);
> +int qe_issue_cmd(uint cmd, uint device, u8 mcn_protocol, u32 cmd_input)
> +{
> + unsigned long flags;
> + u32 cecr;
> + u8 mcn_shift = 0, dev_shift = 0;
> +
> + spin_lock_irqsave(&qe_lock, flags);
> + if (cmd == QE_RESET) {
> + out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
> + } else {
> + if (cmd == QE_ASSIGN_PAGE) {
> + /* Here device is the SNUM, not sub-block */
> + dev_shift = QE_CR_SNUM_SHIFT;
> + } else if (cmd == QE_ASSIGN_RISC) {
> + /* Here device is the SNUM, and mcnProtocol is
> + * e_QeCmdRiscAssignment value */
> + dev_shift = QE_CR_SNUM_SHIFT;
> + mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
> + } else {
> + if (device == QE_CR_SUBBLOCK_USB)
> + mcn_shift = QE_CR_MCN_USB_SHIFT;
> + else
> + mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
> + }
> +
> + out_be32(&qe_immr->cp.cecdr,
> + immrbar_virt_to_phys((void *)cmd_input));
> + out_be32(&qe_immr->cp.cecr,
> + (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
> + mcn_protocol << mcn_shift));
> + }
> +
> + /* wait for the QE_CR_FLG to clear */
> + do {
> + cecr = in_be32(&qe_immr->cp.cecr);
> + } while (cecr & QE_CR_FLG);
> + spin_unlock_irqrestore(&qe_lock, flags);
> +
> + return 0;
> +}
> +
> +/* Set a baud rate generator. This needs lots of work. There are
> + * 16 BRGs, which can be connected to the QE channels or output
> + * as clocks. The BRGs are in two different block of internal
> + * memory mapped space.
> + * The baud rate clock is the system clock divided by something.
> + * It was set up long ago during the initial boot phase and is
> + * is given to us.
> + * Baud rate clocks are zero-based in the driver code (as that maps
> + * to port numbers). Documentation uses 1-based numbering.
> + */
> +static unsigned int brg_clk = 0;
> +
> +unsigned int get_brg_clk(void)
> +{
> + struct device_node *qe;
> + if (brg_clk)
> + return brg_clk;
> +
> + qe = of_find_node_by_type(NULL, "qe");
> + if (qe) {
> + unsigned int size;
> + u32 *prop = (u32 *) get_property(qe, "brg-frequency", &size);
> + brg_clk = *prop;
> + of_node_put(qe);
> + };
> + return brg_clk;
> +}
> +
> +/* This function is used by UARTS, or anything else that uses a 16x
> + * oversampled clock.
> + */
> +void qe_setbrg(uint brg, uint rate)
> +{
> + volatile uint *bp;
> + u32 divisor;
> + int div16 = 0;
> +
> + bp = (uint *) & qe_immr->brg.brgc1;
> + bp += brg;
> +
> + divisor = (get_brg_clk() / rate);
> + if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
> + div16 = 1;
> + divisor /= 16;
> + }
> +
> + *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
> + if (div16)
> + *bp |= QE_BRGC_DIV16;
> +}
> +
> +static void qe_snums_init(void)
> +{
> + int i;
> +
> + /* Initialize the SNUMs array. */
> + for (i = 0; i < QE_NUM_OF_SNUM; i++)
> + snums[i].state = QE_SNUM_STATE_FREE;
> +
> + /* Initialize SNUMs (thread serial numbers) according to QE
> + * spec chapter 4, SNUM table */
> + i = 0;
> + snums[i++].num = 0x04;
> + snums[i++].num = 0x05;
> + snums[i++].num = 0x0C;
> + snums[i++].num = 0x0D;
> + snums[i++].num = 0x14;
> + snums[i++].num = 0x15;
> + snums[i++].num = 0x1C;
> + snums[i++].num = 0x1D;
> + snums[i++].num = 0x24;
> + snums[i++].num = 0x25;
> + snums[i++].num = 0x2C;
> + snums[i++].num = 0x2D;
> + snums[i++].num = 0x34;
> + snums[i++].num = 0x35;
> + snums[i++].num = 0x88;
> + snums[i++].num = 0x89;
> + snums[i++].num = 0x98;
> + snums[i++].num = 0x99;
> + snums[i++].num = 0xA8;
> + snums[i++].num = 0xA9;
> + snums[i++].num = 0xB8;
> + snums[i++].num = 0xB9;
> + snums[i++].num = 0xC8;
> + snums[i++].num = 0xC9;
> + snums[i++].num = 0xD8;
> + snums[i++].num = 0xD9;
> + snums[i++].num = 0xE8;
> + snums[i++].num = 0xE9;
It'd look better if there was just an array with the contents, and a
short loop to copy it over. Or, if you ever anticipate the table being
different for different parts, add it to the device tree instead.
> +}
> +
> +int qe_get_snum(void)
> +{
> + unsigned long flags;
> + int snum = -EBUSY;
> + int i;
> +
> + spin_lock_irqsave(&qe_lock, flags);
> + for (i = 0; i < QE_NUM_OF_SNUM; i++) {
> + if (snums[i].state == QE_SNUM_STATE_FREE) {
> + snums[i].state = QE_SNUM_STATE_USED;
> + snum = snums[i].num;
> + break;
> + }
> + }
> + spin_unlock_irqrestore(&qe_lock, flags);
> +
> + return snum;
> +}
> +
> +EXPORT_SYMBOL(qe_get_snum);
> +
> +void qe_put_snum(u8 snum)
> +{
> + int i;
> +
> + for (i = 0; i < QE_NUM_OF_SNUM; i++) {
> + if (snums[i].num == snum) {
> + snums[i].state = QE_SNUM_STATE_FREE;
> + break;
> + }
> + }
> +}
> +
> +EXPORT_SYMBOL(qe_put_snum);
> +
> +static int qe_sdma_init(void)
> +{
> + sdma_t *sdma = &qe_immr->sdma;
> + uint sdma_buf_offset;
> +
> + if (!sdma)
> + return -ENODEV;
> +
> + /* allocate 2 internal temporary buffers (512 bytes size each) for
> + * the SDMA */
> + sdma_buf_offset = qe_muram_alloc(512 * 2, 64);
> + if (IS_MURAM_ERR(sdma_buf_offset))
> + return -ENOMEM;
> +
> + out_be32(&sdma->sdebcr, sdma_buf_offset & QE_SDEBCR_BA_MASK);
> + out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK | (0x1 >>
> + QE_SDMR_CEN_SHIFT)));
> +
> + return 0;
> +}
> +
> +/*
> + * muram_alloc / muram_free bits.
> + */
> +static DEFINE_SPINLOCK(qe_muram_lock);
> +
> +/* 16 blocks should be enough to satisfy all requests
> + * until the memory subsystem goes up... */
> +static rh_block_t qe_boot_muram_rh_block[16];
> +static rh_info_t qe_muram_info;
> +
> +static void qe_muram_init(void)
> +{
> + /* initialize the info header */
> + rh_init(&qe_muram_info, 1,
> + sizeof(qe_boot_muram_rh_block) /
> + sizeof(qe_boot_muram_rh_block[0]), qe_boot_muram_rh_block);
> +
> + /* Attach the usable muram area */
> + /* XXX: This is actually crap. QE_DATAONLY_BASE and
> + * QE_DATAONLY_SIZE is only a subset of the available muram. It
> + * varies with the processor and the microcode patches activated.
> + * But the following should be at least safe.
> + */
> + rh_attach_region(&qe_muram_info,
> + (void *)QE_MURAM_DATAONLY_BASE,
> + QE_MURAM_DATAONLY_SIZE);
> +}
> +
> +/* This function returns an index into the MURAM area.
> + */
> +uint qe_muram_alloc(uint size, uint align)
> +{
> + void *start;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&qe_muram_lock, flags);
> + start = rh_alloc_align(&qe_muram_info, size, align, "QE");
> + spin_unlock_irqrestore(&qe_muram_lock, flags);
> +
> + return (uint) start;
> +}
> +
> +EXPORT_SYMBOL(qe_muram_alloc);
> +
> +int qe_muram_free(uint offset)
> +{
> + int ret;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&qe_muram_lock, flags);
> + ret = rh_free(&qe_muram_info, (void *)offset);
> + spin_unlock_irqrestore(&qe_muram_lock, flags);
> +
> + return ret;
> +}
> +
> +EXPORT_SYMBOL(qe_muram_free);
> +
> +/* not sure if this is ever needed */
> +uint qe_muram_alloc_fixed(uint offset, uint size)
> +{
> + void *start;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&qe_muram_lock, flags);
> + start =
> + rh_alloc_fixed(&qe_muram_info, (void *)offset, size, "commproc");
> + spin_unlock_irqrestore(&qe_muram_lock, flags);
> +
> + return (uint) start;
> +}
> +
> +EXPORT_SYMBOL(qe_muram_alloc_fixed);
> +
> +void qe_muram_dump(void)
> +{
> + rh_dump(&qe_muram_info);
> +}
> +
> +EXPORT_SYMBOL(qe_muram_dump);
> +
> +void *qe_muram_addr(uint offset)
> +{
> + return (void *)&qe_immr->muram[offset];
> +}
> +
> +EXPORT_SYMBOL(qe_muram_addr);
> diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
> new file mode 100644
> index 0000000..ad3353a
> --- /dev/null
> +++ b/include/asm-powerpc/qe.h
> @@ -0,0 +1,493 @@
> +/*
> + * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
> + *
> + * Author: Shlomi Gridish <gridish@freescale.com>
> + * Maintainer: Li Yang <leoli@freescale.com>
> + *
> + * Description:
> + * QUICC Engine (QE) external definitions and structure.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +#ifdef __KERNEL__
> +#ifndef __QE_H__
> +#define __QE_H__
> +
> +#include <asm/immap_qe.h>
> +
> +/* Multi User RAM addresses.
> + */
> +#define QE_MURAM_DATAONLY_BASE ((uint)0x0)
> +#define QE_MURAM_NOSPACE ((uint)0x7fffffff)
> +#define QE_MURAM_DATAONLY_SIZE ((uint)(48 * 1024) - QE_MURAM_DATAONLY_BASE)
> +
> +static inline long IS_MURAM_ERR(const uint offset)
> +{
> + return (uint) offset > (uint) - 1000L;
> +}
> +
> +#define QE_NUM_OF_SNUM 28
> +#define QE_NUM_OF_BRGS 16
> +#define QE_NUM_OF_PORTS 1024
> +
> +/* Memory partitions
> +*/
> +#define MEM_PART_SYSTEM 0
> +#define MEM_PART_SECONDARY 1
> +#define MEM_PART_MURAM 2
> +
> +/* Export the base address of the communication processor registers
> + * and dual port ram.
> + */
> +int qe_issue_cmd(uint cmd, uint device, u8 mcn_protocol, u32 cmd_input);
> +void qe_setbrg(uint brg, uint rate);
> +int qe_get_snum(void);
> +void qe_put_snum(u8 snum);
> +uint qe_muram_alloc(uint size, uint align);
> +int qe_muram_free(uint offset);
> +uint qe_muram_alloc_fixed(uint offset, uint size);
> +void qe_muram_dump(void);
> +void *qe_muram_addr(uint offset);
> +/* Buffer descriptors.
> +*/
> +typedef struct qe_bd {
> + u16 status;
> + u16 length;
> + u32 buf;
> +} __attribute__ ((packed)) qe_bd_t;
> +
> +#define QE_SIZEOF_BD sizeof(qe_bd_t)
> +
> +#define BD_STATUS_MASK 0xffff0000
> +#define BD_LENGTH_MASK 0x0000ffff
> +
> +#define BD_BUFFER_ARG(bd) ((qe_bd_t *)bd)->buf
> +#define BD_BUFFER_CLEAR(bd) out_be32(&(BD_BUFFER_ARG(bd)), 0);
> +#define BD_BUFFER(bd) in_be32(&(BD_BUFFER_ARG(bd)))
> +#define BD_STATUS_AND_LENGTH_SET(bd, val) out_be32((u32*)bd, val)
> +#define BD_STATUS_AND_LENGTH(bd) in_be32((u32*)bd)
> +#define BD_BUFFER_SET(bd, buffer) out_be32(&(BD_BUFFER_ARG(bd)), \
> + (u32)(buffer))
> +/* Macro for retrieving the following BD.
> + example:
> + next = BD_GET_NEXT( currBd, bdStatus, bdBase, SIZEOF_MY_BD, T_W ) */
> +#define BD_GET_NEXT( curr_bd, bd_status, bd_base, bd_len, last_bd ) \
> + ( (!((bd_status) & (last_bd))) ? ((curr_bd)+(bd_len)) : (bd_base) )
> +
> +/* Alignments
> +*/
> +#define QE_INTR_TABLE_ALIGN 16 /* ??? */
> +#define QE_ALIGNMENT_OF_BD 8
> +#define QE_ALIGNMENT_OF_PRAM 64
> +
> +/* RISC allocation
> +*/
> +typedef enum qe_risc_allocation {
> + QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
> + QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
> + QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose RISC 1 or
> + RISC 2 */
> +} qe_risc_allocation_e;
> +
> +/* QE extended filtering Table Lookup Key Size
> +*/
> +typedef enum qe_fltr_tbl_lookup_key_size {
> + QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
> + = 0x3f, /* LookupKey parsed by the Generate LookupKey
> + CMD is truncated to 8 bytes */
> + QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
> + = 0x5f, /* LookupKey parsed by the Generate LookupKey
> + CMD is truncated to 16 bytes */
> +} qe_fltr_tbl_lookup_key_size_e;
> +
> +/* QE FLTR extended filtering Largest External Table Lookup Key Size
> +*/
> +typedef enum qe_fltr_largest_external_tbl_lookup_key_size_ {
> + QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
> + = 0x0,/* not used */
> + QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
> + = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
> + QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
> + = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES /* 16 bytes */
> +} qe_fltr_largest_external_tbl_lookup_key_size_e;
> +
> +/* structure representing QE parameter RAM
> +*/
> +typedef struct qe_timer_tables {
> + u16 tm_base; /* QE timer table base adr */
> + u16 tm_ptr; /* QE timer table pointer */
> + u16 r_tmr; /* QE timer mode register */
> + u16 r_tmv; /* QE timer valid register */
> + u32 tm_cmd; /* QE timer cmd register */
> + u32 tm_cnt; /* QE timer internal cnt */
> +} __attribute__ ((packed)) qe_timer_tables_t;
> +
> +#define QE_FLTR_TAD_SIZE 8
> +
> +/* QE extended filtering Termination Action Descriptor (TAD)
> +*/
> +typedef struct qe_fltr_tad {
> + u8 serialized[QE_FLTR_TAD_SIZE];
> +} __attribute__ ((packed)) qe_fltr_tad_t;
> +
> +/* Communication Direction.
> +*/
> +typedef enum comm_dir {
> + COMM_DIR_NONE = 0,
> + COMM_DIR_RX = 1,
> + COMM_DIR_TX = 2,
> + COMM_DIR_RX_AND_TX = 3
> +} comm_dir_e;
> +
> +/* Clocks and GRG's
> +*/
> +typedef enum qe_clock {
> + QE_CLK_NONE = 0
> + , QE_BRG1 /* Baud Rate Generator 1 */
> + , QE_BRG2 /* Baud Rate Generator 2 */
> + , QE_BRG3 /* Baud Rate Generator 3 */
> + , QE_BRG4 /* Baud Rate Generator 4 */
> + , QE_BRG5 /* Baud Rate Generator 5 */
> + , QE_BRG6 /* Baud Rate Generator 6 */
> + , QE_BRG7 /* Baud Rate Generator 7 */
> + , QE_BRG8 /* Baud Rate Generator 8 */
> + , QE_BRG9 /* Baud Rate Generator 9 */
> + , QE_BRG10 /* Baud Rate Generator 10 */
> + , QE_BRG11 /* Baud Rate Generator 11 */
> + , QE_BRG12 /* Baud Rate Generator 12 */
> + , QE_BRG13 /* Baud Rate Generator 13 */
> + , QE_BRG14 /* Baud Rate Generator 14 */
> + , QE_BRG15 /* Baud Rate Generator 15 */
> + , QE_BRG16 /* Baud Rate Generator 16 */
> + , QE_CLK1 /* Clock 1 */
> + , QE_CLK2 /* Clock 2 */
> + , QE_CLK3 /* Clock 3 */
> + , QE_CLK4 /* Clock 4 */
> + , QE_CLK5 /* Clock 5 */
> + , QE_CLK6 /* Clock 6 */
> + , QE_CLK7 /* Clock 7 */
> + , QE_CLK8 /* Clock 8 */
> + , QE_CLK9 /* Clock 9 */
> + , QE_CLK10 /* Clock 10 */
> + , QE_CLK11 /* Clock 11 */
> + , QE_CLK12 /* Clock 12 */
> + , QE_CLK13 /* Clock 13 */
> + , QE_CLK14 /* Clock 14 */
> + , QE_CLK15 /* Clock 15 */
> + , QE_CLK16 /* Clock 16 */
> + , QE_CLK17 /* Clock 17 */
> + , QE_CLK18 /* Clock 18 */
> + , QE_CLK19 /* Clock 19 */
> + , QE_CLK20 /* Clock 20 */
> + , QE_CLK21 /* Clock 21 */
> + , QE_CLK22 /* Clock 22 */
> + , QE_CLK23 /* Clock 23 */
> + , QE_CLK24 /* Clock 24 */
> + , QE_CLK_DUMMY
> +} qe_clock_e;
> +
> +/* QE CMXUCR Registers.
> + * There are two UCCs represented in each of the four CMXUCR registers.
> + * These values are for the UCC in the LSBs
> + */
> +#define QE_CMXUCR_MII_ENET_MNG 0x00007000
> +#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
> +#define QE_CMXUCR_GRANT 0x00008000
> +#define QE_CMXUCR_TSA 0x00004000
> +#define QE_CMXUCR_BKPT 0x00000100
> +#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
> +
> +/* QE CMXGCR Registers.
> +*/
> +#define QE_CMXGCR_MII_ENET_MNG 0x00007000
> +#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
> +#define QE_CMXGCR_USBCS 0x0000000f
> +
> +/* QE CECR Commands.
> +*/
> +#define QE_CR_FLG 0x00010000
> +#define QE_RESET 0x80000000
> +#define QE_INIT_TX_RX 0x00000000
> +#define QE_INIT_RX 0x00000001
> +#define QE_INIT_TX 0x00000002
> +#define QE_ENTER_HUNT_MODE 0x00000003
> +#define QE_STOP_TX 0x00000004
> +#define QE_GRACEFUL_STOP_TX 0x00000005
> +#define QE_RESTART_TX 0x00000006
> +#define QE_CLOSE_RX_BD 0x00000007
> +#define QE_SWITCH_COMMAND 0x00000007
> +#define QE_SET_GROUP_ADDRESS 0x00000008
> +#define QE_START_IDMA 0x00000009
> +#define QE_MCC_STOP_RX 0x00000009
> +#define QE_ATM_TRANSMIT 0x0000000a
> +#define QE_HPAC_CLEAR_ALL 0x0000000b
> +#define QE_GRACEFUL_STOP_RX 0x0000001a
> +#define QE_RESTART_RX 0x0000001b
> +#define QE_HPAC_SET_PRIORITY 0x0000010b
> +#define QE_HPAC_STOP_TX 0x0000020b
> +#define QE_HPAC_STOP_RX 0x0000030b
> +#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
> +#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
> +#define QE_HPAC_START_TX 0x0000060b
> +#define QE_HPAC_START_RX 0x0000070b
> +#define QE_USB_STOP_TX 0x0000000a
> +#define QE_USB_RESTART_TX 0x0000000b
> +#define QE_QMC_STOP_TX 0x0000000c
> +#define QE_QMC_STOP_RX 0x0000000d
> +#define QE_SS7_SU_FIL_RESET 0x0000000e
> +/* jonathbr added from here down for 83xx */
> +#define QE_RESET_BCS 0x0000000a
> +#define QE_MCC_INIT_TX_RX_16 0x00000003
> +#define QE_MCC_STOP_TX 0x00000004
> +#define QE_MCC_INIT_TX_1 0x00000005
> +#define QE_MCC_INIT_RX_1 0x00000006
> +#define QE_MCC_RESET 0x00000007
> +#define QE_SET_TIMER 0x00000008
> +#define QE_RANDOM_NUMBER 0x0000000c
> +#define QE_ATM_MULTI_THREAD_INIT 0x00000011
> +#define QE_ASSIGN_PAGE 0x00000012
> +#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
> +#define QE_START_FLOW_CONTROL 0x00000014
> +#define QE_STOP_FLOW_CONTROL 0x00000015
> +#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
> +
> +#define QE_ASSIGN_RISC 0x00000010
> +#define QE_CR_MCN_NORMAL_SHIFT 6
> +#define QE_CR_MCN_USB_SHIFT 4
> +#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
> +#define QE_CR_SNUM_SHIFT 17
> +
> +/* QE CECR Sub Block - sub block of QE command.
> +*/
> +#define QE_CR_SUBBLOCK_INVALID 0x00000000
> +#define QE_CR_SUBBLOCK_USB 0x03200000
> +#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
> +#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
> +#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
> +#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
> +#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
> +#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
> +#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
> +#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
> +#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
> +#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
> +#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
> +#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
> +#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
> +#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
> +#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
> +#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
> +#define QE_CR_SUBBLOCK_MCC1 0x03800000
> +#define QE_CR_SUBBLOCK_MCC2 0x03a00000
> +#define QE_CR_SUBBLOCK_MCC3 0x03000000
> +#define QE_CR_SUBBLOCK_IDMA1 0x02800000
> +#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
> +#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
> +#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
> +#define QE_CR_SUBBLOCK_HPAC 0x01e00000
> +#define QE_CR_SUBBLOCK_SPI1 0x01400000
> +#define QE_CR_SUBBLOCK_SPI2 0x01600000
> +#define QE_CR_SUBBLOCK_RAND 0x01c00000
> +#define QE_CR_SUBBLOCK_TIMER 0x01e00000
> +#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
> +
> +/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
> +*/
> +#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
> +#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
> +#define QE_CR_PROTOCOL_ATM_POS 0x0A
> +#define QE_CR_PROTOCOL_ETHERNET 0x0C
> +#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
> +
> +/* BMR byte order
> +*/
> +#define QE_BMR_BYTE_ORDER_BO_PPC 0x08 /* powerpc little endian */
> +#define QE_BMR_BYTE_ORDER_BO_MOT 0x10 /* motorola big endian */
> +#define QE_BMR_BYTE_ORDER_BO_MAX 0x18
> +
> +/* BRG configuration register
> +*/
> +#define QE_BRGC_ENABLE 0x00010000
> +#define QE_BRGC_DIVISOR_SHIFT 1
> +#define QE_BRGC_DIVISOR_MAX 0xFFF
> +#define QE_BRGC_DIV16 1
> +/* QE Timers registers */
> +#define QE_GTCFR1_PCAS 0x80
> +#define QE_GTCFR1_STP2 0x20
> +#define QE_GTCFR1_RST2 0x10
> +#define QE_GTCFR1_GM2 0x08
> +#define QE_GTCFR1_GM1 0x04
> +#define QE_GTCFR1_STP1 0x02
> +#define QE_GTCFR1_RST1 0x01
> +
> +/* SDMA registers */
> +#define QE_SDSR_BER1 0x02000000
> +#define QE_SDSR_BER2 0x01000000
> +
> +#define QE_SDMR_GLB_1_MSK 0x80000000
> +#define QE_SDMR_ADR_SEL 0x20000000
> +#define QE_SDMR_BER1_MSK 0x02000000
> +#define QE_SDMR_BER2_MSK 0x01000000
> +#define QE_SDMR_EB1_MSK 0x00800000
> +#define QE_SDMR_ER1_MSK 0x00080000
> +#define QE_SDMR_ER2_MSK 0x00040000
> +#define QE_SDMR_CEN_MASK 0x0000E000
> +#define QE_SDMR_SBER_1 0x00000200
> +#define QE_SDMR_SBER_2 0x00000200
> +#define QE_SDMR_EB1_PR_MASK 0x000000C0
> +#define QE_SDMR_ER1_PR 0x00000008
> +
> +#define QE_SDMR_CEN_SHIFT 13
> +#define QE_SDMR_EB1_PR_SHIFT 6
> +
> +#define QE_SDTM_MSNUM_SHIFT 24
> +
> +#define QE_SDEBCR_BA_MASK 0x01FFFFFF
> +
> +/* UPC
> +*/
> +#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
> +#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
> +#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
> +#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
> +#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
> +
> +/* UCC
> +*/
> +#define UCC_GUEMR_MODE_MASK_RX 0x02
> +#define UCC_GUEMR_MODE_MASK_TX 0x01
> +#define UCC_GUEMR_MODE_FAST_RX 0x02
> +#define UCC_GUEMR_MODE_FAST_TX 0x01
> +#define UCC_GUEMR_MODE_SLOW_RX 0x00
> +#define UCC_GUEMR_MODE_SLOW_TX 0x00
> +#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
> + must be set 1 */
> +
> +/* structure representing UCC SLOW parameter RAM
> +*/
> +typedef struct ucc_slow_pram {
> + u16 rbase; /* RX BD base address */
> + u16 tbase; /* TX BD base address */
> + u8 rfcr; /* Rx function code */
> + u8 tfcr; /* Tx function code */
> + u16 mrblr; /* Rx buffer length */
> + u32 rstate; /* Rx internal state */
> + u32 rptr; /* Rx internal data pointer */
> + u16 rbptr; /* rb BD Pointer */
> + u16 rcount; /* Rx internal byte count */
> + u32 rtemp; /* Rx temp */
> + u32 tstate; /* Tx internal state */
> + u32 tptr; /* Tx internal data pointer */
> + u16 tbptr; /* Tx BD pointer */
> + u16 tcount; /* Tx byte count */
> + u32 ttemp; /* Tx temp */
> + u32 rcrc; /* temp receive CRC */
> + u32 tcrc; /* temp transmit CRC */
> +} __attribute__ ((packed)) ucc_slow_pram_t;
> +
> +/* General UCC SLOW Mode Register (GUMRH & GUMRL)
> +*/
> +#define UCC_SLOW_GUMR_H_CRC16 0x00004000
> +#define UCC_SLOW_GUMR_H_CRC16CCITT 0x00000000
> +#define UCC_SLOW_GUMR_H_CRC32CCITT 0x00008000
> +#define UCC_SLOW_GUMR_H_REVD 0x00002000
> +#define UCC_SLOW_GUMR_H_TRX 0x00001000
> +#define UCC_SLOW_GUMR_H_TTX 0x00000800
> +#define UCC_SLOW_GUMR_H_CDP 0x00000400
> +#define UCC_SLOW_GUMR_H_CTSP 0x00000200
> +#define UCC_SLOW_GUMR_H_CDS 0x00000100
> +#define UCC_SLOW_GUMR_H_CTSS 0x00000080
> +#define UCC_SLOW_GUMR_H_TFL 0x00000040
> +#define UCC_SLOW_GUMR_H_RFW 0x00000020
> +#define UCC_SLOW_GUMR_H_TXSY 0x00000010
> +#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
> +#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
> +#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
> +#define UCC_SLOW_GUMR_H_RTSM 0x00000002
> +#define UCC_SLOW_GUMR_H_RSYN 0x00000001
> +
> +#define UCC_SLOW_GUMR_L_TCI 0x10000000
> +#define UCC_SLOW_GUMR_L_RINV 0x02000000
> +#define UCC_SLOW_GUMR_L_TINV 0x01000000
> +#define UCC_SLOW_GUMR_L_TEND 0x00020000
> +#define UCC_SLOW_GUMR_L_ENR 0x00000020
> +#define UCC_SLOW_GUMR_L_ENT 0x00000010
> +
> +/* General UCC FAST Mode Register
> +*/
> +#define UCC_FAST_GUMR_TCI 0x20000000
> +#define UCC_FAST_GUMR_TRX 0x10000000
> +#define UCC_FAST_GUMR_TTX 0x08000000
> +#define UCC_FAST_GUMR_CDP 0x04000000
> +#define UCC_FAST_GUMR_CTSP 0x02000000
> +#define UCC_FAST_GUMR_CDS 0x01000000
> +#define UCC_FAST_GUMR_CTSS 0x00800000
> +#define UCC_FAST_GUMR_TXSY 0x00020000
> +#define UCC_FAST_GUMR_RSYN 0x00010000
> +#define UCC_FAST_GUMR_RTSM 0x00002000
> +#define UCC_FAST_GUMR_REVD 0x00000400
> +#define UCC_FAST_GUMR_ENR 0x00000020
> +#define UCC_FAST_GUMR_ENT 0x00000010
> +
> +/* Slow UCC Event Register (UCCE)
> +*/
> +#define UCC_SLOW_UCCE_GLR 0x1000
> +#define UCC_SLOW_UCCE_GLT 0x0800
> +#define UCC_SLOW_UCCE_DCC 0x0400
> +#define UCC_SLOW_UCCE_FLG 0x0200
> +#define UCC_SLOW_UCCE_AB 0x0200
> +#define UCC_SLOW_UCCE_IDLE 0x0100
> +#define UCC_SLOW_UCCE_GRA 0x0080
> +#define UCC_SLOW_UCCE_TXE 0x0010
> +#define UCC_SLOW_UCCE_RXF 0x0008
> +#define UCC_SLOW_UCCE_CCR 0x0008
> +#define UCC_SLOW_UCCE_RCH 0x0008
> +#define UCC_SLOW_UCCE_BSY 0x0004
> +#define UCC_SLOW_UCCE_TXB 0x0002
> +#define UCC_SLOW_UCCE_TX 0x0002
> +#define UCC_SLOW_UCCE_RX 0x0001
> +#define UCC_SLOW_UCCE_GOV 0x0001
> +#define UCC_SLOW_UCCE_GUN 0x0002
> +#define UCC_SLOW_UCCE_GINT 0x0004
> +#define UCC_SLOW_UCCE_IQOV 0x0008
> +
> +#define UCC_SLOW_UCCE_HDLC_SET (UCC_SLOW_UCCE_TXE|UCC_SLOW_UCCE_BSY| \
> + UCC_SLOW_UCCE_GRA|UCC_SLOW_UCCE_TXB|UCC_SLOW_UCCE_RXF| \
> + UCC_SLOW_UCCE_DCC|UCC_SLOW_UCCE_GLT|UCC_SLOW_UCCE_GLR)
> +#define UCC_SLOW_UCCE_ENET_SET (UCC_SLOW_UCCE_TXE|UCC_SLOW_UCCE_BSY| \
> + UCC_SLOW_UCCE_GRA|UCC_SLOW_UCCE_TXB|UCC_SLOW_UCCE_RXF)
> +#define UCC_SLOW_UCCE_TRANS_SET (UCC_SLOW_UCCE_TXE|UCC_SLOW_UCCE_BSY| \
> + UCC_SLOW_UCCE_GRA|UCC_SLOW_UCCE_TX |UCC_SLOW_UCCE_RX | \
> + UCC_SLOW_UCCE_DCC|UCC_SLOW_UCCE_GLT|UCC_SLOW_UCCE_GLR)
> +#define UCC_SLOW_UCCE_UART_SET (UCC_SLOW_UCCE_BSY|UCC_SLOW_UCCE_GRA| \
> + UCC_SLOW_UCCE_TXB|UCC_SLOW_UCCE_TX |UCC_SLOW_UCCE_RX | \
> + UCC_SLOW_UCCE_GLT|UCC_SLOW_UCCE_GLR)
> +#define UCC_SLOW_UCCE_QMC_SET (UCC_SLOW_UCCE_IQOV|UCC_SLOW_UCCE_GINT| \
> + UCC_SLOW_UCCE_GUN|UCC_SLOW_UCCE_GOV)
> +
> +#define UCC_SLOW_UCCE_OTHER (UCC_SLOW_UCCE_TXE|UCC_SLOW_UCCE_BSY| \
> + UCC_SLOW_UCCE_GRA|UCC_SLOW_UCCE_DCC|UCC_SLOW_UCCE_GLT| \
> + UCC_SLOW_UCCE_GLR)
> +
> +#define UCC_SLOW_INTR_TX UCC_SLOW_UCCE_TXB
> +#define UCC_SLOW_INTR_RX (UCC_SLOW_UCCE_RXF | UCC_SLOW_UCCE_RX)
> +#define UCC_SLOW_INTR (UCC_SLOW_INTR_TX | UCC_SLOW_INTR_RX)
> +
> +/* Transmit On Demand (UTORD)
> +*/
> +#define UCC_SLOW_TOD 0x8000
> +#define UCC_FAST_TOD 0x8000
> +
> +/* Function code masks.
> +*/
> +#define FC_GBL 0x20
> +#define FC_DTB_LCL 0x02
> +#define UCC_FAST_FUNCTION_CODE_GBL 0x20
> +#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
> +#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
> +
> +#endif /* __QE_H__ */
> +#endif /* __KERNEL__ */
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* RE: how an application program utilizes the driver.
From: Eric Nuckols @ 2006-09-21 17:06 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <BAY110-F240E99BA0EDF765EC09402B2230@phx.gbl>
this probably isn't the level /topic to ask on the list, so I suggest
reading the Linux Device Drivers book...
you'll want to access the device via ioctl() calls , but there has to be a
little more involved to get to that point:
experiment with the scull device driver in this book
http://lwn.net/images/pdf/LDD3/ch06.pdf
----Original Message Follows----
From: "Ming Liu" <eemingliu@hotmail.com>
To: linuxppc-embedded@ozlabs.org
Subject: how an application program utilizes the driver.
Date: Wed, 20 Sep 2006 13:48:25 +0000
Dear all,
Maybe this question sounds stupid for most software engineers. But I really
have much confusion on this topic. So I have to ask for explanation.
My situation is: I want to write a driver for my custom device.(In the
driver there are some functions defined to read or write my device.) Then
in my application program, I use these defined functions to operate my
hardware device. I think this is a normal process to operate the hardware
with driver+app, right?
My driver is defined in drv_hello.c. I have compiled it into a module
drv_hello.ko and it could be insmoded or rmmoded correctly. It looks like:
//drv_hello.c
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
MODULE_LICENSE("Dual BSD/GPL");
void show_hello(){
printk("hello.\n");
}
static int hello_init(void){
printk(KERN_ALERT "module starts.\n");
return 0;
}
static void hello_exit(void){
printk(KERN_ALERT "module exits.\n");
}
module_init(hello_init);
module_exit(hello_exit);
EXPORT_SYMBOL(show_hello);
In my application program app_hello.c, I use the function show_hello to
achieve the simple task: print "hello" on the console. Here is my app
program:
//app_hello.c
extern void show_hello();
int main(int argc, char** argv)
{
show_hello();
return 0;
}
Then, here comes my problem: I don't know how to compile my application
program and then it could dynamically refer to the function show_hello()
defined in the memory area of the driver module. How can I tell the
compiler and linker that the app program is expected to be linked with the
driver module dynamically? If possible, please give me a detailed
explanation.
Waiting for your suggestion. Thanks for your help.
Regards
Ming
_________________________________________________________________
ÓëÁª»úµÄÅóÓѽøÐн»Á÷£¬ÇëʹÓà MSN Messenger: http://messenger.msn.com/cn
_______________________________________________
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* RE: Lite5200 NFS mount issue
From: Edward Jubenville @ 2006-09-21 16:43 UTC (permalink / raw)
To: Andersson Tord , Linuxppc-embedded
In-Reply-To: <18CE82D3EF6EA84F9A1A79D6051A090028500C@CORPAPPL020.corp.saab.se>
Tord Andersson wrote:
> When analyzing the IP traffic with Etherreal, it was seen that
> the problems were caused by loss of fragmented IP-packets. When
> the IP fragmentation was removed by forcing NFS's UDP size to
> less than the Ethernet MTU size, the problems disappeared.
> We used the kernel NFS argument option to this effect;
> nfsroot=${serverip}:${rootpath},rsize=1024,wsize=1024
You may not be having a board problem or a kernel problem. I had exactly
the same problem with an almost identical configuration as you. Using
Etherreal at various points in my network, I found that an Ethernet switch
in the communication path was dropping packets before the board ever saw
them. I solved it the same way that you did (with rsize/wsize), and it has
worked fine ever since.
See my post on 7/26/2006, subject "Re: Slow boot with NFS, server not
responding".
Ed Jubenville
^ permalink raw reply
* Re: How to move from /ppc/ to /powerpc/
From: Fredrik Roubert @ 2006-09-21 16:08 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20060913132817.GD18263@igloo.df.lth.se>
[-- Attachment #1.1: Type: text/plain, Size: 1614 bytes --]
Hi!
Now I've written an adapted DTS (see attachment) for my custom board,
based on the mpc8349emds.dts from the kernel source. I use Matthew
McClintock's patches to U-Boot to load the kernel with the DTD.
I compile the DTS using the following command line:
dtc -V 16 -I dts -O dtb px5500.dts > px5500.dtb
I've compiled an unmodified 2.6.18 kernel configured for powerpc and the
MPC834x SYS platform. The system boots OK and I can log in using SSH.
However, I have problems with the serial console. During boot, I get the
following printout:
Booting using flat device tree at 0x400000
Using MPC834x SYS machine description
Linux version 2.6.18 (frer@milou) (gcc version 4.1.1) #1 PREEMPT Thu Sep 21 17:31:30 CEST 2006
setup_arch: bootmem
mpc834x_sys_setup_arch()
Found MPC83xx PCI host bridge at 0x00000000ff408500. Firmware bus number: 0->0
arch: exit
Built 1 zonelists. Total pages: 32768
Kernel command line: root=/dev/nfs rw nfsroot=150.158.215.227:/home/rootfs/dev-ds ip=150.158.211.83:150.158.215.227:150.158.212.1:255.255.248.0:dev-ds:eth0:off console=ttyS0,115200 console=ttyS0,115200 rtc-x1205.force=0,0x6f
IPIC (128 IRQ sources) at fdefc700
PID hash table entries: 1024 (order: 10, 4096 bytes)
The serial console stops working after the call to console_init().
Except for the serial console, the system seems to be running fine. Does
anyone have any ideas about what might be wrong and how I could try to
track this problem down?
Cheers // Fredrik Roubert
--
Visserij 192 | +32 473 344527 / +46 708 776974
BE-9000 Gent | http://www.df.lth.se/~roubert/
[-- Attachment #1.2: px5500.dts --]
[-- Type: text/plain, Size: 3765 bytes --]
/ {
model = "PX5500";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8349@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
linux,boot-cpu;
};
};
memory {
device_type = "memory";
reg = <00000000 08000000>; // 128MB at 0
};
chosen {
name = "chosen";
linux,platform = <00000600>;
linux,stdout-path = "/soc8349@ff400000/serial@4500";
bootargs = "root=/dev/nfs rw nfsroot=150.158.215.227:/home/rootfs/dev-ds ip=150.158.211.83:150.158.215.227:150.158.212.1:255.255.248.0:dev-ds:eth0:off console=ttyS0,115200 console=ttyS0,115200 rtc-x1205.force=0,0x6f";
};
soc8349@ff400000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff400000 00100000>;
reg = <ff400000 00000200>;
bus-frequency = <0>;
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <e 8>;
interrupt-parent = <700>;
dfsrr;
};
mdio@24520 {
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
#address-cells = <1>;
#size-cells = <0>;
linux,phandle = <24520>;
ethernet-phy@0 {
linux,phandle = <2452000>;
interrupt-parent = <700>;
interrupts = <11 2>;
reg = <1>;
device_type = "ethernet-phy";
};
ethernet-phy@1 {
linux,phandle = <2452001>;
interrupt-parent = <700>;
interrupts = <12 2>;
reg = <3>;
device_type = "ethernet-phy";
};
};
ethernet@24000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
address = [ 00 00 00 00 00 00 ];
local-mac-address = [ 00 11 00 11 ff a1 ];
interrupts = <20 8 21 8 22 8>;
interrupt-parent = <700>;
phy-handle = <2452000>;
};
ethernet@25000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <25000 1000>;
address = [ 00 00 00 00 00 00 ];
local-mac-address = [ 00 11 00 11 ff a2 ];
interrupts = <23 8 24 8 25 8>;
interrupt-parent = <700>;
phy-handle = <2452001>;
};
serial@4500 {
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>;
clock-frequency = <0>;
interrupts = <9 8>;
interrupt-parent = <700>;
};
serial@4600 {
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>;
clock-frequency = <0>;
interrupts = <a 8>;
interrupt-parent = <700>;
};
pci@8500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0e */
7000 0 0 1 700 17 8
7000 0 0 2 700 00 8
7000 0 0 3 700 00 8
7000 0 0 4 700 00 8>;
interrupt-parent = <700>;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
compatible = "83xx";
device_type = "pci";
};
/* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
* sense == 8: Level, low assertion
* sense == 2: Edge, high-to-low change
*/
pic@700 {
linux,phandle = <700>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};
};
[-- Attachment #2: Type: application/pgp-signature, Size: 303 bytes --]
^ permalink raw reply
* Re: [PATCH 2/11] qe_lib: Add common files
From: Vitaly Bordug @ 2006-09-21 15:37 UTC (permalink / raw)
To: Li Yang; +Cc: linuxppc-dev
In-Reply-To: <F6AD7E21CDF4E145A44F61F43EE6D9399B44FE@tmnt04.transmode.se>
On Thu, 21 Sep 2006 17:21:39 +0200
"Joakim Tjernlund" <joakim.tjernlund@transmode.se> wrote:
> > diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
> > +#define QE_MURAM_DATAONLY_BASE ((uint)0x0)
> > +#define QE_MURAM_NOSPACE ((uint)0x7fffffff)
> > +#define QE_MURAM_DATAONLY_SIZE ((uint)(48 * 1024) -
> > QE_MURAM_DATAONLY_BASE)
>
> QE_MURAM_DATAONLY_SIZE is 16*1024 on 8321
>
> Also, you have line wrapping that has mangled all long lines in all
> patches.
>
Definitely. That is why I gave up on thunderbird a while ago...
I'd suggest to use either STGit embedded abilities, or git-send-email (combined with git-format-patch)
if non-attached stuff is required.
--
Sincerely,
Vitaly
^ permalink raw reply
* Re: [PATCH] Start arch/powerpc/boot code reorganization
From: Segher Boessenkool @ 2006-09-21 15:31 UTC (permalink / raw)
To: Matt Porter; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <20060921133707.GA29137@gate.crashing.org>
> On PPC44x (and other PowerPC processors) the number of address cells
> to represent a virtual address and a physical address differ due the
> 36-bits of physical address space.
The number of virtual address cells is always 1. A cell isn't always
32-bits though. Want more confusion? Lots of properties are called
"<something>-cells" etc., but those names are historical; the proper
name for the things encoded in properties is "32-bit integers".
> Regardless of the name of the
> new property, it should be defined to allow a different number of
> address cells to represent an address in virtual address space.
How about you check whether the "64-bit" property exists in the CPU
nodes?
>> (*) This isn't strictly correct, but OF doesn't describe the size of
>> virtual addresses anywhere. In practice, it's the same as the size
>> of physical addresses always. Oh, and the name "virtual" isn't
>> correct
>> in PowerPC-speak anyway, heh.
>
> Actually, in practice, it's not always the same size as a physical
> address. We have 36-bit physical addressing systems in the real world.
Darn, and you have #address-cells = 2 in the root node? It's allowed,
sure.
> FWIW, I'd be happy with this property name or fw,address. When we
> discussed this on IRC the thought was to conform to what already
> existed for this purpose in the OF spec. Since the address prop sounds
> like it will confuse some people I think it makes sense to add a
> new property (might as well just throw out the spec :P).
But if you do make something new, you'll have to make it better
than what you're replacing, or what's the point :-)
Segher
^ permalink raw reply
* Re: [PATCH 4/11] qe_lib: Add QE I/O ports API
From: Vitaly Bordug @ 2006-09-21 15:21 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: linuxppc-dev, Li Yang
In-Reply-To: <F6AD7E21CDF4E145A44F61F43EE6D9399B44EF@tmnt04.transmode.se>
On Thu, 21 Sep 2006 16:52:14 +0200
"Joakim Tjernlund" <joakim.tjernlund@transmode.se> wrote:
> Hi Leo
>
> As you know I working with your earlier patches, trying to adopt them
> for
> 8321. Everthing works but ethernet on UCC2 and UCC4, ethernet on UCC3
> works though.
>
> Anyhow I found some minor changes I had to do to match 8321 that is
> generic 83xx code.
> Below is the first:
> > ---
> > arch/powerpc/sysdev/qe_lib/qe_io.c | 272
> > +#define NUM_OF_PAR_IOS 7
>
> NUM_OF_PAR_IOS is 4 on 8321
>
> > +static int qe_irq_ports[NUM_OF_PAR_IOS][NUM_OF_PINS] = {
> > + /* 0-7 */ /* 8-15 */ /* 16 - 23 */ /*
> > 24 - 31 */
> > + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,1, 1,0,0,0,0,0,0,0,
> > 0,0,0,0,0,1,1,0},
> > + {0,0,0,1,0,1,0,0, 0,0,0,0,1,1,0,0, 0,0,0,0,0,0,0,0,
> > 0,0,1,1,0,0,0,0},
> > + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,
> > 0,0,0,1,1,1,0,0},
> > + {0,0,0,0,0,0,0,0, 0,0,0,0,1,1,0,0, 1,1,0,0,0,0,0,0,
> > 0,0,1,1,0,0,0,0},
> > + {0,0,0,0,0,0,0,0, 0,0,0,0,1,1,0,0, 0,0,0,0,0,0,0,0,
> > 1,1,1,1,0,0,0,1},
> > + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,1,0,0,0,
> > 0,0,0,0,0,0,0,0},
> > + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,
> > 0,0,0,0,0,0,0,1}
> > +};
>
> qe_irq_ports is diffrent on 8321 not only the number of rows.
>
> These needs to configuruable based on CPU model and/or type of board.
>
Well, eventually this stuff aims to serve not 83xx/qe, but for cpm(1,2)-equipped stuff
too. Apparently, we'll have to do something wise to afford that...
OTOH, this is good as a starting point I guess.
--
Sincerely,
Vitaly
^ permalink raw reply
* RE: [PATCH 2/11] qe_lib: Add common files
From: Joakim Tjernlund @ 2006-09-21 15:21 UTC (permalink / raw)
To: Li Yang, linuxppc-dev
> diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
> +#define QE_MURAM_DATAONLY_BASE ((uint)0x0)
> +#define QE_MURAM_NOSPACE ((uint)0x7fffffff)
> +#define QE_MURAM_DATAONLY_SIZE ((uint)(48 * 1024) -=20
> QE_MURAM_DATAONLY_BASE)
QE_MURAM_DATAONLY_SIZE is 16*1024 on 8321
Also, you have line wrapping that has mangled all long lines in all
patches.
Jocke
^ permalink raw reply
* Re: [PATCH]: powerpc: clarify use of twi/isync in io macros
From: Segher Boessenkool @ 2006-09-21 15:06 UTC (permalink / raw)
To: Paul Mackerras; +Cc: Stephen Rothwell, ppc-dev
In-Reply-To: <17682.34922.240565.233215@cargo.ozlabs.ibm.com>
>> + * A data-dependent branch followed by an isync ensures that no
>> + * instructions after the isync in program order will be
>> + * (speculatively) executed, so the load that the twi depends
>> + * on has to complete before anything else is executed; in
>
> While the statement about branches is true, it's not especially
> relevant when it comes to twi.
twi is a data-dependent branch -- all exceptions are branches (well
they do change the execution flow!), and this one is generated
directly by an insn even. Traps and "normal" branches are neighbours
in the opcode maps, too, FWIW ;-)
> What's happening is that isync has to
> prevent any following instructions from starting execution until all
> previous instructions have completed, meaning that they have got to
> the point of knowing whether they will generate an exception or not.
It also has to know whether the isync will be executed at all, in
the sequential model.
> In general the processor doesn't know whether twi will generate an
> exception until the data it depends on is available, and that's why
> the isync has to wait for the previous load to have returned the
> data.
Yeah, the main point is that the load insn can complete _before_
the data has come back ("the storage access has been performed"),
so an isync without another insn depending on the load result
won't do.
Care to write some better explanatory text than the rubbish I
came up with? :-)
Btw, you say "in general the CPU doesn't know", but it _can_ know
in this code, as the TO field is 0 (so it can never trap). Is
there anything preventing/forbidding a CPU from optimising this
case? I see it spelled out for "conditional branch" insns, but
it would be interesting to know if the arch guarantees no insn
will complete before its input regs are ready.
^ permalink raw reply
* RE: [PATCH 4/11] qe_lib: Add QE I/O ports API
From: Joakim Tjernlund @ 2006-09-21 14:52 UTC (permalink / raw)
To: Li Yang, linuxppc-dev
Hi Leo
As you know I working with your earlier patches, trying to adopt them
for
8321. Everthing works but ethernet on UCC2 and UCC4, ethernet on UCC3
works though.
Anyhow I found some minor changes I had to do to match 8321 that is
generic 83xx code.
Below is the first:
> ---
> arch/powerpc/sysdev/qe_lib/qe_io.c | 272=20
> +#define NUM_OF_PAR_IOS 7
NUM_OF_PAR_IOS is 4 on 8321
> +static int qe_irq_ports[NUM_OF_PAR_IOS][NUM_OF_PINS] =3D {
> + /* 0-7 */ /* 8-15 */ /* 16 - 23 */ /*=20
> 24 - 31 */
> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,1, 1,0,0,0,0,0,0,0,=20
> 0,0,0,0,0,1,1,0},
> + {0,0,0,1,0,1,0,0, 0,0,0,0,1,1,0,0, 0,0,0,0,0,0,0,0,=20
> 0,0,1,1,0,0,0,0},
> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,=20
> 0,0,0,1,1,1,0,0},
> + {0,0,0,0,0,0,0,0, 0,0,0,0,1,1,0,0, 1,1,0,0,0,0,0,0,=20
> 0,0,1,1,0,0,0,0},
> + {0,0,0,0,0,0,0,0, 0,0,0,0,1,1,0,0, 0,0,0,0,0,0,0,0,=20
> 1,1,1,1,0,0,0,1},
> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,1,0,0,0,=20
> 0,0,0,0,0,0,0,0},
> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,=20
> 0,0,0,0,0,0,0,1}
> +};
qe_irq_ports is diffrent on 8321 not only the number of rows.
These needs to configuruable based on CPU model and/or type of board.
Jocke
^ permalink raw reply
* RE: Lite5200 NFS mount issue
From: Andersson Tord @ 2006-09-21 14:53 UTC (permalink / raw)
To: Linuxppc-embedded
Hi,
I have some additional information on the problems we had with NFS on =
the Lite5200 card and the=20
2.4.25 kernel (DENX linuxppc_2_4_devel 2006-04-06) .=20
When analyzing the IP traffic with Etherreal, it was seen that the =
problems were=20
caused by loss of fragmented IP-packets. When the IP fragmentation was =
removed by forcing NFS's=20
UDP size to less than the Ethernet MTU size, the problems disappeared.=20
We used the kernel NFS argument option to this effect;
nfsroot=3D${serverip}:${rootpath},rsize=3D1024,wsize=3D1024
Still, the question remains, why do fragmented packets get lost? Do =
anyone know of any related FEC/BESTCOMM/driver/buffer issues which might =
cause this problem? The problem also exist with the 5200B version.=20
Regards,
Tord Andersson
=20
> -----Original Message-----
> From:
> linuxppc-embedded-bounces+tord.andersson=3Dcombitechsystems.com@
> ozlabs.org
> [mailto:linuxppc-embedded-bounces+tord.andersson=3Dcombitechsyst
> ems.com@ozlabs.org] On Behalf Of Bj=F6rn =D6stby
> Sent: den 20 juni 2006 10:15
> To: linuxppc-embedded@ozlabs.org
> Subject: Lite5200 NFS mount issue
>=20
>=20
> Hi all,
> I'm using u-boot 1.1.4 (CVS downloaded 2006-05-04) and ELDK
> 4.0. I've encountered=20
> problems when trying to mount a NFS root filesystem when=20
> using the Lite MPC5200 development board. The system mounts=20
> ok when the board is connected to office wide=20
> network switches but if the board is connected directly=20
> through a small 100/10Mbit switch to the NFS server, the=20
> mount halts as shown in the log below (The 100/10Mbit switch=20
> do work as other boards can mount their filesystem through=20
> these). Does anyone recognize this problem and know a=20
> suitable work-around/solution?
>=20
> =3D>run flash_nfs
> ## Booting image at ff0a0000 ...
> Image Name: Linux-2.4.25
> Created: 2006-06-16 13:11:56 UTC
> Image Type: PowerPC Linux Kernel Image (gzip compressed)
> Data Size: 945550 Bytes =3D 923.4 kB
> Load Address: 00000000
> Entry Point: 00000000
> Verifying Checksum ... OK
> Uncompressing Kernel Image ... OK
> Memory BAT mapping: BAT2=3D64Mb, BAT3=3D0Mb, residual: 0Mb
> Linux version 2.4.25 (tord@toshiba) (gcc version 4.0.0 (DENX
> ELDK 4.0 4.0.0)) #1 fre jun 16 14:46:35 CEST 2006 On node 0=20
> totalpages: 16384
> zone(0): 16384 pages.
> zone(1): 0 pages.
> zone(2): 0 pages.
> Kernel command line: root=3D/dev/nfs rw=20
> nfsroot=3D10.3.67.98:/opt/eldk_4_0/ppc_6xx=20
> ip=3D10.3.67.99:10.3.67.98:10.3.67.1:::eth0:off panic=3D1=20
...
> Looking up port of RPC 100003/2 on 10.3.67.98
> Looking up port of RPC 100005/1 on 10.3.67.98
> VFS: Mounted root (nfs filesystem).
> Freeing unused kernel memory: 80k init
> nfs: server 10.3.67.98 not responding, still trying
> nfs: server 10.3.67.98 OK
> nfs: server 10.3.67.98 not responding, still trying
> nfs: server 10.3.67.98 OK
> [time to this about 5 minutes]
> INIT: version 2.85 booting
> nfs: server 10.3.67.98 not responding, still trying
> nfs: server 10.3.67.98 OK
> nfs: server 10.3.67.98 not responding, still trying
> nfs: server 10.3.67.98 OK
>=20
> Regards,
> Bjorn Ostby
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>=20
^ permalink raw reply
* Kernel hangs after "Now booting the kernel"
From: Brian Rutledge @ 2006-09-21 14:50 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 1550 bytes --]
Hi
I am using an Embedded Planet 852T board with a planet core
bootloader. I am trying to boot the kernel (2.6) and the boot sequence
gets as far as:
>go
[Go 00200000]
loaded at: 00200000 0030A160
relocated to: 00400000 0050A160
board data at: 00508124 00508140
relocated to: 004050B4 004050D0
zimage at: 004058FD 0050704A
avail ram: 0050B000 01000000
Linux/PPC load: console=ttyS0,9600 console=tty0 root=/dev/ram0
init=/linuxrc rw
Uncompressing Linux...done.
Now booting the kernel
After which nothing happens.
Does the kernel try an set up the serial port at this point
or can I assume that the serial is operational based on the output up to
this point?
Are there any other areas I should be looking at?
Thanks Brian
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^ permalink raw reply
* Re: [Fastboot] [PATCH] kexec: remove memory reserve patching for powerpc device tree
From: Vivek Goyal @ 2006-09-21 14:32 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev, Horms, Fastboot mailing list
In-Reply-To: <E1GQPNv-0003yi-H5@jdl.com>
On Thu, Sep 21, 2006 at 09:18:39AM -0500, Jon Loeliger wrote:
> So, like, the other day Vivek Goyal mumbled:
> >
> > Now with distros adopting kexce-tools, I am in for maintaining the backward
> > compatibility as far as possible. Putting a note in the code is good that
> > down the line, get rid of this code.
>
> Perhaps scheduling it as an entry in
>
> Documentation/feature-removal-schedule.txt
>
> just so people (distros) can plan around it?
Perfect. In kexec-tools it can go in doc/feature-removal-schedule.txt.
-Vivek
^ permalink raw reply
* Re: [PATCH] Start arch/powerpc/boot code reorganization
From: Matt Porter @ 2006-09-21 14:26 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <E1GQPKk-0003y1-Uq@jdl.com>
On Thu, Sep 21, 2006 at 09:15:22AM -0500, Jon Loeliger wrote:
> So, like, the other day Matt Porter mumbled:
> >
> > Since the address prop sounds
> > like it will confuse some people I think it makes sense to add a
> > new property (might as well just throw out the spec :P).
>
> Ayyyy, mate. She be not so much a "code" as she be a "guideline".
Yeah, yeah, of course. We only use it when convenient.
> Huh? That was the other day? Neeeveeer mind.
:)
-Matt
^ permalink raw reply
* Re: [Fastboot] [PATCH] kexec: remove memory reserve patching for powerpc device tree
From: Jon Loeliger @ 2006-09-21 14:18 UTC (permalink / raw)
To: vgoyal; +Cc: linuxppc-dev, Horms, Fastboot mailing list
In-Reply-To: <20060921135534.GA1542@in.ibm.com>
So, like, the other day Vivek Goyal mumbled:
>
> Now with distros adopting kexce-tools, I am in for maintaining the backward
> compatibility as far as possible. Putting a note in the code is good that
> down the line, get rid of this code.
Perhaps scheduling it as an entry in
Documentation/feature-removal-schedule.txt
just so people (distros) can plan around it?
jdl
^ permalink raw reply
* Re: [PATCH] Start arch/powerpc/boot code reorganization
From: Jon Loeliger @ 2006-09-21 14:15 UTC (permalink / raw)
To: Matt Porter; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <20060921133707.GA29137@gate.crashing.org>
So, like, the other day Matt Porter mumbled:
>
> Since the address prop sounds
> like it will confuse some people I think it makes sense to add a
> new property (might as well just throw out the spec :P).
Ayyyy, mate. She be not so much a "code" as she be a "guideline".
Huh? That was the other day? Neeeveeer mind.
jdl
^ permalink raw reply
* Re: IDE not found on Performa due to interrupt breakage
From: Olaf Hering @ 2006-09-21 14:14 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1158839781.26347.106.camel@localhost.localdomain>
On Thu, Sep 21, Benjamin Herrenschmidt wrote:
> On Thu, 2006-09-21 at 13:50 +0200, Olaf Hering wrote:
> > The IDE controller is not usable on a Performa 6400 with 2.6.18:
> >
> > <6>hda: Enabling MultiWord DMA 2
> > <4>ide0: Disabled unable to get IRQ 13.
> > <6>ide0: failed to initialize IDE interface
>
> .../...
>
> Looks like a workaround for bogus OF bitrotted... What about this patch:
This patch work ok. Thanks.
^ permalink raw reply
* Re: [Fastboot] [PATCH] kdump: don't call __ioremap() for pfn = 0
From: Vivek Goyal @ 2006-09-21 14:10 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, paulus, Fastboot mailing list
In-Reply-To: <1158836557.7062.52.camel@localhost.localdomain>
On Thu, Sep 21, 2006 at 09:02:37PM +1000, Michael Ellerman wrote:
> On Thu, 2006-09-21 at 10:07 +0530, Sachin P. Sant wrote:
> > Hi
> >
> > While using dd command to retrive the dump from /dev/oldmem, there comes
> > a rare case where pfn value is zero. In this case the __ioremap() call
> > returns
> > NULL and hence copying fails.
> >
> > # dd if=/dev/oldmem of=/dev/null
> > dd: reading `/dev/oldmem': Bad address
> > 0+0 records in
> > 0+0 records out
> > 0 bytes (0 B) copied, 0.000121 seconds, 0.0 kB/s
> >
> > Attached is a patch to fix this problem. During such rare cases don't call
> > __ioremap() to do the address translation, instead use __va() .
>
> It's not really rare, it's just when we're reading /dev/oldmem directly.
>
> We can actually use the __va() trick for the whole linear mapping rather
> than just pfn 0, which saves the ioremap. We also shouldn't really be
> trying to iounmap(__va(0)).
>
Makes sense. We can take advantage of linear mappings mapped till max_pfn
and avoid ioremap().
> +
> +static size_t copy_oldmem_vaddr(void *vaddr, char *buf, size_t csize,
> + unsigned long offset, int userbuf)
> +{
> + if (userbuf) {
> + if (copy_to_user((char __user *)buf, (vaddr + offset), csize)) {
> + return -EFAULT;
> + }
Probably you can get rid of above pair of braces as there is only single
statement under if.
>
> - if (userbuf) {
> - if (copy_to_user((char __user *)buf, (vaddr + offset), csize)) {
> - iounmap(vaddr);
> - return -EFAULT;
> - }
> - } else
> - memcpy(buf, (vaddr + offset), csize);
> + if (pfn < max_pfn) {
Should this be (pfn <= max_pfn) ?
-Vivek
^ permalink raw reply
* Re: [Fastboot] [PATCH] kexec: remove memory reserve patching for powerpc device tree
From: Vivek Goyal @ 2006-09-21 13:55 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Horms, Fastboot mailing list
In-Reply-To: <1158810033.7062.23.camel@localhost.localdomain>
On Thu, Sep 21, 2006 at 01:40:33PM +1000, Michael Ellerman wrote:
> On Thu, 2006-09-21 at 11:51 +0900, Horms wrote:
> > On Thu, Sep 21, 2006 at 11:59:04AM +1000, Michael Ellerman wrote:
> > > On Thu, 2006-09-21 at 11:10 +1000, Michael Neuling wrote:
> > > > This code no longer needed with Jimi's auto reserve of device tree blob
> > > > kernel patch now in 2.6.18.
> > > >
> > > > This patch will break Linux if you're kexecing to a kernel which doesn't
> > > > have this patch (ie. earlier than 2.6.17). Required kernel patch is
> > > > this one:
> > > > http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=4d1f3f25d9c303d1ce63b42cc94c54ac0ab2e950
> > > >
> > >
> > > Although it'd be nice to get rid of that code, I'm not sure we want to
> > > go breaking this. This will mean RHEL5 and SLES10 users can't use
> > > upstream kexec-tools :/
> >
> > Surely if they are using a RHEL5 or SLES10 kernel then its
> > reasonably to expect they are also using a RHEL5 or SLES10 supplied
> > kexec-tool.
>
> Or Ubuntu Dapper .. Debian Stable .. FC whatever. In general they'll be
> using the distro tools sure, but I'd rather not force them to. I
> generally expect to be able to run mainline kernels without upgrading my
> entire distro - it should cut both ways IMHO.
>
Now with distros adopting kexce-tools, I am in for maintaining the backward
compatibility as far as possible. Putting a note in the code is good that
down the line, get rid of this code.
-Vivek
^ permalink raw reply
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