* glibc-2.5 test suite hangs/crashes the machine
From: Fabio Massimo Di Nitto @ 2006-10-27 5:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: linuxppc-dev, Jeff Bailey, Ben Collins
Hi everybody,
i am in the process of bootstrapping the new toolchain for ubuntu and I am
hitting a problem building glibc-2.5 on ppc.
This behaviour has been reproduced on 2.6.15/2.6.17 and 2.6.19-rc2 (where the
machine crashes) and with ppc32 and ppc64 kernels.
A hard reboot of the machine is required to get rid of the Zl processes hanging
around that keep spinning the CPU at 100%.
I did place sources here: http://people.ubuntu.com/~fabbione/benh/
but i start to believe it is a kernel bug we are exploiting only now.
Any hint or help for what to look for would be extremely appreciated.
Thanks
Fabio
--
I'm going to make him an offer he can't refuse.
^ permalink raw reply
* Re: MPC5200 (Board: PM520) I2C Problem
From: Andrey Volkov @ 2006-10-27 7:29 UTC (permalink / raw)
To: RPo; +Cc: 'linuxppc-embedded@ozlabs.org'
In-Reply-To: <F05B338A1B21D9119FFF0004761A51136AB28E@exchange-server.ow.ks>
Hello Rainer
RPo wrote:
> Hi,
>
> I'm currently using the MPC5200 based board "PM520" and
> want to access the I2C bus. To do so, I attached a PCF8574P
> to the bus. But I was not successful in setting the outputs
> of this IC.
<...snip..>
Revision of MPC5200? (third string engraved on the MPC)
If L25R then check this doco:
http://www.freescale.com/files/32bit/doc/errata/MPC5200E.pdf
(if be short - I2C didn't work on this revision chips)
--
Regards
Andrey Volkov
^ permalink raw reply
* Re: CPM2 SCC/SMC break handling broken
From: Laurent Pinchart @ 2006-10-27 9:01 UTC (permalink / raw)
To: Ricardo Scop; +Cc: linuxppc-embedded
In-Reply-To: <200610261918.37769.scop@digitel.com.br>
Hi Ricardo,
> > Hi everybody,
> >
> > I need to generate a break on a CPM2 SMC serial port (same issue with SCC
> > serial ports).
> >
> > The tcsendbreak() man page states that the function should generate a
> > break between 250ms and 500ms, but testing showed that the break is one
> > character long (10 bits in 8N1 mode).
>
> [snip]
>
> > CPM_CR_STOP_TX is documented to generate a break of BRKCR characters. The
> > BRKCR register is initialized to 1, so only 1 break character is sent,
> > which won't last between 250ms and 500ms.
>
> [snip]
>
> > Could anyone think of a proper solution which would not disturb the other
> > drivers too much ?
>
> Well, one could always set the BRKCR parameter to the maximum number of
> break characters permitted by it's size, since the break condition will
> anyway end as soon as the RESTART TX command is issued as a consequence of
> the tty->driver->break_ctl(tty, 0) call. But I did not test this.
That's a very good idea, but the documentation is a bit misleading here. I
tested the CPM2 behaviour, and found out that the break will last BRKCR
characters, even if a RESTART TX command is sent sooner.
The user manual states
"The SMC sends a programmable number of break characters according to BRKCR
and reverts to idle or sends data if a RESTART TRANSMIT is issued before
completion."
I suppose they meant that, if a RESTART TX command is issued before completion
of the break sequence, the SMC will send data at the end of the break
sequence. This is at least the behaviour I noticed after trying your idea.
Laurent Pinchart
^ permalink raw reply
* Re: [POWERPC] MPC52xx is a 6xx variant, remove PPC_52xx config option
From: Andrey Volkov @ 2006-10-27 9:56 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-embedded
In-Reply-To: <11618347593934-git-send-email-grant.likely@secretlab.ca>
Grant Likely wrote:
> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> ---
> arch/powerpc/Kconfig | 5 -----
> 1 files changed, 0 insertions(+), 5 deletions(-)
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index f9b11c1..6bff8b7 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -126,11 +126,6 @@ config CLASSIC32
> systems, 64 bit IBM RS/6000 or an Apple G5, choose 6xx.
> Note that the kernel runs in 32-bit mode even on 64-bit chips.
>
> -config PPC_52xx
> - bool "Freescale 52xx"
> - select 6xx
> - select PPC_FPU
> -
> config PPC_82xx
> bool "Freescale 82xx"
> select 6xx
Please _don't_ do it, since mpc5200 platform drivers depend from this
option.
--
Regards
Andrey Volkov
^ permalink raw reply
* Re: [POWERPC] MPC52xx is a 6xx variant, remove PPC_52xx config option
From: Benjamin Herrenschmidt @ 2006-10-27 10:24 UTC (permalink / raw)
To: Andrey Volkov; +Cc: linuxppc-embedded
In-Reply-To: <4541D7D5.7090001@varma-el.com>
On Fri, 2006-10-27 at 13:56 +0400, Andrey Volkov wrote:
> Grant Likely wrote:
> > Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> > ---
> > arch/powerpc/Kconfig | 5 -----
> > 1 files changed, 0 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> > index f9b11c1..6bff8b7 100644
> > --- a/arch/powerpc/Kconfig
> > +++ b/arch/powerpc/Kconfig
> > @@ -126,11 +126,6 @@ config CLASSIC32
> > systems, 64 bit IBM RS/6000 or an Apple G5, choose 6xx.
> > Note that the kernel runs in 32-bit mode even on 64-bit chips.
> >
> > -config PPC_52xx
> > - bool "Freescale 52xx"
> > - select 6xx
> > - select PPC_FPU
> > -
> > config PPC_82xx
> > bool "Freescale 82xx"
> > select 6xx
> Please _don't_ do it, since mpc5200 platform drivers depend from this
> option.
And that should be fixed. We are yet discussing the proper way of
integrating 52xx in arch/powerpc, but that definitely doesn't involve
making it an exclusive processor type. Besides, there will probably be
enough changes in the drivers to adapt them to of_platform_device type
probing that we might just well fork them all anyway.
Ben.
^ permalink raw reply
* Re: [PATCH 2.6.19-rc3 1/2] ehea: kzalloc GFP_ATOMIC fix
From: Christoph Raisch @ 2006-10-27 11:17 UTC (permalink / raw)
To: Andrew Morton
Cc: Thomas Q Klein, Jeff Garzik, Jan-Bernd Themann, netdev,
linux-kernel, linux-ppc, Marcus Eder
In-Reply-To: <20061026201313.9c831fc9.akpm@osdl.org>
Andrew Morton <akpm@osdl.org> wrote on 27.10.2006 05:13:13:
> On Wed, 25 Oct 2006 13:11:42 +0200
> Jan-Bernd Themann <ossthema@de.ibm.com> wrote:
>
> > This patch fixes kzalloc parameters (GFP_ATOMIC instead of GFP_KERNEL)
>
> why?
these few kcallocs run in atomic context in some situations.
therefore GFP_KERNEL is no good idea.
Christoph R.
^ permalink raw reply
* Re: MPC5200 (Board: PM520) I2C Problem
From: Roman Fietze @ 2006-10-27 11:15 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <4541B547.1010908@varma-el.com>
[-- Attachment #1: Type: text/plain, Size: 818 bytes --]
Hello,
On Friday 27 October 2006 09:29, Andrey Volkov wrote:
> Revision of MPC5200? (third string engraved on the MPC)
> If L25R then check this doco:
> http://www.freescale.com/files/32bit/doc/errata/MPC5200E.pdf
> (if be short - I2C didn't work on this revision chips)
We have an "MPC5200CBV400 L25R Rev 2" on our boards, and we
successfully drive a PCF8563 real time clock and an UDA1380 Codec on
the same line.
The problems described in the errata are an arbitration loss problem
and, depending on teh chp's Rev, a clock noise problem.
Probably your problem is related to the connected I2C client?
Roman
--
Roman Fietze Telemotive AG Büro Mühlhausen
Breitwiesen 73347 Mühlhausen
Tel.: +49(0)7335/18493-45 http://www.telemotive.de
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* [PATCH] Powerpc: Make pci_read_irq_line the default: on mpc7448hpc2 board
From: Zang Roy-r61911 @ 2006-10-27 11:51 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev list, Alexandre.Bounine@tundra.com
In-Reply-To: <1161141538.24931.9.camel@localhost.localdomain>
The following patch updates the tsi108/9 pci interrupt controller code
on mpc7448hpc2 board.
The patch should apply after Ben's patch
http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027287.html
Of course, the mpc7448hpc2 part in that patch should be replaced by this
one :-).
---
arch/powerpc/boot/dts/mpc7448hpc2.dts | 44 ++++++----
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c | 96 +++++----------------
arch/powerpc/sysdev/tsi108_pci.c | 63 ++++++++++++--
3 files changed, 108 insertions(+), 95 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index d7b985e..3f9454e 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -161,29 +161,41 @@
interrupt-map = <
/* IDSEL 0x11 */
- 0800 0 0 1 7400 24 0
- 0800 0 0 2 7400 25 0
- 0800 0 0 3 7400 26 0
- 0800 0 0 4 7400 27 0
+ 0800 0 0 1 1180 24 0
+ 0800 0 0 2 1180 25 0
+ 0800 0 0 3 1180 26 0
+ 0800 0 0 4 1180 27 0
/* IDSEL 0x12 */
- 1000 0 0 1 7400 25 0
- 1000 0 0 2 7400 26 0
- 1000 0 0 3 7400 27 0
- 1000 0 0 4 7400 24 0
+ 1000 0 0 1 1180 25 0
+ 1000 0 0 2 1180 26 0
+ 1000 0 0 3 1180 27 0
+ 1000 0 0 4 1180 24 0
/* IDSEL 0x13 */
- 1800 0 0 1 7400 26 0
- 1800 0 0 2 7400 27 0
- 1800 0 0 3 7400 24 0
- 1800 0 0 4 7400 25 0
+ 1800 0 0 1 1180 26 0
+ 1800 0 0 2 1180 27 0
+ 1800 0 0 3 1180 24 0
+ 1800 0 0 4 1180 25 0
/* IDSEL 0x14 */
- 2000 0 0 1 7400 27 0
- 2000 0 0 2 7400 24 0
- 2000 0 0 3 7400 25 0
- 2000 0 0 4 7400 26 0
+ 2000 0 0 1 1180 27 0
+ 2000 0 0 2 1180 24 0
+ 2000 0 0 3 1180 25 0
+ 2000 0 0 4 1180 26 0
>;
+ router@1180 {
+ linux,phandle = <1180>;
+ clock-frequency = <0>;
+ interrupt-controller;
+ device_type = "pic-router";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ built-in;
+ big-endian;
+ interrupts = <17 2>;
+ interrupt-parent = <7400>;
+ };
};
};
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index bdb475c..c77be14 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -60,7 +60,7 @@ #endif
extern int tsi108_setup_pci(struct device_node *dev);
extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
-extern void tsi108_pci_int_init(void);
+extern void tsi108_pci_int_init(struct device_node *node);
extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
int mpc7448_hpc2_exclude_device(u_char bus, u_char devfn)
@@ -71,65 +71,6 @@ int mpc7448_hpc2_exclude_device(u_char b
return PCIBIOS_SUCCESSFUL;
}
-/*
- * find pci slot by devfn in interrupt map of OF tree
- */
-u8 find_slot_by_devfn(unsigned int *interrupt_map, unsigned int devfn)
-{
- int i;
- unsigned int tmp;
- for (i = 0; i < 4; i++){
- tmp = interrupt_map[i*4*7];
- if ((tmp >> 11) == (devfn >> 3))
- return i;
- }
- return i;
-}
-
-/*
- * Scans the interrupt map for pci device
- */
-void mpc7448_hpc2_fixup_irq(struct pci_dev *dev)
-{
- struct pci_controller *hose;
- struct device_node *node;
- const unsigned int *interrupt;
- int busnr;
- int len;
- u8 slot;
- u8 pin;
-
- /* Lookup the hose */
- busnr = dev->bus->number;
- hose = pci_bus_to_hose(busnr);
- if (!hose)
- printk(KERN_ERR "No pci hose found\n");
-
- /* Check it has an OF node associated */
- node = (struct device_node *) hose->arch_data;
- if (!node)
- printk(KERN_ERR "No pci node found\n");
-
- interrupt = get_property(node, "interrupt-map", &len);
- slot = find_slot_by_devfn(interrupt, dev->devfn);
- pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
- if (pin == 0 || pin > 4)
- pin = 1;
- pin--;
- dev->irq = interrupt[slot*4*7 + pin*7 + 5];
- DBG("TSI_PCI: dev->irq = 0x%x\n", dev->irq);
-}
-/* temporary pci irq map fixup*/
-
-void __init mpc7448_hpc2_pcibios_fixup(void)
-{
- struct pci_dev *dev = NULL;
- for_each_pci_dev(dev) {
- mpc7448_hpc2_fixup_irq(dev);
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
- }
-}
-
static void __init mpc7448_hpc2_setup_arch(void)
{
struct device_node *cpu;
@@ -192,9 +133,12 @@ static void __init mpc7448_hpc2_init_IRQ
{
struct mpic *mpic;
phys_addr_t mpic_paddr = 0;
+ struct device_node *tsi_pic;
+#ifdef CONFIG_PCI
unsigned int cascade_pci_irq;
struct device_node *tsi_pci;
- struct device_node *tsi_pic;
+ struct device_node *cascade_node = NULL;
+#endif
tsi_pic = of_find_node_by_type(NULL, "open-pic");
if (tsi_pic) {
@@ -208,31 +152,41 @@ static void __init mpc7448_hpc2_init_IRQ
return;
}
- DBG("%s: tsi108pic phys_addr = 0x%x\n", __FUNCTION__,
+ DBG("%s: tsi108 pic phys_addr = 0x%x\n", __FUNCTION__,
(u32) mpic_paddr);
mpic = mpic_alloc(tsi_pic, mpic_paddr,
MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
- 0, /* num_sources used */
- 0, /* num_sources used */
+ 24,
+ NR_IRQS-4, /* num_sources used */
"Tsi108_PIC");
- BUG_ON(mpic == NULL); /* XXXX */
+ BUG_ON(mpic == NULL);
+
+ mpic_assign_isu(mpic, 0, mpic_paddr + 0x100);
+
mpic_init(mpic);
-
+
+#ifdef CONFIG_PCI
tsi_pci = of_find_node_by_type(NULL, "pci");
- if (tsi_pci == 0) {
+ if (tsi_pci == NULL) {
printk("%s: No tsi108 pci node found !\n", __FUNCTION__);
return;
}
+ cascade_node = of_find_node_by_type(NULL, "pic-router");
+ if (cascade_node == NULL) {
+ printk("%s: No tsi108 pci cascade node found !\n", __FUNCTION__);
+ return;
+ }
cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0);
+ DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __FUNCTION__,
+ (u32) cascade_pci_irq);
+ tsi108_pci_int_init(cascade_node);
set_irq_data(cascade_pci_irq, mpic);
set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
-
- tsi108_pci_int_init();
-
+#endif
/* Configure MPIC outputs to CPU0 */
tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
of_node_put(tsi_pic);
@@ -290,7 +244,6 @@ static int mpc7448_machine_check_excepti
return 1;
}
return 0;
-
}
define_machine(mpc7448_hpc2){
@@ -300,7 +253,6 @@ define_machine(mpc7448_hpc2){
.init_IRQ = mpc7448_hpc2_init_IRQ,
.show_cpuinfo = mpc7448_hpc2_show_cpuinfo,
.get_irq = mpic_get_irq,
- .pcibios_fixup = mpc7448_hpc2_pcibios_fixup,
.restart = mpc7448_hpc2_restart,
.calibrate_decr = generic_calibrate_decr,
.machine_check_exception= mpc7448_machine_check_exception,
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c
index 322f86e..059d34a 100644
--- a/arch/powerpc/sysdev/tsi108_pci.c
+++ b/arch/powerpc/sysdev/tsi108_pci.c
@@ -3,6 +3,8 @@
*
* 2004-2005 (c) Tundra Semiconductor Corp.
* Author: Alex Bounine (alexandreb@tundra.com)
+ * Author: Roy Zang (tie-fei.zang@freescale.com)
+ * Add pci interrupt router host
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
@@ -48,6 +50,8 @@ #define tsi_mk_config_addr(bus, devfunc,
u32 tsi108_pci_cfg_base;
u32 tsi108_csr_vir_base;
+static struct device_node *pci_irq_node;
+static struct irq_host *pci_irq_host;
extern u32 get_vir_csrbase(void);
extern u32 tsi108_read_reg(u32 reg_offset);
@@ -378,6 +382,51 @@ static struct irq_chip tsi108_pci_irq =
.unmask = tsi108_pci_irq_enable,
};
+static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct,
+ u32 *intspec, unsigned int intsize,
+ irq_hw_number_t *out_hwirq, unsigned int *out_flags)
+{
+ *out_hwirq = intspec[0];
+ *out_flags = IRQ_TYPE_LEVEL_HIGH;
+ return 0;
+}
+
+static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t hw)
+{ unsigned int irq;
+ DBG("%s(%d, 0x%lx)\n", __FUNCTION__, virq, hw);
+ if ((virq >= 1) && (virq <= 4)){
+ irq = virq + IRQ_PCI_INTAD_BASE - 1;
+ get_irq_desc(irq)->status |= IRQ_LEVEL;
+ set_irq_chip(irq, &tsi108_pci_irq);
+ }
+ return 0;
+}
+static void pci_irq_host_unmap(struct irq_host *h, unsigned int virq)
+{
+ /* Make sure irq is masked in hardware */
+
+ tsi108_pci_int_mask(virq);
+
+ /* remove chip and handler */
+ set_irq_chip_and_handler(virq, NULL, NULL);
+
+ /* Make sure it's completed */
+ synchronize_irq(virq);
+}
+
+static int pci_irq_host_match(struct irq_host *h, struct device_node *node)
+{
+ return pci_irq_node == NULL || pci_irq_node == node;
+}
+
+static struct irq_host_ops pci_irq_host_ops = {
+ .match = pci_irq_host_match,
+ .map = pci_irq_host_map,
+ .unmap = pci_irq_host_unmap,
+ .xlate = pci_irq_host_xlate,
+};
+
/*
* Exported functions
*/
@@ -391,15 +440,15 @@ static struct irq_chip tsi108_pci_irq =
* to the MPIC.
*/
-void __init tsi108_pci_int_init(void)
+void __init tsi108_pci_int_init(struct device_node *node)
{
- u_int i;
-
DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
-
- for (i = 0; i < NUM_PCI_IRQS; i++) {
- irq_desc[i + IRQ_PCI_INTAD_BASE].chip = &tsi108_pci_irq;
- irq_desc[i + IRQ_PCI_INTAD_BASE].status |= IRQ_LEVEL;
+
+ pci_irq_node = of_node_get(node);
+ pci_irq_host = irq_alloc_host(IRQ_HOST_MAP_LEGACY, 0, &pci_irq_host_ops, 0);
+ if (pci_irq_host == NULL) {
+ printk(KERN_ERR "pci_irq_host: failed to allocate irq host !\n");
+ return;
}
init_pci_source();
--
1.4.0
^ permalink raw reply related
* Re: MPC5200 (Board: PM520) I2C Problem
From: Andrey Volkov @ 2006-10-27 12:44 UTC (permalink / raw)
To: Roman Fietze; +Cc: linuxppc-embedded
In-Reply-To: <200610271315.19077.roman.fietze@telemotive.de>
Hi,
Roman Fietze wrote:
> Hello,
>
> On Friday 27 October 2006 09:29, Andrey Volkov wrote:
>
>> Revision of MPC5200? (third string engraved on the MPC)
>> If L25R then check this doco:
>> http://www.freescale.com/files/32bit/doc/errata/MPC5200E.pdf
>> (if be short - I2C didn't work on this revision chips)
>
> We have an "MPC5200CBV400 L25R Rev 2" on our boards, and we
> successfully drive a PCF8563 real time clock and an UDA1380 Codec on
> the same line.
>
> The problems described in the errata are an arbitration loss problem
> and, depending on teh chp's Rev, a clock noise problem.
>
> Probably your problem is related to the connected I2C client?
Problem was not in noise. Chips of this rev. _sometime_ didn't
generate clock in ACK/NAK phase. Such behavior acceptable for
a RTC (you could reread clock, after timeout), but for eeprom - not.
--
Regards
Andrey
^ permalink raw reply
* Re: [POWERPC] MPC52xx is a 6xx variant, remove PPC_52xx config option
From: Grant Likely @ 2006-10-27 13:21 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-embedded
In-Reply-To: <1161944693.25682.70.camel@localhost.localdomain>
On 10/27/06, Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> On Fri, 2006-10-27 at 13:56 +0400, Andrey Volkov wrote:
> > Please _don't_ do it, since mpc5200 platform drivers depend from this
> > option.
>
> And that should be fixed. We are yet discussing the proper way of
> integrating 52xx in arch/powerpc, but that definitely doesn't involve
> making it an exclusive processor type. Besides, there will probably be
> enough changes in the drivers to adapt them to of_platform_device type
> probing that we might just well fork them all anyway.
Besides; this is only arch/powerpc. 52xx doesn't event boot on
arch/powerpc yet.
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH 2/3] Create compat_sys_migrate_pages
From: Christoph Lameter @ 2006-10-27 13:24 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linux-mm, ppc-dev, paulus, LKML, ak
In-Reply-To: <20061027102834.5db261af.sfr@canb.auug.org.au>
On Fri, 27 Oct 2006, Stephen Rothwell wrote:
> No they aren't because they have compat routines that convert the bitmaps
> before calling the "normal" syscall. They, importantly, only use
> compat_alloc_user_space once each.
Ah...
> > Fixing get_nodes() to do the proper thing would fix all of these
> > without having to touch sys_migrate_pages or creating a compat_ function
> > (which usually is placed in kernel/compat.c)
>
> You need the compat_ version of the syscalls to know if you were called
> from a 32bit application in order to know if you may need to fixup the
> bitmaps that are passed from/to user mode.
The compat functions should be placed in kernel/compat.c next to
compat_sys_move_pages.
^ permalink raw reply
* initial success with uartlite w/interrupt and 2.6.18.1
From: robert corley @ 2006-10-27 13:38 UTC (permalink / raw)
To: David Bolcsfoldi; +Cc: linux linuxppc-embedded
DB;=0A=0AI moved the declaration to outside the loop and now the uartlite d=
river sends and receives=0Adata. See below for details (as if it needs exp=
laining, right? :-))=0A=0AFYI, the RS232 irq line stays high (it's level-t=
riggered for RX data) for 9usec, although I=0Asuspect that isn't the irq se=
rvice time as it probably drops as soon as the RX fifo is read.=0AStill, it=
's good to know that it takes that long from irq start to reading a byte.=
=0A=0AI still don't know why I could not get it to properly function in 2.6=
.17, although I was close =0Awith the latest patch you gave me.=0A=0ANow on=
to the temac...=0A=0A-cy=0A=0A---------------- code follows -------------=
---------=0A=0Astatic irqreturn_t ulite_isr(int irq, void *dev_id, struct p=
t_regs *regs)=0A{=0A struct uart_port *port =3D (struct uart_port *)=
dev_id;=0A int busy;=0A int stat;=0A=0A spin_lock(&por=
t->lock); /* Lock the port in case of printk */=0A=0A do {=0A =
stat =3D readb((unsigned volatile *) (port->membase + ULITE_STATUS=
_BYTE));=0A busy =3D ulite_receive(port, stat);=0A =
busy |=3D ulite_transmit(port, stat);=0A } while (busy);=0A=
=0A spin_unlock(&port->lock);=0A=0A tty_flip_buffer_push(port=
->info->tty);=0A=0A return IRQ_HANDLED;=0A}=0A=0A=0A=0A
^ permalink raw reply
* Re: Building new FEC code on 8xx with 2.6.17 kernel
From: Vitaly Bordug @ 2006-10-27 13:38 UTC (permalink / raw)
To: robin.gilks; +Cc: ppc embedded list
In-Reply-To: <454163B2.4010308@tait.co.nz>
On Fri, 27 Oct 2006 14:41:06 +1300
Robin Gilks <robin.gilks@tait.co.nz> wrote:
> Greetings
>
> Just having a first stab at building for an 859T based product so I
> assume I'll be using the new FEC driver. I'm getting two unresolved
> references as follows:
>
> drivers/built-in.o: In function
> `fec_8xx_init':fec_main.c:(.init.text+0x1a40): undefined reference to
> `fec_8xx_platform_init'
> drivers/built-in.o: In function
> `fec_8xx_cleanup':fec_main.c:(.exit.text+0x39c): undefined reference to
> `fec_8xx_platform_cleanup'
>
> No big deal as I can see an example for the netta platform (whatever
> that is) that defines these functions and I can hack that to suit my
> hardware - what I can't find is where CONFIG_NETTA is defined. I can't
> find it in any Kconfig file, and I want to use the same mechanism for
> selecting my platform.
>
> Any ideas? (or is FEC still broken on CPM1 processors)
>
Please use fs_enet driver (drivers/fs_enet). You can find the reference for platform code at
say arch/ppc/platforms/mpc885_setup.c
--
Sincerely,
Vitaly
^ permalink raw reply
* Re: [PATCH] Powerpc: Make pci_read_irq_line the default: on mpc7448hpc2 board
From: Zang Roy-r61911 @ 2006-10-27 14:51 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev list, Alexandre.Bounine@tundra.com
In-Reply-To: <1161949906.25263.19.camel@localhost.localdomain>
On Fri, 2006-10-27 at 19:51, Zang Roy-r61911 wrote:
> The following patch updates the tsi108/9 pci interrupt controller code
> on mpc7448hpc2 board.
>
> The patch should apply after Ben's patch
> http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027287.html
>
> Of course, the mpc7448hpc2 part in that patch should be replaced by this
> one :-).
>
Missed the following line :-)
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
> arch/powerpc/boot/dts/mpc7448hpc2.dts | 44 ++++++----
> arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c | 96 +++++----------------
> arch/powerpc/sysdev/tsi108_pci.c | 63 ++++++++++++--
> 3 files changed, 108 insertions(+), 95 deletions(-)
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Nicolas DET @ 2006-10-27 14:52 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <1161919709.25682.61.camel@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 771 bytes --]
Benjamin Herrenschmidt wrote:
> On Thu, 2006-10-26 at 14:00 -0600, Grant Likely wrote:
>> My comments are satisfied
>>
>> Acked-by: Grant Likely <grant.likely@secretlab.ca>
>
> Nack.
>
> The irq code doesn't properly use the genirq infrastructure. It's not
> setting flow handlers, not implementing set_irq_type, not using the new
> mask/unmask instead of the toplevel enable/disable...
>
>
Done.
We agree on IRC last night to postpone this implementation later on.
However, here it is.
This patch compiles fine when applied to the kernel 2.6.19-rc3. I also
tested gcc 3.3.5 and 4.1.2.
I made some tests and did not found any issue. However, more
testing/stressing/torturing and also with on others platforms is
required to fully validate the driver.
Regards
[-- Attachment #2: chrpmpc52xx_2.6.19-rc3.patch --]
[-- Type: text/plain, Size: 24917 bytes --]
--- a/arch/powerpc/sysdev/Makefile 2006-10-25 19:07:24.000000000 +0200
+++ b/arch/powerpc/sysdev/Makefile 2006-10-27 15:31:41.000000000 +0200
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_PPC_TODC) += todc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_PPC_MPC52xx_PIC) += mpc52xx_pic.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
--- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-27 15:58:29.000000000 +0200
@@ -0,0 +1,414 @@
+/*
+ * arch/powerpc/sysdev/mpc52xx_pic.c
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx
+ * embedded CPU.
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#undef DEBUG
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/hardirq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/mpc52xx.h>
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+static struct irq_host *mpc52xx_irqhost = NULL;
+
+static void mpc52xx_ic_mask(unsigned int virq)
+{
+ u32 val;
+ int irq;
+ int l1irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l1=%d, l2=%d\n", __func__, irq, l1irq, l2irq);
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ if (l2irq != 0)
+ BUG();
+
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << 11);
+ out_be32(&intr->ctrl, val);
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ if ( (l2irq >= 1) && (l2irq <= 3) ) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << (11 - l2irq));
+ out_be32(&intr->ctrl, val);
+ } else {
+ val = in_be32(&intr->main_mask);
+ val |= 1 << (16 - l2irq);
+ out_be32(&intr->main_mask, val);
+ }
+ break;
+
+ case MPC52xx_IRQ_L1_PERP:
+ val = in_be32(&intr->per_mask);
+ val |= 1 << (31 - l2irq);
+ out_be32(&intr->per_mask, val);
+ break;
+
+ case MPC52xx_IRQ_L1_SDMA:
+ val = in_be32(&sdma->IntMask);
+ val |= 1 << l2irq;
+ out_be32(&sdma->IntMask, val);
+ break;
+
+ default:
+ printk(KERN_ERR "MPC52xx PIC: Wrong interrupt\n");
+ }
+}
+
+static void mpc52xx_ic_unmask(unsigned int virq)
+{
+ u32 val;
+ int irq;
+ int l1irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l1=%d, l2=%d\n", __func__, irq, l1irq, l2irq);
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ if (l2irq != 0)
+ BUG();
+
+ val = in_be32(&intr->ctrl);
+ val |= 1 << 11;
+ out_be32(&intr->ctrl, val);
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ if ( (l2irq >= 1) && (l2irq <= 3) ) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << (11 - l2irq);
+ out_be32(&intr->ctrl, val);
+ } else {
+ val = in_be32(&intr->main_mask);
+ val &= ~(1 << (16 - l2irq));
+ out_be32(&intr->main_mask, val);
+ }
+ break;
+
+ case MPC52xx_IRQ_L1_PERP:
+ val = in_be32(&intr->per_mask);
+ val &= ~(1 << (31 - l2irq));
+ out_be32(&intr->per_mask, val);
+ break;
+
+ case MPC52xx_IRQ_L1_SDMA:
+ val = in_be32(&sdma->IntMask);
+ val &= ~(1 << l2irq);
+ out_be32(&sdma->IntMask, val);
+ break;
+
+ default:
+ printk(KERN_ERR "MPC52xx PIC: Wrong interrupt\n");
+ }
+}
+
+static void mpc52xx_ic_ack(unsigned int virq)
+{
+ u32 val;
+ int irq;
+ int l1irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l1=%d, l2=%d\n", __func__, irq, l1irq, l2irq);
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ if (l2irq != 0)
+ BUG();
+
+ val = in_be32(&intr->ctrl);
+ val |= 0x08000000;
+ out_be32(&intr->ctrl, val);
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ if ( (l2irq >= 1) && (l2irq <= 3) ) {
+ val = in_be32(&intr->ctrl);
+ val |= 0x08000000 >> l2irq;
+ out_be32(&intr->ctrl, val);
+ }
+ break;
+
+ case MPC52xx_IRQ_L1_PERP:
+ val = in_be32(&intr->per_mask);
+ val &= ~(1 << (31 - l2irq));
+ out_be32(&intr->per_mask, val);
+ break;
+
+ case MPC52xx_IRQ_L1_SDMA:
+ out_be32(&sdma->IntPend, 1 << l2irq);
+ break;
+
+ default:
+ printk(KERN_ERR "MPC52xx PIC: Wrong interrupt\n");
+ }
+}
+
+static void mpc52xx_ic_mask_and_ack(unsigned int irq)
+{
+ mpc52xx_ic_mask(irq);
+ mpc52xx_ic_ack(irq);
+}
+
+static struct irq_chip mpc52xx_irqchip = {
+ .typename = " MPC52xx ",
+ .mask = mpc52xx_ic_mask,
+ .unmask = mpc52xx_ic_unmask,
+ .mask_ack = mpc52xx_ic_mask_and_ack,
+};
+
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
+{
+ pr_debug("%s: %p vs %p\n", __func__, find_mpc52xx_picnode(), node);
+ return find_mpc52xx_picnode() == node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
+ u32 * intspec, unsigned int intsize,
+ irq_hw_number_t * out_hwirq,
+ unsigned int *out_flags)
+{
+ static unsigned char map_senses[4] = {
+ IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_EDGE_FALLING,
+ IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_LEVEL_LOW,
+ };
+
+ int intrvect_l1;
+ int intrvect_l2;
+ int intrvect_type;
+ int intrvect_linux;
+
+ if (intsize != 3)
+ return -1;
+
+ intrvect_l1 = (int)intspec[0];
+ intrvect_l2 = (int)intspec[1];
+ intrvect_type = (int)intspec[2];
+
+ pr_debug("l1=%d, l2=%d, type=%d\n", intrvect_l1, intrvect_l2,
+ intrvect_type);
+
+ intrvect_linux =
+ (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;
+ intrvect_linux |=
+ (intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;
+
+ pr_debug("return %x\n", intrvect_linux);
+
+ *out_hwirq = intrvect_linux;
+ *out_flags = map_senses[intrvect_type];
+
+ return 0;
+
+}
+
+static int mpc52xx_islevel(int num)
+{
+ u32 ictl_req;
+ int ictl_type;
+
+ ictl_req = in_be32(&intr->ctrl);
+ ictl_type = (ictl_req >> 16) & 0x3;
+
+ switch (ictl_type) {
+ case 0:
+ case 3:
+ return 1;
+ }
+
+ return 0;
+}
+
+static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t irq)
+{
+ int l1irq;
+ int l2irq;
+ unsigned int status;
+
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ status = get_irq_desc(virq)->status;
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ if (l2irq != 0)
+ BUG();
+ if (mpc52xx_islevel(0))
+ status |= IRQ_LEVEL;
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ if (mpc52xx_islevel(l2irq))
+ status |= IRQ_LEVEL;
+ break;
+
+ default:
+ status |= IRQ_LEVEL;
+ }
+
+ get_irq_desc(virq)->status = status;
+ set_irq_chip_and_handler(virq, &mpc52xx_irqchip,
+ (status & IRQ_LEVEL) ? handle_level_irq :
+ handle_edge_irq);
+
+ pr_debug("%s: virq=%x, hw=%x. desc status=%x\n", __func__, virq,
+ (int)irq, status);
+
+ return 0;
+}
+
+void mpc52xx_irqhost_unmap(struct irq_host *h, unsigned int virq)
+{
+ pr_debug("%s: v=%x\n", __func__, virq);
+
+ mpc52xx_ic_mask(virq);
+ set_irq_chip_and_handler(virq, NULL, NULL);
+ synchronize_irq(virq);
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops = {
+ .match = mpc52xx_irqhost_match,
+ .xlate = mpc52xx_irqhost_xlate,
+ .map = mpc52xx_irqhost_map,
+ .unmap = mpc52xx_irqhost_unmap,
+};
+
+void __init mpc52xx_init_irq(void)
+{
+ int i;
+ u32 intr_ctrl;
+
+ /* Remap the necessary zones */
+ intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
+ sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE);
+
+ if ((intr == NULL) || (sdma == NULL))
+ panic("Can't ioremap PIC/SDMA register or init_irq !");
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+ /* Initialize irq_desc[i].handler's with mpc52xx_ic. */
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc[i].chip = &mpc52xx_irqchip;
+ irq_desc[i].status = IRQ_LEVEL;
+
+ }
+
+ /*
+ * As last step, add an irq host to translate the real
+ * hw irq information provided by the ofw to linux virq
+ */
+
+ mpc52xx_irqhost =
+ irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_IRQS, &mpc52xx_irqhost_ops,
+ -1);
+}
+
+unsigned int mpc52xx_get_irq(void)
+{
+ u32 status;
+ int irq = NO_IRQ_IGNORE;
+
+ status = in_be32(&intr->enc_status);
+ if (status & 0x00000400) { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq |=
+ (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x00200000) { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq |=
+ (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x20000000) { /* peripheral */
+ peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) - 1;
+ irq |=
+ (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else
+ irq |=
+ (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+
+ }
+
+ pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
+ irq_linear_revmap(mpc52xx_irqhost, irq));
+
+ return irq_linear_revmap(mpc52xx_irqhost, irq);
+}
--- a/arch/powerpc/Kconfig 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/Kconfig 2006-10-27 15:50:21.000000000 +0200
@@ -384,6 +384,11 @@ config PPC_CHRP
select PPC_RTAS
select PPC_MPC106
select PPC_UDBG_16550
+ select PPC_MPC52xx_PIC
+ default y
+
+config PPC_MPC52xx_PIC
+ bool
default y
config PPC_PMAC
--- a/arch/powerpc/platforms/chrp/setup.c 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/platforms/chrp/setup.c 2006-10-27 16:08:03.000000000 +0200
@@ -51,6 +51,7 @@
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/xmon.h>
+#include <asm/mpc52xx.h>
#include "chrp.h"
@@ -435,6 +436,18 @@ static struct irqaction xmon_irqaction =
};
#endif
+static int __init chrp_find_mpc52xx_pic(void)
+{
+ if (find_mpc52xx_picnode()) {
+ printk(KERN_INFO "Found MPC52xx Interrupt Controller\n");
+ ppc_md.get_irq = mpc52xx_get_irq;
+ mpc52xx_init_irq();
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
static void __init chrp_find_8259(void)
{
struct device_node *np, *pic = NULL;
@@ -496,6 +509,7 @@ void __init chrp_init_IRQ(void)
#endif
chrp_find_openpic();
chrp_find_8259();
+ chrp_find_mpc52xx_pic();
#ifdef CONFIG_SMP
/* Pegasos has no MPIC, those ops would make it crash. It might be an
diff -uprN a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
--- a/include/asm-powerpc/mpc52xx.h 1970-01-01 01:00:00.000000000 +0100
+++ b/include/asm-powerpc/mpc52xx.h 2006-10-27 15:51:55.000000000 +0200
@@ -0,0 +1,414 @@
+/*
+ * include/asm-ppc/mpc52xx.h
+ *
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Originally written by Dale Farnsworth <dfarnsworth@mvista.com>
+ * for the 2.4 kernel.
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_POWERPC_MPC52xx_H__
+#define __ASM_POWERPC_MPC52xx_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/prom.h>
+
+#endif /* __ASSEMBLY__ */
+
+
+#ifdef CONFIG_PCI
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define _IO_BASE 0
+#define _ISA_MEM_BASE 0
+#define PCI_DRAM_OFFSET 0
+#endif
+
+
+/* ======================================================================== */
+/* PPC Sys devices definition */
+/* ======================================================================== */
+
+enum ppc_sys_devices {
+ MPC52xx_MSCAN1,
+ MPC52xx_MSCAN2,
+ MPC52xx_SPI,
+ MPC52xx_USB,
+ MPC52xx_BDLC,
+ MPC52xx_PSC1,
+ MPC52xx_PSC2,
+ MPC52xx_PSC3,
+ MPC52xx_PSC4,
+ MPC52xx_PSC5,
+ MPC52xx_PSC6,
+ MPC52xx_FEC,
+ MPC52xx_ATA,
+ MPC52xx_I2C1,
+ MPC52xx_I2C2,
+ NUM_PPC_SYS_DEVS,
+};
+
+
+/* ======================================================================== */
+/* Main registers/struct addresses */
+/* ======================================================================== */
+
+/* MBAR position */
+#define MPC52xx_MBAR 0xf0000000 /* Phys address */
+#define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */
+#define MPC52xx_MBAR_SIZE 0x00010000
+
+#define MPC52xx_PA(x) ((phys_addr_t)(MPC52xx_MBAR + (x)))
+#define MPC52xx_VA(x) ((void __iomem *)(MPC52xx_MBAR_VIRT + (x)))
+
+/* Registers zone offset/size */
+#define MPC52xx_MMAP_CTL_OFFSET 0x0000
+#define MPC52xx_MMAP_CTL_SIZE 0x068
+#define MPC52xx_SDRAM_OFFSET 0x0100
+#define MPC52xx_SDRAM_SIZE 0x010
+#define MPC52xx_CDM_OFFSET 0x0200
+#define MPC52xx_CDM_SIZE 0x038
+#define MPC52xx_INTR_OFFSET 0x0500
+#define MPC52xx_INTR_SIZE 0x04c
+#define MPC52xx_GPTx_OFFSET(x) (0x0600 + ((x)<<4))
+#define MPC52xx_GPT_SIZE 0x010
+#define MPC52xx_RTC_OFFSET 0x0800
+#define MPC52xx_RTC_SIZE 0x024
+#define MPC52xx_GPIO_OFFSET 0x0b00
+#define MPC52xx_GPIO_SIZE 0x040
+#define MPC52xx_GPIO_WKUP_OFFSET 0x0c00
+#define MPC52xx_GPIO_WKUP_SIZE 0x028
+#define MPC52xx_PCI_OFFSET 0x0d00
+#define MPC52xx_PCI_SIZE 0x100
+#define MPC52xx_SDMA_OFFSET 0x1200
+#define MPC52xx_SDMA_SIZE 0x100
+#define MPC52xx_XLB_OFFSET 0x1f00
+#define MPC52xx_XLB_SIZE 0x100
+#define MPC52xx_PSCx_OFFSET(x) (((x)!=6)?(0x1e00+((x)<<9)):0x2c00)
+#define MPC52xx_PSC_SIZE 0x0a0
+
+/* SRAM used for SDMA */
+#define MPC52xx_SRAM_OFFSET 0x8000
+#define MPC52xx_SRAM_SIZE 0x4000
+
+
+/* ======================================================================== */
+/* IRQ mapping */
+/* ======================================================================== */
+
+#define MPC52xx_IRQ_L1_CRIT 0
+#define MPC52xx_IRQ_L1_MAIN 1
+#define MPC52xx_IRQ_L1_PERP 2
+#define MPC52xx_IRQ_L1_SDMA 3
+
+#define MPC52xx_IRQ_L1_OFFSET (6)
+#define MPC52xx_IRQ_L1_MASK (0xc0)
+
+#define MPC52xx_IRQ_L2_OFFSET (0)
+#define MPC52xx_IRQ_L2_MASK (0x3f)
+
+
+/* ======================================================================== */
+/* Structures mapping of some unit register set */
+/* ======================================================================== */
+
+#ifndef __ASSEMBLY__
+
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+ u32 mbar; /* MMAP_CTRL + 0x00 */
+
+ u32 cs0_start; /* MMAP_CTRL + 0x04 */
+ u32 cs0_stop; /* MMAP_CTRL + 0x08 */
+ u32 cs1_start; /* MMAP_CTRL + 0x0c */
+ u32 cs1_stop; /* MMAP_CTRL + 0x10 */
+ u32 cs2_start; /* MMAP_CTRL + 0x14 */
+ u32 cs2_stop; /* MMAP_CTRL + 0x18 */
+ u32 cs3_start; /* MMAP_CTRL + 0x1c */
+ u32 cs3_stop; /* MMAP_CTRL + 0x20 */
+ u32 cs4_start; /* MMAP_CTRL + 0x24 */
+ u32 cs4_stop; /* MMAP_CTRL + 0x28 */
+ u32 cs5_start; /* MMAP_CTRL + 0x2c */
+ u32 cs5_stop; /* MMAP_CTRL + 0x30 */
+
+ u32 sdram0; /* MMAP_CTRL + 0x34 */
+ u32 sdram1; /* MMAP_CTRL + 0X38 */
+
+ u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
+
+ u32 boot_start; /* MMAP_CTRL + 0x4c */
+ u32 boot_stop; /* MMAP_CTRL + 0x50 */
+
+ u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
+
+ u32 cs6_start; /* MMAP_CTRL + 0x58 */
+ u32 cs6_stop; /* MMAP_CTRL + 0x5c */
+ u32 cs7_start; /* MMAP_CTRL + 0x60 */
+ u32 cs7_stop; /* MMAP_CTRL + 0x64 */
+};
+
+/* SDRAM control */
+struct mpc52xx_sdram {
+ u32 mode; /* SDRAM + 0x00 */
+ u32 ctrl; /* SDRAM + 0x04 */
+ u32 config1; /* SDRAM + 0x08 */
+ u32 config2; /* SDRAM + 0x0c */
+};
+
+/* Interrupt controller */
+struct mpc52xx_intr {
+ u32 per_mask; /* INTR + 0x00 */
+ u32 per_pri1; /* INTR + 0x04 */
+ u32 per_pri2; /* INTR + 0x08 */
+ u32 per_pri3; /* INTR + 0x0c */
+ u32 ctrl; /* INTR + 0x10 */
+ u32 main_mask; /* INTR + 0x14 */
+ u32 main_pri1; /* INTR + 0x18 */
+ u32 main_pri2; /* INTR + 0x1c */
+ u32 reserved1; /* INTR + 0x20 */
+ u32 enc_status; /* INTR + 0x24 */
+ u32 crit_status; /* INTR + 0x28 */
+ u32 main_status; /* INTR + 0x2c */
+ u32 per_status; /* INTR + 0x30 */
+ u32 reserved2; /* INTR + 0x34 */
+ u32 per_error; /* INTR + 0x38 */
+};
+
+/* SDMA */
+struct mpc52xx_sdma {
+ u32 taskBar; /* SDMA + 0x00 */
+ u32 currentPointer; /* SDMA + 0x04 */
+ u32 endPointer; /* SDMA + 0x08 */
+ u32 variablePointer;/* SDMA + 0x0c */
+
+ u8 IntVect1; /* SDMA + 0x10 */
+ u8 IntVect2; /* SDMA + 0x11 */
+ u16 PtdCntrl; /* SDMA + 0x12 */
+
+ u32 IntPend; /* SDMA + 0x14 */
+ u32 IntMask; /* SDMA + 0x18 */
+
+ u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
+
+ u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
+
+ u32 cReqSelect; /* SDMA + 0x5c */
+ u32 task_size0; /* SDMA + 0x60 */
+ u32 task_size1; /* SDMA + 0x64 */
+ u32 MDEDebug; /* SDMA + 0x68 */
+ u32 ADSDebug; /* SDMA + 0x6c */
+ u32 Value1; /* SDMA + 0x70 */
+ u32 Value2; /* SDMA + 0x74 */
+ u32 Control; /* SDMA + 0x78 */
+ u32 Status; /* SDMA + 0x7c */
+ u32 PTDDebug; /* SDMA + 0x80 */
+};
+
+/* GPT */
+struct mpc52xx_gpt {
+ u32 mode; /* GPTx + 0x00 */
+ u32 count; /* GPTx + 0x04 */
+ u32 pwm; /* GPTx + 0x08 */
+ u32 status; /* GPTx + 0X0c */
+};
+
+/* RTC */
+struct mpc52xx_rtc {
+ u32 time_set; /* RTC + 0x00 */
+ u32 date_set; /* RTC + 0x04 */
+ u32 stopwatch; /* RTC + 0x08 */
+ u32 int_enable; /* RTC + 0x0c */
+ u32 time; /* RTC + 0x10 */
+ u32 date; /* RTC + 0x14 */
+ u32 stopwatch_intr; /* RTC + 0x18 */
+ u32 bus_error; /* RTC + 0x1c */
+ u32 dividers; /* RTC + 0x20 */
+};
+
+/* GPIO */
+struct mpc52xx_gpio {
+ u32 port_config; /* GPIO + 0x00 */
+ u32 simple_gpioe; /* GPIO + 0x04 */
+ u32 simple_ode; /* GPIO + 0x08 */
+ u32 simple_ddr; /* GPIO + 0x0c */
+ u32 simple_dvo; /* GPIO + 0x10 */
+ u32 simple_ival; /* GPIO + 0x14 */
+ u8 outo_gpioe; /* GPIO + 0x18 */
+ u8 reserved1[3]; /* GPIO + 0x19 */
+ u8 outo_dvo; /* GPIO + 0x1c */
+ u8 reserved2[3]; /* GPIO + 0x1d */
+ u8 sint_gpioe; /* GPIO + 0x20 */
+ u8 reserved3[3]; /* GPIO + 0x21 */
+ u8 sint_ode; /* GPIO + 0x24 */
+ u8 reserved4[3]; /* GPIO + 0x25 */
+ u8 sint_ddr; /* GPIO + 0x28 */
+ u8 reserved5[3]; /* GPIO + 0x29 */
+ u8 sint_dvo; /* GPIO + 0x2c */
+ u8 reserved6[3]; /* GPIO + 0x2d */
+ u8 sint_inten; /* GPIO + 0x30 */
+ u8 reserved7[3]; /* GPIO + 0x31 */
+ u16 sint_itype; /* GPIO + 0x34 */
+ u16 reserved8; /* GPIO + 0x36 */
+ u8 gpio_control; /* GPIO + 0x38 */
+ u8 reserved9[3]; /* GPIO + 0x39 */
+ u8 sint_istat; /* GPIO + 0x3c */
+ u8 sint_ival; /* GPIO + 0x3d */
+ u8 bus_errs; /* GPIO + 0x3e */
+ u8 reserved10; /* GPIO + 0x3f */
+};
+
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
+#define MPC52xx_GPIO_PCI_DIS (1<<15)
+
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+ u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
+ u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
+ u8 wkup_ode; /* GPIO_WKUP + 0x04 */
+ u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
+ u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
+ u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
+ u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
+ u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
+ u8 wkup_inten; /* GPIO_WKUP + 0x10 */
+ u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
+ u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
+ u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
+ u16 wkup_itype; /* GPIO_WKUP + 0x18 */
+ u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
+ u8 wkup_maste; /* GPIO_WKUP + 0x1C */
+ u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
+ u8 wkup_ival; /* GPIO_WKUP + 0x20 */
+ u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
+ u8 wkup_istat; /* GPIO_WKUP + 0x24 */
+ u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
+};
+
+/* XLB Bus control */
+struct mpc52xx_xlb {
+ u8 reserved[0x40];
+ u32 config; /* XLB + 0x40 */
+ u32 version; /* XLB + 0x44 */
+ u32 status; /* XLB + 0x48 */
+ u32 int_enable; /* XLB + 0x4c */
+ u32 addr_capture; /* XLB + 0x50 */
+ u32 bus_sig_capture; /* XLB + 0x54 */
+ u32 addr_timeout; /* XLB + 0x58 */
+ u32 data_timeout; /* XLB + 0x5c */
+ u32 bus_act_timeout; /* XLB + 0x60 */
+ u32 master_pri_enable; /* XLB + 0x64 */
+ u32 master_priority; /* XLB + 0x68 */
+ u32 base_address; /* XLB + 0x6c */
+ u32 snoop_window; /* XLB + 0x70 */
+};
+
+#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
+#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
+
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+ u32 jtag_id; /* CDM + 0x00 reg0 read only */
+ u32 rstcfg; /* CDM + 0x04 reg1 read only */
+ u32 breadcrumb; /* CDM + 0x08 reg2 */
+
+ u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
+ u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
+ u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
+ u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
+
+ u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
+ u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
+ u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
+
+ u32 clk_enables; /* CDM + 0x14 reg5 */
+
+ u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
+ u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
+
+ u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
+ u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
+ u8 reserved1; /* CDM + 0x1e reg7 byte2 */
+ u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
+
+ u8 soft_reset; /* CDM + 0x20 u8 byte0 */
+ u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
+ u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
+
+ u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
+ u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
+ u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
+ u8 reserved3; /* CDM + 0x27 reg9 byte3 */
+
+ u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
+ u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
+
+ u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
+ u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
+
+ u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
+ u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
+
+ u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
+ u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+/* ========================================================================= */
+/* Prototypes for MPC52xx syslib */
+/* ========================================================================= */
+
+#ifndef __ASSEMBLY__
+
+extern void mpc52xx_init_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
+
+extern unsigned long mpc52xx_find_end_of_memory(void);
+extern void mpc52xx_set_bat(void);
+extern void mpc52xx_map_io(void);
+extern void mpc52xx_restart(char *cmd);
+extern void mpc52xx_halt(void);
+extern void mpc52xx_power_off(void);
+extern void mpc52xx_progress(char *s, unsigned short hex);
+extern void mpc52xx_calibrate_decr(void);
+
+extern void mpc52xx_find_bridges(void);
+
+extern void mpc52xx_setup_cpu(void);
+
+static inline struct device_node *
+find_mpc52xx_picnode(void)
+{
+ return of_find_compatible_node(NULL, "interrupt-controller", "mpc5200-pic");
+}
+
+ /* Matching of PSC function */
+struct mpc52xx_psc_func {
+ int id;
+ char *func;
+};
+
+extern int mpc52xx_match_psc_function(int psc_idx, const char *func);
+extern struct mpc52xx_psc_func mpc52xx_psc_functions[];
+ /* This array is to be defined in platform file */
+
+#endif /* __ASSEMBLY__ */
+
+
+#endif /* _ASM_POWERPC_MPC52xx_H__ */
[-- Attachment #3: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: [PATCH] Xilinx UART Lite 2.6.18 driver
From: Peter Korsgaard @ 2006-10-27 15:03 UTC (permalink / raw)
To: dbolcsfoldi, linuxppc-embedded
In-Reply-To: <87lknadbbl.fsf@sleipner.barco.com>
>>>>> "Peter" == Peter Korsgaard <jacmet@sunsite.dk> writes:
Peter> I'll test and take a closer look at your patch when I have
Peter> access to hw again on Monday.
Sorry, it got a bit later than promised, but I've now had a closer
look at your patch ..
--- uartlite/arch/ppc/boot/simple/misc.c 2006-10-15 14:09:47.000000000 -0700
+++ uartlite-mod/arch/ppc/boot/simple/misc.c 2006-10-15 13:58:51.000000000 -0700
@@ -48,7 +48,8 @@
#if (defined(CONFIG_SERIAL_8250_CONSOLE) \
|| defined(CONFIG_VGA_CONSOLE) \
|| defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \
- || defined(CONFIG_SERIAL_MPSC_CONSOLE)) \
+ || defined(CONFIG_SERIAL_MPSC_CONSOLE) \
+ || defined(CONFIG_SERIAL_UARTLITE_CONSOLE)) \
&& !defined(CONFIG_GEMINI)
#define INTERACTIVE_CONSOLE 1
#endif
The Xilinx boards use misc-embedded.c not misc.c - Why is this needed?
+unsigned long serial_init(int chan, void *ignored)
+{
+ switch (chan) {
+ #ifdef XPAR_XUL_UART_0_BASEADDR
+ case 0:
+ return XPAR_XUL_UART_0_BASEADDR;
+ #endif
+ #ifdef XPAR_XUL_UART_1_BASEADDR
+ case 1:
+ return XPAR_XUL_UART_1_BASEADDR;
+ #endif
+ #ifdef XPAR_XUL_UART_2_BASEADDR
+ case 2:
+ return XPAR_XUL_UART_2_BASEADDR;
+ #endif
+ #ifdef XPAR_XUL_UART_3_BASEADDR
+ case 3:
+ return XPAR_XUL_UART_3_BASEADDR;
+ #endif
This doesn't help much as you don't use the com_port argument in the
other functions.
Where did you get the XPAR_XUL_UART_ defines from? Our xparameters.h
seem to contain XPAR_UARTLITE_ defines instead.
@@ -131,12 +115,16 @@
struct uart_port *port = (struct uart_port *)dev_id;
int busy;
+ spin_lock(&port->lock); /* Lock the port in case of printk */
+
In an interrupt handler? Why? The console_write does a spin_lock_irqsave.
static int __init ulite_console_setup(struct console *co, char *options)
{
+ int i, ret;
struct uart_port *port;
-
+ struct platform_device *pdev;
+
if (co->index < 0 || co->index >= ULITE_NR_UARTS)
return -EINVAL;
port = &ports[co->index];
/* not initialized yet? */
- if (!port->membase)
- return -ENODEV;
+ if (!port->membase) {
+ /* We might be early console */
Is this really necessary? The platform probe get's called quite early, E.G.:
Breakpoint 2, ulite_probe (pdev=0xc01c84d0) at drivers/serial/uartlite.c:392
392 {
(gdb) print __log_buf
$1 = "<5>Linux version 2.6.19-rc3 (peko@sleipner) (gcc version 3.4.5) #19 Fri Oct 27 16:39:00 CEST 2006\n<6>Barco ThinLite (V2P) <peter.korsgaard@barco.com>\n<7>Entering add_active_range(0, 0, 15360) 0 entrie"...
You can always use the ppc_md.progress() stuff for really early
debugging if needed. I would prefer to keep this workaround out of
uartlite.c if it isn't needed.
--
Bye, Peter Korsgaard
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Nicolas DET @ 2006-10-27 15:04 UTC (permalink / raw)
To: Nicolas DET; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <45421C97.80501@bplan-gmbh.de>
[-- Attachment #1: Type: text/plain, Size: 2074 bytes --]
Nicolas DET wrote:
> Benjamin Herrenschmidt wrote:
>> On Thu, 2006-10-26 at 14:00 -0600, Grant Likely wrote:
>>> My comments are satisfied
>>>
>>> Acked-by: Grant Likely <grant.likely@secretlab.ca>
>>
>> Nack.
>>
>> The irq code doesn't properly use the genirq infrastructure. It's not
>> setting flow handlers, not implementing set_irq_type, not using the new
>> mask/unmask instead of the toplevel enable/disable...
>>
>>
>
> Done.
>
> We agree on IRC last night to postpone this implementation later on.
> However, here it is.
>
> This patch compiles fine when applied to the kernel 2.6.19-rc3. I also
> tested gcc 3.3.5 and 4.1.2.
>
> I made some tests and did not found any issue. However, more
> testing/stressing/torturing and also with on others platforms is
> required to fully validate the driver.
>
>
> /* Pegasos has no MPIC, those ops would make it crash. It might be an
> diff -uprN a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
> --- a/include/asm-powerpc/mpc52xx.h 1970-01-01 01:00:00.000000000 +0100
> +++ b/include/asm-powerpc/mpc52xx.h 2006-10-27 15:51:55.000000000 +0200
> @@ -0,0 +1,414 @@
> +/*
> + * include/asm-ppc/mpc52xx.h
> + *
Fixed to powerpc
> +#endif /* __ASSEMBLY__ */
> +
> +
> +#ifdef CONFIG_PCI
> +#define _IO_BASE isa_io_base
> +#define _ISA_MEM_BASE isa_mem_base
> +#define PCI_DRAM_OFFSET pci_dram_offset
> +#else
> +#define _IO_BASE 0
> +#define _ISA_MEM_BASE 0
> +#define PCI_DRAM_OFFSET 0
> +#endif
> +
> +
> +/* ======================================================================== */
> +/* PPC Sys devices definition */
> +/* ======================================================================== */
> +
> +enum ppc_sys_devices {
> + MPC52xx_MSCAN1,
> + MPC52xx_MSCAN2,
> + MPC52xx_SPI,
> + MPC52xx_USB,
> + MPC52xx_BDLC,
> + MPC52xx_PSC1,
> + MPC52xx_PSC2,
> + MPC52xx_PSC3,
> + MPC52xx_PSC4,
> + MPC52xx_PSC5,
> + MPC52xx_PSC6,
> + MPC52xx_FEC,
> + MPC52xx_ATA,
> + MPC52xx_I2C1,
> + MPC52xx_I2C2,
> + NUM_PPC_SYS_DEVS,
> +};
> +
> +
Removed
[-- Attachment #2: chrpmpc52xx_2.6.19-rc3.patch --]
[-- Type: text/plain, Size: 24385 bytes --]
--- a/arch/powerpc/sysdev/Makefile 2006-10-25 19:07:24.000000000 +0200
+++ b/arch/powerpc/sysdev/Makefile 2006-10-27 15:31:41.000000000 +0200
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_PPC_TODC) += todc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_PPC_MPC52xx_PIC) += mpc52xx_pic.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
--- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-27 15:58:29.000000000 +0200
@@ -0,0 +1,414 @@
+/*
+ * arch/powerpc/sysdev/mpc52xx_pic.c
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx
+ * embedded CPU.
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#undef DEBUG
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/hardirq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/mpc52xx.h>
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+static struct irq_host *mpc52xx_irqhost = NULL;
+
+static void mpc52xx_ic_mask(unsigned int virq)
+{
+ u32 val;
+ int irq;
+ int l1irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l1=%d, l2=%d\n", __func__, irq, l1irq, l2irq);
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ if (l2irq != 0)
+ BUG();
+
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << 11);
+ out_be32(&intr->ctrl, val);
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ if ( (l2irq >= 1) && (l2irq <= 3) ) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << (11 - l2irq));
+ out_be32(&intr->ctrl, val);
+ } else {
+ val = in_be32(&intr->main_mask);
+ val |= 1 << (16 - l2irq);
+ out_be32(&intr->main_mask, val);
+ }
+ break;
+
+ case MPC52xx_IRQ_L1_PERP:
+ val = in_be32(&intr->per_mask);
+ val |= 1 << (31 - l2irq);
+ out_be32(&intr->per_mask, val);
+ break;
+
+ case MPC52xx_IRQ_L1_SDMA:
+ val = in_be32(&sdma->IntMask);
+ val |= 1 << l2irq;
+ out_be32(&sdma->IntMask, val);
+ break;
+
+ default:
+ printk(KERN_ERR "MPC52xx PIC: Wrong interrupt\n");
+ }
+}
+
+static void mpc52xx_ic_unmask(unsigned int virq)
+{
+ u32 val;
+ int irq;
+ int l1irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l1=%d, l2=%d\n", __func__, irq, l1irq, l2irq);
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ if (l2irq != 0)
+ BUG();
+
+ val = in_be32(&intr->ctrl);
+ val |= 1 << 11;
+ out_be32(&intr->ctrl, val);
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ if ( (l2irq >= 1) && (l2irq <= 3) ) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << (11 - l2irq);
+ out_be32(&intr->ctrl, val);
+ } else {
+ val = in_be32(&intr->main_mask);
+ val &= ~(1 << (16 - l2irq));
+ out_be32(&intr->main_mask, val);
+ }
+ break;
+
+ case MPC52xx_IRQ_L1_PERP:
+ val = in_be32(&intr->per_mask);
+ val &= ~(1 << (31 - l2irq));
+ out_be32(&intr->per_mask, val);
+ break;
+
+ case MPC52xx_IRQ_L1_SDMA:
+ val = in_be32(&sdma->IntMask);
+ val &= ~(1 << l2irq);
+ out_be32(&sdma->IntMask, val);
+ break;
+
+ default:
+ printk(KERN_ERR "MPC52xx PIC: Wrong interrupt\n");
+ }
+}
+
+static void mpc52xx_ic_ack(unsigned int virq)
+{
+ u32 val;
+ int irq;
+ int l1irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l1=%d, l2=%d\n", __func__, irq, l1irq, l2irq);
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ if (l2irq != 0)
+ BUG();
+
+ val = in_be32(&intr->ctrl);
+ val |= 0x08000000;
+ out_be32(&intr->ctrl, val);
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ if ( (l2irq >= 1) && (l2irq <= 3) ) {
+ val = in_be32(&intr->ctrl);
+ val |= 0x08000000 >> l2irq;
+ out_be32(&intr->ctrl, val);
+ }
+ break;
+
+ case MPC52xx_IRQ_L1_PERP:
+ val = in_be32(&intr->per_mask);
+ val &= ~(1 << (31 - l2irq));
+ out_be32(&intr->per_mask, val);
+ break;
+
+ case MPC52xx_IRQ_L1_SDMA:
+ out_be32(&sdma->IntPend, 1 << l2irq);
+ break;
+
+ default:
+ printk(KERN_ERR "MPC52xx PIC: Wrong interrupt\n");
+ }
+}
+
+static void mpc52xx_ic_mask_and_ack(unsigned int irq)
+{
+ mpc52xx_ic_mask(irq);
+ mpc52xx_ic_ack(irq);
+}
+
+static struct irq_chip mpc52xx_irqchip = {
+ .typename = " MPC52xx ",
+ .mask = mpc52xx_ic_mask,
+ .unmask = mpc52xx_ic_unmask,
+ .mask_ack = mpc52xx_ic_mask_and_ack,
+};
+
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
+{
+ pr_debug("%s: %p vs %p\n", __func__, find_mpc52xx_picnode(), node);
+ return find_mpc52xx_picnode() == node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
+ u32 * intspec, unsigned int intsize,
+ irq_hw_number_t * out_hwirq,
+ unsigned int *out_flags)
+{
+ static unsigned char map_senses[4] = {
+ IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_EDGE_FALLING,
+ IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_LEVEL_LOW,
+ };
+
+ int intrvect_l1;
+ int intrvect_l2;
+ int intrvect_type;
+ int intrvect_linux;
+
+ if (intsize != 3)
+ return -1;
+
+ intrvect_l1 = (int)intspec[0];
+ intrvect_l2 = (int)intspec[1];
+ intrvect_type = (int)intspec[2];
+
+ pr_debug("l1=%d, l2=%d, type=%d\n", intrvect_l1, intrvect_l2,
+ intrvect_type);
+
+ intrvect_linux =
+ (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;
+ intrvect_linux |=
+ (intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;
+
+ pr_debug("return %x\n", intrvect_linux);
+
+ *out_hwirq = intrvect_linux;
+ *out_flags = map_senses[intrvect_type];
+
+ return 0;
+
+}
+
+static int mpc52xx_islevel(int num)
+{
+ u32 ictl_req;
+ int ictl_type;
+
+ ictl_req = in_be32(&intr->ctrl);
+ ictl_type = (ictl_req >> 16) & 0x3;
+
+ switch (ictl_type) {
+ case 0:
+ case 3:
+ return 1;
+ }
+
+ return 0;
+}
+
+static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t irq)
+{
+ int l1irq;
+ int l2irq;
+ unsigned int status;
+
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ status = get_irq_desc(virq)->status;
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ if (l2irq != 0)
+ BUG();
+ if (mpc52xx_islevel(0))
+ status |= IRQ_LEVEL;
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ if (mpc52xx_islevel(l2irq))
+ status |= IRQ_LEVEL;
+ break;
+
+ default:
+ status |= IRQ_LEVEL;
+ }
+
+ get_irq_desc(virq)->status = status;
+ set_irq_chip_and_handler(virq, &mpc52xx_irqchip,
+ (status & IRQ_LEVEL) ? handle_level_irq :
+ handle_edge_irq);
+
+ pr_debug("%s: virq=%x, hw=%x. desc status=%x\n", __func__, virq,
+ (int)irq, status);
+
+ return 0;
+}
+
+void mpc52xx_irqhost_unmap(struct irq_host *h, unsigned int virq)
+{
+ pr_debug("%s: v=%x\n", __func__, virq);
+
+ mpc52xx_ic_mask(virq);
+ set_irq_chip_and_handler(virq, NULL, NULL);
+ synchronize_irq(virq);
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops = {
+ .match = mpc52xx_irqhost_match,
+ .xlate = mpc52xx_irqhost_xlate,
+ .map = mpc52xx_irqhost_map,
+ .unmap = mpc52xx_irqhost_unmap,
+};
+
+void __init mpc52xx_init_irq(void)
+{
+ int i;
+ u32 intr_ctrl;
+
+ /* Remap the necessary zones */
+ intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
+ sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE);
+
+ if ((intr == NULL) || (sdma == NULL))
+ panic("Can't ioremap PIC/SDMA register or init_irq !");
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+ /* Initialize irq_desc[i].handler's with mpc52xx_ic. */
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc[i].chip = &mpc52xx_irqchip;
+ irq_desc[i].status = IRQ_LEVEL;
+
+ }
+
+ /*
+ * As last step, add an irq host to translate the real
+ * hw irq information provided by the ofw to linux virq
+ */
+
+ mpc52xx_irqhost =
+ irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_IRQS, &mpc52xx_irqhost_ops,
+ -1);
+}
+
+unsigned int mpc52xx_get_irq(void)
+{
+ u32 status;
+ int irq = NO_IRQ_IGNORE;
+
+ status = in_be32(&intr->enc_status);
+ if (status & 0x00000400) { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq |=
+ (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x00200000) { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq |=
+ (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x20000000) { /* peripheral */
+ peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) - 1;
+ irq |=
+ (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else
+ irq |=
+ (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+
+ }
+
+ pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
+ irq_linear_revmap(mpc52xx_irqhost, irq));
+
+ return irq_linear_revmap(mpc52xx_irqhost, irq);
+}
--- a/arch/powerpc/Kconfig 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/Kconfig 2006-10-27 15:50:21.000000000 +0200
@@ -384,6 +384,11 @@ config PPC_CHRP
select PPC_RTAS
select PPC_MPC106
select PPC_UDBG_16550
+ select PPC_MPC52xx_PIC
+ default y
+
+config PPC_MPC52xx_PIC
+ bool
default y
config PPC_PMAC
--- a/arch/powerpc/platforms/chrp/setup.c 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/platforms/chrp/setup.c 2006-10-27 16:08:03.000000000 +0200
@@ -51,6 +51,7 @@
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/xmon.h>
+#include <asm/mpc52xx.h>
#include "chrp.h"
@@ -435,6 +436,18 @@ static struct irqaction xmon_irqaction =
};
#endif
+static int __init chrp_find_mpc52xx_pic(void)
+{
+ if (find_mpc52xx_picnode()) {
+ printk(KERN_INFO "Found MPC52xx Interrupt Controller\n");
+ ppc_md.get_irq = mpc52xx_get_irq;
+ mpc52xx_init_irq();
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
static void __init chrp_find_8259(void)
{
struct device_node *np, *pic = NULL;
@@ -496,6 +509,7 @@ void __init chrp_init_IRQ(void)
#endif
chrp_find_openpic();
chrp_find_8259();
+ chrp_find_mpc52xx_pic();
#ifdef CONFIG_SMP
/* Pegasos has no MPIC, those ops would make it crash. It might be an
diff -uprN a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
--- a/include/asm-powerpc/mpc52xx.h 1970-01-01 01:00:00.000000000 +0100
+++ b/include/asm-powerpc/mpc52xx.h 2006-10-27 15:51:55.000000000 +0200
@@ -0,0 +1,414 @@
+/*
+ * include/asm-powerpc/mpc52xx.h
+ *
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Originally written by Dale Farnsworth <dfarnsworth@mvista.com>
+ * for the 2.4 kernel.
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_POWERPC_MPC52xx_H__
+#define __ASM_POWERPC_MPC52xx_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/prom.h>
+
+#endif /* __ASSEMBLY__ */
+
+
+#ifdef CONFIG_PCI
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define _IO_BASE 0
+#define _ISA_MEM_BASE 0
+#define PCI_DRAM_OFFSET 0
+#endif
+
+/* ======================================================================== */
+/* Main registers/struct addresses */
+/* ======================================================================== */
+
+/* MBAR position */
+#define MPC52xx_MBAR 0xf0000000 /* Phys address */
+#define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */
+#define MPC52xx_MBAR_SIZE 0x00010000
+
+#define MPC52xx_PA(x) ((phys_addr_t)(MPC52xx_MBAR + (x)))
+#define MPC52xx_VA(x) ((void __iomem *)(MPC52xx_MBAR_VIRT + (x)))
+
+/* Registers zone offset/size */
+#define MPC52xx_MMAP_CTL_OFFSET 0x0000
+#define MPC52xx_MMAP_CTL_SIZE 0x068
+#define MPC52xx_SDRAM_OFFSET 0x0100
+#define MPC52xx_SDRAM_SIZE 0x010
+#define MPC52xx_CDM_OFFSET 0x0200
+#define MPC52xx_CDM_SIZE 0x038
+#define MPC52xx_INTR_OFFSET 0x0500
+#define MPC52xx_INTR_SIZE 0x04c
+#define MPC52xx_GPTx_OFFSET(x) (0x0600 + ((x)<<4))
+#define MPC52xx_GPT_SIZE 0x010
+#define MPC52xx_RTC_OFFSET 0x0800
+#define MPC52xx_RTC_SIZE 0x024
+#define MPC52xx_GPIO_OFFSET 0x0b00
+#define MPC52xx_GPIO_SIZE 0x040
+#define MPC52xx_GPIO_WKUP_OFFSET 0x0c00
+#define MPC52xx_GPIO_WKUP_SIZE 0x028
+#define MPC52xx_PCI_OFFSET 0x0d00
+#define MPC52xx_PCI_SIZE 0x100
+#define MPC52xx_SDMA_OFFSET 0x1200
+#define MPC52xx_SDMA_SIZE 0x100
+#define MPC52xx_XLB_OFFSET 0x1f00
+#define MPC52xx_XLB_SIZE 0x100
+#define MPC52xx_PSCx_OFFSET(x) (((x)!=6)?(0x1e00+((x)<<9)):0x2c00)
+#define MPC52xx_PSC_SIZE 0x0a0
+
+/* SRAM used for SDMA */
+#define MPC52xx_SRAM_OFFSET 0x8000
+#define MPC52xx_SRAM_SIZE 0x4000
+
+
+/* ======================================================================== */
+/* IRQ mapping */
+/* ======================================================================== */
+
+#define MPC52xx_IRQ_L1_CRIT 0
+#define MPC52xx_IRQ_L1_MAIN 1
+#define MPC52xx_IRQ_L1_PERP 2
+#define MPC52xx_IRQ_L1_SDMA 3
+
+#define MPC52xx_IRQ_L1_OFFSET (6)
+#define MPC52xx_IRQ_L1_MASK (0xc0)
+
+#define MPC52xx_IRQ_L2_OFFSET (0)
+#define MPC52xx_IRQ_L2_MASK (0x3f)
+
+
+/* ======================================================================== */
+/* Structures mapping of some unit register set */
+/* ======================================================================== */
+
+#ifndef __ASSEMBLY__
+
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+ u32 mbar; /* MMAP_CTRL + 0x00 */
+
+ u32 cs0_start; /* MMAP_CTRL + 0x04 */
+ u32 cs0_stop; /* MMAP_CTRL + 0x08 */
+ u32 cs1_start; /* MMAP_CTRL + 0x0c */
+ u32 cs1_stop; /* MMAP_CTRL + 0x10 */
+ u32 cs2_start; /* MMAP_CTRL + 0x14 */
+ u32 cs2_stop; /* MMAP_CTRL + 0x18 */
+ u32 cs3_start; /* MMAP_CTRL + 0x1c */
+ u32 cs3_stop; /* MMAP_CTRL + 0x20 */
+ u32 cs4_start; /* MMAP_CTRL + 0x24 */
+ u32 cs4_stop; /* MMAP_CTRL + 0x28 */
+ u32 cs5_start; /* MMAP_CTRL + 0x2c */
+ u32 cs5_stop; /* MMAP_CTRL + 0x30 */
+
+ u32 sdram0; /* MMAP_CTRL + 0x34 */
+ u32 sdram1; /* MMAP_CTRL + 0X38 */
+
+ u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
+
+ u32 boot_start; /* MMAP_CTRL + 0x4c */
+ u32 boot_stop; /* MMAP_CTRL + 0x50 */
+
+ u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
+
+ u32 cs6_start; /* MMAP_CTRL + 0x58 */
+ u32 cs6_stop; /* MMAP_CTRL + 0x5c */
+ u32 cs7_start; /* MMAP_CTRL + 0x60 */
+ u32 cs7_stop; /* MMAP_CTRL + 0x64 */
+};
+
+/* SDRAM control */
+struct mpc52xx_sdram {
+ u32 mode; /* SDRAM + 0x00 */
+ u32 ctrl; /* SDRAM + 0x04 */
+ u32 config1; /* SDRAM + 0x08 */
+ u32 config2; /* SDRAM + 0x0c */
+};
+
+/* Interrupt controller */
+struct mpc52xx_intr {
+ u32 per_mask; /* INTR + 0x00 */
+ u32 per_pri1; /* INTR + 0x04 */
+ u32 per_pri2; /* INTR + 0x08 */
+ u32 per_pri3; /* INTR + 0x0c */
+ u32 ctrl; /* INTR + 0x10 */
+ u32 main_mask; /* INTR + 0x14 */
+ u32 main_pri1; /* INTR + 0x18 */
+ u32 main_pri2; /* INTR + 0x1c */
+ u32 reserved1; /* INTR + 0x20 */
+ u32 enc_status; /* INTR + 0x24 */
+ u32 crit_status; /* INTR + 0x28 */
+ u32 main_status; /* INTR + 0x2c */
+ u32 per_status; /* INTR + 0x30 */
+ u32 reserved2; /* INTR + 0x34 */
+ u32 per_error; /* INTR + 0x38 */
+};
+
+/* SDMA */
+struct mpc52xx_sdma {
+ u32 taskBar; /* SDMA + 0x00 */
+ u32 currentPointer; /* SDMA + 0x04 */
+ u32 endPointer; /* SDMA + 0x08 */
+ u32 variablePointer;/* SDMA + 0x0c */
+
+ u8 IntVect1; /* SDMA + 0x10 */
+ u8 IntVect2; /* SDMA + 0x11 */
+ u16 PtdCntrl; /* SDMA + 0x12 */
+
+ u32 IntPend; /* SDMA + 0x14 */
+ u32 IntMask; /* SDMA + 0x18 */
+
+ u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
+
+ u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
+
+ u32 cReqSelect; /* SDMA + 0x5c */
+ u32 task_size0; /* SDMA + 0x60 */
+ u32 task_size1; /* SDMA + 0x64 */
+ u32 MDEDebug; /* SDMA + 0x68 */
+ u32 ADSDebug; /* SDMA + 0x6c */
+ u32 Value1; /* SDMA + 0x70 */
+ u32 Value2; /* SDMA + 0x74 */
+ u32 Control; /* SDMA + 0x78 */
+ u32 Status; /* SDMA + 0x7c */
+ u32 PTDDebug; /* SDMA + 0x80 */
+};
+
+/* GPT */
+struct mpc52xx_gpt {
+ u32 mode; /* GPTx + 0x00 */
+ u32 count; /* GPTx + 0x04 */
+ u32 pwm; /* GPTx + 0x08 */
+ u32 status; /* GPTx + 0X0c */
+};
+
+/* RTC */
+struct mpc52xx_rtc {
+ u32 time_set; /* RTC + 0x00 */
+ u32 date_set; /* RTC + 0x04 */
+ u32 stopwatch; /* RTC + 0x08 */
+ u32 int_enable; /* RTC + 0x0c */
+ u32 time; /* RTC + 0x10 */
+ u32 date; /* RTC + 0x14 */
+ u32 stopwatch_intr; /* RTC + 0x18 */
+ u32 bus_error; /* RTC + 0x1c */
+ u32 dividers; /* RTC + 0x20 */
+};
+
+/* GPIO */
+struct mpc52xx_gpio {
+ u32 port_config; /* GPIO + 0x00 */
+ u32 simple_gpioe; /* GPIO + 0x04 */
+ u32 simple_ode; /* GPIO + 0x08 */
+ u32 simple_ddr; /* GPIO + 0x0c */
+ u32 simple_dvo; /* GPIO + 0x10 */
+ u32 simple_ival; /* GPIO + 0x14 */
+ u8 outo_gpioe; /* GPIO + 0x18 */
+ u8 reserved1[3]; /* GPIO + 0x19 */
+ u8 outo_dvo; /* GPIO + 0x1c */
+ u8 reserved2[3]; /* GPIO + 0x1d */
+ u8 sint_gpioe; /* GPIO + 0x20 */
+ u8 reserved3[3]; /* GPIO + 0x21 */
+ u8 sint_ode; /* GPIO + 0x24 */
+ u8 reserved4[3]; /* GPIO + 0x25 */
+ u8 sint_ddr; /* GPIO + 0x28 */
+ u8 reserved5[3]; /* GPIO + 0x29 */
+ u8 sint_dvo; /* GPIO + 0x2c */
+ u8 reserved6[3]; /* GPIO + 0x2d */
+ u8 sint_inten; /* GPIO + 0x30 */
+ u8 reserved7[3]; /* GPIO + 0x31 */
+ u16 sint_itype; /* GPIO + 0x34 */
+ u16 reserved8; /* GPIO + 0x36 */
+ u8 gpio_control; /* GPIO + 0x38 */
+ u8 reserved9[3]; /* GPIO + 0x39 */
+ u8 sint_istat; /* GPIO + 0x3c */
+ u8 sint_ival; /* GPIO + 0x3d */
+ u8 bus_errs; /* GPIO + 0x3e */
+ u8 reserved10; /* GPIO + 0x3f */
+};
+
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
+#define MPC52xx_GPIO_PCI_DIS (1<<15)
+
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+ u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
+ u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
+ u8 wkup_ode; /* GPIO_WKUP + 0x04 */
+ u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
+ u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
+ u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
+ u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
+ u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
+ u8 wkup_inten; /* GPIO_WKUP + 0x10 */
+ u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
+ u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
+ u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
+ u16 wkup_itype; /* GPIO_WKUP + 0x18 */
+ u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
+ u8 wkup_maste; /* GPIO_WKUP + 0x1C */
+ u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
+ u8 wkup_ival; /* GPIO_WKUP + 0x20 */
+ u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
+ u8 wkup_istat; /* GPIO_WKUP + 0x24 */
+ u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
+};
+
+/* XLB Bus control */
+struct mpc52xx_xlb {
+ u8 reserved[0x40];
+ u32 config; /* XLB + 0x40 */
+ u32 version; /* XLB + 0x44 */
+ u32 status; /* XLB + 0x48 */
+ u32 int_enable; /* XLB + 0x4c */
+ u32 addr_capture; /* XLB + 0x50 */
+ u32 bus_sig_capture; /* XLB + 0x54 */
+ u32 addr_timeout; /* XLB + 0x58 */
+ u32 data_timeout; /* XLB + 0x5c */
+ u32 bus_act_timeout; /* XLB + 0x60 */
+ u32 master_pri_enable; /* XLB + 0x64 */
+ u32 master_priority; /* XLB + 0x68 */
+ u32 base_address; /* XLB + 0x6c */
+ u32 snoop_window; /* XLB + 0x70 */
+};
+
+#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
+#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
+
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+ u32 jtag_id; /* CDM + 0x00 reg0 read only */
+ u32 rstcfg; /* CDM + 0x04 reg1 read only */
+ u32 breadcrumb; /* CDM + 0x08 reg2 */
+
+ u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
+ u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
+ u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
+ u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
+
+ u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
+ u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
+ u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
+
+ u32 clk_enables; /* CDM + 0x14 reg5 */
+
+ u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
+ u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
+
+ u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
+ u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
+ u8 reserved1; /* CDM + 0x1e reg7 byte2 */
+ u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
+
+ u8 soft_reset; /* CDM + 0x20 u8 byte0 */
+ u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
+ u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
+
+ u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
+ u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
+ u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
+ u8 reserved3; /* CDM + 0x27 reg9 byte3 */
+
+ u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
+ u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
+
+ u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
+ u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
+
+ u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
+ u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
+
+ u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
+ u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+/* ========================================================================= */
+/* Prototypes for MPC52xx syslib */
+/* ========================================================================= */
+
+#ifndef __ASSEMBLY__
+
+extern void mpc52xx_init_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
+
+extern unsigned long mpc52xx_find_end_of_memory(void);
+extern void mpc52xx_set_bat(void);
+extern void mpc52xx_map_io(void);
+extern void mpc52xx_restart(char *cmd);
+extern void mpc52xx_halt(void);
+extern void mpc52xx_power_off(void);
+extern void mpc52xx_progress(char *s, unsigned short hex);
+extern void mpc52xx_calibrate_decr(void);
+
+extern void mpc52xx_find_bridges(void);
+
+extern void mpc52xx_setup_cpu(void);
+
+static inline struct device_node *
+find_mpc52xx_picnode(void)
+{
+ return of_find_compatible_node(NULL, "interrupt-controller", "mpc5200-pic");
+}
+
+ /* Matching of PSC function */
+struct mpc52xx_psc_func {
+ int id;
+ char *func;
+};
+
+extern int mpc52xx_match_psc_function(int psc_idx, const char *func);
+extern struct mpc52xx_psc_func mpc52xx_psc_functions[];
+ /* This array is to be defined in platform file */
+
+#endif /* __ASSEMBLY__ */
+
+
+#endif /* _ASM_POWERPC_MPC52xx_H__ */
[-- Attachment #3: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: glibc-2.5 test suite hangs/crashes the machine
From: Jeff Bailey @ 2006-10-27 16:22 UTC (permalink / raw)
To: Fabio Massimo Di Nitto; +Cc: Ben Collins, Paul Mackerras, linuxppc-dev
In-Reply-To: <45419F79.2020300@ubuntu.com>
Le vendredi 27 octobre 2006 =C3=A0 07:56 +0200, Fabio Massimo Di Nitto a
=C3=A9crit :
> Hi everybody,
>=20
> i am in the process of bootstrapping the new toolchain for ubuntu and I a=
m
> hitting a problem building glibc-2.5 on ppc.
>=20
> This behaviour has been reproduced on 2.6.15/2.6.17 and 2.6.19-rc2 (where=
the
> machine crashes) and with ppc32 and ppc64 kernels.
> A hard reboot of the machine is required to get rid of the Zl processes h=
anging
> around that keep spinning the CPU at 100%.
>=20
> I did place sources here: http://people.ubuntu.com/~fabbione/benh/
>=20
> but i start to believe it is a kernel bug we are exploiting only now.
>=20
> Any hint or help for what to look for would be extremely appreciated.
Heya Fabio, just an update, it looks like the tests that are zombie'ing
are the nptl tst-robust[1-8] tests. According to /proc/##/wchan, the
tasks are cheerfully spinning in do_exit.
If there's other info I can get you, lemme know.
--=20
Jeff Bailey
Manager, Technical Support
Canonical Ltd. - Sales, Service, and Support.
+1 514 940-8910
http://www.ubuntu.com/
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Jon Loeliger @ 2006-10-27 17:08 UTC (permalink / raw)
To: Nicolas DET
Cc: akpm, linuxppc-dev@ozlabs.org, sl, sha,
linuxppc-embedded@ozlabs.org
In-Reply-To: <45421FFD.8070407@bplan-gmbh.de>
On Fri, 2006-10-27 at 10:04, Nicolas DET wrote:
> > diff -uprN a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
> > --- a/include/asm-powerpc/mpc52xx.h 1970-01-01 01:00:00.000000000 +0100
> > +++ b/include/asm-powerpc/mpc52xx.h 2006-10-27 15:51:55.000000000 +0200
> > @@ -0,0 +1,414 @@
> > +/*
> > + * include/asm-ppc/mpc52xx.h
> > + *
>
>
> Fixed to powerpc
I thought we were removing the names of files from
within the file itself, right?
Thanks,
jdl
^ permalink raw reply
* [POWERPC] Cleanup pegasos i8259 not in device tree workaround.
From: Grant Likely @ 2006-10-27 16:42 UTC (permalink / raw)
To: Nicolas DET, Benjamin Herrenschmidt, linuxppc-dev
From: Grant Likely <grant.likely@secretlab.ca>
Only make assumptions about i8259 presence if ppc_md.get_irq is not set.
Previous workaround only checked chrp_mpic value.
Nicolas, please verify that this patch fixes your mpc52xx pic problems.
Ben, I got tired of how often this question was being raised, so I just
wrote this patch; I've compiled, but cannot test it.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
---
arch/powerpc/platforms/chrp/setup.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c
index 49b8dab..a5466ed 100644
--- a/arch/powerpc/platforms/chrp/setup.c
+++ b/arch/powerpc/platforms/chrp/setup.c
@@ -451,7 +451,7 @@ static void __init chrp_find_8259(void)
* we have a pegasos that claims to be chrp but doesn't have
* a proper interrupt tree
*/
- if (pic == NULL && chrp_mpic != NULL) {
+ if (pic == NULL && ppc_md.get_irq != NULL) {
printk(KERN_ERR "i8259: Not found in device-tree"
" assuming no legacy interrupts\n");
return;
--
1.4.3.rc2.g0503
^ permalink raw reply related
* Building ELDK 3.0/3.1 from SRPMS
From: John W @ 2006-10-27 18:21 UTC (permalink / raw)
To: linuxppc-embedded
Hello-
I having trouble rebuilding ELDK 3.0 & ELDK 3.1 from
the source RPMS. I have spent a great deal of time on
this, and I have a feeling that maybe I’m just not
doing something correctly (setting up the build
environment, retrieving source/specs from CVS..
etc..). My build machine is Red Hat 9.0 without any
updates (Kernel 2.4.20-8, the Shrike release).
The following is the process I’m using to setup my
development environment for ELDK 3.0
#Make build directory
mkdir /opt/eldkv3.0
#checkout tarballs & build. One caveat is that I’m
behind a proxy server, and I’m having to check these
files out on remote computer, and tar -czvf the
directories up, and copying the files to the build
computer. I would imagine that this is functionally
equivalent.
cd /opt/eldkv3.0
cvs -d :pserver:anonymous@www.denx.de:/cvsroot login
cvs -z6 -d :pserver:anonymous@www.denx.de:/cvsroot co
-rELDK_3_0 -P eldk_tarballs
cvs -z6 -d :pserver:anonymous@www.denx.de:/cvsroot co
-rELDK_3_0 -P eldk_build
#get yellowdog 3.0 prestine SRPMS
cd /opt/eldkv3.0
mkdir SRPMS
cd /opt/eldkv3.0/SRPMS
wget -r -nd -np -l1 -A ‘*.rpm’
http://ydl.osuosl.org/releases/yellowdog-3.0/en/os/SRPMS/
wget -r -nd -np -l1 -A ‘*.rpm’
http://ydl.osuosl.org/updates/yellowdog-3.0/SRPMS/
#export the prefix & target architecture
export ELDK_PREFIX=/opt/eldkv3.0
export TARGET_CPU_FAMILY_LIST=”4xx”
#execute build process
cd /opt/eldkv3.0/build
./ELDK_BUILD
Executing ELDK_BUILD seems to build almost everything,
but there seems to be a lot of packages missing,
namely libstdc++.so. When checking the logs, I see
something suspicious while build the make RPM in that
it shows the following failure:
/opt/eldkv3.0/build/ppc-2006-10-27/logs/build_make.log:
….
checking for waitpid... yes
checking for wait3... yes
checking for union wait... no
checking for sys_siglist declaration in signal.h or
unistd.h... yes
checking for library containing getpwnam... none
required
checking for location of SCCS get command... get
checking if system libc has GNU glob... yes
updating cache ./config.cache
creating ./config.status
creating build.sh
creating Makefile
creating glob/Makefile
creating i18n/Makefile
creating config.h
+ make
cd . && aclocal
cd . && automake --gnu --include-deps Makefile
Makefile.am: required file `./depcomp' not found
make: *** [Makefile.in] Error 1
error: Bad exit status from
/opt/eldkv3.0/build/ppc-2006-10-27/work/var/tmp/rpm-tmp.54649
(%build)
RPM build errors:
Bad exit status from
/opt/eldkv3.0/build/ppc-2006-10-27/work/var/tmp/rpm-tmp.54649
(%build)
I’m not exactly sure that by fixing this problem will
install libstdc++ correctly, infact, I’m not exactly
sure why ELDK is not completely building everything.
In trying to remedy this problem, I have upgraded my
system to use autoconf 2.60, automake 1.9 and m4
1.4.7, but none of those seems to help. The only
other thing I can think of is upgrading my version of
bison.
I have also tried the same type of method to build
ELDK 3.1 from SRPMS, and have received the same error
from the build_make.log file.
Any help would be greatly appreciated!
John M. Woo
jmwoo2 <at> yahoo.com
__________________________________________________
Do You Yahoo!?
Tired of spam? Yahoo! Mail has the best spam protection around
http://mail.yahoo.com
^ permalink raw reply
* Re: CPM2 SCC/SMC break handling broken
From: Ricardo Scop @ 2006-10-27 18:20 UTC (permalink / raw)
To: Laurent Pinchart; +Cc: linuxppc-embedded
In-Reply-To: <200610271101.38911.laurent.pinchart@tbox.biz>
Hi Laurent,
On Friday 27 October 2006 07:01, Laurent Pinchart wrote:
> Hi Ricardo,
>
> > > Hi everybody,
> > >
> > > I need to generate a break on a CPM2 SMC serial port (same issue wi=
th
> > > SCC serial ports).
> > >
> > > The tcsendbreak() man page states that the function should generate=
a
> > > break between 250ms and 500ms, but testing showed that the break is=
one
> > > character long (10 bits in 8N1 mode).
> >
> > [snip]
> >
> > > CPM_CR_STOP_TX is documented to generate a break of BRKCR character=
s.
> > > The BRKCR register is initialized to 1, so only 1 break character i=
s
> > > sent, which won't last between 250ms and 500ms.
> >
> > [snip]
> >
> > > Could anyone think of a proper solution which would not disturb the
> > > other drivers too much ?
> >
> > Well, one could always set the BRKCR parameter to the maximum number =
of
> > break characters permitted by it's size, since the break condition wi=
ll
> > anyway end as soon as the RESTART TX command is issued as a consequen=
ce
> > of the tty->driver->break_ctl(tty, 0) call. But I did not test this.
>
> That's a very good idea, but the documentation is a bit misleading here=
=2E I
> tested the CPM2 behaviour, and found out that the break will last BRKCR
> characters, even if a RESTART TX command is sent sooner.
>
> The user manual states
>
> "The SMC sends a programmable number of break characters according to B=
RKCR
> and reverts to idle or sends data if a RESTART TRANSMIT is issued befor=
e
> completion."
>
> I suppose they meant that, if a RESTART TX command is issued before
> completion of the break sequence, the SMC will send data at the end of =
the
> break sequence. This is at least the behaviour I noticed after trying y=
our
> idea.
Too bad.... :( One more good idea to the junk bin.
Hmm, just a wild shot you can try, while you're at that: what about setti=
ng=20
BRKCR to zero and issuing another STOP TRANSMIT, just before the RESTART=20
TRANSMIT?=20
Another reasonable shot would be to disable and reenable the transmitter =
in an=20
attempt to stop the break sequence; though I don't know what happens to t=
he=20
SMC state machine in this case.
Too wild guesses? Well, maybe someone at Freescale can have a better idea=
=2E :)
Best regards,
Ricardo Scop.
^ permalink raw reply
* TEMAC drivers for kernel 2.6.17.1
From: Pradeep Sampath @ 2006-10-27 19:20 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 5540 bytes --]
Hi,
I am using linux kernel 2.6.17.1 on ML403 dev board. I am trying to get the TEMAC to work but with no success. I applied TEMAC patches from http://source.mvista.com/~ank/paulus-powerpc/20060309/. But the ethernet interface does not seem to come up.
Is there any other TEMAC patch out there which is known to work with 2.6 kernel?
For the BSP I tried using the ML403 EDK Embedded PowerPC reference design from Xilinx. But it doesn't come with a PLB TEMAC in the design. I also tried to use xapp902 which has the PLB TEMAC module. But on running "Generate Libraries and BSPs" it does not generate any sources code under "drivers" or "arch" folder.
-Pradeep
I have attached the boot up logs from the hyper-terminal.
loaded at: 00400000 0051913C
board data at: 00517124 0051713C
relocated to: 004050E0 004050F8
zimage at: 004057F5 00516F4D
avail ram: 0051A000 10000000
Linux/PPC load: console=ttyS0,9600 root=/dev/xsa2
Uncompressing Linux...done.
Now booting the kernel
[ 0.000000] Linux version 2.6.17.1 (psampath@psampath-test) (gcc version 3.4.
1) #5 Sun Oct 22 10:25:16 PDT 2006
[ 0.000000] Xilinx ML403 Reference System (Virtex-4 FX)
[ 0.000000] Built 1 zonelists
[ 0.000000] Kernel command line: console=ttyS0,9600 root=/dev/xsa2
[ 0.000000] Xilinx INTC #0 at 0xD1000FC0 mapped to 0xFDFFEFC0
[ 0.000000] PID hash table entries: 2048 (order: 11, 8192 bytes)
[ 0.000183] Console: colour dummy device 80x25
[ 0.001962] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.005114] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.060120] Memory: 257280k available (1808k kernel code, 616k data, 84k init
, 0k highmem)
[ 0.248262] Security Framework v1.0.0 initialized
[ 0.248328] SELinux: Disabled at boot.
[ 0.248481] Mount-cache hash table entries: 512
[ 0.254057] NET: Registered protocol family 16
[ 0.262730] NET: Registered protocol family 2
[ 0.316488] IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.317422] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.317970] TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.318284] TCP: Hash tables configured (established 8192 bind 4096)
[ 0.318320] TCP reno registered
[ 0.325013] audit: initializing netlink socket (disabled)
[ 0.325150] audit(0.324:1): initialized
[ 0.326666] VFS: Disk quotas dquot_6.5.1
[ 0.326910] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[ 0.327817] Initializing Cryptographic API
[ 0.327891] io scheduler noop registered
[ 0.328088] io scheduler anticipatory registered (default)
[ 0.328173] io scheduler deadline registered
[ 0.328345] io scheduler cfq registered
[ 0.946309] Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing
enabled
[ 0.955054] serial8250.0: ttyS0 at MMIO 0xa0001003 (irq = 9) is a 16450
[ 3.002532] RAMDISK driver initialized: 16 RAM disks of 65536K size 1024 bloc
ksize
[ 3.093986] xsa: xsa1 xsa2
[ 3.138222] i8042.c: No controller found.
[ 3.186302] TCP bic registered
[ 3.222088] NET: Registered protocol family 8
[ 3.274064] NET: Registered protocol family 20
[ 3.336810] EXT3-fs: INFO: recovery required on readonly filesystem.
[ 3.412076] EXT3-fs: write access will be enabled during recovery.
[ 3.717927] kjournald starting. Commit interval 5 seconds
[ 3.782937] EXT3-fs: recovery complete.
[ 3.870012] EXT3-fs: mounted filesystem with ordered data mode.
[ 3.940755] VFS: Mounted root (ext3 filesystem) readonly.
[ 4.004944] Freeing unused kernel memory: 84k init
INIT: version 2.78 booting
Activating swap...
/etc/init.d/rcS: /dev/null: Read-only file system
[ 9.866081] EXT3-fs warning: mounting unchecked fs, running e2fsck is recomme
nded
[ 9.957819] EXT3 FS on xsa2, internal journal
Checking all file systems...
fsck 1.27 (8-Mar-2002)
Calculating module dependencies... depmod: QM_MODULES: Function not implemented
done.
Loading modules:
modprobe: Can't open dependencies file /lib/modules/2.6.17.1/modules.dep (No suc
h file or directory)
Mounting local filesystems...
nothing was mounted
Cleaning: /etc/network/ifstate.
Setting up IP spoofing protection: rp_filter.
Disable TCP/IP Explicit Congestion Notification: done.
Configuring network interfaces: done.
Starting portmap daemon: portmap.
Starting dhcpcd on eth0
Running ntpdate to synchronize clock.
Cleaning: /tmp /var/lock /var/runfind: ./syslogd.pid: Input/output error
find: ./syslogd.pid: Input/output error
find: ./inetd.pid: Input/output error
find: ./inetd.pid: Input/output error
dhcpcd[734]: dhcpStart: socket: Address family not supported by protocol
.
sed: can't read /etc/motd: Input/output error
INIT: Entering runlevel: 3': Input/output
Starting kernel log daemon: klogd.
Starting system log daemon: syslogd
Starting web server: apache.
Starting internet superserver: inetdstart-stop-daemon: open pidfile /var/run/ine
td.pid: Input/output error
.
Hostname: ml403.
Creating barrier for shutdown
Starting X11 session for user 'linux'
PAM_unix[966]: (su) session opened for user linux by (uid=0)
Welcome to the ML403 Evaluation Board
(C) 2004 Xilinx, I
MontaVista(R) Linux(R) Professional Edition 3.1
ml403 login: root
PAM-securetty[988]: Couldn't open /etc/securetty
Password:
PAM_unix[988]: (login) session opened for user root by LOGIN(uid=0)
Last login: Thu Jan 1 00:16:05 1970 on console
login[988]: ROOT LOGIN on `console'
root@ml403:~#
[-- Attachment #2: Type: text/html, Size: 7228 bytes --]
^ permalink raw reply
* Re: [1/2] build failure for E500 CPUs w/ CONFIG_OPROFLE=y
From: Andy Fleming @ 2006-10-27 20:03 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: linuxppc-dev list, Vitaly Wool, oprofile-list
In-Reply-To: <45411B46.9060106@ru.mvista.com>
On Oct 26, 2006, at 15:32, Sergei Shtylyov wrote:
> Hello.
>
> Vitaly Wool wrote:
>> Hello Kumar,
>
>>> This makes sense to me since we are just increasing kernel code size
>>> for code we would never use for an FSL_BOOKE part if we do it the
>>> other way. I dont think its that much more messy with the ifdef's.
>
>> Okay, if you're fine with this patch, is it possible that you
>> include it
>> into your tree?
>
>>> If you want to do the other cleanup as well I've got no issue with
>>> that, but we really should NOT build in support for 7450 into a
>>> FSL_BOOKE kernel when reasonably avoidable.
>
>> That's fine with me.
>> As of the cleanups, well... looks to me some more patches will follow
>> soon, kinda bugfixing ones rather than cleanups first :)
>
> The most funny/stupd thing is that the patch existed since May
> but it never
> went in:
>
> http://patchwork.ozlabs.org/linuxppc/patch?id=5531
Yeah, I guess it got lost. After looking at both patches, I see the
different approaches. I think I'd vote for the older patch, since it
also solves some SMP issues that will crop up when the dual-core 8572
comes out. In fact, it's similar to this patch: http://
patchwork.ozlabs.org/linuxppc/patch?id=4012
Oi. Ok, I'm going to update and resend that patch in just a second
(Ok, this took longer than I thought, due to the lwsync patch I sent
out being required). I like Vitaly's patch, but the one I sent
cleans up some early design mistakes I made in the original ppc32
oprofile code.
>
>> Thanks,
>> Vitaly
>
> WBR, Sergei
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* [PATCH] Fix oprofile support for e500 in arch/powerpc
From: Andy Fleming @ 2006-10-27 20:06 UTC (permalink / raw)
To: linuxppc-dev, linuxppc-embedded, Paul Mackerras, Kumar Gala; +Cc: Oprofile List
Fixed a compile error in building the 85xx support with oprofile, and in
the process cleaned up some issues with the fsl_booke performance monitor
code.
* Reorganized FSL Book-E performance monitoring code so that the 7450
wouldn't be built if the e500 was, and cleaned it up so it was more
self-contained.
* Added a cpu_setup function for FSL Book-E. The original
cpu_setup function prototype had no arguments, assuming that
the reg_setup function would copy the required information into
variables which represented the registers. This was silly for
e500, since it has 1 register per counter (rather than 3 for
all counters), so the code has been restructured to have
cpu_setup take the current counter config array as an argument,
with op_powerpc_setup() invoking op_powerpc_cpu_setup() through
on_each_cpu(), and op_powerpc_cpu_setup() invoking the
model-specific cpu_setup function with an argument. The
argument is ignored on all other platforms at present.
* Fixed a confusing line where a trinary operator only had two
arguments
Signed-off-by: Andrew Fleming <afleming@freescale.com>
---
This is a very slight respin of this patch:
http://patchwork.ozlabs.org/linuxppc/patch?id=5531
Thanks to Vitaly Wool for noticing that this bug still existed!
arch/powerpc/kernel/Makefile | 1
arch/powerpc/kernel/perfmon_fsl_booke.c | 221 ----------------------------
arch/powerpc/kernel/pmc.c | 2
arch/powerpc/oprofile/Makefile | 2
arch/powerpc/oprofile/common.c | 10 +
arch/powerpc/oprofile/op_model_7450.c | 2
arch/powerpc/oprofile/op_model_fsl_booke.c | 170 +++++++++++++++++-----
arch/powerpc/oprofile/op_model_power4.c | 2
arch/powerpc/oprofile/op_model_rs64.c | 2
include/asm-powerpc/oprofile_impl.h | 87 +++++++++++
include/asm-powerpc/pmc.h | 13 --
11 files changed, 234 insertions(+), 278 deletions(-)
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 8b133af..7af23c4 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -38,7 +38,6 @@ obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6x
obj-$(CONFIG_TAU) += tau_6xx.o
obj32-$(CONFIG_SOFTWARE_SUSPEND) += swsusp_32.o
obj32-$(CONFIG_MODULES) += module_32.o
-obj-$(CONFIG_E500) += perfmon_fsl_booke.o
ifeq ($(CONFIG_PPC_MERGE),y)
diff --git a/arch/powerpc/kernel/perfmon_fsl_booke.c b/arch/powerpc/kernel/perfmon_fsl_booke.c
deleted file mode 100644
index e0dcf2b..0000000
--- a/arch/powerpc/kernel/perfmon_fsl_booke.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* arch/powerpc/kernel/perfmon_fsl_booke.c
- * Freescale Book-E Performance Monitor code
- *
- * Author: Andy Fleming
- * Copyright (c) 2004 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/stddef.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/slab.h>
-#include <linux/user.h>
-#include <linux/a.out.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/prctl.h>
-
-#include <asm/pgtable.h>
-#include <asm/uaccess.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/reg.h>
-#include <asm/xmon.h>
-#include <asm/pmc.h>
-
-static inline u32 get_pmlca(int ctr);
-static inline void set_pmlca(int ctr, u32 pmlca);
-
-static inline u32 get_pmlca(int ctr)
-{
- u32 pmlca;
-
- switch (ctr) {
- case 0:
- pmlca = mfpmr(PMRN_PMLCA0);
- break;
- case 1:
- pmlca = mfpmr(PMRN_PMLCA1);
- break;
- case 2:
- pmlca = mfpmr(PMRN_PMLCA2);
- break;
- case 3:
- pmlca = mfpmr(PMRN_PMLCA3);
- break;
- default:
- panic("Bad ctr number\n");
- }
-
- return pmlca;
-}
-
-static inline void set_pmlca(int ctr, u32 pmlca)
-{
- switch (ctr) {
- case 0:
- mtpmr(PMRN_PMLCA0, pmlca);
- break;
- case 1:
- mtpmr(PMRN_PMLCA1, pmlca);
- break;
- case 2:
- mtpmr(PMRN_PMLCA2, pmlca);
- break;
- case 3:
- mtpmr(PMRN_PMLCA3, pmlca);
- break;
- default:
- panic("Bad ctr number\n");
- }
-}
-
-void init_pmc_stop(int ctr)
-{
- u32 pmlca = (PMLCA_FC | PMLCA_FCS | PMLCA_FCU |
- PMLCA_FCM1 | PMLCA_FCM0);
- u32 pmlcb = 0;
-
- switch (ctr) {
- case 0:
- mtpmr(PMRN_PMLCA0, pmlca);
- mtpmr(PMRN_PMLCB0, pmlcb);
- break;
- case 1:
- mtpmr(PMRN_PMLCA1, pmlca);
- mtpmr(PMRN_PMLCB1, pmlcb);
- break;
- case 2:
- mtpmr(PMRN_PMLCA2, pmlca);
- mtpmr(PMRN_PMLCB2, pmlcb);
- break;
- case 3:
- mtpmr(PMRN_PMLCA3, pmlca);
- mtpmr(PMRN_PMLCB3, pmlcb);
- break;
- default:
- panic("Bad ctr number!\n");
- }
-}
-
-void set_pmc_event(int ctr, int event)
-{
- u32 pmlca;
-
- pmlca = get_pmlca(ctr);
-
- pmlca = (pmlca & ~PMLCA_EVENT_MASK) |
- ((event << PMLCA_EVENT_SHIFT) &
- PMLCA_EVENT_MASK);
-
- set_pmlca(ctr, pmlca);
-}
-
-void set_pmc_user_kernel(int ctr, int user, int kernel)
-{
- u32 pmlca;
-
- pmlca = get_pmlca(ctr);
-
- if(user)
- pmlca &= ~PMLCA_FCU;
- else
- pmlca |= PMLCA_FCU;
-
- if(kernel)
- pmlca &= ~PMLCA_FCS;
- else
- pmlca |= PMLCA_FCS;
-
- set_pmlca(ctr, pmlca);
-}
-
-void set_pmc_marked(int ctr, int mark0, int mark1)
-{
- u32 pmlca = get_pmlca(ctr);
-
- if(mark0)
- pmlca &= ~PMLCA_FCM0;
- else
- pmlca |= PMLCA_FCM0;
-
- if(mark1)
- pmlca &= ~PMLCA_FCM1;
- else
- pmlca |= PMLCA_FCM1;
-
- set_pmlca(ctr, pmlca);
-}
-
-void pmc_start_ctr(int ctr, int enable)
-{
- u32 pmlca = get_pmlca(ctr);
-
- pmlca &= ~PMLCA_FC;
-
- if (enable)
- pmlca |= PMLCA_CE;
- else
- pmlca &= ~PMLCA_CE;
-
- set_pmlca(ctr, pmlca);
-}
-
-void pmc_start_ctrs(int enable)
-{
- u32 pmgc0 = mfpmr(PMRN_PMGC0);
-
- pmgc0 &= ~PMGC0_FAC;
- pmgc0 |= PMGC0_FCECE;
-
- if (enable)
- pmgc0 |= PMGC0_PMIE;
- else
- pmgc0 &= ~PMGC0_PMIE;
-
- mtpmr(PMRN_PMGC0, pmgc0);
-}
-
-void pmc_stop_ctrs(void)
-{
- u32 pmgc0 = mfpmr(PMRN_PMGC0);
-
- pmgc0 |= PMGC0_FAC;
-
- pmgc0 &= ~(PMGC0_PMIE | PMGC0_FCECE);
-
- mtpmr(PMRN_PMGC0, pmgc0);
-}
-
-void dump_pmcs(void)
-{
- printk("pmgc0: %x\n", mfpmr(PMRN_PMGC0));
- printk("pmc\t\tpmlca\t\tpmlcb\n");
- printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC0),
- mfpmr(PMRN_PMLCA0), mfpmr(PMRN_PMLCB0));
- printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC1),
- mfpmr(PMRN_PMLCA1), mfpmr(PMRN_PMLCB1));
- printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC2),
- mfpmr(PMRN_PMLCA2), mfpmr(PMRN_PMLCB2));
- printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC3),
- mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3));
-}
-
-EXPORT_SYMBOL(init_pmc_stop);
-EXPORT_SYMBOL(set_pmc_event);
-EXPORT_SYMBOL(set_pmc_user_kernel);
-EXPORT_SYMBOL(set_pmc_marked);
-EXPORT_SYMBOL(pmc_start_ctr);
-EXPORT_SYMBOL(pmc_start_ctrs);
-EXPORT_SYMBOL(pmc_stop_ctrs);
-EXPORT_SYMBOL(dump_pmcs);
diff --git a/arch/powerpc/kernel/pmc.c b/arch/powerpc/kernel/pmc.c
index a0a2efa..3d8f6f4 100644
--- a/arch/powerpc/kernel/pmc.c
+++ b/arch/powerpc/kernel/pmc.c
@@ -71,7 +71,7 @@ int reserve_pmc_hardware(perf_irq_t new_
}
pmc_owner_caller = __builtin_return_address(0);
- perf_irq = new_perf_irq ? : dummy_perf;
+ perf_irq = new_perf_irq ? new_perf_irq : dummy_perf;
out:
spin_unlock(&pmc_owner_lock);
diff --git a/arch/powerpc/oprofile/Makefile b/arch/powerpc/oprofile/Makefile
index 3145d61..0b5df9c 100644
--- a/arch/powerpc/oprofile/Makefile
+++ b/arch/powerpc/oprofile/Makefile
@@ -13,4 +13,4 @@ DRIVER_OBJS := $(addprefix ../../../driv
oprofile-y := $(DRIVER_OBJS) common.o backtrace.o
oprofile-$(CONFIG_PPC64) += op_model_rs64.o op_model_power4.o
oprofile-$(CONFIG_FSL_BOOKE) += op_model_fsl_booke.o
-oprofile-$(CONFIG_PPC32) += op_model_7450.o
+oprofile-$(CONFIG_6xx) += op_model_7450.o
diff --git a/arch/powerpc/oprofile/common.c b/arch/powerpc/oprofile/common.c
index fd0bbbe..63bbef3 100644
--- a/arch/powerpc/oprofile/common.c
+++ b/arch/powerpc/oprofile/common.c
@@ -34,6 +34,11 @@ static void op_handle_interrupt(struct p
model->handle_interrupt(regs, ctr);
}
+static void op_powerpc_cpu_setup(void *dummy)
+{
+ model->cpu_setup(ctr);
+}
+
static int op_powerpc_setup(void)
{
int err;
@@ -47,7 +52,7 @@ static int op_powerpc_setup(void)
model->reg_setup(ctr, &sys, model->num_counters);
/* Configure the registers on all cpus. */
- on_each_cpu(model->cpu_setup, NULL, 0, 1);
+ on_each_cpu(op_powerpc_cpu_setup, NULL, 0, 1);
return 0;
}
@@ -142,7 +147,8 @@ #ifdef CONFIG_PPC64
case PPC_OPROFILE_POWER4:
model = &op_model_power4;
break;
-#else
+#endif
+#ifdef CONFIG_6xx
case PPC_OPROFILE_G4:
model = &op_model_7450;
break;
diff --git a/arch/powerpc/oprofile/op_model_7450.c b/arch/powerpc/oprofile/op_model_7450.c
index d8ee3ae..f481c0e 100644
--- a/arch/powerpc/oprofile/op_model_7450.c
+++ b/arch/powerpc/oprofile/op_model_7450.c
@@ -81,7 +81,7 @@ static void pmc_stop_ctrs(void)
/* Configures the counters on this CPU based on the global
* settings */
-static void fsl7450_cpu_setup(void *unused)
+static void fsl7450_cpu_setup(struct op_counter_config *ctr)
{
/* freeze all counters */
pmc_stop_ctrs();
diff --git a/arch/powerpc/oprofile/op_model_fsl_booke.c b/arch/powerpc/oprofile/op_model_fsl_booke.c
index e29dede..0b3c31f 100644
--- a/arch/powerpc/oprofile/op_model_fsl_booke.c
+++ b/arch/powerpc/oprofile/op_model_fsl_booke.c
@@ -32,42 +32,152 @@ static unsigned long reset_value[OP_MAX_
static int num_counters;
static int oprofile_running;
-static inline unsigned int ctr_read(unsigned int i)
+static void init_pmc_stop(int ctr)
{
- switch(i) {
- case 0:
- return mfpmr(PMRN_PMC0);
- case 1:
- return mfpmr(PMRN_PMC1);
- case 2:
- return mfpmr(PMRN_PMC2);
- case 3:
- return mfpmr(PMRN_PMC3);
- default:
- return 0;
- }
-}
+ u32 pmlca = (PMLCA_FC | PMLCA_FCS | PMLCA_FCU |
+ PMLCA_FCM1 | PMLCA_FCM0);
+ u32 pmlcb = 0;
-static inline void ctr_write(unsigned int i, unsigned int val)
-{
- switch(i) {
+ switch (ctr) {
case 0:
- mtpmr(PMRN_PMC0, val);
+ mtpmr(PMRN_PMLCA0, pmlca);
+ mtpmr(PMRN_PMLCB0, pmlcb);
break;
case 1:
- mtpmr(PMRN_PMC1, val);
+ mtpmr(PMRN_PMLCA1, pmlca);
+ mtpmr(PMRN_PMLCB1, pmlcb);
break;
case 2:
- mtpmr(PMRN_PMC2, val);
+ mtpmr(PMRN_PMLCA2, pmlca);
+ mtpmr(PMRN_PMLCB2, pmlcb);
break;
case 3:
- mtpmr(PMRN_PMC3, val);
+ mtpmr(PMRN_PMLCA3, pmlca);
+ mtpmr(PMRN_PMLCB3, pmlcb);
break;
default:
- break;
+ panic("Bad ctr number!\n");
}
}
+static void set_pmc_event(int ctr, int event)
+{
+ u32 pmlca;
+
+ pmlca = get_pmlca(ctr);
+
+ pmlca = (pmlca & ~PMLCA_EVENT_MASK) |
+ ((event << PMLCA_EVENT_SHIFT) &
+ PMLCA_EVENT_MASK);
+
+ set_pmlca(ctr, pmlca);
+}
+
+static void set_pmc_user_kernel(int ctr, int user, int kernel)
+{
+ u32 pmlca;
+
+ pmlca = get_pmlca(ctr);
+
+ if(user)
+ pmlca &= ~PMLCA_FCU;
+ else
+ pmlca |= PMLCA_FCU;
+
+ if(kernel)
+ pmlca &= ~PMLCA_FCS;
+ else
+ pmlca |= PMLCA_FCS;
+
+ set_pmlca(ctr, pmlca);
+}
+
+static void set_pmc_marked(int ctr, int mark0, int mark1)
+{
+ u32 pmlca = get_pmlca(ctr);
+
+ if(mark0)
+ pmlca &= ~PMLCA_FCM0;
+ else
+ pmlca |= PMLCA_FCM0;
+
+ if(mark1)
+ pmlca &= ~PMLCA_FCM1;
+ else
+ pmlca |= PMLCA_FCM1;
+
+ set_pmlca(ctr, pmlca);
+}
+
+static void pmc_start_ctr(int ctr, int enable)
+{
+ u32 pmlca = get_pmlca(ctr);
+
+ pmlca &= ~PMLCA_FC;
+
+ if (enable)
+ pmlca |= PMLCA_CE;
+ else
+ pmlca &= ~PMLCA_CE;
+
+ set_pmlca(ctr, pmlca);
+}
+
+static void pmc_start_ctrs(int enable)
+{
+ u32 pmgc0 = mfpmr(PMRN_PMGC0);
+
+ pmgc0 &= ~PMGC0_FAC;
+ pmgc0 |= PMGC0_FCECE;
+
+ if (enable)
+ pmgc0 |= PMGC0_PMIE;
+ else
+ pmgc0 &= ~PMGC0_PMIE;
+
+ mtpmr(PMRN_PMGC0, pmgc0);
+}
+
+static void pmc_stop_ctrs(void)
+{
+ u32 pmgc0 = mfpmr(PMRN_PMGC0);
+
+ pmgc0 |= PMGC0_FAC;
+
+ pmgc0 &= ~(PMGC0_PMIE | PMGC0_FCECE);
+
+ mtpmr(PMRN_PMGC0, pmgc0);
+}
+
+static void dump_pmcs(void)
+{
+ printk("pmgc0: %x\n", mfpmr(PMRN_PMGC0));
+ printk("pmc\t\tpmlca\t\tpmlcb\n");
+ printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC0),
+ mfpmr(PMRN_PMLCA0), mfpmr(PMRN_PMLCB0));
+ printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC1),
+ mfpmr(PMRN_PMLCA1), mfpmr(PMRN_PMLCB1));
+ printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC2),
+ mfpmr(PMRN_PMLCA2), mfpmr(PMRN_PMLCB2));
+ printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC3),
+ mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3));
+}
+
+static void fsl_booke_cpu_setup(struct op_counter_config *ctr)
+{
+ int i;
+
+ /* freeze all counters */
+ pmc_stop_ctrs();
+
+ for (i = 0;i < num_counters;i++) {
+ init_pmc_stop(i);
+
+ set_pmc_event(i, ctr[i].event);
+
+ set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
+ }
+}
static void fsl_booke_reg_setup(struct op_counter_config *ctr,
struct op_system_config *sys,
@@ -77,23 +187,14 @@ static void fsl_booke_reg_setup(struct o
num_counters = num_ctrs;
- /* freeze all counters */
- pmc_stop_ctrs();
-
/* Our counters count up, and "count" refers to
* how much before the next interrupt, and we interrupt
* on overflow. So we calculate the starting value
* which will give us "count" until overflow.
* Then we set the events on the enabled counters */
- for (i = 0; i < num_counters; ++i) {
+ for (i = 0; i < num_counters; ++i)
reset_value[i] = 0x80000000UL - ctr[i].count;
- init_pmc_stop(i);
-
- set_pmc_event(i, ctr[i].event);
-
- set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
- }
}
static void fsl_booke_start(struct op_counter_config *ctr)
@@ -105,8 +206,8 @@ static void fsl_booke_start(struct op_co
for (i = 0; i < num_counters; ++i) {
if (ctr[i].enabled) {
ctr_write(i, reset_value[i]);
- /* Set Each enabled counterd to only
- * count when the Mark bit is not set */
+ /* Set each enabled counter to only
+ * count when the Mark bit is *not* set */
set_pmc_marked(i, 1, 0);
pmc_start_ctr(i, 1);
} else {
@@ -177,6 +278,7 @@ static void fsl_booke_handle_interrupt(s
struct op_powerpc_model op_model_fsl_booke = {
.reg_setup = fsl_booke_reg_setup,
+ .cpu_setup = fsl_booke_cpu_setup,
.start = fsl_booke_start,
.stop = fsl_booke_stop,
.handle_interrupt = fsl_booke_handle_interrupt,
diff --git a/arch/powerpc/oprofile/op_model_power4.c b/arch/powerpc/oprofile/op_model_power4.c
index 6a927ef..356709d 100644
--- a/arch/powerpc/oprofile/op_model_power4.c
+++ b/arch/powerpc/oprofile/op_model_power4.c
@@ -82,7 +82,7 @@ static inline int mmcra_must_set_sample(
return 0;
}
-static void power4_cpu_setup(void *unused)
+static void power4_cpu_setup(struct op_counter_config *ctr)
{
unsigned int mmcr0 = mmcr0_val;
unsigned long mmcra = mmcra_val;
diff --git a/arch/powerpc/oprofile/op_model_rs64.c b/arch/powerpc/oprofile/op_model_rs64.c
index 042f8f4..19c5ee0 100644
--- a/arch/powerpc/oprofile/op_model_rs64.c
+++ b/arch/powerpc/oprofile/op_model_rs64.c
@@ -102,7 +102,7 @@ static void rs64_reg_setup(struct op_cou
/* XXX setup user and kernel profiling */
}
-static void rs64_cpu_setup(void *unused)
+static void rs64_cpu_setup(struct op_counter_config *ctr)
{
unsigned int mmcr0;
diff --git a/include/asm-powerpc/oprofile_impl.h b/include/asm-powerpc/oprofile_impl.h
index 5b33994..07a10e5 100644
--- a/include/asm-powerpc/oprofile_impl.h
+++ b/include/asm-powerpc/oprofile_impl.h
@@ -42,7 +42,7 @@ struct op_powerpc_model {
void (*reg_setup) (struct op_counter_config *,
struct op_system_config *,
int num_counters);
- void (*cpu_setup) (void *);
+ void (*cpu_setup) (struct op_counter_config *);
void (*start) (struct op_counter_config *);
void (*stop) (void);
void (*handle_interrupt) (struct pt_regs *,
@@ -121,7 +121,90 @@ #endif
break;
}
}
-#endif /* !CONFIG_FSL_BOOKE */
+#else /* CONFIG_FSL_BOOKE */
+static inline u32 get_pmlca(int ctr)
+{
+ u32 pmlca;
+
+ switch (ctr) {
+ case 0:
+ pmlca = mfpmr(PMRN_PMLCA0);
+ break;
+ case 1:
+ pmlca = mfpmr(PMRN_PMLCA1);
+ break;
+ case 2:
+ pmlca = mfpmr(PMRN_PMLCA2);
+ break;
+ case 3:
+ pmlca = mfpmr(PMRN_PMLCA3);
+ break;
+ default:
+ panic("Bad ctr number\n");
+ }
+
+ return pmlca;
+}
+
+static inline void set_pmlca(int ctr, u32 pmlca)
+{
+ switch (ctr) {
+ case 0:
+ mtpmr(PMRN_PMLCA0, pmlca);
+ break;
+ case 1:
+ mtpmr(PMRN_PMLCA1, pmlca);
+ break;
+ case 2:
+ mtpmr(PMRN_PMLCA2, pmlca);
+ break;
+ case 3:
+ mtpmr(PMRN_PMLCA3, pmlca);
+ break;
+ default:
+ panic("Bad ctr number\n");
+ }
+}
+
+static inline unsigned int ctr_read(unsigned int i)
+{
+ switch(i) {
+ case 0:
+ return mfpmr(PMRN_PMC0);
+ case 1:
+ return mfpmr(PMRN_PMC1);
+ case 2:
+ return mfpmr(PMRN_PMC2);
+ case 3:
+ return mfpmr(PMRN_PMC3);
+ default:
+ return 0;
+ }
+}
+
+static inline void ctr_write(unsigned int i, unsigned int val)
+{
+ switch(i) {
+ case 0:
+ mtpmr(PMRN_PMC0, val);
+ break;
+ case 1:
+ mtpmr(PMRN_PMC1, val);
+ break;
+ case 2:
+ mtpmr(PMRN_PMC2, val);
+ break;
+ case 3:
+ mtpmr(PMRN_PMC3, val);
+ break;
+ default:
+ break;
+ }
+}
+
+
+#endif /* CONFIG_FSL_BOOKE */
+
extern void op_powerpc_backtrace(struct pt_regs * const regs, unsigned int depth);
diff --git a/include/asm-powerpc/pmc.h b/include/asm-powerpc/pmc.h
index 07d6a42..8588be6 100644
--- a/include/asm-powerpc/pmc.h
+++ b/include/asm-powerpc/pmc.h
@@ -32,18 +32,5 @@ #ifdef CONFIG_PPC64
void power4_enable_pmcs(void);
#endif
-#ifdef CONFIG_FSL_BOOKE
-void init_pmc_stop(int ctr);
-void set_pmc_event(int ctr, int event);
-void set_pmc_user_kernel(int ctr, int user, int kernel);
-void set_pmc_marked(int ctr, int mark0, int mark1);
-void pmc_start_ctr(int ctr, int enable);
-void pmc_start_ctrs(int enable);
-void pmc_stop_ctrs(void);
-void dump_pmcs(void);
-
-extern struct op_powerpc_model op_model_fsl_booke;
-#endif
-
#endif /* __KERNEL__ */
#endif /* _POWERPC_PMC_H */
--
1.4.2.3
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