* Re: minor progress with plb_temac v3.00a, EDK 8.2, & 2.6.18.1
From: robert corley @ 2006-11-07 18:37 UTC (permalink / raw)
To: Pradeep Sampath; +Cc: linux linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 13853 bytes --]
Pradeep;
I found the process of "uprading" the xapp902 reference design to be troublesome when I removed the GMII loop-back; as
such, I aborted the process and just started from scratch.
I am currently debugging my design and have a functional plb_temac but only at 10Mbps speeds.
-R. Corley
----- Original Message ----
From: Pradeep Sampath <pradeepsampath@yahoo.com>
To: David H. Lynch Jr. <dhlii@dlasys.net>; robert corley <rdcorle@yahoo.com>
Cc: linux linuxppc-embedded <linuxppc-embedded@ozlabs.org>
Sent: Tuesday, November 7, 2006 1:05:08 PM
Subject: Re: minor progress with plb_temac v3.00a, EDK 8.2, & 2.6.18.1
Hello,
I was able to get the booting with a ramdisk working and also David B./Peter's uartlite patches to work. Now I see the linux command line without any kernel panics. Thanks to everybody out there.
Next step is to get the PLB TEMAC 3.00.a working...
Question 1: I have started with the xapp902 reference design. I replaced the existing plb_temac_0 and hard_temac_0 instances with the plb_temac_0 (version 3.00.a) and hard_temac_0 (version 3.00.b). When I "generate libraries and BSP" I get the following error.
ERROR:MDT - intc () - Internal error: Number of interrupt inputs on opb_intc_0
(1) is not the same as length of total number of interrupt sources (2). If
any interrupt source is a vector then libgen does not support this use case
while
executing
"error "Internal error: Number of interrupt inputs on $periph_name
($num_intr_inputs) is not the same as length of total number of interrupt.....
.....
ARG: C_PHY_TYPE VALUE: 1
ERROR:MDT - Error while running "generate" for processor ppc405_0...
Or is it better to generate the EDK design from start rather than using the reference design?
Question 2: For the adapter.c for TEMAC, I am using the C:\EDK\sw\ThirdParty\bsp\linux_2_6_v1_00_a\drivers\temac_linux_2_6_v2_00_b\src\adapter.c as indicated by Rick Moleres. Can I use it as is or it requires further tweaking? If yes, then what are the changes.
Question 3: Are the files under linux\arch\ppc\platforms\xilinx_ocp required? I thought the files in ../drivers/xilinx_edk => should take care of all the dma stuff?
Could someone provide
some insight into all these questions?
-Pradeep
"David H. Lynch Jr." <dhlii@dlasys.net> wrote:
robert corley wrote: Pradeep;
Booting with a ramdisk is a matter of putting the appropriate image in the arch/ppc/boot/images directory (I obtained mine from the gsrd design files), adding the root=/dev/ram rw on the command-line boot options, making the .config changes for ram disk support and initrd usage, and issuing a make zImage.initrd command.
Beware when upgrading to 2.6.18.1 as
you may have difficulties with the adapter.c you obtained previously. The adapter.c in EDK 8.2 is not as easy to find. Using the EDK to generate software components for linux will not expose the proper adapter.c. I had to use the path that Rick Moleres posted earlier to retrieve the adapter.c which I used for 2.6.18.1 and in my notes.
-cy
I am booting with a ramdisk using initramfs. Aside from its being somewhat harder to find documentation I beleive it is actually easier.
In the simplest form, create a directory on your host that contains exactly what you want on the ramdisk.
Enable CONFIG_INITRAMFS
and point the CONFIG_INITRAMFS_SOURCE to that directory.
It is pretty much that simple. The linux build process creates a kernel - I use zImage.elf that has the ramdisk compressed
and concatentated.
Nothing except the Linux kernel itself has to make any accomidations for the ramdisk. The bootloader does not have to deal with another file, or pass pointers to it to Linux, ....
It took some time to get it working - mostly because I did nto know what I was doing, but in hindsight it is really easy.
----- Original Message ----
From: Pradeep Sampath <pradeepsampath@yahoo.com>
To: robert corley <rdcorle@yahoo.com>
Sent: Thursday, November 2, 2006 7:57:25 PM
Subject: Re: minor progress with plb_temac v3.00a, EDK 8.2, & 2.6.18.1
This is great! I played around for a while with the Sysace CF driver patches and got it to work. Since you are booting with ramdisk image would you be kind enough to add more text on how to do that? I see that you are using UART Lite? Does it require any special setting for the boot logs to show up on the standard hyperterminal.
I am planning on rebuilding the whole system using EDK 8.2 and linux kernel 2.6.18.1.
-Pradeep
robert corley <rdcorle@yahoo.com> wrote:
For those interested, I have
acheived some measure of success with the plb_temac driver.
I have attached a txt file of what I had to do to get it working under 2.6.18.1
I am using the plb_temac in DMA mode 3
Below you will see the boot dump.
For those able to help, can anyone provide insight as to the failure of setting PHY link speed?
-cy
====================
----------------------------------------------------------------------
2.6.18.1 kernel with all patches
11/02/2006 15:30
plb_temac v3.00a
hard_temac v3.00b
loaded at: 00400000 009F1138
board data at: 009EF120 009EF138
relocated to: 004040B4 004040CC
zimage at: 00404EC7 0057C1F2
initrd at: 0057D000 009EE6FE
avail ram: 009F2000 04000000
Linux/PPC load: console=ttyUL0 single ip=192.168.1.100:192.168.1.144:192.168.1.1:255.255.255.0:nab:: ramdisk_size=4660000 root=/dev/ram rw
Uncompressing Linux...done.
Now booting the kernel
[
0.000000] Linux version 2.6.18.1 (rdcorle@athena) (gcc version 3.4.2) #2 Thu Nov 2 21:56:32 UTC 2006
[ 0.000000] Xilinx ML403 Reference System (Virtex-4 FX)
[ 0.000000] Built 1 zonelists. Total pages: 16384
[ 0.000000] Kernel command line: console=ttyUL0 single ip=192.168.1.100:192.168.1.144:192.168.1.1:255.255.255.0:nab:: ramdisk_size=4660000 root=/dev/ram rw
[ 0.000000] Xilinx INTC #0 at 0xD1000FC0 mapped to 0xFDFFFFC0
[ 0.000000] PID hash table entries: 512 (order: 9, 2048 bytes)
[ 0.000158] Console: colour dummy device 80x25
[ 0.000568] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.001277] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.012895] Memory: 57060k available (2548k kernel code, 640k data, 96k init, 0k highmem)
[ 0.104378] Mount-cache hash table entries: 512
[ 0.106721] checking if image is initramfs...it isn't (no cpio magic); looks like an initrd
[ 2.414242] Freeing initrd memory:
4549k freed
[ 2.418712] NET: Registered protocol family 16
[ 2.427313] NET: Registered protocol family 2
[ 2.464244] IP route cache hash table entries: 512 (order: -1, 2048 bytes)
[ 2.465037] TCP established hash table entries: 2048 (order: 1, 8192 bytes)
[ 2.465205] TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
[ 2.465296] TCP: Hash tables configured (established 2048 bind 1024)
[ 2.465324] TCP reno registered
[ 2.474633] NTFS driver 2.1.27 [Flags: R/O].
[ 2.475046] JFS: nTxBlock = 481, nTxLock = 3854
[ 2.477623] SGI XFS with no debug enabled
[ 2.479001] io scheduler noop registered
[ 2.479109] io scheduler anticipatory registered
[ 2.479197] io scheduler deadline registered
[ 2.479402] io scheduler cfq registered (default)
[ 2.517627] uartlite.0: ttyUL0 at MMIO 0xa0000000 (irq = 1) is a uartlite
[ 2.691029] RAMDISK driver initialized: 16 RAM disks of 4660000K size 1024 blocksize
[ 2.703933] loop: loaded (max 8
devices)
[ 2.709698] XTemac: using sgDMA mode.
[ 2.713493] XTemac: using TxDRE mode
[ 2.717081] XTemac: using RxDRE mode
[ 2.720678] XTemac: buffer descriptor size: 32768 (0x8000)
[ 2.726622] XTemac: (buffer_descriptor_init) phy: 0x580000, virt: 0xff100000, size: 0x8000
[ 2.741073] eth0: Xilinx TEMAC #0 at 0x60000000 mapped to 0xC5050000, irq=0
[ 2.748080] eth0: XTemac id 1.0f, block id 5, type 8
[ 2.753636] mice: PS/2 mouse device common for all mice
[ 2.759529] TCP bic registered
[ 3.264317] eth0: XTemac: Options: 0xb8f2
[ 15.227339] eth0: XTemac: Not able to set the speed to 1000 (status: 0x148)
[ 25.200394] eth0: XTemac: Not able to set the speed to 100 (status: 0x148)
[ 35.173357] eth0: XTemac: Not able to set the speed to 10 (status: 0x148)
[ 35.180122] eth0: XTemac: could not negotiate speed
[ 35.187740] eth0: XTemac: Send Threshold = 16, Receive Threshold = 2
[ 35.194116] eth0: XTemac: Send Wait bound = 1, Receive
Wait bound = 1
[ 36.205399] IP-Config: Complete:
[ 36.208459] device=eth0, addr=192.168.1.100, mask=255.255.255.0, gw=192.168.1.1,
[ 36.216339] host=nab, domain=, nis-domain=(none),
[ 36.221487] bootserver=192.168.1.144, rootserver=192.168.1.144, rootpath=
[ 36.229826] RAMDISK: Compressed image found at block 0
[ 37.200498] eth0: XTemac: PHY Link carrier lost.
[ 39.097820] VFS: Mounted root (ext2 filesystem).
[ 39.102751] Freeing unused kernel memory: 96k init
[ 39.108356] ulite_startup: UART status = 0x0014
[ 39.124619] ulite_startup: UART status = 0x0014
[ 39.134313] ulite_startup: UART status = 0x0014
BusyBox v1.00-pre9 (2004.04.18-19:53+0000) Built-in shell (ash)
Enter 'help' for a list of built-in commands.
-sh: can't access tty; job control turned off
steps for plb_temac drivers under EDK 8.2.02i (w/SP2.4+0)
Using plb_temac v3.00a & hard_temac v3.00b
Generate s/w libraries
1. copy
or ftp the following files from C:\EDK\sw\ThirdParty\bsp\linux_2_6_v1_00_a\linux\
to the base directory of the linux source tree
USED:
arch\ppc\platforms\4xx\xparameters\xparameters.h
** UNUSED
arch\ppc\platforms\4xx\virtex.c
arch\ppc\boot\simple\embed_config.c
include\linux\xilinx_devices.h
2. copy C:\EDK\sw\ThirdParty\bsp\linux_2_6_v1_00_a\drivers\temac_linux_2_6_v2_00_b\src\adapter.c to
../drivers/net/xilinx_temac/adapter.c
3. copy or ftp ..\linux\arch\ppc\platforms\xilinx_ocp => drivers/xilinx_edk
Note: Remove all old files first *except* Kconfig, xio.h
4. modify drivers/xilinx_edk/Makefile with the following to look like this:
# Linux file to EXPORT_SYMBOL all of the Xilinx entries.
obj-$(CONFIG_XILINX_EDK) += xilinx_syms.o
#
# # The Xilinx OS independent code.
xilinx_syms-objs := xbasic_types.o \
xdmav3.o xdmav3_intr.o xdmav3_selftest.o xdmav3_simple.o xdmav3_sg.o \
xipif_v1_23_b.o
\
xpacket_fifo_l_v2_00_a.o xpacket_fifo_v2_00_a.o \
xversion.o
5. Modify your copied xparameters_ml403.h (see notes below) as follows:
add these lines after #define XPAR_PLB_TEMAC_0_INCLUDE_RX_CSUM
#define XPAR_TEMAC_0_IPIF_RDFIFO_DEPTH XPAR_PLB_TEMAC_0_RXFIFO_DEPTH
#define XPAR_TEMAC_0_IPIF_WRFIFO_DEPTH XPAR_PLB_TEMAC_0_TXFIFO_DEPTH
#define XPAR_TEMAC_0_MAC_FIFO_DEPTH XPAR_PLB_TEMAC_0_MAC_FIFO_DEPTH
#define XPAR_TEMAC_0_TEMAC_DCR_HOST 0
#define XPAR_TEMAC_0_INCLUDE_DRE 1
6. (optional) modify arch/ppc/platforms/virtex.h to accomodate RX_CSUM XPAR
struct xtemac_platform_data {
#ifdef XPAR_TEMAC_0_INCLUDE_RX_CSUM
u8 tx_dre;
u8 rx_dre;
u8 tx_csum;
u8 rx_csum;
u8 phy_type;
#endif
u8 dma_mode;
u32 rx_pkt_fifo_depth;
u32 tx_pkt_fifo_depth;
u16 mac_fifo_depth;
u8 dcr_host;
u8 dre;
u8 mac_addr[6];
};
7. Modify ../drivers/net/xilinx_temac/adapter.c to remove #include and
add
#include
add #include
____________________________________________________________________________________
NOTES:
1. Don't forget to copy EDK-generated xparameters.h to ../arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
=====================================================
Files in latest patch:
../drivers/net/xilinx_temac =
Makefile
adapter.c
xtemac.c
xtemac_control.c
xtemac_fifo.c
xtemac_intr.c
xtemac_intr_fifo.c
xtemac_intr_sgdma.c
xtemac_l.c
xtemac_sgdma.c
xtemac.h
xtemac_i.h
xtemac_l.h
Files in ..\linux\drivers\net\xilinx_temac => (** = new
files)
Makefile
adapter.c
xtemac.c
xtemac_control.c
xtemac_fifo.c
xtemac_g.c**
xtemac_intr.c
xtemac_intr_fifo.c
xtemac_intr_sgdma.c
xtemac_l.c
xtemac_selftest.c**
xtemac_sgdma.c
xtemac_sinit.c**
xtemac_stats.c**
xtemac.h
xtemac_i.h
xtemac_l.h
============================================================
Files in ../drivers/xilinx_edk =>
Kconfig
Makefile
xbasic_types.c
xdmav2.c
xdmav2_intr.c
xdmav2_sg.c
xdmav2_simple.c
xilinx_syms.c
xpacket_fifo_l_v2_00_a.c
xpacket_fifo_v2_00_a.c
xbasic_types.h
xdmabdv2.h
xdmav2.h
xdmav2_l.h
xio.h
xpacket_fifo_l_v2_00_a.h
xpacket_fifo_v2_00_a.h
xstatus.h
Files in
..\linux\arch\ppc\platforms\xilinx_ocp=>
Makefile
xbasic_types.c
xutil_memtest.c
xpacket_fifo_v2_00_a.c
xdmav3.c
xpacket_fifo_l_v2_00_a.c
xdmav3_intr.c
xipif_v1_23_b.c
xdmav3_selftest.c
xdmav3_sg.c
xdmav3_simple.c
xversion.c
xenv.h
xenv_none.h
xenv_vxworks.h
xdmav3_l.h
xipif_v1_23_b.h
xdmav3.h
xpacket_fifo_l_v2_00_a.h
xdmabdv3.h
xpacket_fifo_v2_00_a.h
xparameters_ml300.h
xstatus.h
xutil.h
xbasic_types.h
xenv_linux.h
xversion.h
_______________________________________________
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
_______________________________________________ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
-- Dave Lynch DLA Systems Software Development: Embedded Linux 717.627.3770 dhlii@dlasys.net http://www.dlasys.net fax: 1.253.369.9244 Cell: 1.717.587.7774 Over 25 years' experience in platforms, languages, and technologies too numerous to list. "Any intelligent fool can make things bigger and more complex... It takes a touch of genius - and a lot of courage to move in the opposite
direction." Albert Einstein
[-- Attachment #2: Type: text/html, Size: 17307 bytes --]
^ permalink raw reply
* Re: [PATCH] adding ROM chips to device tree
From: Sergei Shtylyov @ 2006-11-07 18:29 UTC (permalink / raw)
To: Josh Boyer, Vitaly Wool; +Cc: linuxppc-embedded
In-Reply-To: <454A4266.8040505@ru.mvista.com>
Sergei Shtylyov wrote:
> Hello.
>
> Josh Boyer wrote:
>
>
>>>+
>>>+ Required properties:
>>>+
>>>+ - device_type : has to be "rom"
>>Why "rom" instead of "NOR"?
> What does "NOR" mean -- logical operator? :-)
> I'd yet agree with "nor-flash", however, the physmap-driven device may not
> always be writeable, IIUC...
Hence an idea: maybe we need to introduce the "writeable" property (just a
logical value, i.e. absent/resent)?
>>>+ - compatible : Should be the name of the MTD driver. Currently, this is
>>>+ most likely to be "physmap".
>>>+ - reg : Offset and length of the register set for the device.
>>reg doesn't really describe a register set here. It's the overall
>>memory space for flash.
Since "reg" property is the way for device to claim its I/O resources, it
must be used to describe the decoded memory range, I think. Maybe I should
have added a comment about its meaning for direct mapped devices in the first
place...
> This is no more a standard boilerplate, if you look at this file.
No more than a boilerplate, I meant to say.
WBR, Sergei
^ permalink raw reply
* Re: build problems with powerpc allmodconfig
From: Judith Lebzelter @ 2006-11-07 18:09 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev
>> - vioscsi linkage fails because iseries_vscsi.c and rpa_vscsi.c.
>> This needs some trivial indirection via function vectors, but
>> how can we find out which one to use from the driver? Both
>> seem to look the same in the device tree
>
> The maintainer suggested that we just don't build vioscsi for iseries
> if we are building the rpa version as it is not often used (in particular,
> it is not used for installations). We could, however distinguish them
> by changing the "compat" field in the iSeries device tree if we wished.
>
How about just adding an 'ifndef' in the Makefile, as in the patch below?
This compiles ibmvscsic.o fine.
Judith Lebzelter
---
Index: linux/drivers/scsi/ibmvscsi/Makefile
===================================================================
--- linux.orig/drivers/scsi/ibmvscsi/Makefile 2006-11-06 16:52:09.000000000 -0800
+++ linux/drivers/scsi/ibmvscsi/Makefile 2006-11-07 09:35:34.019969437 -0800
@@ -1,7 +1,9 @@
obj-$(CONFIG_SCSI_IBMVSCSI) += ibmvscsic.o
ibmvscsic-y += ibmvscsi.o
+ifndef CONFIG_PPC_PSERIES
ibmvscsic-$(CONFIG_PPC_ISERIES) += iseries_vscsi.o
+endif
ibmvscsic-$(CONFIG_PPC_PSERIES) += rpa_vscsi.o
obj-$(CONFIG_SCSI_IBMVSCSIS) += ibmvstgt.o
^ permalink raw reply
* Re: minor progress with plb_temac v3.00a, EDK 8.2, & 2.6.18.1
From: Pradeep Sampath @ 2006-11-07 18:05 UTC (permalink / raw)
To: David H. Lynch Jr., robert corley; +Cc: linux linuxppc-embedded
In-Reply-To: <454D203D.4060908@dlasys.net>
[-- Attachment #1: Type: text/plain, Size: 12878 bytes --]
Hello,
I was able to get the booting with a ramdisk working and also David B./Peter's uartlite patches to work. Now I see the linux command line without any kernel panics. Thanks to everybody out there.
Next step is to get the PLB TEMAC 3.00.a working...
Question 1: I have started with the xapp902 reference design. I replaced the existing plb_temac_0 and hard_temac_0 instances with the plb_temac_0 (version 3.00.a) and hard_temac_0 (version 3.00.b). When I "generate libraries and BSP" I get the following error.
ERROR:MDT - intc () - Internal error: Number of interrupt inputs on opb_intc_0
(1) is not the same as length of total number of interrupt sources (2). If
any interrupt source is a vector then libgen does not support this use case
while executing
"error "Internal error: Number of interrupt inputs on $periph_name
($num_intr_inputs) is not the same as length of total number of interrupt.....
.....
ARG: C_PHY_TYPE VALUE: 1
ERROR:MDT - Error while running "generate" for processor ppc405_0...
Or is it better to generate the EDK design from start rather than using the reference design?
Question 2: For the adapter.c for TEMAC, I am using the C:\EDK\sw\ThirdParty\bsp\linux_2_6_v1_00_a\drivers\temac_linux_2_6_v2_00_b\src\adapter.c as indicated by Rick Moleres. Can I use it as is or it requires further tweaking? If yes, then what are the changes.
Question 3: Are the files under linux\arch\ppc\platforms\xilinx_ocp required? I thought the files in ../drivers/xilinx_edk => should take care of all the dma stuff?
Could someone provide some insight into all these questions?
-Pradeep
"David H. Lynch Jr." <dhlii@dlasys.net> wrote:
robert corley wrote: Pradeep;
Booting with a ramdisk is a matter of putting the appropriate image in the arch/ppc/boot/images directory (I obtained mine from the gsrd design files), adding the root=/dev/ram rw on the command-line boot options, making the .config changes for ram disk support and initrd usage, and issuing a make zImage.initrd command.
Beware when upgrading to 2.6.18.1 as you may have difficulties with the adapter.c you obtained previously. The adapter.c in EDK 8.2 is not as easy to find. Using the EDK to generate software components for linux will not expose the proper adapter.c. I had to use the path that Rick Moleres posted earlier to retrieve the adapter.c which I used for 2.6.18.1 and in my notes.
-cy
I am booting with a ramdisk using initramfs. Aside from its being somewhat harder to find documentation I beleive it is actually easier.
In the simplest form, create a directory on your host that contains exactly what you want on the ramdisk.
Enable CONFIG_INITRAMFS
and point the CONFIG_INITRAMFS_SOURCE to that directory.
It is pretty much that simple. The linux build process creates a kernel - I use zImage.elf that has the ramdisk compressed and concatentated.
Nothing except the Linux kernel itself has to make any accomidations for the ramdisk. The bootloader does not have to deal with another file, or pass pointers to it to Linux, ....
It took some time to get it working - mostly because I did nto know what I was doing, but in hindsight it is really easy.
----- Original Message ----
From: Pradeep Sampath <pradeepsampath@yahoo.com>
To: robert corley <rdcorle@yahoo.com>
Sent: Thursday, November 2, 2006 7:57:25 PM
Subject: Re: minor progress with plb_temac v3.00a, EDK 8.2, & 2.6.18.1
This is great! I played around for a while with the Sysace CF driver patches and got it to work. Since you are booting with ramdisk image would you be kind enough to add more text on how to do that? I see that you are using UART Lite? Does it require any special setting for the boot logs to show up on the standard hyperterminal.
I am planning on rebuilding the whole system using EDK 8.2 and linux kernel 2.6.18.1.
-Pradeep
robert corley <rdcorle@yahoo.com> wrote:
For those interested, I have acheived some measure of success with the plb_temac driver.
I have attached a txt file of what I had to do to get it working under 2.6.18.1
I am using the plb_temac in DMA mode 3
Below you will see the boot dump.
For those able to help, can anyone provide insight as to the failure of setting PHY link speed?
-cy
====================
----------------------------------------------------------------------
2.6.18.1 kernel with all patches
11/02/2006 15:30
plb_temac v3.00a
hard_temac v3.00b
loaded at: 00400000 009F1138
board data at: 009EF120 009EF138
relocated to: 004040B4 004040CC
zimage at: 00404EC7 0057C1F2
initrd at: 0057D000 009EE6FE
avail ram: 009F2000 04000000
Linux/PPC load: console=ttyUL0 single ip=192.168.1.100:192.168.1.144:192.168.1.1:255.255.255.0:nab:: ramdisk_size=4660000 root=/dev/ram rw
Uncompressing Linux...done.
Now booting the kernel
[ 0.000000] Linux version 2.6.18.1 (rdcorle@athena) (gcc version 3.4.2) #2 Thu Nov 2 21:56:32 UTC 2006
[ 0.000000] Xilinx ML403 Reference System (Virtex-4 FX)
[ 0.000000] Built 1 zonelists. Total pages: 16384
[ 0.000000] Kernel command line: console=ttyUL0 single ip=192.168.1.100:192.168.1.144:192.168.1.1:255.255.255.0:nab:: ramdisk_size=4660000 root=/dev/ram rw
[ 0.000000] Xilinx INTC #0 at 0xD1000FC0 mapped to 0xFDFFFFC0
[ 0.000000] PID hash table entries: 512 (order: 9, 2048 bytes)
[ 0.000158] Console: colour dummy device 80x25
[ 0.000568] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.001277] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.012895] Memory: 57060k available (2548k kernel code, 640k data, 96k init, 0k highmem)
[ 0.104378] Mount-cache hash table entries: 512
[ 0.106721] checking if image is initramfs...it isn't (no cpio magic); looks like an initrd
[ 2.414242] Freeing initrd memory: 4549k freed
[ 2.418712] NET: Registered protocol family 16
[ 2.427313] NET: Registered protocol family 2
[ 2.464244] IP route cache hash table entries: 512 (order: -1, 2048 bytes)
[ 2.465037] TCP established hash table entries: 2048 (order: 1, 8192 bytes)
[ 2.465205] TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
[ 2.465296] TCP: Hash tables configured (established 2048 bind 1024)
[ 2.465324] TCP reno registered
[ 2.474633] NTFS driver 2.1.27 [Flags: R/O].
[ 2.475046] JFS: nTxBlock = 481, nTxLock = 3854
[ 2.477623] SGI XFS with no debug enabled
[ 2.479001] io scheduler noop registered
[ 2.479109] io scheduler anticipatory registered
[ 2.479197] io scheduler deadline registered
[ 2.479402] io scheduler cfq registered (default)
[ 2.517627] uartlite.0: ttyUL0 at MMIO 0xa0000000 (irq = 1) is a uartlite
[ 2.691029] RAMDISK driver initialized: 16 RAM disks of 4660000K size 1024 blocksize
[ 2.703933] loop: loaded (max 8 devices)
[ 2.709698] XTemac: using sgDMA mode.
[ 2.713493] XTemac: using TxDRE mode
[ 2.717081] XTemac: using RxDRE mode
[ 2.720678] XTemac: buffer descriptor size: 32768 (0x8000)
[ 2.726622] XTemac: (buffer_descriptor_init) phy: 0x580000, virt: 0xff100000, size: 0x8000
[ 2.741073] eth0: Xilinx TEMAC #0 at 0x60000000 mapped to 0xC5050000, irq=0
[ 2.748080] eth0: XTemac id 1.0f, block id 5, type 8
[ 2.753636] mice: PS/2 mouse device common for all mice
[ 2.759529] TCP bic registered
[ 3.264317] eth0: XTemac: Options: 0xb8f2
[ 15.227339] eth0: XTemac: Not able to set the speed to 1000 (status: 0x148)
[ 25.200394] eth0: XTemac: Not able to set the speed to 100 (status: 0x148)
[ 35.173357] eth0: XTemac: Not able to set the speed to 10 (status: 0x148)
[ 35.180122] eth0: XTemac: could not negotiate speed
[ 35.187740] eth0: XTemac: Send Threshold = 16, Receive Threshold = 2
[ 35.194116] eth0: XTemac: Send Wait bound = 1, Receive Wait bound = 1
[ 36.205399] IP-Config: Complete:
[ 36.208459] device=eth0, addr=192.168.1.100, mask=255.255.255.0, gw=192.168.1.1,
[ 36.216339] host=nab, domain=, nis-domain=(none),
[ 36.221487] bootserver=192.168.1.144, rootserver=192.168.1.144, rootpath=
[ 36.229826] RAMDISK: Compressed image found at block 0
[ 37.200498] eth0: XTemac: PHY Link carrier lost.
[ 39.097820] VFS: Mounted root (ext2 filesystem).
[ 39.102751] Freeing unused kernel memory: 96k init
[ 39.108356] ulite_startup: UART status = 0x0014
[ 39.124619] ulite_startup: UART status = 0x0014
[ 39.134313] ulite_startup: UART status = 0x0014
BusyBox v1.00-pre9 (2004.04.18-19:53+0000) Built-in shell (ash)
Enter 'help' for a list of built-in commands.
-sh: can't access tty; job control turned off
steps for plb_temac drivers under EDK 8.2.02i (w/SP2.4+0)
Using plb_temac v3.00a & hard_temac v3.00b
Generate s/w libraries
1. copy or ftp the following files from C:\EDK\sw\ThirdParty\bsp\linux_2_6_v1_00_a\linux\
to the base directory of the linux source tree
USED:
arch\ppc\platforms\4xx\xparameters\xparameters.h
** UNUSED
arch\ppc\platforms\4xx\virtex.c
arch\ppc\boot\simple\embed_config.c
include\linux\xilinx_devices.h
2. copy C:\EDK\sw\ThirdParty\bsp\linux_2_6_v1_00_a\drivers\temac_linux_2_6_v2_00_b\src\adapter.c to
../drivers/net/xilinx_temac/adapter.c
3. copy or ftp ..\linux\arch\ppc\platforms\xilinx_ocp => drivers/xilinx_edk
Note: Remove all old files first *except* Kconfig, xio.h
4. modify drivers/xilinx_edk/Makefile with the following to look like this:
# Linux file to EXPORT_SYMBOL all of the Xilinx entries.
obj-$(CONFIG_XILINX_EDK) += xilinx_syms.o
#
# # The Xilinx OS independent code.
xilinx_syms-objs := xbasic_types.o \
xdmav3.o xdmav3_intr.o xdmav3_selftest.o xdmav3_simple.o xdmav3_sg.o \
xipif_v1_23_b.o \
xpacket_fifo_l_v2_00_a.o xpacket_fifo_v2_00_a.o \
xversion.o
5. Modify your copied xparameters_ml403.h (see notes below) as follows:
add these lines after #define XPAR_PLB_TEMAC_0_INCLUDE_RX_CSUM
#define XPAR_TEMAC_0_IPIF_RDFIFO_DEPTH XPAR_PLB_TEMAC_0_RXFIFO_DEPTH
#define XPAR_TEMAC_0_IPIF_WRFIFO_DEPTH XPAR_PLB_TEMAC_0_TXFIFO_DEPTH
#define XPAR_TEMAC_0_MAC_FIFO_DEPTH XPAR_PLB_TEMAC_0_MAC_FIFO_DEPTH
#define XPAR_TEMAC_0_TEMAC_DCR_HOST 0
#define XPAR_TEMAC_0_INCLUDE_DRE 1
6. (optional) modify arch/ppc/platforms/virtex.h to accomodate RX_CSUM XPAR
struct xtemac_platform_data {
#ifdef XPAR_TEMAC_0_INCLUDE_RX_CSUM
u8 tx_dre;
u8 rx_dre;
u8 tx_csum;
u8 rx_csum;
u8 phy_type;
#endif
u8 dma_mode;
u32 rx_pkt_fifo_depth;
u32 tx_pkt_fifo_depth;
u16 mac_fifo_depth;
u8 dcr_host;
u8 dre;
u8 mac_addr[6];
};
7. Modify ../drivers/net/xilinx_temac/adapter.c to remove #include and
add #include
add #include
____________________________________________________________________________________
NOTES:
1. Don't forget to copy EDK-generated xparameters.h to ../arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
=====================================================
Files in latest patch:
../drivers/net/xilinx_temac =
Makefile
adapter.c
xtemac.c
xtemac_control.c
xtemac_fifo.c
xtemac_intr.c
xtemac_intr_fifo.c
xtemac_intr_sgdma.c
xtemac_l.c
xtemac_sgdma.c
xtemac.h
xtemac_i.h
xtemac_l.h
Files in ..\linux\drivers\net\xilinx_temac => (** = new files)
Makefile
adapter.c
xtemac.c
xtemac_control.c
xtemac_fifo.c
xtemac_g.c**
xtemac_intr.c
xtemac_intr_fifo.c
xtemac_intr_sgdma.c
xtemac_l.c
xtemac_selftest.c**
xtemac_sgdma.c
xtemac_sinit.c**
xtemac_stats.c**
xtemac.h
xtemac_i.h
xtemac_l.h
============================================================
Files in ../drivers/xilinx_edk =>
Kconfig
Makefile
xbasic_types.c
xdmav2.c
xdmav2_intr.c
xdmav2_sg.c
xdmav2_simple.c
xilinx_syms.c
xpacket_fifo_l_v2_00_a.c
xpacket_fifo_v2_00_a.c
xbasic_types.h
xdmabdv2.h
xdmav2.h
xdmav2_l.h
xio.h
xpacket_fifo_l_v2_00_a.h
xpacket_fifo_v2_00_a.h
xstatus.h
Files in ..\linux\arch\ppc\platforms\xilinx_ocp=>
Makefile
xbasic_types.c
xutil_memtest.c
xpacket_fifo_v2_00_a.c
xdmav3.c
xpacket_fifo_l_v2_00_a.c
xdmav3_intr.c
xipif_v1_23_b.c
xdmav3_selftest.c
xdmav3_sg.c
xdmav3_simple.c
xversion.c
xenv.h
xenv_none.h
xenv_vxworks.h
xdmav3_l.h
xipif_v1_23_b.h
xdmav3.h
xpacket_fifo_l_v2_00_a.h
xdmabdv3.h
xpacket_fifo_v2_00_a.h
xparameters_ml300.h
xstatus.h
xutil.h
xbasic_types.h
xenv_linux.h
xversion.h
_______________________________________________
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
---------------------------------
_______________________________________________ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
-- Dave Lynch DLA Systems Software Development: Embedded Linux 717.627.3770 dhlii@dlasys.net http://www.dlasys.net fax: 1.253.369.9244 Cell: 1.717.587.7774 Over 25 years' experience in platforms, languages, and technologies too numerous to list. "Any intelligent fool can make things bigger and more complex... It takes a touch of genius - and a lot of courage to move in the opposite direction." Albert Einstein
[-- Attachment #2: Type: text/html, Size: 16131 bytes --]
^ permalink raw reply
* Re: [PATCH] powerpc: Add of_platform support for OHCI/Bigendian HC
From: Kumar Gala @ 2006-11-07 17:37 UTC (permalink / raw)
To: Sylvain Munaut; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <4550C31E.4080805@246tNt.com>
On Nov 7, 2006, at 11:32 AM, Sylvain Munaut wrote:
>
>>>>> This patch use of_platform device to probe and install OHCI big
>>>>> endian HC.
>>>>>
>>>>> PS: I did not success to properly inline the file using
>>>>> thrunderbird.
>>>>>
>>>>
>>>> You really copy the USB maintainers on this. Also, why bother with
>>>> the Kconfig for USB_OHCI_HCD_PPC_OF_BE/USB_OHCI_HCD_PPC_OF_LE?
>>>>
>>> I think it's a good idea to use those :
>>> - Just including both when PPC_OF is used is overkill because it
>>> makes
>>> all USB
>>> perform useless tests if you never intend to use the LE version for
>>> example.
>>> - Using the already defined symbol USB_OHCI_BIG_ENDIAN would force
>>> other ohci user to select BE/LE and they may not want to expose
>>> this.
>>
>> Maybe I'm missing something, but it looks like the _OF_LE & _OF_BE
>> are
>> just configuring what matches may occur. This seems like a one time
>> event.
>
> +
> +config USB_OHCI_HCD_PPC_OF_BE
> + bool "Support big endian HC"
> + depends on USB_OHCI_HCD_PPC_OF
> + default y
> + select USB_OHCI_BIG_ENDIAN
> +
> +config USB_OHCI_HCD_PPC_OF_LE
> + bool "Support little endian HC"
> + depends on USB_OHCI_HCD_PPC_OF
> + default n
> + select USB_OHCI_LITTLE_ENDIAN
>
> What's important is the USB_OHCI_BIG_ENDIAN and
> USB_OHCI_LITTLE_ENDIAN symbols that are selected when you choose
> these options.
> When both are active, each usb mmio access will test either to
> access in BE mode or LE mode. If only one is active, the test is
> hardcoded.
Missed that part. Now it makes sense.
- k
^ permalink raw reply
* Re: [PATCH] powerpc: Add of_platform support for OHCI/Bigendian HC
From: Sylvain Munaut @ 2006-11-07 17:32 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <754FECA8-A7B4-44FE-A08D-89019F9005A8@kernel.crashing.org>
>>>> This patch use of_platform device to probe and install OHCI big
>>>> endian HC.
>>>>
>>>> PS: I did not success to properly inline the file using thrunderbird.
>>>>
>>>
>>> You really copy the USB maintainers on this. Also, why bother with
>>> the Kconfig for USB_OHCI_HCD_PPC_OF_BE/USB_OHCI_HCD_PPC_OF_LE?
>>>
>> I think it's a good idea to use those :
>> - Just including both when PPC_OF is used is overkill because it makes
>> all USB
>> perform useless tests if you never intend to use the LE version for
>> example.
>> - Using the already defined symbol USB_OHCI_BIG_ENDIAN would force
>> other ohci user to select BE/LE and they may not want to expose this.
>
> Maybe I'm missing something, but it looks like the _OF_LE & _OF_BE are
> just configuring what matches may occur. This seems like a one time
> event.
+
+config USB_OHCI_HCD_PPC_OF_BE
+ bool "Support big endian HC"
+ depends on USB_OHCI_HCD_PPC_OF
+ default y
+ select USB_OHCI_BIG_ENDIAN
+
+config USB_OHCI_HCD_PPC_OF_LE
+ bool "Support little endian HC"
+ depends on USB_OHCI_HCD_PPC_OF
+ default n
+ select USB_OHCI_LITTLE_ENDIAN
What's important is the USB_OHCI_BIG_ENDIAN and USB_OHCI_LITTLE_ENDIAN symbols that are selected when you choose these options.
When both are active, each usb mmio access will test either to access in BE mode or LE mode. If only one is active, the test is hardcoded.
Sylvain
^ permalink raw reply
* Problem connecting a Ti TUSB2077a hub to Cypress SL811 host
From: Chaffin, Michael @ 2006-11-07 17:07 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: Mouw, Jamie, Newman, David
[-- Attachment #1: Type: text/plain, Size: 2949 bytes --]
I have a running 2.4.26 Linux kernel (penguinppc.org) on a commercial
built embedded PPC405 (Xilinx VirtexII Pro) attached to a Cypress SL811
shown to work, I am now trying to attach a Texas Instruments TUSB2077a
Hub chip. When I first attach the hub to the host on Data +/- (pins 7 &
8) the host recognizes the hub and then reports "USB device not
accepting new address (error=-110)
** SNIP **
/dev # cd /mnt
/mnt # insmod usbcore.o -f
Warning: kernel-module version mismatch
usbcore.o was compiled for kernel version
2.4.26-msi
while this kernel is version 2.4.26-pre3
Warning: loading usbcore.o will taint the kernel: forced
load
See http://www.tux.org/lkml/#export-tainted for
information about tainted modules
Module usbcore loaded, with warnings
/mnt # insmod -f sl__
/mnt # insmod -f sl811.o _[J
Warning: kernel-module version mismatch
sl811.o was compiled for kernel version
2.4.26-msi
while this kernel is version 2.4.26-pre3
Warning: loading sl811.o will taint the kernel: no
license
See http://www.tux.org/lkml/#export-tainted for
information about tainted modules
Warning: loading sl811.o will taint the kernel: forced
load
Module sl811 loaded, with warnings
/mnt #
; MSC - External Hub is identified
; MSC - And reports over-current on three of the four
available ports
hub.c: port 2 over-current change
hub.c: port 3 over-current change
hub.c: port 4 over-current change
; MSC - Host controller unable to set USB address on new
HUB
; Hub is disconnected and un-reachable from this point
on
hub.c: USB device not accepting new address (error=-110)
hub.c: error resetting hub 2 - disconnecting
** SNIP **
At this point the hub is completely un-responsive, but re-plugging the
hub will return the same results. If I have a thumb drive attached to
the hub, before I plug the hub into the host controller, I see the thumb
drive properly but exit with the same error "USB device not accepting
new address (error=-110).
** SNIP **
usb.c: USB device 2 (vend/prod 0x781/0x7104) is not
claimed by any active driver.
; MSC - Thumb drive is enumberated
Length = 18
DescriptorType = 01
USB version = 2.00
Vendor:Product = 0781:7104
MaxPacketSize0 = 64
NumConfigurations = 1
Device version = 10.33
Device Class:SubClass:Protocol = 00:00:00
Per-interface classes
Configuration:
bLength = 9
. . . . .
bInterval = 00
; MSC - Host controller unable to set USB address on new
HUB
; Hub is disconnected and un-reachable from this point
on
hub.c: USB device not accepting new address (error=-110)
hub.c: error resetting hub 127 - disconnecting
** SNIP **
What am I doing wrong?
Michael S. Chaffin
Satellite Test Engineer
MicroSat Systems, Inc.
microsatsystems.com
[-- Attachment #2: Type: text/html, Size: 7040 bytes --]
^ permalink raw reply
* Re: [PATCH] powerpc: Add of_platform support for OHCI/Bigendian HC
From: Kumar Gala @ 2006-11-07 16:46 UTC (permalink / raw)
To: Sylvain Munaut; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <454FC539.2050900@246tNt.com>
On Nov 6, 2006, at 5:28 PM, Sylvain Munaut wrote:
> Kumar Gala wrote:
>> On Nov 6, 2006, at 4:35 AM, Nicolas DET wrote:
>>
>>
>>> This patch use of_platform device to probe and install OHCI big
>>> endian HC.
>>>
>>> PS: I did not success to properly inline the file using
>>> thrunderbird.
>>>
>>
>> You really copy the USB maintainers on this. Also, why bother with
>> the Kconfig for USB_OHCI_HCD_PPC_OF_BE/USB_OHCI_HCD_PPC_OF_LE?
>>
> I think it's a good idea to use those :
> - Just including both when PPC_OF is used is overkill because it
> makes
> all USB
> perform useless tests if you never intend to use the LE version for
> example.
> - Using the already defined symbol USB_OHCI_BIG_ENDIAN would force
> other ohci user to select BE/LE and they may not want to expose this.
Maybe I'm missing something, but it looks like the _OF_LE & _OF_BE
are just configuring what matches may occur. This seems like a one
time event.
> However in this bus glue test :
>
> + || defined (CONFIG_USB_OHCI_HCD_PPC_OF_LE) \
> + || defined (CONFIG_USB_OHCI_HCD_PPC_OF_BE) \
>
> I would just test for CONFIG_USB_OHCI_HCD_PPC_OF to keep things the
> same
> betwenn all the bus glues. (Sure it would be stupid to select
> PPC_OF and neither
> LE nor BE ...)
>
> But that's just me and if the usb maintainer is ok with it, it's
> his call.
>
>
> So otherwise, looks good to me. Haven't tested in hw yet ... I'll
> report asap.
>
>
> Sylvain
^ permalink raw reply
* Re: [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Grant Likely @ 2006-11-07 16:30 UTC (permalink / raw)
To: Sylvain Munaut; +Cc: linuxppc-dev, sven, linuxppc-embedded
In-Reply-To: <455063C6.6070205@246tNt.com>
On 11/7/06, Sylvain Munaut <tnt@246tnt.com> wrote:
> Nicolas DET wrote:
>
> > This patch add MPC52xx Interrupt controller for ARCH=powerpc.
> >
> > It includes the main code in arch/powerpc/sysdev/ ad well as an header file in
> > include/asm-powerpc.
> >
> > The header file has now distinct section for the struct and the IRQ mapping/enconding define
> >
> > Signed-off-by: Nicolas DET <nd@bplan-gmbh.de>
> Acked-by: Sylvain Munaut <tnt@246tNt.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH 1/1] PPC32 : Huge-page support for ppc440
From: Matt Porter @ 2006-11-07 15:47 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Roland Dreier, Edi Shmueli, linuxppc-embedded
In-Reply-To: <1162871122.28571.396.camel@localhost.localdomain>
On Tue, Nov 07, 2006 at 02:45:22PM +1100, Benjamin Herrenschmidt wrote:
> On Mon, 2006-11-06 at 19:26 -0800, Roland Dreier wrote:
> > > Also, while it's great to have somebody do this work, I doubt there is
> > > much interest in merging it for arch/ppc...
> >
> > On that subject, what's the latest on moving ppc4xx to arch/powerpc?
> > At the kernel summit you told me to chill out and wait, but I'll
> > repeat my offer to help out....
>
> Well, I told you that Matt Porter was about to do it :-) Now I haven't
> heard from him since. Feel free to jump in, just make sure you keep in
> sync with Josh and Matt.
Er, wait a minute. :) I did some work then got busy again. I handed my
starting point stuff to Josh who has been continuing on with some work.
So there is progress happening there on the basic enablement, that is,
outside of your contributions on mmio dcr handling etc.
-Matt
^ permalink raw reply
* Re: [PATCH] adding ROM chips to device tree: respin
From: Sergei Shtylyov @ 2006-11-07 15:27 UTC (permalink / raw)
To: Vitaly Wool; +Cc: linuxppc-embedded
In-Reply-To: <20061107141923.16b2d2f1.vwool@ru.mvista.com>
Hello.
Vitaly Wool wrote:
> inlined below is the patch which adds support for flash device descriptions to the OF device tree. It's inspired by and partially borrowed from Sergei's patch which can be found at http://patchwork.ozlabs.org/linuxppc/patch?id=6526 but arranges things in a different way.
> It should be used together with the corresponding MTD layer extension the current version of which was recently posted to linux-mtd list for discussion and can be found at http://lists.infradead.org/pipermail/linux-mtd/2006-November/016700.html.
> In fact, currently this description can handle only flash devices mapped into memory in a linear way.
> This patch is a respin of the patch which can be found at http://ozlabs.org/pipermail/linuxppc-embedded/2006-November/025013.html with comments from Sergei and Josh taken into account.
>
> Documentation/powerpc/booting-without-of.txt | 37 +++++++++++++++++++++++++++
> arch/powerpc/sysdev/Makefile | 1
> arch/powerpc/sysdev/rom.c | 31 ++++++++++++++++++++++
> 3 files changed, 69 insertions(+)
>
> Signed-off-by: Vitaly Wool <vwool@ru.mvista.com>
>
> Index: powerpc/Documentation/powerpc/booting-without-of.txt
> ===================================================================
> --- powerpc.orig/Documentation/powerpc/booting-without-of.txt
> +++ powerpc/Documentation/powerpc/booting-without-of.txt
> @@ -6,6 +6,8 @@
> IBM Corp.
> (c) 2005 Becky Bruce <becky.bruce at freescale.com>,
> Freescale Semiconductor, FSL SOC and 32-bit additions
> +(c) 2006 MontaVista Software, Inc.
> + Flash chip node definition
>
> May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet.
>
> @@ -1693,6 +1695,41 @@ platforms are moved over to use the flat
> };
> };
>
> + g) Flash chip nodes
> +
> + Flash chips (Memory Technology Devices) are often used for solid state
> + file systems on embedded devices.
> +
> + Required properties:
> +
> + - device_type : has to be "rom"
> + - compatible : Should be the name of the MTD driver. Currently, this is
> + most likely to be "physmap".
> + - memory_space : Offset and length of the register set for the device.
NAK. There's no need to define an extra property where "reg" should be used.
> + - bank-width : Width of the flash data bus in bytes. Required
> + for the NOR flashes (compatible == "physmap" and others) ONLY.
Then it can not be called a *required* property I think.
> +
> + Recommended properties :
> +
> + - partitions : Several pairs of 32-bit values where the first value is
> + partition's offset from the start of the MTD device and the second
> + one is partition size in bytes with LSB used to signify a read only
> + partititon (so, the parition size should always be an even number).
> + - partition-names : The list of concatenated zero terminated strings
> + representing the partition names.
> +
> + Example:
> +
> + flash@ff000000 {
> + device_type = "rom";
> + compatible = "physmap";
> + memory_space = <ff000000 01000000>;
> + bank-width = <4>;
> + partitions = <00000000 00f80000
> + 00f80000 00080001>;
> + partition-names = "fs\0firmware";
> + };
> +
> More devices will be defined as this spec matures.
>
>
> Index: powerpc/arch/powerpc/sysdev/Makefile
> ===================================================================
> --- powerpc.orig/arch/powerpc/sysdev/Makefile
> +++ powerpc/arch/powerpc/sysdev/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
> obj-$(CONFIG_FSL_SOC) += fsl_soc.o
> obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
> obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
> +obj-$(CONFIG_MTD) += rom.o
>
> ifeq ($(CONFIG_PPC_MERGE),y)
> obj-$(CONFIG_PPC_I8259) += i8259.o
> Index: powerpc/arch/powerpc/sysdev/rom.c
> ===================================================================
> --- /dev/null
> +++ powerpc/arch/powerpc/sysdev/rom.c
> @@ -0,0 +1,31 @@
> +/*
> + * arch/powerpc/sysdev/flash.c
> + *
> + * Flash memory registration
> + *
> + * (C) 2006 MontaVista Software, Inc. This file is licensed under
> + * the terms of the GNU General Public License version 2. This program
> + * is licensed "as is" without any warranty of any kind, whether express
> + * or implied.
> + */
> +
> +#include <asm/of_device.h>
> +
> +static int __init powerpc_flash_init(void)
> +{
> + struct device_node *node = NULL;
> + int num = 0;
> +
> + /*
> + * We care only about physmap devices now as there's no
> + * description defined for other ROM types yet
> + */
Not true. The description only says that it's *most probably* compatible
with "physmap", that's all. I don't see why we have to limit ourselves here.
> + while ((node = of_find_compatible_node(node, "rom", "physmap"))
> + != NULL) {
> + of_platform_device_create(node, "physmap-flash", NULL);
> + ++num;
Why are you counting them, can you say?
> + }
> + return 0;
> +}
> +
> +arch_initcall(powerpc_flash_init);
WBR, Sergei
^ permalink raw reply
* Re: [PATCH] CPM_UART: Fixed SMC handling for CPM2 processors
From: Vitaly Bordug @ 2006-11-07 14:47 UTC (permalink / raw)
To: Kalle Pokki; +Cc: Paul, linuxppc-embedded, Mackerras
In-Reply-To: <Pine.LNX.4.64.0611071451130.3291@host32.eke.fi>
[-- Attachment #1: Type: text/plain, Size: 2222 bytes --]
On Tue, 7 Nov 2006 15:21:00 +0200 (EET)
Kalle Pokki wrote:
> On Tue, 7 Nov 2006, Vitaly Bordug wrote:
>
> > Well, yes, but are you _sure_ pram_base will be the same across all
> > the 82xx PQ2, that happen to have smc wired to Ethernet?
> >
> > If not I am considering storing it in the platform_data is better
> > approach.
>
> Yes, pram_base is always 0x87fc for SMC1 and 0x88fc for SMC2. This is
> for all PowerQUICC II families (8260, 8272, and 8280). I'm not sure
> how PQ2 Pro and PQ3 and handled, but I suspect they don't share these
> definitions.
>
ok
> Anyway, I'm only extending the already existing conventions to the
> platform device approach. These same decisions have already been made
> in the past and are used in the cpm_uart compat mode. It may be that
> Freescale someday releases a microcode patch that relocates the SMC
> parameter RAM, but even in this case it would be better to use the
> same approach with compat mode and platform device mode to avoid
> confusion.
>
> I could have used the numerical address offsets in the resource
> definition, but I wanted to emphasize the fact that the offsets are
> already defined by the DPRAM memory allocator (this is a little
> hackish, yes) instead of hardware directly requiring these exact
> values.
>
Aha, I recall now. There was nearly exactly the same discussion in the past.
The recap was since ppc_platform_devices[] approach is not flexible enough, revisit issue from the
arch/powerpc POV.
> This snippet is from cpm2.h:
>
> /* Dual Port RAM addresses. The first 16K is available for
> almost
> * any CPM use, so we put the BDs there. The first 128
> bytes are
> * used for SMC1 and SMC2 parameter RAM, so we start
> allocating
> * BDs above that. All of this must change when we start
> * downloading RAM microcode.
> */
> #define CPM_DATAONLY_BASE ((uint)128)
>
> My patch puts pram_base exactly here.
>
>
I know, the questionable thing was if there is enough "value" to add yet another platform device for that.
Since it improves current ppc being and sort of puts a note for powerpc port, I'm inclined to ACK.
Thanks,
-Vitaly
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Installing u-boot on sbc8260 via ethernet using minicom
From: federicosibilio @ 2006-11-07 13:38 UTC (permalink / raw)
To: linuxppc-embedded
i've tryed to install u-boot using minicom, but i'm not able to=20
configure in shell boot params,=20
using this...
boot device : motfcc
unit number : 0
processor number : 0
host name : motfcc0
inet on ethernet (e) : 192.168.0.4
inet on backplane (b): 192.168.0.4
host inet (h) : 192.168.0.3
gateway inet (g) : 192.168.0.3
flags (f) : 0x80
target name (tn) : sbc8260
when i reboot target it appears in minicom the message below:
AT S7=3D45 S0=3D0 L1 V1 X4 &c1 E1 Q0
0x1f058b0 (tBoot): miiPhyInit check cable connection
Attached TCP/IP interface to motfcc0.
Warning: no netmask specified.
Attaching network interface lo0... done.
Loading... Erroneous header read
Error loading file: errno =3D 0x610001.
Can't load boot file!!
=C3=BC
my questions are?
what file must i put into target?(u-boot.bin?)
in which way can i upload it?(using tftp with 192.168.0.4 and using=20
put command, it gives timeout for transmission, but ping to=20
192.168.0.3=20
works normally until in minicom appears error message)
Please help me to configure and install u-boot
thanks very much!!!
Naviga e telefona senza limiti con Tiscali =20
Scopri le promozioni Tiscali adsl: navighi e telefoni senza canone Telecom
http://abbonati.tiscali.it/adsl/
^ permalink raw reply
* why need disable icache
From: enorm @ 2006-11-07 13:16 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 223 bytes --]
Hi, all
I have been confused by cache recently.
1. why need we disable icache and dcache at the beginning of the u-boot code?
2. when can we enable them ?
Your answers will be honestly welcomed.
Best regards
Enorm
[-- Attachment #2: Type: text/html, Size: 783 bytes --]
^ permalink raw reply
* Re: [PATCH] CPM_UART: Fixed SMC handling for CPM2 processors
From: Kalle Pokki @ 2006-11-07 13:21 UTC (permalink / raw)
To: Vitaly Bordug; +Cc: linuxppc-embedded, Paul Mackerras
In-Reply-To: <20061107150842.6ac9e8ce@vitb.ru.mvista.com>
On Tue, 7 Nov 2006, Vitaly Bordug wrote:
> Well, yes, but are you _sure_ pram_base will be the same across all the
> 82xx PQ2, that happen to have smc wired to Ethernet?
>
> If not I am considering storing it in the platform_data is better approach.
Yes, pram_base is always 0x87fc for SMC1 and 0x88fc for SMC2. This is
for all PowerQUICC II families (8260, 8272, and 8280). I'm not sure how
PQ2 Pro and PQ3 and handled, but I suspect they don't share these
definitions.
Anyway, I'm only extending the already existing conventions to the
platform device approach. These same decisions have already been made in
the past and are used in the cpm_uart compat mode. It may be that
Freescale someday releases a microcode patch that relocates the SMC
parameter RAM, but even in this case it would be better to use the same
approach with compat mode and platform device mode to avoid confusion.
I could have used the numerical address offsets in the resource
definition, but I wanted to emphasize the fact that the offsets are
already defined by the DPRAM memory allocator (this is a little hackish,
yes) instead of hardware directly requiring these exact values.
This snippet is from cpm2.h:
/* Dual Port RAM addresses. The first 16K is available for almost
* any CPM use, so we put the BDs there. The first 128 bytes are
* used for SMC1 and SMC2 parameter RAM, so we start allocating
* BDs above that. All of this must change when we start
* downloading RAM microcode.
*/
#define CPM_DATAONLY_BASE ((uint)128)
My patch puts pram_base exactly here.
^ permalink raw reply
* Re: [PATCH] CPM_UART: Fixed SMC handling for CPM2 processors
From: Vitaly Bordug @ 2006-11-07 12:08 UTC (permalink / raw)
To: Kalle Pokki; +Cc: Paul Mackerras, linuxppc-embedded
In-Reply-To: <Pine.LNX.4.64.0611062237300.16727@host32.eke.fi>
On Mon, 6 Nov 2006 22:49:49 +0200 (EET)
Kalle Pokki <kalle.pokki@iki.fi> wrote:
> On Mon, 6 Nov 2006, Vitaly Bordug wrote:
>
> >> This patch renames these the two existing resources, and introduces a
> >> new one, "pram_base", which is a pointer to the parameter RAM. The
> >> parameter RAM for SMC1 and SMC2 is put in the first 128 bytes of the
> >> DPRAM. This memory was already reserved from the DPRAM memory
> >> allocator for this purpose.
> >>
> > Well just one objection. pram_base should not be a device unless it applies to all the stuff of
> > SoC family which is not the case.
> >
> > For this aim, I'd put what you need into the platform_data, or follow the same approach 8xx stuff having.
>
> I'm not sure I follow you now. "pram_base" is not a device by itself, but
> it's just another resource in the PQ2 version of the SMC devices in the
> platform_data. So the resource is only present when it is needed, and for
> other platform devices that don't have this resource, the cpm_uart code
> does nothing (as it should not).
>
Well, yes, but are you _sure_ pram_base will be the same across all the 82xx PQ2, that happen to have smc wired to Ethernet?
If not I am considering storing it in the platform_data is better approach.
> The only difference to the 8xx version is the new "pram_base" resource,
> and it is required with PQ2, right?
Prolly, and I actually tried the same when introduced 8xx stuff. It was not permitted because such a thing could not be stuck to one value, and as long as we'll have it compiled into the devices table, others will have to use that offset (yet maybe having the specific dpram required for another purpose).
Hope that clarifies my position...
--
Sincerely,
Vitaly
^ permalink raw reply
* Re: [PATCH 23/31] powerpc: Cell "Spider" MMIO workarounds
From: Christoph Hellwig @ 2006-11-07 11:55 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20061107072414.87D5F688CC@ozlabs.org>
On Tue, Nov 07, 2006 at 06:22:57PM +1100, Benjamin Herrenschmidt wrote:
> + * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
> + * that is iMac G5 and latest single CPU desktop.
This doesn't make any sense ;-)
^ permalink raw reply
* Re: [PATCH 1/1] PPC32 : Huge-page support for ppc440
From: Josh Boyer @ 2006-11-07 11:52 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Roland Dreier, Edi Shmueli, linuxppc-embedded
In-Reply-To: <1162871122.28571.396.camel@localhost.localdomain>
On Tue, 2006-11-07 at 14:45 +1100, Benjamin Herrenschmidt wrote:
> On Mon, 2006-11-06 at 19:26 -0800, Roland Dreier wrote:
> > > Also, while it's great to have somebody do this work, I doubt there is
> > > much interest in merging it for arch/ppc...
> >
> > On that subject, what's the latest on moving ppc4xx to arch/powerpc?
> > At the kernel summit you told me to chill out and wait, but I'll
> > repeat my offer to help out....
>
> Well, I told you that Matt Porter was about to do it :-) Now I haven't
> heard from him since. Feel free to jump in, just make sure you keep in
> sync with Josh and Matt.
>
> One of the reason waiting was a good idea too is that we didn't have a
> proper mecanism for stuffing device-trees in zImage wrappers, which we
> have now.
I've gotten this mostly working for 44x. I need to rebase and do a few
cleanups on the patches though.
> Also, I've started doing some work around 4xx devices used on MMIO
> platforms (like the Axon southbridge on Cell), and while doing that,
> started moving EMAC to be an of_platform_device (or rather a set of them
> since EMAC is made of multiple devices). (Based on initial work by
> Shaun).
That'll come in handy soon. Right now, the zImage wrapper uncompresses
the kernel and jumps to it, but I don't get any further output. It's
just a matter of getting time and I need to sit down and work on this
some more.
josh
^ permalink raw reply
* [PATCH] adding ROM chips to device tree: respin
From: Vitaly Wool @ 2006-11-07 11:19 UTC (permalink / raw)
To: linuxppc-embedded
Hello folks,
inlined below is the patch which adds support for flash device descriptions to the OF device tree. It's inspired by and partially borrowed from Sergei's patch which can be found at http://patchwork.ozlabs.org/linuxppc/patch?id=6526 but arranges things in a different way.
It should be used together with the corresponding MTD layer extension the current version of which was recently posted to linux-mtd list for discussion and can be found at http://lists.infradead.org/pipermail/linux-mtd/2006-November/016700.html.
In fact, currently this description can handle only flash devices mapped into memory in a linear way.
This patch is a respin of the patch which can be found at http://ozlabs.org/pipermail/linuxppc-embedded/2006-November/025013.html with comments from Sergei and Josh taken into account.
Documentation/powerpc/booting-without-of.txt | 37 +++++++++++++++++++++++++++
arch/powerpc/sysdev/Makefile | 1
arch/powerpc/sysdev/rom.c | 31 ++++++++++++++++++++++
3 files changed, 69 insertions(+)
Signed-off-by: Vitaly Wool <vwool@ru.mvista.com>
Index: powerpc/Documentation/powerpc/booting-without-of.txt
===================================================================
--- powerpc.orig/Documentation/powerpc/booting-without-of.txt
+++ powerpc/Documentation/powerpc/booting-without-of.txt
@@ -6,6 +6,8 @@
IBM Corp.
(c) 2005 Becky Bruce <becky.bruce at freescale.com>,
Freescale Semiconductor, FSL SOC and 32-bit additions
+(c) 2006 MontaVista Software, Inc.
+ Flash chip node definition
May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet.
@@ -1693,6 +1695,41 @@ platforms are moved over to use the flat
};
};
+ g) Flash chip nodes
+
+ Flash chips (Memory Technology Devices) are often used for solid state
+ file systems on embedded devices.
+
+ Required properties:
+
+ - device_type : has to be "rom"
+ - compatible : Should be the name of the MTD driver. Currently, this is
+ most likely to be "physmap".
+ - memory_space : Offset and length of the register set for the device.
+ - bank-width : Width of the flash data bus in bytes. Required
+ for the NOR flashes (compatible == "physmap" and others) ONLY.
+
+ Recommended properties :
+
+ - partitions : Several pairs of 32-bit values where the first value is
+ partition's offset from the start of the MTD device and the second
+ one is partition size in bytes with LSB used to signify a read only
+ partititon (so, the parition size should always be an even number).
+ - partition-names : The list of concatenated zero terminated strings
+ representing the partition names.
+
+ Example:
+
+ flash@ff000000 {
+ device_type = "rom";
+ compatible = "physmap";
+ memory_space = <ff000000 01000000>;
+ bank-width = <4>;
+ partitions = <00000000 00f80000
+ 00f80000 00080001>;
+ partition-names = "fs\0firmware";
+ };
+
More devices will be defined as this spec matures.
Index: powerpc/arch/powerpc/sysdev/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/sysdev/Makefile
+++ powerpc/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_MTD) += rom.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
Index: powerpc/arch/powerpc/sysdev/rom.c
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/sysdev/rom.c
@@ -0,0 +1,31 @@
+/*
+ * arch/powerpc/sysdev/flash.c
+ *
+ * Flash memory registration
+ *
+ * (C) 2006 MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <asm/of_device.h>
+
+static int __init powerpc_flash_init(void)
+{
+ struct device_node *node = NULL;
+ int num = 0;
+
+ /*
+ * We care only about physmap devices now as there's no
+ * description defined for other ROM types yet
+ */
+ while ((node = of_find_compatible_node(node, "rom", "physmap"))
+ != NULL) {
+ of_platform_device_create(node, "physmap-flash", NULL);
+ ++num;
+ }
+ return 0;
+}
+
+arch_initcall(powerpc_flash_init);
^ permalink raw reply
* Re: [RFC/PATCH 6/7] MPIC MSI backend
From: Segher Boessenkool @ 2006-11-07 11:12 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Greg Kroah-Hartman, linuxppc-dev, Eric W. Biederman, linux-pci,
David S. Miller
In-Reply-To: <1162890963.28571.465.camel@localhost.localdomain>
> Not only, even with the current code... basically keep the
> sense/polarity flags of the LSI intact in the irq_desc, just add the
> IRQF_MSI bit to "override" them when we configure the interrupt to
> be an
> MSI. Then, irq_chip->startup() instead of set_irq_type() does the
> actual
> configuration of the MPIC and, seeing the IRQF_MSI flags, does the
> right
> thing.
>
> That way, when restoring the IRQ back to LSI, we just clear
> IRQF_MSI and
> the old sense/polarity settings will still be there in the descriptor
> and MPIC will do the right thing on the next startup().
Cute trick, and not MPIC (or even PowerPC) specific either :-)
> Are you sure about that ?
Yes. "Legacy PCI" INTx interrupts are send as "virtual wire"
interrupts over PCIe; Attu asserts interrupt #3 on Kodiak's
MPIC if any of INTA..INTD is hot (I have no idea how to
distinguish between those four, though -- and that seems to be
pretty important, heh).
> In this case, we need a special kludge for
> now. I though the MSI stuff could override any of the MPIC vectors,
> but
> you might well be right there, it might not work with the U4 internal
> ones.
U4 interrupts 0..7 from HT (or PCIe) are not decoded on U4;
0..3 on U3 (which supports MSI-via-HT just fine).
> Yes, I know :-) We need specific code to discover that a device is
> hanging off the Attu instead of HT. I already explained it all to
> Michael, it shouldn't be too hard. I even have a card setup to test
> it,
> just didn't have time to do it just yet.
I never tested Attu interrupts at all (just the MSI write
port), glad _someone_ is testing it :-)
Segher
^ permalink raw reply
* Re: [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Sylvain Munaut @ 2006-11-07 10:45 UTC (permalink / raw)
To: Nicolas DET; +Cc: linuxppc-dev, sven, linuxppc-embedded
In-Reply-To: <200611071040.kA7Aeea6006482@post.webmailer.de>
Nicolas DET wrote:
> This patch add MPC52xx Interrupt controller for ARCH=powerpc.
>
> It includes the main code in arch/powerpc/sysdev/ ad well as an header file in
> include/asm-powerpc.
>
> The header file has now distinct section for the struct and the IRQ mapping/enconding define
>
> Signed-off-by: Nicolas DET <nd@bplan-gmbh.de>
Acked-by: Sylvain Munaut <tnt@246tNt.com>
^ permalink raw reply
* [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Nicolas DET @ 2006-11-07 10:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sven, linuxppc-embedded
This patch add MPC52xx Interrupt controller for ARCH=3Dpowerpc.
It includes the main code in arch/powerpc/sysdev/ ad well as an header file=
in
include/asm-powerpc.
The header file has now distinct section for the struct and the IRQ mapping=
/enconding define
Signed-off-by: Nicolas DET <nd@bplan-gmbh.de>
---
--- a/arch/powerpc/sysdev/mpc52xx_pic.c=091970-01-01 01:00:00.000000000 +01=
00
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c=092006-11-07 10:57:28.000000000 +01=
00
@@ -0,0 +1,527 @@
+/*
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx.
+ *
+ * Copyright (C) 2006 bplan GmbH
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *=20
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+#undef DEBUG
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/hardirq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/mpc52xx.h>
+
+/*
+ *
+*/
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+static struct irq_host *mpc52xx_irqhost =3D NULL;
+
+static unsigned char mpc52xx_map_senses[4] =3D {
+=09IRQ_TYPE_LEVEL_HIGH,
+=09IRQ_TYPE_EDGE_RISING,
+=09IRQ_TYPE_EDGE_FALLING,
+=09IRQ_TYPE_LEVEL_LOW,
+};
+
+/*
+ *
+*/
+
+static inline void io_be_setbit(u32 __iomem *addr, int bitno)
+{
+=09out_be32(addr, in_be32(addr) | (1 << bitno) );
+}
+
+static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
+{
+=09out_be32(addr, in_be32(addr) & ~(1 << bitno));
+}
+
+/*
+ * IRQ[0-3] interrupt irq_chip
+*/
+
+static void mpc52xx_extirq_mask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_clrbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_extirq_unmask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_setbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_extirq_ack(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_setbit(&intr->ctrl, 27-l2irq);
+}
+
+static struct irq_chip mpc52xx_extirq_irqchip =3D {
+=09.typename =3D " MPC52xx IRQ[0-3] ",
+=09.mask =3D mpc52xx_extirq_mask,
+=09.unmask =3D mpc52xx_extirq_unmask,
+=09.ack =3D mpc52xx_extirq_ack,
+};
+
+/*
+ * Main interrupt irq_chip
+*/
+
+static void mpc52xx_main_mask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_setbit(&intr->main_mask, 15 - l2irq);
+}
+
+static void mpc52xx_main_unmask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_clrbit(&intr->main_mask, 15 - l2irq);
+}
+
+static struct irq_chip mpc52xx_main_irqchip =3D {
+=09.typename =3D "MPC52xx Main",
+=09.mask =3D mpc52xx_main_mask,
+=09.mask_ack =3D mpc52xx_main_mask,
+=09.unmask =3D mpc52xx_main_unmask,
+};
+
+/*
+ * Peripherals interrupt irq_chip
+*/
+
+static void mpc52xx_periph_mask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_setbit(&intr->per_mask, 31 - l2irq);
+}
+
+static void mpc52xx_periph_unmask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_clrbit(&intr->per_mask, 31 - l2irq);
+}
+
+static struct irq_chip mpc52xx_periph_irqchip =3D {
+=09.typename =3D "MPC52xx Peripherals",
+=09.mask =3D mpc52xx_periph_mask,
+=09.mask_ack =3D mpc52xx_periph_mask,
+=09.unmask =3D mpc52xx_periph_unmask,
+};
+
+/*
+ * SDMA interrupt irq_chip
+*/
+
+static void mpc52xx_sdma_mask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_setbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_unmask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_clrbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_ack(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09out_be32(&sdma->IntPend, 1 << l2irq);
+}
+
+static struct irq_chip mpc52xx_sdma_irqchip =3D {
+=09.typename =3D "MPC52xx SDMA",
+=09.mask =3D mpc52xx_sdma_mask,
+=09.unmask =3D mpc52xx_sdma_unmask,
+=09.ack =3D mpc52xx_sdma_ack,
+};
+
+/*
+ * irq_host
+*/
+
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *n=
ode)
+{
+=09pr_debug("%s: node=3D%pn", __func__, node);
+=09return mpc52xx_irqhost->host_data =3D=3D node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *c=
t,
+=09=09=09=09 u32 * intspec, unsigned int intsize,
+=09=09=09=09 irq_hw_number_t * out_hwirq,
+=09=09=09=09 unsigned int *out_flags)
+{
+=09int intrvect_l1;
+=09int intrvect_l2;
+=09int intrvect_type;
+=09int intrvect_linux;
+
+=09if (intsize !=3D 3)
+=09=09return -1;
+
+=09intrvect_l1 =3D (int)intspec[0];
+=09intrvect_l2 =3D (int)intspec[1];
+=09intrvect_type =3D (int)intspec[2];
+
+=09intrvect_linux =3D
+=09 (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;
+=09intrvect_linux |=3D
+=09 (intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;
+
+=09pr_debug("return %x, l1=3D%d, l2=3D%dn", intrvect_linux, intrvect_l1,
+=09=09 intrvect_l2);
+
+=09*out_hwirq =3D intrvect_linux;
+=09*out_flags =3D mpc52xx_map_senses[intrvect_type];
+
+=09return 0;
+}
+
+/*
+ * this function retrieves the correct IRQ type out
+ * of the MPC regs
+ * Only externals IRQs needs this
+*/
+static int mpc52xx_irqx_gettype(int irq)
+{
+=09int type;
+=09u32 ctrl_reg;
+
+=09ctrl_reg =3D in_be32(&intr->ctrl);
+=09type =3D (ctrl_reg >> (22 - irq * 2)) & 0x3;
+
+=09return mpc52xx_map_senses[type];
+}
+
+static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
+=09=09=09 irq_hw_number_t irq)
+{
+=09int l1irq;
+=09int l2irq;
+=09struct irq_chip *good_irqchip;
+=09void *good_handle;
+=09int type;
+
+=09l1irq =3D (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09/*
+=09 * Most of ours IRQs will be level low
+=09 * Only external IRQs on some platform may be others
+=09 */
+=09type =3D IRQ_TYPE_LEVEL_LOW;
+
+=09switch (l1irq) {
+=09case MPC52xx_IRQ_L1_CRIT:
+=09=09pr_debug("%s: Critical. l2=3D%xn", __func__, l2irq);
+
+=09=09BUG_ON(l2irq !=3D 0);
+
+=09=09type =3D mpc52xx_irqx_gettype(l2irq);
+=09=09good_irqchip =3D &mpc52xx_extirq_irqchip;
+=09=09break;
+
+=09case MPC52xx_IRQ_L1_MAIN:
+=09=09pr_debug("%s: Main IRQ[1-3] l2=3D%xn", __func__, l2irq);
+
+=09=09if ((l2irq >=3D 1) && (l2irq <=3D 3)) {
+=09=09=09type =3D mpc52xx_irqx_gettype(l2irq);
+=09=09=09good_irqchip =3D &mpc52xx_extirq_irqchip;
+=09=09} else {
+=09=09=09good_irqchip =3D &mpc52xx_main_irqchip;
+=09=09}
+=09=09break;
+
+=09case MPC52xx_IRQ_L1_PERP:
+=09=09pr_debug("%s: Peripherals. l2=3D%xn", __func__, l2irq);
+=09=09good_irqchip =3D &mpc52xx_periph_irqchip;
+=09=09break;
+
+=09case MPC52xx_IRQ_L1_SDMA:
+=09=09pr_debug("%s: SDMA. l2=3D%xn", __func__, l2irq);
+=09=09good_irqchip =3D &mpc52xx_sdma_irqchip;
+=09=09break;
+
+=09default:
+=09=09pr_debug("%s: Error, unknown L1 IRQ (0x%x)n", __func__, l1irq);
+=09=09printk(KERN_ERR "Unknow IRQ!n");
+=09=09return -EINVAL;
+=09}
+
+=09switch (type) {
+=09case IRQ_TYPE_EDGE_FALLING:
+=09case IRQ_TYPE_EDGE_RISING:
+=09=09good_handle =3D handle_edge_irq;
+=09=09break;
+=09default:
+=09=09good_handle =3D handle_level_irq;
+=09}
+
+=09set_irq_chip_and_handler(virq, good_irqchip, good_handle);
+
+=09pr_debug("%s: virq=3D%x, hw=3D%x. type=3D%xn", __func__, virq,
+=09=09 (int)irq, type);
+
+=09return 0;
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops =3D {
+=09.match =3D mpc52xx_irqhost_match,
+=09.xlate =3D mpc52xx_irqhost_xlate,
+=09.map =3D mpc52xx_irqhost_map,
+};
+
+/*
+ * init (public)
+*/
+
+void __init mpc52xx_init_irq(void)
+{
+=09struct device_node *picnode =3D NULL;
+=09int picnode_regsize;
+=09u32 picnode_regoffset;
+
+=09struct device_node *sdmanode =3D NULL;
+=09int sdmanode_regsize;
+=09u32 sdmanode_regoffset;
+
+=09u64 size64;
+=09int flags;
+
+=09u32 intr_ctrl;
+
+=09picnode =3D of_find_compatible_node(NULL, "interrupt-controller", "mpc5=
200-pic");
+=09if (picnode =3D=3D NULL) {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to find the interrupt controlle=
r in the OpenFirmware device treen");
+=09=09goto end;
+=09}
+
+=09sdmanode =3D of_find_compatible_node(NULL, "dma-controller", "mpc5200-b=
estcomm");
+=09if (sdmanode =3D=3D NULL) {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to find the Bestcomm DMA contro=
ller device in the OpenFirmware device treen");
+=09=09goto end;
+=09}
+
+=09/* Retrieve PIC ressources */
+=09picnode_regoffset =3D (u32) of_get_address(picnode, 0, &size64, &flags)=
;
+=09if (picnode_regoffset =3D=3D 0) {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to get the interrupt controller=
addressn");
+=09=09goto end;
+=09}
+
+=09picnode_regoffset =3D of_translate_address(picnode, (u32 *) picnode_reg=
offset);
+=09picnode_regsize =3D (int) size64;=09
+
+=09/* Retrieve SDMA ressources */
+=09sdmanode_regoffset =3D (u32) of_get_address(sdmanode, 0, &size64, &flag=
s);
+=09if (sdmanode_regoffset =3D=3D 0) {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to get the Bestcomm DMA control=
ler addressn");
+=09=09goto end;
+=09}
+
+=09sdmanode_regoffset =3D of_translate_address(sdmanode, (u32 *) sdmanode_=
regoffset);
+=09sdmanode_regsize =3D (int) size64;
+
+=09/* Remap the necessary zones */
+=09intr =3D ioremap(picnode_regoffset, picnode_regsize);
+=09if (intr =3D=3D NULL) {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to ioremap interrupt controller=
registers!");
+=09=09goto end;
+=09}
+
+=09sdma =3D ioremap(sdmanode_regoffset, sdmanode_regsize);
+=09if (sdma =3D=3D NULL) {
+=09=09iounmap(intr);
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to ioremap Bestcomm DMA control=
ler registers!");
+=09=09goto end;
+=09}
+
+=09printk(KERN_INFO "MPC52xx PIC: MPC52xx PIC Remapped at 0x%8.8xn", picno=
de_regoffset);
+=09printk(KERN_INFO "MPC52xx PIC: MPC52xx SDMA Remapped at 0x%8.8xn", sdma=
node_regoffset);
+
+=09/* Disable all interrupt sources. */
+=09out_be32(&sdma->IntPend, 0xffffffff);=09/* 1 means clear pending */
+=09out_be32(&sdma->IntMask, 0xffffffff);=09/* 1 means disabled */
+=09out_be32(&intr->per_mask, 0x7ffffc00);=09/* 1 means disabled */
+=09out_be32(&intr->main_mask, 0x00010fff);=09/* 1 means disabled */
+=09intr_ctrl =3D in_be32(&intr->ctrl);
+=09intr_ctrl &=3D 0x00ff0000;=09/* Keeps IRQ[0-3] config */
+=09intr_ctrl |=3D 0x0f000000 |=09/* clear IRQ 0-3 */
+=09 0x00001000 |=09/* MEE master external enable */
+=09 0x00000000 |=09/* 0 means disable IRQ 0-3 */
+=09 0x00000001;=09=09/* CEb route critical normally */
+=09out_be32(&intr->ctrl, intr_ctrl);
+
+=09/* Zero a bunch of the priority settings. */
+=09out_be32(&intr->per_pri1, 0);
+=09out_be32(&intr->per_pri2, 0);
+=09out_be32(&intr->per_pri3, 0);
+=09out_be32(&intr->main_pri1, 0);
+=09out_be32(&intr->main_pri2, 0);
+
+=09/*
+=09 * As last step, add an irq host to translate the real
+=09 * hw irq information provided by the ofw to linux virq
+=09 */
+
+=09mpc52xx_irqhost =3D
+=09 irq_alloc_host(IRQ_HOST_MAP_LINEAR, MPC52xx_IRQ_HIGHTESTHWIRQ,
+=09=09=09 &mpc52xx_irqhost_ops, -1);
+
+=09if (mpc52xx_irqhost) {
+=09=09mpc52xx_irqhost->host_data =3D picnode;
+=09=09printk(KERN_INFO "MPC52xx PIC is up and running!n");
+=09} else {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to allocate the IRQ hostn");
+=09}
+
+end:
+=09of_node_put(picnode);
+=09of_node_put(sdmanode);
+}
+
+/*
+ * get_irq (public)
+*/
+unsigned int mpc52xx_get_irq(void)
+{
+=09u32 status;
+=09int irq =3D NO_IRQ_IGNORE;
+
+=09status =3D in_be32(&intr->enc_status);
+=09if (status & 0x00000400) {=09/* critical */
+=09=09irq =3D (status >> 8) & 0x3;
+=09=09if (irq =3D=3D 2)=09/* high priority peripheral */
+=09=09=09goto peripheral;
+=09=09irq |=3D
+=09=09 (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &
+=09=09 MPC52xx_IRQ_L1_MASK;
+=09} else if (status & 0x00200000) {=09/* main */
+=09=09irq =3D (status >> 16) & 0x1f;
+=09=09if (irq =3D=3D 4)=09/* low priority peripheral */
+=09=09=09goto peripheral;
+=09=09irq |=3D
+=09=09 (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &
+=09=09 MPC52xx_IRQ_L1_MASK;
+=09} else if (status & 0x20000000) {=09/* peripheral */
+=09 peripheral:
+=09=09irq =3D (status >> 24) & 0x1f;
+=09=09if (irq =3D=3D 0) {=09/* bestcomm */
+=09=09=09status =3D in_be32(&sdma->IntPend);
+=09=09=09irq =3D ffs(status) - 1;
+=09=09=09irq |=3D
+=09=09=09 (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &
+=09=09=09 MPC52xx_IRQ_L1_MASK;
+=09=09} else
+=09=09=09irq |=3D
+=09=09=09 (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &
+=09=09=09 MPC52xx_IRQ_L1_MASK;
+
+=09}
+
+=09pr_debug("%s: irq=3D%x. virq=3D%dn", __func__, irq,
+=09=09 irq_linear_revmap(mpc52xx_irqhost, irq));
+
+=09return irq_linear_revmap(mpc52xx_irqhost, irq);
+}
--- a/arch/powerpc/sysdev/Makefile=092006-11-01 09:18:43.000000000 +0100
+++ b/arch/powerpc/sysdev/Makefile=092006-11-07 11:21:25.000000000 +0100
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC)=09=09+=3D fsl_soc.o
obj-$(CONFIG_PPC_TODC)=09=09+=3D todc.o
obj-$(CONFIG_TSI108_BRIDGE)=09+=3D tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE)=09+=3D qe_lib/
+obj-$(CONFIG_PPC_MPC52xx)=09+=3D mpc52xx_pic.o
=20
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259)=09=09+=3D i8259.o
--- a/include/asm-powerpc/mpc52xx.h=091970-01-01 01:00:00.000000000 +0100
+++ b/include/asm-powerpc/mpc52xx.h=092006-11-07 10:57:28.000000000 +0100
@@ -0,0 +1,285 @@
+/*
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_POWERPC_MPC52xx_H__
+#define __ASM_POWERPC_MPC52xx_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/prom.h>
+#endif /* __ASSEMBLY__ */
+
+/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */
+/* HW IRQ mapping =
*/
+/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */
+
+#define MPC52xx_IRQ_L1_CRIT=09(0)
+#define MPC52xx_IRQ_L1_MAIN=09(1)
+#define MPC52xx_IRQ_L1_PERP=09(2)
+#define MPC52xx_IRQ_L1_SDMA=09(3)
+
+#define MPC52xx_IRQ_L1_OFFSET (6)
+#define MPC52xx_IRQ_L1_MASK (0xc0)
+
+#define MPC52xx_IRQ_L2_OFFSET (0)
+#define MPC52xx_IRQ_L2_MASK (0x3f)
+
+#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
+
+/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */
+/* Structures mapping of some unit register set =
*/
+/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */
+
+#ifndef __ASSEMBLY__
+
+/* Interrupt controller Register set */
+struct mpc52xx_intr {
+=09u32 per_mask;=09=09/* INTR + 0x00 */
+=09u32 per_pri1;=09=09/* INTR + 0x04 */
+=09u32 per_pri2;=09=09/* INTR + 0x08 */
+=09u32 per_pri3;=09=09/* INTR + 0x0c */
+=09u32 ctrl;=09=09/* INTR + 0x10 */
+=09u32 main_mask;=09=09/* INTR + 0x14 */
+=09u32 main_pri1;=09=09/* INTR + 0x18 */
+=09u32 main_pri2;=09=09/* INTR + 0x1c */
+=09u32 reserved1;=09=09/* INTR + 0x20 */
+=09u32 enc_status;=09=09/* INTR + 0x24 */
+=09u32 crit_status;=09/* INTR + 0x28 */
+=09u32 main_status;=09/* INTR + 0x2c */
+=09u32 per_status;=09=09/* INTR + 0x30 */
+=09u32 reserved2;=09=09/* INTR + 0x34 */
+=09u32 per_error;=09=09/* INTR + 0x38 */
+};
+
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+=09u32 mbar;=09=09/* MMAP_CTRL + 0x00 */
+
+=09u32 cs0_start;=09=09/* MMAP_CTRL + 0x04 */
+=09u32 cs0_stop;=09=09/* MMAP_CTRL + 0x08 */
+=09u32 cs1_start;=09=09/* MMAP_CTRL + 0x0c */
+=09u32 cs1_stop;=09=09/* MMAP_CTRL + 0x10 */
+=09u32 cs2_start;=09=09/* MMAP_CTRL + 0x14 */
+=09u32 cs2_stop;=09=09/* MMAP_CTRL + 0x18 */
+=09u32 cs3_start;=09=09/* MMAP_CTRL + 0x1c */
+=09u32 cs3_stop;=09=09/* MMAP_CTRL + 0x20 */
+=09u32 cs4_start;=09=09/* MMAP_CTRL + 0x24 */
+=09u32 cs4_stop;=09=09/* MMAP_CTRL + 0x28 */
+=09u32 cs5_start;=09=09/* MMAP_CTRL + 0x2c */
+=09u32 cs5_stop;=09=09/* MMAP_CTRL + 0x30 */
+
+=09u32 sdram0;=09=09/* MMAP_CTRL + 0x34 */
+=09u32 sdram1;=09=09/* MMAP_CTRL + 0X38 */
+
+=09u32 reserved[4];=09/* MMAP_CTRL + 0x3c .. 0x48 */
+
+=09u32 boot_start;=09=09/* MMAP_CTRL + 0x4c */
+=09u32 boot_stop;=09=09/* MMAP_CTRL + 0x50 */
+
+=09u32 ipbi_ws_ctrl;=09/* MMAP_CTRL + 0x54 */
+
+=09u32 cs6_start;=09=09/* MMAP_CTRL + 0x58 */
+=09u32 cs6_stop;=09=09/* MMAP_CTRL + 0x5c */
+=09u32 cs7_start;=09=09/* MMAP_CTRL + 0x60 */
+=09u32 cs7_stop;=09=09/* MMAP_CTRL + 0x64 */
+};
+
+/* SDRAM control */
+struct mpc52xx_sdram {
+=09u32 mode;=09=09/* SDRAM + 0x00 */
+=09u32 ctrl;=09=09/* SDRAM + 0x04 */
+=09u32 config1;=09=09/* SDRAM + 0x08 */
+=09u32 config2;=09=09/* SDRAM + 0x0c */
+};
+
+/* SDMA */
+struct mpc52xx_sdma {
+=09u32 taskBar;=09=09/* SDMA + 0x00 */
+=09u32 currentPointer;=09/* SDMA + 0x04 */
+=09u32 endPointer;=09=09/* SDMA + 0x08 */
+=09u32 variablePointer;=09/* SDMA + 0x0c */
+
+=09u8 IntVect1;=09=09/* SDMA + 0x10 */
+=09u8 IntVect2;=09=09/* SDMA + 0x11 */
+=09u16 PtdCntrl;=09=09/* SDMA + 0x12 */
+
+=09u32 IntPend;=09=09/* SDMA + 0x14 */
+=09u32 IntMask;=09=09/* SDMA + 0x18 */
+
+=09u16 tcr[16];=09=09/* SDMA + 0x1c .. 0x3a */
+
+=09u8 ipr[32];=09=09/* SDMA + 0x3c .. 0x5b */
+
+=09u32 cReqSelect;=09=09/* SDMA + 0x5c */
+=09u32 task_size0;=09=09/* SDMA + 0x60 */
+=09u32 task_size1;=09=09/* SDMA + 0x64 */
+=09u32 MDEDebug;=09=09/* SDMA + 0x68 */
+=09u32 ADSDebug;=09=09/* SDMA + 0x6c */
+=09u32 Value1;=09=09/* SDMA + 0x70 */
+=09u32 Value2;=09=09/* SDMA + 0x74 */
+=09u32 Control;=09=09/* SDMA + 0x78 */
+=09u32 Status;=09=09/* SDMA + 0x7c */
+=09u32 PTDDebug;=09=09/* SDMA + 0x80 */
+};
+
+/* GPT */
+struct mpc52xx_gpt {
+=09u32 mode;=09=09/* GPTx + 0x00 */
+=09u32 count;=09=09/* GPTx + 0x04 */
+=09u32 pwm;=09=09/* GPTx + 0x08 */
+=09u32 status;=09=09/* GPTx + 0X0c */
+};
+
+/* GPIO */
+struct mpc52xx_gpio {
+=09u32 port_config;=09/* GPIO + 0x00 */
+=09u32 simple_gpioe;=09/* GPIO + 0x04 */
+=09u32 simple_ode;=09=09/* GPIO + 0x08 */
+=09u32 simple_ddr;=09=09/* GPIO + 0x0c */
+=09u32 simple_dvo;=09=09/* GPIO + 0x10 */
+=09u32 simple_ival;=09/* GPIO + 0x14 */
+=09u8 outo_gpioe;=09=09/* GPIO + 0x18 */
+=09u8 reserved1[3];=09/* GPIO + 0x19 */
+=09u8 outo_dvo;=09=09/* GPIO + 0x1c */
+=09u8 reserved2[3];=09/* GPIO + 0x1d */
+=09u8 sint_gpioe;=09=09/* GPIO + 0x20 */
+=09u8 reserved3[3];=09/* GPIO + 0x21 */
+=09u8 sint_ode;=09=09/* GPIO + 0x24 */
+=09u8 reserved4[3];=09/* GPIO + 0x25 */
+=09u8 sint_ddr;=09=09/* GPIO + 0x28 */
+=09u8 reserved5[3];=09/* GPIO + 0x29 */
+=09u8 sint_dvo;=09=09/* GPIO + 0x2c */
+=09u8 reserved6[3];=09/* GPIO + 0x2d */
+=09u8 sint_inten;=09=09/* GPIO + 0x30 */
+=09u8 reserved7[3];=09/* GPIO + 0x31 */
+=09u16 sint_itype;=09=09/* GPIO + 0x34 */
+=09u16 reserved8;=09=09/* GPIO + 0x36 */
+=09u8 gpio_control;=09/* GPIO + 0x38 */
+=09u8 reserved9[3];=09/* GPIO + 0x39 */
+=09u8 sint_istat;=09=09/* GPIO + 0x3c */
+=09u8 sint_ival;=09=09/* GPIO + 0x3d */
+=09u8 bus_errs;=09=09/* GPIO + 0x3e */
+=09u8 reserved10;=09=09/* GPIO + 0x3f */
+};
+
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD=094
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD=095
+#define MPC52xx_GPIO_PCI_DIS=09=09=09(1<<15)
+
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+=09u8 wkup_gpioe;=09=09/* GPIO_WKUP + 0x00 */
+=09u8 reserved1[3];=09/* GPIO_WKUP + 0x03 */
+=09u8 wkup_ode;=09=09/* GPIO_WKUP + 0x04 */
+=09u8 reserved2[3];=09/* GPIO_WKUP + 0x05 */
+=09u8 wkup_ddr;=09=09/* GPIO_WKUP + 0x08 */
+=09u8 reserved3[3];=09/* GPIO_WKUP + 0x09 */
+=09u8 wkup_dvo;=09=09/* GPIO_WKUP + 0x0C */
+=09u8 reserved4[3];=09/* GPIO_WKUP + 0x0D */
+=09u8 wkup_inten;=09=09/* GPIO_WKUP + 0x10 */
+=09u8 reserved5[3];=09/* GPIO_WKUP + 0x11 */
+=09u8 wkup_iinten;=09=09/* GPIO_WKUP + 0x14 */
+=09u8 reserved6[3];=09/* GPIO_WKUP + 0x15 */
+=09u16 wkup_itype;=09=09/* GPIO_WKUP + 0x18 */
+=09u8 reserved7[2];=09/* GPIO_WKUP + 0x1A */
+=09u8 wkup_maste;=09=09/* GPIO_WKUP + 0x1C */
+=09u8 reserved8[3];=09/* GPIO_WKUP + 0x1D */
+=09u8 wkup_ival;=09=09/* GPIO_WKUP + 0x20 */
+=09u8 reserved9[3];=09/* GPIO_WKUP + 0x21 */
+=09u8 wkup_istat;=09=09/* GPIO_WKUP + 0x24 */
+=09u8 reserved10[3];=09/* GPIO_WKUP + 0x25 */
+};
+
+/* XLB Bus control */
+struct mpc52xx_xlb {
+=09u8 reserved[0x40];
+=09u32 config;=09=09/* XLB + 0x40 */
+=09u32 version;=09=09/* XLB + 0x44 */
+=09u32 status;=09=09/* XLB + 0x48 */
+=09u32 int_enable;=09=09/* XLB + 0x4c */
+=09u32 addr_capture;=09/* XLB + 0x50 */
+=09u32 bus_sig_capture;=09/* XLB + 0x54 */
+=09u32 addr_timeout;=09/* XLB + 0x58 */
+=09u32 data_timeout;=09/* XLB + 0x5c */
+=09u32 bus_act_timeout;=09/* XLB + 0x60 */
+=09u32 master_pri_enable;=09/* XLB + 0x64 */
+=09u32 master_priority;=09/* XLB + 0x68 */
+=09u32 base_address;=09/* XLB + 0x6c */
+=09u32 snoop_window;=09/* XLB + 0x70 */
+};
+
+#define MPC52xx_XLB_CFG_PLDIS=09=09(1 << 31)
+#define MPC52xx_XLB_CFG_SNOOP=09=09(1 << 15)
+
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+=09u32 jtag_id;=09=09/* CDM + 0x00 reg0 read only */
+=09u32 rstcfg;=09=09/* CDM + 0x04 reg1 read only */
+=09u32 breadcrumb;=09=09/* CDM + 0x08 reg2 */
+
+=09u8 mem_clk_sel;=09=09/* CDM + 0x0c reg3 byte0 */
+=09u8 xlb_clk_sel;=09=09/* CDM + 0x0d reg3 byte1 read only */
+=09u8 ipb_clk_sel;=09=09/* CDM + 0x0e reg3 byte2 */
+=09u8 pci_clk_sel;=09=09/* CDM + 0x0f reg3 byte3 */
+
+=09u8 ext_48mhz_en;=09/* CDM + 0x10 reg4 byte0 */
+=09u8 fd_enable;=09=09/* CDM + 0x11 reg4 byte1 */
+=09u16 fd_counters;=09/* CDM + 0x12 reg4 byte2,3 */
+
+=09u32 clk_enables;=09/* CDM + 0x14 reg5 */
+
+=09u8 osc_disable;=09=09/* CDM + 0x18 reg6 byte0 */
+=09u8 reserved0[3];=09/* CDM + 0x19 reg6 byte1,2,3 */
+
+=09u8 ccs_sleep_enable;=09/* CDM + 0x1c reg7 byte0 */
+=09u8 osc_sleep_enable;=09/* CDM + 0x1d reg7 byte1 */
+=09u8 reserved1;=09=09/* CDM + 0x1e reg7 byte2 */
+=09u8 ccs_qreq_test;=09/* CDM + 0x1f reg7 byte3 */
+
+=09u8 soft_reset;=09=09/* CDM + 0x20 u8 byte0 */
+=09u8 no_ckstp;=09=09/* CDM + 0x21 u8 byte0 */
+=09u8 reserved2[2];=09/* CDM + 0x22 u8 byte1,2,3 */
+
+=09u8 pll_lock;=09=09/* CDM + 0x24 reg9 byte0 */
+=09u8 pll_looselock;=09/* CDM + 0x25 reg9 byte1 */
+=09u8 pll_sm_lockwin;=09/* CDM + 0x26 reg9 byte2 */
+=09u8 reserved3;=09=09/* CDM + 0x27 reg9 byte3 */
+
+=09u16 reserved4;=09=09/* CDM + 0x28 reg10 byte0,1 */
+=09u16 mclken_div_psc1;=09/* CDM + 0x2a reg10 byte2,3 */
+
+=09u16 reserved5;=09=09/* CDM + 0x2c reg11 byte0,1 */
+=09u16 mclken_div_psc2;=09/* CDM + 0x2e reg11 byte2,3 */
+
+=09u16 reserved6;=09=09/* CDM + 0x30 reg12 byte0,1 */
+=09u16 mclken_div_psc3;=09/* CDM + 0x32 reg12 byte2,3 */
+
+=09u16 reserved7;=09=09/* CDM + 0x34 reg13 byte0,1 */
+=09u16 mclken_div_psc6;=09/* CDM + 0x36 reg13 byte2,3 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
*/
+/* Prototypes for MPC52xx sysdev =
*/
+/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
*/
+
+#ifndef __ASSEMBLY__
+
+extern void mpc52xx_init_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_POWERPC_MPC52xx_H__ */
+
^ permalink raw reply
* Re: [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Nicolas DET @ 2006-11-07 9:22 UTC (permalink / raw)
To: Sylvain Munaut; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <454FC6B2.10909@246tNt.com>
[-- Attachment #1: Type: text/plain, Size: 1494 bytes --]
Sylvain Munaut wrote:
>> +
>> + /*
>> + * Most of ours IRQs will be level low
>> + * Only external IRQs on some platform may be others
>> + */
>> + type = IRQ_TYPE_LEVEL_LOW;
>>
> I've been wondering : Why LEVEL_LOW ?
> Aren't they LEVEL_HIGH ?
> (not that it changes much here ...)
>
It makes only sense for the ext interrupts and not for the internal
peripherals.
I made everything level low because it's quiet common (for example:
PCI). Moreover, On our hardware (Efika) the IRQ[0-3] are dedicated to
the PCI.
Anyway, as the current code looks inside the chipset register to
retrieve the real settings, the 'type' vaiiable will be overwrite if
require.
In my opinion, others platforms (without proper hw init by the firmware)
may overwrite the external interrupt control reg in their platforms
specific part.
>> +
>> +end:
>> + of_node_put(picnode);
>> + of_node_put(sdmanode);
>>
> Is of_node_put specified as resilient to NULL argument ? (in the error
> path, that could happen)
of_node_put() is said to be NULL pointer safe.
>
> Also, I think "PANIC" would be appropriate in the error path. If we
> can't init
> the PIC properly we may as well give up ... It's not like we're going to
> do much
> without it ...
>
Well, panic or not your board won't do much ;-)
Moreover, the serial console should work a bit without interrupt.
On another hand, init_IRQ may return a value to indicate it succeed or
not. but, this is beyound the scope of this patch.
Regards,
[-- Attachment #2: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: [RFC/PATCH 6/7] MPIC MSI backend
From: Benjamin Herrenschmidt @ 2006-11-07 9:16 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Greg Kroah-Hartman, linuxppc-dev, Eric W. Biederman, linux-pci,
David S. Miller
In-Reply-To: <3210FBE5-5F22-4759-A728-A98175A435D6@kernel.crashing.org>
> > Yes, I will do a cleanup pass on the MPIC code there. I think it
> > should
> > only program the chip for polarity/sense in startup() and thus can
> > "override" the native LSI setting of that vector when the interrupt is
> > flagged as MSI without actually losing the original information.
>
> You mean when we (in the future) reserve a range of vectors
> for MSI allocation at MPIC startup? Sure, that works.
Not only, even with the current code... basically keep the
sense/polarity flags of the LSI intact in the irq_desc, just add the
IRQF_MSI bit to "override" them when we configure the interrupt to be an
MSI. Then, irq_chip->startup() instead of set_irq_type() does the actual
configuration of the MPIC and, seeing the IRQF_MSI flags, does the right
thing.
That way, when restoring the IRQ back to LSI, we just clear IRQF_MSI and
the old sense/polarity settings will still be there in the descriptor
and MPIC will do the right thing on the next startup().
> ["The PCIe slot" == the 16x PCIe slot on PowerMacs here, for
> the record; it isn't connected over a bridge to HT, but is
> directly connected to the CPC945 (U4) chip.]
Yup, the Attu if you prefer :-)
> There are more problems there (with this current code): the LSI
> IRQ will always be #3, which cannot be used as an MSI IRQ;
Are you sure about that ? In this case, we need a special kludge for
now. I though the MSI stuff could override any of the MPIC vectors, but
you might well be right there, it might not work with the U4 internal
ones.
> and the MSI address to use can not be found on a parent HT bridge
> (as there is none, duh). That last problem makes the patch
> perfectly safe for the CPC945 PCIe port though :-)
Yes, I know :-) We need specific code to discover that a device is
hanging off the Attu instead of HT. I already explained it all to
Michael, it shouldn't be too hard. I even have a card setup to test it,
just didn't have time to do it just yet.
> Can't we just check here? If not, what's the point of having
> a return code here? although doing the check in check() might
> be conceptually nicer, sure.
Yes, nicer and avoids going all the way to allocating stuff and then
having to de-allocate.
Ben.
^ permalink raw reply
* Re: [RFC/PATCH 6/7] MPIC MSI backend
From: Segher Boessenkool @ 2006-11-07 9:04 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Greg Kroah-Hartman, linuxppc-dev, Eric W. Biederman, linux-pci,
David S. Miller
In-Reply-To: <1162888963.28571.459.camel@localhost.localdomain>
> Agreed, though I prefer the naming to be ht_find_capability().
Of course, I just took "_msi" out of the name here ;-)
> Yes, I will do a cleanup pass on the MPIC code there. I think it
> should
> only program the chip for polarity/sense in startup() and thus can
> "override" the native LSI setting of that vector when the interrupt is
> flagged as MSI without actually losing the original information.
You mean when we (in the future) reserve a range of vectors
for MSI allocation at MPIC startup? Sure, that works.
> Right now, as you noticed, it's a non-issue for MSIs coming off HT, as
> both HT interrupts and MSIs are programmed to be edge in the MPIC
> itself, however, this is not ok with interrupts from the PCIe slot fow
> which, according to the device-tree on my Quad G5, the LSI is level
> low.
["The PCIe slot" == the 16x PCIe slot on PowerMacs here, for
the record; it isn't connected over a bridge to HT, but is
directly connected to the CPC945 (U4) chip.]
There are more problems there (with this current code): the LSI
IRQ will always be #3, which cannot be used as an MSI IRQ; and
the MSI address to use can not be found on a parent HT bridge
(as there is none, duh). That last problem makes the patch
perfectly safe for the CPC945 PCIe port though :-)
> Something else I'd like to do is add a generic IRQF_MSI purely for the
> sake of displaying "MSI" instead of "Edge" in /proc/interrupts :-)
Yes definitely.
> Though it might be useful for some backends to track what interrupts
> have been configured as MSI too.
That, too.
>>> ++static int msi_mpic_setup_msi_msg(struct pci_dev *pdev,
>>> + struct msix_entry *entry, struct msi_msg *msg, int type)
>>> +{
>>> + u64 addr;
>>> +
>>> + addr = find_ht_magic_addr(pdev);
>>> + msg->address_lo = addr & 0xFFFFFFFF;
>>> + msg->address_hi = addr >> 32;
>>
>> You don't seem the check whether the "magic address" is outside
>> of 32-bit range and the device can do 32-bit only?
>
> Good point. It happens not to be on our chipset / firmware but we
> should
> probably check in the check() callback. If it's the case, then we
> refuse
> to enable MSI for that device.
Can't we just check here? If not, what's the point of having
a return code here? although doing the check in check() might
be conceptually nicer, sure.
Segher
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox