* Re: [PATCH 8/13] powerpc: Add arch/powerpc mv64x60_eth platform data setup
From: Arnd Bergmann @ 2007-04-26 0:18 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
In-Reply-To: <20070426000009.GJ4046@mag.az.mvista.com>
On Thursday 26 April 2007, Mark A. Greer wrote:
> Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> --- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/mv64x60.c
> +++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c
> @@ -511,3 +511,138 @@ ret_node_put:
> =A0}
> =A0
> =A0arch_initcall(mv64x60_mpsc_platform_device_init);
> +
> +/*
> + * Create mv64x60_eth platform device
> + */
> +static int __init eth_register_shared_pdev(struct device_node *np)
> +{
> +=A0=A0=A0=A0=A0=A0=A0struct platform_device *pdev;
No need to put this into architecture specific code, just register
the of_platform_driver from mv643xx_init_module and use the device
you get passed in there.
Once arch/ppc is dead, you can remove the platform_driver from mv643xx
entirely.
Arnd <><
^ permalink raw reply
* Re: [PATCH 7/13] powerpc: Add arch/powerpc mv64x60 MPSC platform data setup
From: Arnd Bergmann @ 2007-04-26 0:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
In-Reply-To: <20070425235939.GI4046@mag.az.mvista.com>
On Thursday 26 April 2007, Mark A. Greer wrote:
> +static int __init mv64x60_mpsc_platform_device_init(void)
> +{
> +=A0=A0=A0=A0=A0=A0=A0struct device_node *np =3D NULL;
> +=A0=A0=A0=A0=A0=A0=A0unsigned int i;
> +=A0=A0=A0=A0=A0=A0=A0struct platform_device *pdev;
> +=A0=A0=A0=A0=A0=A0=A0int err;
> +
> +=A0=A0=A0=A0=A0=A0=A0for (i =3D 0; (np =3D of_find_compatible_node(np, "=
serial", "mpsc")); i++) {
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0struct resource r[5];
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0struct mpsc_pdata pdata;
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0const unsigned int *prop;
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0const phandle *ph;
> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0struct device_node *sdma, *=
brg;
This looks wrong to me. See drivers/serial/of_serial.c to find how we do it=
for
8250 compatible serial ports. You should probably just add your serial port
stuff in there as well, instead of doing your own scanning of the device tr=
ee.
> + pdev =3D platform_device_register_simple(MPSC_CTLR_NAME, =
i, r, 5);
> + if (IS_ERR(pdev)) {
> + err =3D PTR_ERR(pdev);
> + goto ret_node_put;
> + }
Now this really needs some explanation.
Why the heck do you have a platform device that gets its resources from
nonstandard properties of a serial port?
Arnd <><
^ permalink raw reply
* Re: Serial console via SCC2 on Mpc8xx
From: Wolfgang Denk @ 2007-04-26 0:14 UTC (permalink / raw)
To: JSL; +Cc: linuxppc-embedded
In-Reply-To: <00bc01c7876e$57a60980$6501a8c0@KontorPC>
In message <00bc01c7876e$57a60980$6501a8c0@KontorPC> you wrote:
>
> Has anyone had success with SCC2 as serial console instead of SMC1/2
Yes.
> uart. Has not yet found any Linux that have support for that when
> lokking at Linux 2.6 or 2.4 for MPC860P
Our 2.4.25 kernel tree supports serial console on any of the SMC1...2
and SCC1...4 ports (at least on the boards that support that).
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk
Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Accident: A condition in which presence of mind is good, but absence
of body is better.
^ permalink raw reply
* Re: [PATCH] [2.6.22] pasemi: hardware rng driver
From: Olof Johansson @ 2007-04-26 0:09 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linuxppc-dev, egor, mb
In-Reply-To: <200704260138.32220.arnd@arndb.de>
On Thu, Apr 26, 2007 at 01:38:31AM +0200, Arnd Bergmann wrote:
> On Wednesday 25 April 2007, Olof Johansson wrote:
>
> > +static void __iomem *rng_regs;
> > +
> > +static int pasemi_rng_data_present(struct hwrng *rng)
> > +{
> > + return (in_le32(rng_regs + SDCRNG_CTL_REG)
> > + & SDCRNG_CTL_FVLD_M) ? 1 : 0;
> > +}
>
> It would be nicer to get rid of the global rng_regs variable by sticking
> it into rng->priv.
Good point.
> > +static int __devinit rng_probe(struct of_device *ofdev,
> > + const struct of_device_id *match)
> > +{
> > + struct device_node *rng_np;
> > + struct resource res;
> > + int err = 0;
> > +
> > + rng_np = of_find_compatible_node(NULL, "rng", "1682m-rng");
> > + if (!rng_np)
> > + return -ENODEV;
>
> I would guess that the call to of_find_compatible_node is entirely bogus
> here, because the device is already passed in as ofdev in to the probe
> function.
Yup. Leftover from pre-of_platform
> > +int rng_init(void)
> > +{
> > + return of_register_platform_driver(&rng_driver);
> > +}
> > +
> > +void rng_exit(void)
> > +{
> > + of_unregister_platform_driver(&rng_driver);
> > +}
> > +
> > +device_initcall(rng_init);
>
> rng_init and rng_exit should be static
> rng_init should be __init
> rng_exit should be __exit
> Since the driver is tristate in Kconfig, it would be more conventional to
> use module_init() instead of device_initcall().
> rng_exit needs to be marked as module_exit() to allow unloading the driver.
Yup, will fix.
Thanks.
-Olof
^ permalink raw reply
* Re: [PATCH] powerpc: Add EDAC platform devices for 85xx
From: David Gibson @ 2007-04-26 0:08 UTC (permalink / raw)
To: Dave Jiang; +Cc: linuxppc-dev
In-Reply-To: <20070425213700.GA8814@blade.az.mvista.com>
On Wed, Apr 25, 2007 at 02:37:00PM -0700, Dave Jiang wrote:
> Add memory controller and l2-cache controller entries in the dts files for 85xx
> platforms. Also adding code to create the platform devices used by EDAC drivers
> to claim the resources in order to access the error registers and interrupts.
>
> Signed-off-by: Dave Jiang <djiang@mvista.com>
>
> ---
>
> arch/powerpc/boot/dts/mpc8540ads.dts | 21 ++++++
> arch/powerpc/boot/dts/mpc8548cds.dts | 21 ++++++
> arch/powerpc/boot/dts/mpc8560ads.dts | 23 +++++++-
> arch/powerpc/sysdev/fsl_soc.c | 115 ++++++++++++++++++++++++++++++++++
> 4 files changed, 179 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
> index f261d64..8bb7593 100644
> --- a/arch/powerpc/boot/dts/mpc8540ads.dts
> +++ b/arch/powerpc/boot/dts/mpc8540ads.dts
> @@ -48,6 +48,27 @@
> reg = <e0000000 00100000>; // CCSRBAR 1M
> bus-frequency = <0>;
>
> + mem-ctrl@2000 {
> + device_type = "mem-ctrl";
> + compatible = "85xx";
> + reg = <2000 1000>;
> + linux,phandle = <2000>;
> + interrupt-parent = <40000>;
Please don't use explicit phandles. Use dtc's label feature where you
need to put phandles into properties.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: powerpc: Abolish PHYS_FMT macro from arch/powerpc
From: David Gibson @ 2007-04-25 0:51 UTC (permalink / raw)
To: Linas Vepstas; +Cc: Paul Mackerras, linuxppc-dev
In-Reply-To: <20070424170052.GW31947@austin.ibm.com>
On Tue, Apr 24, 2007 at 12:00:52PM -0500, Linas Vepstas wrote:
> On Tue, Apr 24, 2007 at 03:05:18PM +1000, David Gibson wrote:
> > 32-bit powerpc systems define a macro, PHYS_FMT, giving a printf
>
> Your patch removed the use of the macro, but does not remove the definition
> of the macro.
Yes, that's because the definition is in asm-ppc, and it's still used
in asm-ppc. My upcoming patches which start to remove arch/powerpc's
final dependencies on asm-ppc won't be moving PHYS_FMT across.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* [PATCH 13/13] powerpc: Add arch/powerpc support for the Motorola PrPMC2800 platform
From: Mark A. Greer @ 2007-04-26 0:02 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
---
Kconfig | 2
configs/prpmc2800_defconfig | 1437 ++++++++++++++++++++++++++++++++++++++
platforms/embedded6xx/Kconfig | 9
platforms/embedded6xx/Makefile | 1
platforms/embedded6xx/prpmc2800.c | 169 ++++
5 files changed, 1617 insertions(+), 1 deletion(-)
Index: powerpc/arch/powerpc/platforms/embedded6xx/Kconfig
===================================================================
--- powerpc.orig/arch/powerpc/platforms/embedded6xx/Kconfig
+++ powerpc/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -25,6 +25,15 @@ config MPC7448HPC2
help
Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga)
platform
+
+config PPC_PRPMC2800
+ bool "Motorola-PrPMC2800"
+ select MV64X60
+ select NOT_COHERENT_CACHE
+ select WANT_DEVICE_TREE
+ help
+ This option enables support for the Motorola PrPMC2800 board
+
endchoice
config TSI108_BRIDGE
Index: powerpc/arch/powerpc/platforms/embedded6xx/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/platforms/embedded6xx/Makefile
+++ powerpc/arch/powerpc/platforms/embedded6xx/Makefile
@@ -3,3 +3,4 @@
#
obj-$(CONFIG_MPC7448HPC2) += mpc7448_hpc2.o
obj-$(CONFIG_LINKSTATION) += linkstation.o ls_uart.o
+obj-$(CONFIG_PPC_PRPMC2800) += prpmc2800.o
Index: powerpc/arch/powerpc/platforms/embedded6xx/prpmc2800.c
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/platforms/embedded6xx/prpmc2800.c
@@ -0,0 +1,169 @@
+/*
+ * Board setup routines for the Motorola PrPMC2800
+ *
+ * Author: Dale Farnsworth <dale@farnsworth.org>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/seq_file.h>
+
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/kexec.h>
+
+#include <mm/mmu_decl.h>
+
+#include <sysdev/mv64x60.h>
+
+#define MV64x60_MPP_CNTL_0 0x0000
+#define MV64x60_MPP_CNTL_2 0x0008
+
+#define MV64x60_GPP_IO_CNTL 0x0000
+#define MV64x60_GPP_LEVEL_CNTL 0x0010
+#define MV64x60_GPP_VALUE_SET 0x0018
+
+#define PLATFORM_NAME_MAX 32
+
+static char prpmc2800_platform_name[PLATFORM_NAME_MAX];
+
+static void __iomem *mv64x60_mpp_reg_base;
+static void __iomem *mv64x60_gpp_reg_base;
+
+static void __init prpmc2800_setup_arch(void)
+{
+ struct device_node *np;
+ phys_addr_t paddr;
+ const unsigned int *reg;
+ const unsigned int *prop;
+
+ /*
+ * ioremap mpp and gpp registers in case they are later
+ * needed by prpmc2800_reset_board().
+ */
+ np = of_find_compatible_node(NULL, NULL, "mv64x60-mpp");
+ reg = of_get_property(np, "reg", NULL);
+ paddr = of_translate_address(np, reg);
+ of_node_put(np);
+ mv64x60_mpp_reg_base = ioremap(paddr, reg[1]);
+
+ np = of_find_compatible_node(NULL, NULL, "mv64x60-gpp");
+ reg = of_get_property(np, "reg", NULL);
+ paddr = of_translate_address(np, reg);
+ of_node_put(np);
+ mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
+
+ np = of_find_node_by_type(NULL, "cpu");
+ prop = of_get_property(np, "clock-frequency", NULL);
+ if (prop)
+ loops_per_jiffy = *prop / HZ;
+ of_node_put(np);
+
+ mv64x60_pci_init();
+
+ printk("Motorola %s\n", prpmc2800_platform_name);
+}
+
+static void prpmc2800_reset_board(void)
+{
+ u32 temp;
+
+ local_irq_disable();
+
+ temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0);
+ temp &= 0xFFFF0FFF;
+ out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0, temp);
+
+ temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
+ temp |= 0x00000004;
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp);
+
+ temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
+ temp |= 0x00000004;
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp);
+
+ temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2);
+ temp &= 0xFFFF0FFF;
+ out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2, temp);
+
+ temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
+ temp |= 0x00080000;
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp);
+
+ temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
+ temp |= 0x00080000;
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp);
+
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_VALUE_SET, 0x00080004);
+}
+
+static void prpmc2800_restart(char *cmd)
+{
+ volatile ulong i = 10000000;
+
+ prpmc2800_reset_board();
+
+ while (i-- > 0);
+ panic("restart failed\n");
+}
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PPRPM2800_COHERENCY_SETTING "off"
+#else
+#define PPRPM2800_COHERENCY_SETTING "on"
+#endif
+
+void prpmc2800_show_cpuinfo(struct seq_file *m)
+{
+ uint memsize = total_memory;
+
+ seq_printf(m, "Vendor\t\t: Motorola\n");
+ seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+ seq_printf(m, "coherency\t: %s\n", PPRPM2800_COHERENCY_SETTING);
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init prpmc2800_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+ unsigned long len = PLATFORM_NAME_MAX;
+ void *m;
+
+ if (!of_flat_dt_is_compatible(root, "PrPMC2800"))
+ return 0;
+
+ /* Update ppc_md.name with name from dt */
+ m = of_get_flat_dt_prop(root, "model", &len);
+ if (m)
+ strncpy(prpmc2800_platform_name, m,
+ min((int)len, PLATFORM_NAME_MAX - 1));
+
+ return 1;
+}
+
+define_machine(prpmc2800){
+ .name = prpmc2800_platform_name,
+ .probe = prpmc2800_probe,
+ .setup_arch = prpmc2800_setup_arch,
+ .show_cpuinfo = prpmc2800_show_cpuinfo,
+ .init_IRQ = mv64x60_init_irq,
+ .get_irq = mv64x60_get_irq,
+ .restart = prpmc2800_restart,
+ .calibrate_decr = generic_calibrate_decr,
+#ifdef CONFIG_KEXEC
+ .machine_kexec = default_machine_kexec,
+ .machine_kexec_prepare = default_machine_kexec_prepare,
+ .machine_crash_shutdown = default_machine_crash_shutdown,
+#endif
+};
Index: powerpc/arch/powerpc/configs/prpmc2800_defconfig
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/configs/prpmc2800_defconfig
@@ -0,0 +1,1437 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.21-rc7
+# Wed Apr 25 12:55:17 2007
+#
+# CONFIG_PPC64 is not set
+CONFIG_PPC32=y
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+# CONFIG_PPC_UDBG_16550 is not set
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+# CONFIG_DEFAULT_UIMAGE is not set
+
+#
+# Processor support
+#
+CONFIG_CLASSIC32=y
+# CONFIG_PPC_82xx is not set
+# CONFIG_PPC_83xx is not set
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_86xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_6xx=y
+CONFIG_PPC_FPU=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_ALTIVEC=y
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_SMP is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Platform support
+#
+# CONFIG_PPC_MULTIPLATFORM is not set
+CONFIG_EMBEDDED6xx=y
+# CONFIG_APUS is not set
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_MPC5200 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_LINKSTATION is not set
+# CONFIG_MPC7448HPC2 is not set
+CONFIG_PPC_PRPMC2800=y
+CONFIG_MV64X60=y
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+
+#
+# CPU Frequency support
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_TAU is not set
+# CONFIG_CPM2 is not set
+
+#
+# Kernel options
+#
+CONFIG_HIGHMEM=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+# CONFIG_KEXEC is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_DEVICE_TREE="prpmc2800.dts"
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+# CONFIG_PPC_INDIRECT_PCI_BE is not set
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCIEPORTBUS is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# OneNAND Flash Device Drivers
+#
+# CONFIG_MTD_ONENAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNPACPI is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# Misc devices
+#
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_OPTI621 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+# CONFIG_IDEDMA_ONLYDISK is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+CONFIG_BLK_DEV_PDC202XX_NEW=y
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+
+#
+# Serial ATA (prod) and Parallel ATA (experimental) drivers
+#
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+CONFIG_SATA_MV=y
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIL24 is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
+# CONFIG_FUSION_SAS is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+# CONFIG_MAC_EMUMOUSEBTN is not set
+# CONFIG_WINDFARM is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_FIXED_PHY is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+# CONFIG_E1000_NAPI is not set
+# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_MV643XX_ETH=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_MPSC=y
+CONFIG_SERIAL_MPSC_CONSOLE=y
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_FB is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# HID Devices
+#
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_SPLIT_ISO is not set
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_HCD_PPC_OF is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_TOUCHSCREEN is not set
+# CONFIG_USB_YEALINK is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+# CONFIG_USB_ATI_REMOTE2 is not set
+# CONFIG_USB_KEYSPAN_REMOTE is not set
+# CONFIG_USB_APPLETOUCH is not set
+# CONFIG_USB_GTCO is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+#
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+
+#
+# RTC drivers
+#
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_TEST is not set
+CONFIG_RTC_DRV_MAX6900=y
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# Auxiliary Display support
+#
+
+#
+# Virtualization
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+# CONFIG_UCC_SLOW is not set
+# CONFIG_UCC_FAST is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+
+#
+# Instrumentation Support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
Index: powerpc/arch/powerpc/Kconfig
===================================================================
--- powerpc.orig/arch/powerpc/Kconfig
+++ powerpc/arch/powerpc/Kconfig
@@ -431,7 +431,7 @@ config ARCH_ENABLE_MEMORY_HOTPLUG
config KEXEC
bool "kexec system call (EXPERIMENTAL)"
- depends on PPC_MULTIPLATFORM && EXPERIMENTAL
+ depends on (PPC_PRPMC2800 || PPC_MULTIPLATFORM) && EXPERIMENTAL
help
kexec is a system call that implements the ability to shutdown your
current kernel, and to start another kernel. It is like a reboot
^ permalink raw reply
* [PATCH 12/13] powerpc: Add bootwrapper support for Motorola PrPMC2800 platform
From: Mark A. Greer @ 2007-04-26 0:02 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
Add support for Motorola ECC PrPMC280/PrPMC2800 Platform.
The PrPMC280 sits on an F101 baseboard and the PrPMC2800 sits on a
F101e baseboard. Logic has been added to determine which board
(and variant thereof) the code is being run on.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
Makefile | 3
prpmc2800.c | 566 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 568 insertions(+), 1 deletion(-)
Index: powerpc/arch/powerpc/boot/prpmc2800.c
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/prpmc2800.c
@@ -0,0 +1,566 @@
+/*
+ * Motorola ECC prpmc280/f101 & prpmc2800/f101e platform code.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "page.h"
+#include "string.h"
+#include "stdio.h"
+#include "io.h"
+#include "ops.h"
+#include "gunzip_util.h"
+#include "mv64x60.h"
+
+extern char _end[];
+extern char _vmlinux_start[], _vmlinux_end[];
+extern char _dtb_start[], _dtb_end[];
+
+#define KB 1024U
+#define MB (KB*KB)
+#define GB (KB*MB)
+#define MHz (1000U*1000U)
+#define GHz (1000U*MHz)
+
+#define BOARD_MODEL "PrPMC2800"
+#define BOARD_MODEL_MAX 32 /* max strlen(BOARD_MODEL) + 1 */
+
+#define EEPROM2_ADDR 0xa4
+#define EEPROM3_ADDR 0xa8
+
+BSS_STACK(16*KB);
+
+static u8 *bridge_base;
+
+typedef enum {
+ BOARD_MODEL_PRPMC280,
+ BOARD_MODEL_PRPMC2800,
+} prpmc2800_board_model;
+
+typedef enum {
+ BRIDGE_TYPE_MV64360,
+ BRIDGE_TYPE_MV64362,
+} prpmc2800_bridge_type;
+
+struct prpmc2800_board_info {
+ prpmc2800_board_model model;
+ char variant;
+ prpmc2800_bridge_type bridge_type;
+ u8 subsys0;
+ u8 subsys1;
+ u8 vpd4;
+ u8 vpd4_mask;
+ u32 core_speed;
+ u32 mem_size;
+ u32 boot_flash;
+ u32 user_flash;
+};
+
+static struct prpmc2800_board_info prpmc2800_board_info[] = {
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'a',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 1*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'b',
+ .bridge_type = BRIDGE_TYPE_MV64362,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x01,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 0,
+ .user_flash = 0,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'c',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x02,
+ .vpd4_mask = 0x0f,
+ .core_speed = 733*MHz,
+ .mem_size = 512*MB,
+ .boot_flash = 1*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'd',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x03,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 1*GB,
+ .boot_flash = 1*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'e',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x04,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 1*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'f',
+ .bridge_type = BRIDGE_TYPE_MV64362,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x05,
+ .vpd4_mask = 0x0f,
+ .core_speed = 733*MHz,
+ .mem_size = 128*MB,
+ .boot_flash = 1*MB,
+ .user_flash = 0,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'g',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x06,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 256*MB,
+ .boot_flash = 1*MB,
+ .user_flash = 0,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'h',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x07,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 1*GB,
+ .boot_flash = 1*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'a',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xb2,
+ .subsys1 = 0x8c,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'b',
+ .bridge_type = BRIDGE_TYPE_MV64362,
+ .subsys0 = 0xb2,
+ .subsys1 = 0x8d,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 0,
+ .user_flash = 0,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'c',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xb2,
+ .subsys1 = 0x8e,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 733*MHz,
+ .mem_size = 512*MB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'd',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xb2,
+ .subsys1 = 0x8f,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 1*GHz,
+ .mem_size = 1*GB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'e',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xa2,
+ .subsys1 = 0x8a,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'f',
+ .bridge_type = BRIDGE_TYPE_MV64362,
+ .subsys0 = 0xa2,
+ .subsys1 = 0x8b,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 733*MHz,
+ .mem_size = 128*MB,
+ .boot_flash = 2*MB,
+ .user_flash = 0,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'g',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xa2,
+ .subsys1 = 0x8c,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 1*GHz,
+ .mem_size = 2*GB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'h',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xa2,
+ .subsys1 = 0x8d,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 733*MHz,
+ .mem_size = 1*GB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+};
+
+static struct prpmc2800_board_info *prpmc2800_get_board_info(u8 *vpd)
+{
+ struct prpmc2800_board_info *bip;
+ int i;
+
+ for (i=0,bip=prpmc2800_board_info; i<ARRAY_SIZE(prpmc2800_board_info);
+ i++,bip++)
+ if ((vpd[0] == bip->subsys0) && (vpd[1] == bip->subsys1)
+ && ((vpd[4] & bip->vpd4_mask) == bip->vpd4))
+ return bip;
+
+ return NULL;
+}
+
+/* Get VPD from i2c eeprom 2, then match it to a board info entry */
+static struct prpmc2800_board_info *prpmc2800_get_bip(void)
+{
+ struct prpmc2800_board_info *bip;
+ u8 vpd[5];
+ int rc;
+
+ if (mv64x60_i2c_open())
+ fatal("Error: Can't open i2c device\n\r");
+
+ /* Get VPD from i2c eeprom-2 */
+ memset(vpd, 0, sizeof(vpd));
+ rc = mv64x60_i2c_read(EEPROM2_ADDR, vpd, 0x1fde, 2, sizeof(vpd));
+ if (rc < 0)
+ fatal("Error: Couldn't read eeprom2\n\r");
+ mv64x60_i2c_close();
+
+ /* Get board type & related info */
+ bip = prpmc2800_get_board_info(vpd);
+ if (bip == NULL) {
+ printf("Error: Unsupported board or corrupted VPD:\n\r");
+ fatal(" 0x%x 0x%x 0x%x 0x%x 0x%x\n\r",
+ vpd[0], vpd[1], vpd[2], vpd[3], vpd[4]);
+ }
+
+ return bip;
+}
+
+static void prpmc2800_bridge_setup(struct prpmc2800_board_info *bip)
+{
+ u32 i, v[12], enables, acc_bits;
+ u32 pci_base_hi, pci_base_lo, size, buf[2];
+ unsigned long cpu_base;
+ int rc;
+ void *devp;
+ u8 *bridge_pbase, is_coherent;
+ struct mv64x60_cpu2pci_win *tbl;
+
+ bridge_pbase = mv64x60_get_bridge_pbase();
+ is_coherent = mv64x60_is_coherent();
+
+ if (is_coherent)
+ acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB
+ | MV64x60_PCI_ACC_CNTL_SWAP_NONE
+ | MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES
+ | MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES;
+ else
+ acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE
+ | MV64x60_PCI_ACC_CNTL_SWAP_NONE
+ | MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES
+ | MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES;
+
+ mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
+ mv64x60_config_pci_windows(bridge_base, bridge_pbase, 0, 0,
+ bip->mem_size, acc_bits);
+
+ /* Get the cpu -> pci i/o & mem mappings from the device tree */
+ devp = finddevice("/mv64x60/pci@80000000");
+ if (devp == NULL)
+ fatal("Error: Missing /mv64x60/pci@80000000"
+ " device tree node\n\r");
+
+ rc = getprop(devp, "ranges", v, sizeof(v));
+ if (rc != sizeof(v))
+ fatal("Error: Can't find /mv64x60/pci@80000000/ranges"
+ " property\n\r");
+
+ /* Get the cpu -> pci i/o & mem mappings from the device tree */
+ devp = finddevice("/mv64x60");
+ if (devp == NULL)
+ fatal("Error: Missing /mv64x60 device tree node\n\r");
+
+ enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
+ enables |= 0x0007fe00; /* Disable all cpu->pci windows */
+ out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
+
+ for (i=0; i<12; i+=6) {
+ switch (v[i] & 0xff000000) {
+ case 0x01000000: /* PCI I/O Space */
+ tbl = mv64x60_cpu2pci_io;
+ break;
+ case 0x02000000: /* PCI MEM Space */
+ tbl = mv64x60_cpu2pci_mem;
+ break;
+ default:
+ continue;
+ }
+
+ pci_base_hi = v[i+1];
+ pci_base_lo = v[i+2];
+ cpu_base = v[i+3];
+ size = v[i+5];
+
+ buf[0] = cpu_base;
+ buf[1] = size;
+
+ if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
+ fatal("Error: Can't translate PCI address 0x%x\n\r",
+ (u32)cpu_base);
+
+ mv64x60_config_cpu2pci_window(bridge_base, 0, pci_base_hi,
+ pci_base_lo, cpu_base, size, tbl);
+ }
+
+ enables &= ~0x00000600; /* Enable cpu->pci0 i/o, cpu->pci0 mem0 */
+ out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
+}
+
+/* XXX turn off WDT, DMA engines, timers */
+
+static void prpmc2800_fixups(void)
+{
+ u32 v[2], l;
+ int rc;
+ void *devp;
+ char model[BOARD_MODEL_MAX];
+ struct prpmc2800_board_info *bip;
+
+ bip = prpmc2800_get_bip(); /* Get board info based on VPD */
+ prpmc2800_bridge_setup(bip); /* Do necessary bridge setup */
+
+ /* Now fixup device tree properties */
+ /* Set /model appropriately */
+ devp = finddevice("/");
+ if (devp == NULL)
+ fatal("Error: Missing '/' device tree node\n\r");
+ memset(model, 0, BOARD_MODEL_MAX);
+ strncpy(model, BOARD_MODEL, BOARD_MODEL_MAX - 2);
+ l = strlen(model);
+ if (bip->model == BOARD_MODEL_PRPMC280)
+ l--;
+ model[l++] = bip->variant;
+ model[l++] = '\0';
+ setprop(devp, "model", model, l);
+
+ /* Set /cpus/PowerPC,7447/clock-frequency */
+ devp = finddevice("/cpus/PowerPC,7447");
+ if (devp == NULL)
+ fatal("Error: Missing proper /cpus device tree node\n\r");
+ v[0] = bip->core_speed;
+ setprop(devp, "clock-frequency", &v[0], sizeof(v[0]));
+
+ /* Set /memory/reg size */
+ devp = finddevice("/memory");
+ if (devp == NULL)
+ fatal("Error: Missing /memory device tree node\n\r");
+ v[0] = 0;
+ v[1] = bip->mem_size;
+ setprop(devp, "reg", v, sizeof(v));
+
+ /* Update /mv64x60/device_type, if this is a mv64362 */
+ if (bip->bridge_type == BRIDGE_TYPE_MV64362) {
+ devp = finddevice("/mv64x60");
+ if (devp == NULL)
+ fatal("Error: Missing /mv64x60 device tree node\n\r");
+ setprop(devp, "device_type", "mv64362", strlen("mv64362") + 1);
+ }
+
+ /* Set User FLASH size */
+ devp = finddevice("/mv64x60/flash@a0000000");
+ if (devp == NULL)
+ fatal("Error: Missing User FLASH device tree node\n\r");
+ rc = getprop(devp, "reg", v, sizeof(v));
+ if (rc != sizeof(v))
+ fatal("Error: Can't find User FLASH reg property\n\r");
+ v[1] = bip->user_flash;
+ setprop(devp, "reg", v, sizeof(v));
+}
+
+#define MV64x60_MPP_CNTL_0 0xf000
+#define MV64x60_MPP_CNTL_2 0xf008
+#define MV64x60_GPP_IO_CNTL 0xf100
+#define MV64x60_GPP_LEVEL_CNTL 0xf110
+#define MV64x60_GPP_VALUE_SET 0xf118
+
+static void prpmc2800_reset(void)
+{
+ u32 temp;
+
+ if (bridge_base != 0) {
+ temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
+ temp &= 0xFFFF0FFF;
+ out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);
+
+ temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
+ temp |= 0x00000004;
+ out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
+
+ temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
+ temp |= 0x00000004;
+ out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
+
+ temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
+ temp &= 0xFFFF0FFF;
+ out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);
+
+ temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
+ temp |= 0x00080000;
+ out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
+
+ temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
+ temp |= 0x00080000;
+ out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
+
+ out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),
+ 0x00080004);
+ }
+
+ for (;;);
+}
+
+#define HEAP_SIZE (16*MB)
+static struct gunzip_state gzstate;
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ struct elf_info ei;
+ char *heap_start, *dtb;
+ int dt_size = _dtb_end - _dtb_start;
+ void *vmlinuz_addr = _vmlinux_start;
+ unsigned long vmlinuz_size = _vmlinux_end - _vmlinux_start;
+ char elfheader[256];
+
+ if (dt_size <= 0) /* No fdt */
+ exit();
+
+ /*
+ * Start heap after end of the kernel (after decompressed to
+ * address 0) or the end of the zImage, whichever is higher.
+ * That's so things allocated by simple_alloc won't overwrite
+ * any part of the zImage and the kernel won't overwrite the dtb
+ * when decompressed & relocated.
+ */
+ gunzip_start(&gzstate, vmlinuz_addr, vmlinuz_size);
+ gunzip_exactly(&gzstate, elfheader, sizeof(elfheader));
+
+ if (!parse_elf32(elfheader, &ei))
+ exit();
+
+ heap_start = (char *)(ei.memsize + ei.elfoffset); /* end of kernel*/
+ heap_start = max(heap_start, (char *)_end); /* end of zImage */
+
+ if ((unsigned)simple_alloc_init(heap_start, HEAP_SIZE, 2*KB, 16)
+ > (128*MB))
+ exit();
+
+ /* Relocate dtb to safe area past end of zImage & kernel */
+ dtb = malloc(dt_size);
+ if (!dtb)
+ exit();
+ memmove(dtb, _dtb_start, dt_size);
+ if (ft_init(dtb, dt_size, 16))
+ exit();
+
+ bridge_base = mv64x60_get_bridge_base();
+
+ platform_ops.fixups = prpmc2800_fixups;
+ platform_ops.exit = prpmc2800_reset;
+
+ if (serial_console_init() < 0)
+ exit();
+}
+
+/* Following code is put at very beginning of zImage (64KB into ELF file) */
+asm (" .globl _zimage_start\n\
+ _zimage_start:\n\
+ mfmsr 10\n\
+ rlwinm 10,10,0,~(1<<15) /* Clear MSR_EE */\n\
+ sync\n\
+ mtmsr 10\n\
+ isync\n\
+ b _zimage_start_lib\n\
+");
Index: powerpc/arch/powerpc/boot/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/boot/Makefile
+++ powerpc/arch/powerpc/boot/Makefile
@@ -44,7 +44,7 @@ src-wlib := string.S crt0.S stdio.c main
ns16550.c serial.c simple_alloc.c div64.S util.S \
gunzip_util.c elf_util.c devtree.c mv64x60.c mpsc.c \
mv64x60_i2c.c $(zlib)
-src-plat := of.c cuboot-83xx.c
+src-plat := of.c cuboot-83xx.c prpmc2800.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -130,6 +130,7 @@ image-$(CONFIG_PPC_CELLEB) += zImage.ps
image-$(CONFIG_PPC_CHRP) += zImage.chrp
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
+image-$(CONFIG_PPC_PRPMC2800) += zImage.prpmc2800
image-$(CONFIG_DEFAULT_UIMAGE) += uImage cuImage
# For 32-bit powermacs, build the COFF and miboot images
^ permalink raw reply
* [PATCH 11/13] powerpc: Add DTS file for the Motorola PrPMC2800 platform
From: Mark A. Greer @ 2007-04-26 0:01 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
prpmc2800.dts | 322 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 322 insertions(+)
Index: powerpc/arch/powerpc/boot/dts/prpmc2800.dts
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/dts/prpmc2800.dts
@@ -0,0 +1,322 @@
+/* Device Tree Source for Motorola PrPMC2800
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * To build:
+ * dtc -I dts -O asm -o prpmc2800.S -V 16 -b 0 prpmc2800.dts
+ * dtc -I dts -O dtb -o prpmc2800.dtb -V 16 -b 0 prpmc2800.dts
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "PrPMC280/PrPMC2800"; /* Updated by bootwrapper */
+ compatible = "PrPMC2800";
+ coherency-off;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,7447 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <0>; /* Set by bootwrapper */
+ bus-frequency = <7f28155>; /* 133.333333 MHz */
+ timebase-frequency = <1fca055>; /* 33.333333 MHz */
+ /* Following required by dtc but not used */
+ i-cache-line-size = <0>;
+ d-cache-line-size = <0>;
+ i-cache-size = <0>;
+ d-cache-size = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 00000000>; /* Set by bootwrapper */
+ };
+
+ mv64x60@f1000000 { /* Marvell Discovery */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+ device_type = "mv64360";
+ compatible = "mv64x60";
+ clock-frequency = <7f28155>; /* 133.333333 Mhz */
+ reg = <f1000000 00010000>;
+ virtual-reg = <f1000000>;
+ ranges = <88000000 88000000 01000000 /* PCI 0 I/O Space */
+ 80000000 80000000 08000000 /* PCI 0 MEM Space */
+ a0000000 a0000000 04000000 /* User FLASH */
+ 00000000 f1000000 00010000 /* Bridge's regs */
+ f2000000 f2000000 00040000>; /* Integrated SRAM */
+
+ flash@a0000000 {
+ device_type = "rom";
+ compatible = "direct-mapped";
+ reg = <a0000000 0>; /* Size set by bootwrapper */
+ probe-type = "CFI";
+ bank-width = <4>;
+ partitions = <00000000 00100000 /* RO */
+ 00100000 00040001 /* RW */
+ 00140000 00400000 /* RO */
+ 00540000 039c0000 /* RO */
+ 03f00000 00100000>; /* RO */
+ partition-names = "FW Image A\0FW Config Data\0Kernel Image\0Filesystem\0FW Image B";
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "mdio";
+ compatible = "mv64x60-mdio";
+ ethernet-phy@1 {
+ device_type = "ethernet-phy";
+ compatible = "bcm5421";
+ interrupts = <4c>; /* GPP 12 */
+ interrupt-parent = <&/mv64x60/pic>;
+ reg = <1>;
+ };
+ ethernet-phy@3 {
+ device_type = "ethernet-phy";
+ compatible = "bcm5421";
+ interrupts = <4c>; /* GPP 12 */
+ interrupt-parent = <&/mv64x60/pic>;
+ reg = <3>;
+ };
+ };
+
+ ethernet@2000 { /* mac-address set by bootwrapper */
+ reg = <2000 2000>;
+ eth0 {
+ device_type = "network";
+ compatible = "mv64x60-eth";
+ block-index = <0>;
+ interrupts = <20>;
+ interrupt-parent = <&/mv64x60/pic>;
+ phy = <&/mv64x60/mdio/ethernet-phy@1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ eth1 {
+ device_type = "network";
+ compatible = "mv64x60-eth";
+ block-index = <1>;
+ interrupts = <21>;
+ interrupt-parent = <&/mv64x60/pic>;
+ phy = <&/mv64x60/mdio/ethernet-phy@3>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+
+ sdma@4000 {
+ device_type = "dma";
+ compatible = "mv64x60-sdma";
+ reg = <4000 c18>;
+ virtual-reg = <f1004000>;
+ interrupt-base = <0>;
+ interrupts = <24>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ sdma@6000 {
+ device_type = "dma";
+ compatible = "mv64x60-sdma";
+ reg = <6000 c18>;
+ virtual-reg = <f1006000>;
+ interrupt-base = <0>;
+ interrupts = <26>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ brg@b200 {
+ device_type = "brg";
+ compatible = "mv64x60-brg";
+ reg = <b200 8>;
+ clock-src = <8>;
+ clock-frequency = <7ed6b40>;
+ current-speed = <2580>;
+ bcr = <0>;
+ };
+
+ brg@b208 {
+ device_type = "brg";
+ compatible = "mv64x60-brg";
+ reg = <b208 8>;
+ clock-src = <8>;
+ clock-frequency = <7ed6b40>;
+ current-speed = <2580>;
+ bcr = <0>;
+ };
+
+ cunit@f200 {
+ device_type = "mv64x60-cunit";
+ reg = <f200 200>;
+ };
+
+ mpscrouting@b400 {
+ device_type = "mpscrouting";
+ reg = <b400 c>;
+ };
+
+ mpscintr@b800 {
+ device_type = "mpscintr";
+ reg = <b800 100>;
+ virtual-reg = <f100b800>;
+ };
+
+ mpsc@8000 {
+ device_type = "serial";
+ compatible = "mpsc";
+ reg = <8000 38>;
+ virtual-reg = <f1008000>;
+ sdma = <&/mv64x60/sdma@4000>;
+ brg = <&/mv64x60/brg@b200>;
+ cunit = <&/mv64x60/cunit@f200>;
+ mpscrouting = <&/mv64x60/mpscrouting@b400>;
+ mpscintr = <&/mv64x60/mpscintr@b800>;
+ block-index = <0>;
+ max_idle = <28>;
+ chr_1 = <0>;
+ chr_2 = <0>;
+ chr_10 = <3>;
+ mpcr = <0>;
+ interrupts = <28>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ mpsc@9000 {
+ device_type = "serial";
+ compatible = "mpsc";
+ reg = <9000 38>;
+ virtual-reg = <f1009000>;
+ sdma = <&/mv64x60/sdma@6000>;
+ brg = <&/mv64x60/brg@b208>;
+ cunit = <&/mv64x60/cunit@f200>;
+ mpscrouting = <&/mv64x60/mpscrouting@b400>;
+ mpscintr = <&/mv64x60/mpscintr@b800>;
+ block-index = <1>;
+ max_idle = <28>;
+ chr_1 = <0>;
+ chr_2 = <0>;
+ chr_10 = <3>;
+ mpcr = <0>;
+ interrupts = <2a>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ i2c@c000 {
+ device_type = "i2c";
+ compatible = "mv64x60-i2c";
+ reg = <c000 20>;
+ virtual-reg = <f100c000>;
+ freq_m = <8>;
+ freq_n = <3>;
+ timeout = <3e8>; /* 1000 = 1 second */
+ retries = <1>;
+ interrupts = <25>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ pic {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ device_type = "mv64x60-pic";
+ compatible = "mv64x60-pic";
+ reg = <0000 88>;
+ interrupt-controller;
+ };
+
+ mpp@f000 {
+ device_type = "mv64x60-mpp";
+ compatible = "mv64x60-mpp";
+ reg = <f000 10>;
+ };
+
+ gpp@f100 {
+ device_type = "mv64x60-gpp";
+ compatible = "mv64x60-gpp";
+ reg = <f100 20>;
+ };
+
+ pci@80000000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ compatible = "mv64x60-pci";
+ reg = <0cf8 8>;
+ ranges = <01000000 0 0 88000000 0 01000000
+ 02000000 0 80000000 80000000 0 08000000>;
+ bus-range = <0 ff>;
+ clock-frequency = <3EF1480>;
+ interrupt-pci-iack = <0c34>;
+ interrupt-parent = <&/mv64x60/pic>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0a */
+ 5000 0 0 1 &/mv64x60/pic 50
+ 5000 0 0 2 &/mv64x60/pic 51
+ 5000 0 0 3 &/mv64x60/pic 5b
+ 5000 0 0 4 &/mv64x60/pic 5d
+
+ /* IDSEL 0x0b */
+ 5800 0 0 1 &/mv64x60/pic 5b
+ 5800 0 0 2 &/mv64x60/pic 5d
+ 5800 0 0 3 &/mv64x60/pic 50
+ 5800 0 0 4 &/mv64x60/pic 51
+
+ /* IDSEL 0x0c */
+ 6000 0 0 1 &/mv64x60/pic 5b
+ 6000 0 0 2 &/mv64x60/pic 5d
+ 6000 0 0 3 &/mv64x60/pic 50
+ 6000 0 0 4 &/mv64x60/pic 51
+
+ /* IDSEL 0x0d */
+ 6800 0 0 1 &/mv64x60/pic 5d
+ 6800 0 0 2 &/mv64x60/pic 50
+ 6800 0 0 3 &/mv64x60/pic 51
+ 6800 0 0 4 &/mv64x60/pic 5b
+ >;
+ };
+
+ cpu-error@0070 {
+ device_type = "mv64x60-cpu-error";
+ reg = <0070 10 0128 28>;
+ interrupts = <03>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ sram-error@0380 {
+ device_type = "mv64x60-sram-error";
+ reg = <0380 80>;
+ interrupts = <0d>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ pci-error@1dc0 {
+ device_type = "mv64x60-pci-error";
+ reg = <1d40 40 0c28 4>;
+ interrupts = <0c>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ memctrl@1400 {
+ device_type = "mv64x60-memctrl";
+ reg = <1400 60>;
+ interrupts = <11>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+ };
+
+ chosen {
+ linux,platform = <1>;
+ bootargs = "ip=on console=ttyMM0";
+ linux,stdout-path = "/mv64x60/mpsc@8000";
+ };
+};
^ permalink raw reply
* [PATCH 10/13] powerpc: Add arch/powerpc mv64x60 PCI setup
From: Mark A. Greer @ 2007-04-26 0:01 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
---
mv64x60.c | 176 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
mv64x60.h | 2
2 files changed, 178 insertions(+)
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/mv64x60.c
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c
@@ -18,12 +18,14 @@
#include <linux/string.h>
#include <linux/mv643xx.h>
#include <linux/platform_device.h>
+#include <linux/pci.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/irq.h>
#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
#include "mv64x60.h"
@@ -721,3 +723,177 @@ ret_node_put:
}
arch_initcall(mv64x60_i2c_platform_device_init);
+
+#ifdef CONFIG_PCI
+static int mv64x60_pci_exclude_bridge = 1;
+static struct pci_controller *mv64x60_primary_hose;
+static int mv64x60_pci2_busno;
+
+#ifdef CONFIG_SYSFS
+/* 32-bit hex or dec stringified number + '\n' */
+#define MV64X60_VAL_LEN_MAX 11
+#define MV64X60_PCICFG_CPCI_HOTSWAP 0x68
+
+DECLARE_MUTEX(mv64x60_hs_lock);
+
+static ssize_t mv64x60_hs_reg_read(struct kobject *kobj, char *buf, loff_t off,
+ size_t count)
+{
+ u32 v;
+ int save_exclude;
+
+ if (off > 0)
+ return 0;
+ if (count < MV64X60_VAL_LEN_MAX)
+ return -EINVAL;
+
+ if (down_interruptible(&mv64x60_hs_lock))
+ return -ERESTARTSYS;
+ save_exclude = mv64x60_pci_exclude_bridge;
+ mv64x60_pci_exclude_bridge = 0;
+ early_read_config_dword(mv64x60_primary_hose, 0, PCI_DEVFN(0, 0),
+ MV64X60_PCICFG_CPCI_HOTSWAP, &v);
+ mv64x60_pci_exclude_bridge = save_exclude;
+ up(&mv64x60_hs_lock);
+
+ return sprintf(buf, "0x%08x\n", v);
+}
+
+static ssize_t mv64x60_hs_reg_write(struct kobject *kobj, char *buf,
+ loff_t off, size_t count)
+{
+ u32 v;
+ int save_exclude;
+
+ if (off > 0)
+ return 0;
+ if (count <= 0)
+ return -EINVAL;
+
+ if (sscanf(buf, "%i", &v) == 1) {
+ if (down_interruptible(&mv64x60_hs_lock))
+ return -ERESTARTSYS;
+ save_exclude = mv64x60_pci_exclude_bridge;
+ mv64x60_pci_exclude_bridge = 0;
+ early_write_config_dword(mv64x60_primary_hose, 0,
+ PCI_DEVFN(0, 0),
+ MV64X60_PCICFG_CPCI_HOTSWAP, v);
+ mv64x60_pci_exclude_bridge = save_exclude;
+ up(&mv64x60_hs_lock);
+ }
+ else
+ count = -EINVAL;
+
+ return count;
+}
+
+static struct bin_attribute mv64x60_hs_reg_attr = { /* Hotswap register */
+ .attr = {
+ .name = "hs_reg",
+ .mode = S_IRUGO | S_IWUSR,
+ .owner = THIS_MODULE,
+ },
+ .size = MV64X60_VAL_LEN_MAX,
+ .read = mv64x60_hs_reg_read,
+ .write = mv64x60_hs_reg_write,
+};
+
+static int __init mv64x60_sysfs_init(void)
+{
+ struct device_node *np;
+ struct platform_device *pdev;
+ const unsigned int *prop;
+
+ np = of_find_compatible_node(NULL, NULL, "mv64x60");
+ if (!np)
+ return 0;
+
+ pdev = platform_device_register_simple("mv64x60", 0, NULL, 0);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ prop = of_get_property(np, "hs_reg_valid", NULL);
+ of_node_put(np);
+ if (!prop)
+ return 0;
+
+ return sysfs_create_bin_file(&pdev->dev.kobj, &mv64x60_hs_reg_attr);
+}
+
+subsys_initcall(mv64x60_sysfs_init);
+
+#endif /* CONFIG_SYSFS */
+
+static int mv64x60_exclude_device(u_char bus, u_char devfn)
+{
+ if ((bus == 0 || bus == mv64x60_pci2_busno) &&
+ PCI_SLOT(devfn) == 0 && mv64x60_pci_exclude_bridge)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int __init mv64x60_add_bridge(struct device_node *dev)
+{
+ int len;
+ struct pci_controller *hose;
+ struct resource rsrc;
+ const int *bus_range;
+ int primary;
+
+ memset(&rsrc, 0, sizeof(rsrc));
+
+ /* Fetch host bridge registers address */
+ if (of_address_to_resource(dev, 0, &rsrc)) {
+ printk(KERN_ERR "No PCI reg property in device tree\n");
+ return -ENODEV;
+ }
+
+ /* Get bus range if any */
+ bus_range = of_get_property(dev, "bus-range", &len);
+ if (bus_range == NULL || len < 2 * sizeof(int))
+ printk(KERN_WARNING "Can't get bus-range for %s, assume"
+ " bus 0\n", dev->full_name);
+
+ hose = pcibios_alloc_controller();
+ if (!hose)
+ return -ENOMEM;
+
+ hose->arch_data = dev;
+ hose->set_cfg_type = 1;
+
+ hose->first_busno = bus_range ? bus_range[0] : 0;
+ hose->last_busno = bus_range ? bus_range[1] : 0xff;
+ primary = hose->first_busno == 0;
+
+ setup_indirect_pci(hose, rsrc.start, rsrc.start + 4);
+
+ if (primary)
+ mv64x60_primary_hose = hose;
+ else {
+ hose->bus_offset = hose->first_busno;
+ mv64x60_pci2_busno = hose->first_busno;
+ }
+
+ printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "
+ "Firmware bus number: %d->%d\n",
+ (unsigned long long)rsrc.start, hose->first_busno,
+ hose->last_busno);
+
+ /* Interpret the "ranges" property */
+ /* This also maps the I/O region and sets isa_io/mem_base */
+ pci_process_bridge_OF_ranges(hose, dev, primary);
+
+ return 0;
+}
+
+void __init mv64x60_pci_init(void)
+{
+ struct device_node *np = NULL;
+
+ ppc_md.pci_exclude_device = mv64x60_exclude_device;
+
+ while ((np = of_find_compatible_node(np, "pci", "mv64x60-pci")))
+ mv64x60_add_bridge(np);
+}
+#endif /* CONFIG_PCI */
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.h
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/mv64x60.h
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.h
@@ -6,4 +6,6 @@
extern void __init mv64x60_init_irq(void);
extern unsigned int mv64x60_get_irq(void);
+extern void __init mv64x60_pci_init(void);
+
#endif /* __MV64X60_H__ */
^ permalink raw reply
* [PATCH 9/13] powerpc: Add arch/powerpc mv64x60 I2C platform data setup
From: Mark A. Greer @ 2007-04-26 0:00 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
---
mv64x60.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/mv64x60.c
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c
@@ -646,3 +646,78 @@ ret_node_put:
}
arch_initcall(mv64x60_eth_platform_device_init);
+
+/*
+ * Create mv64x60_i2c platform device
+ */
+static int __init mv64x60_i2c_platform_device_init(void)
+{
+ struct device_node *np = NULL;
+ int i;
+ struct platform_device *pdev;
+ int err;
+
+ for (i = 0;
+ (np = of_find_compatible_node(np, "i2c", "mv64x60-i2c"));
+ i++) {
+ struct resource r[2];
+ struct mv64xxx_i2c_pdata pdata;
+ const unsigned int *prop;
+
+ err = of_address_to_resource(np, 0, &r[0]);
+ if (err)
+ goto ret_node_put;
+
+ memset(&r[1], 0, sizeof(r[1]));
+ of_irq_to_resource(np, 0, &r[1]);
+
+ pdev = platform_device_register_simple(MV64XXX_I2C_CTLR_NAME,
+ 0, r, 2);
+ if (IS_ERR(pdev)) {
+ err = PTR_ERR(pdev);
+ goto ret_node_put;
+ }
+
+ memset(&pdata, 0, sizeof(pdata));
+
+ prop = of_get_property(np, "freq_m", NULL);
+ if (!prop) {
+ err = -ENODEV;
+ goto ret_unreg;
+ }
+ pdata.freq_m = *prop;
+
+ prop = of_get_property(np, "freq_n", NULL);
+ if (!prop) {
+ err = -ENODEV;
+ goto ret_unreg;
+ }
+ pdata.freq_n = *prop;
+
+ prop = of_get_property(np, "timeout", NULL);
+ if (prop)
+ pdata.timeout = *prop;
+ else
+ pdata.timeout = 1000; /* 1 second */
+
+ prop = of_get_property(np, "retries", NULL);
+ if (prop)
+ pdata.retries = *prop;
+ else
+ pdata.retries = 1;
+
+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+ if (err)
+ goto ret_unreg;
+ }
+
+ return 0;
+
+ret_unreg:
+ platform_device_unregister(pdev);
+ret_node_put:
+ of_node_put(np);
+ return err;
+}
+
+arch_initcall(mv64x60_i2c_platform_device_init);
^ permalink raw reply
* [PATCH 8/13] powerpc: Add arch/powerpc mv64x60_eth platform data setup
From: Mark A. Greer @ 2007-04-26 0:00 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
---
arch/powerpc/sysdev/mv64x60.c | 135 ++++++++++++++++++++++++++++++++++++++++++
drivers/net/Kconfig | 2
2 files changed, 136 insertions(+), 1 deletion(-)
Index: linux-2.6-powerpc-df/drivers/net/Kconfig
===================================================================
--- linux-2.6-powerpc-df.orig/drivers/net/Kconfig
+++ linux-2.6-powerpc-df/drivers/net/Kconfig
@@ -2301,7 +2301,7 @@ config UGETH_HAS_GIGA
config MV643XX_ETH
tristate "MV-643XX Ethernet support"
- depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32)
+ depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MV64X60 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32)
select MII
help
This driver supports the gigabit Ethernet on the Marvell MV643XX
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/mv64x60.c
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c
@@ -511,3 +511,138 @@ ret_node_put:
}
arch_initcall(mv64x60_mpsc_platform_device_init);
+
+/*
+ * Create mv64x60_eth platform device
+ */
+static int __init eth_register_shared_pdev(struct device_node *np)
+{
+ struct platform_device *pdev;
+ struct resource res;
+ int err;
+
+ np = of_get_parent(np);
+ if (!np)
+ return -ENODEV;
+
+ err = of_address_to_resource(np, 0, &res);
+ of_node_put(np);
+ if (err)
+ return err;
+
+ pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, 0,
+ &res, 1);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ return 0;
+}
+
+static int __init mv64x60_eth_platform_device_init(void)
+{
+ struct device_node *np = NULL;
+ unsigned int i;
+ struct platform_device *pdev;
+ int err;
+
+ for (i = 0;
+ (np = of_find_compatible_node(np, "network", "mv64x60-eth"));
+ i++) {
+ struct device_node *phy;
+ struct mv643xx_eth_platform_data pdata;
+ const u8 *mac_addr;
+ const void *prop;
+ const phandle *ph;
+ struct resource res;
+
+ if (i == 0) {
+ err = eth_register_shared_pdev(np);
+ if (err)
+ goto ret_node_put;
+ }
+
+ memset(&res, 0, sizeof(res));
+ of_irq_to_resource(np, 0, &res);
+
+ pdev = platform_device_register_simple(MV643XX_ETH_NAME,
+ i, &res, 1);
+ if (IS_ERR(pdev)) {
+ err = PTR_ERR(pdev);
+ goto ret_node_put;
+ }
+
+ memset(&pdata, 0, sizeof(pdata));
+
+ prop = of_get_property(np, "block-index", NULL);
+ if (prop)
+ pdata.port_number = *(int *)prop;
+ else
+ pdata.port_number = i;
+
+ mac_addr = of_get_mac_address(np);
+ if (mac_addr)
+ memcpy(pdata.mac_addr, mac_addr, 6);
+
+ prop = of_get_property(np, "speed", NULL);
+ if (prop)
+ pdata.speed = *(int *)prop;
+
+ prop = of_get_property(np, "tx_queue_size", NULL);
+ if (prop)
+ pdata.tx_queue_size = *(int *)prop;
+
+ prop = of_get_property(np, "rx_queue_size", NULL);
+ if (prop)
+ pdata.rx_queue_size = *(int *)prop;
+
+ prop = of_get_property(np, "tx_sram_addr", NULL);
+ if (prop)
+ pdata.tx_sram_addr = *(int *)prop;
+
+ prop = of_get_property(np, "tx_sram_size", NULL);
+ if (prop)
+ pdata.tx_sram_size = *(int *)prop;
+
+ prop = of_get_property(np, "rx_sram_addr", NULL);
+ if (prop)
+ pdata.rx_sram_addr = *(int *)prop;
+
+ prop = of_get_property(np, "rx_sram_size", NULL);
+ if (prop)
+ pdata.rx_sram_size = *(int *)prop;
+
+ ph = of_get_property(np, "phy", NULL);
+ if (!ph) {
+ err = -ENODEV;
+ goto ret_unreg;
+ }
+
+ phy = of_find_node_by_phandle(*ph);
+ if (phy == NULL) {
+ err = -ENODEV;
+ goto ret_unreg;
+ }
+
+ prop = of_get_property(phy, "reg", NULL);
+ if (prop) {
+ pdata.force_phy_addr = 1;
+ pdata.phy_addr = *(int *)prop;
+ }
+
+ of_node_put(phy);
+
+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+ if (err)
+ goto ret_unreg;
+ }
+
+ return 0;
+
+ret_unreg:
+ platform_device_unregister(pdev);
+ret_node_put:
+ of_node_put(np);
+ return err;
+}
+
+arch_initcall(mv64x60_eth_platform_device_init);
^ permalink raw reply
* [PATCH 7/13] powerpc: Add arch/powerpc mv64x60 MPSC platform data setup
From: Mark A. Greer @ 2007-04-25 23:59 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
---
mv64x60.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 170 insertions(+)
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/mv64x60.c
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c
@@ -15,6 +15,9 @@
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/mv643xx.h>
+#include <linux/platform_device.h>
#include <asm/byteorder.h>
#include <asm/io.h>
@@ -341,3 +344,170 @@ int __init mv64x60_verify_cache_coherenc
}
late_initcall(mv64x60_verify_cache_coherency);
+
+/*
+ * Create MPSC platform device
+ */
+static int __init mv64x60_mpsc_register_shared_pdev(struct device_node *np)
+{
+ struct platform_device *pdev;
+ struct resource r[2];
+ struct mpsc_shared_pdata pdata;
+ const phandle *ph;
+ struct device_node *mpscrouting, *mpscintr;
+ int err;
+
+ ph = of_get_property(np, "mpscrouting", NULL);
+ mpscrouting = of_find_node_by_phandle(*ph);
+ if (!mpscrouting)
+ return -ENODEV;
+
+ err = of_address_to_resource(mpscrouting, 0, &r[0]);
+ of_node_put(mpscrouting);
+ if (err)
+ return err;
+
+ ph = of_get_property(np, "mpscintr", NULL);
+ mpscintr = of_find_node_by_phandle(*ph);
+ if (!mpscintr)
+ return -ENODEV;
+
+ err = of_address_to_resource(mpscintr, 0, &r[1]);
+ of_node_put(mpscintr);
+ if (err)
+ return err;
+
+ pdev = platform_device_register_simple(MPSC_SHARED_NAME, 0, r, 2);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ memset(&pdata, 0, sizeof(pdata));
+
+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+ if (err)
+ platform_device_unregister(pdev);
+
+ return 0;
+}
+
+static int __init mv64x60_mpsc_platform_device_init(void)
+{
+ struct device_node *np = NULL;
+ unsigned int i;
+ struct platform_device *pdev;
+ int err;
+
+ for (i = 0; (np = of_find_compatible_node(np, "serial", "mpsc")); i++) {
+ struct resource r[5];
+ struct mpsc_pdata pdata;
+ const unsigned int *prop;
+ const phandle *ph;
+ struct device_node *sdma, *brg;
+
+ memset(&r, 0, sizeof(r));
+
+ if (i == 0) {
+ err = mv64x60_mpsc_register_shared_pdev(np);
+ if (err)
+ goto ret_node_put;
+ }
+
+ err = of_address_to_resource(np, 0, &r[0]);
+ if (err)
+ goto ret_node_put;
+
+ of_irq_to_resource(np, 0, &r[4]);
+
+ ph = of_get_property(np, "sdma", NULL);
+ sdma = of_find_node_by_phandle(*ph);
+ if (!sdma) {
+ err = -ENODEV;
+ goto ret_node_put;
+ }
+ of_irq_to_resource(sdma, 0, &r[3]);
+ err = of_address_to_resource(sdma, 0, &r[1]);
+ of_node_put(sdma);
+ if (err)
+ goto ret_node_put;
+
+ ph = of_get_property(np, "brg", NULL);
+ brg = of_find_node_by_phandle(*ph);
+ if (!brg) {
+ err = -ENODEV;
+ goto ret_node_put;
+ }
+
+ err = of_address_to_resource(brg, 0, &r[2]);
+ of_node_put(brg);
+ if (err)
+ goto ret_node_put;
+
+ pdev = platform_device_register_simple(MPSC_CTLR_NAME, i, r, 5);
+ if (IS_ERR(pdev)) {
+ err = PTR_ERR(pdev);
+ goto ret_node_put;
+ }
+
+ memset(&pdata, 0, sizeof(pdata));
+
+ pdata.cache_mgmt = 1; /* All current revs need this set */
+
+ prop = of_get_property(np, "max_idle", NULL);
+ if (prop)
+ pdata.max_idle = *prop;
+
+ prop = of_get_property(brg, "current-speed", NULL);
+ if (prop)
+ pdata.default_baud = *prop;
+
+ /* Default is 8 bits, no parity, no flow control */
+ pdata.default_bits = 8;
+ pdata.default_parity = 'n';
+ pdata.default_flow = 'n';
+
+ prop = of_get_property(np, "chr_1", NULL);
+ if (prop)
+ pdata.chr_1_val = *prop;
+
+ prop = of_get_property(np, "chr_2", NULL);
+ if (prop)
+ pdata.chr_2_val = *prop;
+
+ prop = of_get_property(np, "chr_10", NULL);
+ if (prop)
+ pdata.chr_10_val = *prop;
+
+ prop = of_get_property(np, "mpcr", NULL);
+ if (prop)
+ pdata.mpcr_val = *prop;
+
+ prop = of_get_property(brg, "bcr", NULL);
+ if (prop)
+ pdata.bcr_val = *prop;
+
+ pdata.brg_can_tune = 1; /* All current revs need this set */
+
+ prop = of_get_property(brg, "clock-src", NULL);
+ if (prop)
+ pdata.brg_clk_src = *prop;
+
+ prop = of_get_property(brg, "clock-frequency", NULL);
+ if (prop)
+ pdata.brg_clk_freq = *prop;
+
+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+ if (err)
+ goto ret_unreg;
+ of_node_put(np);
+ }
+
+ return 0;
+
+ret_unreg:
+ platform_device_unregister(pdev);
+ret_node_put:
+ of_node_put(np);
+ return err;
+}
+
+arch_initcall(mv64x60_mpsc_platform_device_init);
^ permalink raw reply
* [PATCH 6/13] powerpc: Add arch/powerpc support for Marvell/mv64x60 hostbridge
From: Mark A. Greer @ 2007-04-25 23:58 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
---
platforms/embedded6xx/Kconfig | 4
sysdev/Makefile | 1
sysdev/mv64x60.c | 343 ++++++++++++++++++++++++++++++++++++++++++
sysdev/mv64x60.h | 9 +
4 files changed, 357 insertions(+)
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.c 2007-04-17 12:48:22.000000000 -0700
@@ -0,0 +1,343 @@
+/*
+ * Common routines for the Marvell mv64360/mv64460 host bridges (Discovery)
+ *
+ * Author: Dale Farnsworth <dale@farnsworth.org>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/irq.h>
+#include <asm/machdep.h>
+
+#include "mv64x60.h"
+
+/* Interrupt Controller Interface Registers */
+#define MV64X60_IC_MAIN_CAUSE_LO 0x0004
+#define MV64X60_IC_MAIN_CAUSE_HI 0x000c
+#define MV64X60_IC_CPU0_INTR_MASK_LO 0x0014
+#define MV64X60_IC_CPU0_INTR_MASK_HI 0x001c
+#define MV64X60_IC_CPU0_SELECT_CAUSE 0x0024
+
+#define MV64X60_HIGH_GPP_GROUPS 0x0f000000
+#define MV64X60_SELECT_CAUSE_HIGH 0x40000000
+
+/* General Purpose Pins Controller Interface Registers */
+#define MV64x60_GPP_INTR_CAUSE 0x0008
+#define MV64x60_GPP_INTR_MASK 0x000c
+
+#define MV64x60_LEVEL1_LOW 0
+#define MV64x60_LEVEL1_HIGH 1
+#define MV64x60_LEVEL1_GPP 2
+
+#define MV64x60_LEVEL1_MASK 0x00000060
+#define MV64x60_LEVEL1_OFFSET 5
+
+#define MV64x60_LEVEL2_MASK 0x0000001f
+
+#define MV64x60_NUM_IRQS 96
+
+DEFINE_SPINLOCK(mv64x60_lock);
+
+static void __iomem *mv64x60_irq_reg_base;
+static void __iomem *mv64x60_gpp_reg_base;
+
+/*
+ * Interrupt Controller Handling
+ *
+ * The interrupt controller handles three groups of interrupts:
+ * main low: IRQ0-IRQ31
+ * main high: IRQ32-IRQ63
+ * gpp: IRQ64-IRQ95
+ *
+ * This code handles interrupts in two levels. Level 1 selects the
+ * interrupt group, and level 2 selects an IRQ within that group.
+ * Each group has its own irq_chip structure.
+ */
+
+static u32 mv64x60_cached_low_mask = 0;
+static u32 mv64x60_cached_high_mask = MV64X60_HIGH_GPP_GROUPS;
+static u32 mv64x60_cached_gpp_mask = 0;
+
+static struct irq_host *mv64x60_irq_host;
+
+/*
+ * mv64x60_chip_low functions
+ */
+
+static void mv64x60_mask_low(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_low_mask &= ~(1 << level2);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
+ mv64x60_cached_low_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
+}
+
+static void mv64x60_unmask_low(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_low_mask |= 1 << level2;
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
+ mv64x60_cached_low_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
+}
+
+static struct irq_chip mv64x60_chip_low = {
+ .name = "mv64x60_low",
+ .mask = mv64x60_mask_low,
+ .mask_ack = mv64x60_mask_low,
+ .unmask = mv64x60_unmask_low,
+};
+
+/*
+ * mv64x60_chip_high functions
+ */
+
+static void mv64x60_mask_high(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_high_mask &= ~(1 << level2);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
+ mv64x60_cached_high_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
+}
+
+static void mv64x60_unmask_high(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_high_mask |= 1 << level2;
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
+ mv64x60_cached_high_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
+}
+
+static struct irq_chip mv64x60_chip_high = {
+ .name = "mv64x60_high",
+ .mask = mv64x60_mask_high,
+ .mask_ack = mv64x60_mask_high,
+ .unmask = mv64x60_unmask_high,
+};
+
+/*
+ * mv64x60_chip_gpp functions
+ */
+
+static void mv64x60_mask_gpp(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_gpp_mask &= ~(1 << level2);
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
+ mv64x60_cached_gpp_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
+}
+
+static void mv64x60_mask_ack_gpp(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_gpp_mask &= ~(1 << level2);
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
+ mv64x60_cached_gpp_mask);
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE,
+ ~(1 << level2));
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE);
+}
+
+static void mv64x60_unmask_gpp(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_gpp_mask |= 1 << level2;
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
+ mv64x60_cached_gpp_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
+}
+
+static struct irq_chip mv64x60_chip_gpp = {
+ .name = "mv64x60_gpp",
+ .mask = mv64x60_mask_gpp,
+ .mask_ack = mv64x60_mask_ack_gpp,
+ .unmask = mv64x60_unmask_gpp,
+};
+
+/*
+ * mv64x60_host_ops functions
+ */
+
+static int mv64x60_host_match(struct irq_host *h, struct device_node *np)
+{
+ return mv64x60_irq_host->host_data == np;
+}
+
+static struct irq_chip *mv64x60_chips[] = {
+ [MV64x60_LEVEL1_LOW] = &mv64x60_chip_low,
+ [MV64x60_LEVEL1_HIGH] = &mv64x60_chip_high,
+ [MV64x60_LEVEL1_GPP] = &mv64x60_chip_gpp,
+};
+
+static int mv64x60_host_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t hwirq)
+{
+ int level1;
+
+ get_irq_desc(virq)->status |= IRQ_LEVEL;
+
+ level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
+ BUG_ON(level1 > MV64x60_LEVEL1_GPP);
+ set_irq_chip_and_handler(virq, mv64x60_chips[level1], handle_level_irq);
+
+ return 0;
+}
+
+static struct irq_host_ops mv64x60_host_ops = {
+ .match = mv64x60_host_match,
+ .map = mv64x60_host_map,
+};
+
+/*
+ * Global functions
+ */
+
+void __init mv64x60_init_irq(void)
+{
+ struct device_node *np;
+ phys_addr_t paddr;
+ unsigned int size;
+ const unsigned int *reg;
+ unsigned long flags;
+
+ np = of_find_compatible_node(NULL, "mv64x60-gpp", "mv64x60-gpp");
+ reg = of_get_property(np, "reg", &size);
+ paddr = of_translate_address(np, reg);
+ mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
+ of_node_put(np);
+
+ np = of_find_compatible_node(NULL, "mv64x60-pic", "mv64x60-pic");
+ reg = of_get_property(np, "reg", &size);
+ paddr = of_translate_address(np, reg);
+ of_node_put(np);
+ mv64x60_irq_reg_base = ioremap(paddr, reg[1]);
+
+ mv64x60_irq_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, MV64x60_NUM_IRQS,
+ &mv64x60_host_ops, MV64x60_NUM_IRQS);
+
+ mv64x60_irq_host->host_data = np;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
+ mv64x60_cached_gpp_mask);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
+ mv64x60_cached_low_mask);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
+ mv64x60_cached_high_mask);
+
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE, 0);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_LO, 0);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_HI, 0);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+}
+
+unsigned int mv64x60_get_irq(void)
+{
+ u32 cause;
+ int level1;
+ irq_hw_number_t hwirq;
+ int virq = NO_IRQ;
+
+ cause = in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_SELECT_CAUSE);
+ if (cause & MV64X60_SELECT_CAUSE_HIGH) {
+ cause &= mv64x60_cached_high_mask;
+ level1 = MV64x60_LEVEL1_HIGH;
+ if (cause & MV64X60_HIGH_GPP_GROUPS) {
+ cause = in_le32(mv64x60_gpp_reg_base +
+ MV64x60_GPP_INTR_CAUSE);
+ cause &= mv64x60_cached_gpp_mask;
+ level1 = MV64x60_LEVEL1_GPP;
+ }
+ } else {
+ cause &= mv64x60_cached_low_mask;
+ level1 = MV64x60_LEVEL1_LOW;
+ }
+ if (cause) {
+ hwirq = (level1 << MV64x60_LEVEL1_OFFSET) | __ilog2(cause);
+ virq = irq_linear_revmap(mv64x60_irq_host, hwirq);
+ }
+
+ return virq;
+}
+
+/*
+ * The bootwrapper sets the coherency of the DMA windows according to
+ * the setting in the device tree. For the kernel, coherency is a
+ * compile-time configuration option. Fail if there is a mismatch.
+ */
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define KERNEL_COHERENCY 0
+#else
+#define KERNEL_COHERENCY 1
+#endif
+
+int __init mv64x60_verify_cache_coherency(void)
+{
+ struct device_node *np;
+ const void *prop;
+ int devtree_coherency;
+
+ np = of_find_node_by_path("/");
+ prop = of_get_property(np, "coherency-off", NULL);
+ of_node_put(np);
+
+ devtree_coherency = prop ? 0 : 1;
+
+ if (devtree_coherency != KERNEL_COHERENCY) {
+ printk(KERN_ERR
+ "kernel coherency:%s != device tree_coherency:%s\n",
+ KERNEL_COHERENCY ? "on" : "off",
+ devtree_coherency ? "on" : "off");
+ BUG();
+ }
+
+ return 0;
+}
+
+late_initcall(mv64x60_verify_cache_coherency);
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.h 2007-04-17 12:47:28.000000000 -0700
@@ -0,0 +1,9 @@
+#ifndef __MV64X60_H__
+#define __MV64X60_H__
+
+#include <linux/init.h>
+
+extern void __init mv64x60_init_irq(void);
+extern unsigned int mv64x60_get_irq(void);
+
+#endif /* __MV64X60_H__ */
Index: linux-2.6-powerpc-df/arch/powerpc/platforms/embedded6xx/Kconfig
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/platforms/embedded6xx/Kconfig 2007-04-17 11:35:26.000000000 -0700
+++ linux-2.6-powerpc-df/arch/powerpc/platforms/embedded6xx/Kconfig 2007-04-17 12:47:27.000000000 -0700
@@ -38,6 +38,10 @@
select PPC_INDIRECT_PCI
default y
+config MV64X60
+ bool
+ select PPC_INDIRECT_PCI
+
config MPC10X_OPENPIC
bool
depends on LINKSTATION
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/Makefile
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/Makefile 2007-04-17 11:35:26.000000000 -0700
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/Makefile 2007-04-17 12:46:39.000000000 -0700
@@ -14,6 +14,7 @@
obj-$(CONFIG_FSL_PCIE) += fsl_pcie.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_MV64X60) += mv64x60.o
# contains only the suspend handler for time
obj-$(CONFIG_PM) += timer.o
^ permalink raw reply
* Re: [PATCH] [2.6.22] pasemi: cpufreq driver
From: Olof Johansson @ 2007-04-25 23:57 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linuxppc-dev, egor, paulus, cpufreq
In-Reply-To: <200704260147.35878.arnd@arndb.de>
On Thu, Apr 26, 2007 at 01:47:35AM +0200, Arnd Bergmann wrote:
> On Wednesday 25 April 2007, Olof Johansson wrote:
>
> > +/* This should eventually come out of the device tree */
> > +#define SDCPWR_BASE 0xfc104000
> > +#define SDCPWR_SIZE 0x1000
> > +
> > +#define SDCASR_BASE 0xfc120000
> > +#define SDCASR_SIZE 0x2000
>
> the comment is right. Why don't you do it then? ;-)
Leftovers from when it was a regular platform driver.
> > +static int pas_cpufreq_cpu_init (struct cpufreq_policy *policy)
> > +{
> > + u32 *max_freq;
> > + int i, cur_astate;
> > + struct device_node *cpu;
> > +
> > + cpu = of_get_cpu_node(policy->cpu, NULL);
> > +
> > + if(!cpu)
> > + return -ENODEV;
> > +
> > + sdcpwr_mapbase = ioremap(SDCPWR_BASE, SDCPWR_SIZE);
> > + sdcasr_mapbase = ioremap(SDCASR_BASE, SDCASR_SIZE);
> > + if (!sdcpwr_mapbase || !sdcasr_mapbase)
> > + panic("SDCMAP: Cannot map registers!");
>
> I can't see any check in here that finds out if you are actually running on
> the right hardware.
> The proper way to implement this driver would be to register an
> of_platform_driver for the cpufreq device and then get the register
> addresses from there,
Yup.
> > @@ -155,7 +155,7 @@ source "drivers/cpufreq/Kconfig"
> >
> > config CPU_FREQ_PMAC
> > bool "Support for Apple PowerBooks"
> > - depends on CPU_FREQ && ADB_PMU && PPC32
> > + depends on ADB_PMU && PPC32
> > select CPU_FREQ_TABLE
> > help
> > This adds support for frequency switching on Apple PowerBooks,
> > @@ -164,11 +164,21 @@ config CPU_FREQ_PMAC
> >
> > config CPU_FREQ_PMAC64
> > bool "Support for some Apple G5s"
> > - depends on CPU_FREQ && PPC64
> > + depends on PPC64
> > select CPU_FREQ_TABLE
> > help
> > This adds support for frequency switching on Apple iMac G5,
> > and some of the more recent desktop G5 machines as well.
>
> Why this change?
They're redundant, but they should have been in a separate patch. I
forgot to revert them before rediffing.
> > +config PPC_PASEMI_CPUFREQ
> > + bool "Support for PA Semi PWRficient"
> > + depends on PPC_PASEMI
> > + default y
> > + select CPU_FREQ_TABLE
> > + help
> > + This adds the support for frequency switching on PA Semi
> > + PWRficient processors.
> > +
> > endmenu
>
> Why bool and not tristate?
1) The other cpufreq drivers are bool
2) See the idle loop interaction: It can go tristate once we have runtime
selection of idle loop, but until then we need it for idle=doze.
-Olof
^ permalink raw reply
* [PATCH 5/13] powerpc: Add bootwrapper support for Marvell/mv64x60 I2C
From: Mark A. Greer @ 2007-04-25 23:57 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
Makefile | 3
mv64x60_i2c.c | 206 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 208 insertions(+), 1 deletion(-)
Index: powerpc/arch/powerpc/boot/mv64x60_i2c.c
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/mv64x60_i2c.c
@@ -0,0 +1,206 @@
+/*
+ * Bootloader version of the i2c driver for the MV64x60.
+ *
+ * Author: Dale Farnsworth <dfarnsworth@mvista.com>
+ * Maintained by: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2003, 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express or
+ * implied.
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "page.h"
+#include "string.h"
+#include "stdio.h"
+#include "io.h"
+#include "ops.h"
+#include "mv64x60.h"
+
+extern void udelay(long);
+
+/* Register defines */
+#define MV64x60_I2C_REG_SLAVE_ADDR 0x00
+#define MV64x60_I2C_REG_DATA 0x04
+#define MV64x60_I2C_REG_CONTROL 0x08
+#define MV64x60_I2C_REG_STATUS 0x0c
+#define MV64x60_I2C_REG_BAUD 0x0c
+#define MV64x60_I2C_REG_EXT_SLAVE_ADDR 0x10
+#define MV64x60_I2C_REG_SOFT_RESET 0x1c
+
+#define MV64x60_I2C_CONTROL_ACK 0x04
+#define MV64x60_I2C_CONTROL_IFLG 0x08
+#define MV64x60_I2C_CONTROL_STOP 0x10
+#define MV64x60_I2C_CONTROL_START 0x20
+#define MV64x60_I2C_CONTROL_TWSIEN 0x40
+#define MV64x60_I2C_CONTROL_INTEN 0x80
+
+#define MV64x60_I2C_STATUS_BUS_ERR 0x00
+#define MV64x60_I2C_STATUS_MAST_START 0x08
+#define MV64x60_I2C_STATUS_MAST_REPEAT_START 0x10
+#define MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
+#define MV64x60_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
+#define MV64x60_I2C_STATUS_MAST_WR_ACK 0x28
+#define MV64x60_I2C_STATUS_MAST_WR_NO_ACK 0x30
+#define MV64x60_I2C_STATUS_MAST_LOST_ARB 0x38
+#define MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
+#define MV64x60_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
+#define MV64x60_I2C_STATUS_MAST_RD_DATA_ACK 0x50
+#define MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
+#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
+#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
+#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
+#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
+#define MV64x60_I2C_STATUS_NO_STATUS 0xf8
+
+static u8 *ctlr_base;
+
+static int mv64x60_i2c_wait_for_status(int wanted)
+{
+ int i;
+ int status;
+
+ for (i=0; i<1000; i++) {
+ udelay(10);
+ status = in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_STATUS))
+ & 0xff;
+ if (status == wanted)
+ return status;
+ }
+ return -status;
+}
+
+static int mv64x60_i2c_control(int control, int status)
+{
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
+ return mv64x60_i2c_wait_for_status(status);
+}
+
+static int mv64x60_i2c_read_byte(int control, int status)
+{
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
+ if (mv64x60_i2c_wait_for_status(status) < 0)
+ return -1;
+ return in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA)) & 0xff;
+}
+
+static int mv64x60_i2c_write_byte(int data, int control, int status)
+{
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA), data & 0xff);
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
+ return mv64x60_i2c_wait_for_status(status);
+}
+
+int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size,
+ u32 count)
+{
+ int i;
+ int data;
+ int control;
+ int status;
+
+ if (ctlr_base == NULL)
+ return -1;
+
+ /* send reset */
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SOFT_RESET), 0);
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SLAVE_ADDR), 0);
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_EXT_SLAVE_ADDR), 0);
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_BAUD), (4 << 3) | 0x4);
+
+ if (mv64x60_i2c_control(MV64x60_I2C_CONTROL_TWSIEN,
+ MV64x60_I2C_STATUS_NO_STATUS) < 0)
+ return -1;
+
+ /* send start */
+ control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_START;
+ if (mv64x60_i2c_control(control, status) < 0)
+ return -1;
+
+ /* select device for writing */
+ data = devaddr & ~0x1;
+ control = MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK;
+ if (mv64x60_i2c_write_byte(data, control, status) < 0)
+ return -1;
+
+ /* send offset of data */
+ control = MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_WR_ACK;
+ if (offset_size > 1) {
+ if (mv64x60_i2c_write_byte(offset >> 8, control, status) < 0)
+ return -1;
+ }
+ if (mv64x60_i2c_write_byte(offset, control, status) < 0)
+ return -1;
+
+ /* resend start */
+ control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_REPEAT_START;
+ if (mv64x60_i2c_control(control, status) < 0)
+ return -1;
+
+ /* select device for reading */
+ data = devaddr | 0x1;
+ control = MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK;
+ if (mv64x60_i2c_write_byte(data, control, status) < 0)
+ return -1;
+
+ /* read all but last byte of data */
+ control = MV64x60_I2C_CONTROL_ACK | MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_RD_DATA_ACK;
+
+ for (i=1; i<count; i++) {
+ data = mv64x60_i2c_read_byte(control, status);
+ if (data < 0) {
+ printf("errors on iteration %d\n", i);
+ return -1;
+ }
+ *buf++ = data;
+ }
+
+ /* read last byte of data */
+ control = MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK;
+ data = mv64x60_i2c_read_byte(control, status);
+ if (data < 0)
+ return -1;
+ *buf++ = data;
+
+ /* send stop */
+ control = MV64x60_I2C_CONTROL_STOP | MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_NO_STATUS;
+ if (mv64x60_i2c_control(control, status) < 0)
+ return -1;
+
+ return count;
+}
+
+int mv64x60_i2c_open(void)
+{
+ u32 v;
+ void *devp;
+
+ devp = finddevice("/mv64x60/i2c");
+ if (devp == NULL)
+ goto err_out;
+ if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
+ goto err_out;
+
+ ctlr_base = (u8 *)v;
+ return 0;
+
+err_out:
+ return -1;
+}
+
+void mv64x60_i2c_close(void)
+{
+ ctlr_base = NULL;
+}
Index: powerpc/arch/powerpc/boot/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/boot/Makefile
+++ powerpc/arch/powerpc/boot/Makefile
@@ -42,7 +42,8 @@ $(addprefix $(obj)/,$(zlib) main.o): $(a
src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
ns16550.c serial.c simple_alloc.c div64.S util.S \
- gunzip_util.c elf_util.c devtree.c mv64x60.c mpsc.c $(zlib)
+ gunzip_util.c elf_util.c devtree.c mv64x60.c mpsc.c \
+ mv64x60_i2c.c $(zlib)
src-plat := of.c cuboot-83xx.c
src-boot := $(src-wlib) $(src-plat) empty.c
^ permalink raw reply
* [PATCH 4/13] powerpc: Add bootwrapper support for Marvell MPSC
From: Mark A. Greer @ 2007-04-25 23:57 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
Makefile | 2
mpsc.c | 170 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ops.h | 1
serial.c | 2
4 files changed, 174 insertions(+), 1 deletion(-)
Index: powerpc/arch/powerpc/boot/mpsc.c
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/mpsc.c
@@ -0,0 +1,170 @@
+/*
+ * MPSC/UART driver for the Marvell mv64360, mv64460, ...
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "string.h"
+#include "stdio.h"
+#include "io.h"
+#include "ops.h"
+
+extern void udelay(long delay);
+
+#define MPSC_CHR_1 0x000c
+
+#define MPSC_CHR_2 0x0010
+#define MPSC_CHR_2_TA (1<<7)
+#define MPSC_CHR_2_TCS (1<<9)
+#define MPSC_CHR_2_RA (1<<23)
+#define MPSC_CHR_2_CRD (1<<25)
+#define MPSC_CHR_2_EH (1<<31)
+
+#define MPSC_CHR_4 0x0018
+#define MPSC_CHR_4_Z (1<<29)
+
+#define MPSC_CHR_5 0x001c
+#define MPSC_CHR_5_CTL1_INTR (1<<12)
+#define MPSC_CHR_5_CTL1_VALID (1<<15)
+
+#define MPSC_CHR_10 0x0030
+
+#define MPSC_INTR_CAUSE 0x0000
+#define MPSC_INTR_CAUSE_RCC (1<<6)
+#define MPSC_INTR_MASK 0x0080
+
+#define SDMA_SDCM 0x0008
+#define SDMA_SDCM_AR (1<<15)
+#define SDMA_SDCM_AT (1<<31)
+
+static volatile char *mpsc_base;
+static volatile char *mpscintr_base;
+static u32 chr1, chr2;
+
+static int mpsc_open(void)
+{
+ chr1 = in_le32((u32 *)(mpsc_base + MPSC_CHR_1)) & 0x00ff0000;
+ chr2 = in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & ~(MPSC_CHR_2_TA
+ | MPSC_CHR_2_TCS | MPSC_CHR_2_RA | MPSC_CHR_2_CRD
+ | MPSC_CHR_2_EH);
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_4), MPSC_CHR_4_Z);
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_5),
+ MPSC_CHR_5_CTL1_INTR | MPSC_CHR_5_CTL1_VALID);
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_EH);
+ return 0;
+}
+
+static void mpsc_putc(unsigned char c)
+{
+ while (in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & MPSC_CHR_2_TCS);
+
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_1), chr1 | c);
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_TCS);
+}
+
+static unsigned char mpsc_getc(void)
+{
+ u32 cause = 0;
+ unsigned char c;
+
+ while (!(cause & MPSC_INTR_CAUSE_RCC))
+ cause = in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE));
+
+ c = in_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2));
+ out_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2), c);
+ out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE),
+ cause & ~MPSC_INTR_CAUSE_RCC);
+
+ return c;
+}
+
+static u8 mpsc_tstc(void)
+{
+ return (u8)((in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE))
+ & MPSC_INTR_CAUSE_RCC) != 0);
+}
+
+static void mpsc_stop_dma(volatile char *sdma_base)
+{
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_2),MPSC_CHR_2_TA | MPSC_CHR_2_RA);
+ out_le32((u32 *)(sdma_base + SDMA_SDCM), SDMA_SDCM_AR | SDMA_SDCM_AT);
+
+ while ((in_le32((u32 *)(sdma_base + SDMA_SDCM))
+ & (SDMA_SDCM_AR | SDMA_SDCM_AT)) != 0)
+ udelay(100);
+}
+
+static volatile char *mpsc_get_virtreg_of_phandle(void *devp, char *prop)
+{
+ void *v;
+ int n;
+
+ n = getprop(devp, prop, &v, sizeof(v));
+ if (n != sizeof(v))
+ goto err_out;
+
+ devp = find_node_by_linuxphandle((u32)v);
+ if (devp == NULL)
+ goto err_out;
+
+ n = getprop(devp, "virtual-reg", &v, sizeof(v));
+ if (n == sizeof(v))
+ return v;
+
+err_out:
+ return NULL;
+}
+
+int mpsc_console_init(void *devp, struct serial_console_data *scdp)
+{
+ void *v;
+ int n, reg_set;
+ volatile char *sdma_base;
+
+ n = getprop(devp, "virtual-reg", &v, sizeof(v));
+ if (n != sizeof(v))
+ goto err_out;
+ mpsc_base = v;
+
+ sdma_base = mpsc_get_virtreg_of_phandle(devp, "sdma");
+ if (sdma_base == NULL)
+ goto err_out;
+
+ mpscintr_base = mpsc_get_virtreg_of_phandle(devp, "mpscintr");
+ if (mpscintr_base == NULL)
+ goto err_out;
+
+ n = getprop(devp, "block-index", &v, sizeof(v));
+ if (n != sizeof(v))
+ goto err_out;
+ reg_set = (int)v;
+
+ mpscintr_base += (reg_set == 0) ? 0x4 : 0xc;
+
+ /* Make sure the mpsc ctlrs are shutdown */
+ out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0);
+ out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0);
+ out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0);
+ out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0);
+
+ mpsc_stop_dma(sdma_base);
+
+ scdp->open = mpsc_open;
+ scdp->putc = mpsc_putc;
+ scdp->getc = mpsc_getc;
+ scdp->tstc = mpsc_tstc;
+ scdp->close = NULL;
+
+ return 0;
+
+err_out:
+ return -1;
+}
Index: powerpc/arch/powerpc/boot/serial.c
===================================================================
--- powerpc.orig/arch/powerpc/boot/serial.c
+++ powerpc/arch/powerpc/boot/serial.c
@@ -125,6 +125,8 @@ int serial_console_init(void)
if (!strcmp(compat, "ns16550"))
rc = ns16550_console_init(devp, &serial_cd);
+ else if (!strcmp(compat, "mpsc"))
+ rc = mpsc_console_init(devp, &serial_cd);
/* Add other serial console driver calls here */
Index: powerpc/arch/powerpc/boot/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/boot/Makefile
+++ powerpc/arch/powerpc/boot/Makefile
@@ -42,7 +42,7 @@ $(addprefix $(obj)/,$(zlib) main.o): $(a
src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
ns16550.c serial.c simple_alloc.c div64.S util.S \
- gunzip_util.c elf_util.c devtree.c mv64x60.c $(zlib)
+ gunzip_util.c elf_util.c devtree.c mv64x60.c mpsc.c $(zlib)
src-plat := of.c cuboot-83xx.c
src-boot := $(src-wlib) $(src-plat) empty.c
Index: powerpc/arch/powerpc/boot/ops.h
===================================================================
--- powerpc.orig/arch/powerpc/boot/ops.h
+++ powerpc/arch/powerpc/boot/ops.h
@@ -79,6 +79,7 @@ void start(void);
int ft_init(void *dt_blob, unsigned int max_size, unsigned int max_find_device);
int serial_console_init(void);
int ns16550_console_init(void *devp, struct serial_console_data *scdp);
+int mpsc_console_init(void *devp, struct serial_console_data *scdp);
void *simple_alloc_init(char *base, unsigned long heap_size,
unsigned long granularity, unsigned long max_allocs);
extern void flush_cache(void *, unsigned long);
^ permalink raw reply
* [PATCH 3/13] powerpc: Add bootwrapper support for Marvell/mv64x60 hostbridge
From: Mark A. Greer @ 2007-04-25 23:56 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
Makefile | 2
mv64x60.c | 581 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
mv64x60.h | 70 +++++++
3 files changed, 652 insertions(+), 1 deletion(-)
Index: powerpc/arch/powerpc/boot/mv64x60.c
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/mv64x60.c
@@ -0,0 +1,581 @@
+/*
+ * Marvell hostbridge routines
+ *
+ * Author: Mark A. Greer <source@mvista.com>
+ *
+ * 2004, 2005, 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "page.h"
+#include "string.h"
+#include "stdio.h"
+#include "io.h"
+#include "ops.h"
+#include "mv64x60.h"
+
+#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
+
+#define MV64x60_CPU2MEM_WINDOWS 4
+#define MV64x60_CPU2MEM_0_BASE 0x0008
+#define MV64x60_CPU2MEM_0_SIZE 0x0010
+#define MV64x60_CPU2MEM_1_BASE 0x0208
+#define MV64x60_CPU2MEM_1_SIZE 0x0210
+#define MV64x60_CPU2MEM_2_BASE 0x0018
+#define MV64x60_CPU2MEM_2_SIZE 0x0020
+#define MV64x60_CPU2MEM_3_BASE 0x0218
+#define MV64x60_CPU2MEM_3_SIZE 0x0220
+
+#define MV64x60_ENET2MEM_BAR_ENABLE 0x2290
+#define MV64x60_ENET2MEM_0_BASE 0x2200
+#define MV64x60_ENET2MEM_0_SIZE 0x2204
+#define MV64x60_ENET2MEM_1_BASE 0x2208
+#define MV64x60_ENET2MEM_1_SIZE 0x220c
+#define MV64x60_ENET2MEM_2_BASE 0x2210
+#define MV64x60_ENET2MEM_2_SIZE 0x2214
+#define MV64x60_ENET2MEM_3_BASE 0x2218
+#define MV64x60_ENET2MEM_3_SIZE 0x221c
+#define MV64x60_ENET2MEM_4_BASE 0x2220
+#define MV64x60_ENET2MEM_4_SIZE 0x2224
+#define MV64x60_ENET2MEM_5_BASE 0x2228
+#define MV64x60_ENET2MEM_5_SIZE 0x222c
+#define MV64x60_ENET2MEM_ACC_PROT_0 0x2294
+#define MV64x60_ENET2MEM_ACC_PROT_1 0x2298
+#define MV64x60_ENET2MEM_ACC_PROT_2 0x229c
+
+#define MV64x60_MPSC2MEM_BAR_ENABLE 0xf250
+#define MV64x60_MPSC2MEM_0_BASE 0xf200
+#define MV64x60_MPSC2MEM_0_SIZE 0xf204
+#define MV64x60_MPSC2MEM_1_BASE 0xf208
+#define MV64x60_MPSC2MEM_1_SIZE 0xf20c
+#define MV64x60_MPSC2MEM_2_BASE 0xf210
+#define MV64x60_MPSC2MEM_2_SIZE 0xf214
+#define MV64x60_MPSC2MEM_3_BASE 0xf218
+#define MV64x60_MPSC2MEM_3_SIZE 0xf21c
+#define MV64x60_MPSC_0_REMAP 0xf240
+#define MV64x60_MPSC_1_REMAP 0xf244
+#define MV64x60_MPSC2MEM_ACC_PROT_0 0xf254
+#define MV64x60_MPSC2MEM_ACC_PROT_1 0xf258
+#define MV64x60_MPSC2REGS_BASE 0xf25c
+
+#define MV64x60_IDMA2MEM_BAR_ENABLE 0x0a80
+#define MV64x60_IDMA2MEM_0_BASE 0x0a00
+#define MV64x60_IDMA2MEM_0_SIZE 0x0a04
+#define MV64x60_IDMA2MEM_1_BASE 0x0a08
+#define MV64x60_IDMA2MEM_1_SIZE 0x0a0c
+#define MV64x60_IDMA2MEM_2_BASE 0x0a10
+#define MV64x60_IDMA2MEM_2_SIZE 0x0a14
+#define MV64x60_IDMA2MEM_3_BASE 0x0a18
+#define MV64x60_IDMA2MEM_3_SIZE 0x0a1c
+#define MV64x60_IDMA2MEM_4_BASE 0x0a20
+#define MV64x60_IDMA2MEM_4_SIZE 0x0a24
+#define MV64x60_IDMA2MEM_5_BASE 0x0a28
+#define MV64x60_IDMA2MEM_5_SIZE 0x0a2c
+#define MV64x60_IDMA2MEM_6_BASE 0x0a30
+#define MV64x60_IDMA2MEM_6_SIZE 0x0a34
+#define MV64x60_IDMA2MEM_7_BASE 0x0a38
+#define MV64x60_IDMA2MEM_7_SIZE 0x0a3c
+#define MV64x60_IDMA2MEM_ACC_PROT_0 0x0a70
+#define MV64x60_IDMA2MEM_ACC_PROT_1 0x0a74
+#define MV64x60_IDMA2MEM_ACC_PROT_2 0x0a78
+#define MV64x60_IDMA2MEM_ACC_PROT_3 0x0a7c
+
+#define MV64x60_PCI_ACC_CNTL_WINDOWS 6
+#define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c
+#define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc
+
+#define MV64x60_PCI0_BAR_ENABLE 0x0c3c
+#define MV64x60_PCI02MEM_0_SIZE 0x0c08
+#define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00
+#define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04
+#define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08
+#define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10
+#define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14
+#define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18
+#define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20
+#define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24
+#define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28
+#define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30
+#define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34
+#define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38
+#define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40
+#define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44
+#define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48
+#define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50
+#define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54
+#define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58
+
+#define MV64x60_PCI1_BAR_ENABLE 0x0cbc
+#define MV64x60_PCI12MEM_0_SIZE 0x0c88
+#define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80
+#define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84
+#define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88
+#define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90
+#define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94
+#define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98
+#define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0
+#define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4
+#define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8
+#define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0
+#define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4
+#define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8
+#define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0
+#define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4
+#define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8
+#define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0
+#define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4
+#define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8
+
+#define MV64x60_CPU2PCI_SWAP_NONE 0x01000000
+
+#define MV64x60_CPU2PCI0_IO_BASE 0x0048
+#define MV64x60_CPU2PCI0_IO_SIZE 0x0050
+#define MV64x60_CPU2PCI0_IO_REMAP 0x00f0
+#define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058
+#define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060
+#define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8
+#define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320
+
+#define MV64x60_CPU2PCI1_IO_BASE 0x0090
+#define MV64x60_CPU2PCI1_IO_SIZE 0x0098
+#define MV64x60_CPU2PCI1_IO_REMAP 0x0108
+#define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0
+#define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8
+#define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110
+#define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340
+
+struct mv64x60_mem_win {
+ u32 hi;
+ u32 lo;
+ u32 size;
+};
+
+struct mv64x60_pci_win {
+ u32 fcn;
+ u32 hi;
+ u32 lo;
+ u32 size;
+};
+
+/* PCI config access routines */
+struct {
+ u32 addr;
+ u32 data;
+} static mv64x60_pci_cfgio[2] = {
+ { /* hose 0 */
+ .addr = 0xcf8,
+ .data = 0xcfc,
+ },
+ { /* hose 1 */
+ .addr = 0xc78,
+ .data = 0xc7c,
+ }
+};
+
+u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset)
+{
+ out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),
+ (1 << 31) | (bus << 16) | (devfn << 8) | offset);
+ return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data));
+}
+
+void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset,
+ u32 val)
+{
+ out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),
+ (1 << 31) | (bus << 16) | (devfn << 8) | offset);
+ out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val);
+}
+
+/* I/O ctlr -> system memory setup */
+static struct mv64x60_mem_win mv64x60_cpu2mem[MV64x60_CPU2MEM_WINDOWS] = {
+ {
+ .lo = MV64x60_CPU2MEM_0_BASE,
+ .size = MV64x60_CPU2MEM_0_SIZE,
+ },
+ {
+ .lo = MV64x60_CPU2MEM_1_BASE,
+ .size = MV64x60_CPU2MEM_1_SIZE,
+ },
+ {
+ .lo = MV64x60_CPU2MEM_2_BASE,
+ .size = MV64x60_CPU2MEM_2_SIZE,
+ },
+ {
+ .lo = MV64x60_CPU2MEM_3_BASE,
+ .size = MV64x60_CPU2MEM_3_SIZE,
+ },
+};
+
+static struct mv64x60_mem_win mv64x60_enet2mem[MV64x60_CPU2MEM_WINDOWS] = {
+ {
+ .lo = MV64x60_ENET2MEM_0_BASE,
+ .size = MV64x60_ENET2MEM_0_SIZE,
+ },
+ {
+ .lo = MV64x60_ENET2MEM_1_BASE,
+ .size = MV64x60_ENET2MEM_1_SIZE,
+ },
+ {
+ .lo = MV64x60_ENET2MEM_2_BASE,
+ .size = MV64x60_ENET2MEM_2_SIZE,
+ },
+ {
+ .lo = MV64x60_ENET2MEM_3_BASE,
+ .size = MV64x60_ENET2MEM_3_SIZE,
+ },
+};
+
+static struct mv64x60_mem_win mv64x60_mpsc2mem[MV64x60_CPU2MEM_WINDOWS] = {
+ {
+ .lo = MV64x60_MPSC2MEM_0_BASE,
+ .size = MV64x60_MPSC2MEM_0_SIZE,
+ },
+ {
+ .lo = MV64x60_MPSC2MEM_1_BASE,
+ .size = MV64x60_MPSC2MEM_1_SIZE,
+ },
+ {
+ .lo = MV64x60_MPSC2MEM_2_BASE,
+ .size = MV64x60_MPSC2MEM_2_SIZE,
+ },
+ {
+ .lo = MV64x60_MPSC2MEM_3_BASE,
+ .size = MV64x60_MPSC2MEM_3_SIZE,
+ },
+};
+
+static struct mv64x60_mem_win mv64x60_idma2mem[MV64x60_CPU2MEM_WINDOWS] = {
+ {
+ .lo = MV64x60_IDMA2MEM_0_BASE,
+ .size = MV64x60_IDMA2MEM_0_SIZE,
+ },
+ {
+ .lo = MV64x60_IDMA2MEM_1_BASE,
+ .size = MV64x60_IDMA2MEM_1_SIZE,
+ },
+ {
+ .lo = MV64x60_IDMA2MEM_2_BASE,
+ .size = MV64x60_IDMA2MEM_2_SIZE,
+ },
+ {
+ .lo = MV64x60_IDMA2MEM_3_BASE,
+ .size = MV64x60_IDMA2MEM_3_SIZE,
+ },
+};
+
+static u32 mv64x60_dram_selects[MV64x60_CPU2MEM_WINDOWS] = {0xe,0xd,0xb,0x7};
+
+/*
+ * ENET, MPSC, and IDMA ctlrs on the MV64x60 have separate windows that
+ * must be set up so that the respective ctlr can access system memory.
+ * Configure them to be same as cpu->memory windows.
+ */
+void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
+ u8 is_coherent)
+{
+ u32 i, base, size, enables, prot = 0, snoop_bits = 0;
+
+ /* Disable ctlr->mem windows */
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f);
+ out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf);
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0xff);
+
+ if (is_coherent)
+ snoop_bits = 0x2 << 12; /* Writeback */
+
+ enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
+
+ for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
+ if (enables & (1 << i)) /* Set means disabled */
+ continue;
+
+ base = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].lo))
+ << 16;
+ base |= snoop_bits | (mv64x60_dram_selects[i] << 8);
+ size = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].size))
+ << 16;
+ prot |= (0x3 << (i << 1)); /* RW access */
+
+ out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].lo), base);
+ out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].size), size);
+ out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].lo), base);
+ out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].size), size);
+ out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].lo), base);
+ out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].size), size);
+ }
+
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_0), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_1), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_2), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_0), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_1), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_0), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_1), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_2), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_3), prot);
+
+ /* Set mpsc->bridge's reg window to the bridge's internal registers. */
+ out_le32((u32 *)(bridge_base + MV64x60_MPSC2REGS_BASE),
+ (u32)bridge_pbase);
+
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), enables);
+ out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), enables);
+ out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_BAR_ENABLE), enables);
+}
+
+/* PCI MEM -> system memory, et. al. setup */
+static struct mv64x60_pci_win mv64x60_pci2mem[2] = {
+ { /* hose 0 */
+ .fcn = 0,
+ .hi = 0x14,
+ .lo = 0x10,
+ .size = MV64x60_PCI02MEM_0_SIZE,
+ },
+ { /* hose 1 */
+ .fcn = 0,
+ .hi = 0x94,
+ .lo = 0x90,
+ .size = MV64x60_PCI12MEM_0_SIZE,
+ },
+};
+
+static struct
+mv64x60_mem_win mv64x60_pci_acc[2][MV64x60_PCI_ACC_CNTL_WINDOWS] = {
+ { /* hose 0 */
+ {
+ .hi = MV64x60_PCI0_ACC_CNTL_0_BASE_HI,
+ .lo = MV64x60_PCI0_ACC_CNTL_0_BASE_LO,
+ .size = MV64x60_PCI0_ACC_CNTL_0_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI0_ACC_CNTL_1_BASE_HI,
+ .lo = MV64x60_PCI0_ACC_CNTL_1_BASE_LO,
+ .size = MV64x60_PCI0_ACC_CNTL_1_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI0_ACC_CNTL_2_BASE_HI,
+ .lo = MV64x60_PCI0_ACC_CNTL_2_BASE_LO,
+ .size = MV64x60_PCI0_ACC_CNTL_2_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI0_ACC_CNTL_3_BASE_HI,
+ .lo = MV64x60_PCI0_ACC_CNTL_3_BASE_LO,
+ .size = MV64x60_PCI0_ACC_CNTL_3_SIZE,
+ },
+ },
+ { /* hose 1 */
+ {
+ .hi = MV64x60_PCI1_ACC_CNTL_0_BASE_HI,
+ .lo = MV64x60_PCI1_ACC_CNTL_0_BASE_LO,
+ .size = MV64x60_PCI1_ACC_CNTL_0_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI1_ACC_CNTL_1_BASE_HI,
+ .lo = MV64x60_PCI1_ACC_CNTL_1_BASE_LO,
+ .size = MV64x60_PCI1_ACC_CNTL_1_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI1_ACC_CNTL_2_BASE_HI,
+ .lo = MV64x60_PCI1_ACC_CNTL_2_BASE_LO,
+ .size = MV64x60_PCI1_ACC_CNTL_2_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI1_ACC_CNTL_3_BASE_HI,
+ .lo = MV64x60_PCI1_ACC_CNTL_3_BASE_LO,
+ .size = MV64x60_PCI1_ACC_CNTL_3_SIZE,
+ },
+ },
+};
+
+static struct mv64x60_mem_win mv64x60_pci2reg[2] = {
+ {
+ .hi = 0x24,
+ .lo = 0x20,
+ .size = 0,
+ },
+ {
+ .hi = 0xa4,
+ .lo = 0xa0,
+ .size = 0,
+ },
+};
+
+/* Only need to use 1 window (per hose) to get access to all of system memory */
+void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
+ u8 bus, u32 mem_size, u32 acc_bits)
+{
+ u32 i, offset, bar_enable, enables;
+
+ /* Disable all windows but PCI MEM -> Bridge's regs window */
+ enables = ~(1 << 9);
+ bar_enable = hose ? MV64x60_PCI1_BAR_ENABLE : MV64x60_PCI0_BAR_ENABLE;
+ out_le32((u32 *)(bridge_base + bar_enable), enables);
+
+ for (i=0; i<MV64x60_PCI_ACC_CNTL_WINDOWS; i++)
+ out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][i].lo), 0);
+
+ /* If mem_size is 0, leave windows disabled */
+ if (mem_size == 0)
+ return;
+
+ /* Cause automatic updates of PCI remap regs */
+ offset = hose ?
+ MV64x60_PCI1_PCI_DECODE_CNTL : MV64x60_PCI0_PCI_DECODE_CNTL;
+ i = in_le32((u32 *)(bridge_base + offset));
+ out_le32((u32 *)(bridge_base + offset), i & ~0x1);
+
+ mem_size = (mem_size - 1) & 0xfffff000;
+
+ /* Map PCI MEM addr 0 -> System Mem addr 0 */
+ mv64x60_cfg_write(bridge_base, hose, bus,
+ PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn),
+ mv64x60_pci2mem[hose].hi, 0);
+ mv64x60_cfg_write(bridge_base, hose, bus,
+ PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn),
+ mv64x60_pci2mem[hose].lo, 0);
+ out_le32((u32 *)(bridge_base + mv64x60_pci2mem[hose].size),mem_size);
+
+ acc_bits |= MV64x60_PCI_ACC_CNTL_ENABLE;
+ out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].hi), 0);
+ out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].lo), acc_bits);
+ out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].size),mem_size);
+
+ /* Set PCI MEM->bridge's reg window to where they are in CPU mem map */
+ i = (u32)bridge_base;
+ i &= 0xffff0000;
+ i |= (0x2 << 1);
+ mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),
+ mv64x60_pci2reg[hose].hi, 0);
+ mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),
+ mv64x60_pci2reg[hose].lo, i);
+
+ enables &= ~0x1; /* Enable PCI MEM -> System Mem window 0 */
+ out_le32((u32 *)(bridge_base + bar_enable), enables);
+}
+
+/* CPU -> PCI I/O & MEM setup */
+struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2] = {
+ { /* hose 0 */
+ .lo = MV64x60_CPU2PCI0_IO_BASE,
+ .size = MV64x60_CPU2PCI0_IO_SIZE,
+ .remap_hi = 0,
+ .remap_lo = MV64x60_CPU2PCI0_IO_REMAP,
+ },
+ { /* hose 1 */
+ .lo = MV64x60_CPU2PCI1_IO_BASE,
+ .size = MV64x60_CPU2PCI1_IO_SIZE,
+ .remap_hi = 0,
+ .remap_lo = MV64x60_CPU2PCI1_IO_REMAP,
+ },
+};
+
+struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2] = {
+ { /* hose 0 */
+ .lo = MV64x60_CPU2PCI0_MEM_0_BASE,
+ .size = MV64x60_CPU2PCI0_MEM_0_SIZE,
+ .remap_hi = MV64x60_CPU2PCI0_MEM_0_REMAP_HI,
+ .remap_lo = MV64x60_CPU2PCI0_MEM_0_REMAP_LO,
+ },
+ { /* hose 1 */
+ .lo = MV64x60_CPU2PCI1_MEM_0_BASE,
+ .size = MV64x60_CPU2PCI1_MEM_0_SIZE,
+ .remap_hi = MV64x60_CPU2PCI1_MEM_0_REMAP_HI,
+ .remap_lo = MV64x60_CPU2PCI1_MEM_0_REMAP_LO,
+ },
+};
+
+/* Only need to set up 1 window to pci mem space */
+void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
+ u32 pci_base_lo, u32 cpu_base, u32 size,
+ struct mv64x60_cpu2pci_win *offset_tbl)
+{
+ cpu_base >>= 16;
+ cpu_base |= MV64x60_CPU2PCI_SWAP_NONE;
+ out_le32((u32 *)(bridge_base + offset_tbl[hose].lo), cpu_base);
+
+ if (offset_tbl[hose].remap_hi != 0)
+ out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_hi),
+ pci_base_hi);
+ out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_lo),
+ pci_base_lo >> 16);
+
+ size = (size - 1) >> 16;
+ out_le32((u32 *)(bridge_base + offset_tbl[hose].size), size);
+}
+
+/* Read mem ctlr to get the amount of mem in system */
+u32 mv64x60_get_mem_size(u8 *bridge_base)
+{
+ u32 enables, i, v;
+ u32 mem = 0;
+
+ enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
+
+ for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
+ if (!(enables & (1<<i))) {
+ v = in_le32((u32*)(bridge_base
+ + mv64x60_cpu2mem[i].size));
+ v = ((v & 0xffff) + 1) << 16;
+ mem += v;
+ }
+
+ return mem;
+}
+
+/* Get physical address of bridge's registers */
+u8 *mv64x60_get_bridge_pbase(void)
+{
+ u32 v[2];
+ void *devp;
+
+ devp = finddevice("/mv64x60");
+ if (devp == NULL)
+ goto err_out;
+ if (getprop(devp, "reg", v, sizeof(v)) != sizeof(v))
+ goto err_out;
+
+ return (u8 *)v[0];
+
+err_out:
+ return 0;
+}
+
+/* Get virtual address of bridge's registers */
+u8 *mv64x60_get_bridge_base(void)
+{
+ u32 v;
+ void *devp;
+
+ devp = finddevice("/mv64x60");
+ if (devp == NULL)
+ goto err_out;
+ if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
+ goto err_out;
+
+ return (u8 *)v;
+
+err_out:
+ return 0;
+}
+
+u8 mv64x60_is_coherent(void)
+{
+ u32 v;
+ void *devp;
+
+ devp = finddevice("/");
+ if (devp == NULL)
+ return 1; /* Assume coherency on */
+
+ if (getprop(devp, "coherency-off", &v, sizeof(v)) < 0)
+ return 1; /* Coherency on */
+ else
+ return 0;
+}
Index: powerpc/arch/powerpc/boot/mv64x60.h
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/mv64x60.h
@@ -0,0 +1,70 @@
+/*
+ * Author: Mark A. Greer <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef _PPC_BOOT_MV64x60_H_
+#define _PPC_BOOT_MV64x60_H_
+
+#define MV64x60_CPU_BAR_ENABLE 0x0278
+
+#define MV64x60_PCI_ACC_CNTL_ENABLE (1<<0)
+#define MV64x60_PCI_ACC_CNTL_REQ64 (1<<1)
+#define MV64x60_PCI_ACC_CNTL_SNOOP_NONE 0x00000000
+#define MV64x60_PCI_ACC_CNTL_SNOOP_WT 0x00000004
+#define MV64x60_PCI_ACC_CNTL_SNOOP_WB 0x00000008
+#define MV64x60_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c
+#define MV64x60_PCI_ACC_CNTL_ACCPROT (1<<4)
+#define MV64x60_PCI_ACC_CNTL_WRPROT (1<<5)
+#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
+#define MV64x60_PCI_ACC_CNTL_SWAP_NONE 0x00000040
+#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080
+#define MV64x60_PCI_ACC_CNTL_SWAP_WORD 0x000000c0
+#define MV64x60_PCI_ACC_CNTL_SWAP_MASK 0x000000c0
+#define MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000
+#define MV64x60_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100
+#define MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200
+#define MV64x60_PCI_ACC_CNTL_MBURST_MASK 0x00000300
+#define MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000
+#define MV64x60_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400
+#define MV64x60_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800
+#define MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00
+#define MV64x60_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00
+
+struct mv64x60_cpu2pci_win {
+ u32 lo;
+ u32 size;
+ u32 remap_hi;
+ u32 remap_lo;
+};
+
+extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2];
+extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2];
+
+u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
+ u8 offset);
+void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
+ u8 offset, u32 val);
+
+void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
+ u8 is_coherent);
+void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
+ u8 bus, u32 mem_size, u32 acc_bits);
+void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
+ u32 pci_base_lo, u32 cpu_base, u32 size,
+ struct mv64x60_cpu2pci_win *offset_tbl);
+u32 mv64x60_get_mem_size(u8 *bridge_base);
+u8 *mv64x60_get_bridge_pbase(void);
+u8 *mv64x60_get_bridge_base(void);
+u8 mv64x60_is_coherent(void);
+
+int mv64x60_i2c_open(void);
+int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size,
+ u32 count);
+void mv64x60_i2c_close(void);
+
+#endif /* _PPC_BOOT_MV64x60_H_ */
Index: powerpc/arch/powerpc/boot/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/boot/Makefile
+++ powerpc/arch/powerpc/boot/Makefile
@@ -42,7 +42,7 @@ $(addprefix $(obj)/,$(zlib) main.o): $(a
src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
ns16550.c serial.c simple_alloc.c div64.S util.S \
- gunzip_util.c elf_util.c $(zlib) devtree.c
+ gunzip_util.c elf_util.c devtree.c mv64x60.c $(zlib)
src-plat := of.c cuboot-83xx.c
src-boot := $(src-wlib) $(src-plat) empty.c
^ permalink raw reply
* [PATCH 2/13] powerpc: Add dt_xlate_addr() to bootwrapper
From: Mark A. Greer @ 2007-04-25 23:55 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
dt_xlate_reg() looks up the 'reg' property in the specified node
to get the address and size to translate. Add dt_xlate_addr()
which is passed in the address and size to translate.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
devtree.c | 45 ++++++++++++++++++++++++++++++++-------------
ops.h | 4 ++--
2 files changed, 34 insertions(+), 15 deletions(-)
Index: powerpc/arch/powerpc/boot/devtree.c
===================================================================
--- powerpc.orig/arch/powerpc/boot/devtree.c
+++ powerpc/arch/powerpc/boot/devtree.c
@@ -205,12 +205,13 @@ static int find_range(u32 *reg, u32 *ran
* In particular, PCI is not supported. Also, only the beginning of the
* reg block is tracked; size is ignored except in ranges.
*/
-int dt_xlate_reg(void *node, int res, unsigned long *addr,
- unsigned long *size)
+static u32 dt_xlate_buf[MAX_ADDR_CELLS * MAX_RANGES * 3];
+
+static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
+ unsigned long *size)
{
u32 last_addr[MAX_ADDR_CELLS];
u32 this_addr[MAX_ADDR_CELLS];
- u32 buf[MAX_ADDR_CELLS * MAX_RANGES * 3];
void *parent;
u64 ret_addr, ret_size;
u32 naddr, nsize, prev_naddr;
@@ -225,18 +226,17 @@ int dt_xlate_reg(void *node, int res, un
if (nsize > 2)
return 0;
- buflen = getprop(node, "reg", buf, sizeof(buf)) / 4;
offset = (naddr + nsize) * res;
- if (buflen < offset + naddr + nsize)
+ if (reglen < offset + naddr + nsize)
return 0;
- copy_val(last_addr, buf + offset, naddr);
+ copy_val(last_addr, dt_xlate_buf + offset, naddr);
- ret_size = buf[offset + naddr];
+ ret_size = dt_xlate_buf[offset + naddr];
if (nsize == 2) {
ret_size <<= 32;
- ret_size |= buf[offset + naddr + 1];
+ ret_size |= dt_xlate_buf[offset + naddr + 1];
}
while ((node = get_parent(node))) {
@@ -244,24 +244,25 @@ int dt_xlate_reg(void *node, int res, un
get_reg_format(node, &naddr, &nsize);
- buflen = getprop(node, "ranges", buf, sizeof(buf));
+ buflen = getprop(node, "ranges", dt_xlate_buf,
+ sizeof(dt_xlate_buf));
if (buflen < 0)
continue;
- if (buflen > sizeof(buf))
+ if (buflen > sizeof(dt_xlate_buf))
return 0;
- offset = find_range(last_addr, buf, prev_naddr,
+ offset = find_range(last_addr, dt_xlate_buf, prev_naddr,
naddr, nsize, buflen / 4);
if (offset < 0)
return 0;
- copy_val(this_addr, buf + offset, prev_naddr);
+ copy_val(this_addr, dt_xlate_buf + offset, prev_naddr);
if (!sub_reg(last_addr, this_addr))
return 0;
- copy_val(this_addr, buf + offset + prev_naddr, naddr);
+ copy_val(this_addr, dt_xlate_buf + offset + prev_naddr, naddr);
if (!add_reg(last_addr, this_addr))
return 0;
@@ -287,3 +288,21 @@ int dt_xlate_reg(void *node, int res, un
return 1;
}
+
+int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size)
+{
+ int reglen;
+
+ reglen = getprop(node, "reg", dt_xlate_buf, sizeof(dt_xlate_buf)) / 4;
+ return dt_xlate(node, res, reglen, addr, size);
+}
+
+int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr)
+{
+
+ if (buflen > sizeof(dt_xlate_buf))
+ return 0;
+
+ memcpy(dt_xlate_buf, buf, buflen);
+ return dt_xlate(node, 0, buflen / 4, xlated_addr, NULL);
+}
Index: powerpc/arch/powerpc/boot/ops.h
===================================================================
--- powerpc.orig/arch/powerpc/boot/ops.h
+++ powerpc/arch/powerpc/boot/ops.h
@@ -82,8 +82,8 @@ int ns16550_console_init(void *devp, str
void *simple_alloc_init(char *base, unsigned long heap_size,
unsigned long granularity, unsigned long max_allocs);
extern void flush_cache(void *, unsigned long);
-int dt_xlate_reg(void *node, int res, unsigned long *addr,
- unsigned long *size);
+int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size);
+int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr);
static inline void *finddevice(const char *name)
{
^ permalink raw reply
* [PATCH 1/13] powerpc: Add Makefile rule to wrap dts file in zImage
From: Mark A. Greer @ 2007-04-25 23:55 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070425234630.GA4046@mag.az.mvista.com>
Add 'zImage.dts' and 'zImage.dts_initrd' build rules that automatically
compile and wrap a dts file into the zImage file. The rules are similar
to the initrd rules.
The dts file is expected to be arch/powerpc/boot/dts/$(CONFIG_DEVICE_TREE)
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
Makefile | 2 +-
boot/Makefile | 24 +++++++++++++++++++++++-
2 files changed, 24 insertions(+), 2 deletions(-)
Index: powerpc/arch/powerpc/boot/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/boot/Makefile
+++ powerpc/arch/powerpc/boot/Makefile
@@ -144,9 +144,27 @@ targets += $(image-y) $(initrd-y)
$(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image.gz
+dts- := $(patsubst zImage%, zImage.dts%, $(image-n) $(image-))
+dts-y := $(patsubst zImage%, zImage.dts%, $(image-y))
+dts-y := $(filter-out $(image-y), $(dts-y))
+targets += $(image-y) $(dts-y)
+
+dts_initrd- := $(patsubst zImage%, zImage.dts_initrd%, $(image-n) $(image-))
+dts_initrd-y := $(patsubst zImage%, zImage.dts_initrd%, $(image-y))
+dts_initrd-y := $(filter-out $(image-y), $(dts_initrd-y))
+targets += $(image-y) $(dts_initrd-y)
+
+$(addprefix $(obj)/, $(dts_initrd-y)): $(obj)/ramdisk.image.gz
+
# Don't put the ramdisk on the pattern rule; when its missing make will try
# the pattern rule with less dependencies that also matches (even with the
# hard dependency listed).
+$(obj)/zImage.dts_initrd.%: vmlinux $(wrapperbits)
+ $(call if_changed,wrap,$*,$(dts),,$(obj)/ramdisk.image.gz)
+
+$(obj)/zImage.dts.%: vmlinux $(wrapperbits)
+ $(call if_changed,wrap,$*,$(dts))
+
$(obj)/zImage.initrd.%: vmlinux $(wrapperbits)
$(call if_changed,wrap,$*,,,$(obj)/ramdisk.image.gz)
@@ -175,13 +193,17 @@ $(obj)/zImage: $(addprefix $(obj)/, $(i
@rm -f $@; ln $< $@
$(obj)/zImage.initrd: $(addprefix $(obj)/, $(initrd-y))
@rm -f $@; ln $< $@
+$(obj)/zImage.dts: $(addprefix $(obj)/, $(dts-y))
+ @rm -f $@; ln $< $@
+$(obj)/zImage.dts_initrd: $(addprefix $(obj)/, $(dts_initrd-y))
+ @rm -f $@; ln $< $@
install: $(CONFIGURE) $(image-y)
sh -x $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" vmlinux System.map "$(INSTALL_PATH)" $<
# anything not in $(targets)
clean-files += $(image-) $(initrd-) zImage zImage.initrd \
- cuImage.elf cuImage.bin.gz
+ cuImage.elf cuImage.bin.gz zImage.dts zImage.dts_initrd
# clean up files cached by wrapper
clean-kernel := vmlinux.strip vmlinux.bin
Index: powerpc/arch/powerpc/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/Makefile
+++ powerpc/arch/powerpc/Makefile
@@ -148,7 +148,7 @@ all: $(KBUILD_IMAGE)
CPPFLAGS_vmlinux.lds := -Upowerpc
-BOOT_TARGETS = zImage zImage.initrd uImage cuImage
+BOOT_TARGETS = zImage zImage.initrd zImage.dts zImage.dts_initrd uImage cuImage
PHONY += $(BOOT_TARGETS)
^ permalink raw reply
* Re: [PATCH] [2.6.22] edac: pasemi_edac backend driver
From: Arnd Bergmann @ 2007-04-25 23:48 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Olof Johansson, egor, norsk5, bluesmoke-devel
In-Reply-To: <20070425204309.GA19781@lixom.net>
On Wednesday 25 April 2007, Olof Johansson wrote:
> EDAC driver for the memory controllers on PA Semi PA6T-1682M.
Despite my best effort at nitpicking, I can't find anything wrong with
this driver ;-)
> Signed-off-by: Egor Martovetsky <egor@pasemi.com>
> Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
^ permalink raw reply
* Re: [PATCH] [2.6.22] pasemi: cpufreq driver
From: Arnd Bergmann @ 2007-04-25 23:47 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Olof Johansson, egor, paulus, cpufreq
In-Reply-To: <20070425204633.GC19781@lixom.net>
On Wednesday 25 April 2007, Olof Johansson wrote:
> +/* This should eventually come out of the device tree */
> +#define SDCPWR_BASE 0xfc104000
> +#define SDCPWR_SIZE 0x1000
> +
> +#define SDCASR_BASE 0xfc120000
> +#define SDCASR_SIZE 0x2000
the comment is right. Why don't you do it then? ;-)
> +static int pas_cpufreq_cpu_init (struct cpufreq_policy *policy)
> +{
> + u32 *max_freq;
> + int i, cur_astate;
> + struct device_node *cpu;
> +
> + cpu = of_get_cpu_node(policy->cpu, NULL);
> +
> + if(!cpu)
> + return -ENODEV;
> +
> + sdcpwr_mapbase = ioremap(SDCPWR_BASE, SDCPWR_SIZE);
> + sdcasr_mapbase = ioremap(SDCASR_BASE, SDCASR_SIZE);
> + if (!sdcpwr_mapbase || !sdcasr_mapbase)
> + panic("SDCMAP: Cannot map registers!");
I can't see any check in here that finds out if you are actually running on
the right hardware.
The proper way to implement this driver would be to register an
of_platform_driver for the cpufreq device and then get the register
addresses from there,
> @@ -155,7 +155,7 @@ source "drivers/cpufreq/Kconfig"
>
> config CPU_FREQ_PMAC
> bool "Support for Apple PowerBooks"
> - depends on CPU_FREQ && ADB_PMU && PPC32
> + depends on ADB_PMU && PPC32
> select CPU_FREQ_TABLE
> help
> This adds support for frequency switching on Apple PowerBooks,
> @@ -164,11 +164,21 @@ config CPU_FREQ_PMAC
>
> config CPU_FREQ_PMAC64
> bool "Support for some Apple G5s"
> - depends on CPU_FREQ && PPC64
> + depends on PPC64
> select CPU_FREQ_TABLE
> help
> This adds support for frequency switching on Apple iMac G5,
> and some of the more recent desktop G5 machines as well.
Why this change?
> +config PPC_PASEMI_CPUFREQ
> + bool "Support for PA Semi PWRficient"
> + depends on PPC_PASEMI
> + default y
> + select CPU_FREQ_TABLE
> + help
> + This adds the support for frequency switching on PA Semi
> + PWRficient processors.
> +
> endmenu
Why bool and not tristate?
Arnd <><
^ permalink raw reply
* [PATCH 0/13] powerpc: Add support for Marvell/mv64x60 and prpmc2800
From: Mark A. Greer @ 2007-04-25 23:46 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
The following set of patches add support for the Motorola prpmc2800/f101e platform.
To support that platform, several other patches are required that can be grouped as
follows:
- 1 patch to add Makefile rules that automatically compile & wrap a dts into
a zImage
- 1 patch to add a new interface to the dt_xlate code.
- 3 mv64x60 bootwrapper patches
- 5 mv64x60 kernel patches
- 3 prpmc2800 patches
Mark
^ permalink raw reply
* Re: [PATCH] [2.6.22] pasemi: hardware rng driver
From: Arnd Bergmann @ 2007-04-25 23:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Olof Johansson, egor, mb
In-Reply-To: <20070425204512.GB19781@lixom.net>
On Wednesday 25 April 2007, Olof Johansson wrote:
> +static void __iomem *rng_regs;
> +
> +static int pasemi_rng_data_present(struct hwrng *rng)
> +{
> + return (in_le32(rng_regs + SDCRNG_CTL_REG)
> + & SDCRNG_CTL_FVLD_M) ? 1 : 0;
> +}
It would be nicer to get rid of the global rng_regs variable by sticking
it into rng->priv.
> +static int __devinit rng_probe(struct of_device *ofdev,
> + const struct of_device_id *match)
> +{
> + struct device_node *rng_np;
> + struct resource res;
> + int err = 0;
> +
> + rng_np = of_find_compatible_node(NULL, "rng", "1682m-rng");
> + if (!rng_np)
> + return -ENODEV;
I would guess that the call to of_find_compatible_node is entirely bogus
here, because the device is already passed in as ofdev in to the probe
function.
> +int rng_init(void)
> +{
> + return of_register_platform_driver(&rng_driver);
> +}
> +
> +void rng_exit(void)
> +{
> + of_unregister_platform_driver(&rng_driver);
> +}
> +
> +device_initcall(rng_init);
rng_init and rng_exit should be static
rng_init should be __init
rng_exit should be __exit
Since the driver is tristate in Kconfig, it would be more conventional to
use module_init() instead of device_initcall().
rng_exit needs to be marked as module_exit() to allow unloading the driver.
Arnd <><
^ permalink raw reply
* Re: [PATCH 3/6] Consolidate of_find_property
From: David Miller @ 2007-04-25 23:28 UTC (permalink / raw)
To: segher; +Cc: linuxppc-dev, sfr, paulus
In-Reply-To: <86094f4e887d90dbff1be6d20e5fdd5c@kernel.crashing.org>
From: Segher Boessenkool <segher@kernel.crashing.org>
Date: Thu, 26 Apr 2007 01:18:59 +0200
> > Meanwhile any feedback on the idea of pushing all of this
> > consolidation and cleanup work through one of our trees
> > instead of having all of these difficult dependencies
> > between the two?
>
> Set up a branch in one of the Git repos that is for
> this consolidation work only, that both the arch trees
> can pull from? The beauty with Git is that this won't
> lead to merge problems :-)
I rebase my GIT tree as patches very often, and I have many direct
dependencies on this work both at the beginning and further along in
my tree.
So this won't work, that's why I haven't suggested it.
^ permalink raw reply
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