* Re: [PATCH] snd-aoa-i2sbus: use MODULE_DEVICE_TABLE instead of plain MODULE_ALIAS
From: Takashi Iwai @ 2007-05-10 16:29 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev list, ALSA development, Sylvain Munaut
In-Reply-To: <1178813914.3806.28.camel@johannes.berg>
At Thu, 10 May 2007 18:18:33 +0200,
Johannes Berg wrote:
>
> On Thu, 2007-05-10 at 18:00 +0200, Takashi Iwai wrote:
>
> > Well, the alsa.git push request was already posted twice, but it
> > wasn't merged yet... Hopefully Linus will catch up soon.
>
> This patch doesn't seem to be in perex/alsa.git either though, or are
> you pushing through some other tree now?
It's in linus branch.
Takashi
^ permalink raw reply
* Re: [PATCH] snd-aoa-i2sbus: use MODULE_DEVICE_TABLE instead of plain MODULE_ALIAS
From: Johannes Berg @ 2007-05-10 16:33 UTC (permalink / raw)
To: Takashi Iwai; +Cc: linuxppc-dev list, ALSA development, Sylvain Munaut
In-Reply-To: <1178813914.3806.28.camel@johannes.berg>
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On Thu, 2007-05-10 at 18:19 +0200, Johannes Berg wrote:
> This patch doesn't seem to be in perex/alsa.git either though, or are
> you pushing through some other tree now?
Ah, sorry, it's on the "linus" branch.
johannes
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^ permalink raw reply
* Re: [PATCH] Remove CPU_FTR_NEED_COHERENT for 7448.
From: Jon Loeliger @ 2007-05-10 16:44 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <Pine.LNX.4.64.0705101117200.6072@localhost.localdomain>
On Thu, 2007-05-10 at 11:17, Kumar Gala wrote:
> >
> > Remove CPU_FTR_NEED_COHERENT for MPC7448 (and single-core MPC86xx).
> > This prevents needlessly setting M=1 when not SMP.
> >
>
> applied.
>
> - k
Sweet. Thanks!
jdl
^ permalink raw reply
* 83xx: requesting external interrupts
From: Alex Zeffertt @ 2007-05-10 16:45 UTC (permalink / raw)
To: linuxppc-embedded
Hi list,
I'm trying to port a driver from 2.6.11 to 2.6.21 and I'm stuck on the following line:
request_irq(MPC83xx_IRQ_EXT5, mpc832xemds_phy_interrupt, SA_SHIRQ, "pm5384", dev);
The first problem is that MPC83xx_IRQ_EXT5 is no longer defined. If I hard code this to
what I think is the right value (i.e. 21) then request_irq fails on insmod.
I obviously need to do something different now that ARCH=powerpc, but I can't find any
examples of code which requests 83xx external interrupts. Can anybody help?
TIA,
Alex
^ permalink raw reply
* Re: [PATCH] Performance Stats: Kernel patch
From: Linas Vepstas @ 2007-05-10 16:47 UTC (permalink / raw)
To: Maxim Uvarov; +Cc: linuxppc-dev, Andrew Morton, pavel, wli, dada1
In-Reply-To: <4642F27E.10700@ru.mvista.com>
On Thu, May 10, 2007 at 10:22:54AM +0000, Maxim Uvarov wrote:
> Linas Vepstas wrote:
> >On Tue, May 08, 2007 at 04:26:51PM +0000, Maxim Uvarov wrote:
> >>+ addq $1, threadinfo_syscall_count(%rcx) # Increment syscalls
> >
> >again, #ifdef CONFIG_TASKSTATS,
>
> So I don't really sure if defines are needed in entry.S code. I tried
> to do
> some tests and it is impossible to catch the performance difference (small
> overhead).
"A penny here, and a penny there, and pretty soon it adds up to real
money". Its a hot path, and its an easy fix.
--linas
^ permalink raw reply
* [PATCH] powerpc: add dts entries to 85xx for EDAC
From: Dave Jiang @ 2007-05-10 17:03 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus
In-Reply-To: <3E2DA6EA-8952-47B3-A395-C416D7AC9D62@kernel.crashing.org>
Adding memory-controller and l2-cache-controller entries to be used by EDAC
as of_devices.
Signed-off-by: Dave Jiang <djiang@mvista.com>
---
Fixed up additional changes per Kumar.
arch/powerpc/boot/dts/mpc8540ads.dts | 16 ++++++++++++++++
arch/powerpc/boot/dts/mpc8548cds.dts | 16 ++++++++++++++++
arch/powerpc/boot/dts/mpc8560ads.dts | 18 +++++++++++++++++-
3 files changed, 49 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index f261d64..d91e81c 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -48,6 +48,22 @@
reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>;
+ memory-controller@2000 {
+ compatible = "fsl,8540-memory-controller";
+ reg = <2000 1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <2 2>;
+ };
+
+ l2-cache-controller@20000 {
+ compatible = "fsl,8540-l2-cache-controller";
+ reg = <20000 1000>;
+ cache-line-size = <20>; // 32 bytes
+ cache-size = <40000>; // L2, 256K
+ interrupt-parent = <&mpic>;
+ interrupts = <0 2>;
+ };
+
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index b2b2200..ad96381 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -48,6 +48,22 @@
reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>;
+ memory-controller@2000 {
+ compatible = "fsl,8548-memory-controller";
+ reg = <2000 1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <2 2>;
+ };
+
+ l2-cache-controller@20000 {
+ compatible = "fsl,8548-l2-cache-controller";
+ reg = <20000 1000>;
+ cache-line-size = <20>; // 32 bytes
+ cache-size = <80000>; // L2, 512K
+ interrupt-parent = <&mpic>;
+ interrupts = <0 2>;
+ };
+
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 1f2afe9..8068215 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -48,6 +48,22 @@
reg = <e0000000 00000200>;
bus-frequency = <13ab6680>;
+ memory-controller@2000 {
+ compatible = "fsl,8540-memory-controller";
+ reg = <2000 1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <2 2>;
+ };
+
+ l2-cache-controller@20000 {
+ compatible = "fsl,8540-l2-cache-controller";
+ reg = <20000 1000>;
+ cache-line-size = <20>; // 32 bytes
+ cache-size = <40000>; // L2, 256K
+ interrupt-parent = <&mpic>;
+ interrupts = <0 2>;
+ };
+
mdio@24520 {
device_type = "mdio";
compatible = "gianfar";
@@ -110,7 +126,7 @@
#address-cells = <3>;
compatible = "85xx";
device_type = "pci";
- reg = <8000 400>;
+ reg = <8000 1000>;
clock-frequency = <3f940aa>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
^ permalink raw reply related
* Re: 83xx: requesting external interrupts
From: Ben Warren @ 2007-05-10 17:07 UTC (permalink / raw)
To: Alex Zeffertt; +Cc: linuxppc-embedded
In-Reply-To: <46434C1E.3020004@cambridgebroadband.com>
Alex,
Follow this thread...
http://marc.info/?l=linuxppc-embedded&m=116849062702002&w=2
On Thu, 2007-05-10 at 17:45 +0100, Alex Zeffertt wrote:
> Hi list,
>
> I'm trying to port a driver from 2.6.11 to 2.6.21 and I'm stuck on the following line:
>
> request_irq(MPC83xx_IRQ_EXT5, mpc832xemds_phy_interrupt, SA_SHIRQ, "pm5384", dev);
>
> The first problem is that MPC83xx_IRQ_EXT5 is no longer defined. If I hard code this to
> what I think is the right value (i.e. 21) then request_irq fails on insmod.
>
> I obviously need to do something different now that ARCH=powerpc, but I can't find any
> examples of code which requests 83xx external interrupts. Can anybody help?
>
> TIA,
>
> Alex
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: Building ppc/powerpc kernel to run under QEMU.
From: Linas Vepstas @ 2007-05-10 17:28 UTC (permalink / raw)
To: Rob Landley; +Cc: linuxppc-dev
In-Reply-To: <200705092203.26042.rob@landley.net>
Hi Rob,
On Wed, May 09, 2007 at 10:03:25PM -0400, Rob Landley wrote:
> I've been puttering around with my Firmware Linux project trying to add
> powerpc as a supported platform. I can build kernels that qemu can boot (such
> as a "prep" kernel) using ARCH=ppc, but that one doesn't support make
> headers_install.
>
> Using ARCH=powerpc makes headers_install work, but there's no kernel .config
> I've been able to come up with that generates a kernel I can boot under qemu.
Hmm. I'm not a boot expert, (although many people on this list are).
Any hint of where the boot is failing? Maybe qemu is not setting up
a device tree?
> what's the status of the
> ppc->powerpc migration,
pretty far along; bits f ppc are getting nuked regularly.
> and is there any known way to get ARCH=powerpc to
> build a kernel qemu can boot?
Dunno...
--linas
^ permalink raw reply
* Fixed PHY problems
From: Joakim Tjernlund @ 2007-05-10 17:41 UTC (permalink / raw)
To: linuxppc-dev
Trying to boot todays linus tree with fixed PHY support enabled gets me this:
Fixed PHY: Registered new driver
Device 'fixed@100:1' does not have a release() function, it is broken and must be fixed.
------------[ cut here ]------------
Badness at drivers/base/core.c:107
Call Trace:
[cffc1dc0] [c0008324] show_stack+0x48/0x194 (unreliable)
[cffc1df0] [c00f4a4c] report_bug+0x84/0xec
[cffc1e00] [c000dde8] program_check_exception+0x274/0x55c
[cffc1e20] [c000f770] ret_from_except_full+0x0/0x4c
--- Exception: 700 at device_release+0x54/0x90
LR = device_release+0x54/0x90
[cffc1ef0] [c00f5e1c] kobject_cleanup+0xb4/0xb8
[cffc1f10] [c00f6ca0] kref_put+0x68/0x80
[cffc1f20] [c00f5d58] kobject_put+0x24/0x34
[cffc1f30] [c01150bc] put_device+0x1c/0x2c
[cffc1f40] [c0243a9c] fixed_init+0x1cc/0x210
[cffc1f60] [c022e828] kernel_init+0x8c/0x2b4
[cffc1ff0] [c000ff4c] kernel_thread+0x44/0x60
The other thing is, how do I specify a fixed PHY
in OF?
Jocke
^ permalink raw reply
* Re: [PATCH] Performance Stats: Kernel patch
From: Andrew Morton @ 2007-05-10 18:12 UTC (permalink / raw)
To: Maxim Uvarov; +Cc: linuxppc-dev, wli, pavel, dada1
In-Reply-To: <4642FDD6.5090609@ru.mvista.com>
On Thu, 10 May 2007 11:11:18 +0000 Maxim Uvarov <muvarov@ru.mvista.com> wrote:
> >syscall entry is a super-hotpath and there will be a developer revolt
> >if we go adding an incl to that path, sorry.
> >
> >
> >
> Yes, I know that it is very critical part of code. May be protection with
> ifdef CONFIG_TASKSTATS in all entry.S can be solution?
> In that case we can be sure that nothing wrong can not happen,
> and if this functionality is needed we can turn on this.
I very much hope that all distributors will enable taskstats, so that won't
help.
I don't think the syscall-counting feature has a future, sorry. Perhaps
you could do something like hooking it up on-demand by insertion of a kprobe,
dunno.
> >(Did that incl also cover the int 80 entry?)
> >
> >
> Actually not. But counter increments each time when syscall calls.
> But it is in very save place, just after
> SAVE_ALL
> GET_THREAD_INFO(%ebp)
> So it is very hard to break something.
>
What I meant was: the code appears to be counting sysenter-invoked syscalls,
but it isn't counting not int 80-invoked syscalls.
^ permalink raw reply
* Re: [PATCH] Performance Stats: Kernel patch
From: Andrew Morton @ 2007-05-10 18:25 UTC (permalink / raw)
To: Maxim Uvarov; +Cc: linuxppc-dev, pavel, wli, dada1
In-Reply-To: <20070510114221.7576.67522.stgit@localhost.localdomain>
On Thu, 10 May 2007 11:42:22 +0000 Maxim Uvarov <muvarov@ru.mvista.com> wrote:
> From: Maxim Uvarov <muvarov@ru.mvista.com>
> To: Andrew Morton <akpm@linux-foundation.org>
> Cc: <wli@holomorphy.com>, <dada1@cosmosbay.com>, <pavel@ucw.cz>, <linas@austin.ibm.com>
> Cc: linuxppc-dev@ozlabs.org
> Cc: <wli@holomorphy.com>, <dada1@cosmosbay.com>, <pavel@ucw.cz>, <linas@austin.ibm.com>
The addressees are still odd.
> Subject: [PATCH] Performance Stats: Kernel patch
> Date: Thu, 10 May 2007 11:42:22 +0000
> User-Agent: StGIT/0.12.1
>
>
> Patch makes available to the user the following
> task and process performance statistics:
> * Involuntary Context Switches (task_struct->nivcsw)
> * Voluntary Context Switches (task_struct->nvcsw)
> * Number of system calls (added new counter
> thread_info->sysall_count)
The patch looks good, thanks. Except, as I said, I don't think we can
justify the syscall counter. Yes, it's useful information and yes the
overhead is low.
But it adds overhead to every syscall on every machine in the world, which
is a lot of overhead. And the number of machines which actually _use_ that
information will be small.
But hey, I might be wrong - perhaps lots of people have a burning need for
this information. But we're not in a position to find that out because you
keep on mucking up the email recipient list :(
The patch is confused about the type of the syscall counter. In some
places it is "unsigned long" but it gets sent to userspace as __u32.
Considering that this counter can be overflowed in a matter of seconds, you
definitely want it to be 64-bit on 64-bit machines. And you probably want
it to be 64-bit on 32-bit machines as well. More overhead there though.
Anyway, I suggest you fix that up and rereresend the patch, getting the
headers correct and we'll ask a wider audience about the
value-versus-overhead issue.
I suspect we'll end up only supporting the context-switch counters. Given
that this requires an uprev to the taskstats interface, we should look at
whether there are other things which we should be exporting but which were
forgotten. I'll have a think about that sometime.
^ permalink raw reply
* [RFC/PATCH] Fixup WARNINGs related to COMMON symbol
From: Kumar Gala @ 2007-05-10 19:03 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
We now get the following warnings:
WARNING: "ee_restarts" [arch/powerpc/kernel/built-in] is COMMON symbol
WARNING: "fee_restarts" [arch/powerpc/kernel/built-in] is COMMON symbol
WARNING: "htab_hash_searches" [arch/powerpc/mm/built-in] is COMMON symbol
WARNING: "next_slot" [arch/powerpc/mm/built-in] is COMMON symbol
WARNING: "mmu_hash_lock" [arch/powerpc/mm/built-in] is COMMON symbol
WARNING: "primary_pteg_full" [arch/powerpc/mm/built-in] is COMMON symbol
because these symbols are defined as .comm. It is not clear if there is
any reason for these sybmols to be .comm. Only mmu_hash_lock is global
and needed outside of the file scope its defined in.
If this patch looks good, I'll spin a version for arch/ppc and repost.
- k
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index c29d165..c7082d0 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -596,7 +596,11 @@ fast_exception_return:
mr r12,r4 /* restart at exc_exit_restart */
b 2b
- .comm fee_restarts,4
+ .section .bss
+ .align 2
+fee_restarts:
+ .space 4
+ .text
/* aargh, a nonrecoverable interrupt, panic */
/* aargh, we don't know which trap this is */
@@ -851,7 +855,11 @@ load_dbcr0:
mtspr SPRN_DBSR,r11 /* clear all pending debug events */
blr
- .comm global_dbcr0,8
+ .section .bss
+ .align 4
+global_dbcr0:
+ .space 8
+ .text
#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
do_work: /* r10 contains MSR_KERNEL here */
@@ -926,7 +934,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_601)
/* shouldn't return */
b 4b
- .comm ee_restarts,4
+ .section .bss
+ .align 2
+ee_restarts:
+ .space 4
+ .text
/*
* PROM code for specific machines follows. Put it
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index ddceefc..8e1c059 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -30,7 +30,11 @@
#include <asm/asm-offsets.h>
#ifdef CONFIG_SMP
- .comm mmu_hash_lock,4
+ .section .bss
+ .align 2
+ .globl mmu_hash_lock
+mmu_hash_lock:
+ .space 4
#endif /* CONFIG_SMP */
/*
@@ -455,9 +459,15 @@ found_slot:
sync /* make sure pte updates get to memory */
blr
- .comm next_slot,4
- .comm primary_pteg_full,4
- .comm htab_hash_searches,4
+ .section .bss
+ .align 2
+next_slot:
+ .space 4
+primary_pteg_full:
+ .space 4
+htab_hash_searches:
+ .space 4
+ .text
/*
* Flush the entry for a particular page from the hash table.
diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h
^ permalink raw reply related
* [PATCH 0/13] powerpc: Add support for Marvell/mv64x60 and prpmc2800
From: Mark A. Greer @ 2007-05-10 20:02 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
This is the latest and hopefully last round of patches for adding mv64x60
and prpmc2800 support to arch/powerpc. It would be great if this could
still get into 2.6.22.
Thanks,
Mark
^ permalink raw reply
* [PATCH 1/13] powerpc: Add Makefile rules to wrap dts file in zImage
From: Mark A. Greer @ 2007-05-10 20:04 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
Add 'zImage.dts' and 'zImage.dts_initrd' build rules that automatically
compile and wrap a dts file from arch/powerpc/boot/dts into the zImage file.
The resulting zImage will be arch/powerpc/boot/zImage.dts.<platform> and
arch/powerpc/boot/zImage.dts_initrd.<platform>, respectively.
Having separate rules allows the user to choose whether to include a device
tree--and which device tree--at build time. This is useful when one Makefile
target builds a zImage that runs on several platforms except for differing
device trees. By just setting CONFIG_DEVICE_TREE and running "make zImage.dts"
the exact zImage you want is built without Makefile bloat or manually running
the wrapper script.
The dts file is expected to be arch/powerpc/boot/dts/$(CONFIG_DEVICE_TREE)
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
arch/powerpc/Makefile | 2 +-
arch/powerpc/boot/Makefile | 24 +++++++++++++++++++++++-
2 files changed, 24 insertions(+), 2 deletions(-)
Index: powerpc/arch/powerpc/boot/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/boot/Makefile
+++ powerpc/arch/powerpc/boot/Makefile
@@ -154,9 +154,27 @@ targets += $(image-y) $(initrd-y)
$(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image.gz
+dts- := $(patsubst zImage%, zImage.dts%, $(image-n) $(image-))
+dts-y := $(patsubst zImage%, zImage.dts%, $(image-y))
+dts-y := $(filter-out $(image-y), $(dts-y))
+targets += $(image-y) $(dts-y)
+
+dts_initrd- := $(patsubst zImage%, zImage.dts_initrd%, $(image-n) $(image-))
+dts_initrd-y := $(patsubst zImage%, zImage.dts_initrd%, $(image-y))
+dts_initrd-y := $(filter-out $(image-y), $(dts_initrd-y))
+targets += $(image-y) $(dts_initrd-y)
+
+$(addprefix $(obj)/, $(dts_initrd-y)): $(obj)/ramdisk.image.gz
+
# Don't put the ramdisk on the pattern rule; when its missing make will try
# the pattern rule with less dependencies that also matches (even with the
# hard dependency listed).
+$(obj)/zImage.dts_initrd.%: vmlinux $(wrapperbits)
+ $(call if_changed,wrap,$*,$(dts),,$(obj)/ramdisk.image.gz)
+
+$(obj)/zImage.dts.%: vmlinux $(wrapperbits)
+ $(call if_changed,wrap,$*,$(dts))
+
$(obj)/zImage.initrd.%: vmlinux $(wrapperbits)
$(call if_changed,wrap,$*,,,$(obj)/ramdisk.image.gz)
@@ -195,13 +213,17 @@ $(obj)/zImage: $(addprefix $(obj)/, $(i
@rm -f $@; ln $< $@
$(obj)/zImage.initrd: $(addprefix $(obj)/, $(initrd-y))
@rm -f $@; ln $< $@
+$(obj)/zImage.dts: $(addprefix $(obj)/, $(dts-y))
+ @rm -f $@; ln $< $@
+$(obj)/zImage.dts_initrd: $(addprefix $(obj)/, $(dts_initrd-y))
+ @rm -f $@; ln $< $@
install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
sh -x $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" vmlinux System.map "$(INSTALL_PATH)" $<
# anything not in $(targets)
clean-files += $(image-) $(initrd-) zImage zImage.initrd cuImage.* \
- treeImage.*
+ treeImage.* zImage.dts zImage.dts_initrd
# clean up files cached by wrapper
clean-kernel := vmlinux.strip vmlinux.bin
Index: powerpc/arch/powerpc/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/Makefile
+++ powerpc/arch/powerpc/Makefile
@@ -148,7 +148,7 @@ all: $(KBUILD_IMAGE)
CPPFLAGS_vmlinux.lds := -Upowerpc
-BOOT_TARGETS = zImage zImage.initrd uImage
+BOOT_TARGETS = zImage zImage.initrd zImage.dts zImage.dts_initrd uImage cuImage
PHONY += $(BOOT_TARGETS)
^ permalink raw reply
* [PATCH 2/13] powerpc: Add bootwrapper support for Marvell/mv64x60 hostbridge
From: Mark A. Greer @ 2007-05-10 20:05 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
The mv64x60 host bridge has many windows between its various components
(cpu, system memory, ethernet ctlr, MPSC, DMA ctlr, PCI MEM, PCI I/O).
Unfortunately, the firmware on some of mv64x60-based platforms do not
properly or completely configure those windows (e.g., MPSC->system memory
windows not configured or CPU->PCI MEM space not configured).
So, the missing configuration needs to be done in either the bootwrapper
or in the kernel. To keep the kernel as clean as possible, it is done
in the bootwrapper. Note that I/O controller configuration is NOT being
done, its only the windows to allow the I/O controllers and other components
to access memory, etc. that is being done--drivers assume that their
controllers can already access system memory).
Table of routines and the windows they configure:
mv64x60_config_ctlr_windows() ENET->System Memory
MPSC->System Memory
IDMA->System Memory
mv64x60_config_pci_windows() PCI MEM->System Memory
PCI I/O->Bridge's Registers
mv64x60_config_cpu2pci_window() CPU->PCI MEM
CPU->PCI I/O
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
arch/powerpc/boot/Makefile | 2
arch/powerpc/boot/mv64x60.c | 581 ++++++++++++++++++++++++++++++++++
arch/powerpc/boot/mv64x60.h | 70 ++++
3 files changed, 652 insertions(+), 1 deletion(-)
Index: powerpc/arch/powerpc/boot/mv64x60.c
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/mv64x60.c
@@ -0,0 +1,581 @@
+/*
+ * Marvell hostbridge routines
+ *
+ * Author: Mark A. Greer <source@mvista.com>
+ *
+ * 2004, 2005, 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "page.h"
+#include "string.h"
+#include "stdio.h"
+#include "io.h"
+#include "ops.h"
+#include "mv64x60.h"
+
+#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
+
+#define MV64x60_CPU2MEM_WINDOWS 4
+#define MV64x60_CPU2MEM_0_BASE 0x0008
+#define MV64x60_CPU2MEM_0_SIZE 0x0010
+#define MV64x60_CPU2MEM_1_BASE 0x0208
+#define MV64x60_CPU2MEM_1_SIZE 0x0210
+#define MV64x60_CPU2MEM_2_BASE 0x0018
+#define MV64x60_CPU2MEM_2_SIZE 0x0020
+#define MV64x60_CPU2MEM_3_BASE 0x0218
+#define MV64x60_CPU2MEM_3_SIZE 0x0220
+
+#define MV64x60_ENET2MEM_BAR_ENABLE 0x2290
+#define MV64x60_ENET2MEM_0_BASE 0x2200
+#define MV64x60_ENET2MEM_0_SIZE 0x2204
+#define MV64x60_ENET2MEM_1_BASE 0x2208
+#define MV64x60_ENET2MEM_1_SIZE 0x220c
+#define MV64x60_ENET2MEM_2_BASE 0x2210
+#define MV64x60_ENET2MEM_2_SIZE 0x2214
+#define MV64x60_ENET2MEM_3_BASE 0x2218
+#define MV64x60_ENET2MEM_3_SIZE 0x221c
+#define MV64x60_ENET2MEM_4_BASE 0x2220
+#define MV64x60_ENET2MEM_4_SIZE 0x2224
+#define MV64x60_ENET2MEM_5_BASE 0x2228
+#define MV64x60_ENET2MEM_5_SIZE 0x222c
+#define MV64x60_ENET2MEM_ACC_PROT_0 0x2294
+#define MV64x60_ENET2MEM_ACC_PROT_1 0x2298
+#define MV64x60_ENET2MEM_ACC_PROT_2 0x229c
+
+#define MV64x60_MPSC2MEM_BAR_ENABLE 0xf250
+#define MV64x60_MPSC2MEM_0_BASE 0xf200
+#define MV64x60_MPSC2MEM_0_SIZE 0xf204
+#define MV64x60_MPSC2MEM_1_BASE 0xf208
+#define MV64x60_MPSC2MEM_1_SIZE 0xf20c
+#define MV64x60_MPSC2MEM_2_BASE 0xf210
+#define MV64x60_MPSC2MEM_2_SIZE 0xf214
+#define MV64x60_MPSC2MEM_3_BASE 0xf218
+#define MV64x60_MPSC2MEM_3_SIZE 0xf21c
+#define MV64x60_MPSC_0_REMAP 0xf240
+#define MV64x60_MPSC_1_REMAP 0xf244
+#define MV64x60_MPSC2MEM_ACC_PROT_0 0xf254
+#define MV64x60_MPSC2MEM_ACC_PROT_1 0xf258
+#define MV64x60_MPSC2REGS_BASE 0xf25c
+
+#define MV64x60_IDMA2MEM_BAR_ENABLE 0x0a80
+#define MV64x60_IDMA2MEM_0_BASE 0x0a00
+#define MV64x60_IDMA2MEM_0_SIZE 0x0a04
+#define MV64x60_IDMA2MEM_1_BASE 0x0a08
+#define MV64x60_IDMA2MEM_1_SIZE 0x0a0c
+#define MV64x60_IDMA2MEM_2_BASE 0x0a10
+#define MV64x60_IDMA2MEM_2_SIZE 0x0a14
+#define MV64x60_IDMA2MEM_3_BASE 0x0a18
+#define MV64x60_IDMA2MEM_3_SIZE 0x0a1c
+#define MV64x60_IDMA2MEM_4_BASE 0x0a20
+#define MV64x60_IDMA2MEM_4_SIZE 0x0a24
+#define MV64x60_IDMA2MEM_5_BASE 0x0a28
+#define MV64x60_IDMA2MEM_5_SIZE 0x0a2c
+#define MV64x60_IDMA2MEM_6_BASE 0x0a30
+#define MV64x60_IDMA2MEM_6_SIZE 0x0a34
+#define MV64x60_IDMA2MEM_7_BASE 0x0a38
+#define MV64x60_IDMA2MEM_7_SIZE 0x0a3c
+#define MV64x60_IDMA2MEM_ACC_PROT_0 0x0a70
+#define MV64x60_IDMA2MEM_ACC_PROT_1 0x0a74
+#define MV64x60_IDMA2MEM_ACC_PROT_2 0x0a78
+#define MV64x60_IDMA2MEM_ACC_PROT_3 0x0a7c
+
+#define MV64x60_PCI_ACC_CNTL_WINDOWS 6
+#define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c
+#define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc
+
+#define MV64x60_PCI0_BAR_ENABLE 0x0c3c
+#define MV64x60_PCI02MEM_0_SIZE 0x0c08
+#define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00
+#define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04
+#define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08
+#define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10
+#define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14
+#define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18
+#define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20
+#define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24
+#define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28
+#define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30
+#define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34
+#define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38
+#define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40
+#define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44
+#define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48
+#define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50
+#define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54
+#define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58
+
+#define MV64x60_PCI1_BAR_ENABLE 0x0cbc
+#define MV64x60_PCI12MEM_0_SIZE 0x0c88
+#define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80
+#define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84
+#define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88
+#define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90
+#define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94
+#define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98
+#define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0
+#define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4
+#define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8
+#define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0
+#define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4
+#define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8
+#define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0
+#define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4
+#define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8
+#define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0
+#define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4
+#define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8
+
+#define MV64x60_CPU2PCI_SWAP_NONE 0x01000000
+
+#define MV64x60_CPU2PCI0_IO_BASE 0x0048
+#define MV64x60_CPU2PCI0_IO_SIZE 0x0050
+#define MV64x60_CPU2PCI0_IO_REMAP 0x00f0
+#define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058
+#define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060
+#define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8
+#define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320
+
+#define MV64x60_CPU2PCI1_IO_BASE 0x0090
+#define MV64x60_CPU2PCI1_IO_SIZE 0x0098
+#define MV64x60_CPU2PCI1_IO_REMAP 0x0108
+#define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0
+#define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8
+#define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110
+#define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340
+
+struct mv64x60_mem_win {
+ u32 hi;
+ u32 lo;
+ u32 size;
+};
+
+struct mv64x60_pci_win {
+ u32 fcn;
+ u32 hi;
+ u32 lo;
+ u32 size;
+};
+
+/* PCI config access routines */
+struct {
+ u32 addr;
+ u32 data;
+} static mv64x60_pci_cfgio[2] = {
+ { /* hose 0 */
+ .addr = 0xcf8,
+ .data = 0xcfc,
+ },
+ { /* hose 1 */
+ .addr = 0xc78,
+ .data = 0xc7c,
+ }
+};
+
+u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset)
+{
+ out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),
+ (1 << 31) | (bus << 16) | (devfn << 8) | offset);
+ return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data));
+}
+
+void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset,
+ u32 val)
+{
+ out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),
+ (1 << 31) | (bus << 16) | (devfn << 8) | offset);
+ out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val);
+}
+
+/* I/O ctlr -> system memory setup */
+static struct mv64x60_mem_win mv64x60_cpu2mem[MV64x60_CPU2MEM_WINDOWS] = {
+ {
+ .lo = MV64x60_CPU2MEM_0_BASE,
+ .size = MV64x60_CPU2MEM_0_SIZE,
+ },
+ {
+ .lo = MV64x60_CPU2MEM_1_BASE,
+ .size = MV64x60_CPU2MEM_1_SIZE,
+ },
+ {
+ .lo = MV64x60_CPU2MEM_2_BASE,
+ .size = MV64x60_CPU2MEM_2_SIZE,
+ },
+ {
+ .lo = MV64x60_CPU2MEM_3_BASE,
+ .size = MV64x60_CPU2MEM_3_SIZE,
+ },
+};
+
+static struct mv64x60_mem_win mv64x60_enet2mem[MV64x60_CPU2MEM_WINDOWS] = {
+ {
+ .lo = MV64x60_ENET2MEM_0_BASE,
+ .size = MV64x60_ENET2MEM_0_SIZE,
+ },
+ {
+ .lo = MV64x60_ENET2MEM_1_BASE,
+ .size = MV64x60_ENET2MEM_1_SIZE,
+ },
+ {
+ .lo = MV64x60_ENET2MEM_2_BASE,
+ .size = MV64x60_ENET2MEM_2_SIZE,
+ },
+ {
+ .lo = MV64x60_ENET2MEM_3_BASE,
+ .size = MV64x60_ENET2MEM_3_SIZE,
+ },
+};
+
+static struct mv64x60_mem_win mv64x60_mpsc2mem[MV64x60_CPU2MEM_WINDOWS] = {
+ {
+ .lo = MV64x60_MPSC2MEM_0_BASE,
+ .size = MV64x60_MPSC2MEM_0_SIZE,
+ },
+ {
+ .lo = MV64x60_MPSC2MEM_1_BASE,
+ .size = MV64x60_MPSC2MEM_1_SIZE,
+ },
+ {
+ .lo = MV64x60_MPSC2MEM_2_BASE,
+ .size = MV64x60_MPSC2MEM_2_SIZE,
+ },
+ {
+ .lo = MV64x60_MPSC2MEM_3_BASE,
+ .size = MV64x60_MPSC2MEM_3_SIZE,
+ },
+};
+
+static struct mv64x60_mem_win mv64x60_idma2mem[MV64x60_CPU2MEM_WINDOWS] = {
+ {
+ .lo = MV64x60_IDMA2MEM_0_BASE,
+ .size = MV64x60_IDMA2MEM_0_SIZE,
+ },
+ {
+ .lo = MV64x60_IDMA2MEM_1_BASE,
+ .size = MV64x60_IDMA2MEM_1_SIZE,
+ },
+ {
+ .lo = MV64x60_IDMA2MEM_2_BASE,
+ .size = MV64x60_IDMA2MEM_2_SIZE,
+ },
+ {
+ .lo = MV64x60_IDMA2MEM_3_BASE,
+ .size = MV64x60_IDMA2MEM_3_SIZE,
+ },
+};
+
+static u32 mv64x60_dram_selects[MV64x60_CPU2MEM_WINDOWS] = {0xe,0xd,0xb,0x7};
+
+/*
+ * ENET, MPSC, and IDMA ctlrs on the MV64x60 have separate windows that
+ * must be set up so that the respective ctlr can access system memory.
+ * Configure them to be same as cpu->memory windows.
+ */
+void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
+ u8 is_coherent)
+{
+ u32 i, base, size, enables, prot = 0, snoop_bits = 0;
+
+ /* Disable ctlr->mem windows */
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f);
+ out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf);
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0xff);
+
+ if (is_coherent)
+ snoop_bits = 0x2 << 12; /* Writeback */
+
+ enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
+
+ for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
+ if (enables & (1 << i)) /* Set means disabled */
+ continue;
+
+ base = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].lo))
+ << 16;
+ base |= snoop_bits | (mv64x60_dram_selects[i] << 8);
+ size = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].size))
+ << 16;
+ prot |= (0x3 << (i << 1)); /* RW access */
+
+ out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].lo), base);
+ out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].size), size);
+ out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].lo), base);
+ out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].size), size);
+ out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].lo), base);
+ out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].size), size);
+ }
+
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_0), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_1), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_2), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_0), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_1), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_0), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_1), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_2), prot);
+ out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_3), prot);
+
+ /* Set mpsc->bridge's reg window to the bridge's internal registers. */
+ out_le32((u32 *)(bridge_base + MV64x60_MPSC2REGS_BASE),
+ (u32)bridge_pbase);
+
+ out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), enables);
+ out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), enables);
+ out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_BAR_ENABLE), enables);
+}
+
+/* PCI MEM -> system memory, et. al. setup */
+static struct mv64x60_pci_win mv64x60_pci2mem[2] = {
+ { /* hose 0 */
+ .fcn = 0,
+ .hi = 0x14,
+ .lo = 0x10,
+ .size = MV64x60_PCI02MEM_0_SIZE,
+ },
+ { /* hose 1 */
+ .fcn = 0,
+ .hi = 0x94,
+ .lo = 0x90,
+ .size = MV64x60_PCI12MEM_0_SIZE,
+ },
+};
+
+static struct
+mv64x60_mem_win mv64x60_pci_acc[2][MV64x60_PCI_ACC_CNTL_WINDOWS] = {
+ { /* hose 0 */
+ {
+ .hi = MV64x60_PCI0_ACC_CNTL_0_BASE_HI,
+ .lo = MV64x60_PCI0_ACC_CNTL_0_BASE_LO,
+ .size = MV64x60_PCI0_ACC_CNTL_0_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI0_ACC_CNTL_1_BASE_HI,
+ .lo = MV64x60_PCI0_ACC_CNTL_1_BASE_LO,
+ .size = MV64x60_PCI0_ACC_CNTL_1_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI0_ACC_CNTL_2_BASE_HI,
+ .lo = MV64x60_PCI0_ACC_CNTL_2_BASE_LO,
+ .size = MV64x60_PCI0_ACC_CNTL_2_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI0_ACC_CNTL_3_BASE_HI,
+ .lo = MV64x60_PCI0_ACC_CNTL_3_BASE_LO,
+ .size = MV64x60_PCI0_ACC_CNTL_3_SIZE,
+ },
+ },
+ { /* hose 1 */
+ {
+ .hi = MV64x60_PCI1_ACC_CNTL_0_BASE_HI,
+ .lo = MV64x60_PCI1_ACC_CNTL_0_BASE_LO,
+ .size = MV64x60_PCI1_ACC_CNTL_0_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI1_ACC_CNTL_1_BASE_HI,
+ .lo = MV64x60_PCI1_ACC_CNTL_1_BASE_LO,
+ .size = MV64x60_PCI1_ACC_CNTL_1_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI1_ACC_CNTL_2_BASE_HI,
+ .lo = MV64x60_PCI1_ACC_CNTL_2_BASE_LO,
+ .size = MV64x60_PCI1_ACC_CNTL_2_SIZE,
+ },
+ {
+ .hi = MV64x60_PCI1_ACC_CNTL_3_BASE_HI,
+ .lo = MV64x60_PCI1_ACC_CNTL_3_BASE_LO,
+ .size = MV64x60_PCI1_ACC_CNTL_3_SIZE,
+ },
+ },
+};
+
+static struct mv64x60_mem_win mv64x60_pci2reg[2] = {
+ {
+ .hi = 0x24,
+ .lo = 0x20,
+ .size = 0,
+ },
+ {
+ .hi = 0xa4,
+ .lo = 0xa0,
+ .size = 0,
+ },
+};
+
+/* Only need to use 1 window (per hose) to get access to all of system memory */
+void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
+ u8 bus, u32 mem_size, u32 acc_bits)
+{
+ u32 i, offset, bar_enable, enables;
+
+ /* Disable all windows but PCI MEM -> Bridge's regs window */
+ enables = ~(1 << 9);
+ bar_enable = hose ? MV64x60_PCI1_BAR_ENABLE : MV64x60_PCI0_BAR_ENABLE;
+ out_le32((u32 *)(bridge_base + bar_enable), enables);
+
+ for (i=0; i<MV64x60_PCI_ACC_CNTL_WINDOWS; i++)
+ out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][i].lo), 0);
+
+ /* If mem_size is 0, leave windows disabled */
+ if (mem_size == 0)
+ return;
+
+ /* Cause automatic updates of PCI remap regs */
+ offset = hose ?
+ MV64x60_PCI1_PCI_DECODE_CNTL : MV64x60_PCI0_PCI_DECODE_CNTL;
+ i = in_le32((u32 *)(bridge_base + offset));
+ out_le32((u32 *)(bridge_base + offset), i & ~0x1);
+
+ mem_size = (mem_size - 1) & 0xfffff000;
+
+ /* Map PCI MEM addr 0 -> System Mem addr 0 */
+ mv64x60_cfg_write(bridge_base, hose, bus,
+ PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn),
+ mv64x60_pci2mem[hose].hi, 0);
+ mv64x60_cfg_write(bridge_base, hose, bus,
+ PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn),
+ mv64x60_pci2mem[hose].lo, 0);
+ out_le32((u32 *)(bridge_base + mv64x60_pci2mem[hose].size),mem_size);
+
+ acc_bits |= MV64x60_PCI_ACC_CNTL_ENABLE;
+ out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].hi), 0);
+ out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].lo), acc_bits);
+ out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].size),mem_size);
+
+ /* Set PCI MEM->bridge's reg window to where they are in CPU mem map */
+ i = (u32)bridge_base;
+ i &= 0xffff0000;
+ i |= (0x2 << 1);
+ mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),
+ mv64x60_pci2reg[hose].hi, 0);
+ mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),
+ mv64x60_pci2reg[hose].lo, i);
+
+ enables &= ~0x1; /* Enable PCI MEM -> System Mem window 0 */
+ out_le32((u32 *)(bridge_base + bar_enable), enables);
+}
+
+/* CPU -> PCI I/O & MEM setup */
+struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2] = {
+ { /* hose 0 */
+ .lo = MV64x60_CPU2PCI0_IO_BASE,
+ .size = MV64x60_CPU2PCI0_IO_SIZE,
+ .remap_hi = 0,
+ .remap_lo = MV64x60_CPU2PCI0_IO_REMAP,
+ },
+ { /* hose 1 */
+ .lo = MV64x60_CPU2PCI1_IO_BASE,
+ .size = MV64x60_CPU2PCI1_IO_SIZE,
+ .remap_hi = 0,
+ .remap_lo = MV64x60_CPU2PCI1_IO_REMAP,
+ },
+};
+
+struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2] = {
+ { /* hose 0 */
+ .lo = MV64x60_CPU2PCI0_MEM_0_BASE,
+ .size = MV64x60_CPU2PCI0_MEM_0_SIZE,
+ .remap_hi = MV64x60_CPU2PCI0_MEM_0_REMAP_HI,
+ .remap_lo = MV64x60_CPU2PCI0_MEM_0_REMAP_LO,
+ },
+ { /* hose 1 */
+ .lo = MV64x60_CPU2PCI1_MEM_0_BASE,
+ .size = MV64x60_CPU2PCI1_MEM_0_SIZE,
+ .remap_hi = MV64x60_CPU2PCI1_MEM_0_REMAP_HI,
+ .remap_lo = MV64x60_CPU2PCI1_MEM_0_REMAP_LO,
+ },
+};
+
+/* Only need to set up 1 window to pci mem space */
+void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
+ u32 pci_base_lo, u32 cpu_base, u32 size,
+ struct mv64x60_cpu2pci_win *offset_tbl)
+{
+ cpu_base >>= 16;
+ cpu_base |= MV64x60_CPU2PCI_SWAP_NONE;
+ out_le32((u32 *)(bridge_base + offset_tbl[hose].lo), cpu_base);
+
+ if (offset_tbl[hose].remap_hi != 0)
+ out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_hi),
+ pci_base_hi);
+ out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_lo),
+ pci_base_lo >> 16);
+
+ size = (size - 1) >> 16;
+ out_le32((u32 *)(bridge_base + offset_tbl[hose].size), size);
+}
+
+/* Read mem ctlr to get the amount of mem in system */
+u32 mv64x60_get_mem_size(u8 *bridge_base)
+{
+ u32 enables, i, v;
+ u32 mem = 0;
+
+ enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
+
+ for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
+ if (!(enables & (1<<i))) {
+ v = in_le32((u32*)(bridge_base
+ + mv64x60_cpu2mem[i].size));
+ v = ((v & 0xffff) + 1) << 16;
+ mem += v;
+ }
+
+ return mem;
+}
+
+/* Get physical address of bridge's registers */
+u8 *mv64x60_get_bridge_pbase(void)
+{
+ u32 v[2];
+ void *devp;
+
+ devp = finddevice("/mv64x60");
+ if (devp == NULL)
+ goto err_out;
+ if (getprop(devp, "reg", v, sizeof(v)) != sizeof(v))
+ goto err_out;
+
+ return (u8 *)v[0];
+
+err_out:
+ return 0;
+}
+
+/* Get virtual address of bridge's registers */
+u8 *mv64x60_get_bridge_base(void)
+{
+ u32 v;
+ void *devp;
+
+ devp = finddevice("/mv64x60");
+ if (devp == NULL)
+ goto err_out;
+ if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
+ goto err_out;
+
+ return (u8 *)v;
+
+err_out:
+ return 0;
+}
+
+u8 mv64x60_is_coherent(void)
+{
+ u32 v;
+ void *devp;
+
+ devp = finddevice("/");
+ if (devp == NULL)
+ return 1; /* Assume coherency on */
+
+ if (getprop(devp, "coherency-off", &v, sizeof(v)) < 0)
+ return 1; /* Coherency on */
+ else
+ return 0;
+}
Index: powerpc/arch/powerpc/boot/mv64x60.h
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/mv64x60.h
@@ -0,0 +1,70 @@
+/*
+ * Author: Mark A. Greer <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef _PPC_BOOT_MV64x60_H_
+#define _PPC_BOOT_MV64x60_H_
+
+#define MV64x60_CPU_BAR_ENABLE 0x0278
+
+#define MV64x60_PCI_ACC_CNTL_ENABLE (1<<0)
+#define MV64x60_PCI_ACC_CNTL_REQ64 (1<<1)
+#define MV64x60_PCI_ACC_CNTL_SNOOP_NONE 0x00000000
+#define MV64x60_PCI_ACC_CNTL_SNOOP_WT 0x00000004
+#define MV64x60_PCI_ACC_CNTL_SNOOP_WB 0x00000008
+#define MV64x60_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c
+#define MV64x60_PCI_ACC_CNTL_ACCPROT (1<<4)
+#define MV64x60_PCI_ACC_CNTL_WRPROT (1<<5)
+#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
+#define MV64x60_PCI_ACC_CNTL_SWAP_NONE 0x00000040
+#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080
+#define MV64x60_PCI_ACC_CNTL_SWAP_WORD 0x000000c0
+#define MV64x60_PCI_ACC_CNTL_SWAP_MASK 0x000000c0
+#define MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000
+#define MV64x60_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100
+#define MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200
+#define MV64x60_PCI_ACC_CNTL_MBURST_MASK 0x00000300
+#define MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000
+#define MV64x60_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400
+#define MV64x60_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800
+#define MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00
+#define MV64x60_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00
+
+struct mv64x60_cpu2pci_win {
+ u32 lo;
+ u32 size;
+ u32 remap_hi;
+ u32 remap_lo;
+};
+
+extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2];
+extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2];
+
+u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
+ u8 offset);
+void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
+ u8 offset, u32 val);
+
+void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
+ u8 is_coherent);
+void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
+ u8 bus, u32 mem_size, u32 acc_bits);
+void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
+ u32 pci_base_lo, u32 cpu_base, u32 size,
+ struct mv64x60_cpu2pci_win *offset_tbl);
+u32 mv64x60_get_mem_size(u8 *bridge_base);
+u8 *mv64x60_get_bridge_pbase(void);
+u8 *mv64x60_get_bridge_base(void);
+u8 mv64x60_is_coherent(void);
+
+int mv64x60_i2c_open(void);
+int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size,
+ u32 count);
+void mv64x60_i2c_close(void);
+
+#endif /* _PPC_BOOT_MV64x60_H_ */
Index: powerpc/arch/powerpc/boot/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/boot/Makefile
+++ powerpc/arch/powerpc/boot/Makefile
@@ -43,7 +43,7 @@ $(addprefix $(obj)/,$(zlib) gunzip_util.
src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
ns16550.c serial.c simple_alloc.c div64.S util.S \
gunzip_util.c elf_util.c $(zlib) devtree.c \
- 44x.c ebony.c
+ 44x.c ebony.c mv64x60.c
src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \
cuboot-ebony.c treeboot-ebony.c
src-boot := $(src-wlib) $(src-plat) empty.c
^ permalink raw reply
* [PATCH 3/13] powerpc: Add bootwrapper support for Marvell MPSC
From: Mark A. Greer @ 2007-05-10 20:05 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
The bootwrapper requires a serial driver to allow cmdline editing
and information reporting on the console. This driver is required
by platforms that boot a zImage and use the MPSC for the console.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
arch/powerpc/boot/Makefile | 2
arch/powerpc/boot/mpsc.c | 170 +++++++++++++++++++++++++++++++++++
arch/powerpc/boot/ops.h | 1
arch/powerpc/boot/serial.c | 2
4 files changed, 174 insertions(+), 1 deletion(-)
Index: powerpc/arch/powerpc/boot/mpsc.c
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/mpsc.c
@@ -0,0 +1,170 @@
+/*
+ * MPSC/UART driver for the Marvell mv64360, mv64460, ...
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "string.h"
+#include "stdio.h"
+#include "io.h"
+#include "ops.h"
+
+extern void udelay(long delay);
+
+#define MPSC_CHR_1 0x000c
+
+#define MPSC_CHR_2 0x0010
+#define MPSC_CHR_2_TA (1<<7)
+#define MPSC_CHR_2_TCS (1<<9)
+#define MPSC_CHR_2_RA (1<<23)
+#define MPSC_CHR_2_CRD (1<<25)
+#define MPSC_CHR_2_EH (1<<31)
+
+#define MPSC_CHR_4 0x0018
+#define MPSC_CHR_4_Z (1<<29)
+
+#define MPSC_CHR_5 0x001c
+#define MPSC_CHR_5_CTL1_INTR (1<<12)
+#define MPSC_CHR_5_CTL1_VALID (1<<15)
+
+#define MPSC_CHR_10 0x0030
+
+#define MPSC_INTR_CAUSE 0x0000
+#define MPSC_INTR_CAUSE_RCC (1<<6)
+#define MPSC_INTR_MASK 0x0080
+
+#define SDMA_SDCM 0x0008
+#define SDMA_SDCM_AR (1<<15)
+#define SDMA_SDCM_AT (1<<31)
+
+static volatile char *mpsc_base;
+static volatile char *mpscintr_base;
+static u32 chr1, chr2;
+
+static int mpsc_open(void)
+{
+ chr1 = in_le32((u32 *)(mpsc_base + MPSC_CHR_1)) & 0x00ff0000;
+ chr2 = in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & ~(MPSC_CHR_2_TA
+ | MPSC_CHR_2_TCS | MPSC_CHR_2_RA | MPSC_CHR_2_CRD
+ | MPSC_CHR_2_EH);
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_4), MPSC_CHR_4_Z);
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_5),
+ MPSC_CHR_5_CTL1_INTR | MPSC_CHR_5_CTL1_VALID);
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_EH);
+ return 0;
+}
+
+static void mpsc_putc(unsigned char c)
+{
+ while (in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & MPSC_CHR_2_TCS);
+
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_1), chr1 | c);
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_TCS);
+}
+
+static unsigned char mpsc_getc(void)
+{
+ u32 cause = 0;
+ unsigned char c;
+
+ while (!(cause & MPSC_INTR_CAUSE_RCC))
+ cause = in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE));
+
+ c = in_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2));
+ out_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2), c);
+ out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE),
+ cause & ~MPSC_INTR_CAUSE_RCC);
+
+ return c;
+}
+
+static u8 mpsc_tstc(void)
+{
+ return (u8)((in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE))
+ & MPSC_INTR_CAUSE_RCC) != 0);
+}
+
+static void mpsc_stop_dma(volatile char *sdma_base)
+{
+ out_le32((u32 *)(mpsc_base + MPSC_CHR_2),MPSC_CHR_2_TA | MPSC_CHR_2_RA);
+ out_le32((u32 *)(sdma_base + SDMA_SDCM), SDMA_SDCM_AR | SDMA_SDCM_AT);
+
+ while ((in_le32((u32 *)(sdma_base + SDMA_SDCM))
+ & (SDMA_SDCM_AR | SDMA_SDCM_AT)) != 0)
+ udelay(100);
+}
+
+static volatile char *mpsc_get_virtreg_of_phandle(void *devp, char *prop)
+{
+ void *v;
+ int n;
+
+ n = getprop(devp, prop, &v, sizeof(v));
+ if (n != sizeof(v))
+ goto err_out;
+
+ devp = find_node_by_linuxphandle((u32)v);
+ if (devp == NULL)
+ goto err_out;
+
+ n = getprop(devp, "virtual-reg", &v, sizeof(v));
+ if (n == sizeof(v))
+ return v;
+
+err_out:
+ return NULL;
+}
+
+int mpsc_console_init(void *devp, struct serial_console_data *scdp)
+{
+ void *v;
+ int n, reg_set;
+ volatile char *sdma_base;
+
+ n = getprop(devp, "virtual-reg", &v, sizeof(v));
+ if (n != sizeof(v))
+ goto err_out;
+ mpsc_base = v;
+
+ sdma_base = mpsc_get_virtreg_of_phandle(devp, "sdma");
+ if (sdma_base == NULL)
+ goto err_out;
+
+ mpscintr_base = mpsc_get_virtreg_of_phandle(devp, "mpscintr");
+ if (mpscintr_base == NULL)
+ goto err_out;
+
+ n = getprop(devp, "block-index", &v, sizeof(v));
+ if (n != sizeof(v))
+ goto err_out;
+ reg_set = (int)v;
+
+ mpscintr_base += (reg_set == 0) ? 0x4 : 0xc;
+
+ /* Make sure the mpsc ctlrs are shutdown */
+ out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0);
+ out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0);
+ out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0);
+ out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0);
+
+ mpsc_stop_dma(sdma_base);
+
+ scdp->open = mpsc_open;
+ scdp->putc = mpsc_putc;
+ scdp->getc = mpsc_getc;
+ scdp->tstc = mpsc_tstc;
+ scdp->close = NULL;
+
+ return 0;
+
+err_out:
+ return -1;
+}
Index: powerpc/arch/powerpc/boot/serial.c
===================================================================
--- powerpc.orig/arch/powerpc/boot/serial.c
+++ powerpc/arch/powerpc/boot/serial.c
@@ -125,6 +125,8 @@ int serial_console_init(void)
if (!strcmp(compat, "ns16550"))
rc = ns16550_console_init(devp, &serial_cd);
+ else if (!strcmp(compat, "mpsc"))
+ rc = mpsc_console_init(devp, &serial_cd);
/* Add other serial console driver calls here */
Index: powerpc/arch/powerpc/boot/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/boot/Makefile
+++ powerpc/arch/powerpc/boot/Makefile
@@ -43,7 +43,7 @@ $(addprefix $(obj)/,$(zlib) gunzip_util.
src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
ns16550.c serial.c simple_alloc.c div64.S util.S \
gunzip_util.c elf_util.c $(zlib) devtree.c \
- 44x.c ebony.c mv64x60.c
+ 44x.c ebony.c mv64x60.c mpsc.c
src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \
cuboot-ebony.c treeboot-ebony.c
src-boot := $(src-wlib) $(src-plat) empty.c
Index: powerpc/arch/powerpc/boot/ops.h
===================================================================
--- powerpc.orig/arch/powerpc/boot/ops.h
+++ powerpc/arch/powerpc/boot/ops.h
@@ -79,6 +79,7 @@ void start(void);
int ft_init(void *dt_blob, unsigned int max_size, unsigned int max_find_device);
int serial_console_init(void);
int ns16550_console_init(void *devp, struct serial_console_data *scdp);
+int mpsc_console_init(void *devp, struct serial_console_data *scdp);
void *simple_alloc_init(char *base, unsigned long heap_size,
unsigned long granularity, unsigned long max_allocs);
extern void flush_cache(void *, unsigned long);
^ permalink raw reply
* [PATCH 4/13] powerpc: Add bootwrapper support for Marvell/mv64x60 I2C
From: Mark A. Greer @ 2007-05-10 20:06 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
Some platforms support a variety processor modules with no method of
determining which exact processor module is being used except by
examining Vital Product Data (VPD). The modules may have different
amounts of memory, clock frequencies, etc. so reading the VPD becomes
necessary to correctly set properties in the device tree before its
passed to the kernel.
Often the VPD is stored in I2C EEPROMs so an I2C driver becomes necessary.
This I2C driver is for the I2C controller that's embedded on the Marvel
mv64x60 line of host bridges.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
arch/powerpc/boot/Makefile | 2
arch/powerpc/boot/mv64x60_i2c.c | 206 ++++++++++++++++++++++++++++++
2 files changed, 207 insertions(+), 1 deletion(-)
Index: powerpc/arch/powerpc/boot/mv64x60_i2c.c
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/mv64x60_i2c.c
@@ -0,0 +1,206 @@
+/*
+ * Bootloader version of the i2c driver for the MV64x60.
+ *
+ * Author: Dale Farnsworth <dfarnsworth@mvista.com>
+ * Maintained by: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2003, 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express or
+ * implied.
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "page.h"
+#include "string.h"
+#include "stdio.h"
+#include "io.h"
+#include "ops.h"
+#include "mv64x60.h"
+
+extern void udelay(long);
+
+/* Register defines */
+#define MV64x60_I2C_REG_SLAVE_ADDR 0x00
+#define MV64x60_I2C_REG_DATA 0x04
+#define MV64x60_I2C_REG_CONTROL 0x08
+#define MV64x60_I2C_REG_STATUS 0x0c
+#define MV64x60_I2C_REG_BAUD 0x0c
+#define MV64x60_I2C_REG_EXT_SLAVE_ADDR 0x10
+#define MV64x60_I2C_REG_SOFT_RESET 0x1c
+
+#define MV64x60_I2C_CONTROL_ACK 0x04
+#define MV64x60_I2C_CONTROL_IFLG 0x08
+#define MV64x60_I2C_CONTROL_STOP 0x10
+#define MV64x60_I2C_CONTROL_START 0x20
+#define MV64x60_I2C_CONTROL_TWSIEN 0x40
+#define MV64x60_I2C_CONTROL_INTEN 0x80
+
+#define MV64x60_I2C_STATUS_BUS_ERR 0x00
+#define MV64x60_I2C_STATUS_MAST_START 0x08
+#define MV64x60_I2C_STATUS_MAST_REPEAT_START 0x10
+#define MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
+#define MV64x60_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
+#define MV64x60_I2C_STATUS_MAST_WR_ACK 0x28
+#define MV64x60_I2C_STATUS_MAST_WR_NO_ACK 0x30
+#define MV64x60_I2C_STATUS_MAST_LOST_ARB 0x38
+#define MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
+#define MV64x60_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
+#define MV64x60_I2C_STATUS_MAST_RD_DATA_ACK 0x50
+#define MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
+#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
+#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
+#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
+#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
+#define MV64x60_I2C_STATUS_NO_STATUS 0xf8
+
+static u8 *ctlr_base;
+
+static int mv64x60_i2c_wait_for_status(int wanted)
+{
+ int i;
+ int status;
+
+ for (i=0; i<1000; i++) {
+ udelay(10);
+ status = in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_STATUS))
+ & 0xff;
+ if (status == wanted)
+ return status;
+ }
+ return -status;
+}
+
+static int mv64x60_i2c_control(int control, int status)
+{
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
+ return mv64x60_i2c_wait_for_status(status);
+}
+
+static int mv64x60_i2c_read_byte(int control, int status)
+{
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
+ if (mv64x60_i2c_wait_for_status(status) < 0)
+ return -1;
+ return in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA)) & 0xff;
+}
+
+static int mv64x60_i2c_write_byte(int data, int control, int status)
+{
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA), data & 0xff);
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
+ return mv64x60_i2c_wait_for_status(status);
+}
+
+int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size,
+ u32 count)
+{
+ int i;
+ int data;
+ int control;
+ int status;
+
+ if (ctlr_base == NULL)
+ return -1;
+
+ /* send reset */
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SOFT_RESET), 0);
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SLAVE_ADDR), 0);
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_EXT_SLAVE_ADDR), 0);
+ out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_BAUD), (4 << 3) | 0x4);
+
+ if (mv64x60_i2c_control(MV64x60_I2C_CONTROL_TWSIEN,
+ MV64x60_I2C_STATUS_NO_STATUS) < 0)
+ return -1;
+
+ /* send start */
+ control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_START;
+ if (mv64x60_i2c_control(control, status) < 0)
+ return -1;
+
+ /* select device for writing */
+ data = devaddr & ~0x1;
+ control = MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK;
+ if (mv64x60_i2c_write_byte(data, control, status) < 0)
+ return -1;
+
+ /* send offset of data */
+ control = MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_WR_ACK;
+ if (offset_size > 1) {
+ if (mv64x60_i2c_write_byte(offset >> 8, control, status) < 0)
+ return -1;
+ }
+ if (mv64x60_i2c_write_byte(offset, control, status) < 0)
+ return -1;
+
+ /* resend start */
+ control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_REPEAT_START;
+ if (mv64x60_i2c_control(control, status) < 0)
+ return -1;
+
+ /* select device for reading */
+ data = devaddr | 0x1;
+ control = MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK;
+ if (mv64x60_i2c_write_byte(data, control, status) < 0)
+ return -1;
+
+ /* read all but last byte of data */
+ control = MV64x60_I2C_CONTROL_ACK | MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_RD_DATA_ACK;
+
+ for (i=1; i<count; i++) {
+ data = mv64x60_i2c_read_byte(control, status);
+ if (data < 0) {
+ printf("errors on iteration %d\n", i);
+ return -1;
+ }
+ *buf++ = data;
+ }
+
+ /* read last byte of data */
+ control = MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK;
+ data = mv64x60_i2c_read_byte(control, status);
+ if (data < 0)
+ return -1;
+ *buf++ = data;
+
+ /* send stop */
+ control = MV64x60_I2C_CONTROL_STOP | MV64x60_I2C_CONTROL_TWSIEN;
+ status = MV64x60_I2C_STATUS_NO_STATUS;
+ if (mv64x60_i2c_control(control, status) < 0)
+ return -1;
+
+ return count;
+}
+
+int mv64x60_i2c_open(void)
+{
+ u32 v;
+ void *devp;
+
+ devp = finddevice("/mv64x60/i2c");
+ if (devp == NULL)
+ goto err_out;
+ if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
+ goto err_out;
+
+ ctlr_base = (u8 *)v;
+ return 0;
+
+err_out:
+ return -1;
+}
+
+void mv64x60_i2c_close(void)
+{
+ ctlr_base = NULL;
+}
Index: powerpc/arch/powerpc/boot/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/boot/Makefile
+++ powerpc/arch/powerpc/boot/Makefile
@@ -43,7 +43,7 @@ $(addprefix $(obj)/,$(zlib) gunzip_util.
src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
ns16550.c serial.c simple_alloc.c div64.S util.S \
gunzip_util.c elf_util.c $(zlib) devtree.c \
- 44x.c ebony.c mv64x60.c mpsc.c
+ 44x.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c
src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \
cuboot-ebony.c treeboot-ebony.c
src-boot := $(src-wlib) $(src-plat) empty.c
^ permalink raw reply
* [PATCH 5/13] powerpc: Add interrupt support for Marvell mv64x60 chips
From: Mark A. Greer @ 2007-05-10 20:06 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
There are 3 interrupt groups each with its own status/mask registers.
We use a separate struct irq_chip for each interrupt group and handle
interrupts in two stages or levels: level 1 selects the appropriate
struct irq_chip, and level 2 selects individual interrupts within
that irq_chip.
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
---
arch/powerpc/sysdev/Makefile | 1
arch/powerpc/sysdev/mv64x60.h | 9
arch/powerpc/sysdev/mv64x60_pic.c | 305 ++++++++++++++++++++++++++++
3 files changed, 315 insertions(+)
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60_pic.c
===================================================================
--- /dev/null
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60_pic.c
@@ -0,0 +1,305 @@
+/*
+ * Interrupt handling for Marvell mv64360/mv64460 host bridges (Discovery)
+ *
+ * Author: Dale Farnsworth <dale@farnsworth.org>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/irq.h>
+
+#include "mv64x60.h"
+
+/* Interrupt Controller Interface Registers */
+#define MV64X60_IC_MAIN_CAUSE_LO 0x0004
+#define MV64X60_IC_MAIN_CAUSE_HI 0x000c
+#define MV64X60_IC_CPU0_INTR_MASK_LO 0x0014
+#define MV64X60_IC_CPU0_INTR_MASK_HI 0x001c
+#define MV64X60_IC_CPU0_SELECT_CAUSE 0x0024
+
+#define MV64X60_HIGH_GPP_GROUPS 0x0f000000
+#define MV64X60_SELECT_CAUSE_HIGH 0x40000000
+
+/* General Purpose Pins Controller Interface Registers */
+#define MV64x60_GPP_INTR_CAUSE 0x0008
+#define MV64x60_GPP_INTR_MASK 0x000c
+
+#define MV64x60_LEVEL1_LOW 0
+#define MV64x60_LEVEL1_HIGH 1
+#define MV64x60_LEVEL1_GPP 2
+
+#define MV64x60_LEVEL1_MASK 0x00000060
+#define MV64x60_LEVEL1_OFFSET 5
+
+#define MV64x60_LEVEL2_MASK 0x0000001f
+
+#define MV64x60_NUM_IRQS 96
+
+static DEFINE_SPINLOCK(mv64x60_lock);
+
+static void __iomem *mv64x60_irq_reg_base;
+static void __iomem *mv64x60_gpp_reg_base;
+
+/*
+ * Interrupt Controller Handling
+ *
+ * The interrupt controller handles three groups of interrupts:
+ * main low: IRQ0-IRQ31
+ * main high: IRQ32-IRQ63
+ * gpp: IRQ64-IRQ95
+ *
+ * This code handles interrupts in two levels. Level 1 selects the
+ * interrupt group, and level 2 selects an IRQ within that group.
+ * Each group has its own irq_chip structure.
+ */
+
+static u32 mv64x60_cached_low_mask;
+static u32 mv64x60_cached_high_mask = MV64X60_HIGH_GPP_GROUPS;
+static u32 mv64x60_cached_gpp_mask;
+
+static struct irq_host *mv64x60_irq_host;
+
+/*
+ * mv64x60_chip_low functions
+ */
+
+static void mv64x60_mask_low(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_low_mask &= ~(1 << level2);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
+ mv64x60_cached_low_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
+}
+
+static void mv64x60_unmask_low(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_low_mask |= 1 << level2;
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
+ mv64x60_cached_low_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
+}
+
+static struct irq_chip mv64x60_chip_low = {
+ .name = "mv64x60_low",
+ .mask = mv64x60_mask_low,
+ .mask_ack = mv64x60_mask_low,
+ .unmask = mv64x60_unmask_low,
+};
+
+/*
+ * mv64x60_chip_high functions
+ */
+
+static void mv64x60_mask_high(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_high_mask &= ~(1 << level2);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
+ mv64x60_cached_high_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
+}
+
+static void mv64x60_unmask_high(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_high_mask |= 1 << level2;
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
+ mv64x60_cached_high_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
+}
+
+static struct irq_chip mv64x60_chip_high = {
+ .name = "mv64x60_high",
+ .mask = mv64x60_mask_high,
+ .mask_ack = mv64x60_mask_high,
+ .unmask = mv64x60_unmask_high,
+};
+
+/*
+ * mv64x60_chip_gpp functions
+ */
+
+static void mv64x60_mask_gpp(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_gpp_mask &= ~(1 << level2);
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
+ mv64x60_cached_gpp_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
+}
+
+static void mv64x60_mask_ack_gpp(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_gpp_mask &= ~(1 << level2);
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
+ mv64x60_cached_gpp_mask);
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE,
+ ~(1 << level2));
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE);
+}
+
+static void mv64x60_unmask_gpp(unsigned int virq)
+{
+ int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ mv64x60_cached_gpp_mask |= 1 << level2;
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
+ mv64x60_cached_gpp_mask);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+ (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
+}
+
+static struct irq_chip mv64x60_chip_gpp = {
+ .name = "mv64x60_gpp",
+ .mask = mv64x60_mask_gpp,
+ .mask_ack = mv64x60_mask_ack_gpp,
+ .unmask = mv64x60_unmask_gpp,
+};
+
+/*
+ * mv64x60_host_ops functions
+ */
+
+static int mv64x60_host_match(struct irq_host *h, struct device_node *np)
+{
+ return mv64x60_irq_host->host_data == np;
+}
+
+static struct irq_chip *mv64x60_chips[] = {
+ [MV64x60_LEVEL1_LOW] = &mv64x60_chip_low,
+ [MV64x60_LEVEL1_HIGH] = &mv64x60_chip_high,
+ [MV64x60_LEVEL1_GPP] = &mv64x60_chip_gpp,
+};
+
+static int mv64x60_host_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t hwirq)
+{
+ int level1;
+
+ get_irq_desc(virq)->status |= IRQ_LEVEL;
+
+ level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
+ BUG_ON(level1 > MV64x60_LEVEL1_GPP);
+ set_irq_chip_and_handler(virq, mv64x60_chips[level1], handle_level_irq);
+
+ return 0;
+}
+
+static struct irq_host_ops mv64x60_host_ops = {
+ .match = mv64x60_host_match,
+ .map = mv64x60_host_map,
+};
+
+/*
+ * Global functions
+ */
+
+void __init mv64x60_init_irq(void)
+{
+ struct device_node *np;
+ phys_addr_t paddr;
+ unsigned int size;
+ const unsigned int *reg;
+ unsigned long flags;
+
+ np = of_find_compatible_node(NULL, NULL, "mv64x60-gpp");
+ reg = of_get_property(np, "reg", &size);
+ paddr = of_translate_address(np, reg);
+ mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
+ of_node_put(np);
+
+ np = of_find_compatible_node(NULL, NULL, "mv64x60-pic");
+ reg = of_get_property(np, "reg", &size);
+ paddr = of_translate_address(np, reg);
+ of_node_put(np);
+ mv64x60_irq_reg_base = ioremap(paddr, reg[1]);
+
+ mv64x60_irq_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, MV64x60_NUM_IRQS,
+ &mv64x60_host_ops, MV64x60_NUM_IRQS);
+
+ mv64x60_irq_host->host_data = np;
+
+ spin_lock_irqsave(&mv64x60_lock, flags);
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
+ mv64x60_cached_gpp_mask);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
+ mv64x60_cached_low_mask);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
+ mv64x60_cached_high_mask);
+
+ out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE, 0);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_LO, 0);
+ out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_HI, 0);
+ spin_unlock_irqrestore(&mv64x60_lock, flags);
+}
+
+unsigned int mv64x60_get_irq(void)
+{
+ u32 cause;
+ int level1;
+ irq_hw_number_t hwirq;
+ int virq = NO_IRQ;
+
+ cause = in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_SELECT_CAUSE);
+ if (cause & MV64X60_SELECT_CAUSE_HIGH) {
+ cause &= mv64x60_cached_high_mask;
+ level1 = MV64x60_LEVEL1_HIGH;
+ if (cause & MV64X60_HIGH_GPP_GROUPS) {
+ cause = in_le32(mv64x60_gpp_reg_base +
+ MV64x60_GPP_INTR_CAUSE);
+ cause &= mv64x60_cached_gpp_mask;
+ level1 = MV64x60_LEVEL1_GPP;
+ }
+ } else {
+ cause &= mv64x60_cached_low_mask;
+ level1 = MV64x60_LEVEL1_LOW;
+ }
+ if (cause) {
+ hwirq = (level1 << MV64x60_LEVEL1_OFFSET) | __ilog2(cause);
+ virq = irq_linear_revmap(mv64x60_irq_host, hwirq);
+ }
+
+ return virq;
+}
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.h
===================================================================
--- /dev/null
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.h
@@ -0,0 +1,9 @@
+#ifndef __MV64X60_H__
+#define __MV64X60_H__
+
+#include <linux/init.h>
+
+extern void __init mv64x60_init_irq(void);
+extern unsigned int mv64x60_get_irq(void);
+
+#endif /* __MV64X60_H__ */
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/Makefile
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/Makefile
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_FSL_PCIE) += fsl_pcie.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_MV64X60) += mv64x60_pic.o
# contains only the suspend handler for time
obj-$(CONFIG_PM) += timer.o
^ permalink raw reply
* [PATCH 6/13] powerpc: Create Marvell mv64x60 MPSC (serial) platform_data
From: Mark A. Greer @ 2007-05-10 20:07 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
This patch creates platform_device entries for the Marvell mv64x60
MPSC (multi-protocol serial controller) ports, based on information
contained in the device tree.
This driver (like the other mv64x60 drivers) are unusual in that it
works on both the MIPS and PowerPC architectures. Because of that,
the drivers do not support the normal PowerPC of_platform_bus_type.
They support platform_bus_type instead.
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
arch/powerpc/platforms/embedded6xx/Kconfig | 3
arch/powerpc/sysdev/Makefile | 2
arch/powerpc/sysdev/mv64x60_dev.c | 221 +++++++++++++++++++
3 files changed, 225 insertions(+), 1 deletion(-)
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60_dev.c
===================================================================
--- /dev/null
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60_dev.c
@@ -0,0 +1,221 @@
+/*
+ * Platform device setup for Marvell mv64360/mv64460 host bridges (Discovery)
+ *
+ * Author: Dale Farnsworth <dale@farnsworth.org>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx.h>
+#include <linux/platform_device.h>
+
+#include <asm/prom.h>
+
+/*
+ * These functions provide the necessary setup for the mv64x60 drivers.
+ * These drivers are unusual in that they work on both the MIPS and PowerPC
+ * architectures. Because of that, the drivers do not support the normal
+ * PowerPC of_platform_bus_type. They support platform_bus_type instead.
+ */
+
+/*
+ * Create MPSC platform devices
+ */
+static int __init mv64x60_mpsc_register_shared_pdev(struct device_node *np)
+{
+ struct platform_device *pdev;
+ struct resource r[2];
+ struct mpsc_shared_pdata pdata;
+ const phandle *ph;
+ struct device_node *mpscrouting, *mpscintr;
+ int err;
+
+ ph = of_get_property(np, "mpscrouting", NULL);
+ mpscrouting = of_find_node_by_phandle(*ph);
+ if (!mpscrouting)
+ return -ENODEV;
+
+ err = of_address_to_resource(mpscrouting, 0, &r[0]);
+ of_node_put(mpscrouting);
+ if (err)
+ return err;
+
+ ph = of_get_property(np, "mpscintr", NULL);
+ mpscintr = of_find_node_by_phandle(*ph);
+ if (!mpscintr)
+ return -ENODEV;
+
+ err = of_address_to_resource(mpscintr, 0, &r[1]);
+ of_node_put(mpscintr);
+ if (err)
+ return err;
+
+ memset(&pdata, 0, sizeof(pdata));
+
+ pdev = platform_device_alloc(MPSC_SHARED_NAME, 0);
+ if (!pdev)
+ return -ENOMEM;
+
+ err = platform_device_add_resources(pdev, r, 2);
+ if (err)
+ goto error;
+
+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+ if (err)
+ goto error;
+
+ err = platform_device_add(pdev);
+ if (err)
+ goto error;
+
+ return 0;
+
+error:
+ platform_device_put(pdev);
+ return err;
+}
+
+
+static int __init mv64x60_mpsc_device_setup(struct device_node *np, int id)
+{
+ struct resource r[5];
+ struct mpsc_pdata pdata;
+ struct platform_device *pdev;
+ const unsigned int *prop;
+ const phandle *ph;
+ struct device_node *sdma, *brg;
+ int err;
+ int port_number;
+
+ /* only register the shared platform device the first time through */
+ if (id == 0 && (err = mv64x60_mpsc_register_shared_pdev(np)))
+ return err;
+
+ memset(r, 0, sizeof(r));
+
+ err = of_address_to_resource(np, 0, &r[0]);
+ if (err)
+ return err;
+
+ of_irq_to_resource(np, 0, &r[4]);
+
+ ph = of_get_property(np, "sdma", NULL);
+ sdma = of_find_node_by_phandle(*ph);
+ if (!sdma)
+ return -ENODEV;
+
+ of_irq_to_resource(sdma, 0, &r[3]);
+ err = of_address_to_resource(sdma, 0, &r[1]);
+ of_node_put(sdma);
+ if (err)
+ return err;
+
+ ph = of_get_property(np, "brg", NULL);
+ brg = of_find_node_by_phandle(*ph);
+ if (!brg)
+ return -ENODEV;
+
+ err = of_address_to_resource(brg, 0, &r[2]);
+ of_node_put(brg);
+ if (err)
+ return err;
+
+ prop = of_get_property(np, "block-index", NULL);
+ if (!prop)
+ return -ENODEV;
+ port_number = *(int *)prop;
+
+ memset(&pdata, 0, sizeof(pdata));
+
+ pdata.cache_mgmt = 1; /* All current revs need this set */
+
+ prop = of_get_property(np, "max_idle", NULL);
+ if (prop)
+ pdata.max_idle = *prop;
+
+ prop = of_get_property(brg, "current-speed", NULL);
+ if (prop)
+ pdata.default_baud = *prop;
+
+ /* Default is 8 bits, no parity, no flow control */
+ pdata.default_bits = 8;
+ pdata.default_parity = 'n';
+ pdata.default_flow = 'n';
+
+ prop = of_get_property(np, "chr_1", NULL);
+ if (prop)
+ pdata.chr_1_val = *prop;
+
+ prop = of_get_property(np, "chr_2", NULL);
+ if (prop)
+ pdata.chr_2_val = *prop;
+
+ prop = of_get_property(np, "chr_10", NULL);
+ if (prop)
+ pdata.chr_10_val = *prop;
+
+ prop = of_get_property(np, "mpcr", NULL);
+ if (prop)
+ pdata.mpcr_val = *prop;
+
+ prop = of_get_property(brg, "bcr", NULL);
+ if (prop)
+ pdata.bcr_val = *prop;
+
+ pdata.brg_can_tune = 1; /* All current revs need this set */
+
+ prop = of_get_property(brg, "clock-src", NULL);
+ if (prop)
+ pdata.brg_clk_src = *prop;
+
+ prop = of_get_property(brg, "clock-frequency", NULL);
+ if (prop)
+ pdata.brg_clk_freq = *prop;
+
+ pdev = platform_device_alloc(MPSC_CTLR_NAME, port_number);
+ if (!pdev)
+ return -ENOMEM;
+
+ err = platform_device_add_resources(pdev, r, 5);
+ if (err)
+ goto error;
+
+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+ if (err)
+ goto error;
+
+ err = platform_device_add(pdev);
+ if (err)
+ goto error;
+
+ return 0;
+
+error:
+ platform_device_put(pdev);
+ return err;
+}
+
+static int __init mv64x60_device_setup(void)
+{
+ struct device_node *np = NULL;
+ int id;
+ int err;
+
+ for (id = 0;
+ (np = of_find_compatible_node(np, "serial", "mpsc")); id++)
+ if ((err = mv64x60_mpsc_device_setup(np, id)))
+ goto error;
+
+ return 0;
+
+error:
+ of_node_put(np);
+ return err;
+}
+arch_initcall(mv64x60_device_setup);
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/Makefile
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/Makefile
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_FSL_PCIE) += fsl_pcie.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
-obj-$(CONFIG_MV64X60) += mv64x60_pic.o
+obj-$(CONFIG_MV64X60) += mv64x60_pic.o mv64x60_dev.o
# contains only the suspend handler for time
obj-$(CONFIG_PM) += timer.o
Index: linux-2.6-powerpc-df/arch/powerpc/platforms/embedded6xx/Kconfig
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/platforms/embedded6xx/Kconfig
+++ linux-2.6-powerpc-df/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -38,6 +38,9 @@ config MPC10X_BRIDGE
select PPC_INDIRECT_PCI
default y
+config MV64X60
+ bool
+
config MPC10X_OPENPIC
bool
depends on LINKSTATION
^ permalink raw reply
* [PATCH 7/13] powerpc: Create Marvell mv64x60 ethernet platform_data
From: Mark A. Greer @ 2007-05-10 20:07 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
This patch creates platform_device entries for the Marvell mv64x60
ethernet controller ports, based on information contained in the
device tree.
This driver (like the other mv64x60 drivers) are unusual in that it
works on both the MIPS and PowerPC architectures. Because of that,
the drivers do not support the normal PowerPC of_platform_bus_type.
They support platform_bus_type instead.
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
arch/powerpc/sysdev/mv64x60_dev.c | 127 ++++++++++++++++++++++++++++
drivers/net/Kconfig | 2
2 files changed, 128 insertions(+), 1 deletion(-)
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60_dev.c
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/mv64x60_dev.c
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60_dev.c
@@ -201,6 +201,128 @@ error:
return err;
}
+/*
+ * Create mv64x60_eth platform devices
+ */
+static int __init eth_register_shared_pdev(struct device_node *np)
+{
+ struct platform_device *pdev;
+ struct resource r[1];
+ int err;
+
+ np = of_get_parent(np);
+ if (!np)
+ return -ENODEV;
+
+ err = of_address_to_resource(np, 0, &r[0]);
+ of_node_put(np);
+ if (err)
+ return err;
+
+ pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, 0,
+ r, 1);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ return 0;
+}
+
+static int __init mv64x60_eth_device_setup(struct device_node *np, int id)
+{
+ struct resource r[1];
+ struct mv643xx_eth_platform_data pdata;
+ struct platform_device *pdev;
+ struct device_node *phy;
+ const u8 *mac_addr;
+ const int *prop;
+ const phandle *ph;
+ int err;
+
+ /* only register the shared platform device the first time through */
+ if (id == 0 && (err = eth_register_shared_pdev(np)))
+ return err;;
+
+ memset(r, 0, sizeof(r));
+ of_irq_to_resource(np, 0, &r[0]);
+
+ memset(&pdata, 0, sizeof(pdata));
+
+ prop = of_get_property(np, "block-index", NULL);
+ if (!prop)
+ return -ENODEV;
+ pdata.port_number = *prop;
+
+ mac_addr = of_get_mac_address(np);
+ if (mac_addr)
+ memcpy(pdata.mac_addr, mac_addr, 6);
+
+ prop = of_get_property(np, "speed", NULL);
+ if (prop)
+ pdata.speed = *prop;
+
+ prop = of_get_property(np, "tx_queue_size", NULL);
+ if (prop)
+ pdata.tx_queue_size = *prop;
+
+ prop = of_get_property(np, "rx_queue_size", NULL);
+ if (prop)
+ pdata.rx_queue_size = *prop;
+
+ prop = of_get_property(np, "tx_sram_addr", NULL);
+ if (prop)
+ pdata.tx_sram_addr = *prop;
+
+ prop = of_get_property(np, "tx_sram_size", NULL);
+ if (prop)
+ pdata.tx_sram_size = *prop;
+
+ prop = of_get_property(np, "rx_sram_addr", NULL);
+ if (prop)
+ pdata.rx_sram_addr = *prop;
+
+ prop = of_get_property(np, "rx_sram_size", NULL);
+ if (prop)
+ pdata.rx_sram_size = *prop;
+
+ ph = of_get_property(np, "phy", NULL);
+ if (!ph)
+ return -ENODEV;
+
+ phy = of_find_node_by_phandle(*ph);
+ if (phy == NULL)
+ return -ENODEV;
+
+ prop = of_get_property(phy, "reg", NULL);
+ if (prop) {
+ pdata.force_phy_addr = 1;
+ pdata.phy_addr = *prop;
+ }
+
+ of_node_put(phy);
+
+ pdev = platform_device_alloc(MV643XX_ETH_NAME, pdata.port_number);
+ if (!pdev)
+ return -ENOMEM;
+
+ err = platform_device_add_resources(pdev, r, 1);
+ if (err)
+ goto error;
+
+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+ if (err)
+ goto error;
+
+ err = platform_device_add(pdev);
+ if (err)
+ goto error;
+
+ return 0;
+
+error:
+ platform_device_put(pdev);
+ return err;
+}
+
static int __init mv64x60_device_setup(void)
{
struct device_node *np = NULL;
@@ -212,6 +334,11 @@ static int __init mv64x60_device_setup(v
if ((err = mv64x60_mpsc_device_setup(np, id)))
goto error;
+ for (id = 0;
+ (np = of_find_compatible_node(np, "network", "mv64x60-eth")); id++)
+ if ((err = mv64x60_eth_device_setup(np, id)))
+ goto error;
+
return 0;
error:
Index: linux-2.6-powerpc-df/drivers/net/Kconfig
===================================================================
--- linux-2.6-powerpc-df.orig/drivers/net/Kconfig
+++ linux-2.6-powerpc-df/drivers/net/Kconfig
@@ -2299,7 +2299,7 @@ config UGETH_TX_ON_DEMAND
config MV643XX_ETH
tristate "MV-643XX Ethernet support"
- depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32)
+ depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MV64X60 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32)
select MII
help
This driver supports the gigabit Ethernet on the Marvell MV643XX
^ permalink raw reply
* [PATCH 8/13] powerpc: Create Marvell mv64x60 I2C platform_data
From: Mark A. Greer @ 2007-05-10 20:07 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
This patch creates platform_device entries for the Marvell mv64x60
I2C ports, based on information contained in device tree.
This driver (like the other mv64x60 drivers) are unusual in that it
works on both the MIPS and PowerPC architectures. Because of that,
the drivers do not support the normal PowerPC of_platform_bus_type.
They support platform_bus_type instead.
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
arch/powerpc/sysdev/mv64x60_dev.c | 74 +++++++++++++++++++++++++++-
1 file changed, 72 insertions(+), 2 deletions(-)
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60_dev.c
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/mv64x60_dev.c
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60_dev.c
@@ -323,14 +323,79 @@ error:
return err;
}
+/*
+ * Create mv64x60_i2c platform devices
+ */
+static int __init mv64x60_i2c_device_setup(struct device_node *np, int id)
+{
+ struct resource r[2];
+ struct platform_device *pdev;
+ struct mv64xxx_i2c_pdata pdata;
+ const unsigned int *prop;
+ int err;
+
+ memset(r, 0, sizeof(r));
+
+ err = of_address_to_resource(np, 0, &r[0]);
+ if (err)
+ return err;
+
+ of_irq_to_resource(np, 0, &r[1]);
+
+ memset(&pdata, 0, sizeof(pdata));
+
+ prop = of_get_property(np, "freq_m", NULL);
+ if (!prop)
+ return -ENODEV;
+ pdata.freq_m = *prop;
+
+ prop = of_get_property(np, "freq_n", NULL);
+ if (!prop)
+ return -ENODEV;
+ pdata.freq_n = *prop;
+
+ prop = of_get_property(np, "timeout", NULL);
+ if (prop)
+ pdata.timeout = *prop;
+ else
+ pdata.timeout = 1000; /* 1 second */
+
+ prop = of_get_property(np, "retries", NULL);
+ if (prop)
+ pdata.retries = *prop;
+ else
+ pdata.retries = 1;
+
+ pdev = platform_device_alloc(MV64XXX_I2C_CTLR_NAME, id);
+ if (!pdev)
+ return -ENOMEM;
+
+ err = platform_device_add_resources(pdev, r, 2);
+ if (err)
+ goto error;
+
+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+ if (err)
+ goto error;
+
+ err = platform_device_add(pdev);
+ if (err)
+ goto error;
+
+ return 0;
+
+error:
+ platform_device_put(pdev);
+ return err;
+}
+
static int __init mv64x60_device_setup(void)
{
struct device_node *np = NULL;
int id;
int err;
- for (id = 0;
- (np = of_find_compatible_node(np, "serial", "mpsc")); id++)
+ for (id = 0; (np = of_find_compatible_node(np, "serial", "mpsc")); id++)
if ((err = mv64x60_mpsc_device_setup(np, id)))
goto error;
@@ -339,6 +404,11 @@ static int __init mv64x60_device_setup(v
if ((err = mv64x60_eth_device_setup(np, id)))
goto error;
+ for (id = 0;
+ (np = of_find_compatible_node(np, "i2c", "mv64x60-i2c")); id++)
+ if ((err = mv64x60_i2c_device_setup(np, id)))
+ goto error;
+
return 0;
error:
^ permalink raw reply
* [PATCH 9/13] powerpc: Add Marvell mv64x60 PCI bridge support
From: Mark A. Greer @ 2007-05-10 20:08 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
This patch adds PCI bridge support for the Marvell mv64x60 chip.
We also provide the ability to read/write the mv64x60 hotswap
register via sysfs if the hs_reg_valid property is set in the
device tree.
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
arch/powerpc/platforms/embedded6xx/Kconfig | 1
arch/powerpc/sysdev/Makefile | 3
arch/powerpc/sysdev/mv64x60.h | 2
arch/powerpc/sysdev/mv64x60_pci.c | 172 +++++++++++++++++++
4 files changed, 177 insertions(+), 1 deletion(-)
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/Makefile
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/Makefile
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/Makefile
@@ -14,7 +14,8 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_FSL_PCIE) += fsl_pcie.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
-obj-$(CONFIG_MV64X60) += mv64x60_pic.o mv64x60_dev.o
+mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
+obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o
# contains only the suspend handler for time
obj-$(CONFIG_PM) += timer.o
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.h
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/sysdev/mv64x60.h
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60.h
@@ -6,4 +6,6 @@
extern void __init mv64x60_init_irq(void);
extern unsigned int mv64x60_get_irq(void);
+extern void __init mv64x60_pci_init(void);
+
#endif /* __MV64X60_H__ */
Index: linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60_pci.c
===================================================================
--- /dev/null
+++ linux-2.6-powerpc-df/arch/powerpc/sysdev/mv64x60_pci.c
@@ -0,0 +1,172 @@
+/*
+ * PCI bus setup for Marvell mv64360/mv64460 host bridges (Discovery)
+ *
+ * Author: Dale Farnsworth <dale@farnsworth.org>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+
+#define PCI_HEADER_TYPE_INVALID 0x7f /* Invalid PCI header type */
+
+#ifdef CONFIG_SYSFS
+/* 32-bit hex or dec stringified number + '\n' */
+#define MV64X60_VAL_LEN_MAX 11
+#define MV64X60_PCICFG_CPCI_HOTSWAP 0x68
+
+static ssize_t mv64x60_hs_reg_read(struct kobject *kobj, char *buf, loff_t off,
+ size_t count)
+{
+ struct pci_dev *phb;
+ u32 v;
+
+ if (off > 0)
+ return 0;
+ if (count < MV64X60_VAL_LEN_MAX)
+ return -EINVAL;
+
+ phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
+ if (!phb)
+ return -ENODEV;
+ pci_read_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, &v);
+ pci_dev_put(phb);
+
+ return sprintf(buf, "0x%08x\n", v);
+}
+
+static ssize_t mv64x60_hs_reg_write(struct kobject *kobj, char *buf, loff_t off,
+ size_t count)
+{
+ struct pci_dev *phb;
+ u32 v;
+
+ if (off > 0)
+ return 0;
+ if (count <= 0)
+ return -EINVAL;
+
+ if (sscanf(buf, "%i", &v) != 1)
+ return -EINVAL;
+
+ phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
+ if (!phb)
+ return -ENODEV;
+ pci_write_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, v);
+ pci_dev_put(phb);
+
+ return count;
+}
+
+static struct bin_attribute mv64x60_hs_reg_attr = { /* Hotswap register */
+ .attr = {
+ .name = "hs_reg",
+ .mode = S_IRUGO | S_IWUSR,
+ .owner = THIS_MODULE,
+ },
+ .size = MV64X60_VAL_LEN_MAX,
+ .read = mv64x60_hs_reg_read,
+ .write = mv64x60_hs_reg_write,
+};
+
+static int __init mv64x60_sysfs_init(void)
+{
+ struct device_node *np;
+ struct platform_device *pdev;
+ const unsigned int *prop;
+
+ np = of_find_compatible_node(NULL, NULL, "mv64x60");
+ if (!np)
+ return 0;
+
+ prop = of_get_property(np, "hs_reg_valid", NULL);
+ of_node_put(np);
+
+ pdev = platform_device_register_simple("mv64x60", 0, NULL, 0);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ return sysfs_create_bin_file(&pdev->dev.kobj, &mv64x60_hs_reg_attr);
+}
+
+subsys_initcall(mv64x60_sysfs_init);
+
+#endif /* CONFIG_SYSFS */
+
+static void __init mv64x60_pci_fixup_early(struct pci_dev *dev)
+{
+ /*
+ * Set the host bridge hdr_type to an invalid value so that
+ * pci_setup_device() will ignore the host bridge.
+ */
+ dev->hdr_type = PCI_HEADER_TYPE_INVALID;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360,
+ mv64x60_pci_fixup_early);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64460,
+ mv64x60_pci_fixup_early);
+
+static int __init mv64x60_add_bridge(struct device_node *dev)
+{
+ int len;
+ struct pci_controller *hose;
+ struct resource rsrc;
+ const int *bus_range;
+ int primary;
+
+ memset(&rsrc, 0, sizeof(rsrc));
+
+ /* Fetch host bridge registers address */
+ if (of_address_to_resource(dev, 0, &rsrc)) {
+ printk(KERN_ERR "No PCI reg property in device tree\n");
+ return -ENODEV;
+ }
+
+ /* Get bus range if any */
+ bus_range = of_get_property(dev, "bus-range", &len);
+ if (bus_range == NULL || len < 2 * sizeof(int))
+ printk(KERN_WARNING "Can't get bus-range for %s, assume"
+ " bus 0\n", dev->full_name);
+
+ hose = pcibios_alloc_controller();
+ if (!hose)
+ return -ENOMEM;
+
+ hose->arch_data = dev;
+ hose->set_cfg_type = 1;
+
+ hose->first_busno = bus_range ? bus_range[0] : 0;
+ hose->last_busno = bus_range ? bus_range[1] : 0xff;
+
+ setup_indirect_pci(hose, rsrc.start, rsrc.start + 4);
+ hose->bus_offset = hose->first_busno;
+
+ printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "
+ "Firmware bus number: %d->%d\n",
+ (unsigned long long)rsrc.start, hose->first_busno,
+ hose->last_busno);
+
+ /* Interpret the "ranges" property */
+ /* This also maps the I/O region and sets isa_io/mem_base */
+ primary = (hose->first_busno == 0);
+ pci_process_bridge_OF_ranges(hose, dev, primary);
+
+ return 0;
+}
+
+void __init mv64x60_pci_init(void)
+{
+ struct device_node *np = NULL;
+
+ while ((np = of_find_compatible_node(np, "pci", "mv64x60-pci")))
+ mv64x60_add_bridge(np);
+}
Index: linux-2.6-powerpc-df/arch/powerpc/platforms/embedded6xx/Kconfig
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/platforms/embedded6xx/Kconfig
+++ linux-2.6-powerpc-df/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -40,6 +40,7 @@ config MPC10X_BRIDGE
config MV64X60
bool
+ select PPC_INDIRECT_PCI
config MPC10X_OPENPIC
bool
^ permalink raw reply
* [PATCH 10/13] powerpc: check cache coherency of kernel vs firmware
From: Mark A. Greer @ 2007-05-10 20:08 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
From: Dale Farnsworth <dale@farnsworth.org>
check_cache_coherency() verifies that the cache coherency setting of
the kernel (CONFIG_NOT_COHERENT_CACHE) matches that left by the firmware,
as indicated by coherency-off device tree property.
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
---
arch/powerpc/Kconfig | 3 +
arch/powerpc/kernel/setup-common.c | 41 +++++++++++++++++++
arch/powerpc/platforms/embedded6xx/Kconfig | 1
3 files changed, 45 insertions(+)
Index: linux-2.6-powerpc-df/arch/powerpc/kernel/setup-common.c
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/kernel/setup-common.c
+++ linux-2.6-powerpc-df/arch/powerpc/kernel/setup-common.c
@@ -530,3 +530,44 @@ void __init setup_panic(void)
{
atomic_notifier_chain_register(&panic_notifier_list, &ppc_panic_block);
}
+
+#ifdef CONFIG_CHECK_CACHE_COHERENCY
+/*
+ * For platforms that have configurable cache-coherency. This function
+ * checks that the cache coherency setting of the kernel matches the setting
+ * left by the firmware, as indicated in the device tree. Since a mismatch
+ * will eventually result in DMA failures, we print * and error and call
+ * BUG() in that case.
+ */
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define KERNEL_COHERENCY 0
+#else
+#define KERNEL_COHERENCY 1
+#endif
+
+static int __init check_cache_coherency(void)
+{
+ struct device_node *np;
+ const void *prop;
+ int devtree_coherency;
+
+ np = of_find_node_by_path("/");
+ prop = of_get_property(np, "coherency-off", NULL);
+ of_node_put(np);
+
+ devtree_coherency = prop ? 0 : 1;
+
+ if (devtree_coherency != KERNEL_COHERENCY) {
+ printk(KERN_ERR
+ "kernel coherency:%s != device tree_coherency:%s\n",
+ KERNEL_COHERENCY ? "on" : "off",
+ devtree_coherency ? "on" : "off");
+ BUG();
+ }
+
+ return 0;
+}
+
+late_initcall(check_cache_coherency);
+#endif /* CONFIG_CHECK_CACHE_COHERENCY */
Index: linux-2.6-powerpc-df/arch/powerpc/Kconfig
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/Kconfig
+++ linux-2.6-powerpc-df/arch/powerpc/Kconfig
@@ -373,6 +373,9 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
default y
+
+config CONFIG_CHECK_CACHE_COHERENCY
+ bool
endmenu
source "init/Kconfig"
Index: linux-2.6-powerpc-df/arch/powerpc/platforms/embedded6xx/Kconfig
===================================================================
--- linux-2.6-powerpc-df.orig/arch/powerpc/platforms/embedded6xx/Kconfig
+++ linux-2.6-powerpc-df/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -41,6 +41,7 @@ config MPC10X_BRIDGE
config MV64X60
bool
select PPC_INDIRECT_PCI
+ select CONFIG_CHECK_CACHE_COHERENCY
config MPC10X_OPENPIC
bool
^ permalink raw reply
* [PATCH 11/13] powerpc: Add DTS file for the Motorola PrPMC2800 platform
From: Mark A. Greer @ 2007-05-10 20:08 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
Add the device tree source file for the prpmc2800 line of processor PMCs.
Several of the property values are updated by the bootwrapper but sane
defaults have been chosen in case the bootwrapper can't determine the
exact processor board variant. The defaults should allow the kernel
to boot despite having non-optimal device tree property values.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
arch/powerpc/boot/dts/prpmc2800.dts | 316 ++++++++++++++++++++++++++
1 file changed, 316 insertions(+)
Index: powerpc/arch/powerpc/boot/dts/prpmc2800.dts
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/dts/prpmc2800.dts
@@ -0,0 +1,316 @@
+/* Device Tree Source for Motorola PrPMC2800
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Property values that are labeled as "Default" will be updated by bootwrapper
+ * if it can determine the exact PrPMC type.
+ *
+ * To build:
+ * dtc -I dts -O asm -o prpmc2800.S -b 0 prpmc2800.dts
+ * dtc -I dts -O dtb -o prpmc2800.dtb -b 0 prpmc2800.dts
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "PrPMC280/PrPMC2800"; /* Default */
+ compatible = "PrPMC2800";
+ coherency-off;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,7447 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <2bb0b140>; /* Default (733 MHz) */
+ bus-frequency = <7f28155>; /* 133.333333 MHz */
+ timebase-frequency = <1fca055>; /* 33.333333 MHz */
+ /* Following required by dtc but not used */
+ i-cache-line-size = <0>;
+ d-cache-line-size = <0>;
+ i-cache-size = <0>;
+ d-cache-size = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; /* Default (512MB) */
+ };
+
+ mv64x60@f1000000 { /* Marvell Discovery */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+ model = "mv64360"; /* Default */
+ compatible = "mv64x60";
+ clock-frequency = <7f28155>; /* 133.333333 MHz */
+ reg = <f1000000 00010000>;
+ virtual-reg = <f1000000>;
+ ranges = <88000000 88000000 01000000 /* PCI 0 I/O Space */
+ 80000000 80000000 08000000 /* PCI 0 MEM Space */
+ a0000000 a0000000 04000000 /* User FLASH */
+ 00000000 f1000000 00010000 /* Bridge's regs */
+ f2000000 f2000000 00040000>; /* Integrated SRAM */
+
+ flash@a0000000 {
+ device_type = "rom";
+ compatible = "direct-mapped";
+ reg = <a0000000 4000000>; /* Default (64MB) */
+ probe-type = "CFI";
+ bank-width = <4>;
+ partitions = <00000000 00100000 /* RO */
+ 00100000 00040001 /* RW */
+ 00140000 00400000 /* RO */
+ 00540000 039c0000 /* RO */
+ 03f00000 00100000>; /* RO */
+ partition-names = "FW Image A\0FW Config Data\0Kernel Image\0Filesystem\0FW Image B";
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "mdio";
+ compatible = "mv64x60-mdio";
+ ethernet-phy@1 {
+ device_type = "ethernet-phy";
+ compatible = "bcm5421";
+ interrupts = <4c>; /* GPP 12 */
+ interrupt-parent = <&/mv64x60/pic>;
+ reg = <1>;
+ };
+ ethernet-phy@3 {
+ device_type = "ethernet-phy";
+ compatible = "bcm5421";
+ interrupts = <4c>; /* GPP 12 */
+ interrupt-parent = <&/mv64x60/pic>;
+ reg = <3>;
+ };
+ };
+
+ ethernet@2000 {
+ reg = <2000 2000>;
+ eth0 {
+ device_type = "network";
+ compatible = "mv64x60-eth";
+ block-index = <0>;
+ interrupts = <20>;
+ interrupt-parent = <&/mv64x60/pic>;
+ phy = <&/mv64x60/mdio/ethernet-phy@1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ eth1 {
+ device_type = "network";
+ compatible = "mv64x60-eth";
+ block-index = <1>;
+ interrupts = <21>;
+ interrupt-parent = <&/mv64x60/pic>;
+ phy = <&/mv64x60/mdio/ethernet-phy@3>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+
+ sdma@4000 {
+ device_type = "dma";
+ compatible = "mv64x60-sdma";
+ reg = <4000 c18>;
+ virtual-reg = <f1004000>;
+ interrupt-base = <0>;
+ interrupts = <24>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ sdma@6000 {
+ device_type = "dma";
+ compatible = "mv64x60-sdma";
+ reg = <6000 c18>;
+ virtual-reg = <f1006000>;
+ interrupt-base = <0>;
+ interrupts = <26>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ brg@b200 {
+ compatible = "mv64x60-brg";
+ reg = <b200 8>;
+ clock-src = <8>;
+ clock-frequency = <7ed6b40>;
+ current-speed = <2580>;
+ bcr = <0>;
+ };
+
+ brg@b208 {
+ compatible = "mv64x60-brg";
+ reg = <b208 8>;
+ clock-src = <8>;
+ clock-frequency = <7ed6b40>;
+ current-speed = <2580>;
+ bcr = <0>;
+ };
+
+ cunit@f200 {
+ reg = <f200 200>;
+ };
+
+ mpscrouting@b400 {
+ reg = <b400 c>;
+ };
+
+ mpscintr@b800 {
+ reg = <b800 100>;
+ virtual-reg = <f100b800>;
+ };
+
+ mpsc@8000 {
+ device_type = "serial";
+ compatible = "mpsc";
+ reg = <8000 38>;
+ virtual-reg = <f1008000>;
+ sdma = <&/mv64x60/sdma@4000>;
+ brg = <&/mv64x60/brg@b200>;
+ cunit = <&/mv64x60/cunit@f200>;
+ mpscrouting = <&/mv64x60/mpscrouting@b400>;
+ mpscintr = <&/mv64x60/mpscintr@b800>;
+ block-index = <0>;
+ max_idle = <28>;
+ chr_1 = <0>;
+ chr_2 = <0>;
+ chr_10 = <3>;
+ mpcr = <0>;
+ interrupts = <28>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ mpsc@9000 {
+ device_type = "serial";
+ compatible = "mpsc";
+ reg = <9000 38>;
+ virtual-reg = <f1009000>;
+ sdma = <&/mv64x60/sdma@6000>;
+ brg = <&/mv64x60/brg@b208>;
+ cunit = <&/mv64x60/cunit@f200>;
+ mpscrouting = <&/mv64x60/mpscrouting@b400>;
+ mpscintr = <&/mv64x60/mpscintr@b800>;
+ block-index = <1>;
+ max_idle = <28>;
+ chr_1 = <0>;
+ chr_2 = <0>;
+ chr_10 = <3>;
+ mpcr = <0>;
+ interrupts = <2a>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ i2c@c000 {
+ device_type = "i2c";
+ compatible = "mv64x60-i2c";
+ reg = <c000 20>;
+ virtual-reg = <f100c000>;
+ freq_m = <8>;
+ freq_n = <3>;
+ timeout = <3e8>; /* 1000 = 1 second */
+ retries = <1>;
+ interrupts = <25>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ pic {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ compatible = "mv64x60-pic";
+ reg = <0000 88>;
+ interrupt-controller;
+ };
+
+ mpp@f000 {
+ compatible = "mv64x60-mpp";
+ reg = <f000 10>;
+ };
+
+ gpp@f100 {
+ compatible = "mv64x60-gpp";
+ reg = <f100 20>;
+ };
+
+ pci@80000000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ compatible = "mv64x60-pci";
+ reg = <0cf8 8>;
+ ranges = <01000000 0 0 88000000 0 01000000
+ 02000000 0 80000000 80000000 0 08000000>;
+ bus-range = <0 ff>;
+ clock-frequency = <3EF1480>;
+ interrupt-pci-iack = <0c34>;
+ interrupt-parent = <&/mv64x60/pic>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0a */
+ 5000 0 0 1 &/mv64x60/pic 50
+ 5000 0 0 2 &/mv64x60/pic 51
+ 5000 0 0 3 &/mv64x60/pic 5b
+ 5000 0 0 4 &/mv64x60/pic 5d
+
+ /* IDSEL 0x0b */
+ 5800 0 0 1 &/mv64x60/pic 5b
+ 5800 0 0 2 &/mv64x60/pic 5d
+ 5800 0 0 3 &/mv64x60/pic 50
+ 5800 0 0 4 &/mv64x60/pic 51
+
+ /* IDSEL 0x0c */
+ 6000 0 0 1 &/mv64x60/pic 5b
+ 6000 0 0 2 &/mv64x60/pic 5d
+ 6000 0 0 3 &/mv64x60/pic 50
+ 6000 0 0 4 &/mv64x60/pic 51
+
+ /* IDSEL 0x0d */
+ 6800 0 0 1 &/mv64x60/pic 5d
+ 6800 0 0 2 &/mv64x60/pic 50
+ 6800 0 0 3 &/mv64x60/pic 51
+ 6800 0 0 4 &/mv64x60/pic 5b
+ >;
+ };
+
+ cpu-error@0070 {
+ compatible = "mv64x60-cpu-error";
+ reg = <0070 10 0128 28>;
+ interrupts = <03>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ sram-ctrl@0380 {
+ compatible = "mv64x60-sram-ctrl";
+ reg = <0380 80>;
+ interrupts = <0d>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ pci-error@1d40 {
+ compatible = "mv64x60-pci-error";
+ reg = <1d40 40 0c28 4>;
+ interrupts = <0c>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ mem-ctrl@1400 {
+ compatible = "mv64x60-mem-ctrl";
+ reg = <1400 60>;
+ interrupts = <11>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+ };
+
+ chosen {
+ bootargs = "ip=on console=ttyMM0";
+ linux,stdout-path = "/mv64x60/mpsc@8000";
+ };
+};
^ permalink raw reply
* [PATCH 12/13] powerpc: Add bootwrapper support for Motorola PrPMC2800 platform
From: Mark A. Greer @ 2007-05-10 20:09 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20070510200237.GA19756@mag.az.mvista.com>
The Motorola PrPMC280 and PrPMC2800 processor modules sit on an F101 or
PrPMC2800 baseboard, respectively. There are several variants of each
type of processor module which can have different amounts of memory,
amounts of FLASH, cpu frequencies, and an mv64360 or an mv64362.
The bootwrapper code for that platform reads VPD from an I2C EEPROM
to determine the processor module variant. From the variant, the
amount of memory, etc. is determined and the device tree is updated
accordingly. If the variant cannot be determined (e.g., corrupted
VPD or a previously unknown variant), the property values already
in the device tree are used.
Also, the firmware for those platforms does not completely configure
the mv64x60 host bridge so that configuration is done here.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
---
arch/powerpc/boot/Makefile | 3
arch/powerpc/boot/prpmc2800.c | 577 ++++++++++++++++++++++++++++++++
2 files changed, 579 insertions(+), 1 deletion(-)
Index: powerpc/arch/powerpc/boot/prpmc2800.c
===================================================================
--- /dev/null
+++ powerpc/arch/powerpc/boot/prpmc2800.c
@@ -0,0 +1,577 @@
+/*
+ * Motorola ECC prpmc280/f101 & prpmc2800/f101e platform code.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "page.h"
+#include "string.h"
+#include "stdio.h"
+#include "io.h"
+#include "ops.h"
+#include "gunzip_util.h"
+#include "mv64x60.h"
+
+extern char _end[];
+extern char _vmlinux_start[], _vmlinux_end[];
+extern char _dtb_start[], _dtb_end[];
+
+extern void udelay(long delay);
+
+#define KB 1024U
+#define MB (KB*KB)
+#define GB (KB*MB)
+#define MHz (1000U*1000U)
+#define GHz (1000U*MHz)
+
+#define BOARD_MODEL "PrPMC2800"
+#define BOARD_MODEL_MAX 32 /* max strlen(BOARD_MODEL) + 1 */
+
+#define EEPROM2_ADDR 0xa4
+#define EEPROM3_ADDR 0xa8
+
+BSS_STACK(16*KB);
+
+static u8 *bridge_base;
+
+typedef enum {
+ BOARD_MODEL_PRPMC280,
+ BOARD_MODEL_PRPMC2800,
+} prpmc2800_board_model;
+
+typedef enum {
+ BRIDGE_TYPE_MV64360,
+ BRIDGE_TYPE_MV64362,
+} prpmc2800_bridge_type;
+
+struct prpmc2800_board_info {
+ prpmc2800_board_model model;
+ char variant;
+ prpmc2800_bridge_type bridge_type;
+ u8 subsys0;
+ u8 subsys1;
+ u8 vpd4;
+ u8 vpd4_mask;
+ u32 core_speed;
+ u32 mem_size;
+ u32 boot_flash;
+ u32 user_flash;
+};
+
+static struct prpmc2800_board_info prpmc2800_board_info[] = {
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'a',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 1*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'b',
+ .bridge_type = BRIDGE_TYPE_MV64362,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x01,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 0,
+ .user_flash = 0,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'c',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x02,
+ .vpd4_mask = 0x0f,
+ .core_speed = 733*MHz,
+ .mem_size = 512*MB,
+ .boot_flash = 1*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'd',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x03,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 1*GB,
+ .boot_flash = 1*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'e',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x04,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 1*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'f',
+ .bridge_type = BRIDGE_TYPE_MV64362,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x05,
+ .vpd4_mask = 0x0f,
+ .core_speed = 733*MHz,
+ .mem_size = 128*MB,
+ .boot_flash = 1*MB,
+ .user_flash = 0,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'g',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x06,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 256*MB,
+ .boot_flash = 1*MB,
+ .user_flash = 0,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC280,
+ .variant = 'h',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xff,
+ .subsys1 = 0xff,
+ .vpd4 = 0x07,
+ .vpd4_mask = 0x0f,
+ .core_speed = 1*GHz,
+ .mem_size = 1*GB,
+ .boot_flash = 1*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'a',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xb2,
+ .subsys1 = 0x8c,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'b',
+ .bridge_type = BRIDGE_TYPE_MV64362,
+ .subsys0 = 0xb2,
+ .subsys1 = 0x8d,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 0,
+ .user_flash = 0,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'c',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xb2,
+ .subsys1 = 0x8e,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 733*MHz,
+ .mem_size = 512*MB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'd',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xb2,
+ .subsys1 = 0x8f,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 1*GHz,
+ .mem_size = 1*GB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'e',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xa2,
+ .subsys1 = 0x8a,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 1*GHz,
+ .mem_size = 512*MB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'f',
+ .bridge_type = BRIDGE_TYPE_MV64362,
+ .subsys0 = 0xa2,
+ .subsys1 = 0x8b,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 733*MHz,
+ .mem_size = 128*MB,
+ .boot_flash = 2*MB,
+ .user_flash = 0,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'g',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xa2,
+ .subsys1 = 0x8c,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 1*GHz,
+ .mem_size = 2*GB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+ {
+ .model = BOARD_MODEL_PRPMC2800,
+ .variant = 'h',
+ .bridge_type = BRIDGE_TYPE_MV64360,
+ .subsys0 = 0xa2,
+ .subsys1 = 0x8d,
+ .vpd4 = 0x00,
+ .vpd4_mask = 0x00,
+ .core_speed = 733*MHz,
+ .mem_size = 1*GB,
+ .boot_flash = 2*MB,
+ .user_flash = 64*MB,
+ },
+};
+
+static struct prpmc2800_board_info *prpmc2800_get_board_info(u8 *vpd)
+{
+ struct prpmc2800_board_info *bip;
+ int i;
+
+ for (i=0,bip=prpmc2800_board_info; i<ARRAY_SIZE(prpmc2800_board_info);
+ i++,bip++)
+ if ((vpd[0] == bip->subsys0) && (vpd[1] == bip->subsys1)
+ && ((vpd[4] & bip->vpd4_mask) == bip->vpd4))
+ return bip;
+
+ return NULL;
+}
+
+/* Get VPD from i2c eeprom 2, then match it to a board info entry */
+static struct prpmc2800_board_info *prpmc2800_get_bip(void)
+{
+ struct prpmc2800_board_info *bip;
+ u8 vpd[5];
+ int rc;
+
+ if (mv64x60_i2c_open())
+ fatal("Error: Can't open i2c device\n\r");
+
+ /* Get VPD from i2c eeprom-2 */
+ memset(vpd, 0, sizeof(vpd));
+ rc = mv64x60_i2c_read(EEPROM2_ADDR, vpd, 0x1fde, 2, sizeof(vpd));
+ if (rc < 0)
+ fatal("Error: Couldn't read eeprom2\n\r");
+ mv64x60_i2c_close();
+
+ /* Get board type & related info */
+ bip = prpmc2800_get_board_info(vpd);
+ if (bip == NULL) {
+ printf("Error: Unsupported board or corrupted VPD:\n\r");
+ printf(" 0x%x 0x%x 0x%x 0x%x 0x%x\n\r",
+ vpd[0], vpd[1], vpd[2], vpd[3], vpd[4]);
+ printf("Using device tree defaults...\n\r");
+ }
+
+ return bip;
+}
+
+static void prpmc2800_bridge_setup(u32 mem_size)
+{
+ u32 i, v[12], enables, acc_bits;
+ u32 pci_base_hi, pci_base_lo, size, buf[2];
+ unsigned long cpu_base;
+ int rc;
+ void *devp;
+ u8 *bridge_pbase, is_coherent;
+ struct mv64x60_cpu2pci_win *tbl;
+
+ bridge_pbase = mv64x60_get_bridge_pbase();
+ is_coherent = mv64x60_is_coherent();
+
+ if (is_coherent)
+ acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB
+ | MV64x60_PCI_ACC_CNTL_SWAP_NONE
+ | MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES
+ | MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES;
+ else
+ acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE
+ | MV64x60_PCI_ACC_CNTL_SWAP_NONE
+ | MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES
+ | MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES;
+
+ mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
+ mv64x60_config_pci_windows(bridge_base, bridge_pbase, 0, 0, mem_size,
+ acc_bits);
+
+ /* Get the cpu -> pci i/o & mem mappings from the device tree */
+ devp = finddevice("/mv64x60/pci@80000000");
+ if (devp == NULL)
+ fatal("Error: Missing /mv64x60/pci@80000000"
+ " device tree node\n\r");
+
+ rc = getprop(devp, "ranges", v, sizeof(v));
+ if (rc != sizeof(v))
+ fatal("Error: Can't find /mv64x60/pci@80000000/ranges"
+ " property\n\r");
+
+ /* Get the cpu -> pci i/o & mem mappings from the device tree */
+ devp = finddevice("/mv64x60");
+ if (devp == NULL)
+ fatal("Error: Missing /mv64x60 device tree node\n\r");
+
+ enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
+ enables |= 0x0007fe00; /* Disable all cpu->pci windows */
+ out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
+
+ for (i=0; i<12; i+=6) {
+ switch (v[i] & 0xff000000) {
+ case 0x01000000: /* PCI I/O Space */
+ tbl = mv64x60_cpu2pci_io;
+ break;
+ case 0x02000000: /* PCI MEM Space */
+ tbl = mv64x60_cpu2pci_mem;
+ break;
+ default:
+ continue;
+ }
+
+ pci_base_hi = v[i+1];
+ pci_base_lo = v[i+2];
+ cpu_base = v[i+3];
+ size = v[i+5];
+
+ buf[0] = cpu_base;
+ buf[1] = size;
+
+ if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
+ fatal("Error: Can't translate PCI address 0x%x\n\r",
+ (u32)cpu_base);
+
+ mv64x60_config_cpu2pci_window(bridge_base, 0, pci_base_hi,
+ pci_base_lo, cpu_base, size, tbl);
+ }
+
+ enables &= ~0x00000600; /* Enable cpu->pci0 i/o, cpu->pci0 mem0 */
+ out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
+}
+
+static void prpmc2800_fixups(void)
+{
+ u32 v[2], l, mem_size;
+ int rc;
+ void *devp;
+ char model[BOARD_MODEL_MAX];
+ struct prpmc2800_board_info *bip;
+
+ bip = prpmc2800_get_bip(); /* Get board info based on VPD */
+
+ mem_size = (bip) ? bip->mem_size : mv64x60_get_mem_size(bridge_base);
+ prpmc2800_bridge_setup(mem_size); /* Do necessary bridge setup */
+
+ /* If the VPD doesn't match what we know about, just use the
+ * defaults already in the device tree.
+ */
+ if (!bip)
+ return;
+
+ /* Know the board type so override device tree defaults */
+ /* Set /model appropriately */
+ devp = finddevice("/");
+ if (devp == NULL)
+ fatal("Error: Missing '/' device tree node\n\r");
+ memset(model, 0, BOARD_MODEL_MAX);
+ strncpy(model, BOARD_MODEL, BOARD_MODEL_MAX - 2);
+ l = strlen(model);
+ if (bip->model == BOARD_MODEL_PRPMC280)
+ l--;
+ model[l++] = bip->variant;
+ model[l++] = '\0';
+ setprop(devp, "model", model, l);
+
+ /* Set /cpus/PowerPC,7447/clock-frequency */
+ devp = finddevice("/cpus/PowerPC,7447");
+ if (devp == NULL)
+ fatal("Error: Missing proper /cpus device tree node\n\r");
+ v[0] = bip->core_speed;
+ setprop(devp, "clock-frequency", &v[0], sizeof(v[0]));
+
+ /* Set /memory/reg size */
+ devp = finddevice("/memory");
+ if (devp == NULL)
+ fatal("Error: Missing /memory device tree node\n\r");
+ v[0] = 0;
+ v[1] = bip->mem_size;
+ setprop(devp, "reg", v, sizeof(v));
+
+ /* Update /mv64x60/model, if this is a mv64362 */
+ if (bip->bridge_type == BRIDGE_TYPE_MV64362) {
+ devp = finddevice("/mv64x60");
+ if (devp == NULL)
+ fatal("Error: Missing /mv64x60 device tree node\n\r");
+ setprop(devp, "model", "mv64362", strlen("mv64362") + 1);
+ }
+
+ /* Set User FLASH size */
+ devp = finddevice("/mv64x60/flash@a0000000");
+ if (devp == NULL)
+ fatal("Error: Missing User FLASH device tree node\n\r");
+ rc = getprop(devp, "reg", v, sizeof(v));
+ if (rc != sizeof(v))
+ fatal("Error: Can't find User FLASH reg property\n\r");
+ v[1] = bip->user_flash;
+ setprop(devp, "reg", v, sizeof(v));
+}
+
+#define MV64x60_MPP_CNTL_0 0xf000
+#define MV64x60_MPP_CNTL_2 0xf008
+#define MV64x60_GPP_IO_CNTL 0xf100
+#define MV64x60_GPP_LEVEL_CNTL 0xf110
+#define MV64x60_GPP_VALUE_SET 0xf118
+
+static void prpmc2800_reset(void)
+{
+ u32 temp;
+
+ udelay(5000000);
+
+ if (bridge_base != 0) {
+ temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
+ temp &= 0xFFFF0FFF;
+ out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);
+
+ temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
+ temp |= 0x00000004;
+ out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
+
+ temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
+ temp |= 0x00000004;
+ out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
+
+ temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
+ temp &= 0xFFFF0FFF;
+ out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);
+
+ temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
+ temp |= 0x00080000;
+ out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
+
+ temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
+ temp |= 0x00080000;
+ out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
+
+ out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),
+ 0x00080004);
+ }
+
+ for (;;);
+}
+
+#define HEAP_SIZE (16*MB)
+static struct gunzip_state gzstate;
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ struct elf_info ei;
+ char *heap_start, *dtb;
+ int dt_size = _dtb_end - _dtb_start;
+ void *vmlinuz_addr = _vmlinux_start;
+ unsigned long vmlinuz_size = _vmlinux_end - _vmlinux_start;
+ char elfheader[256];
+
+ if (dt_size <= 0) /* No fdt */
+ exit();
+
+ /*
+ * Start heap after end of the kernel (after decompressed to
+ * address 0) or the end of the zImage, whichever is higher.
+ * That's so things allocated by simple_alloc won't overwrite
+ * any part of the zImage and the kernel won't overwrite the dtb
+ * when decompressed & relocated.
+ */
+ gunzip_start(&gzstate, vmlinuz_addr, vmlinuz_size);
+ gunzip_exactly(&gzstate, elfheader, sizeof(elfheader));
+
+ if (!parse_elf32(elfheader, &ei))
+ exit();
+
+ heap_start = (char *)(ei.memsize + ei.elfoffset); /* end of kernel*/
+ heap_start = max(heap_start, (char *)_end); /* end of zImage */
+
+ if ((unsigned)simple_alloc_init(heap_start, HEAP_SIZE, 2*KB, 16)
+ > (128*MB))
+ exit();
+
+ /* Relocate dtb to safe area past end of zImage & kernel */
+ dtb = malloc(dt_size);
+ if (!dtb)
+ exit();
+ memmove(dtb, _dtb_start, dt_size);
+ if (ft_init(dtb, dt_size, 16))
+ exit();
+
+ bridge_base = mv64x60_get_bridge_base();
+
+ platform_ops.fixups = prpmc2800_fixups;
+ platform_ops.exit = prpmc2800_reset;
+
+ if (serial_console_init() < 0)
+ exit();
+}
+
+/* _zimage_start called very early--need to turn off external interrupts */
+asm (" .globl _zimage_start\n\
+ _zimage_start:\n\
+ mfmsr 10\n\
+ rlwinm 10,10,0,~(1<<15) /* Clear MSR_EE */\n\
+ sync\n\
+ mtmsr 10\n\
+ isync\n\
+ b _zimage_start_lib\n\
+");
Index: powerpc/arch/powerpc/boot/Makefile
===================================================================
--- powerpc.orig/arch/powerpc/boot/Makefile
+++ powerpc/arch/powerpc/boot/Makefile
@@ -45,7 +45,7 @@ src-wlib := string.S crt0.S stdio.c main
gunzip_util.c elf_util.c $(zlib) devtree.c \
44x.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c
src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \
- cuboot-ebony.c treeboot-ebony.c
+ cuboot-ebony.c treeboot-ebony.c prpmc2800.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -132,6 +132,7 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
image-$(CONFIG_PPC_HOLLY) += zImage.holly-elf
+image-$(CONFIG_PPC_PRPMC2800) += zImage.prpmc2800
image-$(CONFIG_DEFAULT_UIMAGE) += uImage
ifneq ($(CONFIG_DEVICE_TREE),"")
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