* Re: [PATCH v3][POWERPC] document ipic level/sense info
From: Grant Likely @ 2007-07-10 15:03 UTC (permalink / raw)
To: Stuart Yoder; +Cc: linuxppc-dev, paulus
In-Reply-To: <200707101451.l6AEp9A3019214@ld0164-tx32.am.freescale.net>
On 7/10/07, Stuart Yoder <b08248@freescale.com> wrote:
> document level/sense encoding info for IPIC
> interrupt controllers
>
> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
> ---
> + 2 = high to low edge sense type enabled
> + 8 = active low level sense type enabled
> +
> +Note: other level/sense types (0,1,4, etc) are not supported.
Perfect! :-)
Acked-by: Grant Likely <grant.likely@secretlab.ca>
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* [PATCH] Consolidate mm_context_t definition in mmu.h
From: Josh Boyer @ 2007-07-10 15:01 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, david
All of the platforms except PPC64 share a common mm_context_t definition.
Defining it in mmu.h avoids duplicating it in the platform specific mmu
header files.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
---
include/asm-powerpc/mmu-44x.h | 5 -----
include/asm-powerpc/mmu-8xx.h | 4 ----
include/asm-powerpc/mmu-fsl-booke.h | 4 ----
include/asm-powerpc/mmu-hash32.h | 5 -----
include/asm-powerpc/mmu-hash64.h | 16 ----------------
include/asm-powerpc/mmu.h | 28 ++++++++++++++++++++++++++++
6 files changed, 28 insertions(+), 34 deletions(-)
--- linux-2.6.orig/include/asm-powerpc/mmu-44x.h
+++ linux-2.6/include/asm-powerpc/mmu-44x.h
@@ -55,11 +55,6 @@
typedef unsigned long long phys_addr_t;
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
-
#endif /* !__ASSEMBLY__ */
#ifndef CONFIG_PPC_EARLY_DEBUG_44x
--- linux-2.6.orig/include/asm-powerpc/mmu-8xx.h
+++ linux-2.6/include/asm-powerpc/mmu-8xx.h
@@ -138,10 +138,6 @@
#ifndef __ASSEMBLY__
typedef unsigned long phys_addr_t;
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_MMU_8XX_H_ */
--- linux-2.6.orig/include/asm-powerpc/mmu-fsl-booke.h
+++ linux-2.6/include/asm-powerpc/mmu-fsl-booke.h
@@ -79,10 +79,6 @@ typedef unsigned long phys_addr_t;
typedef unsigned long long phys_addr_t;
#endif
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */
--- linux-2.6.orig/include/asm-powerpc/mmu-hash32.h
+++ linux-2.6/include/asm-powerpc/mmu-hash32.h
@@ -79,11 +79,6 @@ struct hash_pte {
unsigned long pp:2; /* Page protection */
};
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
-
typedef unsigned long phys_addr_t;
#endif /* !__ASSEMBLY__ */
--- linux-2.6.orig/include/asm-powerpc/mmu-hash64.h
+++ linux-2.6/include/asm-powerpc/mmu-hash64.h
@@ -359,22 +359,6 @@ extern void stab_initialize(unsigned lon
#ifndef __ASSEMBLY__
-typedef unsigned long mm_context_id_t;
-
-typedef struct {
- mm_context_id_t id;
- u16 user_psize; /* page size index */
-
-#ifdef CONFIG_PPC_MM_SLICES
- u64 low_slices_psize; /* SLB page size encodings */
- u64 high_slices_psize; /* 4 bits per slice for now */
-#else
- u16 sllp; /* SLB page size encoding */
-#endif
- unsigned long vdso_base;
-} mm_context_t;
-
-
static inline unsigned long vsid_scramble(unsigned long protovsid)
{
#if 0
--- linux-2.6.orig/include/asm-powerpc/mmu.h
+++ linux-2.6/include/asm-powerpc/mmu.h
@@ -19,5 +19,33 @@
# include <asm/mmu-8xx.h>
#endif
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_PPC64
+typedef unsigned long mm_context_id_t;
+
+typedef struct {
+ mm_context_id_t id;
+ u16 user_psize; /* page size index */
+
+#ifdef CONFIG_PPC_MM_SLICES
+ u64 low_slices_psize; /* SLB page size encodings */
+ u64 high_slices_psize; /* 4 bits per slice for now */
+#else
+ u16 sllp; /* SLB page size encoding */
+#endif
+ unsigned long vdso_base;
+} mm_context_t;
+
+#else /* !CONFIG_PPC64 */
+
+typedef struct {
+ unsigned long id;
+ unsigned long vdso_base;
+} mm_context_t;
+
+#endif /* CONFIG_PPC64 */
+#endif /* !__ASSEMBLY__ */
+
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MMU_H_ */
^ permalink raw reply
* [patch 0/6] Unify the PCI/PCI Express support for 83xx/85xx/86xx
From: Zang Roy-r61911 @ 2007-07-10 15:50 UTC (permalink / raw)
To: Kumar Gala, Paul Mackerras; +Cc: linuxppc-dev list
This series of patches do:
(1) unify the PCI/PCI express support
for 83xx/85xx/86xx.
(2) Add basic PCI Express support for mpc8548 Rev 2.0
board.
(3) Add basic PCI support for mpc8568mds board.
The patches have been tested on 8548 rev2.0 with Arcadia 3.1
board, mpc8568mds board and 8641HPCN board.
Some of them have been in the tree on opensource.freescale.com.
I regenerated them based on my previous patches and comments.
The baseline is Kumar's current tree for paulus.
The VIA support on CDS board and PCI/E support for
8544DS board will be in next series of patches :-).
^ permalink raw reply
* [patch 1/6] Create common fsl pci/e files based on 86xx platform
From: Zang Roy-r61911 @ 2007-07-10 15:51 UTC (permalink / raw)
To: Kumar Gala, Paul Mackerras; +Cc: linuxppc-dev list
From: Roy Zang <tie-fei.zang@freescale.com>
Move
arch/powerpc/platforms/86xx/pci.c -> arch/powerpc/sysdev/fsl_pci.c
arch/powerpc/sysdev/fsl_pcie.h -> arch/powerpc/sysdev/fsl_pci.h
as the base to unify 83xx/85xx/86xx pci and pcie.
Add CONFIG_FSL_PCI to build fsl_pci.c for Freescale pci and pcie option.
The code is still work for 86xx platform.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/Kconfig | 4 +
arch/powerpc/platforms/86xx/Kconfig | 1 +
arch/powerpc/platforms/86xx/Makefile | 1 -
arch/powerpc/platforms/86xx/pci.c | 238 ----------------------------------
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_pci.c | 238 ++++++++++++++++++++++++++++++++++
arch/powerpc/sysdev/fsl_pci.h | 94 +++++++++++++
arch/powerpc/sysdev/fsl_pcie.h | 94 -------------
8 files changed, 338 insertions(+), 333 deletions(-)
delete mode 100644 arch/powerpc/platforms/86xx/pci.c
create mode 100644 arch/powerpc/sysdev/fsl_pci.c
create mode 100644 arch/powerpc/sysdev/fsl_pci.h
delete mode 100644 arch/powerpc/sysdev/fsl_pcie.h
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index cbfbd98..8c780bf 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -419,6 +419,10 @@ config SBUS
config FSL_SOC
bool
+config FSL_PCI
+ bool
+ depends on PPC_86xx
+
# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
config MCA
bool
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 0faebfd..c848173 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -16,6 +16,7 @@ config MPC8641
bool
select PPC_INDIRECT_PCI
select PPC_INDIRECT_PCI_BE
+ select FSL_PCI
select PPC_UDBG_16550
select MPIC
default y if MPC8641_HPCN
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index 418fd8f..3376c77 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -4,4 +4,3 @@
obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
deleted file mode 100644
index 73cd5b0..0000000
--- a/arch/powerpc/platforms/86xx/pci.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * MPC86XX pci setup code
- *
- * Recode: ZHANG WEI <wei.zhang@freescale.com>
- * Initial author: Xianghua Xiao <x.xiao@freescale.com>
- *
- * Copyright 2006 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/serial.h>
-
-#include <asm/system.h>
-#include <asm/atomic.h>
-#include <asm/io.h>
-#include <asm/prom.h>
-#include <asm/pci-bridge.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pcie.h>
-
-#include "mpc86xx.h"
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
-#else
-#define DBG(fmt, args...)
-#endif
-
-struct pcie_outbound_window_regs {
- uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
- uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
- uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
- char res1[4];
- uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
- char res2[12];
-};
-
-struct pcie_inbound_window_regs {
- uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
- char res1[4];
- uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
- uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
- uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
- char res2[12];
-};
-
-static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
-{
- volatile struct ccsr_pex *pcie;
- volatile struct pcie_outbound_window_regs *pcieow;
- volatile struct pcie_inbound_window_regs *pcieiw;
- int i = 0;
-
- DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
- rsrc->end - rsrc->start + 1);
- pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
-
- /* Disable all windows (except pexowar0 since its ignored) */
- pcie->pexowar1 = 0;
- pcie->pexowar2 = 0;
- pcie->pexowar3 = 0;
- pcie->pexowar4 = 0;
- pcie->pexiwar1 = 0;
- pcie->pexiwar2 = 0;
- pcie->pexiwar3 = 0;
-
- pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
- pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
-
- /* Setup outbound MEM window */
- for(i = 0; i < 3; i++)
- if (hose->mem_resources[i].flags & IORESOURCE_MEM){
- DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
- hose->mem_resources[i].start,
- hose->mem_resources[i].end
- - hose->mem_resources[i].start + 1);
- pcieow->pexotar = (hose->mem_resources[i].start) >> 12
- & 0x000fffff;
- pcieow->pexotear = 0;
- pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
- & 0x000fffff;
- /* Enable, Mem R/W */
- pcieow->pexowar = 0x80044000 |
- (__ilog2(hose->mem_resources[i].end
- - hose->mem_resources[i].start + 1)
- - 1);
- pcieow++;
- }
-
- /* Setup outbound IO window */
- if (hose->io_resource.flags & IORESOURCE_IO){
- DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
- hose->io_resource.start,
- hose->io_resource.end - hose->io_resource.start + 1,
- hose->io_base_phys);
- pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
- pcieow->pexotear = 0;
- pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
- /* Enable, IO R/W */
- pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
- - hose->io_resource.start + 1) - 1);
- }
-
- /* Setup 2G inbound Memory Window @ 0 */
- pcieiw->pexitar = 0x00000000;
- pcieiw->pexiwbar = 0x00000000;
- /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
- pcieiw->pexiwar = 0xa0f5501e;
-}
-
-static void __init
-mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
-{
- u16 cmd;
-
- DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
- pcie_offset, pcie_size);
-
- early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
- | PCI_COMMAND_IO;
- early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
-
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
-}
-
-static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
-{
- struct resource *res;
- int i, res_idx = PCI_BRIDGE_RESOURCES;
- struct pci_controller *hose;
-
- /*
- * Make the bridge be transparent.
- */
- dev->transparent = 1;
-
- hose = pci_bus_to_host(dev->bus);
- if (!hose) {
- printk(KERN_ERR "Can't find hose for bus %d\n",
- dev->bus->number);
- return;
- }
-
- if (hose->io_resource.flags) {
- res = &dev->resource[res_idx++];
- res->start = hose->io_resource.start;
- res->end = hose->io_resource.end;
- res->flags = hose->io_resource.flags;
- }
-
- for (i = 0; i < 3; i++) {
- res = &dev->resource[res_idx + i];
- res->start = hose->mem_resources[i].start;
- res->end = hose->mem_resources[i].end;
- res->flags = hose->mem_resources[i].flags;
- }
-}
-
-
-DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
-DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
-
-#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
-#define PCIE_LTSSM_L0 0x16 /* L0 state */
-
-int __init mpc86xx_add_bridge(struct device_node *dev)
-{
- int len;
- struct pci_controller *hose;
- struct resource rsrc;
- const int *bus_range;
- int has_address = 0;
- int primary = 0;
- u16 val;
-
- DBG("Adding PCIE host bridge %s\n", dev->full_name);
-
- /* Fetch host bridge registers address */
- has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
-
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int))
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
-
- pci_assign_all_buses = 1;
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
-
- hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
- PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
-
- hose->first_busno = bus_range ? bus_range[0] : 0x0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
-
- setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
-
- /* Probe the hose link training status */
- early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
- if (val < PCIE_LTSSM_L0)
- return -ENXIO;
-
- /* Setup the PCIE host controller. */
- mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
-
- if ((rsrc.start & 0xfffff) == 0x8000)
- primary = 1;
-
- printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long) rsrc.start,
- hose->first_busno, hose->last_busno);
-
- DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, primary);
-
- /* Setup PEX window registers */
- setup_pcie_atmu(hose, &rsrc);
-
- return 0;
-}
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 7d8ac1b..0a9ae95 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PPC_PMI) += pmi.o
obj-$(CONFIG_U3_DART) += dart_iommu.o
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
+obj-$(CONFIG_FSL_PCI) += fsl_pci.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
new file mode 100644
index 0000000..24ba1b6
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -0,0 +1,238 @@
+/*
+ * MPC86XX pci setup code
+ *
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/serial.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "../platforms/86xx/mpc86xx.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
+#else
+#define DBG(fmt, args...)
+#endif
+
+struct pcie_outbound_window_regs {
+ uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
+ uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
+ uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
+ char res1[4];
+ uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
+ char res2[12];
+};
+
+struct pcie_inbound_window_regs {
+ uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
+ char res1[4];
+ uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
+ uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
+ uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
+ char res2[12];
+};
+
+static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
+{
+ volatile struct ccsr_pex *pcie;
+ volatile struct pcie_outbound_window_regs *pcieow;
+ volatile struct pcie_inbound_window_regs *pcieiw;
+ int i = 0;
+
+ DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
+ rsrc->end - rsrc->start + 1);
+ pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
+
+ /* Disable all windows (except pexowar0 since its ignored) */
+ pcie->pexowar1 = 0;
+ pcie->pexowar2 = 0;
+ pcie->pexowar3 = 0;
+ pcie->pexowar4 = 0;
+ pcie->pexiwar1 = 0;
+ pcie->pexiwar2 = 0;
+ pcie->pexiwar3 = 0;
+
+ pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
+ pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
+
+ /* Setup outbound MEM window */
+ for(i = 0; i < 3; i++)
+ if (hose->mem_resources[i].flags & IORESOURCE_MEM){
+ DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
+ hose->mem_resources[i].start,
+ hose->mem_resources[i].end
+ - hose->mem_resources[i].start + 1);
+ pcieow->pexotar = (hose->mem_resources[i].start) >> 12
+ & 0x000fffff;
+ pcieow->pexotear = 0;
+ pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
+ & 0x000fffff;
+ /* Enable, Mem R/W */
+ pcieow->pexowar = 0x80044000 |
+ (__ilog2(hose->mem_resources[i].end
+ - hose->mem_resources[i].start + 1)
+ - 1);
+ pcieow++;
+ }
+
+ /* Setup outbound IO window */
+ if (hose->io_resource.flags & IORESOURCE_IO){
+ DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
+ hose->io_resource.start,
+ hose->io_resource.end - hose->io_resource.start + 1,
+ hose->io_base_phys);
+ pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
+ pcieow->pexotear = 0;
+ pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
+ /* Enable, IO R/W */
+ pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
+ - hose->io_resource.start + 1) - 1);
+ }
+
+ /* Setup 2G inbound Memory Window @ 0 */
+ pcieiw->pexitar = 0x00000000;
+ pcieiw->pexiwbar = 0x00000000;
+ /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
+ pcieiw->pexiwar = 0xa0f5501e;
+}
+
+static void __init
+mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
+{
+ u16 cmd;
+
+ DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
+ pcie_offset, pcie_size);
+
+ early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+ | PCI_COMMAND_IO;
+ early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
+
+ early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
+}
+
+static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
+{
+ struct resource *res;
+ int i, res_idx = PCI_BRIDGE_RESOURCES;
+ struct pci_controller *hose;
+
+ /*
+ * Make the bridge be transparent.
+ */
+ dev->transparent = 1;
+
+ hose = pci_bus_to_host(dev->bus);
+ if (!hose) {
+ printk(KERN_ERR "Can't find hose for bus %d\n",
+ dev->bus->number);
+ return;
+ }
+
+ if (hose->io_resource.flags) {
+ res = &dev->resource[res_idx++];
+ res->start = hose->io_resource.start;
+ res->end = hose->io_resource.end;
+ res->flags = hose->io_resource.flags;
+ }
+
+ for (i = 0; i < 3; i++) {
+ res = &dev->resource[res_idx + i];
+ res->start = hose->mem_resources[i].start;
+ res->end = hose->mem_resources[i].end;
+ res->flags = hose->mem_resources[i].flags;
+ }
+}
+
+
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
+
+#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
+#define PCIE_LTSSM_L0 0x16 /* L0 state */
+
+int __init mpc86xx_add_bridge(struct device_node *dev)
+{
+ int len;
+ struct pci_controller *hose;
+ struct resource rsrc;
+ const int *bus_range;
+ int has_address = 0;
+ int primary = 0;
+ u16 val;
+
+ DBG("Adding PCIE host bridge %s\n", dev->full_name);
+
+ /* Fetch host bridge registers address */
+ has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
+
+ /* Get bus range if any */
+ bus_range = of_get_property(dev, "bus-range", &len);
+ if (bus_range == NULL || len < 2 * sizeof(int))
+ printk(KERN_WARNING "Can't get bus-range for %s, assume"
+ " bus 0\n", dev->full_name);
+
+ pci_assign_all_buses = 1;
+ hose = pcibios_alloc_controller(dev);
+ if (!hose)
+ return -ENOMEM;
+
+ hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
+ PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
+
+ hose->first_busno = bus_range ? bus_range[0] : 0x0;
+ hose->last_busno = bus_range ? bus_range[1] : 0xff;
+
+ setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
+
+ /* Probe the hose link training status */
+ early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
+ if (val < PCIE_LTSSM_L0)
+ return -ENXIO;
+
+ /* Setup the PCIE host controller. */
+ mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
+
+ if ((rsrc.start & 0xfffff) == 0x8000)
+ primary = 1;
+
+ printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
+ "Firmware bus number: %d->%d\n",
+ (unsigned long) rsrc.start,
+ hose->first_busno, hose->last_busno);
+
+ DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
+ hose, hose->cfg_addr, hose->cfg_data);
+
+ /* Interpret the "ranges" property */
+ /* This also maps the I/O region and sets isa_io/mem_base */
+ pci_process_bridge_OF_ranges(hose, dev, primary);
+
+ /* Setup PEX window registers */
+ setup_pcie_atmu(hose, &rsrc);
+
+ return 0;
+}
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
new file mode 100644
index 0000000..8d9779c
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -0,0 +1,94 @@
+/*
+ * MPC85xx/86xx PCI Express structure define
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __POWERPC_FSL_PCIE_H
+#define __POWERPC_FSL_PCIE_H
+
+/* PCIE Express IO block registers in 85xx/86xx */
+
+struct ccsr_pex {
+ __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
+ __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
+ u8 __iomem res1[4];
+ __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
+ __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
+ u8 __iomem res2[12];
+ __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
+ __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
+ __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
+ __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */
+ u8 __iomem res3[3024];
+ __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
+ __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
+ u8 __iomem res4[8];
+ __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
+ u8 __iomem res5[12];
+ __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
+ __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
+ __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
+ u8 __iomem res6[4];
+ __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
+ u8 __iomem res7[12];
+ __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
+ __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
+ __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
+ u8 __iomem res8[4];
+ __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
+ u8 __iomem res9[12];
+ __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
+ __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
+ __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
+ u8 __iomem res10[4];
+ __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
+ u8 __iomem res11[12];
+ __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
+ __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
+ __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
+ u8 __iomem res12[4];
+ __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
+ u8 __iomem res13[12];
+ u8 __iomem res14[256];
+ __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
+ u8 __iomem res15[4];
+ __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
+ __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
+ __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
+ u8 __iomem res16[12];
+ __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
+ u8 __iomem res17[4];
+ __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
+ __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
+ __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
+ u8 __iomem res18[12];
+ __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
+ u8 __iomem res19[4];
+ __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
+ __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
+ __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
+ u8 __iomem res20[12];
+ __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */
+ u8 __iomem res21[4];
+ __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
+ u8 __iomem res22[4];
+ __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */
+ u8 __iomem res23[12];
+ __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
+ u8 __iomem res24[4];
+ __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
+ __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
+ __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
+ __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
+};
+
+#endif /* __POWERPC_FSL_PCIE_H */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/sysdev/fsl_pcie.h b/arch/powerpc/sysdev/fsl_pcie.h
deleted file mode 100644
index 8d9779c..0000000
--- a/arch/powerpc/sysdev/fsl_pcie.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * MPC85xx/86xx PCI Express structure define
- *
- * Copyright 2007 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __POWERPC_FSL_PCIE_H
-#define __POWERPC_FSL_PCIE_H
-
-/* PCIE Express IO block registers in 85xx/86xx */
-
-struct ccsr_pex {
- __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
- __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
- u8 __iomem res1[4];
- __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
- __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
- u8 __iomem res2[12];
- __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
- __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
- __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
- __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */
- u8 __iomem res3[3024];
- __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
- __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
- u8 __iomem res4[8];
- __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
- u8 __iomem res5[12];
- __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
- __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
- __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
- u8 __iomem res6[4];
- __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
- u8 __iomem res7[12];
- __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
- __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
- __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
- u8 __iomem res8[4];
- __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
- u8 __iomem res9[12];
- __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
- __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
- __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
- u8 __iomem res10[4];
- __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
- u8 __iomem res11[12];
- __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
- __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
- __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
- u8 __iomem res12[4];
- __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
- u8 __iomem res13[12];
- u8 __iomem res14[256];
- __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
- u8 __iomem res15[4];
- __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
- __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
- __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
- u8 __iomem res16[12];
- __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
- u8 __iomem res17[4];
- __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
- __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
- __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
- u8 __iomem res18[12];
- __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
- u8 __iomem res19[4];
- __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
- __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
- __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
- u8 __iomem res20[12];
- __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */
- u8 __iomem res21[4];
- __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
- u8 __iomem res22[4];
- __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */
- u8 __iomem res23[12];
- __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
- u8 __iomem res24[4];
- __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
-};
-
-#endif /* __POWERPC_FSL_PCIE_H */
-#endif /* __KERNEL__ */
--
1.5.1
^ permalink raw reply related
* [patch 2/6] Rewrite Freescale pci/pcie routing for 85xx/86xx pci/pcie controller
From: Zang Roy-r61911 @ 2007-07-10 15:51 UTC (permalink / raw)
To: Kumar Gala, Paul Mackerras; +Cc: linuxppc-dev list
From: Roy Zang <tie-fei.zang@freescale.com>
Rewrite Freescale pci/pcie routing for 83xx/85xx/86xx pci/pcie
controller.
The routing are common for 83xx/85xx/86xx pci/pcie host.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/sysdev/fsl_pci.c | 244 ++++++++++++++++++-----------------------
arch/powerpc/sysdev/fsl_pci.h | 143 +++++++++++-------------
2 files changed, 172 insertions(+), 215 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 24ba1b6..5e15cfc 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1,136 +1,98 @@
/*
- * MPC86XX pci setup code
+ * MPC85xx/86xx PCI/PCIE support routing.
*
- * Recode: ZHANG WEI <wei.zhang@freescale.com>
- * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ * Copyright 2007 Freescale Semiconductor, Inc
*
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Rewrite the routing for Frescale PCI and PCI Express
+ * Roy Zang <tie-fei.zang@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/init.h>
+#include <linux/kernel.h>
#include <linux/pci.h>
-#include <linux/serial.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
-#include <asm/system.h>
-#include <asm/atomic.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
-#include "../platforms/86xx/mpc86xx.h"
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
-#else
-#define DBG(fmt, args...)
-#endif
-
-struct pcie_outbound_window_regs {
- uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
- uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
- uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
- char res1[4];
- uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
- char res2[12];
-};
-
-struct pcie_inbound_window_regs {
- uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
- char res1[4];
- uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
- uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
- uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
- char res2[12];
-};
-
-static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
+/* atmu setup for fsl pci/pcie controller */
+void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
{
- volatile struct ccsr_pex *pcie;
- volatile struct pcie_outbound_window_regs *pcieow;
- volatile struct pcie_inbound_window_regs *pcieiw;
- int i = 0;
+ struct ccsr_pci __iomem *pci;
+ int i;
- DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
+ pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start,
rsrc->end - rsrc->start + 1);
- pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
-
- /* Disable all windows (except pexowar0 since its ignored) */
- pcie->pexowar1 = 0;
- pcie->pexowar2 = 0;
- pcie->pexowar3 = 0;
- pcie->pexowar4 = 0;
- pcie->pexiwar1 = 0;
- pcie->pexiwar2 = 0;
- pcie->pexiwar3 = 0;
-
- pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
- pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
-
- /* Setup outbound MEM window */
- for(i = 0; i < 3; i++)
- if (hose->mem_resources[i].flags & IORESOURCE_MEM){
- DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
- hose->mem_resources[i].start,
- hose->mem_resources[i].end
- - hose->mem_resources[i].start + 1);
- pcieow->pexotar = (hose->mem_resources[i].start) >> 12
- & 0x000fffff;
- pcieow->pexotear = 0;
- pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
- & 0x000fffff;
- /* Enable, Mem R/W */
- pcieow->pexowar = 0x80044000 |
- (__ilog2(hose->mem_resources[i].end
- - hose->mem_resources[i].start + 1)
- - 1);
- pcieow++;
- }
-
- /* Setup outbound IO window */
- if (hose->io_resource.flags & IORESOURCE_IO){
- DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
- hose->io_resource.start,
- hose->io_resource.end - hose->io_resource.start + 1,
- hose->io_base_phys);
- pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
- pcieow->pexotear = 0;
- pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
- /* Enable, IO R/W */
- pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
- - hose->io_resource.start + 1) - 1);
- }
-
- /* Setup 2G inbound Memory Window @ 0 */
- pcieiw->pexitar = 0x00000000;
- pcieiw->pexiwbar = 0x00000000;
- /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
- pcieiw->pexiwar = 0xa0f5501e;
+ pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
+
+ /* Disable all windows (except powar0 since its ignored) */
+ for(i = 1; i < 5; i++)
+ out_be32(&pci->pow[i].powar, 0);
+ for(i = 0; i < 3; i++)
+ out_be32(&pci->piw[i].piwar, 0);
+
+ /* Setup outbound MEM window */
+ for(i = 0; i < 3; i++)
+ if (hose->mem_resources[i].flags & IORESOURCE_MEM){
+ pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
+ hose->mem_resources[i].start,
+ hose->mem_resources[i].end
+ - hose->mem_resources[i].start + 1);
+ out_be32(&pci->pow[i+1].potar,
+ (hose->mem_resources[i].start >> 12)
+ & 0x000fffff);
+ out_be32(&pci->pow[i+1].potear, 0);
+ out_be32(&pci->pow[i+1].powbar,
+ (hose->mem_resources[i].start >> 12)
+ & 0x000fffff);
+ /* Enable, Mem R/W */
+ out_be32(&pci->pow[i+1].powar, 0x80044000
+ | (__ilog2(hose->mem_resources[i].end
+ - hose->mem_resources[i].start + 1) - 1));
+ }
+
+ /* Setup outbound IO window */
+ if (hose->io_resource.flags & IORESOURCE_IO){
+ pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
+ hose->io_resource.start,
+ hose->io_resource.end - hose->io_resource.start + 1,
+ hose->io_base_phys);
+ out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)
+ & 0x000fffff);
+ out_be32(&pci->pow[i+1].potear, 0);
+ out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)
+ & 0x000fffff);
+ /* Enable, IO R/W */
+ out_be32(&pci->pow[i+1].powar, 0x80088000
+ | (__ilog2(hose->io_resource.end
+ - hose->io_resource.start + 1) - 1));
+ }
+
+ /* Setup 2G inbound Memory Window @ 1 */
+ out_be32(&pci->piw[2].pitar, 0x00000000);
+ out_be32(&pci->piw[2].piwbar,0x00000000);
+ out_be32(&pci->piw[2].piwar, PIWAR_2G);
}
-static void __init
-mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
+void __init setup_pci_cmd(struct pci_controller *hose)
{
u16 cmd;
-
- DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
- pcie_offset, pcie_size);
-
early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
- | PCI_COMMAND_IO;
+ | PCI_COMMAND_IO;
early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
-
early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
}
@@ -167,72 +129,76 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
}
}
+int __init fsl_pcie_check_link(struct pci_controller *hose)
+{
+ u16 val;
+ early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
+ if (val < PCIE_LTSSM_L0)
+ return 1;
+ return 0;
+}
-DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
-DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
-
-#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
-#define PCIE_LTSSM_L0 0x16 /* L0 state */
-
-int __init mpc86xx_add_bridge(struct device_node *dev)
+int __init fsl_add_bridge(struct device_node *dev, int is_primary)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
- int has_address = 0;
- int primary = 0;
- u16 val;
- DBG("Adding PCIE host bridge %s\n", dev->full_name);
+ pr_debug("Adding PCI host bridge %s\n", dev->full_name);
/* Fetch host bridge registers address */
- has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
+ if (of_address_to_resource(dev, 0, &rsrc)) {
+ printk(KERN_WARNING "Can't get pci register base!");
+ return -ENOMEM;
+ }
/* Get bus range if any */
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int))
printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
+ " bus 0\n", dev->full_name);
pci_assign_all_buses = 1;
hose = pcibios_alloc_controller(dev);
if (!hose)
return -ENOMEM;
- hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
- PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
-
hose->first_busno = bus_range ? bus_range[0] : 0x0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
- setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
-
- /* Probe the hose link training status */
- early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
- if (val < PCIE_LTSSM_L0)
- return -ENXIO;
+ /* check PCI express bridge */
+ if (of_device_is_compatible(dev, "fsl,mpc85xx-pciex") ||
+ of_device_is_compatible(dev, "fsl,mpc86xx-pciex"))
+ hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
+ PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
- /* Setup the PCIE host controller. */
- mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
+ setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
+ setup_pci_cmd(hose);
- if ((rsrc.start & 0xfffff) == 0x8000)
- primary = 1;
+ /* check PCI express link status */
+ if (of_device_is_compatible(dev, "fsl,mpc85xx-pciex") ||
+ of_device_is_compatible(dev, "fsl,mpc86xx-pciex"))
+ if (fsl_pcie_check_link(hose))
+ return -ENXIO;
- printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long) rsrc.start,
- hose->first_busno, hose->last_busno);
+ printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx."
+ "Firmware bus number: %d->%d\n",
+ (unsigned long long)rsrc.start, hose->first_busno,
+ hose->last_busno);
- DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
+ pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
hose, hose->cfg_addr, hose->cfg_data);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, primary);
+ pci_process_bridge_OF_ranges(hose, dev, is_primary);
/* Setup PEX window registers */
- setup_pcie_atmu(hose, &rsrc);
+ setup_pci_atmu(hose, &rsrc);
return 0;
}
+
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index 8d9779c..91f94de 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -11,84 +11,75 @@
*/
#ifdef __KERNEL__
-#ifndef __POWERPC_FSL_PCIE_H
-#define __POWERPC_FSL_PCIE_H
+#ifndef __POWERPC_FSL_PCI_H
+#define __POWERPC_FSL_PCI_H
-/* PCIE Express IO block registers in 85xx/86xx */
+#define PCIE_LTSSM 0x04000004 /* PCIE Link Training and Status */
+#define PCIE_LTSSM_L0 0x16 /* L0 state */
+#define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
-struct ccsr_pex {
- __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
- __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
- u8 __iomem res1[4];
- __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
- __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
- u8 __iomem res2[12];
- __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
- __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
- __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
- __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */
- u8 __iomem res3[3024];
- __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
- __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
- u8 __iomem res4[8];
- __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
- u8 __iomem res5[12];
- __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
- __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
- __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
- u8 __iomem res6[4];
- __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
- u8 __iomem res7[12];
- __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
- __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
- __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
- u8 __iomem res8[4];
- __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
- u8 __iomem res9[12];
- __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
- __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
- __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
- u8 __iomem res10[4];
- __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
- u8 __iomem res11[12];
- __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
- __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
- __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
- u8 __iomem res12[4];
- __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
- u8 __iomem res13[12];
- u8 __iomem res14[256];
- __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
- u8 __iomem res15[4];
- __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
- __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
- __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
- u8 __iomem res16[12];
- __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
- u8 __iomem res17[4];
- __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
- __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
- __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
- u8 __iomem res18[12];
- __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
- u8 __iomem res19[4];
- __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
- __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
- __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
- u8 __iomem res20[12];
- __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */
- u8 __iomem res21[4];
- __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
- u8 __iomem res22[4];
- __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */
- u8 __iomem res23[12];
- __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
- u8 __iomem res24[4];
- __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
+/* PCI/PCI Express outbound window reg */
+struct pci_outbound_window_regs {
+ __be32 potar; /* 0x.0 - Outbound translation address register */
+ __be32 potear; /* 0x.4 - Outbound translation extended address register */
+ __be32 powbar; /* 0x.8 - Outbound window base address register */
+ u8 res1[4];
+ __be32 powar; /* 0x.10 - Outbound window attributes register */
+ u8 res2[12];
};
-#endif /* __POWERPC_FSL_PCIE_H */
+/* PCI/PCI Express inbound window reg */
+struct pci_inbound_window_regs {
+ __be32 pitar; /* 0x.0 - Inbound translation address register */
+ u8 res1[4];
+ __be32 piwbar; /* 0x.8 - Inbound window base address register */
+ __be32 piwbear; /* 0x.c - Inbound window base extended address register */
+ __be32 piwar; /* 0x.10 - Inbound window attributes register */
+ u8 res2[12];
+};
+
+/* PCI/PCI Express IO block registers for 85xx/86xx */
+struct ccsr_pci {
+ __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
+ __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
+ __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
+ __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
+ __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
+ u8 res2[12];
+ __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
+ __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
+ __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
+ __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
+ u8 res3[3024];
+/* PCI/PCI Express outbound window 0-4
+ * Window 0 is the default window and is the only window enabled upon reset.
+ * The default outbound register set is used when a transaction misses
+ * in all of the other outbound windows.
+ */
+ struct pci_outbound_window_regs pow[5];
+
+ u8 res14[256];
+
+/* PCI/PCI Express inbound window 3-1
+ * inbound window 1 supports only a 32-bit base address and does not
+ * define an inbound window base extended address register.
+ */
+ struct pci_inbound_window_regs piw[3];
+
+ __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
+ u8 res21[4];
+ __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
+ u8 res22[4];
+ __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
+ u8 res23[12];
+ __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
+ u8 res24[4];
+ __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
+ __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
+ __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
+ __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
+};
+
+int __init fsl_add_bridge(struct device_node *dev, int is_primary);
+#endif /* __POWERPC_FSL_PCI_H */
#endif /* __KERNEL__ */
--
1.5.1
^ permalink raw reply related
* Re: xilinx gpio in kernel 2.6
From: Mirek23 @ 2007-07-10 15:52 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <10285090.post@talk.nabble.com>
Hi All,
After some time I have found the way how to deal with GPIO driver from the
user space:
First you have to mknod xgpio under /dev :
crw-rw-rw- 1 root root 10, 185 Jun 1 13:59 /dev/xgpio
Example program below shows how to read from the GPIO channel.
To write to the channel change the call:
ioctl(fgpio,XGPIO_IN,&sGpioData); to ioctl(fgpio,XGPIO_OUT,&sGpioData);
#include <stdlib.h>
#include <stdio.h>
#include <sys/ioctl.h>
#include <fcntl.h>
#include <linux/xgpio_ioctl.h>
main(){
int fgpio =0;
struct xgpio_ioctl_data sGpioData;
/* {
__u32 device;
__u32 mask;
__u32 data;
}*/
sGpioData.device=0; /* N=0,1,2,3-> GPIO DEV NR 2*N (Lower 32 bit part
)
2*N+1 (Upper 32 bit part
)*/
sGpioData.mask=0xffffffff;
sGpioData.data=0x55555555;
fgpio = open ("/dev/xgpio",O_RDWR);
if( fgpio != -1){
ioctl(fgpio,XGPIO_IN,&sGpioData);//pointer here to xgpio_ioctl_data
printf("Dip Swich readout 0x%X\n",sGpioData.data);
}
else
printf("Can not open GPIO\n");
close(fgpio);
}// end main
--
View this message in context: http://www.nabble.com/xilinx-gpio-in-kernel-2.6-tf3670122.html#a11523745
Sent from the linuxppc-embedded mailing list archive at Nabble.com.
^ permalink raw reply
* [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node
From: Zang Roy-r61911 @ 2007-07-10 15:52 UTC (permalink / raw)
To: Kumar Gala, Paul Mackerras; +Cc: linuxppc-dev list
From: Roy Zang <tie-fei.zang@freescale.com>
Add 8548 CDS PCI express controller node and PCI-X device node.
The current dts file is suitable for 8548 Rev 2.0 board with
Arcadia 3.1.
This kind of board combination is the most popular.
Indentify pci, pcie host by compatible property "fsl,mpc85xx-pci"
and "fsl, mpc85xx-pciex".
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/boot/dts/mpc8548cds.dts | 156 +++++++++++++++++++++++-----------
1 files changed, 105 insertions(+), 51 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 9d0b84b..d60821b 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,5 +1,5 @@
/*
- * MPC8555 CDS Device Tree Source
+ * MPC8548 CDS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
*
@@ -186,67 +186,96 @@
pci1: pci@8000 {
interrupt-map-mask = <1f800 0 0 7>;
interrupt-map = <
+ /* IDSEL 0x4 (PCIX Slot 2) */
+ 02000 0 0 1 &mpic 0 1
+ 02000 0 0 2 &mpic 1 1
+ 02000 0 0 3 &mpic 2 1
+ 02000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x5 (PCIX Slot 3) */
+ 02800 0 0 1 &mpic 1 1
+ 02800 0 0 2 &mpic 2 1
+ 02800 0 0 3 &mpic 3 1
+ 02800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x6 (PCIX Slot 4) */
+ 03000 0 0 1 &mpic 2 1
+ 03000 0 0 2 &mpic 3 1
+ 03000 0 0 3 &mpic 0 1
+ 03000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x8 (PCIX Slot 5) */
+ 04000 0 0 1 &mpic 0 1
+ 04000 0 0 2 &mpic 1 1
+ 04000 0 0 3 &mpic 2 1
+ 04000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0xC (Tsi310 bridge) */
+ 06000 0 0 1 &mpic 0 1
+ 06000 0 0 2 &mpic 1 1
+ 06000 0 0 3 &mpic 2 1
+ 06000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x14 (Slot 2) */
+ 0a000 0 0 1 &mpic 0 1
+ 0a000 0 0 2 &mpic 1 1
+ 0a000 0 0 3 &mpic 2 1
+ 0a000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x15 (Slot 3) */
+ 0a800 0 0 1 &mpic 1 1
+ 0a800 0 0 2 &mpic 2 1
+ 0a800 0 0 3 &mpic 3 1
+ 0a800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x16 (Slot 4) */
+ 0b000 0 0 1 &mpic 2 1
+ 0b000 0 0 2 &mpic 3 1
+ 0b000 0 0 3 &mpic 0 1
+ 0b000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x18 (Slot 5) */
+ 0c000 0 0 1 &mpic 0 1
+ 0c000 0 0 2 &mpic 1 1
+ 0c000 0 0 3 &mpic 2 1
+ 0c000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
+ 0E000 0 0 1 &mpic 0 1
+ 0E000 0 0 2 &mpic 1 1
+ 0E000 0 0 3 &mpic 2 1
+ 0E000 0 0 4 &mpic 3 1
+
+ /* bus 1 , idsel 0x2 Tsi310 bridge secondary */
+ 11000 0 0 1 &mpic 2 1
+ 11000 0 0 2 &mpic 3 1
+ 11000 0 0 3 &mpic 0 1
+ 11000 0 0 4 &mpic 1 1
+
+ /* VIA chip */
+ 12000 0 0 1 &mpic 0 1
+ 12000 0 0 2 &mpic 1 1
+ 12000 0 0 3 &mpic 2 1
+ 12000 0 0 4 &mpic 3 1>;
- /* IDSEL 0x10 */
- 08000 0 0 1 &mpic 0 1
- 08000 0 0 2 &mpic 1 1
- 08000 0 0 3 &mpic 2 1
- 08000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x11 */
- 08800 0 0 1 &mpic 0 1
- 08800 0 0 2 &mpic 1 1
- 08800 0 0 3 &mpic 2 1
- 08800 0 0 4 &mpic 3 1
-
- /* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 &mpic 0 1
- 09000 0 0 2 &mpic 1 1
- 09000 0 0 3 &mpic 2 1
- 09000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 &mpic 1 1
- 09800 0 0 2 &mpic 2 1
- 09800 0 0 3 &mpic 3 1
- 09800 0 0 4 &mpic 0 1
-
- /* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 &mpic 2 1
- 0a000 0 0 2 &mpic 3 1
- 0a000 0 0 3 &mpic 0 1
- 0a000 0 0 4 &mpic 1 1
-
- /* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 &mpic 3 1
- 0a800 0 0 2 &mpic 0 1
- 0a800 0 0 3 &mpic 1 1
- 0a800 0 0 4 &mpic 2 1
-
- /* Bus 1 (Tundra Bridge) */
- /* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 &mpic 0 1
- 19000 0 0 2 &mpic 1 1
- 19000 0 0 3 &mpic 2 1
- 19000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
+ ranges = <02000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
- compatible = "85xx";
+ compatible = "fsl,mpc85xx-pci","85xx";
device_type = "pci";
- i8259@19000 {
+ i8259@4 {
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
- reg = <19000 0 0 0 1>;
+ reg = <12000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
@@ -266,17 +295,42 @@
a800 0 0 2 &mpic b 1
a800 0 0 3 &mpic b 1
a800 0 0 4 &mpic b 1>;
+
interrupt-parent = <&mpic>;
interrupts = <19 2>;
bus-range = <0 0>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 00100000>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 01000000 0 00000000 e2800000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <9000 1000>;
- compatible = "85xx";
+ compatible = "fsl,mpc85xx-pci","85xx";
+ device_type = "pci";
+ };
+ /* PCI Express */
+ pci@a000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x0 (PEX) */
+ 00000 0 0 1 &mpic 0 1
+ 00000 0 0 2 &mpic 1 0
+ 00000 0 0 3 &mpic 2 0
+ 00000 0 0 4 &mpic 3 0>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <1a 2>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 08000000>;
+ clock-frequency = <1fca055>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <a000 1000>;
+ compatible = "fsl,mpc86xx-pciex","86xx";
device_type = "pci";
};
--
1.5.1
^ permalink raw reply related
* [patch 4/6] User Freescale pci/pcie common routing for 83xx/85xx/86xx boards
From: Zang Roy-r61911 @ 2007-07-10 15:52 UTC (permalink / raw)
To: Kumar Gala, Paul Mackerras; +Cc: linuxppc-dev list
From: Roy Zang <tie-fei.zang@freescale.com>
User Freescale pci/pcie common routing for 83xx/85xx/86xx
boards.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/platforms/83xx/Kconfig | 4 +
arch/powerpc/platforms/83xx/mpc8313_rdb.c | 2 +-
arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 +-
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 2 +-
arch/powerpc/platforms/83xx/mpc834x_itx.c | 11 +++-
arch/powerpc/platforms/83xx/mpc834x_mds.c | 11 +++-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
arch/powerpc/platforms/83xx/mpc83xx.h | 2 +-
arch/powerpc/platforms/83xx/pci.c | 57 -----------------
arch/powerpc/platforms/85xx/Kconfig | 1 +
arch/powerpc/platforms/85xx/Makefile | 2 +-
arch/powerpc/platforms/85xx/mpc85xx.h | 1 -
arch/powerpc/platforms/85xx/mpc85xx_ads.c | 3 +-
arch/powerpc/platforms/85xx/mpc85xx_cds.c | 14 +++--
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 6 +-
arch/powerpc/platforms/85xx/pci.c | 91 ----------------------------
arch/powerpc/platforms/86xx/mpc86xx.h | 2 -
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 11 +++-
19 files changed, 51 insertions(+), 175 deletions(-)
delete mode 100644 arch/powerpc/platforms/85xx/pci.c
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 8c780bf..20f7a34 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -421,7 +421,7 @@ config FSL_SOC
config FSL_PCI
bool
- depends on PPC_86xx
+ depends on PPC_85xx || PPC_86xx || PPC_83xx
# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
config MCA
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index ec305f1..d60a431 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -55,23 +55,27 @@ endchoice
config PPC_MPC831x
bool
select PPC_UDBG_16550
+ select FSL_PCI
select PPC_INDIRECT_PCI
default y if MPC8313_RDB
config PPC_MPC832x
bool
select PPC_UDBG_16550
+ select FSL_PCI
select PPC_INDIRECT_PCI
default y if MPC832x_MDS || MPC832x_RDB
config MPC834x
bool
select PPC_UDBG_16550
+ select FSL_PCI
select PPC_INDIRECT_PCI
default y if MPC834x_MDS || MPC834x_ITX
config PPC_MPC836x
bool
select PPC_UDBG_16550
+ select FSL_PCI
select PPC_INDIRECT_PCI
default y if MPC836x_MDS
diff --git a/arch/powerpc/platforms/83xx/mpc8313_rdb.c b/arch/powerpc/platforms/83xx/mpc8313_rdb.c
index 3edfe17..41f4988 100644
--- a/arch/powerpc/platforms/83xx/mpc8313_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc8313_rdb.c
@@ -44,7 +44,7 @@ static void __init mpc8313_rdb_setup_arch(void)
#ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc83xx_add_bridge(np);
+ fsl_add_bridge(np, 1);
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
#endif
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index b39cb52..6ef2acf 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -75,7 +75,7 @@ static void __init mpc832x_sys_setup_arch(void)
#ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc83xx_add_bridge(np);
+ fsl_add_bridge(np, 1);
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
#endif
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index b2b28a4..0acc670 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -48,7 +48,7 @@ static void __init mpc832x_rdb_setup_arch(void)
#ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc83xx_add_bridge(np);
+ fsl_add_bridge(np, 1);
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
#endif
diff --git a/arch/powerpc/platforms/83xx/mpc834x_itx.c b/arch/powerpc/platforms/83xx/mpc834x_itx.c
index 47ba544..defde26 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_itx.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_itx.c
@@ -53,9 +53,14 @@ static void __init mpc834x_itx_setup_arch(void)
ppc_md.progress("mpc834x_itx_setup_arch()", 0);
#ifdef CONFIG_PCI
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc83xx_add_bridge(np);
-
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
+ struct resource rsrc;
+ of_address_to_resource(np, 0, &rsrc);
+ if ((rsrc.start & 0xfffff) == 0x8500)
+ fsl_add_bridge(np, 1);
+ else
+ fsl_add_bridge(np, 0);
+ }
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
#endif
diff --git a/arch/powerpc/platforms/83xx/mpc834x_mds.c b/arch/powerpc/platforms/83xx/mpc834x_mds.c
index 4c9ff9c..dbbf8b0 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_mds.c
@@ -84,9 +84,14 @@ static void __init mpc834x_mds_setup_arch(void)
ppc_md.progress("mpc834x_mds_setup_arch()", 0);
#ifdef CONFIG_PCI
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc83xx_add_bridge(np);
-
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
+ struct resource rsrc;
+ of_address_to_resource(np, 0, &rsrc);
+ if ((rsrc.start & 0xfffff) == 0x8500)
+ fsl_add_bridge(np, 1);
+ else
+ fsl_add_bridge(np, 0);
+ }
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
#endif
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 0e615fd..9f39941 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -81,7 +81,7 @@ static void __init mpc836x_mds_setup_arch(void)
#ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc83xx_add_bridge(np);
+ fsl_add_bridge(np, 1);
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
#endif
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 589ee55..dd1315e 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -48,7 +48,7 @@
* mpc83xx_* files. Mostly for use by mpc83xx_setup
*/
-extern int mpc83xx_add_bridge(struct device_node *dev);
+extern int fsl_add_bridge(struct device_node *dev, int is_primary);
extern int mpc83xx_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn);
extern void mpc83xx_restart(char *cmd);
diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/platforms/83xx/pci.c
index c0e2b89..1fae915 100644
--- a/arch/powerpc/platforms/83xx/pci.c
+++ b/arch/powerpc/platforms/83xx/pci.c
@@ -39,60 +39,3 @@ int mpc83xx_exclude_device(struct pci_controller *hose, u_char bus, u_char devfn
return PCIBIOS_DEVICE_NOT_FOUND;
return PCIBIOS_SUCCESSFUL;
}
-
-int __init mpc83xx_add_bridge(struct device_node *dev)
-{
- int len;
- struct pci_controller *hose;
- struct resource rsrc;
- const int *bus_range;
- int primary = 1, has_address = 0;
- phys_addr_t immr = get_immrbase();
-
- DBG("Adding PCI host bridge %s\n", dev->full_name);
-
- /* Fetch host bridge registers address */
- has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
-
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int)) {
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
- }
-
- pci_assign_all_buses = 1;
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
-
- hose->first_busno = bus_range ? bus_range[0] : 0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
-
- /* MPC83xx supports up to two host controllers one at 0x8500 from immrbar
- * the other at 0x8600, we consider the 0x8500 the primary controller
- */
- /* PCI 1 */
- if ((rsrc.start & 0xfffff) == 0x8500) {
- setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304);
- }
- /* PCI 2 */
- if ((rsrc.start & 0xfffff) == 0x8600) {
- setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384);
- primary = 0;
- }
-
- printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long long)rsrc.start, hose->first_busno,
- hose->last_busno);
-
- DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, primary);
-
- return 0;
-}
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 629926e..112e5c6 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -53,6 +53,7 @@ config MPC85xx
select PPC_INDIRECT_PCI
select PPC_INDIRECT_PCI_BE
select MPIC
+ select FSL_PCI
select SERIAL_8250_SHARE_IRQ if SERIAL_8250
default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \
|| MPC85xx_MDS || MPC8544_DS
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 4e02cbb..d70f2d0 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -1,7 +1,7 @@
#
# Makefile for the PowerPC 85xx linux kernel.
#
-obj-$(CONFIG_PPC_85xx) += misc.o pci.o
+obj-$(CONFIG_PPC_85xx) += misc.o
obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
index 7286ffa..5b34dee 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -15,4 +15,3 @@
*/
extern void mpc85xx_restart(char *);
-extern int mpc85xx_add_bridge(struct device_node *dev);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 7235f70..40a8286 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -29,6 +29,7 @@
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
#include "mpc85xx.h"
#ifdef CONFIG_CPM2
@@ -217,7 +218,7 @@ static void __init mpc85xx_ads_setup_arch(void)
#ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc85xx_add_bridge(np);
+ fsl_add_bridge(np, 1);
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif
}
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 50c8d64..2539bb5 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -45,6 +45,7 @@
#include <asm/i8259.h>
#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
#include "mpc85xx.h"
static int cds_pci_slot = 2;
@@ -58,8 +59,6 @@ static volatile u8 *cadmus;
static int mpc85xx_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn)
{
- if ((bus == hose->first_busno) && PCI_SLOT(devfn) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
/* We explicitly do not go past the Tundra 320 Bridge */
if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -218,9 +217,14 @@ static void __init mpc85xx_cds_setup_arch(void)
}
#ifdef CONFIG_PCI
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc85xx_add_bridge(np);
-
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
+ struct resource rsrc;
+ of_address_to_resource(np, 0, &rsrc);
+ if ((rsrc.start & 0xfffff) == 0x9000)
+ fsl_add_bridge(np, 0);
+ else
+ fsl_add_bridge(np, 1);
+ }
ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 004b80b..9aa96f0 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -46,6 +46,7 @@
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
#include <asm/qe.h>
#include <asm/qe_ic.h>
#include <asm/mpic.h>
@@ -94,9 +95,8 @@ static void __init mpc85xx_mds_setup_arch(void)
}
#ifdef CONFIG_PCI
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
- mpc85xx_add_bridge(np);
- }
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+ fsl_add_bridge(np, 1);
of_node_put(np);
#endif
diff --git a/arch/powerpc/platforms/85xx/pci.c b/arch/powerpc/platforms/85xx/pci.c
deleted file mode 100644
index 8118417..0000000
--- a/arch/powerpc/platforms/85xx/pci.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * FSL SoC setup code
- *
- * Maintained by Kumar Gala (see MAINTAINERS for contact information)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/module.h>
-
-#include <asm/system.h>
-#include <asm/atomic.h>
-#include <asm/io.h>
-#include <asm/pci-bridge.h>
-#include <asm/prom.h>
-#include <sysdev/fsl_soc.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-#ifdef CONFIG_PCI
-int __init mpc85xx_add_bridge(struct device_node *dev)
-{
- int len;
- struct pci_controller *hose;
- struct resource rsrc;
- const int *bus_range;
- int primary = 1, has_address = 0;
- phys_addr_t immr = get_immrbase();
-
- DBG("Adding PCI host bridge %s\n", dev->full_name);
-
- /* Fetch host bridge registers address */
- has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
-
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int)) {
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
- }
-
- pci_assign_all_buses = 1;
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
-
- hose->first_busno = bus_range ? bus_range[0] : 0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
-
- /* PCI 1 */
- if ((rsrc.start & 0xfffff) == 0x8000) {
- setup_indirect_pci(hose, immr + 0x8000, immr + 0x8004);
- }
- /* PCI 2 */
- if ((rsrc.start & 0xfffff) == 0x9000) {
- setup_indirect_pci(hose, immr + 0x9000, immr + 0x9004);
- primary = 0;
- }
-
- printk(KERN_INFO "Found MPC85xx PCI host bridge at 0x%016llx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long long)rsrc.start, hose->first_busno,
- hose->last_busno);
-
- DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, primary);
-
- return 0;
-}
-
-#endif
diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h b/arch/powerpc/platforms/86xx/mpc86xx.h
index 23f7ed2..fdb192b 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx.h
+++ b/arch/powerpc/platforms/86xx/mpc86xx.h
@@ -15,8 +15,6 @@
* mpc86xx_* files. Mostly for use by mpc86xx_setup().
*/
-extern int mpc86xx_add_bridge(struct device_node *dev);
-
extern int mpc86xx_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn);
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 5b01ec7..dab016e 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -32,6 +32,7 @@
#include <asm/mpic.h>
#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
#include "mpc86xx.h"
#include "mpc8641_hpcn.h"
@@ -344,8 +345,14 @@ mpc86xx_hpcn_setup_arch(void)
}
#ifdef CONFIG_PCI
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc86xx_add_bridge(np);
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
+ struct resource rsrc;
+ of_address_to_resource(np, 0, &rsrc);
+ if ((rsrc.start & 0xfffff) == 0x8000)
+ fsl_add_bridge(np, 1);
+ else
+ fsl_add_bridge(np, 0);
+ }
#endif
printk("MPC86xx HPCN board from Freescale Semiconductor\n");
--
1.5.1
^ permalink raw reply related
* [patch 5/6] Update the 83xx/85xx/86xx boards device tree
From: Zang Roy-r61911 @ 2007-07-10 15:53 UTC (permalink / raw)
To: Paul Mackerras, Kumar Gala; +Cc: linuxppc-dev list
From: Roy Zang <tie-fei.zang@freescale.com>
Update the 83xx/85xx/86xx boards device tree.
Indentify pci, pcie host by compatible property
"fsl,mpc83xx-pci","83xx"
"fsl,mpc85xx-pci","85xx"
"fsl,mpc86xx-pci","86xx"
and
"fsl, mpc85xx-pciex","85xx"
"fsl, mpc86xx-pciex","86xx"
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/boot/dts/mpc8313erdb.dts | 2 +-
arch/powerpc/boot/dts/mpc832x_mds.dts | 2 +-
arch/powerpc/boot/dts/mpc832x_rdb.dts | 2 +-
arch/powerpc/boot/dts/mpc8349emitx.dts | 4 ++--
arch/powerpc/boot/dts/mpc8349emitxgp.dts | 2 +-
arch/powerpc/boot/dts/mpc834x_mds.dts | 4 ++--
arch/powerpc/boot/dts/mpc836x_mds.dts | 2 +-
arch/powerpc/boot/dts/mpc8540ads.dts | 2 +-
arch/powerpc/boot/dts/mpc8541cds.dts | 4 ++--
arch/powerpc/boot/dts/mpc8555cds.dts | 4 ++--
arch/powerpc/boot/dts/mpc8560ads.dts | 2 +-
arch/powerpc/boot/dts/mpc8641_hpcn.dts | 4 ++--
12 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index a1533cc..5276843 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -178,7 +178,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
- compatible = "83xx";
+ compatible = "fsl,mpc83xx-pci","83xx";
device_type = "pci";
};
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 4fc0c4d..ee8897b 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -154,7 +154,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
- compatible = "83xx";
+ compatible = "fsl,mpc83xx-pci","83xx";
device_type = "pci";
};
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 447c03f..d83469b 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -123,7 +123,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
- compatible = "83xx";
+ compatible = "fsl,mpc83xx-pci","83xx";
device_type = "pci";
};
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index ae9bca5..911984b 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -197,7 +197,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
- compatible = "83xx";
+ compatible = "fsl,mpc83xx-pci","83xx";
device_type = "pci";
};
@@ -222,7 +222,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8600 100>;
- compatible = "83xx";
+ compatible = "fsl,mpc83xx-pci","83xx";
device_type = "pci";
};
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index f636528..8790349 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -154,7 +154,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8600 100>;
- compatible = "83xx";
+ compatible = "fsl,mpc83xx-pci","83xx";
device_type = "pci";
};
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 310e877..dc4d97d 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -241,7 +241,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
- compatible = "83xx";
+ compatible = "fsl,mpc83xx-pci","83xx";
device_type = "pci";
};
@@ -301,7 +301,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8600 100>;
- compatible = "83xx";
+ compatible = "fsl,mpc83xx-pci","83xx";
device_type = "pci";
};
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 1e914f3..2750eb1 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -169,7 +169,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
- compatible = "83xx";
+ compatible = "fsl,mpc83xx-pci","83xx";
device_type = "pci";
};
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 364a969..8efea9b 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -258,7 +258,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
- compatible = "85xx";
+ compatible = "fsl,mpc85xx-pci","85xx";
device_type = "pci";
};
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 070206f..be89d46 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -193,7 +193,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
- compatible = "85xx";
+ compatible = "fsl,mpc85xx-pci","85xx";
device_type = "pci";
i8259@19000 {
@@ -230,7 +230,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <9000 1000>;
- compatible = "85xx";
+ compatible = "fsl,mpc85xx-pci","85xx";
device_type = "pci";
};
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 17e45d9..0bee322 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -193,7 +193,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
- compatible = "85xx";
+ compatible = "fsl,mpc85xx-pci","85xx";
device_type = "pci";
i8259@19000 {
@@ -230,7 +230,7 @@
#size-cells = <2>;
#address-cells = <3>;
reg = <9000 1000>;
- compatible = "85xx";
+ compatible = "fsl,mpc85xx-pci","85xx";
device_type = "pci";
};
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 21ccaaa..d0627bd 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -136,7 +136,7 @@
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- compatible = "85xx";
+ compatible = "fsl,mpc85xx-pci","85xx";
device_type = "pci";
reg = <8000 1000>;
clock-frequency = <3f940aa>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index db56a02..2b36ae3 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -208,7 +208,7 @@
};
pci@8000 {
- compatible = "86xx";
+ compatible = "fsl,mpc86xx-pciex","86xx";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
@@ -396,7 +396,7 @@
};
pci@9000 {
- compatible = "86xx";
+ compatible = "fsl,mpc86xx-pciex","86xx";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
--
1.5.1
^ permalink raw reply related
* [patch 6/6] Add basic PCI node for mpc8568mds board
From: Zang Roy-r61911 @ 2007-07-10 15:53 UTC (permalink / raw)
To: Kumar Gala, Paul Mackerras; +Cc: linuxppc-dev list
From: Roy Zang <tie-fei.zang@freescale.com>
Add basic PCI node for mpc8568mds board.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/boot/dts/mpc8568mds.dts | 29 +++++++++++++++++++++++++++++
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 6bb18f2..c6cd1d6 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -170,6 +170,35 @@
interrupt-parent = <&mpic>;
};
+ pci@8000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x12 AD18 */
+ 9000 0 0 1 &mpic 5 1
+ 9000 0 0 2 &mpic 6 1
+ 9000 0 0 3 &mpic 7 1
+ 9000 0 0 4 &mpic 4 1
+
+ /* IDSEL 0x13 AD19 */
+ 9800 0 0 1 &mpic 6 1
+ 9800 0 0 2 &mpic 7 1
+ 9800 0 0 3 &mpic 4 1
+ 9800 0 0 4 &mpic 5 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00800000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <8000 1000>;
+ compatible = "fsl,mpc85xx-pci","85xx";
+ device_type = "pci";
+ };
+
serial@4600 {
device_type = "serial";
compatible = "ns16550";
--
1.5.1
^ permalink raw reply related
* Re: [PATCH 1/4] Add DMA sector to Documentation/powerpc/booting-without-of.txt file.
From: Scott Wood @ 2007-07-10 16:11 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev, paulus
In-Reply-To: <14A08601-B779-45BF-BC22-D1A3C9997502@kernel.crashing.org>
On Tue, Jul 10, 2007 at 04:01:19PM +0200, Segher Boessenkool wrote:
> > + - compatible : Should be "fsl,mpc8xxx-dma"
>
> Should _include_, not should _be_. And none of this xxx
> business, of course.
Especially since the 85xx/86xx version is not 100% compatible with the
83xx version. How about fsl,mpc8349-dma and fsl,mpc8548-dma for the two
variants?
> > + - extended : Set the DMA channel to work at extended chain mode.
> > + If not set, the DMA channel will work at basic
> > + chain mode.
>
> Call it "extended-chain-mode", perhaps?
Or don't call it anything. The ability to do extended chain mode is
implicit in being compatible with fsl,mpc8548-dma.
> > + - reserved : Reserve the DMA channel to device.
>
> What does this do? Reserve it for what device, and where?
> The OS driver?
Some hardware has DMA channels hardwired to certain peripherals, such as
an audio codec. This keeps them from being used as general purpose DMA
channels.
I'd rather just treat the different DMA channels as independent devices,
rather than children of a dma "bus", and change the compatible name if
they're not general purpose. There's only one register that's shared
among the channels, and it's a superfluous status summary register.
-Scott
^ permalink raw reply
* Re: [PATCH] Consolidate mm_context_t definition in mmu.h
From: Arnd Bergmann @ 2007-07-10 16:36 UTC (permalink / raw)
To: linuxppc-dev; +Cc: paulus, david
In-Reply-To: <1184079709.32199.6.camel@weaponx.rchland.ibm.com>
On Tuesday 10 July 2007, Josh Boyer wrote:
> +#ifdef CONFIG_PPC64
> +typedef unsigned long mm_context_id_t;
> +
> +typedef struct {
> +=A0=A0=A0=A0=A0=A0=A0mm_context_id_t id;
> +=A0=A0=A0=A0=A0=A0=A0u16 user_psize;=A0=A0=A0=A0=A0=A0=A0=A0=A0/* page s=
ize index */
> +
> +#ifdef CONFIG_PPC_MM_SLICES
> +=A0=A0=A0=A0=A0=A0=A0u64 low_slices_psize;=A0=A0=A0/* SLB page size enco=
dings */
> +=A0=A0=A0=A0=A0=A0=A0u64 high_slices_psize; =A0/* 4 bits per slice for n=
ow */
> +#else
> +=A0=A0=A0=A0=A0=A0=A0u16 sllp;=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0/* SLB page size encoding */
> +#endif
> +=A0=A0=A0=A0=A0=A0=A0unsigned long vdso_base;
> +} mm_context_t;
> +
> +#else /* !CONFIG_PPC64 */
> +
> +typedef struct {
> +=A0=A0=A0=A0=A0=A0=A0unsigned long id;
> +=A0=A0=A0=A0=A0=A0=A0unsigned long vdso_base;
> +} mm_context_t;
> +
> +#endif /* CONFIG_PPC64 */
It seems to me that you can easily consolidate this further, if you
allow the mm_context_id_t on 32 bit, or remove it on 64 bit:
+typedef unsigned long mm_context_id_t;
+
+typedef struct {
+ mm_context_id_t id;
+ u16 user_psize; /* page size index */
+
+#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_MM_SLICES
+ u64 low_slices_psize; /* SLB page size encodings */
+ u64 high_slices_psize; /* 4 bits per slice for now */
+#else
+ u16 sllp; /* SLB page size encoding */
+#endif
+#endif
+ unsigned long vdso_base;
+} mm_context_t;
^ permalink raw reply
* Re: [PATCH 3/4] Extend the DMA-engine API.
From: Randy Dunlap @ 2007-07-10 15:46 UTC (permalink / raw)
To: Zhang Wei; +Cc: linuxppc-dev, akpm, paulus, linux-kernel
In-Reply-To: <11840607111926-git-send-email-wei.zhang@freescale.com>
On Tue, 10 Jul 2007 17:45:11 +0800 Zhang Wei wrote:
> Add channel wait queue and transfer callback dma_xfer_callback().
> If the DMA controller and driver support interrupt, when the
> transfer is finished, it will wakeup the wait queue
> and call the callback function of the channel.
>
> Add dma_async_raw_xfer() to API and device_raw_xfer() to struct dma_device
> for RAW physical address DMA transfer, which will be used at transfer
> between I/O address and memory address.
>
> Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
> ---
> include/linux/dmaengine.h | 35 +++++++++++++++++++++++++++++++++++
> 1 files changed, 35 insertions(+), 0 deletions(-)
> /**
> + * dma_async_raw_xfer - transfor data between physical addresses with callback
transfer
> + * @chan: DMA channel to be used
> + * @dest: destination address (physical)
> + * @src: source address (physical)
> + * @len: length
> + */
> +static inline dma_cookie_t dma_async_raw_xfer(struct dma_chan *chan,
> + dma_addr_t dest, dma_addr_t src, size_t len,
> + dma_xfer_callback cb, void *data)
> +{
---
~Randy
*** Remember to use Documentation/SubmitChecklist when testing your code ***
^ permalink raw reply
* Re: [PATCH] Consolidate mm_context_t definition in mmu.h
From: Josh Boyer @ 2007-07-10 16:47 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linuxppc-dev, paulus, david
In-Reply-To: <200707101836.26413.arnd@arndb.de>
On Tue, 2007-07-10 at 18:36 +0200, Arnd Bergmann wrote:
> On Tuesday 10 July 2007, Josh Boyer wrote:
> > +#ifdef CONFIG_PPC64
> > +typedef unsigned long mm_context_id_t;
> > +
> > +typedef struct {
> > + mm_context_id_t id;
> > + u16 user_psize; /* page size index */
> > +
> > +#ifdef CONFIG_PPC_MM_SLICES
> > + u64 low_slices_psize; /* SLB page size encodings */
> > + u64 high_slices_psize; /* 4 bits per slice for now */
> > +#else
> > + u16 sllp; /* SLB page size encoding */
> > +#endif
> > + unsigned long vdso_base;
> > +} mm_context_t;
> > +
> > +#else /* !CONFIG_PPC64 */
> > +
> > +typedef struct {
> > + unsigned long id;
> > + unsigned long vdso_base;
> > +} mm_context_t;
> > +
> > +#endif /* CONFIG_PPC64 */
>
>
> It seems to me that you can easily consolidate this further, if you
> allow the mm_context_id_t on 32 bit, or remove it on 64 bit:
Hm... good point. Though...
>
> +typedef unsigned long mm_context_id_t;
> +
> +typedef struct {
> + mm_context_id_t id;
> + u16 user_psize; /* page size index */
> +
> +#ifdef CONFIG_PPC64
This needs to be moved up to encompass the u16 user_psize member as
well, yes?
> +#ifdef CONFIG_PPC_MM_SLICES
> + u64 low_slices_psize; /* SLB page size encodings */
> + u64 high_slices_psize; /* 4 bits per slice for now */
> +#else
> + u16 sllp; /* SLB page size encoding */
> +#endif
> +#endif
> + unsigned long vdso_base;
> +} mm_context_t;
josh
^ permalink raw reply
* Re: [kernel-2.6.19]Marvell GT-64260 and Ethernet
From: Muruga Ganapathy @ 2007-07-10 16:52 UTC (permalink / raw)
To: Mark A. Greer, ThomasB, Linuxppc-embedded
You need to check the phy address and the type of the PHY used.
If it is not there/or supported, you may want to include them.
> On Tue, Jul 10, 2007 at 03:41:25PM +0200, ThomasB wrote:
> > >Isn't the ethernet the same on the 64260, 64360, 64460?
> > >
> > >There's definitely a driver for 6436x and above..
> >
> > I just try it, it doesn't work, I receive without end the message:
> > mv643xx PHY read timeout, port 0
> >
> > >I believe that Steve Hill <sjhill@realitydiluted.com> has patched
> > >the mv643xx_eth driver to work with the 64260 and plans to submit
> > >the patches.
> > That's means the patch isn't yet ready?
>
> It probably means you don't something set up for whatever PHY you're
> using.
>
> > I will try to contact him.
>
> A good idea.
>
> > It's nevertheless odd, I read about a file named gt64260_eth.c
during my
> > search on the internet.But I wasn't able to find it :(.
>
> There was one for 2.4 that was in the ppc devel tree but it never went
> mainline. Hopefully, Steve can help you from here.
>
> Mark
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
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^ permalink raw reply
* Re: [PATCH] Consolidate mm_context_t definition in mmu.h
From: Arnd Bergmann @ 2007-07-10 16:55 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev, paulus, david
In-Reply-To: <1184086042.32199.11.camel@weaponx.rchland.ibm.com>
On Tuesday 10 July 2007, Josh Boyer wrote:
> > + =A0 =A0 =A0 u16 user_psize; =A0 =A0 =A0 =A0 /* page size index */
> > +
> > +#ifdef CONFIG_PPC64
>=20
> This needs to be moved up to encompass the u16 user_psize member as
> well, yes?
>=20
Yes, of course. my bad.
Arnd <><
^ permalink raw reply
* [PATCH v4] Create add_rtc() function to enable the RTC CMOS driver
From: Wade Farnsworth @ 2007-07-10 16:55 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <18067.29586.481904.580320@cargo.ozlabs.ibm.com>
In order to use the RTC CMOS driver, each architecture must register a
platform device for the RTC.
This creates a function to register the platform device based on the RTC
device node and verifies that the RTC port against the hard-coded value
in asm/mc146818rtc.h.
Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
---
Fixed line wrapping.
arch/powerpc/sysdev/Makefile | 1
arch/powerpc/sysdev/rtc_cmos_setup.c | 49 +++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 7d8ac1b..f65078c 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o
+obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
# contains only the suspend handler for time
ifeq ($(CONFIG_RTC_CLASS),)
diff --git a/arch/powerpc/sysdev/rtc_cmos_setup.c b/arch/powerpc/sysdev/rtc_cmos_setup.c
new file mode 100644
index 0000000..e276048
--- /dev/null
+++ b/arch/powerpc/sysdev/rtc_cmos_setup.c
@@ -0,0 +1,49 @@
+/*
+ * Setup code for PC-style Real-Time Clock.
+ *
+ * Author: Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/mc146818rtc.h>
+
+#include <asm/prom.h>
+
+static int __init add_rtc(void)
+{
+ struct device_node *np;
+ struct platform_device *pd;
+ struct resource res;
+ int ret;
+
+ np = of_find_compatible_node(NULL, NULL, "pnpPNP,b00");
+ if (!np)
+ return -ENODEV;
+
+ ret = of_address_to_resource(np, 0, &res);
+ of_node_put(np);
+ if (ret)
+ return ret;
+
+ /*
+ * RTC_PORT(x) is hardcoded in asm/mc146818rtc.h. Verify that the
+ * address provided by the device node matches.
+ */
+ if (res.start != RTC_PORT(0))
+ return -EINVAL;
+
+ pd = platform_device_register_simple("rtc_cmos", -1,
+ &res, 1);
+ if (IS_ERR(pd))
+ return PTR_ERR(pd);
+
+ return 0;
+}
+fs_initcall(add_rtc);
^ permalink raw reply related
* Re: [PATCH 1/2] eHEA: Capability flag for DLPAR support
From: Jeff Garzik @ 2007-07-10 16:59 UTC (permalink / raw)
To: Jan-Bernd Themann
Cc: Thomas Klein, Jan-Bernd Themann, netdev, linux-kernel, linux-ppc,
Christoph Raisch, Marcus Eder, Stefan Roscher
In-Reply-To: <200707050926.26087.ossthema@de.ibm.com>
Jan-Bernd Themann wrote:
> This patch introduces a capability flag that is used by the DLPAR userspace
> tool to check which DLPAR features are supported by the eHEA driver.
>
> Missing goto has been included.
>
> Signed-off-by: Jan-Bernd Themann <themann@de.ibm.com>
applied
^ permalink raw reply
* Re: [PATCH 2/2] eHEA: Receive SKB Aggregation
From: Jeff Garzik @ 2007-07-10 17:00 UTC (permalink / raw)
To: Jan-Bernd Themann
Cc: Thomas Klein, Jan-Bernd Themann, netdev, linux-kernel, linux-ppc,
Christoph Raisch, Marcus Eder, Stefan Roscher
In-Reply-To: <200707041209.48658.ossthema@de.ibm.com>
Jan-Bernd Themann wrote:
> This patch enables the receive side processing to aggregate TCP packets within
> the HEA device driver. It analyses the packets already received after an
> interrupt arrived and forwards these as chains of SKBs for the same TCP
> connection with modified header field. We have seen a lower CPU load and
> improved throughput for small numbers of parallel TCP connections.
> As this feature is considered as experimental it is switched off by default
> and can be activated via a module parameter.
>
> Some additional security checks have been added since the last posting.
>
> Signed-off-by: Jan-Bernd Themann <themann@de.ibm.com>
as noted in comments, we don't need to recreate this in every driver.
do something more generic.
^ permalink raw reply
* Re: [PATCH] PHY fixed driver: rework release path and update phy_id notation
From: Jeff Garzik @ 2007-07-10 17:01 UTC (permalink / raw)
To: Vitaly Bordug; +Cc: linuxppc-dev, linux-kernel, netdev
In-Reply-To: <20070609162118.2680.99019.stgit@ACA800FC.ipt.aol.com>
Vitaly Bordug wrote:
> device_bind_driver() error code returning has been fixed.
> release() function has been written, so that to free resources
> in correct way; the release path is now clean.
>
> Before the rework, it used to cause
> Device 'fixed@100:1' does not have a release() function, it is broken
> and must be fixed.
> BUG: at drivers/base/core.c:104 device_release()
>
> Call Trace:
> [<ffffffff802ec380>] kobject_cleanup+0x53/0x7e
> [<ffffffff802ec3ab>] kobject_release+0x0/0x9
> [<ffffffff802ecf3f>] kref_put+0x74/0x81
> [<ffffffff8035493b>] fixed_mdio_register_device+0x230/0x265
> [<ffffffff80564d31>] fixed_init+0x1f/0x35
> [<ffffffff802071a4>] init+0x147/0x2fb
> [<ffffffff80223b6e>] schedule_tail+0x36/0x92
> [<ffffffff8020a678>] child_rip+0xa/0x12
> [<ffffffff80311714>] acpi_ds_init_one_object+0x0/0x83
> [<ffffffff8020705d>] init+0x0/0x2fb
> [<ffffffff8020a66e>] child_rip+0x0/0x12
>
>
> Also changed the notation of the fixed phy definition on
> mdio bus to the form of <speed>+<duplex> to make it able to be used by
> gianfar and ucc_geth that define phy_id strictly as "%d:%d"
>
> Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org>
>
> ---
>
> drivers/net/phy/Kconfig | 4 ++
> drivers/net/phy/fixed.c | 93 +++++++++++++++++++++++++++--------------------
> 2 files changed, 57 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index 09b6f25..a938c48 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -71,4 +71,8 @@ config FIXED_MII_100_FDX
> bool "Emulation for 100M Fdx fixed PHY behavior"
> depends on FIXED_PHY
>
> +config FIXED_MII_1000_FDX
> + bool "Emulation for 1000M Fdx fixed PHY behavior"
> + depends on FIXED_PHY
> +
> endif # PHYLIB
> diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
> index 68c99b4..34b9111 100644
> --- a/drivers/net/phy/fixed.c
> +++ b/drivers/net/phy/fixed.c
> @@ -187,12 +187,29 @@ static struct phy_driver fixed_mdio_driver = {
> .driver = { .owner = THIS_MODULE,},
> };
>
> +static void fixed_mdio_release (struct device * dev)
> +{
> + struct phy_device *phydev = container_of(dev, struct phy_device, dev);
> + struct mii_bus *bus = phydev->bus;
> + struct fixed_info *fixed = bus->priv;
> +
> + kfree(phydev);
> + kfree(bus->dev);
> + kfree(bus);
> + kfree(fixed->regs);
> + kfree(fixed);
> +}
> +
> /*-----------------------------------------------------------------------------
> * This func is used to create all the necessary stuff, bind
> * the fixed phy driver and register all it on the mdio_bus_type.
> - * speed is either 10 or 100, duplex is boolean.
> + * speed is either 10 or 100 or 1000, duplex is boolean.
> * number is used to create multiple fixed PHYs, so that several devices can
> * utilize them simultaneously.
> + *
> + * The device on mdio bus will look like <bus_id>:<phy_id>,
> + * bus_id = number
> + * phy_id = speed+duplex.
> *-----------------------------------------------------------------------------*/
> static int fixed_mdio_register_device(int number, int speed, int duplex)
> {
> @@ -221,6 +238,12 @@ static int fixed_mdio_register_device(int number, int speed, int duplex)
> }
>
> fixed->regs = kzalloc(MII_REGS_NUM*sizeof(int), GFP_KERNEL);
> + if (NULL == fixed->regs) {
> + kfree(dev);
> + kfree(new_bus);
> + kfree(fixed);
> + return -ENOMEM;
> + }
> fixed->regs_num = MII_REGS_NUM;
> fixed->phy_status.speed = speed;
> fixed->phy_status.duplex = duplex;
> @@ -249,57 +272,43 @@ static int fixed_mdio_register_device(int number, int speed, int duplex)
> fixed->phydev = phydev;
>
> if(NULL == phydev) {
> - err = -ENOMEM;
> - goto device_create_fail;
> + kfree(dev);
> + kfree(new_bus);
> + kfree(fixed->regs);
> + kfree(fixed);
> + return -ENOMEM;
> }
>
> phydev->irq = PHY_IGNORE_INTERRUPT;
> phydev->dev.bus = &mdio_bus_type;
>
> - if(number)
> - snprintf(phydev->dev.bus_id, BUS_ID_SIZE,
> - "fixed_%d@%d:%d", number, speed, duplex);
> - else
> - snprintf(phydev->dev.bus_id, BUS_ID_SIZE,
> - "fixed@%d:%d", speed, duplex);
> + snprintf(phydev->dev.bus_id, BUS_ID_SIZE,
> + "%d:%d", number, speed + duplex);
> +
> phydev->bus = new_bus;
>
> + phydev->dev.driver = &fixed_mdio_driver.driver;
> + phydev->dev.release = fixed_mdio_release;
> +
> + err = phydev->dev.driver->probe(&phydev->dev);
> + if(err < 0) {
> + printk(KERN_ERR "Phy %s: problems with fixed driver\n",
> + phydev->dev.bus_id);
> + kfree(phydev);
> + kfree(dev);
> + kfree(new_bus);
> + kfree(fixed->regs);
> + kfree(fixed);
> + return err;
> + }
> +
> err = device_register(&phydev->dev);
> if(err) {
> printk(KERN_ERR "Phy %s failed to register\n",
> phydev->dev.bus_id);
> - goto bus_register_fail;
> - }
use the standard 'goto' style found in the kernel, rather than repeating
all these kfree's.
^ permalink raw reply
* [PATCH v2] Consolidate mm_context_t definition in mmu.h
From: Josh Boyer @ 2007-07-10 17:52 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, arnd, david
All of the platforms except PPC64 share a common mm_context_t definition.
Defining it in mmu.h avoids duplicating it in the platform specific mmu
header files. We further consolidate it by having the PPC32 definition
share the mm_context_id_t type for the id member.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
---
include/asm-powerpc/mmu-44x.h | 5 -----
include/asm-powerpc/mmu-8xx.h | 4 ----
include/asm-powerpc/mmu-fsl-booke.h | 4 ----
include/asm-powerpc/mmu-hash32.h | 5 -----
include/asm-powerpc/mmu-hash64.h | 16 ----------------
include/asm-powerpc/mmu.h | 21 +++++++++++++++++++++
6 files changed, 21 insertions(+), 34 deletions(-)
--- linux-2.6.orig/include/asm-powerpc/mmu-44x.h
+++ linux-2.6/include/asm-powerpc/mmu-44x.h
@@ -55,11 +55,6 @@
typedef unsigned long long phys_addr_t;
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
-
#endif /* !__ASSEMBLY__ */
#ifndef CONFIG_PPC_EARLY_DEBUG_44x
--- linux-2.6.orig/include/asm-powerpc/mmu-8xx.h
+++ linux-2.6/include/asm-powerpc/mmu-8xx.h
@@ -138,10 +138,6 @@
#ifndef __ASSEMBLY__
typedef unsigned long phys_addr_t;
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_MMU_8XX_H_ */
--- linux-2.6.orig/include/asm-powerpc/mmu-fsl-booke.h
+++ linux-2.6/include/asm-powerpc/mmu-fsl-booke.h
@@ -79,10 +79,6 @@ typedef unsigned long phys_addr_t;
typedef unsigned long long phys_addr_t;
#endif
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */
--- linux-2.6.orig/include/asm-powerpc/mmu-hash32.h
+++ linux-2.6/include/asm-powerpc/mmu-hash32.h
@@ -79,11 +79,6 @@ struct hash_pte {
unsigned long pp:2; /* Page protection */
};
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
-
typedef unsigned long phys_addr_t;
#endif /* !__ASSEMBLY__ */
--- linux-2.6.orig/include/asm-powerpc/mmu-hash64.h
+++ linux-2.6/include/asm-powerpc/mmu-hash64.h
@@ -359,22 +359,6 @@ extern void stab_initialize(unsigned lon
#ifndef __ASSEMBLY__
-typedef unsigned long mm_context_id_t;
-
-typedef struct {
- mm_context_id_t id;
- u16 user_psize; /* page size index */
-
-#ifdef CONFIG_PPC_MM_SLICES
- u64 low_slices_psize; /* SLB page size encodings */
- u64 high_slices_psize; /* 4 bits per slice for now */
-#else
- u16 sllp; /* SLB page size encoding */
-#endif
- unsigned long vdso_base;
-} mm_context_t;
-
-
static inline unsigned long vsid_scramble(unsigned long protovsid)
{
#if 0
--- linux-2.6.orig/include/asm-powerpc/mmu.h
+++ linux-2.6/include/asm-powerpc/mmu.h
@@ -19,5 +19,26 @@
# include <asm/mmu-8xx.h>
#endif
+#ifndef __ASSEMBLY__
+
+typedef unsigned long mm_context_id_t;
+
+typedef struct {
+ mm_context_id_t id;
+#ifdef CONFIG_PPC64
+ u16 user_psize; /* page size index */
+
+#ifdef CONFIG_PPC_MM_SLICES
+ u64 low_slices_psize; /* SLB page size encodings */
+ u64 high_slices_psize; /* 4 bits per slice for now */
+#else
+ u16 sllp; /* SLB page size encoding */
+#endif
+#endif /* CONFIG_PPC64 */
+ unsigned long vdso_base;
+} mm_context_t;
+
+#endif /* !__ASSEMBLY__ */
+
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MMU_H_ */
^ permalink raw reply
* Re: [PATCH] [POWERPC] Move generic MPC82xx functions out of ADS-specific
From: Scott Wood @ 2007-07-10 18:05 UTC (permalink / raw)
To: Laurent Pinchart; +Cc: linuxppc-embedded
In-Reply-To: <200707101312.46052.laurent.pinchart@technotrade.biz>
On Tue, Jul 10, 2007 at 01:12:45PM +0200, Laurent Pinchart wrote:
> The non board-specific mpc82xx_halt and mpc82xx_restart functions are defined
> in arch/powerpc/platforms/82xx/mpc82xx_ads.c. This patch moves them to
> mpc82xx.c to make them usable by other MPC82xx boards.
Why are you also moving mpc82xx_ads_show_cpuinfo() to the board file?
It's not really ADS-specific; it should just be renamed.
-Scott
^ permalink raw reply
* Re: more patches pushed to powerpc.git for-2.6.23 branch
From: Josh Boyer @ 2007-07-10 18:06 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <18067.32217.791517.449235@cargo.ozlabs.ibm.com>
On Tue, 2007-07-10 at 22:38 +1000, Paul Mackerras wrote:
> I just pushed the following patches to the for-2.6.23 branch on
> powerpc.git. I intend to ask Linus to pull everything on the
> for-2.6.23 branch shortly, unless I hear loud screams to the
> contrary. :)
Can we get Ben's new emac driver added? It's fairly important for 4xx
work to continue.
Ben?
josh
^ permalink raw reply
* Re: MPC82xx ADS SCC ports initialisation
From: Scott Wood @ 2007-07-10 18:11 UTC (permalink / raw)
To: Laurent Pinchart; +Cc: vbordug, linuxppc-embedded
In-Reply-To: <200707101619.52438.laurent.pinchart@technotrade.biz>
On Tue, Jul 10, 2007 at 04:19:51PM +0200, Laurent Pinchart wrote:
> clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
> clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
> setbits32(&immap->im_cpmux.cmx_scr,
> ((data->clk_tx - 1) << (4 - data->clk_tx)));
> setbits32(&immap->im_cpmux.cmx_scr,
> ((data->clk_rx - 1) << (4 - data->clk_rx)));
>
> The shift right-hand operand doesn't seem to be correct. Could anyone confirm
> this ?
You are correct; it's broken.
> If my assumption is right, could anyone tell me if the MPC82xx
> processors are actually supported by the powerpc architecture, or if the
> MPC82xx ADS code is just a non-functional work in progress.
I have a bunch of 8xx/82xx changes pending; I hope to get them cleaned up
before the merge window ends.
> I also noticed that U-Boot doesn't have flatten device tree support for the
> MPC82xx family.
No, but cuImage for 82xx is on its way.
-Scott
^ permalink raw reply
* Resend: [PATCH] oprofile support for Power 5++
From: Mike Wolf @ 2007-07-10 18:13 UTC (permalink / raw)
To: linuxppc-dev
The patch has not been included and there have been no comments so
I'm resending.
This patch adds a new oprofile cpu type for Power 5 revision 3 chips.
The new name is ppc64/power5++ and is used so that the performance
counters can be set up correctly.
Signed-off-by: Mike Wolf <mjw@us.ibm.com>
--------
linux-2.6.18.ppc64.orig/arch/powerpc/kernel/cputable.c 2006-09-19 22:42:06.000000000 -0500
+++ linux-2.6.18.ppc64/arch/powerpc/kernel/cputable.c 2007-06-11 12:29:47.000000000 -0500
@@ -236,6 +236,21 @@
.oprofile_mmcra_sipr = MMCRA_SIPR,
.platform = "power5",
},
+ { /* Power5++ */
+ .pvr_mask = 0xffffff00,
+ .pvr_value = 0x003b0300,
+ .cpu_name = "POWER5+ (gs)",
+ .cpu_features = CPU_FTRS_POWER5,
+ .cpu_user_features = COMMON_USER_POWER5_PLUS,
+ .icache_bsize = 128,
+ .dcache_bsize = 128,
+ .num_pmcs = 6,
+ .oprofile_cpu_type = "ppc64/power5++",
+ .oprofile_type = PPC_OPROFILE_POWER4,
+ .oprofile_mmcra_sihv = MMCRA_SIHV,
+ .oprofile_mmcra_sipr = MMCRA_SIPR,
+ .platform = "power5+",
+ },
{ /* Power5 GS */
.pvr_mask = 0xffff0000,
.pvr_value = 0x003b0000,
^ permalink raw reply
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