* Re: [PATCH 1/2] [RFC][POWERPC] MPC8568E-MDS: create localbus node
From: Sergei Shtylyov @ 2007-10-15 15:42 UTC (permalink / raw)
To: Anton Vorontsov; +Cc: linuxppc-dev
In-Reply-To: <20071015153525.GA28761@localhost.localdomain>
Anton Vorontsov wrote:
> This patch creates localbus node, moves bcsr into it, and adds
> localbus to the probe path.
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
> index 5439437..296adc3 100644
> --- a/arch/powerpc/boot/dts/mpc8568mds.dts
> +++ b/arch/powerpc/boot/dts/mpc8568mds.dts
> @@ -42,9 +42,17 @@
> reg = <00000000 10000000>;
> };
>
> - bcsr@f8000000 {
> - device_type = "board-control";
> - reg = <f8000000 8000>;
> + localbus@f0000000 {
> + compatible = "fsl,mpc8568mds-localbus";
Is the entity described as "localbus" indeed so *board* specific?
> + #address-cells = <2>;
> + #size-cells = <1>;
> + reg = <f0000000 10000000>;
> + ranges = <0 0 f8000000 0008000>;
Isn't that range a part of "reg"?
> +
> + bcsr@0,0 {
> + device_type = "board-control";
> + reg = <0 0 8000>;
> + };
> };
>
> soc8568@e0000000 {
WBR, Sergei
^ permalink raw reply
* kernel stops booting on quad powermac
From: Johannes Berg @ 2007-10-15 14:56 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 504 bytes --]
Oddly, a recent kernel (23fd50450a34f2558070ceabb0bfebc1c9604af5) stops
booting at "windfarm: Drive bay control loop started.", while previously
"windfarm: CPUs control loops started" was displayed a long time, i.e.
Backside took very long to start.
Haven't had a chance to look into it yet, any ideas? I do have NO_HZ
enabled. I wanted to test the irqtrace patch but I doubt it would be
causing this, usually bugs there caused hangs very early, not this late
in the boot sequence.
johannes
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 828 bytes --]
^ permalink raw reply
* [PATCH 2/2] [POWERPC] MPC8568E-MDS: add support for flash
From: Anton Vorontsov @ 2007-10-15 15:35 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <9aefd05e0d526cb1c6b5c7905581ec781093eb88.1192462414.git.avorontsov@ru.mvista.com>
MPC8568E-MDS have 1 32MB Spansion x16 CFI flash chip. Let's use it.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
Patch is against galak/powerpc.git master branch.
arch/powerpc/boot/dts/mpc8568mds.dts | 35 +++++++++++++++++++++++++++++++++-
1 files changed, 34 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 296adc3..c3b2138 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -47,12 +47,45 @@
#address-cells = <2>;
#size-cells = <1>;
reg = <f0000000 10000000>;
- ranges = <0 0 f8000000 0008000>;
+ ranges = <0 0 f8000000 0008000
+ 1 0 fe000000 2000000>;
bcsr@0,0 {
device_type = "board-control";
reg = <0 0 8000>;
};
+
+ flash@1,0 {
+ compatible = "Spansion,S29GL256N11TFIV2O", "cfi-flash";
+ reg = <1 0 2000000>;
+ probe-type = "CFI";
+ bank-width = <2>;
+ device-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ hrcw@0 {
+ label = "hrcw";
+ reg = <0 20001>;
+ read-only;
+ };
+
+ kernel@20000 {
+ label = "kernel";
+ reg = <20000 200000>;
+ };
+
+ rootfs@220000 {
+ label = "rootfs";
+ reg = <220000 1d60000>;
+ };
+
+ uboot@1f80000 {
+ label = "u-boot";
+ reg = <1f80000 80000>;
+ read-only;
+ };
+ };
};
soc8568@e0000000 {
--
1.5.0.6
^ permalink raw reply related
* [PATCH 1/2] [RFC][POWERPC] MPC8568E-MDS: create localbus node
From: Anton Vorontsov @ 2007-10-15 15:35 UTC (permalink / raw)
To: linuxppc-dev
This patch creates localbus node, moves bcsr into it, and adds
localbus to the probe path.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
Patch is against galak/powerpc.git master branch.
arch/powerpc/boot/dts/mpc8568mds.dts | 14 +++++++++++---
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 +
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 5439437..296adc3 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -42,9 +42,17 @@
reg = <00000000 10000000>;
};
- bcsr@f8000000 {
- device_type = "board-control";
- reg = <f8000000 8000>;
+ localbus@f0000000 {
+ compatible = "fsl,mpc8568mds-localbus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <f0000000 10000000>;
+ ranges = <0 0 f8000000 0008000>;
+
+ bcsr@0,0 {
+ device_type = "board-control";
+ reg = <0 0 8000>;
+ };
};
soc8568@e0000000 {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 61b3eed..0cf994b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -139,6 +139,7 @@ static struct of_device_id mpc85xx_ids[] = {
{ .type = "soc", },
{ .compatible = "soc", },
{ .type = "qe", },
+ { .compatible = "fsl,mpc8568mds-localbus", },
{},
};
--
1.5.0.6
^ permalink raw reply related
* Re: [PATCH v2 2/7] rheap: Changes config mechanism
From: Grant Likely @ 2007-10-15 15:09 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev, paulus, domen.puncer
In-Reply-To: <47137F41.6000404@freescale.com>
On 10/15/07, Timur Tabi <timur@freescale.com> wrote:
> Kumar Gala wrote:
>
> >> If you turn on the QE but don't turn on RHEAP, the build will fail.
> >> Do we want to allow that?
> >
> > nope.
>
> Is there any way to force RHEAP to be selected when it's a user-selectable option?
Yes, you just add menu text line after the "bool". Bestcomm, QE and
others still select it unconditionally.
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH v2 2/7] rheap: Changes config mechanism
From: Timur Tabi @ 2007-10-15 14:54 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus, domen.puncer
In-Reply-To: <4540BB4B-8A7C-4D8F-9BBE-0B6F6DAD4DA3@kernel.crashing.org>
Kumar Gala wrote:
>> If you turn on the QE but don't turn on RHEAP, the build will fail.
>> Do we want to allow that?
>
> nope.
Is there any way to force RHEAP to be selected when it's a user-selectable option?
--
Timur Tabi
Linux Kernel Developer @ Freescale
^ permalink raw reply
* Re: [PATCH v4 3/9] add Freescale SerDes PHY support
From: Arnd Bergmann @ 2007-10-15 14:54 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Li Yang, paulus
In-Reply-To: <1192460190-26891-1-git-send-email-leoli@freescale.com>
On Monday 15 October 2007, Li Yang wrote:
> The SerDes(serializer/deserializer) PHY block is a new SoC block used
> in Freescale chips to support multiple serial interfaces, such as PCI
> Express, SGMII, SATA.
looks good now
> Signed-off-by: Li Yang <leoli@freescale.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
^ permalink raw reply
* Re: [PATCH v2 2/7] rheap: Changes config mechanism
From: Kumar Gala @ 2007-10-15 14:54 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev, paulus, domen.puncer
In-Reply-To: <47137ECD.9020103@freescale.com>
On Oct 15, 2007, at 9:53 AM, Timur Tabi wrote:
> Kumar Gala wrote:
>
>> I don't see why we can't let users select it (saying that
>> differently, we should let users have this ability)
>
> If you turn on the QE but don't turn on RHEAP, the build will
> fail. Do we want to allow that?
nope.
- k
^ permalink raw reply
* Re: [PATCH v2 2/7] rheap: Changes config mechanism
From: Timur Tabi @ 2007-10-15 14:53 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus, domen.puncer
In-Reply-To: <5D5FEAFA-AFB9-4F8D-941E-11686E8992F4@kernel.crashing.org>
Kumar Gala wrote:
> I don't see why we can't let users select it (saying that
> differently, we should let users have this ability)
If you turn on the QE but don't turn on RHEAP, the build will fail. Do we
want to allow that?
--
Timur Tabi
Linux Kernel Developer @ Freescale
^ permalink raw reply
* [PATCH v2] powerpc: Add 1TB workaround for PA6T
From: Olof Johansson @ 2007-10-15 14:58 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
In-Reply-To: <20071012064942.GB30829@lixom.net>
PA6T has a bug where the slbie instruction does not honor the large
segment bit. As a result, we have to always use slbia when switching
context.
We don't have to worry about changing the slbie's during fault processing,
since they should never be replacing one VSID with another using the
same ESID. I.e. there's no risk for inserting duplicate entries due to a
failed slbie of the old entry. So as long as we clear it out on context
switch we should be fine.
Signed-off-by: Olof Johansson <olof@lixom.net>
Index: k.org/arch/powerpc/mm/hash_utils_64.c
===================================================================
--- k.org.orig/arch/powerpc/mm/hash_utils_64.c
+++ k.org/arch/powerpc/mm/hash_utils_64.c
@@ -212,6 +212,7 @@ static int __init htab_dt_scan_seg_sizes
return 1;
}
}
+ cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
return 0;
}
Index: k.org/arch/powerpc/mm/slb.c
===================================================================
--- k.org.orig/arch/powerpc/mm/slb.c
+++ k.org/arch/powerpc/mm/slb.c
@@ -157,7 +157,8 @@ void switch_slb(struct task_struct *tsk,
unsigned long stack = KSTK_ESP(tsk);
unsigned long unmapped_base;
- if (offset <= SLB_CACHE_ENTRIES) {
+ if (!cpu_has_feature(CPU_FTR_NO_SLBIE_B) &&
+ offset <= SLB_CACHE_ENTRIES) {
int i;
asm volatile("isync" : : : "memory");
for (i = 0; i < offset; i++) {
Index: k.org/include/asm-powerpc/cputable.h
===================================================================
--- k.org.orig/include/asm-powerpc/cputable.h
+++ k.org/include/asm-powerpc/cputable.h
@@ -165,6 +165,7 @@ extern void do_feature_fixups(unsigned l
#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
+#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
#ifndef __ASSEMBLY__
@@ -367,7 +368,7 @@ extern void do_feature_fixups(unsigned l
#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
- CPU_FTR_PURR | CPU_FTR_REAL_LE)
+ CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
Index: k.org/arch/powerpc/kernel/entry_64.S
===================================================================
--- k.org.orig/arch/powerpc/kernel/entry_64.S
+++ k.org/arch/powerpc/kernel/entry_64.S
@@ -408,6 +408,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT
std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
+ /* No need to check for CPU_FTR_NO_SLBIE_B here, since when
+ * we have 1TB segments, the only CPUs known to have the errata
+ * only support less than 1TB of system memory and we'll never
+ * actually hit this code path.
+ */
+
slbie r6
slbie r6 /* Workaround POWER5 < DD2.1 issue */
slbmte r7,r0
^ permalink raw reply
* [PATCH v4 9/9] add MPC837x MDS board default device tree
From: Li Yang @ 2007-10-15 14:56 UTC (permalink / raw)
To: galak, paulus, linuxppc-dev; +Cc: Li Yang
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/boot/dts/mpc8377_mds.dts | 281 +++++++++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8378_mds.dts | 263 +++++++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8379_mds.dts | 299 +++++++++++++++++++++++++++++++++
3 files changed, 843 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc8377_mds.dts
create mode 100644 arch/powerpc/boot/dts/mpc8378_mds.dts
create mode 100644 arch/powerpc/boot/dts/mpc8379_mds.dts
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
new file mode 100644
index 0000000..d0bd326
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -0,0 +1,281 @@
+/*
+ * MPC8377E MDS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "fsl,mpc8377emds";
+ compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,837x@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>;
+ i-cache-line-size = <20>;
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ 32-bit;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; // 512MB at 0
+ };
+
+ soc837x@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ compatible = "mpc83xx_wdt";
+ reg = <200 100>;
+ };
+
+ i2c@3000 {
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <e 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <f 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ spi@7000 {
+ compatible = "mpc83xx_spi";
+ reg = <7000 1000>;
+ interrupts = <10 8>;
+ interrupt-parent = < &ipic >;
+ mode = <0>;
+ };
+
+ /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
+ usb@23000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-dr";
+ reg = <23000 1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = < &ipic >;
+ interrupts = <26 8>;
+ phy_type = "utmi_wide";
+ };
+
+ mdio@24520 {
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = < &ipic >;
+ interrupts = <11 8>;
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ phy3: ethernet-phy@3 {
+ interrupt-parent = < &ipic >;
+ interrupts = <12 8>;
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@24000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8 21 8 22 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy2 >;
+ };
+
+ ethernet@25000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 8 24 8 25 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy3 >;
+ };
+
+ serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <9 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ crypto@30000 {
+ model = "SEC3";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 8>;
+ interrupt-parent = < &ipic >;
+ /* Rev. 3.0 geometry */
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <000009fe>;
+ descriptor-types-mask = <03ab0ebf>;
+ };
+
+ sdhc@2e000 {
+ model = "eSDHC";
+ compatible = "fsl,esdhc";
+ reg = <2e000 1000>;
+ interrupts = <2a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ sata@18000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <18000 1000>;
+ interrupts = <2c 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes1 >;
+ };
+
+ sata@19000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <19000 1000>;
+ interrupts = <2d 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes1 >;
+ };
+
+ serdes1:serdes@e3000 {
+ compatible = "fsl,serdes";
+ reg = <e3000 100>;
+ vdd-1v;
+ protocol = "sata";
+ clock = <d#100>;
+ };
+
+ serdes2:serdes@e3100 {
+ compatible = "fsl,serdes";
+ reg = <e3100 100>;
+ vdd-1v;
+ protocol = "pcie";
+ clock = <d#100>;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: pic@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <700 100>;
+ };
+ };
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc83xx-pci", "83xx";
+ device_type = "pci";
+ };
+};
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
new file mode 100644
index 0000000..9f31e09
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -0,0 +1,263 @@
+/*
+ * MPC8378E MDS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "fsl,mpc8378emds";
+ compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,837x@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>;
+ i-cache-line-size = <20>;
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ 32-bit;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; // 512MB at 0
+ };
+
+ soc837x@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ compatible = "mpc83xx_wdt";
+ reg = <200 100>;
+ };
+
+ i2c@3000 {
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <e 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <f 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ spi@7000 {
+ compatible = "mpc83xx_spi";
+ reg = <7000 1000>;
+ interrupts = <10 8>;
+ interrupt-parent = < &ipic >;
+ mode = <0>;
+ };
+
+ /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
+ usb@23000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-dr";
+ reg = <23000 1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = < &ipic >;
+ interrupts = <26 8>;
+ phy_type = "utmi_wide";
+ };
+
+ mdio@24520 {
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = < &ipic >;
+ interrupts = <11 8>;
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ phy3: ethernet-phy@3 {
+ interrupt-parent = < &ipic >;
+ interrupts = <12 8>;
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@24000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8 21 8 22 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy2 >;
+ };
+
+ ethernet@25000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 8 24 8 25 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy3 >;
+ };
+
+ serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <9 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ crypto@30000 {
+ model = "SEC3";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 8>;
+ interrupt-parent = < &ipic >;
+ /* Rev. 3.0 geometry */
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <000009fe>;
+ descriptor-types-mask = <03ab0ebf>;
+ };
+
+ sdhc@2e000 {
+ model = "eSDHC";
+ compatible = "fsl,esdhc";
+ reg = <2e000 1000>;
+ interrupts = <2a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ serdes1:serdes@e3000 {
+ compatible = "fsl,serdes";
+ reg = <e3000 100>;
+ vdd-1v;
+ protocol = "sgmii";
+ clock = <d#100>;
+ };
+
+ serdes2:serdes@e3100 {
+ compatible = "fsl,serdes";
+ reg = <e3100 100>;
+ vdd-1v;
+ protocol = "pcie";
+ clock = <d#100>;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: pic@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <700 100>;
+ };
+ };
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc83xx-pci", "83xx";
+ device_type = "pci";
+ };
+};
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
new file mode 100644
index 0000000..5510e18
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -0,0 +1,299 @@
+/*
+ * MPC8379E MDS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "fsl,mpc8379emds";
+ compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,837x@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>;
+ i-cache-line-size = <20>;
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ 32-bit;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; // 512MB at 0
+ };
+
+ soc837x@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ compatible = "mpc83xx_wdt";
+ reg = <200 100>;
+ };
+
+ i2c@3000 {
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <e 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <f 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ spi@7000 {
+ compatible = "mpc83xx_spi";
+ reg = <7000 1000>;
+ interrupts = <10 8>;
+ interrupt-parent = < &ipic >;
+ mode = <0>;
+ };
+
+ /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
+ usb@23000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-dr";
+ reg = <23000 1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = < &ipic >;
+ interrupts = <26 8>;
+ phy_type = "utmi_wide";
+ };
+
+ mdio@24520 {
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = < &ipic >;
+ interrupts = <11 8>;
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ phy3: ethernet-phy@3 {
+ interrupt-parent = < &ipic >;
+ interrupts = <12 8>;
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@24000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8 21 8 22 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy2 >;
+ };
+
+ ethernet@25000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 8 24 8 25 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy3 >;
+ };
+
+ serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <9 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ crypto@30000 {
+ model = "SEC3";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 8>;
+ interrupt-parent = < &ipic >;
+ /* Rev. 3.0 geometry */
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <000009fe>;
+ descriptor-types-mask = <03ab0ebf>;
+ };
+
+ sdhc@2e000 {
+ model = "eSDHC";
+ compatible = "fsl,esdhc";
+ reg = <2e000 1000>;
+ interrupts = <2a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ sata@18000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <18000 1000>;
+ interrupts = <2c 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes1 >;
+ };
+
+ sata@19000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <19000 1000>;
+ interrupts = <2d 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes1 >;
+ };
+
+ sata@1a000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <1a000 1000>;
+ interrupts = <2e 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes2 >;
+ };
+
+ sata@1b000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <1b000 1000>;
+ interrupts = <2f 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes2 >;
+ };
+
+ serdes1:serdes@e3000 {
+ compatible = "fsl,serdes";
+ reg = <e3000 100>;
+ vdd-1v;
+ protocol = "sata";
+ clock = <d#100>;
+ };
+
+ serdes2:serdes@e3100 {
+ compatible = "fsl,serdes";
+ reg = <e3100 100>;
+ vdd-1v;
+ protocol = "sata";
+ clock = <d#100>;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: pic@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <700 100>;
+ };
+ };
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc83xx-pci", "83xx";
+ device_type = "pci";
+ };
+};
--
1.5.3.2.104.g41ef
^ permalink raw reply related
* [PATCH v4 3/9] add Freescale SerDes PHY support
From: Li Yang @ 2007-10-15 14:56 UTC (permalink / raw)
To: galak, paulus, linuxppc-dev; +Cc: Li Yang
The SerDes(serializer/deserializer) PHY block is a new SoC block used
in Freescale chips to support multiple serial interfaces, such as PCI
Express, SGMII, SATA.
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/platforms/Kconfig | 3 +
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_serdes.c | 195 ++++++++++++++++++++++++++++++++++++++
3 files changed, 199 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/sysdev/fsl_serdes.c
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index cc6013f..ff4fddc 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -313,4 +313,7 @@ config FSL_ULI1575
config CPM
bool
+config FSL_SERDES
+ bool
+
endmenu
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 1a6f564..a892aa0 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \
mv64x60_udbg.o
obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
obj-$(CONFIG_AXON_RAM) += axonram.o
+obj-$(CONFIG_FSL_SERDES) += fsl_serdes.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
diff --git a/arch/powerpc/sysdev/fsl_serdes.c b/arch/powerpc/sysdev/fsl_serdes.c
new file mode 100644
index 0000000..670015d
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_serdes.c
@@ -0,0 +1,195 @@
+/*
+ * arch/powerpc/sysdev/fsl_serdes.c
+ *
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Li Yang <leoli@freescale.com>
+ *
+ * Freescale SerDes initialization routines
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+
+#define FSL_SRDSCR0_OFFS 0x0
+#define FSL_SRDSCR0_DPP_1V2 0x00008800
+#define FSL_SRDSCR1_OFFS 0x4
+#define FSL_SRDSCR1_PLLBW 0x00000040
+#define FSL_SRDSCR2_OFFS 0x8
+#define FSL_SRDSCR2_VDD_1V2 0x00800000
+#define FSL_SRDSCR2_SEIC_MASK 0x00001c1c
+#define FSL_SRDSCR2_SEIC_SATA 0x00001414
+#define FSL_SRDSCR2_SEIC_PEX 0x00001010
+#define FSL_SRDSCR2_SEIC_SGMII 0x00000101
+#define FSL_SRDSCR3_OFFS 0xc
+#define FSL_SRDSCR3_KFR_SATA 0x10100000
+#define FSL_SRDSCR3_KPH_SATA 0x04040000
+#define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000
+#define FSL_SRDSCR3_SDTXL_SATA 0x00000505
+#define FSL_SRDSCR4_OFFS 0x10
+#define FSL_SRDSCR4_PROT_SATA 0x00000808
+#define FSL_SRDSCR4_PROT_PEX 0x00000101
+#define FSL_SRDSCR4_PROT_SGMII 0x00000505
+#define FSL_SRDSCR4_PLANE_X2 0x01000000
+#define FSL_SRDSCR4_RFCKS_100 0x00000000
+#define FSL_SRDSCR4_RFCKS_125 0x10000000
+#define FSL_SRDSCR4_RFCKS_150 0x30000000
+#define FSL_SRDSRSTCTL_OFFS 0x20
+#define FSL_SRDSRSTCTL_RST 0x80000000
+#define FSL_SRDSRSTCTL_SATA_RESET 0xf
+
+static int fsl_serdes_probe(struct of_device *ofdev,
+ const struct of_device_id *match)
+{
+ struct device_node *np = ofdev->node;
+ void __iomem *regs;
+ const char *prot;
+ const unsigned int *freq;
+ u32 rfcks;
+
+ regs = of_iomap(np, 0);
+ if (!regs)
+ return -ENOMEM;
+
+ prot = of_get_property(np, "protocol", NULL);
+ if (!prot)
+ goto out;
+ freq = of_get_property(np, "clock", NULL);
+ if (!freq)
+ goto out;
+ switch (*freq) {
+ case 100:
+ rfcks = FSL_SRDSCR4_RFCKS_100;
+ break;
+ case 125:
+ rfcks = FSL_SRDSCR4_RFCKS_125;
+ break;
+ case 150:
+ rfcks = FSL_SRDSCR4_RFCKS_150;
+ break;
+ default:
+ printk(KERN_ERR "SerDes: Wrong frequency\n");
+ goto out;
+ }
+
+ /* Use default prescale and counter */
+
+ /* 1.0V corevdd */
+ if (of_get_property(np, "vdd-1v", NULL)) {
+ /* DPPE/DPPA = 0 */
+ clrbits32(regs + FSL_SRDSCR0_OFFS, FSL_SRDSCR0_DPP_1V2);
+
+ /* VDD = 0 */
+ clrbits32(regs + FSL_SRDSCR2_OFFS, FSL_SRDSCR2_VDD_1V2);
+ }
+
+ /* protocol specific configuration */
+ if (!strcmp(prot, "sata")) {
+ /* Set and clear reset bits */
+ setbits32(regs + FSL_SRDSRSTCTL_OFFS,
+ FSL_SRDSRSTCTL_SATA_RESET);
+ mdelay(1);
+ clrbits32(regs + FSL_SRDSRSTCTL_OFFS,
+ FSL_SRDSRSTCTL_SATA_RESET);
+
+ /* Configure SRDSCR1 */
+ clrbits32(regs + FSL_SRDSCR1_OFFS, FSL_SRDSCR1_PLLBW);
+
+ /* Configure SRDSCR2 */
+ clrsetbits_be32(regs + FSL_SRDSCR2_OFFS,
+ FSL_SRDSCR2_SEIC_MASK, FSL_SRDSCR2_SEIC_SATA);
+
+ /* Configure SRDSCR3 */
+ out_be32(regs + FSL_SRDSCR3_OFFS, FSL_SRDSCR3_KFR_SATA |
+ FSL_SRDSCR3_KPH_SATA |
+ FSL_SRDSCR3_SDFM_SATA_PEX |
+ FSL_SRDSCR3_SDTXL_SATA);
+
+ /* Configure SRDSCR4 */
+ out_be32(regs + FSL_SRDSCR4_OFFS, rfcks |
+ FSL_SRDSCR4_PROT_SATA);
+
+ } else if (!strcmp(prot, "pcie")) {
+ /* Configure SRDSCR1 */
+ setbits32(regs + FSL_SRDSCR1_OFFS, FSL_SRDSCR1_PLLBW);
+
+ /* Configure SRDSCR2 */
+ clrsetbits_be32(regs + FSL_SRDSCR2_OFFS, FSL_SRDSCR2_SEIC_MASK,
+ FSL_SRDSCR2_SEIC_PEX);
+
+ /* Configure SRDSCR3 */
+ out_be32(regs + FSL_SRDSCR3_OFFS, FSL_SRDSCR3_SDFM_SATA_PEX);
+
+ /* Configure SRDSCR4 */
+ if (of_get_property(np, "pcie-x2", NULL))
+ out_be32(regs + FSL_SRDSCR4_OFFS, rfcks |
+ FSL_SRDSCR4_PROT_PEX | FSL_SRDSCR4_PLANE_X2);
+ else
+ out_be32(regs + FSL_SRDSCR4_OFFS, rfcks |
+ FSL_SRDSCR4_PROT_PEX);
+
+ } else if (!strcmp(prot, "sgmii")) {
+ /* Configure SRDSCR1 */
+ clrbits32(regs + FSL_SRDSCR1_OFFS, FSL_SRDSCR1_PLLBW);
+
+ /* Configure SRDSCR2 */
+ clrsetbits_be32(regs + FSL_SRDSCR2_OFFS, FSL_SRDSCR2_SEIC_MASK,
+ FSL_SRDSCR2_SEIC_SGMII);
+
+ /* Configure SRDSCR3 */
+ out_be32(regs + FSL_SRDSCR3_OFFS, 0);
+
+ /* Configure SRDSCR4 */
+ out_be32(regs + FSL_SRDSCR4_OFFS, rfcks |
+ FSL_SRDSCR4_PROT_SGMII);
+
+ } else {
+ printk(KERN_ERR "SerDes: Wrong protocol\n");
+ goto out;
+ }
+
+ /* Do a software reset */
+ setbits32(regs + FSL_SRDSRSTCTL_OFFS, FSL_SRDSRSTCTL_RST);
+ iounmap(regs);
+
+ dev_printk(KERN_INFO, &ofdev->dev, "Initialized as %s\n", prot);
+
+ return 0;
+out:
+ iounmap(regs);
+ return -EINVAL;
+}
+
+static struct of_device_id fsl_serdes_match[] = {
+ {
+ .compatible = "fsl,serdes",
+ },
+ {},
+};
+
+static struct of_platform_driver fsl_serdes_driver = {
+ .name = "fsl-serdes",
+ .match_table = fsl_serdes_match,
+ .probe = fsl_serdes_probe,
+};
+
+static int __init fsl_serdes_init(void)
+{
+ of_register_platform_driver(&fsl_serdes_driver);
+ return 0;
+}
+device_initcall(fsl_serdes_init);
--
1.5.3.2.104.g41ef
^ permalink raw reply related
* Re: [PATCH v2 4/7] bestcomm: core bestcomm support for Freescale MPC5200
From: Matt Sealey @ 2007-10-15 14:39 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, paulus, domen.puncer
In-Reply-To: <fa686aa40710150720x6c0ab76hf45d434740d5718f@mail.gmail.com>
Grant Likely wrote:
> On 10/15/07, Kumar Gala <galak@kernel.crashing.org> wrote:
>> (Comments just on SRAM code)
>>
>> I think this should be made generic and be utility functionality to
>> rheap.
>>
>> CPM, CPM2, QE, L2 SRAM, etc can all use this. I'd rather we didn't
>> have 3 ways to do the exact same functionality. (cpm_dpalloc,
>> cpm_dpfree, qe_muram_alloc, qe_muram_free)
>
> Fair enough; but not in this patch set. This series is working
> support for bestcomm. To go to the more generic level of being used
> by multiple parts should be done in a separate series.
I suggested this a couple months ago and a couple people here said a
generic SRAM driver would be a bad idea.. (even the tsi1xx and Marvell
chips could use a generic SRAM driver)?
Module probe order comes into play, which is why it was a bad idea; how
do you make sure that SRAM and all it's finer points (which may not be
handled by a generic rheap library - after all, the address, size,
alignment needs to be *passed* to rheap init) is there and probed before
bestcomm, qe ethernet units or cryptography, axe on the 5121e, gigabit
on the marvell, deep sleep code on the 5200b (just listing users atm)
or something or other, without turning the drivers into a hard
dependency of the sram subsystem?
--
Matt Sealey <matt@genesi-usa.com>
Genesi, Manager, Developer Relations
^ permalink raw reply
* Re: [PATCH v3 4/4] FEC mpc52xx: phy part of the driver\
From: Grant Likely @ 2007-10-15 14:30 UTC (permalink / raw)
To: Domen Puncer; +Cc: linuxppc-dev, jgarzik, netdev
In-Reply-To: <20071015105601.GM3000@nd47.coderock.org>
On 10/15/07, Domen Puncer <domen.puncer@telargo.com> wrote:
> On 14/10/07 16:05 -0600, Grant Likely wrote:
> > On 10/14/07, Domen Puncer <domen.puncer@telargo.com> wrote:
> > > PHY part of the driver for mpc5200(b) ethernet.
> >
> > Assuming I understand correctly, this comment is not correct and this
> > patch just adds an MDIO bus driver. PHY drivers are in phylib and
> > data transfer is setup via the core driver, correct?
>
> Right.
>
> >
> > It is conceivable that the PHY is connected to an alternate MDIO bus,
> > or the MDIO bus is used for a PHY connected to an external Ethernet
> > controller.
> >
> > Speaking of which, is it possible to use this MDIO bus without the
> > core FEC being initialized?
>
> IIRC fec doesn't need any initialization for MDIO bus registers to work.
>
> >
> > > +static struct of_device_id fec_mdio_match[] = {
> > > + {
> > > + .type = "mdio",
> > > + .compatible = "mpc5200b-fec-phy",
> >
> > This is not a phy; it's an MDIO bus. Also, shouldn't this be
> > "mpc5200-..." instead of "mpc5200b-..."?
>
> Didn't know if it's ok for mpc5200, guess it is?
I believe it is.
>
> >
> > > + },
> > > + {},
> > > +};
> > > +
> > > +struct of_platform_driver mpc52xx_fec_mdio_driver = {
> > > + .name = "mpc5200b-fec-phy",
> > > + .probe = fec_mdio_probe,
> > > + .remove = fec_mdio_remove,
> > > + .match_table = fec_mdio_match,
> >
> > Inconsistent naming. Please use the same prefix on all global/static
> > symbols (ie. use "mpc52xx_mdio_" instead of the mix of
> > "mpc52xx_fec_mdio_", "fec_mdio_", etc.) I also thing that "fec_mdio_"
> > is too generic because there are a number of different incompatible
> > FEC devices.
>
> OK.
>
> >
> > > +};
> > > +
> > > +/* let fec driver call it, since this has to be registered before it */
> > > +EXPORT_SYMBOL_GPL(mpc52xx_fec_mdio_driver);
> >
> > Why not have a module_init()/module_exit() in this file? I don't
> > think the FEC driver calls this driver's functions directly anymore,
> > and it's still dependent on the of_platform bus probe order anyway.
>
> It was one way of making sure mdio driver is registered before fec.
> (and of_platform bus probe order won't work for modules)
> Nicer alternatives?
However, that assumption only works when the PHY is accessed via the
on-chip MDIO controller. What happens with a different MDIO bus is
used?
...
Need to take a look at how phylib handles the probing order problem;
but really this is something that PHYLIB needs to handle; not the FEC
driver.
> > > --- linux.git.orig/drivers/net/fec_mpc52xx/Kconfig
> > > +++ linux.git/drivers/net/fec_mpc52xx/Kconfig
> > > @@ -11,5 +11,18 @@ config FEC_MPC52xx
> > > ---help---
> > > This option enables support for the MPC5200's on-chip
> > > Fast Ethernet Controller
> > > + If compiled as module, it will be called 'fec_mpc52xx.ko'.
> >
> > Drop this line and make the help text the same format as the other eth
> > drivers in drivers/net.
>
> How exactly is it different now?
> And most of them have the "Module will be called xxx" line.
Okay, you're right. There is a real hodgepodge of help text format in
drivers/net/Kconfig. Do what seems best to you.
>
> >
> > > +
> > > +config FEC_MPC52xx_MDIO
> > > + bool "FEC MII PHY driver"
> > > + depends on FEC_MPC52xx
> > > + default y
> > > + ---help---
> > > + The MPC5200's FEC can connect to the Ethernet either with
> > > + an external MII PHY chip or 10 Mbps 7-wire interface
> > > + (Motorola? industry standard).
> > > + If your board uses an external PHY, enable this.
> >
> > Not strictly true. This enables talking to a PHY using the internal
> > MDIO controller. PHY register access could just as easily be accessed
> > via an alternate interface.
>
> Not just that is also selects which mode will it use.
> If you don't enable this, fec will be set up as 7-wire
> ( 696 rcntrl |= FEC_RCNTRL_MII_MODE;)
Looking at fec.c:
That line is dependent on priv->has_phy. priv->has_phy is set on line
949 which is conditional on the node having the property "phy-handle".
It doesn't look like it is conditional on CONFIG_FEC_MPC52xx_MDIO at
all.
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH v2 4/7] bestcomm: core bestcomm support for Freescale MPC5200
From: Grant Likely @ 2007-10-15 14:20 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus, domen.puncer
In-Reply-To: <C2B03958-38CC-4B5C-96C1-E8B5366C4D49@kernel.crashing.org>
On 10/15/07, Kumar Gala <galak@kernel.crashing.org> wrote:
> (Comments just on SRAM code)
>
> I think this should be made generic and be utility functionality to
> rheap.
>
> CPM, CPM2, QE, L2 SRAM, etc can all use this. I'd rather we didn't
> have 3 ways to do the exact same functionality. (cpm_dpalloc,
> cpm_dpfree, qe_muram_alloc, qe_muram_free)
Fair enough; but not in this patch set. This series is working
support for bestcomm. To go to the more generic level of being used
by multiple parts should be done in a separate series.
>
> see other comments inline.
>
> > +
> > diff --git a/arch/powerpc/sysdev/bestcomm/sram.c b/arch/powerpc/
> > sysdev/bestcomm/sram.c
> > new file mode 100644
> > index 0000000..b3f2ed1
> > --- /dev/null
> > +++ b/arch/powerpc/sysdev/bestcomm/sram.c
> > @@ -0,0 +1,177 @@
> > +/*
> > + * Simple memory allocator for on-board SRAM
> > + *
> > + *
> > + * Maintainer : Sylvain Munaut <tnt@246tNt.com>
> > + *
> > + * Copyright (C) 2005 Sylvain Munaut <tnt@246tNt.com>
> > + *
> > + * This file is licensed under the terms of the GNU General Public
> > License
> > + * version 2. This program is licensed "as is" without any
> > warranty of any
> > + * kind, whether express or implied.
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/slab.h>
> > +#include <linux/spinlock.h>
> > +#include <linux/string.h>
> > +#include <linux/ioport.h>
> > +#include <linux/of.h>
> > +
> > +#include <asm/io.h>
> > +#include <asm/mmu.h>
> > +
> > +#include "sram.h"
> > +
> > +
> > +/* Struct keeping our 'state' */
> > +struct bcom_sram *bcom_sram = NULL;
>
> shouldn't be global, so we can support more than one SRAM.
Again; I agree, but I'm not going to make that change in this series.
>
> > +EXPORT_SYMBOL_GPL(bcom_sram); /* needed for inline functions */
> > +
> > +
> > +/*
> > ======================================================================
> > == */
> > +/* Public
> > API */
> > +/*
> > ======================================================================
> > == */
> > +/* DO NOT USE in interrupts, if needed in irq handler, we should
> > use the
> > + _irqsave version of the spin_locks */
> > +
> > +int bcom_sram_init(struct device_node *sram_node, char *owner)
> > +{
> > + int rv;
> > + const u32 *regaddr_p;
> > + u64 regaddr64, size64;
> > + unsigned int psize;
> > +
> > + /* Create our state struct */
> > + if (bcom_sram) {
> > + printk(KERN_ERR "%s: bcom_sram_init: "
> > + "Already initialiwed !\n", owner);
> > + return -EBUSY;
> > + }
> > +
> > + bcom_sram = kmalloc(sizeof(struct bcom_sram), GFP_KERNEL);
>
> should return this handle to the user.
To be done when this driver is changed to support multiple sram regions.
> > diff --git a/arch/powerpc/sysdev/bestcomm/sram.h b/arch/powerpc/
> > sysdev/bestcomm/sram.h
> > new file mode 100644
> > index 0000000..b6d6689
> > --- /dev/null
> > +++ b/arch/powerpc/sysdev/bestcomm/sram.h
> > @@ -0,0 +1,54 @@
> > +/*
> > + * Handling of a sram zone for bestcomm
> > + *
> > + *
> > + * Copyright (C) 2007 Sylvain Munaut <tnt@246tNt.com>
> > + *
> > + * This file is licensed under the terms of the GNU General Public
> > License
> > + * version 2. This program is licensed "as is" without any
> > warranty of any
> > + * kind, whether express or implied.
> > + */
> > +
> > +#ifndef __BESTCOMM_SRAM_H__
> > +#define __BESTCOMM_SRAM_H__
> > +
> > +#include <asm/rheap.h>
> > +#include <asm/mmu.h>
> > +#include <linux/spinlock.h>
> > +
> > +
> > +/* Structure used internally */
> > + /* The internals are here for the inline functions
> > + * sake, certainly not for the user to mess with !
> > + */
> > +struct bcom_sram {
> > + phys_addr_t base_phys;
> > + void *base_virt;
>
> __iomem for base_virt?
I'll take a look
>
> > + unsigned int size;
> > + rh_info_t *rh;
> > + spinlock_t lock;
> > +};
> > +
> > +extern struct bcom_sram *bcom_sram;
> > +
> > +
> > +/* Public API */
> > +extern int bcom_sram_init(struct device_node *sram_node, char
> > *owner);
> > +extern void bcom_sram_cleanup(void);
> > +
> > +extern void* bcom_sram_alloc(int size, int align, phys_addr_t *phys);
> > +extern void bcom_sram_free(void *ptr);
> > +
> > +static inline phys_addr_t bcom_sram_va2pa(void *va) {
>
> should take bcom_sram handle as a param
>
> > + return bcom_sram->base_phys +
> > + (unsigned long)(va - bcom_sram->base_virt);
>
> shouldn't this cast be phys_addr_t?
I don't think so. ->base_phys is of type phys_addr_t;
(va-bcom_sram->base_virt) is just an offset from ->base_phys.
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* RE: [PATCH v2] [POWERPC] ucc_geth: Fix build break introduced by commit 09f75cd7bf13720738e6a196cc0107ce9a5bd5a0
From: Li Yang-r58472 @ 2007-10-15 14:09 UTC (permalink / raw)
To: Medve Emilian-EMMEDVE1, akpm, jgarzik, netdev, linuxppc-dev
In-Reply-To: <1192455830-1028-1-git-send-email-Emilian.Medve@Freescale.com>
> -----Original Message-----
> From: Medve Emilian-EMMEDVE1=20
> Sent: Monday, October 15, 2007 9:44 PM
> To: akpm@linux-foundation.org; jgarzik@pobox.com; Li=20
> Yang-r58472; netdev@vger.kernel.org; linuxppc-dev@ozlabs.org
> Cc: Medve Emilian-EMMEDVE1
> Subject: [PATCH v2] [POWERPC] ucc_geth: Fix build break=20
> introduced by commit 09f75cd7bf13720738e6a196cc0107ce9a5bd5a0
>=20
> drivers/net/ucc_geth.c: In function 'ucc_geth_rx':
> drivers/net/ucc_geth.c:3483: error: 'dev' undeclared (first=20
> use in this function)
> drivers/net/ucc_geth.c:3483: error: (Each undeclared=20
> identifier is reported only once
> drivers/net/ucc_geth.c:3483: error: for each function it appears in.)
> make[2]: *** [drivers/net/ucc_geth.o] Error 1
>=20
> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Acked-by: Li Yang <leoli@freescale.com>
> ---
>=20
> Here is a convenient link for the culprit patch:=20
> http://git.kernel.org/?p=3Dlinux/kernel/git/jgarzik/netdev-2.6.g
> it;a=3Dcommit;h=3D09f75cd7bf13720738e6a196cc0107ce9a5bd5a0
>=20
> netdev-2.6> scripts/checkpatch.pl=20
> 0001-POWERPC-ucc_geth-Fix-build-break-introduced-by-co.patch
> Your patch has no obvious style problems and is ready for submission.
>=20
> drivers/net/ucc_geth.c | 5 ++++-
> 1 files changed, 4 insertions(+), 1 deletions(-)
>=20
> diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c=20
> index d00e7d4..bec413b 100644
> --- a/drivers/net/ucc_geth.c
> +++ b/drivers/net/ucc_geth.c
> @@ -63,7 +63,7 @@
> #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
> =20
> void uec_set_ethtool_ops(struct net_device *netdev);
> -=09
> +
> static DEFINE_SPINLOCK(ugeth_lock);
> =20
> static struct {
> @@ -3454,9 +3454,12 @@ static int ucc_geth_rx(struct=20
> ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit
> u16 length, howmany =3D 0;
> u32 bd_status;
> u8 *bdBuffer;
> + struct net_device * dev;
> =20
> ugeth_vdbg("%s: IN", __FUNCTION__);
> =20
> + dev =3D ugeth->dev;
> +
> /* collect received buffers */
> bd =3D ugeth->rxBd[rxQ];
> =20
> --
> 1.5.3.GIT
>=20
^ permalink raw reply
* Re: [PATCH v3 3/9] add Freescale SerDes PHY support
From: Arnd Bergmann @ 2007-10-15 14:10 UTC (permalink / raw)
To: linuxppc-dev; +Cc: paulus
In-Reply-To: <989B956029373F45A0B8AF0297081890019B590F@zch01exm26.fsl.freescale.net>
On Monday 15 October 2007, Li Yang-r58472 wrote:
> I'd like to but of_iomap() couldn't provide the physical address of the
> device used as identification.
It looks like you only use the physical address for a single printk,
so you could change that to print the full-name of the device node
instead, or do a dev_printk of the parent of_device if you can change
it the way I suggested in my second comment.
Arnd <><
^ permalink raw reply
* Re: [PATCH v2 2/7] rheap: Changes config mechanism
From: Grant Likely @ 2007-10-15 14:06 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus, domen.puncer
In-Reply-To: <5D5FEAFA-AFB9-4F8D-941E-11686E8992F4@kernel.crashing.org>
On 10/15/07, Kumar Gala <galak@kernel.crashing.org> wrote:
>
> On Oct 15, 2007, at 8:55 AM, Grant Likely wrote:
>
> > On 10/15/07, Kumar Gala <galak@kernel.crashing.org> wrote:
> >>
> >> On Oct 13, 2007, at 11:41 PM, Grant Likely wrote:
> >>
> >>> From: Sylvain Munaut <tnt@246tNt.com>
> >>>
> >>> Instead of having in the makefile all the option that
> >>> requires rheap, we define a configuration symbol
> >>> and when needed we make sure it's selected.
> >>>
> >>> Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
> >>> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> >>> ---
> >>>
> >>> +
> >>> +config PPC_LIB_RHEAP
> >>
> >> we should really have help for this option.
> >
> > This is a non-user-selectable option; none of the other
> > non-user-selectable options have help text.
>
> I don't see why we can't let users select it (saying that
> differently, we should let users have this ability)
Sure; but not in this patch. This patch just changes from one fixed
method for selecting rheap to another.
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH v2 4/7] bestcomm: core bestcomm support for Freescale MPC5200
From: Kumar Gala @ 2007-10-15 14:06 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, paulus, domen.puncer
In-Reply-To: <20071014044205.23438.36036.stgit@trillian.cg.shawcable.net>
(Comments just on SRAM code)
I think this should be made generic and be utility functionality to
rheap.
CPM, CPM2, QE, L2 SRAM, etc can all use this. I'd rather we didn't
have 3 ways to do the exact same functionality. (cpm_dpalloc,
cpm_dpfree, qe_muram_alloc, qe_muram_free)
see other comments inline.
> +
> diff --git a/arch/powerpc/sysdev/bestcomm/sram.c b/arch/powerpc/
> sysdev/bestcomm/sram.c
> new file mode 100644
> index 0000000..b3f2ed1
> --- /dev/null
> +++ b/arch/powerpc/sysdev/bestcomm/sram.c
> @@ -0,0 +1,177 @@
> +/*
> + * Simple memory allocator for on-board SRAM
> + *
> + *
> + * Maintainer : Sylvain Munaut <tnt@246tNt.com>
> + *
> + * Copyright (C) 2005 Sylvain Munaut <tnt@246tNt.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> License
> + * version 2. This program is licensed "as is" without any
> warranty of any
> + * kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +#include <linux/string.h>
> +#include <linux/ioport.h>
> +#include <linux/of.h>
> +
> +#include <asm/io.h>
> +#include <asm/mmu.h>
> +
> +#include "sram.h"
> +
> +
> +/* Struct keeping our 'state' */
> +struct bcom_sram *bcom_sram = NULL;
shouldn't be global, so we can support more than one SRAM.
> +EXPORT_SYMBOL_GPL(bcom_sram); /* needed for inline functions */
> +
> +
> +/*
> ======================================================================
> == */
> +/* Public
> API */
> +/*
> ======================================================================
> == */
> +/* DO NOT USE in interrupts, if needed in irq handler, we should
> use the
> + _irqsave version of the spin_locks */
> +
> +int bcom_sram_init(struct device_node *sram_node, char *owner)
> +{
> + int rv;
> + const u32 *regaddr_p;
> + u64 regaddr64, size64;
> + unsigned int psize;
> +
> + /* Create our state struct */
> + if (bcom_sram) {
> + printk(KERN_ERR "%s: bcom_sram_init: "
> + "Already initialiwed !\n", owner);
> + return -EBUSY;
> + }
> +
> + bcom_sram = kmalloc(sizeof(struct bcom_sram), GFP_KERNEL);
should return this handle to the user.
> + if (!bcom_sram) {
> + printk(KERN_ERR "%s: bcom_sram_init: "
> + "Couldn't allocate internal state !\n", owner);
> + return -ENOMEM;
> + }
> +
> + /* Get address and size of the sram */
> + regaddr_p = of_get_address(sram_node, 0, &size64, NULL);
> + if (!regaddr_p) {
> + printk(KERN_ERR "%s: bcom_sram_init: "
> + "Invalid device node !\n", owner);
> + rv = -EINVAL;
> + goto error_free;
> + }
> +
> + regaddr64 = of_translate_address(sram_node, regaddr_p);
> +
> + bcom_sram->base_phys = (phys_addr_t) regaddr64;
> + bcom_sram->size = (unsigned int) size64;
> +
> + /* Request region */
> + if (!request_mem_region(bcom_sram->base_phys, bcom_sram->size,
> owner)) {
> + printk(KERN_ERR "%s: bcom_sram_init: "
> + "Couln't request region !\n", owner);
> + rv = -EBUSY;
> + goto error_free;
> + }
> +
> + /* Map SRAM */
> + /* sram is not really __iomem */
> + bcom_sram->base_virt = (void*) ioremap(bcom_sram->base_phys,
> bcom_sram->size);
> +
> + if (!bcom_sram->base_virt) {
> + printk(KERN_ERR "%s: bcom_sram_init: "
> + "Map error SRAM zone 0x%08lx (0x%0x)!\n",
> + owner, bcom_sram->base_phys, bcom_sram->size );
> + rv = -ENOMEM;
> + goto error_release;
> + }
> +
> + /* Create an rheap (defaults to 32 bits word alignment) */
> + bcom_sram->rh = rh_create(4);
> +
> + /* Attach the free zones */
> +#if 0
> + /* Currently disabled ... for future use only */
> + reg_addr_p = of_get_property(sram_node, "available", &psize);
> +#else
> + regaddr_p = NULL;
> + psize = 0;
> +#endif
> +
> + if (!regaddr_p || !psize) {
> + /* Attach the whole zone */
> + rh_attach_region(bcom_sram->rh, 0, bcom_sram->size);
> + } else {
> + /* Attach each zone independently */
> + while (psize >= 2 * sizeof(u32)) {
> + phys_addr_t zbase = of_translate_address(sram_node, regaddr_p);
> + rh_attach_region(bcom_sram->rh, zbase - bcom_sram->base_phys,
> regaddr_p[1]);
> + regaddr_p += 2;
> + psize -= 2 * sizeof(u32);
> + }
> + }
> +
> + /* Init our spinlock */
> + spin_lock_init(&bcom_sram->lock);
> +
> + return 0;
> +
> +error_release:
> + release_mem_region(bcom_sram->base_phys, bcom_sram->size);
> +error_free:
> + kfree(bcom_sram);
> + bcom_sram = NULL;
> +
> + return rv;
> +}
> +EXPORT_SYMBOL_GPL(bcom_sram_init);
> +
> +void bcom_sram_cleanup(void)
> +{
> + /* Free resources */
should take bcom_sram handle as a param
> + if (bcom_sram) {
> + rh_destroy(bcom_sram->rh);
> + iounmap((void __iomem *)bcom_sram->base_virt);
> + release_mem_region(bcom_sram->base_phys, bcom_sram->size);
> + kfree(bcom_sram);
> + bcom_sram = NULL;
> + }
> +}
> +EXPORT_SYMBOL_GPL(bcom_sram_cleanup);
> +
> +void* bcom_sram_alloc(int size, int align, phys_addr_t *phys)
> +{
> + unsigned long offset;
should take bcom_sram handle as a param
> +
> + spin_lock(&bcom_sram->lock);
> + offset = rh_alloc_align(bcom_sram->rh, size, align, NULL);
> + spin_unlock(&bcom_sram->lock);
> +
> + if (IS_ERR_VALUE(offset))
> + return NULL;
> +
> + *phys = bcom_sram->base_phys + offset;
> + return bcom_sram->base_virt + offset;
> +}
> +EXPORT_SYMBOL_GPL(bcom_sram_alloc);
> +
> +void bcom_sram_free(void *ptr)
> +{
> + unsigned long offset;
> +
should take bcom_sram handle as a param
> + if (!ptr)
> + return;
> +
> + offset = ptr - bcom_sram->base_virt;
> +
> + spin_lock(&bcom_sram->lock);
> + rh_free(bcom_sram->rh, offset);
> + spin_unlock(&bcom_sram->lock);
> +}
> +EXPORT_SYMBOL_GPL(bcom_sram_free);
> +
> diff --git a/arch/powerpc/sysdev/bestcomm/sram.h b/arch/powerpc/
> sysdev/bestcomm/sram.h
> new file mode 100644
> index 0000000..b6d6689
> --- /dev/null
> +++ b/arch/powerpc/sysdev/bestcomm/sram.h
> @@ -0,0 +1,54 @@
> +/*
> + * Handling of a sram zone for bestcomm
> + *
> + *
> + * Copyright (C) 2007 Sylvain Munaut <tnt@246tNt.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> License
> + * version 2. This program is licensed "as is" without any
> warranty of any
> + * kind, whether express or implied.
> + */
> +
> +#ifndef __BESTCOMM_SRAM_H__
> +#define __BESTCOMM_SRAM_H__
> +
> +#include <asm/rheap.h>
> +#include <asm/mmu.h>
> +#include <linux/spinlock.h>
> +
> +
> +/* Structure used internally */
> + /* The internals are here for the inline functions
> + * sake, certainly not for the user to mess with !
> + */
> +struct bcom_sram {
> + phys_addr_t base_phys;
> + void *base_virt;
__iomem for base_virt?
> + unsigned int size;
> + rh_info_t *rh;
> + spinlock_t lock;
> +};
> +
> +extern struct bcom_sram *bcom_sram;
> +
> +
> +/* Public API */
> +extern int bcom_sram_init(struct device_node *sram_node, char
> *owner);
> +extern void bcom_sram_cleanup(void);
> +
> +extern void* bcom_sram_alloc(int size, int align, phys_addr_t *phys);
> +extern void bcom_sram_free(void *ptr);
> +
> +static inline phys_addr_t bcom_sram_va2pa(void *va) {
should take bcom_sram handle as a param
> + return bcom_sram->base_phys +
> + (unsigned long)(va - bcom_sram->base_virt);
shouldn't this cast be phys_addr_t?
> +}
> +
> +static inline void *bcom_sram_pa2va(phys_addr_t pa) {
should take bcom_sram handle as a param
> + return bcom_sram->base_virt +
> + (unsigned long)(pa - bcom_sram->base_phys);
shouldn't this cast be phys_addr_t?
> +}
> +
> +
> +#endif /* __BESTCOMM_SRAM_H__ */
> +
^ permalink raw reply
* Re: can and mpc5200b
From: Pradyumna Sampath @ 2007-10-15 14:05 UTC (permalink / raw)
To: S. Fricke; +Cc: linuxppc-dev
In-Reply-To: <20071015133233.GB4859@sfrouter>
Hi Silvio,
On 10/15/07, S. Fricke <silvio.fricke@googlemail.com> wrote:
> Hello Friends,
> what is the reasonable can-driver for a mpc5200b?
>
> I have seen for the peak-3.17 driver a port for the mpc5200 from denx on their
> website, but with kernel 2.6.23 I dont have a chance to use this?
Check this out http://developer.berlios.de/projects/socketcan/ . This
is the CAN driver we use and it works pretty well for us. It is very
updated and supports the mscan chipset that is available with the
mpc5200b.
HTH
regards
/prady
--
htp://prady.livejournal.com
^ permalink raw reply
* Re: [PATCH v2 4/7] bestcomm: core bestcomm support for Freescale MPC5200
From: Grant Likely @ 2007-10-15 14:04 UTC (permalink / raw)
To: Matt Sealey; +Cc: linuxppc-dev, paulus, domen.puncer
In-Reply-To: <4713551B.9040103@genesi-usa.com>
On 10/15/07, Matt Sealey <matt@genesi-usa.com> wrote:
>
> My nits:
>
> Grant Likely wrote:
> > From: Sylvain Munaut <tnt@246tNt.com>
> > +static int __devinit
> > +bcom_engine_init(void)
>
> Why "bcom" and not "bestcomm"?
I can type 'bcom' twice as fast. :-) bcom is a suitable shortening;
I'm not concerned about it.
>
> > + /* Disable COMM Bus Prefetch, apparently it's not reliable yet */
> > + /* FIXME: This should be done on 5200 and not 5200B ... */
> > + out_be16(&bcom_eng->regs->PtdCntrl, in_be16(&bcom_eng->regs->PtdCntrl) | 1);
>
> This really, really shouldn't even be here, could it be moved to a platform
> init, or switched on a PVR/SVR here?
I think I'd like to leave it here for getting this series merged; it
may not be good to have it here; but it's not dangerous either. I'm
trying to keep churn on this series down to a minimum.
Please submit a patch to make this change once it's merged.
>
> > +int bcom_sram_init(struct device_node *sram_node, char *owner)
> > +{
> > + int rv;
> > + const u32 *regaddr_p;
> > + u64 regaddr64, size64;
> > + unsigned int psize;
> > +
> > + /* Create our state struct */
> > + if (bcom_sram) {
> > + printk(KERN_ERR "%s: bcom_sram_init: "
> > + "Already initialiwed !\n", owner);
> > + return -EBUSY;
> > + }
>
> initialised or initialized :)
fixed
>
> > + printk(KERN_ERR "%s: bcom_sram_init: "
> > + "Couln't request region !\n", owner);
> > + rv = -EBUSY;
> > + goto error_free;
>
> Couldn't or could not.
fixed; thanks.
Cheers,
g.
>
> --
> Matt Sealey <matt@genesi-usa.com>
> Genesi, Manager, Developer Relations
>
>
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH v2 2/7] rheap: Changes config mechanism
From: Kumar Gala @ 2007-10-15 14:03 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, paulus, domen.puncer
In-Reply-To: <fa686aa40710150655s37d8c7d5ye9122034f768a897@mail.gmail.com>
On Oct 15, 2007, at 8:55 AM, Grant Likely wrote:
> On 10/15/07, Kumar Gala <galak@kernel.crashing.org> wrote:
>>
>> On Oct 13, 2007, at 11:41 PM, Grant Likely wrote:
>>
>>> From: Sylvain Munaut <tnt@246tNt.com>
>>>
>>> Instead of having in the makefile all the option that
>>> requires rheap, we define a configuration symbol
>>> and when needed we make sure it's selected.
>>>
>>> Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
>>> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
>>> ---
>>>
>>> +
>>> +config PPC_LIB_RHEAP
>>
>> we should really have help for this option.
>
> This is a non-user-selectable option; none of the other
> non-user-selectable options have help text.
I don't see why we can't let users select it (saying that
differently, we should let users have this ability)
> I can add a comment; want to give me some text to squirt in there?
grab something out of the comment at the top of lib/rheap.c
- k
^ permalink raw reply
* Re: [PATCH v2 2/7] rheap: Changes config mechanism
From: Grant Likely @ 2007-10-15 13:55 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus, domen.puncer
In-Reply-To: <751956FC-6B75-416C-A62A-67915652EA51@kernel.crashing.org>
On 10/15/07, Kumar Gala <galak@kernel.crashing.org> wrote:
>
> On Oct 13, 2007, at 11:41 PM, Grant Likely wrote:
>
> > From: Sylvain Munaut <tnt@246tNt.com>
> >
> > Instead of having in the makefile all the option that
> > requires rheap, we define a configuration symbol
> > and when needed we make sure it's selected.
> >
> > Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
> > Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> > ---
> >
> > +
> > +config PPC_LIB_RHEAP
>
> we should really have help for this option.
This is a non-user-selectable option; none of the other
non-user-selectable options have help text.
I can add a comment; want to give me some text to squirt in there?
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH] powerpc: Add 1TB workaround for PA6T
From: Olof Johansson @ 2007-10-15 13:59 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <18194.62797.632192.458851@cargo.ozlabs.ibm.com>
On Mon, Oct 15, 2007 at 03:06:21PM +1000, Paul Mackerras wrote:
> Olof Johansson writes:
>
> > @@ -367,7 +368,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
> > #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
> > CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
> > CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
> > - CPU_FTR_PURR | CPU_FTR_REAL_LE)
> > + CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
> > #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
> > CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
> >
> > @@ -375,7 +376,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
> > #define CPU_FTRS_POSSIBLE \
> > (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
> > CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
> > - CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_1T_SEGMENT)
> > + CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_1T_SEGMENT | \
> > + CPU_FTR_NO_SLBIE_B)
> > #else
> > enum {
> > CPU_FTRS_POSSIBLE =
>
> I don't think the second hunk there is necessary, since
> CPU_FTRS_POSSIBLE will already get CPU_FTR_NO_SLBIE_B via
> CPU_FTRS_PA6T.
Oh, you're right. I just tacked it on with the 1T_SEGMENT.
I'll respin today. Ben wanted me to add some comments to the _switch
code as well regarding the slbie.
-Olof
^ permalink raw reply
* [PATCH v2] [POWERPC] ucc_geth: Fix build break introduced by commit 09f75cd7bf13720738e6a196cc0107ce9a5bd5a0
From: Emil Medve @ 2007-10-15 13:43 UTC (permalink / raw)
To: akpm, jgarzik, leoli, netdev, linuxppc-dev; +Cc: Emil Medve
drivers/net/ucc_geth.c: In function 'ucc_geth_rx':
drivers/net/ucc_geth.c:3483: error: 'dev' undeclared (first use in this function)
drivers/net/ucc_geth.c:3483: error: (Each undeclared identifier is reported only once
drivers/net/ucc_geth.c:3483: error: for each function it appears in.)
make[2]: *** [drivers/net/ucc_geth.o] Error 1
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
---
Here is a convenient link for the culprit patch: http://git.kernel.org/?p=linux/kernel/git/jgarzik/netdev-2.6.git;a=commit;h=09f75cd7bf13720738e6a196cc0107ce9a5bd5a0
netdev-2.6> scripts/checkpatch.pl 0001-POWERPC-ucc_geth-Fix-build-break-introduced-by-co.patch
Your patch has no obvious style problems and is ready for submission.
drivers/net/ucc_geth.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index d00e7d4..bec413b 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -63,7 +63,7 @@
#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
void uec_set_ethtool_ops(struct net_device *netdev);
-
+
static DEFINE_SPINLOCK(ugeth_lock);
static struct {
@@ -3454,9 +3454,12 @@ static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit
u16 length, howmany = 0;
u32 bd_status;
u8 *bdBuffer;
+ struct net_device * dev;
ugeth_vdbg("%s: IN", __FUNCTION__);
+ dev = ugeth->dev;
+
/* collect received buffers */
bd = ugeth->rxBd[rxQ];
--
1.5.3.GIT
^ permalink raw reply related
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