* Re: [PATCH v6 2/9] ipic: add new interrupts introduced by new chip
From: Kumar Gala @ 2007-10-18 14:56 UTC (permalink / raw)
To: Li Yang; +Cc: linuxppc-dev, paulus
In-Reply-To: <1192719847-25045-2-git-send-email-leoli@freescale.com>
On Oct 18, 2007, at 10:04 AM, Li Yang wrote:
> These interrupts are introduced by the latest Freescale SoC such as
> MPC837x. The patch also adds comment to interrupts.
>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/sysdev/ipic.c | 224 +++++++++++++++++++++++++++++++++
> +----------
> arch/powerpc/sysdev/ipic.h | 7 +-
> include/asm-powerpc/ipic.h | 12 ++-
> 3 files changed, 186 insertions(+), 57 deletions(-)
see comments:
http://ozlabs.org/pipermail/linuxppc-dev/2007-October/044636.html
- k
^ permalink raw reply
* Re: [PATCH] synchronize_irq needs a barrier
From: Herbert Xu @ 2007-10-18 14:56 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev, akpm, torvalds, linux-kernel
In-Reply-To: <1192676235.12879.40.camel@pasglop>
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>
> Take a real life example:
>
> drivers/message/fusion/mptbase.c
>
> /* Disable interrupts! */
> CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
>
> ioc->active = 0;
> synchronize_irq(pdev->irq);
>
> And we aren't in a spinlock here.
>
> That's just a random example grepped.... I think I see a few more. Then,
> some drivers like tg3 actually do an smp_mb() before calling
> synchronize_irq(). But then, some don't.
I really don't see what the point of the barrier would be here.
Barriers are generally useless unless you have a counter-part
on the other side.
The counterpart here is presumably the interrupt handler, which
should be terminated by the IO write above regardless of the
memory barrier.
Of course I might have missed your point. If so please give
a description like this for the race that you see:
CPU1 CPU2
disable IRQ
whatever the race is
synchronize_irq
> I think trying to have all drivers be correct here is asking for
> trouble, we'd rather have synchronize_irq() be uber-safe. It's not like
> it was used in hot path anyway.
While in general I'd agree with you about give latitude to
drivers, memory barriers I think is something that we can't
afford to.
The reason is that memory barries tend to come in pairs, e.g.,
CPU1 CPU2
write A
wmb
write B
read B
rmb
read A
Taking away either barrier would render the other useless.
So whenever we add only one barrier for the benefit of driver
writers who don't bother to think about barriers we may not
be helping them at all.
In any case, such writers should use easier tools like spin
locks rather than trying to go lockless.
Cheers,
--
Visit Openswan at http://www.openswan.org/
Email: Herbert Xu ~{PmV>HI~} <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH v6 9/9] add MPC837x MDS board default device tree
From: Kumar Gala @ 2007-10-18 14:58 UTC (permalink / raw)
To: Li Yang; +Cc: linuxppc-dev, paulus
In-Reply-To: <1192719847-25045-9-git-send-email-leoli@freescale.com>
On Oct 18, 2007, at 10:04 AM, Li Yang wrote:
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/boot/dts/mpc8377_mds.dts | 282 ++++++++++++++++++++++
> +++++++++
> arch/powerpc/boot/dts/mpc8378_mds.dts | 264 ++++++++++++++++++++++
> +++++++
> arch/powerpc/boot/dts/mpc8379_mds.dts | 300 ++++++++++++++++++++++
> +++++++++++
> 3 files changed, 846 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/mpc8377_mds.dts
> create mode 100644 arch/powerpc/boot/dts/mpc8378_mds.dts
> create mode 100644 arch/powerpc/boot/dts/mpc8379_mds.dts
>
> diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/
> boot/dts/mpc8377_mds.dts
> new file mode 100644
> index 0000000..154d18b
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
> @@ -0,0 +1,282 @@
> +/*
> + * MPC8377E MDS Device Tree Source
> + *
> + * Copyright 2007 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +/ {
> + model = "fsl,mpc8377emds";
> + compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + PowerPC,837x@0 {
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-line-size = <20>;
> + i-cache-line-size = <20>;
> + d-cache-size = <8000>; // L1, 32K
> + i-cache-size = <8000>; // L1, 32K
> + timebase-frequency = <0>;
> + bus-frequency = <0>;
> + clock-frequency = <0>;
> + };
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <00000000 20000000>; // 512MB at 0
> + };
> +
> + soc@e0000000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "soc";
> + ranges = <0 e0000000 00100000>;
> + reg = <e0000000 00000200>;
> + bus-frequency = <0>;
> +
> + wdt@200 {
> + compatible = "mpc83xx_wdt";
> + reg = <200 100>;
> + };
> +
> + i2c@3000 {
still missing #address-cell & #size-cells
> + device_type = "i2c";
> + compatible = "fsl-i2c";
> + reg = <3000 100>;
> + interrupts = <e 8>;
> + interrupt-parent = < &ipic >;
> + dfsrr;
> + };
> +
> + i2c@3100 {
still missing #address-cell & #size-cells
> + device_type = "i2c";
> + compatible = "fsl-i2c";
> + reg = <3100 100>;
> + interrupts = <f 8>;
> + interrupt-parent = < &ipic >;
> + dfsrr;
> + };
> +
> + spi@7000 {
> + compatible = "fsl_spi";
> + reg = <7000 1000>;
> + interrupts = <10 8>;
> + interrupt-parent = < &ipic >;
> + mode = "spi";
mode = "cpu"
> + };
- k
^ permalink raw reply
* [PATCH v6 resend 9/9] add MPC837x MDS board default device tree
From: Li Yang @ 2007-10-18 15:09 UTC (permalink / raw)
To: galak, paulus, linuxppc-dev; +Cc: Li Yang
Signed-off-by: Li Yang <leoli@freescale.com>
---
Fix a typo in previous one.
arch/powerpc/boot/dts/mpc8377_mds.dts | 282 +++++++++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8378_mds.dts | 264 +++++++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8379_mds.dts | 300 +++++++++++++++++++++++++++++++++
3 files changed, 846 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc8377_mds.dts
create mode 100644 arch/powerpc/boot/dts/mpc8378_mds.dts
create mode 100644 arch/powerpc/boot/dts/mpc8379_mds.dts
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
new file mode 100644
index 0000000..154d18b
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -0,0 +1,282 @@
+/*
+ * MPC8377E MDS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "fsl,mpc8377emds";
+ compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,837x@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>;
+ i-cache-line-size = <20>;
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; // 512MB at 0
+ };
+
+ soc@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ compatible = "mpc83xx_wdt";
+ reg = <200 100>;
+ };
+
+ i2c@3000 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <e 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <f 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ spi@7000 {
+ compatible = "fsl_spi";
+ reg = <7000 1000>;
+ interrupts = <10 8>;
+ interrupt-parent = < &ipic >;
+ mode = "cpu";
+ };
+
+ /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
+ usb@23000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-dr";
+ reg = <23000 1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = < &ipic >;
+ interrupts = <26 8>;
+ phy_type = "utmi_wide";
+ };
+
+ mdio@24520 {
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = < &ipic >;
+ interrupts = <11 8>;
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ phy3: ethernet-phy@3 {
+ interrupt-parent = < &ipic >;
+ interrupts = <12 8>;
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@24000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8 21 8 22 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy2 >;
+ };
+
+ ethernet@25000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 8 24 8 25 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy3 >;
+ };
+
+ serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <9 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ crypto@30000 {
+ model = "SEC3";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 8>;
+ interrupt-parent = < &ipic >;
+ /* Rev. 3.0 geometry */
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <000001fe>;
+ descriptor-types-mask = <03ab0ebf>;
+ };
+
+ sdhc@2e000 {
+ model = "eSDHC";
+ compatible = "fsl,esdhc";
+ reg = <2e000 1000>;
+ interrupts = <2a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ sata@18000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <18000 1000>;
+ interrupts = <2c 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes1 >;
+ };
+
+ sata@19000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <19000 1000>;
+ interrupts = <2d 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes1 >;
+ };
+
+ serdes1:serdes@e3000 {
+ compatible = "fsl,serdes";
+ reg = <e3000 100>;
+ vdd-1v;
+ protocol = "sata";
+ clock = <d#100>;
+ };
+
+ serdes2:serdes@e3100 {
+ compatible = "fsl,serdes";
+ reg = <e3100 100>;
+ vdd-1v;
+ protocol = "pcie";
+ clock = <d#100>;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: pic@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <700 100>;
+ };
+ };
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc83xx-pci", "83xx";
+ device_type = "pci";
+ };
+};
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
new file mode 100644
index 0000000..d15b2bd
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -0,0 +1,264 @@
+/*
+ * MPC8378E MDS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "fsl,mpc8378emds";
+ compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,837x@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>;
+ i-cache-line-size = <20>;
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; // 512MB at 0
+ };
+
+ soc@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ compatible = "mpc83xx_wdt";
+ reg = <200 100>;
+ };
+
+ i2c@3000 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <e 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <f 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ spi@7000 {
+ compatible = "fsl_spi";
+ reg = <7000 1000>;
+ interrupts = <10 8>;
+ interrupt-parent = < &ipic >;
+ mode = "cpu";
+ };
+
+ /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
+ usb@23000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-dr";
+ reg = <23000 1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = < &ipic >;
+ interrupts = <26 8>;
+ phy_type = "utmi_wide";
+ };
+
+ mdio@24520 {
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = < &ipic >;
+ interrupts = <11 8>;
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ phy3: ethernet-phy@3 {
+ interrupt-parent = < &ipic >;
+ interrupts = <12 8>;
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@24000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8 21 8 22 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy2 >;
+ };
+
+ ethernet@25000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 8 24 8 25 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy3 >;
+ };
+
+ serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <9 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ crypto@30000 {
+ model = "SEC3";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 8>;
+ interrupt-parent = < &ipic >;
+ /* Rev. 3.0 geometry */
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <000001fe>;
+ descriptor-types-mask = <03ab0ebf>;
+ };
+
+ sdhc@2e000 {
+ model = "eSDHC";
+ compatible = "fsl,esdhc";
+ reg = <2e000 1000>;
+ interrupts = <2a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ serdes1:serdes@e3000 {
+ compatible = "fsl,serdes";
+ reg = <e3000 100>;
+ vdd-1v;
+ protocol = "sgmii";
+ clock = <d#100>;
+ };
+
+ serdes2:serdes@e3100 {
+ compatible = "fsl,serdes";
+ reg = <e3100 100>;
+ vdd-1v;
+ protocol = "pcie";
+ clock = <d#100>;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: pic@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <700 100>;
+ };
+ };
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc83xx-pci", "83xx";
+ device_type = "pci";
+ };
+};
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
new file mode 100644
index 0000000..d6afec5
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -0,0 +1,300 @@
+/*
+ * MPC8379E MDS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "fsl,mpc8379emds";
+ compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,837x@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>;
+ i-cache-line-size = <20>;
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; // 512MB at 0
+ };
+
+ soc@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ compatible = "mpc83xx_wdt";
+ reg = <200 100>;
+ };
+
+ i2c@3000 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <e 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <f 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ spi@7000 {
+ compatible = "fsl_spi";
+ reg = <7000 1000>;
+ interrupts = <10 8>;
+ interrupt-parent = < &ipic >;
+ mode = "cpu";
+ };
+
+ /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
+ usb@23000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-dr";
+ reg = <23000 1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = < &ipic >;
+ interrupts = <26 8>;
+ phy_type = "utmi_wide";
+ };
+
+ mdio@24520 {
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = < &ipic >;
+ interrupts = <11 8>;
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ phy3: ethernet-phy@3 {
+ interrupt-parent = < &ipic >;
+ interrupts = <12 8>;
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@24000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8 21 8 22 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy2 >;
+ };
+
+ ethernet@25000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 8 24 8 25 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy3 >;
+ };
+
+ serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <9 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ crypto@30000 {
+ model = "SEC3";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 8>;
+ interrupt-parent = < &ipic >;
+ /* Rev. 3.0 geometry */
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <000001fe>;
+ descriptor-types-mask = <03ab0ebf>;
+ };
+
+ sdhc@2e000 {
+ model = "eSDHC";
+ compatible = "fsl,esdhc";
+ reg = <2e000 1000>;
+ interrupts = <2a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ sata@18000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <18000 1000>;
+ interrupts = <2c 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes1 >;
+ };
+
+ sata@19000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <19000 1000>;
+ interrupts = <2d 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes1 >;
+ };
+
+ sata@1a000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <1a000 1000>;
+ interrupts = <2e 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes2 >;
+ };
+
+ sata@1b000 {
+ model = "SATA-300";
+ compatible = "fsl,mpc8379-sata";
+ reg = <1b000 1000>;
+ interrupts = <2f 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes2 >;
+ };
+
+ serdes1:serdes@e3000 {
+ compatible = "fsl,serdes";
+ reg = <e3000 100>;
+ vdd-1v;
+ protocol = "sata";
+ clock = <d#100>;
+ };
+
+ serdes2:serdes@e3100 {
+ compatible = "fsl,serdes";
+ reg = <e3100 100>;
+ vdd-1v;
+ protocol = "sata";
+ clock = <d#100>;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: pic@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <700 100>;
+ };
+ };
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc83xx-pci", "83xx";
+ device_type = "pci";
+ };
+};
--
1.5.3.2.104.g41ef
^ permalink raw reply related
* Re: [PATCH v6 3/9] add Freescale SerDes PHY support
From: Kumar Gala @ 2007-10-18 15:00 UTC (permalink / raw)
To: Li Yang; +Cc: linuxppc-dev, paulus
In-Reply-To: <1192719847-25045-3-git-send-email-leoli@freescale.com>
On Oct 18, 2007, at 10:04 AM, Li Yang wrote:
> The SerDes(serializer/deserializer) PHY block is a new SoC block used
> in Freescale chips to support multiple serial interfaces, such as PCI
> Express, SGMII, SATA.
>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/platforms/Kconfig | 3 +
> arch/powerpc/sysdev/Makefile | 1 +
> arch/powerpc/sysdev/fsl_serdes.c | 195 +++++++++++++++++++++++++++
> +++++++++++
> 3 files changed, 199 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/sysdev/fsl_serdes.c
>
> diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/
> platforms/Kconfig
> index 229d355..0719e89 100644
> --- a/arch/powerpc/platforms/Kconfig
> +++ b/arch/powerpc/platforms/Kconfig
> @@ -315,6 +315,9 @@ config FSL_ULI1575
> config CPM
> bool
>
> +config FSL_SERDES
> + bool
> +
do you mind adding help here just something similar to the commit
comment. While a user might not see it, its useful documentation
about what this is all about.
- k
^ permalink raw reply
* Re: [PATCH v6 resend 9/9] add MPC837x MDS board default device tree
From: Kumar Gala @ 2007-10-18 15:01 UTC (permalink / raw)
To: Li Yang; +Cc: linuxppc-dev, paulus
In-Reply-To: <1192720186-25228-1-git-send-email-leoli@freescale.com>
On Oct 18, 2007, at 10:09 AM, Li Yang wrote:
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> Fix a typo in previous one.
>
> arch/powerpc/boot/dts/mpc8377_mds.dts | 282 ++++++++++++++++++++++
> +++++++++
> arch/powerpc/boot/dts/mpc8378_mds.dts | 264 ++++++++++++++++++++++
> +++++++
> arch/powerpc/boot/dts/mpc8379_mds.dts | 300 ++++++++++++++++++++++
> +++++++++++
> 3 files changed, 846 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/mpc8377_mds.dts
> create mode 100644 arch/powerpc/boot/dts/mpc8378_mds.dts
> create mode 100644 arch/powerpc/boot/dts/mpc8379_mds.dts
still has issues with the i2c nodes. (maybe v7 will be lucky)
- k
^ permalink raw reply
* qe: add ability to upload QE firmware
From: Timur Tabi @ 2007-10-18 15:08 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Timur Tabi
Define the layout of a binary blob that contains a QE firmware and instructions
on how to upload it. Add function qe_upload_microcode() to parse the blob
and perform the actual upload. Fully define 'struct rsp' in immap_qe.h to
include the actual RISC Special Registers.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
This patch applies on top of my previous patches
"qe: add function qe_clock_source" and
"ucc_geth: use rx-clock-name and tx-clock-name device tree properties".
This patch defines a new specification for a QE binary file. Please review
the specification as well as the code.
arch/powerpc/sysdev/qe_lib/qe.c | 96 +++++++++++++++++++++++++++++
include/asm-powerpc/immap_qe.h | 29 ++++++++-
include/asm-powerpc/qe.h | 128 +++++++++++++++++++++++++++++++++++++++
3 files changed, 251 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 8551e74..7ca398c 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -25,6 +25,7 @@
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/ioport.h>
+#include <linux/crc32.h>
#include <asm/irq.h>
#include <asm/page.h>
#include <asm/pgtable.h>
@@ -393,3 +394,98 @@ void *qe_muram_addr(unsigned long offset)
return (void *)&qe_immr->muram[offset];
}
EXPORT_SYMBOL(qe_muram_addr);
+
+/*
+ * Download a microcode to the I-RAM at a specific address.
+ *
+ * @firmware: pointer to qe_firmware structure
+ */
+int qe_upload_microcode(const struct qe_firmware *firmware)
+{
+ unsigned int i;
+ unsigned int j;
+ __be32 *code;
+ u32 crc;
+ size_t length = sizeof(struct qe_firmware);
+
+ /* Check the magic and version number */
+ if ((firmware->magic[0] != 'Q') || (firmware->magic[1] != 'E') ||
+ (firmware->magic[2] != 'F') || (firmware->version != 1)) {
+ printk(KERN_ERR "QE: invalid or unsupported microcode\n");
+ return -EPERM;
+ }
+
+ /* Validate the length and check if there's a CRC */
+ for (i = 0; i < firmware->count; i++)
+ length += firmware->microcode[i].count * 4;
+
+ if (firmware->length == (length + sizeof(u32))) {
+ /* Length is valid, and there's a CRC */
+ crc = be32_to_cpu(*((__be32 *) ((void *) firmware + length)));
+ if (crc != crc32(0, firmware, length)) {
+ printk(KERN_ERR "QE: firmware CRC is invalid\n");
+ return -EIO;
+ }
+ } else if (firmware->length != length) {
+ printk(KERN_ERR "QE: invalid length(s) in firware structure\n");
+ return -EPERM;
+ }
+
+ /* If there's only one microcode, then we assume it's common for all
+ RISCs, so we set the CERCR.CIR bit to share the IRAM with all RISCs.
+ This should be safe even on SOCs with only one RISC.
+
+ If there are multiple 'microcode' structures, but each one points
+ to the same microcode binary (ignoring offsets), then we also assume
+ that we want share RAM.
+ */
+ if (firmware->count == 1)
+ setbits16(&qe_immr->cp.cercr, cpu_to_be16(0x800));
+ else {
+ for (i = 1; i < firmware->count; i++)
+ if (firmware->microcode[i].code_offset !=
+ firmware->microcode[0].code_offset)
+ break;
+
+ if (i == firmware->count)
+ setbits16(&qe_immr->cp.cercr, cpu_to_be16(0x800));
+ }
+
+ if (firmware->soc.model)
+ printk(KERN_INFO "QE: uploading microcode '%s' for %u V%u.%u\n",
+ firmware->id, be16_to_cpu(firmware->soc.model),
+ firmware->soc.rev_h, firmware->soc.rev_l);
+ else
+ printk(KERN_INFO "QE: uploading microcode '%s'\n",
+ firmware->id);
+
+ for (i = 0; i < firmware->count; i++) {
+ const struct qe_microcode *ucode = &firmware->microcode[i];
+
+ code = (void *) firmware + be32_to_cpu(ucode->code_offset);
+
+ /* Use auto-increment */
+ out_be32(&qe_immr->iram.iadd, cpu_to_be32(0x80080000 |
+ be32_to_cpu(ucode->iram_offset)));
+
+ for (j = 0; j < ucode->count; j++)
+ out_be32(&qe_immr->iram.idata, be32_to_cpu(code[j]));
+
+ /* Program the traps. We program both RISCs, even on platforms
+ that only have one. This *should* be safe. */
+ for (j = 0; j < 16; j++)
+ if (ucode->traps[j]) {
+ u32 trap = be32_to_cpu(ucode->traps[j]);
+ out_be32(&qe_immr->rsp[0].tibcr[j], trap);
+ out_be32(&qe_immr->rsp[1].tibcr[j], trap);
+ }
+ }
+
+ /* Enable the traps for both RISCs. Again, on a single-RISC system,
+ this should be safe. */
+ out_be32(&qe_immr->rsp[0].eccr, cpu_to_be32(0x20800000));
+ out_be32(&qe_immr->rsp[1].eccr, cpu_to_be32(0x20800000));
+
+ return 0;
+}
+EXPORT_SYMBOL(qe_upload_microcode);
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index aba9806..d0c60c4 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -395,8 +395,33 @@ struct dbg {
/* RISC Special Registers (Trap and Breakpoint) */
struct rsp {
- u32 reg[0x40]; /* 64 32-bit registers */
-} __attribute__ ((packed));
+ __be32 tibcr[16];
+ u8 res0[64];
+ __be32 ibcr0;
+ __be32 ibs0;
+ __be32 ibcnr0;
+ u8 res1[4];
+ __be32 ibcr1;
+ __be32 ibs1;
+ __be32 ibcnr1;
+ __be32 npcr;
+ __be32 dbcr;
+ __be32 dbar;
+ __be32 dbamr;
+ __be32 dbsr;
+ __be32 dbcnr;
+ u8 res2[12];
+ __be32 dbdr_h;
+ __be32 dbdr_l;
+ __be32 dbdmr_h;
+ __be32 dbdmr_l;
+ __be32 bsr;
+ __be32 bor;
+ u8 res3[24];
+ __be32 eccr;
+ __be32 eicr;
+ u8 res4[0x100-0xf8];
+};
struct qe_immap {
struct qe_iram iram; /* I-RAM */
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 81403ee..f773280 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -94,6 +94,134 @@ unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
void qe_muram_dump(void);
void *qe_muram_addr(unsigned long offset);
+/* Structure that defines QE firmware binary files.
+ *
+ * All integers are big-endian. All lengths are in bytes.
+ *
+ * The 'length' field is the size, in bytes, of the entire structure,
+ * including all the microcode embedded in it, as well as the CRC (if
+ * present).
+ *
+ * The 'magic' field is an array of three bytes that contains the letters
+ * 'Q', 'E', and 'F'. This is an identifier that indicates that this
+ * structure is a QE Firmware structure.
+ *
+ * The 'version' field is a single byte that indicates the version of this
+ * structure. If the layout of the structure should ever need to be changed
+ * to add support for additional types of microcode, then the version number
+ * should also be changed. Currently, only version 1 (this version) is
+ * supported, so this field must be set to 1.
+ *
+ * The 'id' field is a null-terminated string suitable for printing.
+ *
+ * The 'count' field indicates the number of 'microcode' structures. If
+ * there are multiple RISC processors, then it's possible to have a
+ * different microcode for each one. This allows for three possible
+ * scenarios:
+ *
+ * 1) Single microcode common to all RISCs
+ * 2) Single microcode copied to multiple offsets, one per RISC
+ * 3) Different microcode and traps for each RISC
+ *
+ * In scenarious (1) and (2), the CERCR.CIR bit is set to 1, which allows
+ * all of IRAM to be shared among all RISC processors.
+ *
+ * The 'soc' structure contains the SOC numbers and revisions used to match
+ * the microcode to the SOC itself. Normally, the microcode loader should
+ * check the data in this structure with the SOC number and revisions, and
+ * only upload the microcode if there's a match. However, because there is
+ * no generic way to obtain the SOC model and revision, this check is not
+ * currently made.
+ *
+ * Although it is not recommended, you can specify '0' in the soc.model
+ * field to skip matching SOCs altogether.
+ *
+ * The 'model' field is a 16-bit number that matches the actual SOC. The
+ * 'rev_h' and 'rev_l' fields match the high and low bytes of the SOC
+ * revision ID.
+ *
+ * For example, to match the 8323, revision 1.0:
+ * soc.model = 8323
+ * soc.rev_h = 1
+ * soc.rev_h = 0
+ *
+ * 'reserved' is neccessary for structure alignment. This field ensures
+ * that the first element of the 'microcode' array is aligned on a 64-bit
+ * boundary.
+ *
+ * 'microcode' (type: struct qe_microcode):
+ * 'traps' is an array of 16 words that contain hardware trap values
+ * for each of the 16 traps. If trap[i] is 0, then this particular
+ * trap is to be ignored (i.e. not written to TIBCR[i]).
+ *
+ * 'vtraps' is an array of 8 words that contain virtual trap values for
+ * each virtual traps. Currently, this field is ignored.
+ *
+ * 'extended_modes' is a bitfield that defines special functionality
+ * which has an impact on the software drivers. Each bit has its own
+ * impact and has special instructions for the driver associated with
+ * it. Currently, this field is ignored.
+ *
+ * 'iram_offset' is the offset into IRAM to start writing the
+ * microcode.
+ *
+ * 'count' is the number of 32-bit words in the microcode.
+ *
+ * 'code_offset' is the offset, in bytes, from the beginning of this
+ * structure where the microcode itself can be found. The first
+ * microcode binary should be located immediately after the 'microcode'
+ * array.
+ *
+ * 'reserved' is necessary for structure alignment. Since 'microcode'
+ * is an array, the 64-bit 'extended_modes' field needs to be aligned
+ * on a 64-bit boundary, and this can only happen if the size of
+ * 'microcode' is a multiple of 8 bytes. To ensure that, we add
+ * 'reserved'.
+ *
+ * In addition, an optional 32-bit CRC can be added after the last
+ * microcode binary. The CRC is checked via the crc32() Linux kernel macro.
+ * It can be calculated using this algorithm:
+ *
+ * u32 crc32(const u8 *p, unsigned int len)
+ * {
+ * unsigned int i;
+ * u32 crc = 0;
+ *
+ * while (len--) {
+ * crc ^= *p++;
+ * for (i = 0; i < 8; i++)
+ * crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
+ * }
+ * return crc;
+ * }
+ */
+struct qe_firmware {
+ __be32 length; /* Length of the entire structure, in bytes */
+ u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
+ u8 version; /* Version of this layout. First ver is '1' */
+ u8 id[63]; /* Null-terminated identifier string */
+ u8 count; /* Number of microcode[] structures */
+ struct {
+ __be16 model; /* The SOC model */
+ u8 rev_h; /* The SOC revision */
+ u8 rev_l; /* The SOC revision */
+ } soc;
+ __be32 reserved; /* Reserved, for alignement */
+ struct qe_microcode {
+ __be32 traps[16]; /* Trap addresses, 0 == ignore */
+ __be32 vtraps[8]; /* Virtual trap addresses */
+ __be64 extended_modes; /* Extended modes */
+ __be32 iram_offset; /* Offset into I-RAM for the code */
+ __be32 count; /* Number of 32-bit words of the code */
+ __be32 code_offset; /* Offset of the actual microcode */
+ __be32 reserved; /* Reserved, for alignement */
+ } microcode[1]; /* At least one microcode */
+ /* All microcode binaries should be located here */
+ /* An optional CRC32 can be added after the microcode binaries here */
+} __attribute__ ((packed));
+
+int qe_upload_microcode(const struct qe_firmware *firmware);
+
/* Buffer descriptors */
struct qe_bd {
__be16 status;
--
1.5.2.4
^ permalink raw reply related
* RE: [PATCH v6 resend 9/9] add MPC837x MDS board default device tree
From: Li Yang-r58472 @ 2007-10-18 15:10 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus
In-Reply-To: <F1717431-3C1F-4528-9949-32C156F5DD4F@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
> Sent: Thursday, October 18, 2007 11:02 PM
> To: Li Yang-r58472
> Cc: paulus@samba.org; linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH v6 resend 9/9] add MPC837x MDS board=20
> default device tree
>=20
>=20
> On Oct 18, 2007, at 10:09 AM, Li Yang wrote:
>=20
> > Signed-off-by: Li Yang <leoli@freescale.com>
> > ---
> > Fix a typo in previous one.
> >
> > arch/powerpc/boot/dts/mpc8377_mds.dts | 282 ++++++++++++++++++++++
> > +++++++++
> > arch/powerpc/boot/dts/mpc8378_mds.dts | 264 ++++++++++++++++++++++
> > +++++++
> > arch/powerpc/boot/dts/mpc8379_mds.dts | 300 ++++++++++++++++++++++
> > +++++++++++
> > 3 files changed, 846 insertions(+), 0 deletions(-) create mode=20
> > 100644 arch/powerpc/boot/dts/mpc8377_mds.dts
> > create mode 100644 arch/powerpc/boot/dts/mpc8378_mds.dts
> > create mode 100644 arch/powerpc/boot/dts/mpc8379_mds.dts
>=20
> still has issues with the i2c nodes. (maybe v7 will be lucky)
Do we still need address-cell and size-cell even when it has no child
node?
- Leo
^ permalink raw reply
* Re: [PATCH v2 3/4] Implement clockevents driver for powerpc
From: Sergei Shtylyov @ 2007-10-18 15:11 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, Thomas Gleixner, Realtime Kernel
In-Reply-To: <18198.44590.721412.314409@cargo.ozlabs.ibm.com>
Hello.
Paul Mackerras wrote:
>>>Tony started from an earlier patch by John Stultz, not from your
>>>patches.
>> Well, that I can believe, yet the clockevents patch has traces of my
>>former work, and looking at read_persisitent_time() it looks suspiciously
>>close to my version too...
> There is basically only one reasonably way to do a lot of this stuff.
>>>The main reason your patches were rejected were that you completely
>>>broke the VDSO and the deterministic time accounting, and made no
>> That's just not true!
>> They didn't broke vDSO (to be precise it was John's patch that broke it),
>>they just removed the vDSO code known to already be broken by -rt patch for
>>several months by then. And they didn't broke determinictic accounting --
>>they just made two things mutually exclusive. I haven't yet seen how the
>>patches that were preferred dealt with it at all.
> OK. My requirement was that the clocksource/clockevent stuff and the
> VDSO were both functional. Your patch didn't meet that requirement.
Which of my patches? There were many, and only one of them dealing with
vDSO. That's reasonable to drop that patch but it's not reasonable to drop the
other ones, not directly connected to vDSO issue. One flaw doesn't make the
whole patchset bad.
And now you have incomplete read_persistent_clock() implementation for
example, god knows why it was preferred to mine -- well, it also implemented
update_persistent_clock() bit those functions haven't appeared at the same
time, so read_persistent_clock() was written by me in the .
>> Really? IMO, the harware does keep a constant interrupt rate better than
>>software.
> Well, if you have actual numbers to back that up, show them to us.
> I don't believe you would be able to measure any difference, and so I
> prefer the simplicity of only implementing the one-shot mode.
Well, that's up to you. I take it you wouldn't accept a patch
implementing auto-reload mode?
>>>Because you broke important features
>> That is *not true*.
>> And nobody had interest to fix them for months (quite strange if they're
>>so important) while I had neither time nor interest to deal with them anymore
>>having written the code that *did work*, and not only for me.
> Well, this is the difference between having a hack that works for you,
Agreed, -rt is a patchset full of hacks. :-)
> and having something that can go upstream into mainline.
It *went* upstream. Mainline wasn't my aim at that time.
> Anyway, this discussion doesn't seem to be going anywhere. If there
> are changes you want made, or any other specific concrete action you
There are. I'll have to send patches (it's not that I have time for this)
but this is surely the fastest way to get things fixed (if I don't get ignored
that is).
> want anyone to do, say so. Otherwise stop whinging.
I just wanted the reasons clarified and got what I wanted -- as I thought,
the decision behind preferring patches was somewhat biased, nobody really
cared about code quality or just wasn't familiar with hrtimers enough to judge
on the code quality...
> Paul.
WBR, Sergei
^ permalink raw reply
* RE: [PATCH v6 2/9] ipic: add new interrupts introduced by new chip
From: Li Yang-r58472 @ 2007-10-18 15:29 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus
In-Reply-To: <3551DBD0-5DCB-4ECE-8509-E99B010A6D07@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
> Sent: Thursday, October 18, 2007 10:57 PM
> To: Li Yang-r58472
> Cc: paulus@samba.org; linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH v6 2/9] ipic: add new interrupts=20
> introduced by new chip
>=20
>=20
> On Oct 18, 2007, at 10:04 AM, Li Yang wrote:
>=20
> > These interrupts are introduced by the latest Freescale SoC such as=20
> > MPC837x. The patch also adds comment to interrupts.
> >
> > Signed-off-by: Li Yang <leoli@freescale.com>
> > ---
> > arch/powerpc/sysdev/ipic.c | 224 +++++++++++++++++++++++++++++++++
> > +----------
> > arch/powerpc/sysdev/ipic.h | 7 +-
> > include/asm-powerpc/ipic.h | 12 ++-
> > 3 files changed, 186 insertions(+), 57 deletions(-)
>=20
> see comments:
>=20
> http://ozlabs.org/pipermail/linuxppc-dev/2007-October/044636.html
But you didn't answer to my feedback
http://ozlabs.org/pipermail/linuxppc-dev/2007-October/044711.html
If you are so persistent on thinking it's harmful rather than useful,
please at least attempt to persuade me.
- Leo
^ permalink raw reply
* Re: [PATCH v6 2/9] ipic: add new interrupts introduced by new chip
From: Kumar Gala @ 2007-10-18 16:16 UTC (permalink / raw)
To: Li Yang-r58472; +Cc: linuxppc-dev, paulus
In-Reply-To: <989B956029373F45A0B8AF0297081890019B5BD8@zch01exm26.fsl.freescale.net>
On Oct 18, 2007, at 10:29 AM, Li Yang-r58472 wrote:
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>> Sent: Thursday, October 18, 2007 10:57 PM
>> To: Li Yang-r58472
>> Cc: paulus@samba.org; linuxppc-dev@ozlabs.org
>> Subject: Re: [PATCH v6 2/9] ipic: add new interrupts
>> introduced by new chip
>>
>>
>> On Oct 18, 2007, at 10:04 AM, Li Yang wrote:
>>
>>> These interrupts are introduced by the latest Freescale SoC such as
>>> MPC837x. The patch also adds comment to interrupts.
>>>
>>> Signed-off-by: Li Yang <leoli@freescale.com>
>>> ---
>>> arch/powerpc/sysdev/ipic.c | 224 +++++++++++++++++++++++++++++++++
>>> +----------
>>> arch/powerpc/sysdev/ipic.h | 7 +-
>>> include/asm-powerpc/ipic.h | 12 ++-
>>> 3 files changed, 186 insertions(+), 57 deletions(-)
>>
>> see comments:
>>
>> http://ozlabs.org/pipermail/linuxppc-dev/2007-October/044636.html
>
> But you didn't answer to my feedback
> http://ozlabs.org/pipermail/linuxppc-dev/2007-October/044711.html
sorry missed this.
> If you are so persistent on thinking it's harmful rather than useful,
> please at least attempt to persuade me.
The MPC5121e users the IPIC and has different interrupt assignment.
I suggest that the UMs be updated to more useful not the code.
- k
^ permalink raw reply
* Re: qe: add ability to upload QE firmware
From: Timur Tabi @ 2007-10-18 16:39 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <11927201051427-git-send-email-timur@freescale.com>
Timur Tabi wrote:
> Define the layout of a binary blob that contains a QE firmware and instructions
> on how to upload it. Add function qe_upload_microcode() to parse the blob
> and perform the actual upload. Fully define 'struct rsp' in immap_qe.h to
> include the actual RISC Special Registers.
>
> Signed-off-by: Timur Tabi <timur@freescale.com>
I need to add a few fields to the structure, but I would still appreciate
comments on the structure and the corresponding code.
--
Timur Tabi
Linux Kernel Developer @ Freescale
^ permalink raw reply
* Re: [PATCH 1/2] qemu platform, v2
From: Milton Miller @ 2007-10-18 17:19 UTC (permalink / raw)
To: Matt Sealey; +Cc: linuxppc-dev, Paul Mackerras, Rob Landley, Christoph Hellwig
In-Reply-To: <47172E80.6090902@genesi-usa.com>
On Oct 18, 2007, at 4:59 AM, Matt Sealey wrote:
> Grant Likely wrote:
>> On 9/30/07, David Gibson <david@gibson.dropbear.id.au> wrote:
>>> On Fri, Sep 28, 2007 at 06:53:28PM +0200, Segher Boessenkool wrote:
>>>
>>> I'm working on merging dtc into the kernel tree instead.
>> I'm kind of late to this party; but I have to say I disagree. Most of
>> us are doing just fine installing the dtc tool (and mkimage tool for
>> that matter). Cloning it in the kernel tree is just asking for
>> divergence.
>
> Which begs the question; why cloning?
>
> Why can't development be MOVED to in-kernel?
Because we don't put userspace testsuites there for one.
And its a stand alone tool and should have its own packaging for a
second (ie the kernel provides the kernel and modules, but not random
user space utilities, in its tarbal).
If we say only some boards or ports are special and need to build then
I would vote for shipping asm files. If we think we need to build any
random embedded platform without installing dtc then we should merge
dtc.
PS the proposed kbuild integration is wrong; it should build it in the
subdirectory.
milton
^ permalink raw reply
* [PATCH v3] Device tree bindings for Xilinx devices
From: Grant Likely @ 2007-10-18 17:22 UTC (permalink / raw)
To: linuxppc-dev, Stephen Neuendorffer, Wolfgang Reissnegger, Leonid,
microblaze-uclinux, Josh Boyer, Arnd Bergmann
From: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
---
Documentation/powerpc/booting-without-of.txt | 264 ++++++++++++++++++++++++++
1 files changed, 264 insertions(+), 0 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index a96e853..d4dedf4 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -52,6 +52,7 @@ Table of Contents
i) Freescale QUICC Engine module (QE)
j) CFI or JEDEC memory-mapped NOR flash
k) Global Utilities Block
+ l) Xilinx IP cores
VII - Specifying interrupt information for devices
1) interrupts property
@@ -2242,6 +2243,269 @@ platforms are moved over to use the flattened-device-tree model.
available.
For Axon: 0x0000012a
+ l) Xilinx IP cores
+
+ The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
+ in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
+ of standard device types (network, serial, etc.) and miscellanious
+ devices (gpio, LCD, spi, etc). Also, since these devices are
+ implemented within the fpga fabric every instance of the device can be
+ synthesised with different options that change the behaviour.
+
+ Each IP-core has a set of parameters which the FPGA designer can use to
+ control how the core is synthesized. Historically, the EDK tool would
+ extract the device parameters relevant to device drivers and copy them
+ into an 'xparameters.h' in the form of #define symbols. This tells the
+ device drivers how the IP cores are configured, but it requres the kernel
+ to be recompiled every time the FPGA bitstream is resynthesized.
+
+ The new approach is to export the parameters into the device tree and
+ generate a new device tree each time the FPGA bitstream changes. The
+ parameters which used to be exported as #defines will now become
+ properties of the device node. In general, device nodes for IP-cores
+ will take the following form:
+
+ (name)@(base-address) {
+ compatible = "xilinx,(ip-core-name)-(HW_VER)"
+ [, (list of compatible devices), ...];
+ reg = <(baseaddr) (size)>;
+ interrupt-parent = <&interrupt-controller-phandle>;
+ interrupts = < ... >;
+ xilinx,(parameter1) = "(string-value)";
+ xilinx,(parameter2) = <(int-value)>;
+ };
+
+ (ip-core-name): the name of the ip block (given after the BEGIN
+ directive in system.mhs). Should be in lowercase
+ and all underscores '_' converted to dashes '-'.
+ (name): is derived from the "PARAMETER INSTANCE" value.
+ (parameter#): C_* parameters from system.mhs. The C_ prefix is
+ dropped from the parameter name, the name is converted
+ to lowercase and all underscore '_' characters are
+ converted to dashes '-'.
+ (baseaddr): the C_BASEADDR parameter.
+ (HW_VER): from the HW_VER parameter.
+ (size): equals C_HIGHADDR - C_BASEADDR + 1
+
+ Typically, the compatible list will include the exact IP core version
+ followed by an older IP core version which implements the same
+ interface or any other device with the same interface.
+
+ 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
+
+ For example, the following block from system.mhs:
+
+ BEGIN opb_uartlite
+ PARAMETER INSTANCE = opb_uartlite_0
+ PARAMETER HW_VER = 1.00.b
+ PARAMETER C_BAUDRATE = 115200
+ PARAMETER C_DATA_BITS = 8
+ PARAMETER C_ODD_PARITY = 0
+ PARAMETER C_USE_PARITY = 0
+ PARAMETER C_CLK_FREQ = 50000000
+ PARAMETER C_BASEADDR = 0xEC100000
+ PARAMETER C_HIGHADDR = 0xEC10FFFF
+ BUS_INTERFACE SOPB = opb_7
+ PORT OPB_Clk = CLK_50MHz
+ PORT Interrupt = opb_uartlite_0_Interrupt
+ PORT RX = opb_uartlite_0_RX
+ PORT TX = opb_uartlite_0_TX
+ PORT OPB_Rst = sys_bus_reset_0
+ END
+
+ becomes the following device tree node:
+
+ opb-uartlite-0@ec100000 {
+ device_type = "serial";
+ compatible = "xilinx,opb-uartlite-1.00.b";
+ reg = <ec100000 10000>;
+ interrupt-parent = <&opb-intc>;
+ interrupts = <1 0>; // got this from the opb_intc parameters
+ current-speed = <d#115200>; // standard serial device prop
+ clock-frequency = <d#50000000>; // standard serial device prop
+ xilinx,data-bits = <8>;
+ xilinx,odd-parity = <0>;
+ xilinx,use-parity = <0>;
+ };
+
+ Some IP cores actually implement 2 or more logical devices. In this case,
+ the device should still describe the whole IP core with a single node
+ and add a child node for each logical device. The ranges property can
+ be used to translate from parent IP-core to the registers of each device.
+ (Note: this makes the assumption that both logical devices have the same
+ bus binding. If this is not true, then separate nodes should be used for
+ each logical device). The 'cell-index' property can be used to enumerate
+ logical devices within an IP core. For example, the following is the
+ system.mhs entry for the dual ps2 controller found on the ml403 reference
+ design.
+
+ BEGIN opb_ps2_dual_ref
+ PARAMETER INSTANCE = opb_ps2_dual_ref_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_BASEADDR = 0xA9000000
+ PARAMETER C_HIGHADDR = 0xA9001FFF
+ BUS_INTERFACE SOPB = opb_v20_0
+ PORT Sys_Intr1 = ps2_1_intr
+ PORT Sys_Intr2 = ps2_2_intr
+ PORT Clkin1 = ps2_clk_rx_1
+ PORT Clkin2 = ps2_clk_rx_2
+ PORT Clkpd1 = ps2_clk_tx_1
+ PORT Clkpd2 = ps2_clk_tx_2
+ PORT Rx1 = ps2_d_rx_1
+ PORT Rx2 = ps2_d_rx_2
+ PORT Txpd1 = ps2_d_tx_1
+ PORT Txpd2 = ps2_d_tx_2
+ END
+
+ It would result in the following device tree nodes:
+
+ opb_ps2_dual_ref_0@a9000000 {
+ ranges = <0 a9000000 2000>;
+ // If this device had extra parameters, then they would
+ // go here.
+ ps2@0 {
+ compatible = "xilinx,opb-ps2-dual-ref-1.00.a";
+ reg = <0 40>;
+ interrupt-parent = <&opb-intc>;
+ interrupts = <3 0>;
+ cell-index = <0>;
+ };
+ ps2@1000 {
+ compatible = "xilinx,opb-ps2-dual-ref-1.00.a";
+ reg = <1000 40>;
+ interrupt-parent = <&opb-intc>;
+ interrupts = <3 0>;
+ cell-index = <0>;
+ };
+ };
+
+ Also, the system.mhs file defines bus attachments from the processor
+ to the devices. The device tree structure should reflect the bus
+ attachments. Again an example; this system.mhs fragment:
+
+ BEGIN ppc405_virtex4
+ PARAMETER INSTANCE = ppc405_0
+ PARAMETER HW_VER = 1.01.a
+ BUS_INTERFACE DPLB = plb_v34_0
+ BUS_INTERFACE IPLB = plb_v34_0
+ END
+
+ BEGIN opb_intc
+ PARAMETER INSTANCE = opb_intc_0
+ PARAMETER HW_VER = 1.00.c
+ PARAMETER C_BASEADDR = 0xD1000FC0
+ PARAMETER C_HIGHADDR = 0xD1000FDF
+ BUS_INTERFACE SOPB = opb_v20_0
+ END
+
+ BEGIN opb_uart16550
+ PARAMETER INSTANCE = opb_uart16550_0
+ PARAMETER HW_VER = 1.00.d
+ PARAMETER C_BASEADDR = 0xa0000000
+ PARAMETER C_HIGHADDR = 0xa0001FFF
+ BUS_INTERFACE SOPB = opb_v20_0
+ END
+
+ BEGIN plb_v34
+ PARAMETER INSTANCE = plb_v34_0
+ PARAMETER HW_VER = 1.02.a
+ END
+
+ BEGIN plb_bram_if_cntlr
+ PARAMETER INSTANCE = plb_bram_if_cntlr_0
+ PARAMETER HW_VER = 1.00.b
+ PARAMETER C_BASEADDR = 0xFFFF0000
+ PARAMETER C_HIGHADDR = 0xFFFFFFFF
+ BUS_INTERFACE SPLB = plb_v34_0
+ END
+
+ BEGIN plb2opb_bridge
+ PARAMETER INSTANCE = plb2opb_bridge_0
+ PARAMETER HW_VER = 1.01.a
+ PARAMETER C_RNG0_BASEADDR = 0x20000000
+ PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
+ PARAMETER C_RNG1_BASEADDR = 0x60000000
+ PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
+ PARAMETER C_RNG2_BASEADDR = 0x80000000
+ PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
+ PARAMETER C_RNG3_BASEADDR = 0xC0000000
+ PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
+ BUS_INTERFACE SPLB = plb_v34_0
+ BUS_INTERFACE MOPB = opb_v20_0
+ END
+
+ Gives this device tree (some properties removed for clarity):
+
+ plb-v34-0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "ibm,plb";
+ ranges; // 1:1 translation
+
+ plb-bram-if-cntrl-0@ffff0000 {
+ reg = <ffff0000 10000>;
+ }
+
+ opb-v20-0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <20000000 20000000 20000000
+ 60000000 60000000 20000000
+ 80000000 80000000 40000000
+ c0000000 c0000000 20000000>;
+
+ opb-uart16550-0@a0000000 {
+ reg = <a00000000 2000>;
+ };
+
+ opb-intc-0@d1000fc0 {
+ reg = <d1000fc0 20>;
+ };
+ };
+ };
+
+ That covers the general approach to binding xilinx IP cores into the
+ device tree. The following are bindings for specific devices:
+
+ i) Xilinx ML300 Framebuffer
+
+ Simple framebuffer device from the ML300 reference design (also on the
+ ML403 reference design as well as others).
+
+ Optional properties:
+ - resolution : <xres yres> pixel resolution of framebuffer. Some
+ implementations use a different resolution. Default
+ is <d#640 d#480>
+ - virt-resolution : <xvirt yvirt> Size of framebuffer in memory.
+ Default is <d#1024 d#480>.
+ - rotate-display (empty) : rotate display 180 degrees.
+
+ ii) Xilinx SystemACE
+
+ The Xilinx SystemACE device is used to program FPGAs from an FPGA
+ bitstream stored on a CF card. It can also be used as a generic CF
+ interface device.
+
+ Required properties:
+ - compatible : Should include "xilinx,sysace" in the list
+
+ Optional properties:
+ - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
+
+ iii) Xilinx EMAC and Xilinx TEMAC
+
+ Xilinx Ethernet devices. In addition to general xilinx properties
+ listed above, nodes for these devices should include a phy-handle
+ property, and may include other common network device properties
+ like local-mac-address.
+
+ iv) Xilinx Uartlite
+
+ Xilinx uartlite devices are simple fixed speed serial ports.
+
+ Requred properties:
+ - current-speed : Baud rate of uartlite
+
More devices will be defined as this spec matures.
VII - Specifying interrupt information for devices
^ permalink raw reply related
* Re: [PATCH 1/2] qemu platform, v2
From: Grant Likely @ 2007-10-18 17:29 UTC (permalink / raw)
To: Milton Miller
Cc: linuxppc-dev, Paul Mackerras, Rob Landley, Christoph Hellwig
In-Reply-To: <440d60abf1ef533839cf5d9beb0584c9@bga.com>
On 10/18/07, Milton Miller <miltonm@bga.com> wrote:
> On Oct 18, 2007, at 4:59 AM, Matt Sealey wrote:
> > Which begs the question; why cloning?
> >
> > Why can't development be MOVED to in-kernel?
>
> Because we don't put userspace testsuites there for one.
>
> And its a stand alone tool and should have its own packaging for a
> second (ie the kernel provides the kernel and modules, but not random
> user space utilities, in its tarbal).
>
> If we say only some boards or ports are special and need to build then
> I would vote for shipping asm files. If we think we need to build any
> random embedded platform without installing dtc then we should merge
> dtc.
I don't think we do. It's looking like there are going to be out of
tree users of dtc also (The are some patches floating around for
u-boot to use the device tree for it's own initialization). I don't
think it's unreasonable to install dtc for embedded development.
I like the idea of shipping asm files to support the qemu target; at
least until qemu gets better firmware.
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: Merge dtc
From: Milton Miller @ 2007-10-18 17:49 UTC (permalink / raw)
To: David Gibson; +Cc: ppcdev, Paul Mackerras, Sam Ravnborg
On Tue Oct 16 15:02:17 EST 2007, David Gibson wrote:
> This very large patch incorporates a copy of dtc into the kernel
> source, in arch/powerpc/boot/dtc-src. This means that dtc is no
> longer an external dependency to build kernels with configurations
> which need a dtb file.
>
> Signed-off-by: David Gibson <david at gibson.dropbear.id.au>
>
> Too big for the list, full patch at
> http://ozlabs.org/~dgibson/home/merge-dtc.patch+
So split it up. The obvious one is "here is the unique content, then
copy these files from dtc git" would have been better.
I finally went and looked at the url. The Kbuild integration is wrong.
It should build dtc in dtc-src and run the binary from there, and the
rules should be in a Kconfig as a normal host-target in that directory.
(I don't have a problem with that Kbuild including Makefie.dtc).
things like the dependancy on scripts_basic in the top level Makefile.
milton
^ permalink raw reply
* RE: [PATCH v3] Device tree bindings for Xilinx devices
From: Stephen Neuendorffer @ 2007-10-18 17:49 UTC (permalink / raw)
To: Grant Likely, linuxppc-dev, Wolfgang Reissnegger, Leonid,
microblaze-uclinux, Josh Boyer, Arnd Bergmann
In-Reply-To: <20071018172259.14948.74736.stgit@trillian.cg.shawcable.net>
=20
> -----Original Message-----
> From: Grant Likely [mailto:grant.likely@secretlab.ca]=20
> Sent: Thursday, October 18, 2007 10:23 AM
> To: linuxppc-dev@ozlabs.org; Stephen Neuendorffer; Wolfgang=20
> Reissnegger; Leonid; microblaze-uclinux@itee.uq.edu.au; Josh=20
> Boyer; Arnd Bergmann
> Subject: [PATCH v3] Device tree bindings for Xilinx devices
>=20
> From: Grant Likely <grant.likely@secretlab.ca>
>=20
> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
This is good enough for the moment, and it reflects the best we can do
right now... But:
> + (parameter#): C_* parameters from system.mhs. The C_=20
> prefix is
> + dropped from the parameter name, the=20
> name is converted
> + to lowercase and all underscore '_'=20
> characters are
> + converted to dashes '-'.
Unfortunately, xparameters don't follow this exactly, particularly for
the 'multiple logical devices' case... Maybe it's worth adding
something like: "For simple devices, the parameter name can be formed
by:"
In any event, this should essentially document what the mechanism for
generating the device trees actually does... Have you updated
gen_mhs_devtree.py to reflect all this?
> + Typically, the compatible list will include the exact IP=20
> core version
> + followed by an older IP core version which implements the same
> + interface or any other device with the same interface.
This seems to be awkward, since it means that the tree *and* the driver
will likely have long lists of compatible types. In the driver, this is
hard to maintain, and in the device tree we don't have an easy way of
knowing exactly what is compatible and what isn't anyway... It seems
better to me to have the
compatible list include the exact type (e.g. xilinx,opb-uartlite-1.00.b)
and
a generic compatibility class (e.g. xilinx,uartlite), and for the
drivers
to essentially define the gross compatibility classes. Then the driver
only has an of_match with:
.compatible =3D "xilinx,uartlite"
Steve
^ permalink raw reply
* [PATCH v3 1/2] [POWERPC] MPC8568E-MDS: create localbus node
From: Anton Vorontsov @ 2007-10-18 18:00 UTC (permalink / raw)
To: linuxppc-dev
This patch creates localbus node, moves bcsr into it, and adds
localbus to the probe path.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/boot/dts/mpc8568mds.dts | 14 +++++++++++---
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 +
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 5439437..be8d512 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -42,9 +42,17 @@
reg = <00000000 10000000>;
};
- bcsr@f8000000 {
- device_type = "board-control";
- reg = <f8000000 8000>;
+ localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8568-localbus";
+ reg = <e0005000 d8>;
+ ranges = <1 0 f8000000 0008000>;
+
+ bcsr@1,0 {
+ device_type = "board-control";
+ reg = <1 0 8000>;
+ };
};
soc8568@e0000000 {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 61b3eed..45ffca4 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -139,6 +139,7 @@ static struct of_device_id mpc85xx_ids[] = {
{ .type = "soc", },
{ .compatible = "soc", },
{ .type = "qe", },
+ { .compatible = "fsl,mpc8568-localbus", },
{},
};
--
1.5.0.6
^ permalink raw reply related
* [PATCH v3 2/2] [POWERPC] MPC8568E-MDS: add support for flash
From: Anton Vorontsov @ 2007-10-18 18:01 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <2eed9d85d53305b2b0d6e8f8287148f7a600ad19.1192730268.git.avorontsov@ru.mvista.com>
MPC8568E-MDS have 1 32MB Spansion x16 CFI flash chip. Let's use it.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/boot/dts/mpc8568mds.dts | 34 +++++++++++++++++++++++++++++++++-
1 files changed, 33 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index be8d512..758ada4 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -47,12 +47,44 @@
#size-cells = <1>;
compatible = "fsl,mpc8568-localbus";
reg = <e0005000 d8>;
- ranges = <1 0 f8000000 0008000>;
+ ranges = <1 0 f8000000 0008000
+ 0 0 fe000000 2000000>;
bcsr@1,0 {
device_type = "board-control";
reg = <1 0 8000>;
};
+
+ flash@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "Spansion,S29GL256N11TFIV2O", "cfi-flash";
+ reg = <0 0 2000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ hrcw@0 {
+ label = "hrcw";
+ reg = <0 20000>;
+ read-only;
+ };
+
+ kernel@20000 {
+ label = "kernel";
+ reg = <20000 200000>;
+ };
+
+ rootfs@220000 {
+ label = "rootfs";
+ reg = <220000 1d60000>;
+ };
+
+ uboot@1f80000 {
+ label = "u-boot";
+ reg = <1f80000 80000>;
+ read-only;
+ };
+ };
};
soc8568@e0000000 {
--
1.5.0.6
^ permalink raw reply related
* Re: [PATCH v3] Device tree bindings for Xilinx devices
From: Grant Likely @ 2007-10-18 18:12 UTC (permalink / raw)
To: Stephen Neuendorffer
Cc: Leonid, Arnd Bergmann, microblaze-uclinux, linuxppc-dev,
Wolfgang Reissnegger
In-Reply-To: <20071018174956.05D7A1AA008D@mail197-blu.bigfish.com>
On 10/18/07, Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> wrote:
>
> > -----Original Message-----
> > From: Grant Likely [mailto:grant.likely@secretlab.ca]
> > Sent: Thursday, October 18, 2007 10:23 AM
> > To: linuxppc-dev@ozlabs.org; Stephen Neuendorffer; Wolfgang
> > Reissnegger; Leonid; microblaze-uclinux@itee.uq.edu.au; Josh
> > Boyer; Arnd Bergmann
> > Subject: [PATCH v3] Device tree bindings for Xilinx devices
> >
> > From: Grant Likely <grant.likely@secretlab.ca>
> >
> > Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
>
> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
>
> This is good enough for the moment, and it reflects the best we can do
> right now... But:
>
> > + (parameter#): C_* parameters from system.mhs. The C_
> > prefix is
> > + dropped from the parameter name, the
> > name is converted
> > + to lowercase and all underscore '_'
> > characters are
> > + converted to dashes '-'.
>
> Unfortunately, xparameters don't follow this exactly, particularly for
> the 'multiple logical devices' case... Maybe it's worth adding
> something like: "For simple devices, the parameter name can be formed
> by:"
What specific parts of this are you concerned about? Examples?
>
> In any event, this should essentially document what the mechanism for
> generating the device trees actually does... Have you updated
> gen_mhs_devtree.py to reflect all this?
No; I'm looking at this as a line in the sand that we can use as a
starting point and discuss the issues.
>
> > + Typically, the compatible list will include the exact IP
> > core version
> > + followed by an older IP core version which implements the same
> > + interface or any other device with the same interface.
>
> This seems to be awkward, since it means that the tree *and* the driver
> will likely have long lists of compatible types. In the driver, this is
> hard to maintain, and in the device tree we don't have an easy way of
> knowing exactly what is compatible and what isn't anyway... It seems
> better to me to have the
> compatible list include the exact type (e.g. xilinx,opb-uartlite-1.00.b)
> and
> a generic compatibility class (e.g. xilinx,uartlite), and for the
> drivers
> to essentially define the gross compatibility classes. Then the driver
> only has an of_match with:
>
> .compatible = "xilinx,uartlite"
The problem with this is how do you define what "xilinx,uartlite" is?
For example; there have been 3 major versions of the plb_temac, and
IIRC v2 and v3 are *not* compatible. Which one is xilinx,temac?
However, this does not need to result in a long list. Basically, the
list should include the exact version of the device plus the first
version that implemented that interface. (hence it is "compatible"
with the earlier version of the device). If there are no prior
devices implementing the same device, then the compatible list has
exactly one instance. This document should probably include a list of
the well-known compatible values for each of the xilinx devices.
I used to try and come up with generic values for compatible, but it
just ends up causing problems in the long run. The concept of what is
generic changes over time, but a specific version is a known quantity.
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* [PATCH v2 0/4] [POWERPC] MPC5200: update gpt binding, add restart support
From: Marian Balakowicz @ 2007-10-18 18:44 UTC (permalink / raw)
To: linuxppc-dev
Here's the second version of MPC5200 patches, please review. Thanks!
[POWERPC] Enable restart support for lite5200 board
[POWERPC] Add restart support for mpc52xx based platforms
[POWERPC] Update device tree binding for mpc5200 gpt
[POWERPC] Add mpc52xx_find_and_map_path(), refactor utility functions
Cheers,
m.
^ permalink raw reply
* [PATCH v2 1/4] [POWERPC] Add mpc52xx_find_and_map_path(), refactor utility functions
From: Marian Balakowicz @ 2007-10-18 18:44 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071018184407.3584.3513.stgit@hekate.izotz.org>
Add helper routine mpc52xx_find_and_map_path(). Extract common code to
mpc52xx_map_node() and refactor mpc52xx_find_and_map().
Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Reviewed-by: Grant Likely <grant.likely@secretlab.ca>
---
arch/powerpc/platforms/52xx/mpc52xx_common.c | 21 +++++++++++++++++----
include/asm-powerpc/mpc52xx.h | 1 +
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index 3bc201e..74b4b41 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -19,14 +19,12 @@
#include <asm/mpc52xx.h>
-void __iomem *
-mpc52xx_find_and_map(const char *compatible)
+static void __iomem *
+mpc52xx_map_node(struct device_node *ofn)
{
- struct device_node *ofn;
const u32 *regaddr_p;
u64 regaddr64, size64;
- ofn = of_find_compatible_node(NULL, NULL, compatible);
if (!ofn)
return NULL;
@@ -42,8 +40,23 @@ mpc52xx_find_and_map(const char *compatible)
return ioremap((u32)regaddr64, (u32)size64);
}
+
+void __iomem *
+mpc52xx_find_and_map(const char *compatible)
+{
+ return mpc52xx_map_node(
+ of_find_compatible_node(NULL, NULL, compatible));
+}
+
EXPORT_SYMBOL(mpc52xx_find_and_map);
+void __iomem *
+mpc52xx_find_and_map_path(const char *path)
+{
+ return mpc52xx_map_node(of_find_node_by_path(path));
+}
+
+EXPORT_SYMBOL(mpc52xx_find_and_map_path);
/**
* mpc52xx_find_ipb_freq - Find the IPB bus frequency for a device
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
index 24751df..9cf05f9 100644
--- a/include/asm-powerpc/mpc52xx.h
+++ b/include/asm-powerpc/mpc52xx.h
@@ -242,6 +242,7 @@ struct mpc52xx_cdm {
#ifndef __ASSEMBLY__
extern void __iomem * mpc52xx_find_and_map(const char *);
+extern void __iomem * mpc52xx_find_and_map_path(const char *path);
extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
extern void mpc5200_setup_xlb_arbiter(void);
extern void mpc52xx_declare_of_platform_devices(void);
^ permalink raw reply related
* [PATCH v2 2/4] [POWERPC] Update device tree binding for mpc5200 gpt
From: Marian Balakowicz @ 2007-10-18 18:44 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071018184407.3584.3513.stgit@hekate.izotz.org>
Add 'fsl,' prefix to 'compatible' property for gpt nodes.
Add 'fsl,' prefix to empty, GPT0 specific 'has-wdt' property.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
---
.../powerpc/mpc52xx-device-tree-bindings.txt | 4 ++-
arch/powerpc/boot/dts/lite5200.dts | 26 +++++++-------------
arch/powerpc/boot/dts/lite5200b.dts | 26 +++++++-------------
drivers/char/watchdog/mpc5200_wdt.c | 3 ++
4 files changed, 23 insertions(+), 36 deletions(-)
diff --git a/Documentation/powerpc/mpc52xx-device-tree-bindings.txt b/Documentation/powerpc/mpc52xx-device-tree-bindings.txt
index e59fcbb..fedf7ef 100644
--- a/Documentation/powerpc/mpc52xx-device-tree-bindings.txt
+++ b/Documentation/powerpc/mpc52xx-device-tree-bindings.txt
@@ -185,7 +185,7 @@ bestcomm@<addr> dma-controller mpc5200-bestcomm 5200 pic also requires
Recommended soc5200 child nodes; populate as needed for your board
name device_type compatible Description
---- ----------- ---------- -----------
-gpt@<addr> gpt mpc5200-gpt General purpose timers
+gpt@<addr> gpt fsl,mpc5200-gpt General purpose timers
rtc@<addr> rtc mpc5200-rtc Real time clock
mscan@<addr> mscan mpc5200-mscan CAN bus controller
pci@<addr> pci mpc5200-pci PCI bridge
@@ -213,7 +213,7 @@ cell-index int When multiple devices are present, is the
5) General Purpose Timer nodes (child of soc5200 node)
On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board
design supports the internal wdt, then the device node for GPT0 should
-include the empty property 'has-wdt'.
+include the empty property 'fsl,has-wdt'.
6) PSC nodes (child of soc5200 node)
PSC nodes can define the optional 'port-number' property to force assignment
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index bc45f5f..6731763 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -70,18 +70,16 @@
};
gpt@600 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <0>;
reg = <600 10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
- has-wdt;
+ fsl,has-wdt;
};
gpt@610 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <1>;
reg = <610 10>;
interrupts = <1 a 0>;
@@ -89,8 +87,7 @@
};
gpt@620 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <2>;
reg = <620 10>;
interrupts = <1 b 0>;
@@ -98,8 +95,7 @@
};
gpt@630 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <3>;
reg = <630 10>;
interrupts = <1 c 0>;
@@ -107,8 +103,7 @@
};
gpt@640 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <4>;
reg = <640 10>;
interrupts = <1 d 0>;
@@ -116,8 +111,7 @@
};
gpt@650 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <5>;
reg = <650 10>;
interrupts = <1 e 0>;
@@ -125,8 +119,7 @@
};
gpt@660 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <6>;
reg = <660 10>;
interrupts = <1 f 0>;
@@ -134,8 +127,7 @@
};
gpt@670 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <7>;
reg = <670 10>;
interrupts = <1 10 0>;
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 6582c9a..b540388 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -70,18 +70,16 @@
};
gpt@600 { // General Purpose Timer
- compatible = "mpc5200b-gpt","mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <0>;
reg = <600 10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
- has-wdt;
+ fsl,has-wdt;
};
gpt@610 { // General Purpose Timer
- compatible = "mpc5200b-gpt","mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <1>;
reg = <610 10>;
interrupts = <1 a 0>;
@@ -89,8 +87,7 @@
};
gpt@620 { // General Purpose Timer
- compatible = "mpc5200b-gpt","mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <2>;
reg = <620 10>;
interrupts = <1 b 0>;
@@ -98,8 +95,7 @@
};
gpt@630 { // General Purpose Timer
- compatible = "mpc5200b-gpt","mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <3>;
reg = <630 10>;
interrupts = <1 c 0>;
@@ -107,8 +103,7 @@
};
gpt@640 { // General Purpose Timer
- compatible = "mpc5200b-gpt","mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <4>;
reg = <640 10>;
interrupts = <1 d 0>;
@@ -116,8 +111,7 @@
};
gpt@650 { // General Purpose Timer
- compatible = "mpc5200b-gpt","mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <5>;
reg = <650 10>;
interrupts = <1 e 0>;
@@ -125,8 +119,7 @@
};
gpt@660 { // General Purpose Timer
- compatible = "mpc5200b-gpt","mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <6>;
reg = <660 10>;
interrupts = <1 f 0>;
@@ -134,8 +127,7 @@
};
gpt@670 { // General Purpose Timer
- compatible = "mpc5200b-gpt","mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <7>;
reg = <670 10>;
interrupts = <1 10 0>;
diff --git a/drivers/char/watchdog/mpc5200_wdt.c b/drivers/char/watchdog/mpc5200_wdt.c
index 9cfb975..11f6a11 100644
--- a/drivers/char/watchdog/mpc5200_wdt.c
+++ b/drivers/char/watchdog/mpc5200_wdt.c
@@ -176,6 +176,8 @@ static int mpc5200_wdt_probe(struct of_device *op, const struct of_device_id *ma
has_wdt = of_get_property(op->node, "has-wdt", NULL);
if (!has_wdt)
+ has_wdt = of_get_property(op->node, "fsl,has-wdt", NULL);
+ if (!has_wdt)
return -ENODEV;
wdt = kzalloc(sizeof(*wdt), GFP_KERNEL);
@@ -254,6 +256,7 @@ static int mpc5200_wdt_shutdown(struct of_device *op)
static struct of_device_id mpc5200_wdt_match[] = {
{ .compatible = "mpc5200-gpt", },
+ { .compatible = "fsl,mpc5200-gpt", },
{},
};
static struct of_platform_driver mpc5200_wdt_driver = {
^ permalink raw reply related
* [PATCH v2 3/4] [POWERPC] Add restart support for mpc52xx based platforms
From: Marian Balakowicz @ 2007-10-18 18:44 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071018184407.3584.3513.stgit@hekate.izotz.org>
Add common helper routines: mpc52xx_map_wdt() and mpc52xx_restart().
This patch relies on Sascha Hauer's patch published in:
http://patchwork.ozlabs.org/linuxppc/patch?id=8910.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/powerpc/platforms/52xx/mpc52xx_common.c | 50 ++++++++++++++++++++++++++
include/asm-powerpc/mpc52xx.h | 3 ++
2 files changed, 53 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index 74b4b41..9850685 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -18,6 +18,13 @@
#include <asm/prom.h>
#include <asm/mpc52xx.h>
+/*
+ * This variable is mapped in mpc52xx_map_wdt() and used in mpc52xx_restart().
+ * Permanent mapping is required because mpc52xx_restart() can be called
+ * from interrupt context while node mapping (which calls ioremap())
+ * cannot be used at such point.
+ */
+static volatile struct mpc52xx_gpt *mpc52xx_wdt = NULL;
static void __iomem *
mpc52xx_map_node(struct device_node *ofn)
@@ -126,3 +133,46 @@ mpc52xx_declare_of_platform_devices(void)
"Error while probing of_platform bus\n");
}
+void __init
+mpc52xx_map_wdt(void)
+{
+ const void *has_wdt;
+ struct device_node *np;
+
+ /* mpc52xx_wdt is mapped here and used in mpc52xx_restart,
+ * possibly from a interrupt context. wdt is only implement
+ * on a gpt0, so check has-wdt property before mapping.
+ */
+ for_each_compatible_node(np, NULL, "fsl,mpc5200-gpt") {
+ has_wdt = of_get_property(np, "fsl,has-wdt", NULL);
+ if (has_wdt) {
+ mpc52xx_wdt = mpc52xx_map_node(np);
+ return;
+ }
+ }
+ for_each_compatible_node(np, NULL, "mpc5200-gpt") {
+ has_wdt = of_get_property(np, "has-wdt", NULL);
+ if (has_wdt) {
+ mpc52xx_wdt = mpc52xx_map_node(np);
+ return;
+ }
+ }
+}
+
+void
+mpc52xx_restart(char *cmd)
+{
+ local_irq_disable();
+
+ /* Turn on the watchdog and wait for it to expire.
+ * It effectively does a reset. */
+ if (mpc52xx_wdt) {
+ out_be32(&mpc52xx_wdt->mode, 0x00000000);
+ out_be32(&mpc52xx_wdt->count, 0x000000ff);
+ out_be32(&mpc52xx_wdt->mode, 0x00009004);
+ } else
+ printk("mpc52xx_restart: Can't access wdt. "
+ "Restart impossible, system halted.\n");
+
+ while (1);
+}
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
index 9cf05f9..39f619f 100644
--- a/include/asm-powerpc/mpc52xx.h
+++ b/include/asm-powerpc/mpc52xx.h
@@ -252,6 +252,9 @@ extern unsigned int mpc52xx_get_irq(void);
extern int __init mpc52xx_add_bridge(struct device_node *node);
+extern void __init mpc52xx_map_wdt(void);
+extern void mpc52xx_restart(char *cmd);
+
#endif /* __ASSEMBLY__ */
#ifdef CONFIG_PM
^ permalink raw reply related
* [PATCH v2 4/4] [POWERPC] Enable restart support for lite5200 board
From: Marian Balakowicz @ 2007-10-18 18:44 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071018184407.3584.3513.stgit@hekate.izotz.org>
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
---
arch/powerpc/platforms/52xx/lite5200.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/52xx/lite5200.c b/arch/powerpc/platforms/52xx/lite5200.c
index 65b7ae4..25d2bfa 100644
--- a/arch/powerpc/platforms/52xx/lite5200.c
+++ b/arch/powerpc/platforms/52xx/lite5200.c
@@ -145,6 +145,9 @@ static void __init lite5200_setup_arch(void)
/* Some mpc5200 & mpc5200b related configuration */
mpc5200_setup_xlb_arbiter();
+ /* Map wdt for mpc52xx_restart() */
+ mpc52xx_map_wdt();
+
#ifdef CONFIG_PM
mpc52xx_suspend.board_suspend_prepare = lite5200_suspend_prepare;
mpc52xx_suspend.board_resume_finish = lite5200_resume_finish;
@@ -183,5 +186,6 @@ define_machine(lite5200) {
.init = mpc52xx_declare_of_platform_devices,
.init_IRQ = mpc52xx_init_irq,
.get_irq = mpc52xx_get_irq,
+ .restart = mpc52xx_restart,
.calibrate_decr = generic_calibrate_decr,
};
^ permalink raw reply related
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