* Re: [PATCH v2 4/4] Freescale enhanced Local Bus Controller FCM NAND support.
From: Arnd Bergmann @ 2007-12-14 21:40 UTC (permalink / raw)
To: linuxppc-dev, avorontsov; +Cc: linux-mtd, dwmw2
In-Reply-To: <20071214195917.GA18616@localhost.localdomain>
On Friday 14 December 2007, Anton Vorontsov wrote:
> > >Maybe this desires its own header?
> >
> > It can be factored out if anything else ever uses it.
>
> It's just confusing to parse lbc-specific and nand-specific code
> placed in the same file.
In that case, you could argue for splitting the implementation into
two C files. I don't see any reason to move stuff into a header
when it's not an interface between two parts of the code, but
only describes a hardware interface used by a single driver.
Arnd <><
^ permalink raw reply
* Re: [PATCH 1/8] powerpc: prpmc2800 - Convert dts file to v1
From: David Gibson @ 2007-12-14 22:03 UTC (permalink / raw)
To: Mark A. Greer; +Cc: linuxppc-dev
In-Reply-To: <20071211003738.GB4995@mag.az.mvista.com>
On Mon, Dec 10, 2007 at 05:37:38PM -0700, Mark A. Greer wrote:
> From: Mark A. Greer <mgreer@mvista.com>
>
> Convert the prpmc2800.dts file to dts-v1. Basically, this means
> converting the numeric constants to be 'C'-like (e.g., hexadecimal
> numbers start with '0x').
[snip]
> interrupt-parent = <&/mv64x60/pic>;
If you're converting to dts-v1, you should also convert any path
references like this to &{/mv64x60/pic} or else use a label. Yes,
some early dts-v1 supporting dtc versions supported these as is, but
the idea is to try to forget that they existed and always require the
{} quoting in dts-v1.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 2/3] mpc82xx: Embedded Planet EP8248E support
From: David Gibson @ 2007-12-14 22:10 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20071214155341.GB16269@ld0162-tx32.am.freescale.net>
On Fri, Dec 14, 2007 at 09:53:41AM -0600, Scott Wood wrote:
> On Thu, Dec 13, 2007 at 11:19:33PM -0600, Kumar Gala wrote:
> > Can we make this a /dts-v1/; since its new.
>
> It's not really new; it's just been collecting dust for a while. :-P
>
> Are there any tools to autoconvert (preferably without losing
> comments)?
dtc itself can convert, but it will lose comments, alas. There's not
really any reasonable way it can be changed to preserve comments.
dtc -I dts -O dts foo.dts
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* [PATCH v3 4/4] Freescale enhanced Local Bus Controller FCM NAND support.
From: Scott Wood @ 2007-12-14 22:17 UTC (permalink / raw)
To: dwmw2; +Cc: linuxppc-dev, linux-mtd
Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
Fixed some formatting issues, removed some leftover debugging cruft,
and added a comment about potential conflicts in the interrupt handling.
drivers/mtd/nand/Kconfig | 9 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/fsl_elbc_nand.c | 1236 ++++++++++++++++++++++++++++++++++++++
3 files changed, 1246 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/fsl_elbc_nand.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 246d451..05d976c 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -306,4 +306,13 @@ config MTD_ALAUDA
These two (and possibly other) Alauda-based cardreaders for
SmartMedia and xD allow raw flash access.
+config MTD_NAND_FSL_ELBC
+ tristate "NAND support for Freescale eLBC controllers"
+ depends on MTD_NAND && PPC_OF
+ help
+ Various Freescale chips, including the 8313, include a NAND Flash
+ Controller Module with built-in hardware ECC capabilities.
+ Enabling this option will enable you to use this to control
+ external NAND devices.
+
endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 3ad6c01..d0d4de2 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -29,5 +29,6 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
obj-$(CONFIG_MTD_ALAUDA) += alauda.o
+obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
new file mode 100644
index 0000000..001c32c
--- /dev/null
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -0,0 +1,1236 @@
+/* Freescale Enhanced Local Bus Controller NAND driver
+ *
+ * Copyright (c) 2006-2007 Freescale Semiconductor
+ *
+ * Authors: Nick Spence <nick.spence@freescale.com>,
+ * Scott Wood <scottwood@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/io.h>
+
+
+#define MAX_BANKS 8
+#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
+#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
+
+struct elbc_bank {
+ __be32 br; /**< Base Register */
+#define BR_BA 0xFFFF8000
+#define BR_BA_SHIFT 15
+#define BR_PS 0x00001800
+#define BR_PS_SHIFT 11
+#define BR_PS_8 0x00000800 /* Port Size 8 bit */
+#define BR_PS_16 0x00001000 /* Port Size 16 bit */
+#define BR_PS_32 0x00001800 /* Port Size 32 bit */
+#define BR_DECC 0x00000600
+#define BR_DECC_SHIFT 9
+#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
+#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
+#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
+#define BR_WP 0x00000100
+#define BR_WP_SHIFT 8
+#define BR_MSEL 0x000000E0
+#define BR_MSEL_SHIFT 5
+#define BR_MS_GPCM 0x00000000 /* GPCM */
+#define BR_MS_FCM 0x00000020 /* FCM */
+#define BR_MS_SDRAM 0x00000060 /* SDRAM */
+#define BR_MS_UPMA 0x00000080 /* UPMA */
+#define BR_MS_UPMB 0x000000A0 /* UPMB */
+#define BR_MS_UPMC 0x000000C0 /* UPMC */
+#define BR_V 0x00000001
+#define BR_V_SHIFT 0
+#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+
+ __be32 or; /**< Base Register */
+#define OR0 0x5004
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_FCM_AM 0xFFFF8000
+#define OR_FCM_AM_SHIFT 15
+#define OR_FCM_BCTLD 0x00001000
+#define OR_FCM_BCTLD_SHIFT 12
+#define OR_FCM_PGS 0x00000400
+#define OR_FCM_PGS_SHIFT 10
+#define OR_FCM_CSCT 0x00000200
+#define OR_FCM_CSCT_SHIFT 9
+#define OR_FCM_CST 0x00000100
+#define OR_FCM_CST_SHIFT 8
+#define OR_FCM_CHT 0x00000080
+#define OR_FCM_CHT_SHIFT 7
+#define OR_FCM_SCY 0x00000070
+#define OR_FCM_SCY_SHIFT 4
+#define OR_FCM_SCY_1 0x00000010
+#define OR_FCM_SCY_2 0x00000020
+#define OR_FCM_SCY_3 0x00000030
+#define OR_FCM_SCY_4 0x00000040
+#define OR_FCM_SCY_5 0x00000050
+#define OR_FCM_SCY_6 0x00000060
+#define OR_FCM_SCY_7 0x00000070
+#define OR_FCM_RST 0x00000008
+#define OR_FCM_RST_SHIFT 3
+#define OR_FCM_TRLX 0x00000004
+#define OR_FCM_TRLX_SHIFT 2
+#define OR_FCM_EHTR 0x00000002
+#define OR_FCM_EHTR_SHIFT 1
+};
+
+struct elbc_regs {
+ struct elbc_bank bank[8];
+ u8 res0[0x28];
+ __be32 mar; /**< UPM Address Register */
+ u8 res1[0x4];
+ __be32 mamr; /**< UPMA Mode Register */
+ __be32 mbmr; /**< UPMB Mode Register */
+ __be32 mcmr; /**< UPMC Mode Register */
+ u8 res2[0x8];
+ __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
+ __be32 mdr; /**< UPM Data Register */
+ u8 res3[0x4];
+ __be32 lsor; /**< Special Operation Initiation Register */
+ __be32 lsdmr; /**< SDRAM Mode Register */
+ u8 res4[0x8];
+ __be32 lurt; /**< UPM Refresh Timer */
+ __be32 lsrt; /**< SDRAM Refresh Timer */
+ u8 res5[0x8];
+ __be32 ltesr; /**< Transfer Error Status Register */
+#define LTESR_BM 0x80000000
+#define LTESR_FCT 0x40000000
+#define LTESR_PAR 0x20000000
+#define LTESR_WP 0x04000000
+#define LTESR_ATMW 0x00800000
+#define LTESR_ATMR 0x00400000
+#define LTESR_CS 0x00080000
+#define LTESR_CC 0x00000001
+#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+ __be32 ltedr; /**< Transfer Error Disable Register */
+ __be32 lteir; /**< Transfer Error Interrupt Register */
+ __be32 lteatr; /**< Transfer Error Attributes Register */
+ __be32 ltear; /**< Transfer Error Address Register */
+ u8 res6[0xC];
+ __be32 lbcr; /**< Configuration Register */
+#define LBCR_LDIS 0x80000000
+#define LBCR_LDIS_SHIFT 31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT 22
+#define LBCR_AHD 0x00200000
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT 17
+#define LBCR_EPAR 0x00010000
+#define LBCR_EPAR_SHIFT 16
+#define LBCR_BMT 0x0000FF00
+#define LBCR_BMT_SHIFT 8
+#define LBCR_INIT 0x00040000
+ __be32 lcrr; /**< Clock Ratio Register */
+#define LCRR_DBYP 0x80000000
+#define LCRR_DBYP_SHIFT 31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT 28
+#define LCRR_ECL 0x03000000
+#define LCRR_ECL_SHIFT 24
+#define LCRR_EADC 0x00030000
+#define LCRR_EADC_SHIFT 16
+#define LCRR_CLKDIV 0x0000000F
+#define LCRR_CLKDIV_SHIFT 0
+ u8 res7[0x8];
+ __be32 fmr; /**< Flash Mode Register */
+#define FMR_CWTO 0x0000F000
+#define FMR_CWTO_SHIFT 12
+#define FMR_BOOT 0x00000800
+#define FMR_ECCM 0x00000100
+#define FMR_AL 0x00000030
+#define FMR_AL_SHIFT 4
+#define FMR_OP 0x00000003
+#define FMR_OP_SHIFT 0
+ __be32 fir; /**< Flash Instruction Register */
+#define FIR_OP0 0xF0000000
+#define FIR_OP0_SHIFT 28
+#define FIR_OP1 0x0F000000
+#define FIR_OP1_SHIFT 24
+#define FIR_OP2 0x00F00000
+#define FIR_OP2_SHIFT 20
+#define FIR_OP3 0x000F0000
+#define FIR_OP3_SHIFT 16
+#define FIR_OP4 0x0000F000
+#define FIR_OP4_SHIFT 12
+#define FIR_OP5 0x00000F00
+#define FIR_OP5_SHIFT 8
+#define FIR_OP6 0x000000F0
+#define FIR_OP6_SHIFT 4
+#define FIR_OP7 0x0000000F
+#define FIR_OP7_SHIFT 0
+#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
+#define FIR_OP_CA 0x1 /* Issue current column address */
+#define FIR_OP_PA 0x2 /* Issue current block+page address */
+#define FIR_OP_UA 0x3 /* Issue user defined address */
+#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
+#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
+ __be32 fcr; /**< Flash Command Register */
+#define FCR_CMD0 0xFF000000
+#define FCR_CMD0_SHIFT 24
+#define FCR_CMD1 0x00FF0000
+#define FCR_CMD1_SHIFT 16
+#define FCR_CMD2 0x0000FF00
+#define FCR_CMD2_SHIFT 8
+#define FCR_CMD3 0x000000FF
+#define FCR_CMD3_SHIFT 0
+ __be32 fbar; /**< Flash Block Address Register */
+#define FBAR_BLK 0x00FFFFFF
+ __be32 fpar; /**< Flash Page Address Register */
+#define FPAR_SP_PI 0x00007C00
+#define FPAR_SP_PI_SHIFT 10
+#define FPAR_SP_MS 0x00000200
+#define FPAR_SP_CI 0x000001FF
+#define FPAR_SP_CI_SHIFT 0
+#define FPAR_LP_PI 0x0003F000
+#define FPAR_LP_PI_SHIFT 12
+#define FPAR_LP_MS 0x00000800
+#define FPAR_LP_CI 0x000007FF
+#define FPAR_LP_CI_SHIFT 0
+ __be32 fbcr; /**< Flash Byte Count Register */
+#define FBCR_BC 0x00000FFF
+ u8 res11[0x8];
+ u8 res8[0xF00];
+};
+
+struct fsl_elbc_ctrl;
+
+/* mtd information per set */
+
+struct fsl_elbc_mtd {
+ struct mtd_info mtd;
+ struct nand_chip chip;
+ struct fsl_elbc_ctrl *ctrl;
+
+ struct device *dev;
+ int bank; /* Chip select bank number */
+ u8 __iomem *vbase; /* Chip select base virtual address */
+ int page_size; /* NAND page size (0=512, 1=2048) */
+ unsigned int fmr; /* FCM Flash Mode Register value */
+};
+
+/* overview of the fsl elbc controller */
+
+struct fsl_elbc_ctrl {
+ struct nand_hw_control controller;
+ struct fsl_elbc_mtd *chips[MAX_BANKS];
+
+ /* device info */
+ struct device *dev;
+ struct elbc_regs __iomem *regs;
+ int irq;
+ wait_queue_head_t irq_wait;
+ unsigned int irq_status; /* status read from LTESR by irq handler */
+ u8 __iomem *addr; /* Address of assigned FCM buffer */
+ unsigned int page; /* Last page written to / read from */
+ unsigned int read_bytes; /* Number of bytes read during command */
+ unsigned int column; /* Saved column from SEQIN */
+ unsigned int index; /* Pointer to next byte to 'read' */
+ unsigned int status; /* status read from LTESR after last op */
+ unsigned int mdr; /* UPM/FCM Data Register value */
+ unsigned int use_mdr; /* Non zero if the MDR is to be set */
+ unsigned int oob; /* Non zero if operating on OOB data */
+ char *oob_poi; /* Place to write ECC after read back */
+};
+
+/* These map to the positions used by the FCM hardware ECC generator */
+
+/* Small Page FLASH with FMR[ECCM] = 0 */
+static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
+ .eccbytes = 3,
+ .eccpos = {6, 7, 8},
+ .oobfree = { {0, 5}, {9, 7} },
+ .oobavail = 12,
+};
+
+/* Small Page FLASH with FMR[ECCM] = 1 */
+static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
+ .eccbytes = 3,
+ .eccpos = {8, 9, 10},
+ .oobfree = { {0, 5}, {6, 2}, {11, 5} },
+ .oobavail = 12,
+};
+
+/* Large Page FLASH with FMR[ECCM] = 0 */
+static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
+ .eccbytes = 12,
+ .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
+ .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
+ .oobavail = 48,
+};
+
+/* Large Page FLASH with FMR[ECCM] = 1 */
+static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
+ .eccbytes = 12,
+ .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
+ .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
+ .oobavail = 48,
+};
+
+/*=================================*/
+
+/*
+ * Set up the FCM hardware block and page address fields, and the fcm
+ * structure addr field to point to the correct FCM buffer in memory
+ */
+static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct elbc_regs __iomem *lbc = ctrl->regs;
+ int buf_num;
+
+ ctrl->page = page_addr;
+
+ out_be32(&lbc->fbar,
+ page_addr >> (chip->phys_erase_shift - chip->page_shift));
+
+ if (priv->page_size) {
+ out_be32(&lbc->fpar,
+ ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
+ (oob ? FPAR_LP_MS : 0) | column);
+ buf_num = (page_addr & 1) << 2;
+ } else {
+ out_be32(&lbc->fpar,
+ ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
+ (oob ? FPAR_SP_MS : 0) | column);
+ buf_num = page_addr & 7;
+ }
+
+ ctrl->addr = priv->vbase + buf_num * 1024;
+ ctrl->index = column;
+
+ /* for OOB data point to the second half of the buffer */
+ if (oob)
+ ctrl->index += priv->page_size ? 2048 : 512;
+
+ dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
+ "index %x, pes %d ps %d\n",
+ buf_num, ctrl->addr, priv->vbase, ctrl->index,
+ chip->phys_erase_shift, chip->page_shift);
+}
+
+/*
+ * execute FCM command and wait for it to complete
+ */
+static int fsl_elbc_run_command(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct elbc_regs __iomem *lbc = ctrl->regs;
+
+ /* Setup the FMR[OP] to execute without write protection */
+ out_be32(&lbc->fmr, priv->fmr | 3);
+ if (ctrl->use_mdr)
+ out_be32(&lbc->mdr, ctrl->mdr);
+
+ dev_vdbg(ctrl->dev,
+ "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
+ in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
+ dev_vdbg(ctrl->dev,
+ "fsl_elbc_run_command: fbar=%08x fpar=%08x "
+ "fbcr=%08x bank=%d\n",
+ in_be32(&lbc->fbar), in_be32(&lbc->fpar),
+ in_be32(&lbc->fbcr), priv->bank);
+
+ /* execute special operation */
+ out_be32(&lbc->lsor, priv->bank);
+
+ /* wait for FCM complete flag or timeout */
+ ctrl->irq_status = 0;
+ wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
+ FCM_TIMEOUT_MSECS * HZ/1000);
+ ctrl->status = ctrl->irq_status;
+
+ /* store mdr value in case it was needed */
+ if (ctrl->use_mdr)
+ ctrl->mdr = in_be32(&lbc->mdr);
+
+ ctrl->use_mdr = 0;
+
+ dev_vdbg(ctrl->dev,
+ "fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
+ ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
+
+ /* returns 0 on success otherwise non-zero) */
+ return ctrl->status == LTESR_CC ? 0 : -EIO;
+}
+
+static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
+{
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct elbc_regs __iomem *lbc = ctrl->regs;
+
+ if (priv->page_size) {
+ out_be32(&lbc->fir,
+ (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_CA << FIR_OP1_SHIFT) |
+ (FIR_OP_PA << FIR_OP2_SHIFT) |
+ (FIR_OP_CW1 << FIR_OP3_SHIFT) |
+ (FIR_OP_RBW << FIR_OP4_SHIFT));
+
+ out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
+ (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
+ } else {
+ out_be32(&lbc->fir,
+ (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_CA << FIR_OP1_SHIFT) |
+ (FIR_OP_PA << FIR_OP2_SHIFT) |
+ (FIR_OP_RBW << FIR_OP3_SHIFT));
+
+ if (oob)
+ out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
+ else
+ out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
+ }
+}
+
+/* cmdfunc send commands to the FCM */
+static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct elbc_regs __iomem *lbc = ctrl->regs;
+
+ ctrl->use_mdr = 0;
+
+ /* clear the read buffer */
+ ctrl->read_bytes = 0;
+ if (command != NAND_CMD_PAGEPROG)
+ ctrl->index = 0;
+
+ switch (command) {
+ /* READ0 and READ1 read the entire buffer to use hardware ECC. */
+ case NAND_CMD_READ1:
+ column += 256;
+
+ /* fall-through */
+ case NAND_CMD_READ0:
+ dev_dbg(ctrl->dev,
+ "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
+ " 0x%x, column: 0x%x.\n", page_addr, column);
+
+
+ out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
+ set_addr(mtd, 0, page_addr, 0);
+
+ ctrl->read_bytes = mtd->writesize + mtd->oobsize;
+ ctrl->index += column;
+
+ fsl_elbc_do_read(chip, 0);
+ fsl_elbc_run_command(mtd);
+ return;
+
+ /* READOOB reads only the OOB because no ECC is performed. */
+ case NAND_CMD_READOOB:
+ dev_vdbg(ctrl->dev,
+ "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
+ " 0x%x, column: 0x%x.\n", page_addr, column);
+
+ out_be32(&lbc->fbcr, mtd->oobsize - column);
+ set_addr(mtd, column, page_addr, 1);
+
+ ctrl->read_bytes = mtd->writesize + mtd->oobsize;
+
+ fsl_elbc_do_read(chip, 1);
+ fsl_elbc_run_command(mtd);
+ return;
+
+ /* READID must read all 5 possible bytes while CEB is active */
+ case NAND_CMD_READID:
+ dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
+
+ out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_UA << FIR_OP1_SHIFT) |
+ (FIR_OP_RBW << FIR_OP2_SHIFT));
+ out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
+ /* 5 bytes for manuf, device and exts */
+ out_be32(&lbc->fbcr, 5);
+ ctrl->read_bytes = 5;
+ ctrl->use_mdr = 1;
+ ctrl->mdr = 0;
+
+ set_addr(mtd, 0, 0, 0);
+ fsl_elbc_run_command(mtd);
+ return;
+
+ /* ERASE1 stores the block and page address */
+ case NAND_CMD_ERASE1:
+ dev_vdbg(ctrl->dev,
+ "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
+ "page_addr: 0x%x.\n", page_addr);
+ set_addr(mtd, 0, page_addr, 0);
+ return;
+
+ /* ERASE2 uses the block and page address from ERASE1 */
+ case NAND_CMD_ERASE2:
+ dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
+
+ out_be32(&lbc->fir,
+ (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_PA << FIR_OP1_SHIFT) |
+ (FIR_OP_CM1 << FIR_OP2_SHIFT));
+
+ out_be32(&lbc->fcr,
+ (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
+ (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
+
+ out_be32(&lbc->fbcr, 0);
+ ctrl->read_bytes = 0;
+
+ fsl_elbc_run_command(mtd);
+ return;
+
+ /* SEQIN sets up the addr buffer and all registers except the length */
+ case NAND_CMD_SEQIN: {
+ __be32 fcr;
+ dev_vdbg(ctrl->dev,
+ "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
+ "page_addr: 0x%x, column: 0x%x.\n",
+ page_addr, column);
+
+ ctrl->column = column;
+ ctrl->oob = 0;
+
+ fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
+ (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
+
+ if (priv->page_size) {
+ out_be32(&lbc->fir,
+ (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_CA << FIR_OP1_SHIFT) |
+ (FIR_OP_PA << FIR_OP2_SHIFT) |
+ (FIR_OP_WB << FIR_OP3_SHIFT) |
+ (FIR_OP_CW1 << FIR_OP4_SHIFT));
+
+ fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
+ } else {
+ out_be32(&lbc->fir,
+ (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_CM2 << FIR_OP1_SHIFT) |
+ (FIR_OP_CA << FIR_OP2_SHIFT) |
+ (FIR_OP_PA << FIR_OP3_SHIFT) |
+ (FIR_OP_WB << FIR_OP4_SHIFT) |
+ (FIR_OP_CW1 << FIR_OP5_SHIFT));
+
+ if (column >= mtd->writesize) {
+ /* OOB area --> READOOB */
+ column -= mtd->writesize;
+ fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
+ ctrl->oob = 1;
+ } else if (column < 256) {
+ /* First 256 bytes --> READ0 */
+ fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
+ } else {
+ /* Second 256 bytes --> READ1 */
+ fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
+ }
+ }
+
+ out_be32(&lbc->fcr, fcr);
+ set_addr(mtd, column, page_addr, ctrl->oob);
+ return;
+ }
+
+ /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
+ case NAND_CMD_PAGEPROG: {
+ int full_page;
+ dev_vdbg(ctrl->dev,
+ "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
+ "writing %d bytes.\n", ctrl->index);
+
+ /* if the write did not start at 0 or is not a full page
+ * then set the exact length, otherwise use a full page
+ * write so the HW generates the ECC.
+ */
+ if (ctrl->oob || ctrl->column != 0 ||
+ ctrl->index != mtd->writesize + mtd->oobsize) {
+ out_be32(&lbc->fbcr, ctrl->index);
+ full_page = 0;
+ } else {
+ out_be32(&lbc->fbcr, 0);
+ full_page = 1;
+ }
+
+ fsl_elbc_run_command(mtd);
+
+ /* Read back the page in order to fill in the ECC for the
+ * caller. Is this really needed?
+ */
+ if (full_page && ctrl->oob_poi) {
+ out_be32(&lbc->fbcr, 3);
+ set_addr(mtd, 6, page_addr, 1);
+
+ ctrl->read_bytes = mtd->writesize + 9;
+
+ fsl_elbc_do_read(chip, 1);
+ fsl_elbc_run_command(mtd);
+
+ memcpy_fromio(ctrl->oob_poi + 6,
+ &ctrl->addr[ctrl->index], 3);
+ ctrl->index += 3;
+ }
+
+ ctrl->oob_poi = NULL;
+ return;
+ }
+
+ /* CMD_STATUS must read the status byte while CEB is active */
+ /* Note - it does not wait for the ready line */
+ case NAND_CMD_STATUS:
+ out_be32(&lbc->fir,
+ (FIR_OP_CM0 << FIR_OP0_SHIFT) |
+ (FIR_OP_RBW << FIR_OP1_SHIFT));
+ out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
+ out_be32(&lbc->fbcr, 1);
+ set_addr(mtd, 0, 0, 0);
+ ctrl->read_bytes = 1;
+
+ fsl_elbc_run_command(mtd);
+
+ /* The chip always seems to report that it is
+ * write-protected, even when it is not.
+ */
+ setbits8(ctrl->addr, NAND_STATUS_WP);
+ return;
+
+ /* RESET without waiting for the ready line */
+ case NAND_CMD_RESET:
+ dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
+ out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
+ out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
+ fsl_elbc_run_command(mtd);
+ return;
+
+ default:
+ dev_err(ctrl->dev,
+ "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
+ command);
+ }
+}
+
+static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
+{
+ /* The hardware does not seem to support multiple
+ * chips per bank.
+ */
+}
+
+/*
+ * Write buf to the FCM Controller Data Buffer
+ */
+static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ unsigned int bufsize = mtd->writesize + mtd->oobsize;
+
+ if (len < 0) {
+ dev_err(ctrl->dev, "write_buf of %d bytes", len);
+ ctrl->status = 0;
+ return;
+ }
+
+ if ((unsigned int)len > bufsize - ctrl->index) {
+ dev_err(ctrl->dev,
+ "write_buf beyond end of buffer "
+ "(%d requested, %u available)\n",
+ len, bufsize - ctrl->index);
+ len = bufsize - ctrl->index;
+ }
+
+ memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
+ ctrl->index += len;
+}
+
+/*
+ * read a byte from either the FCM hardware buffer if it has any data left
+ * otherwise issue a command to read a single byte.
+ */
+static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+
+ /* If there are still bytes in the FCM, then use the next byte. */
+ if (ctrl->index < ctrl->read_bytes)
+ return in_8(&ctrl->addr[ctrl->index++]);
+
+ dev_err(ctrl->dev, "read_byte beyond end of buffer\n");
+ return ERR_BYTE;
+}
+
+/*
+ * Read from the FCM Controller Data Buffer
+ */
+static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ int avail;
+
+ if (len < 0)
+ return;
+
+ avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
+ memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
+ ctrl->index += avail;
+
+ if (len > avail)
+ dev_err(ctrl->dev,
+ "read_buf beyond end of buffer "
+ "(%d requested, %d available)\n",
+ len, avail);
+}
+
+/*
+ * Verify buffer against the FCM Controller Data Buffer
+ */
+static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ int i;
+
+ if (len < 0) {
+ dev_err(ctrl->dev, "write_buf of %d bytes", len);
+ return -EINVAL;
+ }
+
+ if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
+ dev_err(ctrl->dev,
+ "verify_buf beyond end of buffer "
+ "(%d requested, %u available)\n",
+ len, ctrl->read_bytes - ctrl->index);
+
+ ctrl->index = ctrl->read_bytes;
+ return -EINVAL;
+ }
+
+ for (i = 0; i < len; i++)
+ if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
+ break;
+
+ ctrl->index += len;
+ return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
+}
+
+/* This function is called after Program and Erase Operations to
+ * check for success or failure.
+ */
+static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct elbc_regs __iomem *lbc = ctrl->regs;
+
+ if (ctrl->status != LTESR_CC)
+ return NAND_STATUS_FAIL;
+
+ /* Use READ_STATUS command, but wait for the device to be ready */
+ ctrl->use_mdr = 0;
+ out_be32(&lbc->fir,
+ (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_RBW << FIR_OP1_SHIFT));
+ out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
+ out_be32(&lbc->fbcr, 1);
+ set_addr(mtd, 0, 0, 0);
+ ctrl->read_bytes = 1;
+
+ fsl_elbc_run_command(mtd);
+
+ if (ctrl->status != LTESR_CC)
+ return NAND_STATUS_FAIL;
+
+ /* The chip always seems to report that it is
+ * write-protected, even when it is not.
+ */
+ setbits8(ctrl->addr, NAND_STATUS_WP);
+ return fsl_elbc_read_byte(mtd);
+}
+
+static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct elbc_regs __iomem *lbc = ctrl->regs;
+ unsigned int al;
+
+ /* calculate FMR Address Length field */
+ al = 0;
+ if (chip->pagemask & 0xffff0000)
+ al++;
+ if (chip->pagemask & 0xff000000)
+ al++;
+
+ /* add to ECCM mode set in fsl_elbc_init */
+ priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
+ (al << FMR_AL_SHIFT);
+
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n",
+ chip->numchips);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %ld\n",
+ chip->chipsize);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
+ chip->pagemask);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
+ chip->chip_delay);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
+ chip->badblockpos);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
+ chip->chip_shift);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n",
+ chip->page_shift);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
+ chip->phys_erase_shift);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
+ chip->ecclayout);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
+ chip->ecc.mode);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
+ chip->ecc.steps);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
+ chip->ecc.bytes);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
+ chip->ecc.total);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
+ chip->ecc.layout);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %d\n", mtd->size);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
+ mtd->erasesize);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n",
+ mtd->writesize);
+ dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
+ mtd->oobsize);
+
+ /* adjust Option Register and ECC to match Flash page size */
+ if (mtd->writesize == 512) {
+ priv->page_size = 0;
+ clrbits32(&lbc->bank[priv->bank].or, ~OR_FCM_PGS);
+ } else if (mtd->writesize == 2048) {
+ priv->page_size = 1;
+ setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
+ /* adjust ecc setup if needed */
+ if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
+ BR_DECC_CHK_GEN) {
+ chip->ecc.size = 512;
+ chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
+ &fsl_elbc_oob_lp_eccm1 :
+ &fsl_elbc_oob_lp_eccm0;
+ mtd->ecclayout = chip->ecc.layout;
+ mtd->oobavail = chip->ecc.layout->oobavail;
+ }
+ } else {
+ dev_err(ctrl->dev,
+ "fsl_elbc_init: page size %d is not supported\n",
+ mtd->writesize);
+ return -1;
+ }
+
+ /* The default u-boot configuration on MPC8313ERDB causes errors;
+ * more delay is needed. This should be safe for other boards
+ * as well.
+ */
+ setbits32(&lbc->bank[priv->bank].or, 0x70);
+ return 0;
+}
+
+static int fsl_elbc_read_page(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ uint8_t *buf)
+{
+ fsl_elbc_read_buf(mtd, buf, mtd->writesize);
+ fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+ if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
+ mtd->ecc_stats.failed++;
+
+ return 0;
+}
+
+/* ECC will be calculated automatically, and errors will be detected in
+ * waitfunc.
+ */
+static void fsl_elbc_write_page(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ const uint8_t *buf)
+{
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+
+ fsl_elbc_write_buf(mtd, buf, mtd->writesize);
+ fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+ ctrl->oob_poi = chip->oob_poi;
+}
+
+static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
+{
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct nand_chip *chip = &priv->chip;
+
+ dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
+
+ /* Fill in fsl_elbc_mtd structure */
+ priv->mtd.priv = chip;
+ priv->mtd.owner = THIS_MODULE;
+ priv->fmr = 0; /* rest filled in later */
+
+ /* fill in nand_chip structure */
+ /* set up function call table */
+ chip->read_byte = fsl_elbc_read_byte;
+ chip->write_buf = fsl_elbc_write_buf;
+ chip->read_buf = fsl_elbc_read_buf;
+ chip->verify_buf = fsl_elbc_verify_buf;
+ chip->select_chip = fsl_elbc_select_chip;
+ chip->cmdfunc = fsl_elbc_cmdfunc;
+ chip->waitfunc = fsl_elbc_wait;
+ chip->late_init = fsl_elbc_chip_init_tail;
+
+ /* set up nand options */
+ chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
+
+ chip->controller = &ctrl->controller;
+ chip->priv = priv;
+
+ chip->ecc.read_page = fsl_elbc_read_page;
+ chip->ecc.write_page = fsl_elbc_write_page;
+
+ /* If CS Base Register selects full hardware ECC then use it */
+ if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
+ BR_DECC_CHK_GEN) {
+ chip->ecc.mode = NAND_ECC_HW;
+ /* put in small page settings and adjust later if needed */
+ chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
+ &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
+ chip->ecc.size = 512;
+ chip->ecc.bytes = 3;
+ } else {
+ /* otherwise fall back to default software ECC */
+ chip->ecc.mode = NAND_ECC_SOFT;
+ }
+
+ return 0;
+}
+
+static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
+{
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+
+ nand_release(&priv->mtd);
+
+ if (priv->vbase)
+ iounmap(priv->vbase);
+
+ ctrl->chips[priv->bank] = NULL;
+ kfree(priv);
+
+ return 0;
+}
+
+static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
+ struct device_node *node)
+{
+ struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_elbc_mtd *priv;
+ struct resource res;
+#ifdef CONFIG_MTD_PARTITIONS
+ static const char *part_probe_types[]
+ = { "cmdlinepart", "RedBoot", NULL };
+ struct mtd_partition *parts;
+#endif
+ int ret;
+ int bank;
+
+ /* get, allocate and map the memory resource */
+ ret = of_address_to_resource(node, 0, &res);
+ if (ret) {
+ dev_err(ctrl->dev, "failed to get resource\n");
+ return ret;
+ }
+
+ /* find which chip select it is connected to */
+ for (bank = 0; bank < MAX_BANKS; bank++)
+ if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
+ (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
+ (in_be32(&lbc->bank[bank].br) &
+ in_be32(&lbc->bank[bank].or) & BR_BA)
+ == res.start)
+ break;
+
+ if (bank >= MAX_BANKS) {
+ dev_err(ctrl->dev, "address did not match any chip selects\n");
+ return -ENODEV;
+ }
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ ctrl->chips[bank] = priv;
+ priv->bank = bank;
+ priv->ctrl = ctrl;
+ priv->dev = ctrl->dev;
+
+ priv->vbase = ioremap(res.start, res.end - res.start + 1);
+ if (!priv->vbase) {
+ dev_err(ctrl->dev, "failed to map chip region\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ret = fsl_elbc_chip_init(priv);
+ if (ret)
+ goto err;
+
+ ret = nand_scan(&priv->mtd, 1);
+ if (ret)
+ goto err;
+
+#ifdef CONFIG_MTD_PARTITIONS
+ /* First look for RedBoot table or partitions on the command
+ * line, these take precedence over device tree information */
+ ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
+ if (ret < 0)
+ goto err;
+
+#ifdef CONFIG_MTD_OF_PARTS
+ if (ret == 0) {
+ ret = of_mtd_parse_partitions(priv->dev, &priv->mtd,
+ node, &parts);
+ if (ret < 0)
+ goto err;
+ }
+#endif
+
+ if (ret > 0)
+ add_mtd_partitions(&priv->mtd, parts, ret);
+ else
+#endif
+ add_mtd_device(&priv->mtd);
+
+ printk(KERN_INFO "eLBC NAND device at 0x%zx, bank %d\n",
+ res.start, priv->bank);
+ return 0;
+
+err:
+ fsl_elbc_chip_remove(priv);
+ return ret;
+}
+
+static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
+{
+ struct elbc_regs __iomem *lbc = ctrl->regs;
+
+ /* clear event registers */
+ setbits32(&lbc->ltesr, LTESR_NAND_MASK);
+ out_be32(&lbc->lteatr, 0);
+
+ /* Enable interrupts for any detected events */
+ out_be32(&lbc->lteir, LTESR_NAND_MASK);
+
+ ctrl->read_bytes = 0;
+ ctrl->index = 0;
+ ctrl->addr = NULL;
+
+ return 0;
+}
+
+static int __devexit fsl_elbc_ctrl_remove(struct of_device *ofdev)
+{
+ struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
+ int i;
+
+ for (i = 0; i < MAX_BANKS; i++)
+ if (ctrl->chips[i])
+ fsl_elbc_chip_remove(ctrl->chips[i]);
+
+ if (ctrl->irq)
+ free_irq(ctrl->irq, ctrl);
+
+ if (ctrl->regs)
+ iounmap(ctrl->regs);
+
+ dev_set_drvdata(&ofdev->dev, NULL);
+ kfree(ctrl);
+ return 0;
+}
+
+/* NOTE: This interrupt is also used to report other localbus events,
+ * such as transaction errors on other chipselects. If we want to
+ * capture those, we'll need to move the IRQ code into a shared
+ * LBC driver.
+ */
+
+static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
+{
+ struct fsl_elbc_ctrl *ctrl = data;
+ struct elbc_regs __iomem *lbc = ctrl->regs;
+ __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
+
+ if (status) {
+ out_be32(&lbc->ltesr, status);
+ out_be32(&lbc->lteatr, 0);
+
+ ctrl->irq_status = status;
+ smp_wmb();
+ wake_up(&ctrl->irq_wait);
+
+ return IRQ_HANDLED;
+ }
+
+ return IRQ_NONE;
+}
+
+/* fsl_elbc_ctrl_probe
+ *
+ * called by device layer when it finds a device matching
+ * one our driver can handled. This code allocates all of
+ * the resources needed for the controller only. The
+ * resources for the NAND banks themselves are allocated
+ * in the chip probe function.
+*/
+
+static int __devinit fsl_elbc_ctrl_probe(struct of_device *ofdev,
+ const struct of_device_id *match)
+{
+ struct device_node *child;
+ struct fsl_elbc_ctrl *ctrl;
+ int ret;
+
+ ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
+ if (!ctrl)
+ return -ENOMEM;
+
+ dev_set_drvdata(&ofdev->dev, ctrl);
+
+ spin_lock_init(&ctrl->controller.lock);
+ init_waitqueue_head(&ctrl->controller.wq);
+ init_waitqueue_head(&ctrl->irq_wait);
+
+ ctrl->regs = of_iomap(ofdev->node, 0);
+ if (!ctrl->regs) {
+ dev_err(&ofdev->dev, "failed to get memory region\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ctrl->irq = of_irq_to_resource(ofdev->node, 0, NULL);
+ if (ctrl->irq == NO_IRQ) {
+ dev_err(&ofdev->dev, "failed to get irq resource\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ctrl->dev = &ofdev->dev;
+
+ ret = fsl_elbc_ctrl_init(ctrl);
+ if (ret < 0)
+ goto err;
+
+ ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl);
+ if (ret != 0) {
+ dev_err(&ofdev->dev, "failed to install irq (%d)\n",
+ ctrl->irq);
+ ret = ctrl->irq;
+ goto err;
+ }
+
+ child = NULL;
+ while ((child = of_get_next_child(ofdev->node, child)))
+ if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
+ fsl_elbc_chip_probe(ctrl, child);
+
+ return 0;
+
+err:
+ fsl_elbc_ctrl_remove(ofdev);
+ return ret;
+}
+
+static struct of_device_id fsl_elbc_match[] = {
+ {
+ .compatible = "fsl,elbc",
+ },
+ {}
+};
+
+static struct of_platform_driver fsl_elbc_ctrl_driver = {
+ .name = "fsl-elbc",
+ .match_table = fsl_elbc_match,
+ .probe = fsl_elbc_ctrl_probe,
+ .remove = __devexit_p(fsl_elbc_ctrl_remove),
+};
+
+static int __init fsl_elbc_init(void)
+{
+ return of_register_platform_driver(&fsl_elbc_ctrl_driver);
+}
+
+static void __exit fsl_elbc_exit(void)
+{
+ of_unregister_platform_driver(&fsl_elbc_ctrl_driver);
+}
+
+module_init(fsl_elbc_init);
+module_exit(fsl_elbc_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Freescale");
+MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");
--
1.5.3.7
^ permalink raw reply related
* Re: Fix Firmware class name collision
From: Greg KH @ 2007-12-14 22:40 UTC (permalink / raw)
To: Timur Tabi; +Cc: PowerPC dev list, Markus Rechberger
In-Reply-To: <4755FEA0.1050005@freescale.com>
On Tue, Dec 04, 2007 at 07:28:00PM -0600, Timur Tabi wrote:
> Scott Wood wrote:
>
>> The physical address certainly is useful when you have more than one
>> device of the same name.
>
> What I meant was that the physical address isn't helpful by itself.
>
>> So then you'd get "firmware-ucc.e01024". What if there's another ucc at
>> e0102480? For devices with longer names, you'd have even less precision
>> in the address.
>
> Maybe we need to consider a more sophisticated algorithm, one that
> guarantees that the device name in its entirety is preserved? Either that,
> or replace the physical address with something shorter, like the offset to
> the root node only? That way, ucc.e0102400 because just ucc.2400.
You should do something :)
In the near future (2.6.26) there will not be a limit on the size of the
file name, so we should not have this problem anymore.
thanks,
greg k-h
^ permalink raw reply
* Re: Fix Firmware class name collision
From: Timur Tabi @ 2007-12-14 22:46 UTC (permalink / raw)
To: Greg KH; +Cc: PowerPC dev list, Markus Rechberger
In-Reply-To: <20071214224051.GA29580@suse.de>
Greg KH wrote:
> In the near future (2.6.26) there will not be a limit on the size of the
> file name, so we should not have this problem anymore.
In that case, I won't worry about it. I would have preferred 2.6.25, since I
have code going into 2.6.25 that is affected by the current limit.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: apm_emulation regression
From: Rafael J. Wysocki @ 2007-12-15 0:20 UTC (permalink / raw)
To: Johannes Berg; +Cc: linux-pm, ralf, linuxppc-dev list
In-Reply-To: <1197634708.16079.46.camel@johannes.berg>
On Friday, 14 of December 2007, Johannes Berg wrote:
>
> > > It can use the new notifier that happens before freezing yes. Johannes,
> > > I think that's pretty much what my old powermac implementation did
> > > (using my private notifier scheme I had there), might be worth reviving
> > > that bit and sticking it into the generic apm_emu ...
> >
> > Note that you may want to improve on it with a timeout in case userspace
> > doesn't ack...
>
> Yeah heh. I'll take a look, shouldn't be too hard. Except I'm not
> exactly sure how to test it.
Create an artificially malicious application? ;-)
Rafael
^ permalink raw reply
* Re: [PATCH v3 4/4] Freescale enhanced Local Bus Controller FCM NAND support.
From: Josh Boyer @ 2007-12-15 1:08 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, dwmw2, linux-mtd
In-Reply-To: <20071214221736.GA21231@loki.buserror.net>
On Fri, 14 Dec 2007 16:17:36 -0600
Scott Wood <scottwood@freescale.com> wrote:
> Signed-off-by: Nick Spence <nick.spence@freescale.com>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> Fixed some formatting issues, removed some leftover debugging cruft,
> and added a comment about potential conflicts in the interrupt handling.
>
> drivers/mtd/nand/Kconfig | 9 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/fsl_elbc_nand.c | 1236 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1246 insertions(+), 0 deletions(-)
> create mode 100644 drivers/mtd/nand/fsl_elbc_nand.c
>
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 246d451..05d976c 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -306,4 +306,13 @@ config MTD_ALAUDA
> These two (and possibly other) Alauda-based cardreaders for
> SmartMedia and xD allow raw flash access.
>
> +config MTD_NAND_FSL_ELBC
> + tristate "NAND support for Freescale eLBC controllers"
> + depends on MTD_NAND && PPC_OF
> + help
> + Various Freescale chips, including the 8313, include a NAND Flash
> + Controller Module with built-in hardware ECC capabilities.
> + Enabling this option will enable you to use this to control
> + external NAND devices.
> +
> endif # MTD_NAND
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 3ad6c01..d0d4de2 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -29,5 +29,6 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
> obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
> obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
> obj-$(CONFIG_MTD_ALAUDA) += alauda.o
> +obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
>
> nand-objs := nand_base.o nand_bbt.o
> diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
> new file mode 100644
> index 0000000..001c32c
> --- /dev/null
> +++ b/drivers/mtd/nand/fsl_elbc_nand.c
> @@ -0,0 +1,1236 @@
> +/* Freescale Enhanced Local Bus Controller NAND driver
> + *
> + * Copyright (c) 2006-2007 Freescale Semiconductor
> + *
> + * Authors: Nick Spence <nick.spence@freescale.com>,
> + * Scott Wood <scottwood@freescale.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + */
> +
> +#include <linux/module.h>
> +#include <linux/types.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/string.h>
> +#include <linux/ioport.h>
> +#include <linux/of_platform.h>
> +#include <linux/slab.h>
> +#include <linux/interrupt.h>
> +
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/nand_ecc.h>
> +#include <linux/mtd/partitions.h>
> +
> +#include <asm/io.h>
> +
> +
> +#define MAX_BANKS 8
> +#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
> +#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
> +
> +struct elbc_bank {
> + __be32 br; /**< Base Register */
> +#define BR_BA 0xFFFF8000
> +#define BR_BA_SHIFT 15
> +#define BR_PS 0x00001800
> +#define BR_PS_SHIFT 11
> +#define BR_PS_8 0x00000800 /* Port Size 8 bit */
> +#define BR_PS_16 0x00001000 /* Port Size 16 bit */
> +#define BR_PS_32 0x00001800 /* Port Size 32 bit */
> +#define BR_DECC 0x00000600
> +#define BR_DECC_SHIFT 9
> +#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
> +#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
> +#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
> +#define BR_WP 0x00000100
> +#define BR_WP_SHIFT 8
> +#define BR_MSEL 0x000000E0
> +#define BR_MSEL_SHIFT 5
> +#define BR_MS_GPCM 0x00000000 /* GPCM */
> +#define BR_MS_FCM 0x00000020 /* FCM */
> +#define BR_MS_SDRAM 0x00000060 /* SDRAM */
> +#define BR_MS_UPMA 0x00000080 /* UPMA */
> +#define BR_MS_UPMB 0x000000A0 /* UPMB */
> +#define BR_MS_UPMC 0x000000C0 /* UPMC */
> +#define BR_V 0x00000001
> +#define BR_V_SHIFT 0
> +#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
> +
> + __be32 or; /**< Base Register */
Urgh. Maybe it's just me, but when people mix #defines in the middle
of a structure definition I have a hard time actually reading the
structure. You could move the #defines above the structure.
> +#define OR0 0x5004
> +#define OR1 0x500C
> +#define OR2 0x5014
> +#define OR3 0x501C
> +#define OR4 0x5024
> +#define OR5 0x502C
> +#define OR6 0x5034
> +#define OR7 0x503C
> +
> +#define OR_FCM_AM 0xFFFF8000
> +#define OR_FCM_AM_SHIFT 15
> +#define OR_FCM_BCTLD 0x00001000
> +#define OR_FCM_BCTLD_SHIFT 12
> +#define OR_FCM_PGS 0x00000400
> +#define OR_FCM_PGS_SHIFT 10
> +#define OR_FCM_CSCT 0x00000200
> +#define OR_FCM_CSCT_SHIFT 9
> +#define OR_FCM_CST 0x00000100
> +#define OR_FCM_CST_SHIFT 8
> +#define OR_FCM_CHT 0x00000080
> +#define OR_FCM_CHT_SHIFT 7
> +#define OR_FCM_SCY 0x00000070
> +#define OR_FCM_SCY_SHIFT 4
> +#define OR_FCM_SCY_1 0x00000010
> +#define OR_FCM_SCY_2 0x00000020
> +#define OR_FCM_SCY_3 0x00000030
> +#define OR_FCM_SCY_4 0x00000040
> +#define OR_FCM_SCY_5 0x00000050
> +#define OR_FCM_SCY_6 0x00000060
> +#define OR_FCM_SCY_7 0x00000070
> +#define OR_FCM_RST 0x00000008
> +#define OR_FCM_RST_SHIFT 3
> +#define OR_FCM_TRLX 0x00000004
> +#define OR_FCM_TRLX_SHIFT 2
> +#define OR_FCM_EHTR 0x00000002
> +#define OR_FCM_EHTR_SHIFT 1
> +};
> +
> +struct elbc_regs {
> + struct elbc_bank bank[8];
> + u8 res0[0x28];
> + __be32 mar; /**< UPM Address Register */
> + u8 res1[0x4];
> + __be32 mamr; /**< UPMA Mode Register */
> + __be32 mbmr; /**< UPMB Mode Register */
> + __be32 mcmr; /**< UPMC Mode Register */
> + u8 res2[0x8];
> + __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
> + __be32 mdr; /**< UPM Data Register */
> + u8 res3[0x4];
> + __be32 lsor; /**< Special Operation Initiation Register */
> + __be32 lsdmr; /**< SDRAM Mode Register */
> + u8 res4[0x8];
> + __be32 lurt; /**< UPM Refresh Timer */
> + __be32 lsrt; /**< SDRAM Refresh Timer */
> + u8 res5[0x8];
> + __be32 ltesr; /**< Transfer Error Status Register */
> +#define LTESR_BM 0x80000000
> +#define LTESR_FCT 0x40000000
> +#define LTESR_PAR 0x20000000
> +#define LTESR_WP 0x04000000
> +#define LTESR_ATMW 0x00800000
> +#define LTESR_ATMR 0x00400000
> +#define LTESR_CS 0x00080000
> +#define LTESR_CC 0x00000001
> +#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
> + __be32 ltedr; /**< Transfer Error Disable Register */
> + __be32 lteir; /**< Transfer Error Interrupt Register */
> + __be32 lteatr; /**< Transfer Error Attributes Register */
> + __be32 ltear; /**< Transfer Error Address Register */
> + u8 res6[0xC];
> + __be32 lbcr; /**< Configuration Register */
> +#define LBCR_LDIS 0x80000000
> +#define LBCR_LDIS_SHIFT 31
> +#define LBCR_BCTLC 0x00C00000
> +#define LBCR_BCTLC_SHIFT 22
> +#define LBCR_AHD 0x00200000
> +#define LBCR_LPBSE 0x00020000
> +#define LBCR_LPBSE_SHIFT 17
> +#define LBCR_EPAR 0x00010000
> +#define LBCR_EPAR_SHIFT 16
> +#define LBCR_BMT 0x0000FF00
> +#define LBCR_BMT_SHIFT 8
> +#define LBCR_INIT 0x00040000
> + __be32 lcrr; /**< Clock Ratio Register */
> +#define LCRR_DBYP 0x80000000
> +#define LCRR_DBYP_SHIFT 31
> +#define LCRR_BUFCMDC 0x30000000
> +#define LCRR_BUFCMDC_SHIFT 28
> +#define LCRR_ECL 0x03000000
> +#define LCRR_ECL_SHIFT 24
> +#define LCRR_EADC 0x00030000
> +#define LCRR_EADC_SHIFT 16
> +#define LCRR_CLKDIV 0x0000000F
> +#define LCRR_CLKDIV_SHIFT 0
> + u8 res7[0x8];
> + __be32 fmr; /**< Flash Mode Register */
> +#define FMR_CWTO 0x0000F000
> +#define FMR_CWTO_SHIFT 12
> +#define FMR_BOOT 0x00000800
> +#define FMR_ECCM 0x00000100
> +#define FMR_AL 0x00000030
> +#define FMR_AL_SHIFT 4
> +#define FMR_OP 0x00000003
> +#define FMR_OP_SHIFT 0
> + __be32 fir; /**< Flash Instruction Register */
> +#define FIR_OP0 0xF0000000
> +#define FIR_OP0_SHIFT 28
> +#define FIR_OP1 0x0F000000
> +#define FIR_OP1_SHIFT 24
> +#define FIR_OP2 0x00F00000
> +#define FIR_OP2_SHIFT 20
> +#define FIR_OP3 0x000F0000
> +#define FIR_OP3_SHIFT 16
> +#define FIR_OP4 0x0000F000
> +#define FIR_OP4_SHIFT 12
> +#define FIR_OP5 0x00000F00
> +#define FIR_OP5_SHIFT 8
> +#define FIR_OP6 0x000000F0
> +#define FIR_OP6_SHIFT 4
> +#define FIR_OP7 0x0000000F
> +#define FIR_OP7_SHIFT 0
> +#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
> +#define FIR_OP_CA 0x1 /* Issue current column address */
> +#define FIR_OP_PA 0x2 /* Issue current block+page address */
> +#define FIR_OP_UA 0x3 /* Issue user defined address */
> +#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
> +#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
> +#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
> +#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
> +#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
> +#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
> +#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
> +#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
> +#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
> +#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
> +#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
> +#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
> + __be32 fcr; /**< Flash Command Register */
> +#define FCR_CMD0 0xFF000000
> +#define FCR_CMD0_SHIFT 24
> +#define FCR_CMD1 0x00FF0000
> +#define FCR_CMD1_SHIFT 16
> +#define FCR_CMD2 0x0000FF00
> +#define FCR_CMD2_SHIFT 8
> +#define FCR_CMD3 0x000000FF
> +#define FCR_CMD3_SHIFT 0
> + __be32 fbar; /**< Flash Block Address Register */
> +#define FBAR_BLK 0x00FFFFFF
> + __be32 fpar; /**< Flash Page Address Register */
> +#define FPAR_SP_PI 0x00007C00
> +#define FPAR_SP_PI_SHIFT 10
> +#define FPAR_SP_MS 0x00000200
> +#define FPAR_SP_CI 0x000001FF
> +#define FPAR_SP_CI_SHIFT 0
> +#define FPAR_LP_PI 0x0003F000
> +#define FPAR_LP_PI_SHIFT 12
> +#define FPAR_LP_MS 0x00000800
> +#define FPAR_LP_CI 0x000007FF
> +#define FPAR_LP_CI_SHIFT 0
> + __be32 fbcr; /**< Flash Byte Count Register */
> +#define FBCR_BC 0x00000FFF
> + u8 res11[0x8];
> + u8 res8[0xF00];
> +};
> +
> +struct fsl_elbc_ctrl;
> +
> +/* mtd information per set */
> +
> +struct fsl_elbc_mtd {
> + struct mtd_info mtd;
> + struct nand_chip chip;
> + struct fsl_elbc_ctrl *ctrl;
> +
> + struct device *dev;
> + int bank; /* Chip select bank number */
> + u8 __iomem *vbase; /* Chip select base virtual address */
> + int page_size; /* NAND page size (0=512, 1=2048) */
> + unsigned int fmr; /* FCM Flash Mode Register value */
> +};
> +
> +/* overview of the fsl elbc controller */
> +
> +struct fsl_elbc_ctrl {
> + struct nand_hw_control controller;
> + struct fsl_elbc_mtd *chips[MAX_BANKS];
> +
> + /* device info */
> + struct device *dev;
> + struct elbc_regs __iomem *regs;
> + int irq;
> + wait_queue_head_t irq_wait;
> + unsigned int irq_status; /* status read from LTESR by irq handler */
> + u8 __iomem *addr; /* Address of assigned FCM buffer */
> + unsigned int page; /* Last page written to / read from */
> + unsigned int read_bytes; /* Number of bytes read during command */
> + unsigned int column; /* Saved column from SEQIN */
> + unsigned int index; /* Pointer to next byte to 'read' */
> + unsigned int status; /* status read from LTESR after last op */
> + unsigned int mdr; /* UPM/FCM Data Register value */
> + unsigned int use_mdr; /* Non zero if the MDR is to be set */
> + unsigned int oob; /* Non zero if operating on OOB data */
> + char *oob_poi; /* Place to write ECC after read back */
> +};
> +
> +/* These map to the positions used by the FCM hardware ECC generator */
> +
> +/* Small Page FLASH with FMR[ECCM] = 0 */
> +static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
> + .eccbytes = 3,
> + .eccpos = {6, 7, 8},
> + .oobfree = { {0, 5}, {9, 7} },
> + .oobavail = 12,
> +};
> +
> +/* Small Page FLASH with FMR[ECCM] = 1 */
> +static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
> + .eccbytes = 3,
> + .eccpos = {8, 9, 10},
> + .oobfree = { {0, 5}, {6, 2}, {11, 5} },
> + .oobavail = 12,
> +};
> +
> +/* Large Page FLASH with FMR[ECCM] = 0 */
> +static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
> + .eccbytes = 12,
> + .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
> + .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
> + .oobavail = 48,
> +};
> +
> +/* Large Page FLASH with FMR[ECCM] = 1 */
> +static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
> + .eccbytes = 12,
> + .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
> + .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
> + .oobavail = 48,
> +};
> +
> +/*=================================*/
> +
> +/*
> + * Set up the FCM hardware block and page address fields, and the fcm
> + * structure addr field to point to the correct FCM buffer in memory
> + */
> +static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct fsl_elbc_mtd *priv = chip->priv;
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> + struct elbc_regs __iomem *lbc = ctrl->regs;
> + int buf_num;
> +
> + ctrl->page = page_addr;
> +
> + out_be32(&lbc->fbar,
> + page_addr >> (chip->phys_erase_shift - chip->page_shift));
> +
> + if (priv->page_size) {
> + out_be32(&lbc->fpar,
> + ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
> + (oob ? FPAR_LP_MS : 0) | column);
> + buf_num = (page_addr & 1) << 2;
> + } else {
> + out_be32(&lbc->fpar,
> + ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
> + (oob ? FPAR_SP_MS : 0) | column);
> + buf_num = page_addr & 7;
> + }
> +
> + ctrl->addr = priv->vbase + buf_num * 1024;
> + ctrl->index = column;
> +
> + /* for OOB data point to the second half of the buffer */
> + if (oob)
> + ctrl->index += priv->page_size ? 2048 : 512;
> +
> + dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
> + "index %x, pes %d ps %d\n",
> + buf_num, ctrl->addr, priv->vbase, ctrl->index,
> + chip->phys_erase_shift, chip->page_shift);
> +}
> +
> +/*
> + * execute FCM command and wait for it to complete
> + */
> +static int fsl_elbc_run_command(struct mtd_info *mtd)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct fsl_elbc_mtd *priv = chip->priv;
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> + struct elbc_regs __iomem *lbc = ctrl->regs;
> +
> + /* Setup the FMR[OP] to execute without write protection */
> + out_be32(&lbc->fmr, priv->fmr | 3);
> + if (ctrl->use_mdr)
> + out_be32(&lbc->mdr, ctrl->mdr);
> +
> + dev_vdbg(ctrl->dev,
> + "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
> + in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
> + dev_vdbg(ctrl->dev,
> + "fsl_elbc_run_command: fbar=%08x fpar=%08x "
> + "fbcr=%08x bank=%d\n",
> + in_be32(&lbc->fbar), in_be32(&lbc->fpar),
> + in_be32(&lbc->fbcr), priv->bank);
> +
> + /* execute special operation */
> + out_be32(&lbc->lsor, priv->bank);
> +
> + /* wait for FCM complete flag or timeout */
> + ctrl->irq_status = 0;
> + wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
> + FCM_TIMEOUT_MSECS * HZ/1000);
> + ctrl->status = ctrl->irq_status;
> +
> + /* store mdr value in case it was needed */
> + if (ctrl->use_mdr)
> + ctrl->mdr = in_be32(&lbc->mdr);
> +
> + ctrl->use_mdr = 0;
> +
> + dev_vdbg(ctrl->dev,
> + "fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
> + ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
> +
> + /* returns 0 on success otherwise non-zero) */
> + return ctrl->status == LTESR_CC ? 0 : -EIO;
> +}
> +
> +static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
> +{
> + struct fsl_elbc_mtd *priv = chip->priv;
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> + struct elbc_regs __iomem *lbc = ctrl->regs;
> +
> + if (priv->page_size) {
> + out_be32(&lbc->fir,
> + (FIR_OP_CW0 << FIR_OP0_SHIFT) |
> + (FIR_OP_CA << FIR_OP1_SHIFT) |
> + (FIR_OP_PA << FIR_OP2_SHIFT) |
> + (FIR_OP_CW1 << FIR_OP3_SHIFT) |
> + (FIR_OP_RBW << FIR_OP4_SHIFT));
> +
> + out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
> + (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
> + } else {
> + out_be32(&lbc->fir,
> + (FIR_OP_CW0 << FIR_OP0_SHIFT) |
> + (FIR_OP_CA << FIR_OP1_SHIFT) |
> + (FIR_OP_PA << FIR_OP2_SHIFT) |
> + (FIR_OP_RBW << FIR_OP3_SHIFT));
> +
> + if (oob)
> + out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
> + else
> + out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
> + }
> +}
> +
> +/* cmdfunc send commands to the FCM */
> +static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
> + int column, int page_addr)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct fsl_elbc_mtd *priv = chip->priv;
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> + struct elbc_regs __iomem *lbc = ctrl->regs;
> +
> + ctrl->use_mdr = 0;
> +
> + /* clear the read buffer */
> + ctrl->read_bytes = 0;
> + if (command != NAND_CMD_PAGEPROG)
> + ctrl->index = 0;
> +
> + switch (command) {
> + /* READ0 and READ1 read the entire buffer to use hardware ECC. */
> + case NAND_CMD_READ1:
> + column += 256;
> +
> + /* fall-through */
> + case NAND_CMD_READ0:
> + dev_dbg(ctrl->dev,
> + "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
> + " 0x%x, column: 0x%x.\n", page_addr, column);
> +
> +
> + out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
> + set_addr(mtd, 0, page_addr, 0);
> +
> + ctrl->read_bytes = mtd->writesize + mtd->oobsize;
> + ctrl->index += column;
> +
> + fsl_elbc_do_read(chip, 0);
> + fsl_elbc_run_command(mtd);
> + return;
> +
> + /* READOOB reads only the OOB because no ECC is performed. */
> + case NAND_CMD_READOOB:
> + dev_vdbg(ctrl->dev,
> + "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
> + " 0x%x, column: 0x%x.\n", page_addr, column);
> +
> + out_be32(&lbc->fbcr, mtd->oobsize - column);
> + set_addr(mtd, column, page_addr, 1);
> +
> + ctrl->read_bytes = mtd->writesize + mtd->oobsize;
> +
> + fsl_elbc_do_read(chip, 1);
> + fsl_elbc_run_command(mtd);
> + return;
> +
> + /* READID must read all 5 possible bytes while CEB is active */
> + case NAND_CMD_READID:
> + dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
> +
> + out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
> + (FIR_OP_UA << FIR_OP1_SHIFT) |
> + (FIR_OP_RBW << FIR_OP2_SHIFT));
> + out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
> + /* 5 bytes for manuf, device and exts */
> + out_be32(&lbc->fbcr, 5);
> + ctrl->read_bytes = 5;
> + ctrl->use_mdr = 1;
> + ctrl->mdr = 0;
> +
> + set_addr(mtd, 0, 0, 0);
> + fsl_elbc_run_command(mtd);
> + return;
> +
> + /* ERASE1 stores the block and page address */
> + case NAND_CMD_ERASE1:
> + dev_vdbg(ctrl->dev,
> + "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
> + "page_addr: 0x%x.\n", page_addr);
> + set_addr(mtd, 0, page_addr, 0);
> + return;
> +
> + /* ERASE2 uses the block and page address from ERASE1 */
> + case NAND_CMD_ERASE2:
> + dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
> +
> + out_be32(&lbc->fir,
> + (FIR_OP_CW0 << FIR_OP0_SHIFT) |
> + (FIR_OP_PA << FIR_OP1_SHIFT) |
> + (FIR_OP_CM1 << FIR_OP2_SHIFT));
> +
> + out_be32(&lbc->fcr,
> + (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
> + (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
> +
> + out_be32(&lbc->fbcr, 0);
> + ctrl->read_bytes = 0;
> +
> + fsl_elbc_run_command(mtd);
> + return;
> +
> + /* SEQIN sets up the addr buffer and all registers except the length */
> + case NAND_CMD_SEQIN: {
> + __be32 fcr;
> + dev_vdbg(ctrl->dev,
> + "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
> + "page_addr: 0x%x, column: 0x%x.\n",
> + page_addr, column);
> +
> + ctrl->column = column;
> + ctrl->oob = 0;
> +
> + fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
> + (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
> +
> + if (priv->page_size) {
> + out_be32(&lbc->fir,
> + (FIR_OP_CW0 << FIR_OP0_SHIFT) |
> + (FIR_OP_CA << FIR_OP1_SHIFT) |
> + (FIR_OP_PA << FIR_OP2_SHIFT) |
> + (FIR_OP_WB << FIR_OP3_SHIFT) |
> + (FIR_OP_CW1 << FIR_OP4_SHIFT));
> +
> + fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
> + } else {
> + out_be32(&lbc->fir,
> + (FIR_OP_CW0 << FIR_OP0_SHIFT) |
> + (FIR_OP_CM2 << FIR_OP1_SHIFT) |
> + (FIR_OP_CA << FIR_OP2_SHIFT) |
> + (FIR_OP_PA << FIR_OP3_SHIFT) |
> + (FIR_OP_WB << FIR_OP4_SHIFT) |
> + (FIR_OP_CW1 << FIR_OP5_SHIFT));
> +
> + if (column >= mtd->writesize) {
> + /* OOB area --> READOOB */
> + column -= mtd->writesize;
> + fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
> + ctrl->oob = 1;
> + } else if (column < 256) {
> + /* First 256 bytes --> READ0 */
> + fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
> + } else {
> + /* Second 256 bytes --> READ1 */
> + fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
> + }
> + }
> +
> + out_be32(&lbc->fcr, fcr);
> + set_addr(mtd, column, page_addr, ctrl->oob);
> + return;
> + }
> +
> + /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
> + case NAND_CMD_PAGEPROG: {
> + int full_page;
> + dev_vdbg(ctrl->dev,
> + "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
> + "writing %d bytes.\n", ctrl->index);
> +
> + /* if the write did not start at 0 or is not a full page
> + * then set the exact length, otherwise use a full page
> + * write so the HW generates the ECC.
> + */
> + if (ctrl->oob || ctrl->column != 0 ||
> + ctrl->index != mtd->writesize + mtd->oobsize) {
> + out_be32(&lbc->fbcr, ctrl->index);
> + full_page = 0;
> + } else {
> + out_be32(&lbc->fbcr, 0);
> + full_page = 1;
> + }
> +
> + fsl_elbc_run_command(mtd);
> +
> + /* Read back the page in order to fill in the ECC for the
> + * caller. Is this really needed?
> + */
> + if (full_page && ctrl->oob_poi) {
> + out_be32(&lbc->fbcr, 3);
> + set_addr(mtd, 6, page_addr, 1);
> +
> + ctrl->read_bytes = mtd->writesize + 9;
> +
> + fsl_elbc_do_read(chip, 1);
> + fsl_elbc_run_command(mtd);
> +
> + memcpy_fromio(ctrl->oob_poi + 6,
> + &ctrl->addr[ctrl->index], 3);
> + ctrl->index += 3;
> + }
> +
> + ctrl->oob_poi = NULL;
> + return;
> + }
> +
> + /* CMD_STATUS must read the status byte while CEB is active */
> + /* Note - it does not wait for the ready line */
> + case NAND_CMD_STATUS:
> + out_be32(&lbc->fir,
> + (FIR_OP_CM0 << FIR_OP0_SHIFT) |
> + (FIR_OP_RBW << FIR_OP1_SHIFT));
> + out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
> + out_be32(&lbc->fbcr, 1);
> + set_addr(mtd, 0, 0, 0);
> + ctrl->read_bytes = 1;
> +
> + fsl_elbc_run_command(mtd);
> +
> + /* The chip always seems to report that it is
> + * write-protected, even when it is not.
> + */
> + setbits8(ctrl->addr, NAND_STATUS_WP);
> + return;
> +
> + /* RESET without waiting for the ready line */
> + case NAND_CMD_RESET:
> + dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
> + out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
> + out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
> + fsl_elbc_run_command(mtd);
> + return;
> +
> + default:
> + dev_err(ctrl->dev,
> + "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
> + command);
> + }
> +}
> +
> +static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
> +{
> + /* The hardware does not seem to support multiple
> + * chips per bank.
> + */
> +}
> +
> +/*
> + * Write buf to the FCM Controller Data Buffer
> + */
> +static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct fsl_elbc_mtd *priv = chip->priv;
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> + unsigned int bufsize = mtd->writesize + mtd->oobsize;
> +
> + if (len < 0) {
> + dev_err(ctrl->dev, "write_buf of %d bytes", len);
> + ctrl->status = 0;
> + return;
> + }
> +
> + if ((unsigned int)len > bufsize - ctrl->index) {
> + dev_err(ctrl->dev,
> + "write_buf beyond end of buffer "
> + "(%d requested, %u available)\n",
> + len, bufsize - ctrl->index);
> + len = bufsize - ctrl->index;
> + }
> +
> + memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
> + ctrl->index += len;
> +}
> +
> +/*
> + * read a byte from either the FCM hardware buffer if it has any data left
> + * otherwise issue a command to read a single byte.
> + */
> +static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct fsl_elbc_mtd *priv = chip->priv;
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> +
> + /* If there are still bytes in the FCM, then use the next byte. */
> + if (ctrl->index < ctrl->read_bytes)
> + return in_8(&ctrl->addr[ctrl->index++]);
> +
> + dev_err(ctrl->dev, "read_byte beyond end of buffer\n");
> + return ERR_BYTE;
> +}
> +
> +/*
> + * Read from the FCM Controller Data Buffer
> + */
> +static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct fsl_elbc_mtd *priv = chip->priv;
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> + int avail;
> +
> + if (len < 0)
> + return;
> +
> + avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
> + memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
> + ctrl->index += avail;
> +
> + if (len > avail)
> + dev_err(ctrl->dev,
> + "read_buf beyond end of buffer "
> + "(%d requested, %d available)\n",
> + len, avail);
> +}
> +
> +/*
> + * Verify buffer against the FCM Controller Data Buffer
> + */
> +static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct fsl_elbc_mtd *priv = chip->priv;
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> + int i;
> +
> + if (len < 0) {
> + dev_err(ctrl->dev, "write_buf of %d bytes", len);
> + return -EINVAL;
> + }
> +
> + if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
> + dev_err(ctrl->dev,
> + "verify_buf beyond end of buffer "
> + "(%d requested, %u available)\n",
> + len, ctrl->read_bytes - ctrl->index);
> +
> + ctrl->index = ctrl->read_bytes;
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < len; i++)
> + if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
> + break;
> +
> + ctrl->index += len;
> + return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
> +}
> +
> +/* This function is called after Program and Erase Operations to
> + * check for success or failure.
> + */
> +static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
> +{
> + struct fsl_elbc_mtd *priv = chip->priv;
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> + struct elbc_regs __iomem *lbc = ctrl->regs;
> +
> + if (ctrl->status != LTESR_CC)
> + return NAND_STATUS_FAIL;
> +
> + /* Use READ_STATUS command, but wait for the device to be ready */
> + ctrl->use_mdr = 0;
> + out_be32(&lbc->fir,
> + (FIR_OP_CW0 << FIR_OP0_SHIFT) |
> + (FIR_OP_RBW << FIR_OP1_SHIFT));
> + out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
> + out_be32(&lbc->fbcr, 1);
> + set_addr(mtd, 0, 0, 0);
> + ctrl->read_bytes = 1;
> +
> + fsl_elbc_run_command(mtd);
> +
> + if (ctrl->status != LTESR_CC)
> + return NAND_STATUS_FAIL;
> +
> + /* The chip always seems to report that it is
> + * write-protected, even when it is not.
> + */
> + setbits8(ctrl->addr, NAND_STATUS_WP);
> + return fsl_elbc_read_byte(mtd);
> +}
> +
> +static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
> +{
> + struct nand_chip *chip = mtd->priv;
> + struct fsl_elbc_mtd *priv = chip->priv;
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> + struct elbc_regs __iomem *lbc = ctrl->regs;
> + unsigned int al;
> +
> + /* calculate FMR Address Length field */
> + al = 0;
> + if (chip->pagemask & 0xffff0000)
> + al++;
> + if (chip->pagemask & 0xff000000)
> + al++;
> +
> + /* add to ECCM mode set in fsl_elbc_init */
> + priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
> + (al << FMR_AL_SHIFT);
> +
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n",
> + chip->numchips);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %ld\n",
> + chip->chipsize);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
> + chip->pagemask);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
> + chip->chip_delay);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
> + chip->badblockpos);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
> + chip->chip_shift);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n",
> + chip->page_shift);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
> + chip->phys_erase_shift);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
> + chip->ecclayout);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
> + chip->ecc.mode);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
> + chip->ecc.steps);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
> + chip->ecc.bytes);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
> + chip->ecc.total);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
> + chip->ecc.layout);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %d\n", mtd->size);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
> + mtd->erasesize);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n",
> + mtd->writesize);
> + dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
> + mtd->oobsize);
> +
> + /* adjust Option Register and ECC to match Flash page size */
> + if (mtd->writesize == 512) {
> + priv->page_size = 0;
> + clrbits32(&lbc->bank[priv->bank].or, ~OR_FCM_PGS);
> + } else if (mtd->writesize == 2048) {
> + priv->page_size = 1;
> + setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
> + /* adjust ecc setup if needed */
> + if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
> + BR_DECC_CHK_GEN) {
> + chip->ecc.size = 512;
> + chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
> + &fsl_elbc_oob_lp_eccm1 :
> + &fsl_elbc_oob_lp_eccm0;
> + mtd->ecclayout = chip->ecc.layout;
> + mtd->oobavail = chip->ecc.layout->oobavail;
> + }
> + } else {
> + dev_err(ctrl->dev,
> + "fsl_elbc_init: page size %d is not supported\n",
> + mtd->writesize);
> + return -1;
> + }
> +
> + /* The default u-boot configuration on MPC8313ERDB causes errors;
> + * more delay is needed. This should be safe for other boards
> + * as well.
> + */
> + setbits32(&lbc->bank[priv->bank].or, 0x70);
> + return 0;
> +}
> +
> +static int fsl_elbc_read_page(struct mtd_info *mtd,
> + struct nand_chip *chip,
> + uint8_t *buf)
> +{
> + fsl_elbc_read_buf(mtd, buf, mtd->writesize);
> + fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
> +
> + if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
> + mtd->ecc_stats.failed++;
> +
> + return 0;
> +}
> +
> +/* ECC will be calculated automatically, and errors will be detected in
> + * waitfunc.
> + */
> +static void fsl_elbc_write_page(struct mtd_info *mtd,
> + struct nand_chip *chip,
> + const uint8_t *buf)
> +{
> + struct fsl_elbc_mtd *priv = chip->priv;
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> +
> + fsl_elbc_write_buf(mtd, buf, mtd->writesize);
> + fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
> +
> + ctrl->oob_poi = chip->oob_poi;
> +}
> +
> +static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
> +{
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> + struct elbc_regs __iomem *lbc = ctrl->regs;
> + struct nand_chip *chip = &priv->chip;
> +
> + dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
> +
> + /* Fill in fsl_elbc_mtd structure */
> + priv->mtd.priv = chip;
> + priv->mtd.owner = THIS_MODULE;
> + priv->fmr = 0; /* rest filled in later */
> +
> + /* fill in nand_chip structure */
> + /* set up function call table */
> + chip->read_byte = fsl_elbc_read_byte;
> + chip->write_buf = fsl_elbc_write_buf;
> + chip->read_buf = fsl_elbc_read_buf;
> + chip->verify_buf = fsl_elbc_verify_buf;
> + chip->select_chip = fsl_elbc_select_chip;
> + chip->cmdfunc = fsl_elbc_cmdfunc;
> + chip->waitfunc = fsl_elbc_wait;
> + chip->late_init = fsl_elbc_chip_init_tail;
> +
> + /* set up nand options */
> + chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
> +
> + chip->controller = &ctrl->controller;
> + chip->priv = priv;
> +
> + chip->ecc.read_page = fsl_elbc_read_page;
> + chip->ecc.write_page = fsl_elbc_write_page;
> +
> + /* If CS Base Register selects full hardware ECC then use it */
> + if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
> + BR_DECC_CHK_GEN) {
> + chip->ecc.mode = NAND_ECC_HW;
> + /* put in small page settings and adjust later if needed */
> + chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
> + &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
> + chip->ecc.size = 512;
> + chip->ecc.bytes = 3;
> + } else {
> + /* otherwise fall back to default software ECC */
> + chip->ecc.mode = NAND_ECC_SOFT;
> + }
> +
> + return 0;
> +}
> +
> +static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
> +{
> + struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> +
> + nand_release(&priv->mtd);
> +
> + if (priv->vbase)
> + iounmap(priv->vbase);
> +
> + ctrl->chips[priv->bank] = NULL;
> + kfree(priv);
> +
> + return 0;
> +}
> +
> +static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
> + struct device_node *node)
> +{
> + struct elbc_regs __iomem *lbc = ctrl->regs;
> + struct fsl_elbc_mtd *priv;
> + struct resource res;
> +#ifdef CONFIG_MTD_PARTITIONS
> + static const char *part_probe_types[]
> + = { "cmdlinepart", "RedBoot", NULL };
> + struct mtd_partition *parts;
> +#endif
> + int ret;
> + int bank;
> +
> + /* get, allocate and map the memory resource */
> + ret = of_address_to_resource(node, 0, &res);
> + if (ret) {
> + dev_err(ctrl->dev, "failed to get resource\n");
> + return ret;
> + }
> +
> + /* find which chip select it is connected to */
> + for (bank = 0; bank < MAX_BANKS; bank++)
> + if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
> + (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
> + (in_be32(&lbc->bank[bank].br) &
> + in_be32(&lbc->bank[bank].or) & BR_BA)
> + == res.start)
> + break;
> +
> + if (bank >= MAX_BANKS) {
> + dev_err(ctrl->dev, "address did not match any chip selects\n");
> + return -ENODEV;
> + }
> +
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + ctrl->chips[bank] = priv;
> + priv->bank = bank;
> + priv->ctrl = ctrl;
> + priv->dev = ctrl->dev;
> +
> + priv->vbase = ioremap(res.start, res.end - res.start + 1);
> + if (!priv->vbase) {
> + dev_err(ctrl->dev, "failed to map chip region\n");
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + ret = fsl_elbc_chip_init(priv);
> + if (ret)
> + goto err;
> +
> + ret = nand_scan(&priv->mtd, 1);
> + if (ret)
> + goto err;
> +
> +#ifdef CONFIG_MTD_PARTITIONS
> + /* First look for RedBoot table or partitions on the command
> + * line, these take precedence over device tree information */
> + ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
> + if (ret < 0)
> + goto err;
> +
> +#ifdef CONFIG_MTD_OF_PARTS
> + if (ret == 0) {
> + ret = of_mtd_parse_partitions(priv->dev, &priv->mtd,
> + node, &parts);
> + if (ret < 0)
> + goto err;
> + }
> +#endif
> +
> + if (ret > 0)
> + add_mtd_partitions(&priv->mtd, parts, ret);
> + else
> +#endif
> + add_mtd_device(&priv->mtd);
> +
> + printk(KERN_INFO "eLBC NAND device at 0x%zx, bank %d\n",
> + res.start, priv->bank);
> + return 0;
> +
> +err:
> + fsl_elbc_chip_remove(priv);
> + return ret;
> +}
> +
> +static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
> +{
> + struct elbc_regs __iomem *lbc = ctrl->regs;
> +
> + /* clear event registers */
> + setbits32(&lbc->ltesr, LTESR_NAND_MASK);
> + out_be32(&lbc->lteatr, 0);
> +
> + /* Enable interrupts for any detected events */
> + out_be32(&lbc->lteir, LTESR_NAND_MASK);
> +
> + ctrl->read_bytes = 0;
> + ctrl->index = 0;
> + ctrl->addr = NULL;
> +
> + return 0;
> +}
> +
> +static int __devexit fsl_elbc_ctrl_remove(struct of_device *ofdev)
> +{
> + struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
> + int i;
> +
> + for (i = 0; i < MAX_BANKS; i++)
> + if (ctrl->chips[i])
> + fsl_elbc_chip_remove(ctrl->chips[i]);
> +
> + if (ctrl->irq)
> + free_irq(ctrl->irq, ctrl);
> +
> + if (ctrl->regs)
> + iounmap(ctrl->regs);
> +
> + dev_set_drvdata(&ofdev->dev, NULL);
> + kfree(ctrl);
> + return 0;
> +}
> +
> +/* NOTE: This interrupt is also used to report other localbus events,
> + * such as transaction errors on other chipselects. If we want to
> + * capture those, we'll need to move the IRQ code into a shared
> + * LBC driver.
> + */
> +
> +static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
> +{
> + struct fsl_elbc_ctrl *ctrl = data;
> + struct elbc_regs __iomem *lbc = ctrl->regs;
> + __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
> +
> + if (status) {
> + out_be32(&lbc->ltesr, status);
> + out_be32(&lbc->lteatr, 0);
> +
> + ctrl->irq_status = status;
> + smp_wmb();
> + wake_up(&ctrl->irq_wait);
> +
> + return IRQ_HANDLED;
> + }
> +
> + return IRQ_NONE;
> +}
> +
> +/* fsl_elbc_ctrl_probe
> + *
> + * called by device layer when it finds a device matching
> + * one our driver can handled. This code allocates all of
> + * the resources needed for the controller only. The
> + * resources for the NAND banks themselves are allocated
> + * in the chip probe function.
> +*/
> +
> +static int __devinit fsl_elbc_ctrl_probe(struct of_device *ofdev,
> + const struct of_device_id *match)
> +{
> + struct device_node *child;
> + struct fsl_elbc_ctrl *ctrl;
> + int ret;
> +
> + ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
> + if (!ctrl)
> + return -ENOMEM;
> +
> + dev_set_drvdata(&ofdev->dev, ctrl);
> +
> + spin_lock_init(&ctrl->controller.lock);
> + init_waitqueue_head(&ctrl->controller.wq);
> + init_waitqueue_head(&ctrl->irq_wait);
> +
> + ctrl->regs = of_iomap(ofdev->node, 0);
> + if (!ctrl->regs) {
> + dev_err(&ofdev->dev, "failed to get memory region\n");
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + ctrl->irq = of_irq_to_resource(ofdev->node, 0, NULL);
> + if (ctrl->irq == NO_IRQ) {
> + dev_err(&ofdev->dev, "failed to get irq resource\n");
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + ctrl->dev = &ofdev->dev;
> +
> + ret = fsl_elbc_ctrl_init(ctrl);
> + if (ret < 0)
> + goto err;
> +
> + ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl);
> + if (ret != 0) {
> + dev_err(&ofdev->dev, "failed to install irq (%d)\n",
> + ctrl->irq);
> + ret = ctrl->irq;
> + goto err;
> + }
> +
> + child = NULL;
> + while ((child = of_get_next_child(ofdev->node, child)))
> + if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
> + fsl_elbc_chip_probe(ctrl, child);
Don't you need some of_node_put calls here?
> +
> + return 0;
> +
> +err:
> + fsl_elbc_ctrl_remove(ofdev);
> + return ret;
You don't free ctrl if you get an error. Memory leak?
josh
^ permalink raw reply
* Re: [PATCH 2/4] mpc8313erdb: Add NAND to device tree, and call of_platform_bus_probe().
From: David Gibson @ 2007-12-15 1:52 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20071213171714.GA4510@loki.buserror.net>
On Thu, Dec 13, 2007 at 11:17:14AM -0600, Scott Wood wrote:
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> arch/powerpc/boot/dts/mpc8313erdb.dts | 37 +++++++++++++++++++++++++++++
> arch/powerpc/platforms/83xx/mpc8313_rdb.c | 17 +++++++++++++
> 2 files changed, 54 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
> index 9e7eba9..86e851a 100644
> --- a/arch/powerpc/boot/dts/mpc8313erdb.dts
> +++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
> @@ -37,6 +37,43 @@
> reg = <00000000 08000000>; // 128MB at 0
> };
>
> + localbus {
Should be "localbus@e0005000".
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8313-elbc", "fsl,elbc";
> + reg = <e0005000 1000>;
> + interrupts = <d#77 8>;
The IPIC has interrupt numbers up to 77? Wow..
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH v3 4/4] Freescale enhanced Local Bus Controller FCM NAND support.
From: Nathan Lynch @ 2007-12-15 1:23 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev, dwmw2, linux-mtd
In-Reply-To: <20071214190819.29cbe0bb@vader.jdub.homelinux.org>
Josh Boyer wrote:
> On Fri, 14 Dec 2007 16:17:36 -0600
> Scott Wood <scottwood@freescale.com> wrote:
>
> > + child = NULL;
> > + while ((child = of_get_next_child(ofdev->node, child)))
> > + if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
> > + fsl_elbc_chip_probe(ctrl, child);
>
> Don't you need some of_node_put calls here?
The of_... iterators do of_node_put() for you as long as you don't
break out of the loop early.
^ permalink raw reply
* Re: [PATCH v2 2/4] mpc8313erdb: Add NAND to device tree, and call of_platform_bus_probe().
From: David Gibson @ 2007-12-15 1:55 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20071214185826.GB10584@loki.buserror.net>
On Fri, Dec 14, 2007 at 12:58:26PM -0600, Scott Wood wrote:
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> As requested, compatible is used rather than name for probing.
> The simple-bus name comes from ePAPR drafts.
>
> arch/powerpc/boot/dts/mpc8313erdb.dts | 38 +++++++++++++++++++++++++++++
> arch/powerpc/platforms/83xx/mpc8313_rdb.c | 16 ++++++++++++
> 2 files changed, 54 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
> index c5b6665..66b53ec 100644
> --- a/arch/powerpc/boot/dts/mpc8313erdb.dts
> +++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
> @@ -45,10 +45,48 @@
> reg = <00000000 08000000>; // 128MB at 0
> };
>
> + localbus {
Should be "localbus@e0005000".
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
> + reg = <e0005000 1000>;
> + interrupts = <d#77 8>;
> + interrupt-parent = <&ipic>;
> +
> + // CS0 and CS1 are swapped when
> + // booting from nand, but the
> + // addresses are the same.
Should the bootwrapper have some kind of fixup to poke in the correct
chipselect values based on the state?
Or should we have a function to fill in the elbc's ranges property
based on the bridge control registers, as we do for the ebc on 4xx.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 6/6] optimize account_system_vtime
From: Michael Neuling @ 2007-12-15 2:10 UTC (permalink / raw)
To: Milton Miller; +Cc: linuxppc-dev, akpm, Paul Mackerras
In-Reply-To: <mm-cpu-6@bga.com>
In message <mm-cpu-6@bga.com> you wrote:
> We have multiple calls to has_feature being inlined, but gcc can't
> be sure that the store via get_paca() doesn't alias the path to
> cur_cpu_spec->feature.
>
> Reorder to put the calls to read_purr and read_spurr adjacent to each
> other. To add a sense of consistency, reorder the remaining lines to
> perform parallel steps on purr and scaled purr of each line instead of
> calculating and then using one value before going on to the next.
>
> In addition, we can tell gcc that no SPURR means no PURR. The test is
This was suppose read "no PURR means no SPURR"?
> completely hidden in the PURR case, and in the !PURR case the second test
> is eliminated resulting in the simple register copy in the out-of-line
> branch.
>
> Further, gcc sees get_paca()->system_time referenced several times and
> allocates a register to address it (shadowing r13) instead of caching its
> value. Reading into a local varable saves the shadow of r13 and removes
> a potentially duplicate load (between the nested if and its parent).
>
> Signed-off-by: Milton Miller <miltonm@bga.com>
> ---
> The purr and spurr fields of the paca are only used in this c code,
> but system_time and user_time are also used in asm and I decided to
> leave all of these fields in the paca.
>
> Index: kernel/arch/powerpc/kernel/time.c
> ===================================================================
> --- kernel.orig/arch/powerpc/kernel/time.c 2007-12-13 21:58:10.000000000 -
0600
> +++ kernel/arch/powerpc/kernel/time.c 2007-12-13 22:00:36.000000000 -0600
> @@ -219,7 +219,11 @@ static u64 read_purr(void)
> */
> static u64 read_spurr(u64 purr)
> {
> - if (cpu_has_feature(CPU_FTR_SPURR))
> + /*
> + * cpus without PURR won't have a SPURR
> + * We already know the former when we use this, so tell gcc
> + */
> + if (cpu_has_feature(CPU_FTR_PURR) && cpu_has_feature(CPU_FTR_SPURR))
> return mfspr(SPRN_SPURR);
> return purr;
> }
> @@ -230,29 +234,30 @@ static u64 read_spurr(u64 purr)
> */
> void account_system_vtime(struct task_struct *tsk)
> {
> - u64 now, nowscaled, delta, deltascaled;
> + u64 now, nowscaled, delta, deltascaled, sys_time;
> unsigned long flags;
>
> local_irq_save(flags);
> now = read_purr();
> - delta = now - get_paca()->startpurr;
> - get_paca()->startpurr = now;
> nowscaled = read_spurr(now);
> + delta = now - get_paca()->startpurr;
> deltascaled = nowscaled - get_paca()->startspurr;
> + get_paca()->startpurr = now;
> get_paca()->startspurr = nowscaled;
> if (!in_interrupt()) {
> /* deltascaled includes both user and system time.
> * Hence scale it based on the purr ratio to estimate
> * the system time */
> + sys_time = get_paca()->system_time;
> if (get_paca()->user_time)
> - deltascaled = deltascaled * get_paca()->system_time /
> - (get_paca()->system_time + get_paca()->user_time);
> - delta += get_paca()->system_time;
> + deltascaled = deltascaled * sys_time /
> + (sys_time + get_paca()->user_time);
> + delta += sys_time;
> get_paca()->system_time = 0;
> }
> account_system_time(tsk, 0, delta);
> - get_paca()->purrdelta = delta;
> account_system_time_scaled(tsk, deltascaled);
> + get_paca()->purrdelta = delta;
Reordering looks ok to me.
These changes are going to conflict and probably need to be re-optimised
due to this patch in the mm tree.
http://www.kernel.org/pub/linux/kernel/people/akpm/patches/2.6/2.6.24-rc5/2.6.24-rc5-mm1/broken-out/taskstats-scaled-time-cleanup.patch
This moves the s/purrdelta out of the paca and into per-cpu variables.
It's nothing that can't be merged, just flagging it as a future
conflict.
Mikey
^ permalink raw reply
* Re: [PATCH v3 4/4] Freescale enhanced Local Bus Controller FCM NAND support.
From: David Gibson @ 2007-12-15 2:58 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, dwmw2, linux-mtd
In-Reply-To: <20071214221736.GA21231@loki.buserror.net>
On Fri, Dec 14, 2007 at 04:17:36PM -0600, Scott Wood wrote:
> Signed-off-by: Nick Spence <nick.spence@freescale.com>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> Fixed some formatting issues, removed some leftover debugging cruft,
> and added a comment about potential conflicts in the interrupt
> handling.
Why is the NAND MTD driver specific to the elbc bus? And why does it
bind to the elbc node, rather than the nand node under it?
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH v2 2/4] mpc8313erdb: Add NAND to device tree, and call of_platform_bus_probe().
From: Scott Wood @ 2007-12-15 3:48 UTC (permalink / raw)
To: galak, linuxppc-dev
In-Reply-To: <20071215015543.GD6935@localhost.localdomain>
On Sat, Dec 15, 2007 at 12:55:43PM +1100, David Gibson wrote:
> > + // CS0 and CS1 are swapped when
> > + // booting from nand, but the
> > + // addresses are the same.
>
> Should the bootwrapper have some kind of fixup to poke in the correct
> chipselect values based on the state?
>
> Or should we have a function to fill in the elbc's ranges property
> based on the bridge control registers, as we do for the ebc on 4xx.
We could, though I'm inclined to be lazy about it since nothing really
cares (well, the elbc nand code *does* care which chip select it's on,
but it figures it out by matching the address in the localbus registers).
-Scott
^ permalink raw reply
* Re: [PATCH v3 4/4] Freescale enhanced Local Bus Controller FCM NAND support.
From: Scott Wood @ 2007-12-15 3:50 UTC (permalink / raw)
To: dwmw2, linuxppc-dev, linux-mtd
In-Reply-To: <20071215025851.GA8430@localhost.localdomain>
On Sat, Dec 15, 2007 at 01:58:51PM +1100, David Gibson wrote:
> On Fri, Dec 14, 2007 at 04:17:36PM -0600, Scott Wood wrote:
> > Signed-off-by: Nick Spence <nick.spence@freescale.com>
> > Signed-off-by: Scott Wood <scottwood@freescale.com>
> > ---
> > Fixed some formatting issues, removed some leftover debugging cruft,
> > and added a comment about potential conflicts in the interrupt
> > handling.
>
> Why is the NAND MTD driver specific to the elbc bus?
Because the NAND flash controller is part of the elbc.
> And why does it bind to the elbc node, rather than the nand node under
> it?
The FCM registers are part of the eLBC register block; the chip select
mapping is just a data buffer.
-Scott
^ permalink raw reply
* Re: Fix Firmware class name collision
From: Benjamin Herrenschmidt @ 2007-12-15 6:14 UTC (permalink / raw)
To: Greg KH; +Cc: PowerPC dev list, Markus Rechberger, Timur Tabi
In-Reply-To: <20071214224051.GA29580@suse.de>
On Fri, 2007-12-14 at 14:40 -0800, Greg KH wrote:
> On Tue, Dec 04, 2007 at 07:28:00PM -0600, Timur Tabi wrote:
> > Scott Wood wrote:
> >
> >> The physical address certainly is useful when you have more than one
> >> device of the same name.
> >
> > What I meant was that the physical address isn't helpful by itself.
> >
> >> So then you'd get "firmware-ucc.e01024". What if there's another ucc at
> >> e0102480? For devices with longer names, you'd have even less precision
> >> in the address.
> >
> > Maybe we need to consider a more sophisticated algorithm, one that
> > guarantees that the device name in its entirety is preserved? Either that,
> > or replace the physical address with something shorter, like the offset to
> > the root node only? That way, ucc.e0102400 because just ucc.2400.
>
> You should do something :)
>
> In the near future (2.6.26) there will not be a limit on the size of the
> file name, so we should not have this problem anymore.
Not even .25 ? damn ! Any way that fix can be fastracked ? This
limitation has been a major PITA for some time now (this is just -one-
example where it gets in the way).
Ben.
^ permalink raw reply
* Re: [PATCH 03/10] powerpc: Add kexec support for PPC_85xx platforms
From: Benjamin Herrenschmidt @ 2007-12-15 6:16 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev
In-Reply-To: <20071122154607.GA26447@xyzzy.farnsworth.org>
> index 8b642ab..db0e749 100644
> --- a/arch/powerpc/kernel/misc_32.S
> +++ b/arch/powerpc/kernel/misc_32.S
> @@ -816,6 +816,75 @@ relocate_new_kernel:
> /* r4 = reboot_code_buffer */
> /* r5 = start_address */
>
> +#ifdef CONFIG_E500
> + /*
> + * Since we can't turn off the MMU, we must create an identity
> + * map for kernel low memory. We start by invalidating the
> + * TLB entries we don't need.
> + *
> + * First, invalidate the TLB0 entries
> + */
> + li r6, 0x04
> + tlbivax 0, r6
> +#ifdef CONFIG_SMP
> + tlbsync
> +#endif
> + msync
> +
This is really E500 specific or should it be CONFIG_FSL_BOOKE ?
Ben.
^ permalink raw reply
* Re: [PATCH 07/10] powerpc: Implement kmap_atomic_pfn on powerpc
From: Benjamin Herrenschmidt @ 2007-12-15 6:17 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev
In-Reply-To: <20071122154638.GA26514@xyzzy.farnsworth.org>
On Thu, 2007-11-22 at 08:46 -0700, Dale Farnsworth wrote:
> This is needed for the ppc32 /dev/oldmem driver of crash dump.
Kumar's working (well, last I heard he was) on a fixmap mechanism
so we can do that sort of thing without CONFIG_HIGHMEM, you may
want to sync with him here, that would allow to shrink the crash
kernel by not having highmem selected.
Cheers,
Ben.
> Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
> ---
> include/asm-powerpc/highmem.h | 18 ++++++++++++++++++
> 1 files changed, 18 insertions(+), 0 deletions(-)
>
> diff --git a/include/asm-powerpc/highmem.h b/include/asm-powerpc/highmem.h
> index f7b21ee..88d9e05 100644
> --- a/include/asm-powerpc/highmem.h
> +++ b/include/asm-powerpc/highmem.h
> @@ -117,6 +117,24 @@ static inline void kunmap_atomic(void *kvaddr, enum km_type type)
> pagefault_enable();
> }
>
> +/* This is the same as kmap_atomic() but can map memory that doesn't
> + * have a struct page associated with it.
> + */
> +static inline void *kmap_atomic_pfn(unsigned long pfn, enum km_type type)
> +{
> + unsigned int idx;
> + unsigned long vaddr;
> +
> + pagefault_disable();
> +
> + idx = type + KM_TYPE_NR * smp_processor_id();
> + vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE;
> + set_pte_at(&init_mm, vaddr, kmap_pte+idx, pfn_pte(pfn, kmap_prot));
> + flush_tlb_page(NULL, vaddr);
> +
> + return (void*) vaddr;
> +}
> +
> static inline struct page *kmap_atomic_to_page(void *ptr)
> {
> unsigned long idx, vaddr = (unsigned long) ptr;
^ permalink raw reply
* Re: Fix Firmware class name collision
From: Greg KH @ 2007-12-15 6:39 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Kay Sievers
Cc: PowerPC dev list, Markus Rechberger, Timur Tabi
In-Reply-To: <1197699269.6696.41.camel@pasglop>
On Sat, Dec 15, 2007 at 05:14:29PM +1100, Benjamin Herrenschmidt wrote:
>
> On Fri, 2007-12-14 at 14:40 -0800, Greg KH wrote:
> > On Tue, Dec 04, 2007 at 07:28:00PM -0600, Timur Tabi wrote:
> > > Scott Wood wrote:
> > >
> > >> The physical address certainly is useful when you have more than one
> > >> device of the same name.
> > >
> > > What I meant was that the physical address isn't helpful by itself.
> > >
> > >> So then you'd get "firmware-ucc.e01024". What if there's another ucc at
> > >> e0102480? For devices with longer names, you'd have even less precision
> > >> in the address.
> > >
> > > Maybe we need to consider a more sophisticated algorithm, one that
> > > guarantees that the device name in its entirety is preserved? Either that,
> > > or replace the physical address with something shorter, like the offset to
> > > the root node only? That way, ucc.e0102400 because just ucc.2400.
> >
> > You should do something :)
> >
> > In the near future (2.6.26) there will not be a limit on the size of the
> > file name, so we should not have this problem anymore.
>
> Not even .25 ? damn ! Any way that fix can be fastracked ? This
> limitation has been a major PITA for some time now (this is just -one-
> example where it gets in the way).
I'll let Kay answer that, last he said, it involves a _lot_ of changes
throughout the kernel :(
thanks,
greg k-h
^ permalink raw reply
* Re: mmap + segfaults on MPC8349E
From: R. Ebersole (VTI - new) @ 2007-12-15 6:40 UTC (permalink / raw)
To: David Hawkins; +Cc: linuxppc-embedded
In-Reply-To: <475DF30A.1080202@ovro.caltech.edu>
[-- Attachment #1: Type: text/plain, Size: 1107 bytes --]
Dave,
Attached is the driver code that was in use when we had the problem.
(FPGA_orig.7z)
We think that we *may* have resolved the issue.
We have not, yet, completed testing the resolution, however.
Attached is the updated version of the driver (FPGArw.7z).
So far, this version appears OK when using mmap() without
MAP_FIXED. We open() the device O_RDWR | O_SYNC.
We were going to switch to using pread(), pwrite(), and ioctl() to
access the FPGA's registers, but we are going to hold off on that
for now.
David Hawkins wrote:
> Hi,
>
> Ok, so assuming you come back with the fact that the seg-fault
> occurs without bursting. Lets take a look at your driver code.
>
> Cheers,
> Dave
>
>
>
--
Sometimes I feel like a red shirt in the Star Trek episode of life.
--
This message contains confidential information and is intended only for the
individual named. If you are not the intended recipient you should not
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[-- Attachment #2: FPGArw.7z --]
[-- Type: application/octet-stream, Size: 3775 bytes --]
[-- Attachment #3: FPGA_orig.7z --]
[-- Type: application/octet-stream, Size: 2544 bytes --]
^ permalink raw reply
* [PATCH] [POWERPC] 4xx: Add aliases node to 4xx dts files
From: Stefan Roese @ 2007-12-15 7:55 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/powerpc/boot/dts/bamboo.dts | 9 +++++++++
arch/powerpc/boot/dts/ebony.dts | 7 +++++++
arch/powerpc/boot/dts/ep405.dts | 6 ++++++
arch/powerpc/boot/dts/katmai.dts | 7 +++++++
arch/powerpc/boot/dts/kilauea.dts | 7 +++++++
arch/powerpc/boot/dts/rainier.dts | 11 ++++++++++-
arch/powerpc/boot/dts/sequoia.dts | 9 +++++++++
arch/powerpc/boot/dts/taishan.dts | 7 +++++++
arch/powerpc/boot/dts/walnut.dts | 6 ++++++
9 files changed, 68 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/bamboo.dts b/arch/powerpc/boot/dts/bamboo.dts
index 3652aec..2ebb437 100644
--- a/arch/powerpc/boot/dts/bamboo.dts
+++ b/arch/powerpc/boot/dts/bamboo.dts
@@ -18,6 +18,15 @@
compatible = "amcc,bamboo";
dcr-parent = <&/cpus/cpu@0>;
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ serial2 = &UART2;
+ serial3 = &UART3;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts
index 3cb2849..f8790c4 100644
--- a/arch/powerpc/boot/dts/ebony.dts
+++ b/arch/powerpc/boot/dts/ebony.dts
@@ -18,6 +18,13 @@
compatible = "ibm,ebony";
dcr-parent = <&/cpus/cpu@0>;
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/ep405.dts b/arch/powerpc/boot/dts/ep405.dts
index 16cfc0d..9293855 100644
--- a/arch/powerpc/boot/dts/ep405.dts
+++ b/arch/powerpc/boot/dts/ep405.dts
@@ -16,6 +16,12 @@
compatible = "ep405";
dcr-parent = <&/cpus/cpu@0>;
+ aliases {
+ ethernet0 = &EMAC;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 824cf4e..350e70e 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -19,6 +19,13 @@
compatible = "amcc,katmai";
dcr-parent = <&/cpus/cpu@0>;
+ aliases {
+ ethernet0 = &EMAC0;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ serial2 = &UART2;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 0a3fbfa..3814199 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -15,6 +15,13 @@
compatible = "amcc,kilauea";
dcr-parent = <&/cpus/cpu@0>;
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/rainier.dts b/arch/powerpc/boot/dts/rainier.dts
index 63d996e..b2e8231 100644
--- a/arch/powerpc/boot/dts/rainier.dts
+++ b/arch/powerpc/boot/dts/rainier.dts
@@ -19,6 +19,15 @@
compatible = "amcc,rainier";
dcr-parent = <&/cpus/cpu@0>;
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ serial2 = &UART2;
+ serial3 = &UART3;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -93,7 +102,7 @@
#size-cells = <1>;
ranges;
clock-frequency = <0>; /* Filled in by zImage */
-
+
SDRAM0: sdram {
compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali";
dcr-reg = <010 2>;
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
index dbb1b3b..fb88028 100644
--- a/arch/powerpc/boot/dts/sequoia.dts
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -19,6 +19,15 @@
compatible = "amcc,sequoia";
dcr-parent = <&/cpus/cpu@0>;
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ serial2 = &UART2;
+ serial3 = &UART3;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts
index 0dec702..0706a4a 100644
--- a/arch/powerpc/boot/dts/taishan.dts
+++ b/arch/powerpc/boot/dts/taishan.dts
@@ -17,6 +17,13 @@
compatible = "amcc,taishan";
dcr-parent = <&/cpus/cpu@0>;
+ aliases {
+ ethernet0 = &EMAC2;
+ ethernet1 = &EMAC3;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/walnut.dts b/arch/powerpc/boot/dts/walnut.dts
index 8fcf6aa..0e3825e 100644
--- a/arch/powerpc/boot/dts/walnut.dts
+++ b/arch/powerpc/boot/dts/walnut.dts
@@ -16,6 +16,12 @@
compatible = "ibm,walnut";
dcr-parent = <&/cpus/cpu@0>;
+ aliases {
+ ethernet0 = &EMAC;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
--
1.5.3.7.949.g2221a6
^ permalink raw reply related
* [PATCH] [POWERPC] 4xx: Change Kilauea PCIe bus ranges in dts file
From: Stefan Roese @ 2007-12-15 8:10 UTC (permalink / raw)
To: linuxppc-dev
Currently we have some limitations in the 4xx PCIe driver and can't
support all possible PCIe busses. But the current limits in the
dts file are quite low (only 16 busses per RC). This patch increases
the number to 64 per RC.
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/powerpc/boot/dts/kilauea.dts | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 3814199..67c7ea1 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -284,8 +284,8 @@
/* Inbound 2GB range starting at 0 */
dma-ranges = <42000000 0 0 0 0 80000000>;
- /* This drives busses 0x00 to 0x0f */
- bus-range = <00 0f>;
+ /* This drives busses 0x00 to 0x3f */
+ bus-range = <00 3f>;
/* Legacy interrupts (note the weird polarity, the bridge seems
* to invert PCIe legacy interrupts).
@@ -325,8 +325,8 @@
/* Inbound 2GB range starting at 0 */
dma-ranges = <42000000 0 0 0 0 80000000>;
- /* This drives busses 0x10 to 0x1f */
- bus-range = <10 1f>;
+ /* This drives busses 0x40 to 0x7f */
+ bus-range = <40 7f>;
/* Legacy interrupts (note the weird polarity, the bridge seems
* to invert PCIe legacy interrupts).
--
1.5.3.7.949.g2221a6
^ permalink raw reply related
* Re: [PATCH 2/3] [libata] pata_of_platform: OF-Platform PATA device driver
From: Stephen Rothwell @ 2007-12-15 14:09 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Jeff Garzik, Arnd Bergmann, linux-ide, linuxppc-dev, Paul Mundt,
Olof Johansson
In-Reply-To: <20071214182438.GB1017@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 410 bytes --]
On Fri, 14 Dec 2007 21:24:38 +0300 Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
>
> + prop = (u32 *)of_get_property(dn, "reg-shift", NULL);
This cast is unnecessary.
> + if (prop)
> + reg_shift = *prop;
> +
> + prop = (u32 *)of_get_property(dn, "pio-mode", NULL);
So is this one.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH 2/3] [libata] pata_of_platform: OF-Platform PATA device driver
From: Anton Vorontsov @ 2007-12-15 15:19 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Jeff Garzik, Arnd Bergmann, linux-ide, linuxppc-dev, Paul Mundt,
Olof Johansson
In-Reply-To: <20071216010922.13ef21d0.sfr@canb.auug.org.au>
On Sun, Dec 16, 2007 at 01:09:22AM +1100, Stephen Rothwell wrote:
> On Fri, 14 Dec 2007 21:24:38 +0300 Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> >
> > + prop = (u32 *)of_get_property(dn, "reg-shift", NULL);
>
> This cast is unnecessary.
>
> > + if (prop)
> > + reg_shift = *prop;
> > +
> > + prop = (u32 *)of_get_property(dn, "pio-mode", NULL);
>
> So is this one.
Thanks. I changed "prop" to const but obviously forgot to remove casts.
- - - -
From: Anton Vorontsov <avorontsov@ru.mvista.com>
[libata] pata_of_platform: OF-Platform PATA device driver
This driver nicely wraps around pata_platform library functions,
and provides OF platform bus bindings to the PATA devices.
Also add || PPC to the PATA_PLATFORM's "depends on" Kconfig entry,
needed for PA Semi Electra.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Reviewed-by: Olof Johansson <olof@lixom.net>
---
drivers/ata/Kconfig | 12 ++++-
drivers/ata/Makefile | 1 +
drivers/ata/pata_of_platform.c | 104 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 116 insertions(+), 1 deletions(-)
create mode 100644 drivers/ata/pata_of_platform.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index ba63619..64b4964 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -607,13 +607,23 @@ config PATA_WINBOND_VLB
config PATA_PLATFORM
tristate "Generic platform device PATA support"
- depends on EMBEDDED || ARCH_RPC
+ depends on EMBEDDED || ARCH_RPC || PPC
help
This option enables support for generic directly connected ATA
devices commonly found on embedded systems.
If unsure, say N.
+config PATA_OF_PLATFORM
+ tristate "OpenFirmware platform device PATA support"
+ depends on PATA_PLATFORM && PPC_OF
+ help
+ This option enables support for generic directly connected ATA
+ devices commonly found on embedded systems with OpenFirmware
+ bindings.
+
+ If unsure, say N.
+
config PATA_ICSIDE
tristate "Acorn ICS PATA support"
depends on ARM && ARCH_ACORN
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index b13feb2..ebcee64 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_PATA_IXP4XX_CF) += pata_ixp4xx_cf.o
obj-$(CONFIG_PATA_SCC) += pata_scc.o
obj-$(CONFIG_PATA_BF54X) += pata_bf54x.o
obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
+obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
obj-$(CONFIG_PATA_ICSIDE) += pata_icside.o
# Should be last but two libata driver
obj-$(CONFIG_PATA_ACPI) += pata_acpi.o
diff --git a/drivers/ata/pata_of_platform.c b/drivers/ata/pata_of_platform.c
new file mode 100644
index 0000000..b7bc4e4
--- /dev/null
+++ b/drivers/ata/pata_of_platform.c
@@ -0,0 +1,104 @@
+/*
+ * OF-platform PATA driver
+ *
+ * Copyright (c) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/pata_platform.h>
+
+static int __devinit pata_of_platform_probe(struct of_device *ofdev,
+ const struct of_device_id *match)
+{
+ int ret;
+ struct device_node *dn = ofdev->node;
+ struct resource io_res;
+ struct resource ctl_res;
+ struct resource irq_res;
+ unsigned int reg_shift = 0;
+ int pio_mode = 0;
+ int pio_mask;
+ const u32 *prop;
+
+ ret = of_address_to_resource(dn, 0, &io_res);
+ if (ret) {
+ dev_err(&ofdev->dev, "can't get IO address from "
+ "device tree\n");
+ return -EINVAL;
+ }
+
+ ret = of_address_to_resource(dn, 1, &ctl_res);
+ if (ret) {
+ dev_err(&ofdev->dev, "can't get CTL address from "
+ "device tree\n");
+ return -EINVAL;
+ }
+
+ ret = of_irq_to_resource(dn, 0, &irq_res);
+ if (ret == NO_IRQ)
+ irq_res.start = irq_res.end = -1;
+ else
+ irq_res.flags = 0;
+
+ prop = of_get_property(dn, "reg-shift", NULL);
+ if (prop)
+ reg_shift = *prop;
+
+ prop = of_get_property(dn, "pio-mode", NULL);
+ if (prop) {
+ pio_mode = *prop;
+ if (pio_mode > 6) {
+ dev_err(&ofdev->dev, "invalid pio-mode\n");
+ return -EINVAL;
+ }
+ } else {
+ dev_info(&ofdev->dev, "pio-mode unspecified, assuming PIO0\n");
+ }
+
+ pio_mask = 1 << pio_mode;
+ pio_mask |= (1 << pio_mode) - 1;
+
+ return __pata_platform_probe(&ofdev->dev, &io_res, &ctl_res, &irq_res,
+ reg_shift, pio_mask);
+}
+
+static int __devexit pata_of_platform_remove(struct of_device *ofdev)
+{
+ return __pata_platform_remove(&ofdev->dev);
+}
+
+static struct of_device_id pata_of_platform_match[] = {
+ { .compatible = "ata-generic", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, pata_of_platform_match);
+
+static struct of_platform_driver pata_of_platform_driver = {
+ .name = "pata_of_platform",
+ .match_table = pata_of_platform_match,
+ .probe = pata_of_platform_probe,
+ .remove = __devexit_p(pata_of_platform_remove),
+};
+
+static int __init pata_of_platform_init(void)
+{
+ return of_register_platform_driver(&pata_of_platform_driver);
+}
+module_init(pata_of_platform_init);
+
+static void __exit pata_of_platform_exit(void)
+{
+ of_unregister_platform_driver(&pata_of_platform_driver);
+}
+module_exit(pata_of_platform_exit);
+
+MODULE_DESCRIPTION("OF-platform PATA driver");
+MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
+MODULE_LICENSE("GPL");
--
1.5.2.2
^ permalink raw reply related
* Re: Fix Firmware class name collision
From: Kay Sievers @ 2007-12-15 15:46 UTC (permalink / raw)
To: Greg KH; +Cc: Markus Rechberger, Timur Tabi, PowerPC dev list
In-Reply-To: <20071215063917.GA14942@suse.de>
On Fri, 2007-12-14 at 22:39 -0800, Greg KH wrote:
> On Sat, Dec 15, 2007 at 05:14:29PM +1100, Benjamin Herrenschmidt wrote:
> >
> > On Fri, 2007-12-14 at 14:40 -0800, Greg KH wrote:
> > > On Tue, Dec 04, 2007 at 07:28:00PM -0600, Timur Tabi wrote:
> > > > Scott Wood wrote:
> > > >
> > > >> The physical address certainly is useful when you have more than one
> > > >> device of the same name.
> > > >
> > > > What I meant was that the physical address isn't helpful by itself.
> > > >
> > > >> So then you'd get "firmware-ucc.e01024". What if there's another ucc at
> > > >> e0102480? For devices with longer names, you'd have even less precision
> > > >> in the address.
> > > >
> > > > Maybe we need to consider a more sophisticated algorithm, one that
> > > > guarantees that the device name in its entirety is preserved? Either that,
> > > > or replace the physical address with something shorter, like the offset to
> > > > the root node only? That way, ucc.e0102400 because just ucc.2400.
> > >
> > > You should do something :)
> > >
> > > In the near future (2.6.26) there will not be a limit on the size of the
> > > file name, so we should not have this problem anymore.
> >
> > Not even .25 ? damn ! Any way that fix can be fastracked ? This
> > limitation has been a major PITA for some time now (this is just -one-
> > example where it gets in the way).
>
> I'll let Kay answer that, last he said, it involves a _lot_ of changes
> throughout the kernel :(
The current patch gets rid of bus_id and uses the dynamic kobject_name
directly all over the place. It's huge, because the current code expects
a static array and uses strncpy/snprintf all over the place.
I'm currently waiting for the new kobject api to finish, before I update
the patch, not sure if we will make it in time for .25.
Kay
^ permalink raw reply
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