* Re: [PATCH 1/8] pseries: phyp dump: Docmentation
From: Michael Ellerman @ 2008-01-09 22:59 UTC (permalink / raw)
To: Nathan Lynch; +Cc: mahuja, linuxppc-dev, Linas Vepstas, lkessler, strosake
In-Reply-To: <20080109184437.GU14201@localdomain>
[-- Attachment #1: Type: text/plain, Size: 4146 bytes --]
On Wed, 2008-01-09 at 12:44 -0600, Nathan Lynch wrote:
> Hi Linas,
>
> Linas Vepstas wrote:
> >
> > On 08/01/2008, Nathan Lynch <ntl@pobox.com> wrote:
> > > Manish Ahuja wrote:
> > > > +
> > > > +The goal of hypervisor-assisted dump is to enable the dump of
> > > > +a crashed system, and to do so from a fully-reset system, and
> > > > +to minimize the total elapsed time until the system is back
> > > > +in production use.
> > >
> > > Is it actually faster than kdump?
> >
> > This is a basic presumption;
>
> > As a side effect, the system is in
> > production *while* the dump is being taken;
It's in "production" with 256MB of RAM? Err. Sure as the dump progresses
more RAM will be freed, but that's hardly production. I think Nathan's
right, any sysadmin who wants predictability will probably double reboot
anyway.
> > with kdump,
> > you can't go into production until after the dump is finished,
> > and the system has been rebooted a second time. On
> > systems with terabytes of RAM, the time difference can be
> > hours.
> Since you bring up large systems... a system with terabytes of RAM is
> practically guaranteed to be a NUMA configuration with dozens of cpus.
> When processing a dump on such a system, I wonder how well we fare:
> can we successfully boot with (say) 128 cpus and 256MB of usable
> memory? Do we have to hot-online nodes as system memory is freed up
> (and does that even work)? We need to be able to restore the system
> to its optimal topology when the dump is finished; if the best we can
> do is a degraded configuration, the workload will suffer and the
> system admin is likely to just reboot the machine again so the kernel
> will have the right NUMA topology.
Yeah that's a good question. Even if the hot-onlining works, there's
still kernel data structures allocated at boot which want to be
node-local. So the end result will be != a "production" boot.
> > > > +Implementation details:
> > > > +----------------------
> > > > +In order for this scheme to work, memory needs to be reserved
> > > > +quite early in the boot cycle. However, access to the device
> > > > +tree this early in the boot cycle is difficult, and device-tree
> > > > +access is needed to determine if there is a crash data waiting.
> > >
> > > I don't think this bit about early device tree access is correct. By
> > > the time your code is reserving memory (from early_init_devtree(), I
> > > think), RTAS has been instantiated and you are able to test for the
> > > existence of /rtas/ibm,dump-kernel.
> >
> > If I remember right, it was still too early to look up this token directly,
> > so we wrote some code to crawl the flat device tree to find it. But
> > not only was that a lot of work, but I somehow decided that doing this
> > to the flat tree was wrong, as otherwise someone would surely have
> > written the access code. If this can be made to work, that would be
> > great, but we couldn't make it work at the time.
> >
> > > > +To work around this problem, all but 256MB of RAM is reserved
> > > > +during early boot. A short while later in boot, a check is made
> > > > +to determine if there is dump data waiting. If there isn't,
> > > > +then the reserved memory is released to general kernel use.
> > >
> > > So I think these gymnastics are unneeded -- unless I'm
> > > misunderstanding something, you should be able to determine very early
> > > whether to reserve that memory.
> >
> > Only if you can get at rtas, but you can't get at rtas at that point.
AFAICT you don't need to get at RTAS, you just need to look at the
device tree to see if the property is present, and that is trivial.
You probably just need to add a check in early_init_dt_scan_rtas() which
sets a flag for the PHYP dump stuff, or add your own scan routine if you
need.
cheers
--
Michael Ellerman
OzLabs, IBM Australia Development Lab
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* RE: Help with device tree binding for SMC serial
From: Rune Torgersen @ 2008-01-09 23:07 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <47854D6D.2010906@freescale.com>
> From: Scott Wood [mailto:scottwood@freescale.com]=20
> Rune Torgersen wrote:
> >> From: Scott Wood
> >> Don't forget to exclude the SMC parameter RAM from the muram=20
> >> data area=20
> >> in /soc/cpm/muram/data/reg. If you have an older device=20
> tree binding=20
> >> that has no /soc/cpm/muram node, but instead has two resources in=20
> >> /soc/cpm/reg, you need to move to head-of-tree to get this to work.
> >=20
> > Did that, now we get e checkstop resert. Time to hook up the
> > BDI-2000....
> > Is there a way to have the bootwrapper use the u-boot=20
> serial for a while
> > (like a early srial port) for debugging?
>=20
> If you mean calling into u-boot for a console, no, there's no=20
> code for that.
>=20
> What do your cpm and muram nodes look like?
cpm@119c0 {
#address-cells =3D <1>;
#size-cells =3D <1>;
#interrupt-cells =3D <2>;
compatible =3D "fsl,mpc8280-cpm", "fsl,cpm2";
reg =3D <119c0 30>;
ranges;
muram@0 {
#address-cells =3D <1>;
#size-cells =3D <1>;
ranges =3D <0 0 10000>;
data@0 {
compatible =3D "fsl,cpm-muram-data";
reg =3D <100 1f00 9800 800>;
};
};
brg@119f0 {
compatible =3D "fsl,mpc8280-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg =3D <119f0 10 115f0 10>;
};
serial@11a80 {
device_type =3D "serial";
compatible =3D "fsl,mpc8280-smc-uart",
"fsl,cpm2-smc-uart";
reg =3D <11a80 10 0 40>; // <base_address
length parameter_ram_address length>
interrupts =3D <4 8>; // Interrupt from
table 4.3 of mpc8280rm, interrupt is level or edge
interrupt-parent =3D <&PIC>;
fsl,cpm-brg =3D <7>;
fsl,cpm-command =3D <1d000000>; // Page and
Sub-block code of the CPCR
};
};
and chosen node (not sure if needed)
chosen {
linux,stdout-path =3D "/soc/cpm/serial@11a80";
bootargs =3D "console=3DttyS0,115200";
};
^ permalink raw reply
* Re: [PATCH 1/8] pseries: phyp dump: Docmentation
From: Manish Ahuja @ 2008-01-09 23:18 UTC (permalink / raw)
To: michael
Cc: lkessler, linuxppc-dev, Nathan Lynch, mahuja, Linas Vepstas,
strosake
In-Reply-To: <1199919545.7880.11.camel@concordia>
> It's in "production" with 256MB of RAM? Err. Sure as the dump progresses
> more RAM will be freed, but that's hardly production. I think Nathan's
> right, any sysadmin who wants predictability will probably double reboot
> anyway.
Thats a changeable parameter. Its something we chose for now. It by no means
is set in stone. Its not a design parameter. If you like to allocate 1GB we can.
But that is something we did for now. we expect this to be a variable value
dependent upon the size of the system. So if you have 128 GB system and you
can spare 10 gb, you should be able to have 10 GB to boot with.
^ permalink raw reply
* [PATCH 0/2] Add support for Freescale QUICCEngine UART
From: Timur Tabi @ 2008-01-09 23:35 UTC (permalink / raw)
To: galak, linuxppc-dev, linux-serial
This patchset creates a new serial device driver for the Freescale QE.
Part 1 of this patch set contains all the PowerPC-specific changes.
Part 2 contains all the actual driver and changes for Kconfig and Makefile.
The PowerPC portions of this patchset have already been reviewed and
approved. I'd like someone from linux-serial to review the actual driver
itself.
^ permalink raw reply
* [PATCH] [POWERPC] qe: add support for Freescale QUICCEngine UART
From: Timur Tabi @ 2008-01-09 23:35 UTC (permalink / raw)
To: galak, linuxppc-dev, linux-serial; +Cc: Timur Tabi
In-Reply-To: <11999217062265-git-send-email-timur@freescale.com>
Add support for UART serial ports using a Freescale QUICCEngine. Update
booting-without-of.txt to define new properties for a QE UART node. Update
the MPC8323E-MDS device tree to add UCC5 as a UART. Update the QE library
to support slow UCC devices and modules.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
Documentation/powerpc/booting-without-of.txt | 9 ++++-
arch/powerpc/boot/dts/mpc832x_mds.dts | 50 ++++++++++++++++++++++++++
arch/powerpc/sysdev/qe_lib/Kconfig | 2 +-
arch/powerpc/sysdev/qe_lib/ucc_slow.c | 10 +++++-
4 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 53c2295..7ad221f 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1619,7 +1619,7 @@ platforms are moved over to use the flattened-device-tree model.
Required properties:
- device_type : should be "network", "hldc", "uart", "transparent"
- "bisync" or "atm".
+ "bisync", "atm", or "serial".
- compatible : could be "ucc_geth" or "fsl_atm" and so on.
- model : should be "UCC".
- device-id : the ucc number(1-8), corresponding to UCCx in UM.
@@ -1632,6 +1632,13 @@ platforms are moved over to use the flattened-device-tree model.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
- pio-handle : The phandle for the Parallel I/O port configuration.
+ - port-number : for UART drivers, the port number to use, between 0 and 3.
+ This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
+ The port number is added to the minor number of the device. Unlike the
+ CPM UART driver, the port-number is required for the QE UART driver.
+ - soft-uart : for UART drivers, if specified this means the QE UART device
+ driver should use "Soft-UART" mode, which is needed on some SOCs that have
+ broken UART hardware. Soft-UART is provided via a microcode upload.
- rx-clock-name: the UCC receive clock source
"none": clock source is disabled
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 26ac467..758cd98 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -7,6 +7,18 @@
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
+
+ * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
+ * this:
+ *
+ * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
+ * 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
+ * next to the serial ports.
+ * 3) Solder a wire from U61-22 to P19K-22.
+ *
+ * Note that there's a typo in the schematic. The board labels the last column
+ * of pins "P19K", but in the schematic, that column is called "P19J". So if
+ * you're going by the schematic, the pin is called "P19J-K22".
*/
/ {
@@ -169,6 +181,23 @@
1 1e 1 0 1 0 /* TX_EN */
1 1f 2 0 1 0>;/* CRS */
};
+ pio5: ucc_pin@05 {
+ pio-map = <
+ /*
+ * open has
+ * port pin dir drain sel irq
+ */
+ 2 0 1 0 2 0 /* TxD5 */
+ 2 8 2 0 2 0 /* RxD5 */
+
+ 2 1d 2 0 0 0 /* CTS5 */
+ 2 1f 1 0 2 0 /* RTS5 */
+
+ 2 18 2 0 0 0 /* CD */
+
+ >;
+ };
+
};
};
@@ -176,6 +205,7 @@
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
+ compatible = "fsl,qe";
model = "QE";
ranges = <0 e0100000 00100000>;
reg = <e0100000 480>;
@@ -250,6 +280,26 @@
pio-handle = < &pio4 >;
};
+ ucc@2400 {
+ device_type = "serial";
+ compatible = "ucc_uart";
+ model = "UCC";
+ device-id = <5>; /* The UCC number, 1-7*/
+ port-number = <0>; /* Which ttyQEx device */
+ soft-uart; /* We need Soft-UART */
+ reg = <2400 200>;
+ interrupts = <28>; /* From Table 18-12 */
+ interrupt-parent = < &qeic >;
+ /*
+ * For Soft-UART, we need to set TX to 1X, which
+ * means specifying separate clock sources.
+ */
+ rx-clock-name = "brg5";
+ tx-clock-name = "brg6";
+ pio-handle = < &pio5 >;
+ };
+
+
mdio@2320 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
index f611d34..adc6621 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -4,7 +4,7 @@
config UCC_SLOW
bool
- default n
+ default y if SERIAL_QE
help
This option provides qe_lib support to UCC slow
protocols: UART, BISYNC, QMC
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
index 0174b3a..b2870b2 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_slow.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -19,6 +19,7 @@
#include <linux/stddef.h>
#include <linux/interrupt.h>
#include <linux/err.h>
+#include <linux/module.h>
#include <asm/io.h>
#include <asm/immap_qe.h>
@@ -41,6 +42,7 @@ u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
default: return QE_CR_SUBBLOCK_INVALID;
}
}
+EXPORT_SYMBOL(ucc_slow_get_qe_cr_subblock);
void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs)
{
@@ -56,6 +58,7 @@ void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)
qe_issue_cmd(QE_GRACEFUL_STOP_TX, id,
QE_CR_PROTOCOL_UNSPECIFIED, 0);
}
+EXPORT_SYMBOL(ucc_slow_graceful_stop_tx);
void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
{
@@ -65,6 +68,7 @@ void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
}
+EXPORT_SYMBOL(ucc_slow_stop_tx);
void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
{
@@ -74,6 +78,7 @@ void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
}
+EXPORT_SYMBOL(ucc_slow_restart_tx);
void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
{
@@ -94,6 +99,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
}
out_be32(&us_regs->gumr_l, gumr_l);
}
+EXPORT_SYMBOL(ucc_slow_enable);
void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
{
@@ -114,6 +120,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
}
out_be32(&us_regs->gumr_l, gumr_l);
}
+EXPORT_SYMBOL(ucc_slow_disable);
/* Initialize the UCC for Slow operations
*
@@ -347,6 +354,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
*uccs_ret = uccs;
return 0;
}
+EXPORT_SYMBOL(ucc_slow_init);
void ucc_slow_free(struct ucc_slow_private * uccs)
{
@@ -366,5 +374,5 @@ void ucc_slow_free(struct ucc_slow_private * uccs)
kfree(uccs);
}
-
+EXPORT_SYMBOL(ucc_slow_free);
--
1.5.2.4
^ permalink raw reply related
* [PATCH] [SERIAL] qe-uart: add support for Freescale QUICCEngine UART
From: Timur Tabi @ 2008-01-09 23:35 UTC (permalink / raw)
To: galak, linuxppc-dev, linux-serial; +Cc: Timur Tabi
In-Reply-To: <11999217072674-git-send-email-timur@freescale.com>
Add file ucc_uart.c, a serial device driver for the Freescale QUICCEngine.
Update the Kconfig and Makefile accordingly.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
drivers/serial/Kconfig | 10 +
drivers/serial/Makefile | 1 +
drivers/serial/ucc_uart.c | 1507 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1518 insertions(+), 0 deletions(-)
create mode 100644 drivers/serial/ucc_uart.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index d7e1996..d962b74 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -1284,4 +1284,14 @@ config SERIAL_OF_PLATFORM
Currently, only 8250 compatible ports are supported, but
others can easily be added.
+config SERIAL_QE
+ tristate "Freescale QUICC Engine serial port support"
+ depends on QUICC_ENGINE
+ select SERIAL_CORE
+ select FW_LOADER
+ default n
+ help
+ This driver supports the QE serial ports on Freescale embedded
+ PowerPC that contain a QUICC Engine.
+
endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index af6377d..7eb4553 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -64,3 +64,4 @@ obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
+obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
diff --git a/drivers/serial/ucc_uart.c b/drivers/serial/ucc_uart.c
new file mode 100644
index 0000000..6fe4cfc
--- /dev/null
+++ b/drivers/serial/ucc_uart.c
@@ -0,0 +1,1507 @@
+/*
+ * Freescale QUICC Engine UART device driver
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * This driver adds support for UART devices via Freescale's QUICC Engine
+ * found on some Freescale SOCs.
+ *
+ * If Soft-UART support is needed but not already present, then this driver
+ * will request and upload the "Soft-UART" microcode upon probe. The
+ * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
+ * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
+ * (e.g. "11" for 1.1).
+ */
+
+#include <linux/module.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/dma-mapping.h>
+
+#include <linux/fs_uart_pd.h>
+#include <asm/ucc_slow.h>
+
+#include <linux/firmware.h>
+#include <asm/reg.h>
+
+/*
+ * The GUMR flag for Soft UART. This would normally be defined in qe.h,
+ * but Soft-UART is a hack and we want to keep everything related to it in
+ * this file.
+ */
+#define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
+
+/*
+ * soft_uart is 1 if we need to use Soft-UART mode
+ */
+static int soft_uart;
+/*
+ * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
+ */
+static int firmware_loaded;
+
+/* Enable this macro to configure all serial ports in internal loopback
+ mode */
+/* #define LOOPBACK */
+
+/* The major and minor device numbers are defined in
+ * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE
+ * UART, we have major number 204 and minor numbers 46 - 49, which are the
+ * same as for the CPM2. This decision was made because no Freescale part
+ * has both a CPM and a QE.
+ */
+#define SERIAL_QE_MAJOR 204
+#define SERIAL_QE_MINOR 46
+
+/* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
+#define UCC_MAX_UART 4
+
+/* The number of buffer descriptors for receiving characters. */
+#define RX_NUM_FIFO 4
+
+/* The number of buffer descriptors for transmitting characters. */
+#define TX_NUM_FIFO 4
+
+/* The maximum size of the character buffer for a single RX BD. */
+#define RX_BUF_SIZE 32
+
+/* The maximum size of the character buffer for a single TX BD. */
+#define TX_BUF_SIZE 32
+
+#define UCC_WAIT_CLOSING 100
+
+struct ucc_uart_pram {
+ struct ucc_slow_pram common;
+ u8 res1[8]; /* reserved */
+ __be16 maxidl; /* Maximum idle chars */
+ __be16 idlc; /* temp idle counter */
+ __be16 brkcr; /* Break count register */
+ __be16 parec; /* receive parity error counter */
+ __be16 frmec; /* receive framing error counter */
+ __be16 nosec; /* receive noise counter */
+ __be16 brkec; /* receive break condition counter */
+ __be16 brkln; /* last received break length */
+ __be16 uaddr[2]; /* UART address character 1 & 2 */
+ __be16 rtemp; /* Temp storage */
+ __be16 toseq; /* Transmit out of sequence char */
+ __be16 cchars[8]; /* control characters 1-8 */
+ __be16 rccm; /* receive control character mask */
+ __be16 rccr; /* receive control character register */
+ __be16 rlbc; /* receive last break character */
+ __be16 res2; /* reserved */
+ __be32 res3; /* reserved, should be cleared */
+ u8 res4; /* reserved, should be cleared */
+ u8 res5[3]; /* reserved, should be cleared */
+ __be32 res6; /* reserved, should be cleared */
+ __be32 res7; /* reserved, should be cleared */
+ __be32 res8; /* reserved, should be cleared */
+ __be32 res9; /* reserved, should be cleared */
+ __be32 res10; /* reserved, should be cleared */
+ __be32 res11; /* reserved, should be cleared */
+ __be32 res12; /* reserved, should be cleared */
+ __be32 res13; /* reserved, should be cleared */
+/* The rest is for Soft-UART only */
+ __be16 supsmr; /* 0x90, Shadow UPSMR */
+ __be16 res92; /* 0x92, reserved, initialize to 0 */
+ __be32 rx_state; /* 0x94, RX state, initialize to 0 */
+ __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */
+ u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */
+ u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */
+ u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */
+ u8 res14[0xBC - 0x9F]; /* reserved */
+ __be32 dump_ptr; /* 0xBC, Dump pointer */
+ __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */
+ u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */
+ u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */
+ u16 tx_state; /* 0xC6, TX state */
+ u8 res15[0xD0 - 0xC8]; /* reserved */
+ __be32 resD0; /* 0xD0, reserved, initialize to 0 */
+ u8 resD4; /* 0xD4, reserved, initialize to 0 */
+ __be16 resD5; /* 0xD5, reserved, initialize to 0 */
+} __attribute__ ((packed));
+
+/* SUPSMR definitions, for Soft-UART only */
+#define UCC_UART_SUPSMR_SL 0x8000
+#define UCC_UART_SUPSMR_RPM_MASK 0x6000
+#define UCC_UART_SUPSMR_RPM_ODD 0x0000
+#define UCC_UART_SUPSMR_RPM_LOW 0x2000
+#define UCC_UART_SUPSMR_RPM_EVEN 0x4000
+#define UCC_UART_SUPSMR_RPM_HIGH 0x6000
+#define UCC_UART_SUPSMR_PEN 0x1000
+#define UCC_UART_SUPSMR_TPM_MASK 0x0C00
+#define UCC_UART_SUPSMR_TPM_ODD 0x0000
+#define UCC_UART_SUPSMR_TPM_LOW 0x0400
+#define UCC_UART_SUPSMR_TPM_EVEN 0x0800
+#define UCC_UART_SUPSMR_TPM_HIGH 0x0C00
+#define UCC_UART_SUPSMR_FRZ 0x0100
+#define UCC_UART_SUPSMR_UM_MASK 0x00c0
+#define UCC_UART_SUPSMR_UM_NORMAL 0x0000
+#define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040
+#define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0
+#define UCC_UART_SUPSMR_CL_MASK 0x0030
+#define UCC_UART_SUPSMR_CL_8 0x0030
+#define UCC_UART_SUPSMR_CL_7 0x0020
+#define UCC_UART_SUPSMR_CL_6 0x0010
+#define UCC_UART_SUPSMR_CL_5 0x0000
+
+#define UCC_UART_TX_STATE_AHDLC 0x00
+#define UCC_UART_TX_STATE_UART 0x01
+#define UCC_UART_TX_STATE_X1 0x00
+#define UCC_UART_TX_STATE_X16 0x80
+
+#define UCC_UART_PRAM_ALIGNMENT 0x100
+
+#define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD
+#define NUM_CONTROL_CHARS 8
+
+/* Private per-port data structure */
+struct uart_qe_port {
+ struct uart_port port;
+ struct ucc_slow __iomem *uccp;
+ struct ucc_uart_pram __iomem *uccup;
+ struct ucc_slow_info us_info;
+ struct ucc_slow_private *us_private;
+ struct device_node *np;
+ unsigned int ucc_num; /* First ucc is 0, not 1 */
+
+ u16 rx_nrfifos;
+ u16 rx_fifosize;
+ u16 tx_nrfifos;
+ u16 tx_fifosize;
+ int wait_closing;
+ u32 flags;
+ struct qe_bd *rx_bd_base;
+ struct qe_bd *rx_cur;
+ struct qe_bd *tx_bd_base;
+ struct qe_bd *tx_cur;
+ unsigned char *tx_buf;
+ unsigned char *rx_buf;
+ void *bd_virt; /* virtual address of the BD buffers */
+ dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
+ unsigned int bd_size; /* size of BD buffer space */
+};
+
+static struct uart_driver ucc_uart_driver = {
+ .owner = THIS_MODULE,
+ .driver_name = "serial",
+ .dev_name = "ttyQE",
+ .major = SERIAL_QE_MAJOR,
+ .minor = SERIAL_QE_MINOR,
+ .nr = UCC_MAX_UART,
+};
+
+/*
+ * Virtual to physical address translation.
+ *
+ * Given the virtual address for a character buffer, this function returns
+ * the physical (DMA) equivalent.
+ */
+static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
+{
+ if (likely((addr >= qe_port->bd_virt)) &&
+ (addr < (qe_port->bd_virt + qe_port->bd_size)))
+ return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
+
+ /* something nasty happened */
+ printk(KERN_ERR "%s: addr=%p\n", __FUNCTION__, addr);
+ BUG();
+ return 0;
+}
+
+/*
+ * Physical to virtual address translation.
+ *
+ * Given the physical (DMA) address for a character buffer, this function
+ * returns the virtual equivalent.
+ */
+static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
+{
+ /* sanity check */
+ if (likely((addr >= qe_port->bd_dma_addr) &&
+ (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
+ return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
+
+ /* something nasty happened */
+ printk(KERN_ERR "%s: addr=%x\n", __FUNCTION__, addr);
+ BUG();
+ return NULL;
+}
+
+/*
+ * Return 1 if the QE is done transmitting all buffers for this port
+ *
+ * This function scan each BD in sequence. If we find a BD that is not
+ * ready (READY=1), then we return 0 indicating that the QE is still sending
+ * data. If we reach the last BD (WRAP=1), then we know we've scanned
+ * the entire list, and all BDs are done.
+ */
+static unsigned int qe_uart_tx_empty(struct uart_port *port)
+{
+ struct uart_qe_port *qe_port =
+ container_of(port, struct uart_qe_port, port);
+ struct qe_bd *bdp = qe_port->tx_bd_base;
+
+ while (1) {
+ if (in_be16(&bdp->status) & BD_SC_READY)
+ /* This BD is not done, so return "not done" */
+ return 0;
+
+ if (in_be16(&bdp->status) & BD_SC_WRAP)
+ /*
+ * This BD is done and it's the last one, so return
+ * "done"
+ */
+ return 1;
+
+ bdp++;
+ };
+}
+
+/*
+ * Set the modem control lines
+ *
+ * We currently don't support setting modem control lines, but this function
+ * needs to exist, otherwise the kernel will panic.
+ */
+void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+
+/*
+ * Get the current modem control line status
+ *
+ * We don't support changing the modem control line status, so we always
+ * return Carrier Detect, Data Set Ready, and Clear To Send.
+ */
+static unsigned int qe_uart_get_mctrl(struct uart_port *port)
+{
+ return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
+}
+
+/*
+ * Disable the transmit interrupt.
+ *
+ * Although this function is called "stop_tx", it does not actually stop
+ * transmission of data. Instead, it tells the QE to not generate an
+ * interrupt when the UCC is finished sending characters.
+ */
+static void qe_uart_stop_tx(struct uart_port *port)
+{
+ struct uart_qe_port *qe_port =
+ container_of(port, struct uart_qe_port, port);
+
+ clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
+}
+
+/*
+ * Transmit as many characters to the HW as possible.
+ *
+ * This function will attempt to stuff of all the characters from the
+ * kernel's transmit buffer into TX BDs.
+ *
+ * A return value of non-zero indicates that it sucessfully stuffed all
+ * characters from the kernel buffer.
+ *
+ * A return value of zero indicates that there are still characters in the
+ * kernel's buffer that have not been transmitted, but there are no more BDs
+ * available. This function should be called again after a BD has been made
+ * available.
+ */
+static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
+{
+ struct qe_bd *bdp;
+ unsigned char *p;
+ unsigned int count;
+ struct uart_port *port = &qe_port->port;
+ struct circ_buf *xmit = &port->info->xmit;
+
+ bdp = qe_port->rx_cur;
+
+ /* Handle xon/xoff */
+ if (port->x_char) {
+ /* Pick next descriptor and fill from buffer */
+ bdp = qe_port->tx_cur;
+
+ p = qe2cpu_addr(bdp->buf, qe_port);
+
+ *p++ = port->x_char;
+ out_be16(&bdp->length, 1);
+ setbits16(&bdp->status, BD_SC_READY);
+ /* Get next BD. */
+ if (in_be16(&bdp->status) & BD_SC_WRAP)
+ bdp = qe_port->tx_bd_base;
+ else
+ bdp++;
+ qe_port->tx_cur = bdp;
+
+ port->icount.tx++;
+ port->x_char = 0;
+ return 1;
+ }
+
+ if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+ qe_uart_stop_tx(port);
+ return 0;
+ }
+
+ /* Pick next descriptor and fill from buffer */
+ bdp = qe_port->tx_cur;
+
+ while (!(in_be16(&bdp->status) & BD_SC_READY) &&
+ (xmit->tail != xmit->head)) {
+ count = 0;
+ p = qe2cpu_addr(bdp->buf, qe_port);
+ while (count < qe_port->tx_fifosize) {
+ *p++ = xmit->buf[xmit->tail];
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ port->icount.tx++;
+ count++;
+ if (xmit->head == xmit->tail)
+ break;
+ }
+
+ out_be16(&bdp->length, count);
+ setbits16(&bdp->status, BD_SC_READY);
+
+ /* Get next BD. */
+ if (in_be16(&bdp->status) & BD_SC_WRAP)
+ bdp = qe_port->tx_bd_base;
+ else
+ bdp++;
+ }
+ qe_port->tx_cur = bdp;
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+
+ if (uart_circ_empty(xmit)) {
+ /* The kernel buffer is empty, so turn off TX interrupts. We
+ don't need to be told when the QE is finished transmitting
+ the data. */
+ qe_uart_stop_tx(port);
+ return 0;
+ }
+
+ return 1;
+}
+
+/*
+ * Start transmitting data
+ *
+ * This function will start transmitting any available data, if the port
+ * isn't already transmitting data.
+ */
+static void qe_uart_start_tx(struct uart_port *port)
+{
+ struct uart_qe_port *qe_port =
+ container_of(port, struct uart_qe_port, port);
+
+ /* If we currently are transmitting, then just return */
+ if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
+ return;
+
+ /* Otherwise, pump the port and start transmission */
+ if (qe_uart_tx_pump(qe_port))
+ setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
+}
+
+/*
+ * Stop transmitting data
+ */
+static void qe_uart_stop_rx(struct uart_port *port)
+{
+ struct uart_qe_port *qe_port =
+ container_of(port, struct uart_qe_port, port);
+
+ clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
+}
+
+/*
+ * Enable status change interrupts
+ *
+ * We don't support status change interrupts, but we need to define this
+ * function otherwise the kernel will panic.
+ */
+static void qe_uart_enable_ms(struct uart_port *port)
+{
+}
+
+/* Start or stop sending break signal
+ *
+ * This function controls the sending of a break signal. If break_state=1,
+ * then we start sending a break signal. If break_state=0, then we stop
+ * sending the break signal.
+ */
+static void qe_uart_break_ctl(struct uart_port *port, int break_state)
+{
+ struct uart_qe_port *qe_port =
+ container_of(port, struct uart_qe_port, port);
+
+ if (break_state)
+ ucc_slow_stop_tx(qe_port->us_private);
+ else
+ ucc_slow_restart_tx(qe_port->us_private);
+}
+
+/* ISR helper function for receiving character.
+ *
+ * This function is called by the ISR to handling receiving characters
+ */
+static void qe_uart_int_rx(struct uart_qe_port *qe_port)
+{
+ int i;
+ unsigned char ch, *cp;
+ struct uart_port *port = &qe_port->port;
+ struct tty_struct *tty = port->info->tty;
+ struct qe_bd *bdp;
+ u16 status;
+ unsigned int flg;
+
+ /* Just loop through the closed BDs and copy the characters into
+ * the buffer.
+ */
+ bdp = qe_port->rx_cur;
+ while (1) {
+ status = in_be16(&bdp->status);
+
+ /* If this one is empty, then we assume we've read them all */
+ if (status & BD_SC_EMPTY)
+ break;
+
+ /* get number of characters, and check space in RX buffer */
+ i = in_be16(&bdp->length);
+
+ /* If we don't have enough room in RX buffer for the entire BD,
+ * then we try later, which will be the next RX interrupt.
+ */
+ if (tty_buffer_request_room(tty, i) < i) {
+ dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
+ return;
+ }
+
+ /* get pointer */
+ cp = qe2cpu_addr(bdp->buf, qe_port);
+
+ /* loop through the buffer */
+ while (i-- > 0) {
+ ch = *cp++;
+ port->icount.rx++;
+ flg = TTY_NORMAL;
+
+ if (!i && status &
+ (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
+ goto handle_error;
+ if (uart_handle_sysrq_char(port, ch))
+ continue;
+
+error_return:
+ tty_insert_flip_char(tty, ch, flg);
+
+ }
+
+ /* This BD is ready to be used again. Clear status. get next */
+ clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |
+ BD_SC_OV | BD_SC_ID, BD_SC_EMPTY);
+ if (in_be16(&bdp->status) & BD_SC_WRAP)
+ bdp = qe_port->rx_bd_base;
+ else
+ bdp++;
+
+ }
+
+ /* Write back buffer pointer */
+ qe_port->rx_cur = bdp;
+
+ /* Activate BH processing */
+ tty_flip_buffer_push(tty);
+
+ return;
+
+ /* Error processing */
+
+handle_error:
+ /* Statistics */
+ if (status & BD_SC_BR)
+ port->icount.brk++;
+ if (status & BD_SC_PR)
+ port->icount.parity++;
+ if (status & BD_SC_FR)
+ port->icount.frame++;
+ if (status & BD_SC_OV)
+ port->icount.overrun++;
+
+ /* Mask out ignored conditions */
+ status &= port->read_status_mask;
+
+ /* Handle the remaining ones */
+ if (status & BD_SC_BR)
+ flg = TTY_BREAK;
+ else if (status & BD_SC_PR)
+ flg = TTY_PARITY;
+ else if (status & BD_SC_FR)
+ flg = TTY_FRAME;
+
+ /* Overrun does not affect the current character ! */
+ if (status & BD_SC_OV)
+ tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+#ifdef SUPPORT_SYSRQ
+ port->sysrq = 0;
+#endif
+ goto error_return;
+}
+
+/* Interrupt handler
+ *
+ * This interrupt handler is called after a BD is processed.
+ */
+static irqreturn_t qe_uart_int(int irq, void *data)
+{
+ struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
+ struct ucc_slow __iomem *uccp = qe_port->uccp;
+ u16 events;
+
+ /* Clear the interrupts */
+ events = in_be16(&uccp->ucce);
+ out_be16(&uccp->ucce, events);
+
+ if (events & UCC_UART_UCCE_BRKE)
+ uart_handle_break(&qe_port->port);
+
+ if (events & UCC_UART_UCCE_RX)
+ qe_uart_int_rx(qe_port);
+
+ if (events & UCC_UART_UCCE_TX)
+ qe_uart_tx_pump(qe_port);
+
+ return events ? IRQ_HANDLED : IRQ_NONE;
+}
+
+/* Initialize buffer descriptors
+ *
+ * This function initializes all of the RX and TX buffer descriptors.
+ */
+static void qe_uart_initbd(struct uart_qe_port *qe_port)
+{
+ int i;
+ void *bd_virt;
+ struct qe_bd *bdp;
+
+ /* Set the physical address of the host memory buffers in the buffer
+ * descriptors, and the virtual address for us to work with.
+ */
+ bd_virt = qe_port->bd_virt;
+ bdp = qe_port->rx_bd_base;
+ qe_port->rx_cur = qe_port->rx_bd_base;
+ for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
+ out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);
+ out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
+ out_be16(&bdp->length, 0);
+ bd_virt += qe_port->rx_fifosize;
+ bdp++;
+ }
+
+ /* */
+ out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
+ out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
+ out_be16(&bdp->length, 0);
+
+ /* Set the physical address of the host memory
+ * buffers in the buffer descriptors, and the
+ * virtual address for us to work with.
+ */
+ bd_virt = qe_port->bd_virt +
+ L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
+ qe_port->tx_cur = qe_port->tx_bd_base;
+ bdp = qe_port->tx_bd_base;
+ for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
+ out_be16(&bdp->status, BD_SC_INTRPT);
+ out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
+ out_be16(&bdp->length, 0);
+ bd_virt += qe_port->tx_fifosize;
+ bdp++;
+ }
+
+ /* Loopback requires the preamble bit to be set on the first TX BD */
+#ifdef LOOPBACK
+ setbits16(&qe_port->tx_cur->status, BD_SC_P);
+#endif
+
+ out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);
+ out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
+ out_be16(&bdp->length, 0);
+}
+
+/*
+ * Initialize a UCC for UART.
+ *
+ * This function configures a given UCC to be used as a UART device. Basic
+ * UCC initialization is handled in qe_uart_request_port(). This function
+ * does all the UART-specific stuff.
+ */
+static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
+{
+ u32 cecr_subblock;
+ struct ucc_slow __iomem *uccp = qe_port->uccp;
+ struct ucc_uart_pram *uccup = qe_port->uccup;
+
+ unsigned int i;
+
+ /* First, disable TX and RX in the UCC */
+ ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
+
+ /* Program the UCC UART parameter RAM */
+ out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
+ out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
+ out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);
+ out_be16(&uccup->maxidl, 0x10);
+ out_be16(&uccup->brkcr, 1);
+ out_be16(&uccup->parec, 0);
+ out_be16(&uccup->frmec, 0);
+ out_be16(&uccup->nosec, 0);
+ out_be16(&uccup->brkec, 0);
+ out_be16(&uccup->uaddr[0], 0);
+ out_be16(&uccup->uaddr[1], 0);
+ out_be16(&uccup->toseq, 0);
+ for (i = 0; i < 8; i++)
+ out_be16(&uccup->cchars[i], 0xC000);
+ out_be16(&uccup->rccm, 0xc0ff);
+
+ /* Configure the GUMR registers for UART */
+ if (soft_uart)
+ /* Soft-UART requires a 1X multiplier for TX */
+ clrsetbits_be32(&uccp->gumr_l,
+ UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
+ UCC_SLOW_GUMR_L_RDCR_MASK,
+ UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
+ UCC_SLOW_GUMR_L_RDCR_16);
+ else
+ clrsetbits_be32(&uccp->gumr_l,
+ UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
+ UCC_SLOW_GUMR_L_RDCR_MASK,
+ UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
+ UCC_SLOW_GUMR_L_RDCR_16);
+
+ clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
+ UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
+
+#ifdef LOOPBACK
+ clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
+ UCC_SLOW_GUMR_L_DIAG_LOOP);
+ clrsetbits_be32(&uccp->gumr_h,
+ UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
+ UCC_SLOW_GUMR_H_CDS);
+#endif
+
+ /* Enable rx interrupts and clear all pending events. */
+ out_be16(&uccp->uccm, 0);
+ out_be16(&uccp->ucce, 0xffff);
+ out_be16(&uccp->udsr, 0x7e7e);
+
+ /* Initialize UPSMR */
+ out_be16(&uccp->upsmr, 0);
+
+ if (soft_uart) {
+ out_be16(&uccup->supsmr, 0x30);
+ out_be16(&uccup->res92, 0);
+ out_be32(&uccup->rx_state, 0);
+ out_be32(&uccup->rx_cnt, 0);
+ out_8(&uccup->rx_bitmark, 0);
+ out_8(&uccup->rx_length, 10);
+ out_be32(&uccup->dump_ptr, 0x4000);
+ out_8(&uccup->rx_temp_dlst_qe, 0);
+ out_be32(&uccup->rx_frame_rem, 0);
+ out_8(&uccup->rx_frame_rem_size, 0);
+ /* Soft-UART requires TX to be 1X */
+ out_8(&uccup->tx_mode,
+ UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);
+ out_be16(&uccup->tx_state, 0);
+ out_8(&uccup->resD4, 0);
+ out_be16(&uccup->resD5, 0);
+
+ /* Set UART mode.
+ * Enable receive and transmit.
+ */
+
+ /* From the microcode errata:
+ * 1.GUMR_L register, set mode=0010 (QMC).
+ * 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
+ * 3.Set GUMR_H[19:20] (Transparent mode)
+ * 4.Clear GUMR_H[26] (RFW)
+ * ...
+ * 6.Receiver must use 16x over sampling
+ */
+ clrsetbits_be32(&uccp->gumr_l,
+ UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
+ UCC_SLOW_GUMR_L_RDCR_MASK,
+ UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |
+ UCC_SLOW_GUMR_L_RDCR_16);
+
+ clrsetbits_be32(&uccp->gumr_h,
+ UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
+ UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
+ UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
+
+#ifdef LOOPBACK
+ clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
+ UCC_SLOW_GUMR_L_DIAG_LOOP);
+ clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |
+ UCC_SLOW_GUMR_H_CDS);
+#endif
+
+ cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
+ qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
+ QE_CR_PROTOCOL_UNSPECIFIED, 0);
+ }
+}
+
+/*
+ * Initialize the port.
+ */
+static int qe_uart_startup(struct uart_port *port)
+{
+ struct uart_qe_port *qe_port =
+ container_of(port, struct uart_qe_port, port);
+ int ret;
+
+ /*
+ * If we're using Soft-UART mode, then we need to make sure the
+ * firmware has been uploaded first.
+ */
+ if (soft_uart && !firmware_loaded) {
+ dev_err(port->dev, "Soft-UART firmware not uploaded\n");
+ return -ENODEV;
+ }
+
+ qe_uart_initbd(qe_port);
+ qe_uart_init_ucc(qe_port);
+
+ /* Install interrupt handler. */
+ ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
+ qe_port);
+ if (ret) {
+ dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
+ return ret;
+ }
+
+ /* Startup rx-int */
+ setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
+ ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
+
+ return 0;
+}
+
+/*
+ * Shutdown the port.
+ */
+static void qe_uart_shutdown(struct uart_port *port)
+{
+ struct uart_qe_port *qe_port =
+ container_of(port, struct uart_qe_port, port);
+ struct ucc_slow __iomem *uccp = qe_port->uccp;
+ unsigned int timeout = 20;
+
+ /* Disable RX and TX */
+
+ /* Wait for all the BDs marked sent */
+ while (!qe_uart_tx_empty(port)) {
+ if (!--timeout) {
+ dev_warn(port->dev, "shutdown timeout\n");
+ break;
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(2);
+ }
+
+ if (qe_port->wait_closing) {
+ /* Wait a bit longer */
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(qe_port->wait_closing);
+ }
+
+ /* Stop uarts */
+ ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
+ clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
+
+ /* Shut them really down and reinit buffer descriptors */
+ ucc_slow_graceful_stop_tx(qe_port->us_private);
+ qe_uart_initbd(qe_port);
+
+ free_irq(port->irq, qe_port);
+}
+
+/*
+ * Set the serial port parameters.
+ */
+static void qe_uart_set_termios(struct uart_port *port,
+ struct ktermios *termios, struct ktermios *old)
+{
+ struct uart_qe_port *qe_port =
+ container_of(port, struct uart_qe_port, port);
+ struct ucc_slow __iomem *uccp = qe_port->uccp;
+ unsigned int baud;
+ unsigned long flags;
+ u16 upsmr = in_be16(&uccp->upsmr);
+ struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
+ u16 supsmr = in_be16(&uccup->supsmr);
+ u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
+
+ /* Character length programmed into the mode register is the
+ * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
+ * 1 or 2 stop bits, minus 1.
+ * The value 'bits' counts this for us.
+ */
+
+ /* byte size */
+ upsmr &= UCC_UART_UPSMR_CL_MASK;
+ supsmr &= UCC_UART_SUPSMR_CL_MASK;
+
+ switch (termios->c_cflag & CSIZE) {
+ case CS5:
+ upsmr |= UCC_UART_UPSMR_CL_5;
+ supsmr |= UCC_UART_SUPSMR_CL_5;
+ char_length += 5;
+ break;
+ case CS6:
+ upsmr |= UCC_UART_UPSMR_CL_6;
+ supsmr |= UCC_UART_SUPSMR_CL_6;
+ char_length += 6;
+ break;
+ case CS7:
+ upsmr |= UCC_UART_UPSMR_CL_7;
+ supsmr |= UCC_UART_SUPSMR_CL_7;
+ char_length += 7;
+ break;
+ default: /* case CS8 */
+ upsmr |= UCC_UART_UPSMR_CL_8;
+ supsmr |= UCC_UART_SUPSMR_CL_8;
+ char_length += 8;
+ break;
+ }
+
+ /* If CSTOPB is set, we want two stop bits */
+ if (termios->c_cflag & CSTOPB) {
+ upsmr |= UCC_UART_UPSMR_SL;
+ supsmr |= UCC_UART_SUPSMR_SL;
+ char_length++; /* + SL */
+ }
+
+ if (termios->c_cflag & PARENB) {
+ upsmr |= UCC_UART_UPSMR_PEN;
+ supsmr |= UCC_UART_SUPSMR_PEN;
+ char_length++; /* + PEN */
+
+ if (!(termios->c_cflag & PARODD)) {
+ upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
+ UCC_UART_UPSMR_TPM_MASK);
+ upsmr |= UCC_UART_UPSMR_RPM_EVEN |
+ UCC_UART_UPSMR_TPM_EVEN;
+ supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
+ UCC_UART_SUPSMR_TPM_MASK);
+ supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
+ UCC_UART_SUPSMR_TPM_EVEN;
+ }
+ }
+
+ /*
+ * Set up parity check flag
+ */
+ port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
+ if (termios->c_iflag & INPCK)
+ port->read_status_mask |= BD_SC_FR | BD_SC_PR;
+ if (termios->c_iflag & (BRKINT | PARMRK))
+ port->read_status_mask |= BD_SC_BR;
+
+ /*
+ * Characters to ignore
+ */
+ port->ignore_status_mask = 0;
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
+ if (termios->c_iflag & IGNBRK) {
+ port->ignore_status_mask |= BD_SC_BR;
+ /*
+ * If we're ignore parity and break indicators, ignore
+ * overruns too. (For real raw support).
+ */
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= BD_SC_OV;
+ }
+ /*
+ * !!! ignore all characters if CREAD is not set
+ */
+ if ((termios->c_cflag & CREAD) == 0)
+ port->read_status_mask &= ~BD_SC_EMPTY;
+
+ baud = uart_get_baud_rate(port, termios, old, 0, 115200);
+
+ /* Do we really need a spinlock here? */
+ spin_lock_irqsave(&port->lock, flags);
+
+ out_be16(&uccp->upsmr, upsmr);
+ if (soft_uart) {
+ out_be16(&uccup->supsmr, supsmr);
+ out_8(&uccup->rx_length, char_length);
+
+ /* Soft-UART requires a 1X multiplier for TX */
+ qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
+ qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
+ } else {
+ qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
+ qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
+ }
+
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+/*
+ * Return a pointer to a string that describes what kind of port this is.
+ */
+static const char *qe_uart_type(struct uart_port *port)
+{
+ return "QE";
+}
+
+/*
+ * Allocate any memory and I/O resources required by the port.
+ */
+static int qe_uart_request_port(struct uart_port *port)
+{
+ int ret;
+ struct uart_qe_port *qe_port =
+ container_of(port, struct uart_qe_port, port);
+ struct ucc_slow_info *us_info = &qe_port->us_info;
+ struct ucc_slow_private *uccs;
+ unsigned int rx_size, tx_size;
+ void *bd_virt;
+ dma_addr_t bd_dma_addr = 0;
+
+ ret = ucc_slow_init(us_info, &uccs);
+ if (ret) {
+ dev_err(port->dev, "could not initialize UCC%u\n",
+ qe_port->ucc_num);
+ return ret;
+ }
+
+ qe_port->us_private = uccs;
+ qe_port->uccp = uccs->us_regs;
+ qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
+ qe_port->rx_bd_base = uccs->rx_bd;
+ qe_port->tx_bd_base = uccs->tx_bd;
+
+ /*
+ * Allocate the transmit and receive data buffers.
+ */
+
+ rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
+ tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
+
+ bd_virt = dma_alloc_coherent(NULL, rx_size + tx_size, &bd_dma_addr,
+ GFP_KERNEL);
+ if (!bd_virt) {
+ dev_err(port->dev, "could not allocate buffer descriptors\n");
+ return -ENOMEM;
+ }
+
+ qe_port->bd_virt = bd_virt;
+ qe_port->bd_dma_addr = bd_dma_addr;
+ qe_port->bd_size = rx_size + tx_size;
+
+ qe_port->rx_buf = bd_virt;
+ qe_port->tx_buf = qe_port->rx_buf + rx_size;
+
+ return 0;
+}
+
+/*
+ * Configure the port.
+ *
+ * We say we're a CPM-type port because that's mostly true. Once the device
+ * is configured, this driver operates almost identically to the CPM serial
+ * driver.
+ */
+static void qe_uart_config_port(struct uart_port *port, int flags)
+{
+ if (flags & UART_CONFIG_TYPE) {
+ port->type = PORT_CPM;
+ qe_uart_request_port(port);
+ }
+}
+
+/*
+ * Release any memory and I/O resources that were allocated in
+ * qe_uart_request_port().
+ */
+static void qe_uart_release_port(struct uart_port *port)
+{
+ struct uart_qe_port *qe_port =
+ container_of(port, struct uart_qe_port, port);
+ struct ucc_slow_private *uccs = qe_port->us_private;
+
+ dma_free_coherent(NULL, qe_port->bd_size, qe_port->bd_virt,
+ qe_port->bd_dma_addr);
+
+ ucc_slow_free(uccs);
+}
+
+/*
+ * Verify that the data in serial_struct is suitable for this device.
+ */
+static int qe_uart_verify_port(struct uart_port *port,
+ struct serial_struct *ser)
+{
+ if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
+ return -EINVAL;
+
+ if (ser->irq < 0 || ser->irq >= NR_IRQS)
+ return -EINVAL;
+
+ if (ser->baud_base < 9600)
+ return -EINVAL;
+
+ return 0;
+}
+/* UART operations
+ *
+ * Details on these functions can be found in Documentation/serial/driver
+ */
+static struct uart_ops qe_uart_pops = {
+ .tx_empty = qe_uart_tx_empty,
+ .set_mctrl = qe_uart_set_mctrl,
+ .get_mctrl = qe_uart_get_mctrl,
+ .stop_tx = qe_uart_stop_tx,
+ .start_tx = qe_uart_start_tx,
+ .stop_rx = qe_uart_stop_rx,
+ .enable_ms = qe_uart_enable_ms,
+ .break_ctl = qe_uart_break_ctl,
+ .startup = qe_uart_startup,
+ .shutdown = qe_uart_shutdown,
+ .set_termios = qe_uart_set_termios,
+ .type = qe_uart_type,
+ .release_port = qe_uart_release_port,
+ .request_port = qe_uart_request_port,
+ .config_port = qe_uart_config_port,
+ .verify_port = qe_uart_verify_port,
+};
+
+/*
+ * Obtain the SOC model number and revision level
+ *
+ * This function parses the device tree to obtain the SOC model. It then
+ * reads the SVR register to the revision.
+ *
+ * The device tree stores the SOC model two different ways.
+ *
+ * The new way is:
+ *
+ * cpu@0 {
+ * compatible = "PowerPC,8323";
+ * device_type = "cpu";
+ * ...
+ *
+ *
+ * The old way is:
+ * PowerPC,8323@0 {
+ * device_type = "cpu";
+ * ...
+ *
+ * This code first checks the new way, and then the old way.
+ */
+static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
+{
+ struct device_node *np;
+ const char *soc_string;
+ unsigned int svr;
+ unsigned int soc;
+
+ /* Find the CPU node */
+ np = of_find_node_by_type(NULL, "cpu");
+ if (!np)
+ return 0;
+ /* Find the compatible property */
+ soc_string = of_get_property(np, "compatible", NULL);
+ if (!soc_string)
+ /* No compatible property, so try the name. */
+ soc_string = np->name;
+
+ /* Extract the SOC number from the "PowerPC," string */
+ if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
+ return 0;
+
+ /* Get the revision from the SVR */
+ svr = mfspr(SPRN_SVR);
+ *rev_h = (svr >> 4) & 0xf;
+ *rev_l = svr & 0xf;
+
+ return soc;
+}
+
+/*
+ * requst_firmware_nowait() callback function
+ *
+ * This function is called by the kernel when a firmware is made available,
+ * or if it times out waiting for the firmware.
+ */
+static void uart_firmware_cont(const struct firmware *fw, void *context)
+{
+ struct qe_firmware *firmware;
+ struct device *dev = context;
+ int ret;
+
+ if (!fw) {
+ dev_err(dev, "firmware not found\n");
+ return;
+ }
+
+ firmware = (struct qe_firmware *) fw->data;
+
+ if (firmware->header.length != fw->size) {
+ dev_err(dev, "invalid firmware\n");
+ return;
+ }
+
+ ret = qe_upload_firmware(firmware);
+ if (ret) {
+ dev_err(dev, "could not load firmware\n");
+ return;
+ }
+
+ firmware_loaded = 1;
+}
+
+static int ucc_uart_probe(struct of_device *ofdev,
+ const struct of_device_id *match)
+{
+ struct device_node *np = ofdev->node;
+ const unsigned int *iprop; /* Integer OF properties */
+ const char *sprop; /* String OF properties */
+ struct uart_qe_port *qe_port = NULL;
+ struct resource res;
+ int ret;
+
+ /*
+ * Determine if we need Soft-UART mode
+ */
+ if (of_find_property(np, "soft-uart", NULL)) {
+ dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
+ soft_uart = 1;
+ }
+
+ /*
+ * If we are using Soft-UART, determine if we need to upload the
+ * firmware, too.
+ */
+ if (soft_uart) {
+ struct qe_firmware_info *qe_fw_info;
+
+ qe_fw_info = qe_get_firmware_info();
+
+ /* Check if the firmware has been uploaded. */
+ if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
+ firmware_loaded = 1;
+ } else {
+ char filename[32];
+ unsigned int soc;
+ unsigned int rev_h;
+ unsigned int rev_l;
+
+ soc = soc_info(&rev_h, &rev_l);
+ if (!soc) {
+ dev_err(&ofdev->dev, "unknown CPU model\n");
+ return -ENXIO;
+ }
+ sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
+ soc, rev_h, rev_l);
+
+ dev_info(&ofdev->dev, "waiting for firmware %s\n",
+ filename);
+
+ /*
+ * We call request_firmware_nowait instead of
+ * request_firmware so that the driver can load and
+ * initialize the ports without holding up the rest of
+ * the kernel. If hotplug support is enabled in the
+ * kernel, then we use it.
+ */
+ ret = request_firmware_nowait(THIS_MODULE,
+ FW_ACTION_HOTPLUG, filename, &ofdev->dev,
+ &ofdev->dev, uart_firmware_cont);
+ if (ret) {
+ dev_err(&ofdev->dev,
+ "could not load firmware %s\n",
+ filename);
+ return ret;
+ }
+ }
+ }
+
+ qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
+ if (!qe_port) {
+ dev_err(&ofdev->dev, "can't allocate QE port structure\n");
+ return -ENOMEM;
+ }
+
+ /* Search for IRQ and mapbase */
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret) {
+ dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
+ kfree(qe_port);
+ return ret;
+ }
+ if (!res.start) {
+ dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
+ kfree(qe_port);
+ return -EINVAL;
+ }
+ qe_port->port.mapbase = res.start;
+
+ /* Get the UCC number (device ID) */
+ /* UCCs are numbered 1-7 */
+ iprop = of_get_property(np, "device-id", NULL);
+ if (!iprop || (*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
+ dev_err(&ofdev->dev,
+ "missing or invalid UCC specified in device tree\n");
+ kfree(qe_port);
+ return -ENODEV;
+ }
+ qe_port->ucc_num = *iprop - 1;
+
+ /*
+ * In the future, we should not require the BRG to be specified in the
+ * device tree. If no clock-source is specified, then just pick a BRG
+ * to use. This requires a new QE library function that manages BRG
+ * assignments.
+ */
+
+ sprop = of_get_property(np, "rx-clock-name", NULL);
+ if (!sprop) {
+ dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
+ kfree(qe_port);
+ return -ENODEV;
+ }
+
+ qe_port->us_info.rx_clock = qe_clock_source(sprop);
+ if ((qe_port->us_info.rx_clock < QE_BRG1) ||
+ (qe_port->us_info.rx_clock > QE_BRG16)) {
+ dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
+ kfree(qe_port);
+ return -ENODEV;
+ }
+
+#ifdef LOOPBACK
+ /* In internal loopback mode, TX and RX must use the same clock */
+ qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
+#else
+ sprop = of_get_property(np, "tx-clock-name", NULL);
+ if (!sprop) {
+ dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
+ kfree(qe_port);
+ return -ENODEV;
+ }
+ qe_port->us_info.tx_clock = qe_clock_source(sprop);
+#endif
+ if ((qe_port->us_info.tx_clock < QE_BRG1) ||
+ (qe_port->us_info.tx_clock > QE_BRG16)) {
+ dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
+ kfree(qe_port);
+ return -ENODEV;
+ }
+
+ /* Get the port number, numbered 0-3 */
+ iprop = of_get_property(np, "port-number", NULL);
+ if (!iprop) {
+ dev_err(&ofdev->dev, "missing port-number in device tree\n");
+ kfree(qe_port);
+ return -EINVAL;
+ }
+ qe_port->port.line = *iprop;
+ if (qe_port->port.line >= UCC_MAX_UART) {
+ dev_err(&ofdev->dev, "port-number must be 0-%u\n",
+ UCC_MAX_UART - 1);
+ kfree(qe_port);
+ return -EINVAL;
+ }
+
+ qe_port->port.irq = irq_of_parse_and_map(np, 0);
+ if (qe_port->port.irq == NO_IRQ) {
+ dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
+ qe_port->ucc_num + 1);
+ kfree(qe_port);
+ return -EINVAL;
+ }
+
+ /*
+ * Newer device trees have an "fsl,qe" compatible property for the QE
+ * node, but we still need to support older device trees.
+ */
+ np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+ if (!np) {
+ np = of_find_node_by_type(NULL, "qe");
+ if (!np) {
+ dev_err(&ofdev->dev, "could not find 'qe' node\n");
+ kfree(qe_port);
+ return -EINVAL;
+ }
+ }
+
+ iprop = of_get_property(np, "brg-frequency", NULL);
+ if (!iprop) {
+ dev_err(&ofdev->dev,
+ "missing brg-frequency in device tree\n");
+ kfree(qe_port);
+ return -EINVAL;
+ }
+
+ if (*iprop)
+ qe_port->port.uartclk = *iprop;
+ else {
+ /*
+ * Older versions of U-Boot do not initialize the brg-frequency
+ * property, so in this case we assume the BRG frequency is
+ * half the QE bus frequency.
+ */
+ iprop = of_get_property(np, "bus-frequency", NULL);
+ if (!iprop) {
+ dev_err(&ofdev->dev,
+ "missing QE bus-frequency in device tree\n");
+ kfree(qe_port);
+ return -EINVAL;
+ }
+ if (*iprop)
+ qe_port->port.uartclk = *iprop / 2;
+ else {
+ dev_err(&ofdev->dev,
+ "invalid QE bus-frequency in device tree\n");
+ kfree(qe_port);
+ return -EINVAL;
+ }
+ }
+
+ spin_lock_init(&qe_port->port.lock);
+ qe_port->np = np;
+ qe_port->port.dev = &ofdev->dev;
+ qe_port->port.ops = &qe_uart_pops;
+ qe_port->port.iotype = UPIO_MEM;
+
+ qe_port->tx_nrfifos = TX_NUM_FIFO;
+ qe_port->tx_fifosize = TX_BUF_SIZE;
+ qe_port->rx_nrfifos = RX_NUM_FIFO;
+ qe_port->rx_fifosize = RX_BUF_SIZE;
+
+ qe_port->wait_closing = UCC_WAIT_CLOSING;
+ qe_port->port.fifosize = 512;
+ qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
+
+ qe_port->us_info.ucc_num = qe_port->ucc_num;
+ qe_port->us_info.regs = (phys_addr_t) res.start;
+ qe_port->us_info.irq = qe_port->port.irq;
+
+ qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
+ qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
+
+ /* Make sure ucc_slow_init() initializes both TX and RX */
+ qe_port->us_info.init_tx = 1;
+ qe_port->us_info.init_rx = 1;
+
+ /* Add the port to the uart sub-system. This will cause
+ * qe_uart_config_port() to be called, so the us_info structure must
+ * be initialized.
+ */
+ ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
+ if (ret) {
+ dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
+ qe_port->port.line);
+ kfree(qe_port);
+ return ret;
+ }
+
+ dev_set_drvdata(&ofdev->dev, qe_port);
+
+ dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
+ qe_port->ucc_num + 1, qe_port->port.line);
+
+ /* Display the mknod command for this device */
+ dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
+ qe_port->port.line, SERIAL_QE_MAJOR,
+ SERIAL_QE_MINOR + qe_port->port.line);
+
+ return 0;
+}
+
+static int ucc_uart_remove(struct of_device *ofdev)
+{
+ struct uart_qe_port *qe_port = dev_get_drvdata(&ofdev->dev);
+
+ dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
+
+ uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
+
+ dev_set_drvdata(&ofdev->dev, NULL);
+ kfree(qe_port);
+
+ return 0;
+}
+
+static struct of_device_id ucc_uart_match[] = {
+ {
+ .type = "serial",
+ .compatible = "ucc_uart",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ucc_uart_match);
+
+static struct of_platform_driver ucc_uart_of_driver = {
+ .owner = THIS_MODULE,
+ .name = "ucc_uart",
+ .match_table = ucc_uart_match,
+ .probe = ucc_uart_probe,
+ .remove = ucc_uart_remove,
+};
+
+static int __init ucc_uart_init(void)
+{
+ int ret;
+
+ printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
+#ifdef LOOPBACK
+ printk(KERN_INFO "ucc-uart: Using loopback mode\n");
+#endif
+
+ ret = uart_register_driver(&ucc_uart_driver);
+ if (ret) {
+ printk(KERN_ERR "ucc-uart: could not register UART driver\n");
+ return ret;
+ }
+
+ ret = of_register_platform_driver(&ucc_uart_of_driver);
+ if (ret)
+ printk(KERN_ERR
+ "ucc-uart: could not register platform driver\n");
+
+ return ret;
+}
+
+static void __exit ucc_uart_exit(void)
+{
+ printk(KERN_INFO
+ "Freescale QUICC Engine UART device driver unloading\n");
+
+ of_unregister_platform_driver(&ucc_uart_of_driver);
+ uart_unregister_driver(&ucc_uart_driver);
+}
+
+module_init(ucc_uart_init);
+module_exit(ucc_uart_exit);
+
+MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
+MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);
+
--
1.5.2.4
^ permalink raw reply related
* Re: [PATCH 2/3] [libata] pata_of_platform: OF-Platform PATA device driver
From: Stephen Rothwell @ 2008-01-09 23:40 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Olof Johansson, linuxppc-dev, Paul Mundt, Jeff Garzik, linux-ide
In-Reply-To: <20080109191041.GB23283@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 361 bytes --]
Hi Anton,
Juts one small trivial comment (could be fixed later).
On Wed, 9 Jan 2008 22:10:41 +0300 Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
>
> +static struct of_device_id pata_of_platform_match[] = {
This could be declared const.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH 1/3] add default device trees for MPC837x MDS board
From: David Gibson @ 2008-01-09 23:42 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, Li Yang, paulus
In-Reply-To: <fa686aa40801080758o35dce96ej5db45576769561a5@mail.gmail.com>
On Tue, Jan 08, 2008 at 08:58:17AM -0700, Grant Likely wrote:
> Hi Leo,
>
> comments below. I've made my comments on the first file, but they
> apply to the other two also.
>
> Cheers,
> g.
[snip]
> > + ranges = <0 e0000000 00100000>;
> > + reg = <e0000000 00000200>;
> > + bus-frequency = <0>;
> > +
> > + wdt@200 {
> > + compatible = "mpc83xx_wdt";
>
> "fsl,mpc8377_wdt", "fsl,mpc83xx_wdt" as per generic names recommended practice.
Uh.. that's reasonable advice, but it has nothing to do with the
generic names recommended practice.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH] Fix remainder calculating bug in single floating point division
From: David Gibson @ 2008-01-09 23:48 UTC (permalink / raw)
To: Liu Yu; +Cc: linuxppc-dev
In-Reply-To: <6EBEC19BF4A8F843BCD6B9155BBE2515D1B515@zch01exm26.fsl.freescale.net>
On Wed, Jan 09, 2008 at 09:24:07AM +0800, Liu Yu wrote:
>
> >
> > can you provide the test case that shows the error.
> >
>
> It seems that math-emu only be used for MPC8xx on current kernel.
It can be used for IBM/AMCC 4xx too.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 2/3] [libata] pata_of_platform: OF-Platform PATA device driver
From: Olof Johansson @ 2008-01-10 0:36 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: Paul Mundt, linuxppc-dev, Jeff Garzik, linux-ide
In-Reply-To: <20080110104048.2fea6ab3.sfr@canb.auug.org.au>
On Thu, Jan 10, 2008 at 10:40:48AM +1100, Stephen Rothwell wrote:
> Hi Anton,
>
> Juts one small trivial comment (could be fixed later).
>
> On Wed, 9 Jan 2008 22:10:41 +0300 Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> >
> > +static struct of_device_id pata_of_platform_match[] = {
>
> This could be declared const.
Good point, but let's not hold up merge based on this. Need something
for janitors to do too, and it's good enough to merge as-is. :)
-Olof
^ permalink raw reply
* Re: [PATCH 1/3] add default device trees for MPC837x MDS board
From: Grant Likely @ 2008-01-10 0:59 UTC (permalink / raw)
To: Grant Likely, Li Yang, linuxppc-dev, paulus
In-Reply-To: <20080109234215.GA17153@localhost.localdomain>
On 1/9/08, David Gibson <david@gibson.dropbear.id.au> wrote:
> On Tue, Jan 08, 2008 at 08:58:17AM -0700, Grant Likely wrote:
> > > + compatible = "mpc83xx_wdt";
> >
> > "fsl,mpc8377_wdt", "fsl,mpc83xx_wdt" as per generic names recommended practice.
>
> Uh.. that's reasonable advice, but it has nothing to do with the
> generic names recommended practice.
Actually, that *is* advice given in the generic names recommended
practice document:
http://www.openfirmware.org/1275/practice/gnames/gnamv14a.html#HDR11
Section 6.2, last sentence.
:-)
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* [patch 2/4 v3] PS3: Add logical performance monitor repository routines
From: Geoff Levand @ 2008-01-10 1:01 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Takashi Yamamoto
In-Reply-To: <47846B38.7010409@am.sony.com>
From: Takashi Yamamoto <TakashiA.Yamamoto@jp.sony.com>
Add repository routines for the PS3 logical performance monitor.
Signed-off-by: Takashi Yamamoto <TakashiA.Yamamoto@jp.sony.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
v2: o Correct Yamamoto-san's mail addr.
v3: o Change num_pu and pu_id to type u64.
o Add comments to describe some symbol names.
arch/powerpc/platforms/ps3/platform.h | 12 +++--
arch/powerpc/platforms/ps3/repository.c | 75 +++++++++++++++++++++++++++++++-
2 files changed, 83 insertions(+), 4 deletions(-)
--- a/arch/powerpc/platforms/ps3/platform.h
+++ b/arch/powerpc/platforms/ps3/platform.h
@@ -186,10 +186,10 @@ int ps3_repository_read_stor_dev_region(
unsigned int dev_index, unsigned int region_index,
unsigned int *region_id, u64 *region_start, u64 *region_size);
-/* repository pu and memory info */
+/* repository logical pu and memory info */
-int ps3_repository_read_num_pu(unsigned int *num_pu);
-int ps3_repository_read_ppe_id(unsigned int *pu_index, unsigned int *ppe_id);
+int ps3_repository_read_num_pu(u64 *num_pu);
+int ps3_repository_read_pu_id(unsigned int pu_index, u64 *pu_id);
int ps3_repository_read_rm_base(unsigned int ppe_id, u64 *rm_base);
int ps3_repository_read_rm_size(unsigned int ppe_id, u64 *rm_size);
int ps3_repository_read_region_total(u64 *region_total);
@@ -200,9 +200,15 @@ int ps3_repository_read_mm_info(u64 *rm_
int ps3_repository_read_num_be(unsigned int *num_be);
int ps3_repository_read_be_node_id(unsigned int be_index, u64 *node_id);
+int ps3_repository_read_be_id(u64 node_id, u64 *be_id);
int ps3_repository_read_tb_freq(u64 node_id, u64 *tb_freq);
int ps3_repository_read_be_tb_freq(unsigned int be_index, u64 *tb_freq);
+/* repository performance monitor info */
+
+int ps3_repository_read_lpm_privileges(unsigned int be_index, u64 *lpar,
+ u64 *rights);
+
/* repository 'Other OS' area */
int ps3_repository_read_boot_dat_addr(u64 *lpar_addr);
--- a/arch/powerpc/platforms/ps3/repository.c
+++ b/arch/powerpc/platforms/ps3/repository.c
@@ -684,6 +684,35 @@ int ps3_repository_read_stor_dev_region(
return result;
}
+/**
+ * ps3_repository_read_num_pu - Number of logical PU processors for this lpar.
+ */
+
+int ps3_repository_read_num_pu(u64 *num_pu)
+{
+ *num_pu = 0;
+ return read_node(PS3_LPAR_ID_CURRENT,
+ make_first_field("bi", 0),
+ make_field("pun", 0),
+ 0, 0,
+ num_pu, NULL);
+}
+
+/**
+ * ps3_repository_read_pu_id - Read the logical PU id.
+ * @pu_index: Zero based index.
+ * @pu_id: The logical PU id.
+ */
+
+int ps3_repository_read_pu_id(unsigned int pu_index, u64 *pu_id)
+{
+ return read_node(PS3_LPAR_ID_CURRENT,
+ make_first_field("bi", 0),
+ make_field("pu", pu_index),
+ 0, 0,
+ pu_id, NULL);
+}
+
int ps3_repository_read_rm_size(unsigned int ppe_id, u64 *rm_size)
{
return read_node(PS3_LPAR_ID_CURRENT,
@@ -856,6 +885,10 @@ int ps3_repository_read_boot_dat_info(u6
: ps3_repository_read_boot_dat_size(size);
}
+/**
+ * ps3_repository_read_num_be - Number of physical BE processors in the system.
+ */
+
int ps3_repository_read_num_be(unsigned int *num_be)
{
int result;
@@ -871,6 +904,12 @@ int ps3_repository_read_num_be(unsigned
return result;
}
+/**
+ * ps3_repository_read_be_node_id - Read the physical BE processor node id.
+ * @be_index: Zero based index.
+ * @node_id: The BE processor node id.
+ */
+
int ps3_repository_read_be_node_id(unsigned int be_index, u64 *node_id)
{
return read_node(PS3_LPAR_ID_PME,
@@ -881,6 +920,22 @@ int ps3_repository_read_be_node_id(unsig
node_id, 0);
}
+/**
+ * ps3_repository_read_be_id - Read the physical BE processor id.
+ * @node_id: The BE processor node id.
+ * @be_id: The BE processor id.
+ */
+
+int ps3_repository_read_be_id(u64 node_id, u64 *be_id)
+{
+ return read_node(PS3_LPAR_ID_PME,
+ make_first_field("be", 0),
+ node_id,
+ 0,
+ 0,
+ be_id, NULL);
+}
+
int ps3_repository_read_tb_freq(u64 node_id, u64 *tb_freq)
{
return read_node(PS3_LPAR_ID_PME,
@@ -897,11 +952,29 @@ int ps3_repository_read_be_tb_freq(unsig
u64 node_id;
*tb_freq = 0;
- result = ps3_repository_read_be_node_id(0, &node_id);
+ result = ps3_repository_read_be_node_id(be_index, &node_id);
return result ? result
: ps3_repository_read_tb_freq(node_id, tb_freq);
}
+int ps3_repository_read_lpm_privileges(unsigned int be_index, u64 *lpar,
+ u64 *rights)
+{
+ int result;
+ u64 node_id;
+
+ *lpar = 0;
+ *rights = 0;
+ result = ps3_repository_read_be_node_id(be_index, &node_id);
+ return result ? result
+ : read_node(PS3_LPAR_ID_PME,
+ make_first_field("be", 0),
+ node_id,
+ make_field("lpm", 0),
+ make_field("priv", 0),
+ lpar, rights);
+}
+
#if defined(DEBUG)
int ps3_repository_dump_resource_info(const struct ps3_repository_device *repo)
^ permalink raw reply
* [patch 3/4 v3] PS3: Add logical performance monitor device support
From: Geoff Levand @ 2008-01-10 1:01 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
In-Reply-To: <47846B3F.6060003@am.sony.com>
Add PS3 logical performance monitor device support to the
PS3 system-bus and platform device registration routines.
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
v2: o Add enum ps3_lpm_tb_type.
o Remove redundant enclosing structure and return proper
error codes from ps3_register_lpm_devices().
v3: o Add lpm.node_id to struct ps3_system_bus_device.
o Cleanup repository discovery logic.
arch/powerpc/platforms/ps3/device-init.c | 85 +++++++++++++++++++++++++++++++
arch/powerpc/platforms/ps3/system-bus.c | 5 +
include/asm-powerpc/ps3.h | 8 ++
3 files changed, 98 insertions(+)
create mode 100644 arch/powerpc/platforms/ps3/lpm.c
--- a/arch/powerpc/platforms/ps3/device-init.c
+++ b/arch/powerpc/platforms/ps3/device-init.c
@@ -30,6 +30,89 @@
#include "platform.h"
+static int __init ps3_register_lpm_devices(void)
+{
+ int result;
+ u64 tmp1;
+ u64 tmp2;
+ struct ps3_system_bus_device *dev;
+
+ pr_debug(" -> %s:%d\n", __func__, __LINE__);
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return -ENOMEM;
+
+ dev->match_id = PS3_MATCH_ID_LPM;
+ dev->dev_type = PS3_DEVICE_TYPE_LPM;
+
+ /* The current lpm driver only supports a single BE processor. */
+
+ result = ps3_repository_read_be_node_id(0, &dev->lpm.node_id);
+
+ if (result) {
+ pr_debug("%s:%d: ps3_repository_read_be_node_id failed \n",
+ __func__, __LINE__);
+ goto fail_read_repo;
+ }
+
+ result = ps3_repository_read_lpm_privileges(dev->lpm.node_id, &tmp1,
+ &dev->lpm.rights);
+
+ if (result) {
+ pr_debug("%s:%d: ps3_repository_read_lpm_privleges failed \n",
+ __func__, __LINE__);
+ goto fail_read_repo;
+ }
+
+ lv1_get_logical_partition_id(&tmp2);
+
+ if (tmp1 != tmp2) {
+ pr_debug("%s:%d: wrong lpar\n",
+ __func__, __LINE__);
+ result = -ENODEV;
+ goto fail_rights;
+ }
+
+ if (!(dev->lpm.rights & PS3_LPM_RIGHTS_USE_LPM)) {
+ pr_debug("%s:%d: don't have rights to use lpm\n",
+ __func__, __LINE__);
+ result = -EPERM;
+ goto fail_rights;
+ }
+
+ pr_debug("%s:%d: pu_id %lu, rights %lu(%lxh)\n",
+ __func__, __LINE__, dev->lpm.pu_id, dev->lpm.rights,
+ dev->lpm.rights);
+
+ result = ps3_repository_read_pu_id(0, &dev->lpm.pu_id);
+
+ if (result) {
+ pr_debug("%s:%d: ps3_repository_read_pu_id failed \n",
+ __func__, __LINE__);
+ goto fail_read_repo;
+ }
+
+ result = ps3_system_bus_device_register(dev);
+
+ if (result) {
+ pr_debug("%s:%d ps3_system_bus_device_register failed\n",
+ __func__, __LINE__);
+ goto fail_register;
+ }
+
+ pr_debug(" <- %s:%d\n", __func__, __LINE__);
+ return 0;
+
+
+fail_register:
+fail_rights:
+fail_read_repo:
+ kfree(dev);
+ pr_debug(" <- %s:%d: failed\n", __func__, __LINE__);
+ return result;
+}
+
/**
* ps3_setup_gelic_device - Setup and register a gelic device instance.
*
@@ -787,6 +870,8 @@ static int __init ps3_register_devices(v
ps3_register_sound_devices();
+ ps3_register_lpm_devices();
+
pr_debug(" <- %s:%d\n", __func__, __LINE__);
return 0;
}
--- a/arch/powerpc/platforms/ps3/system-bus.c
+++ b/arch/powerpc/platforms/ps3/system-bus.c
@@ -715,6 +715,7 @@ int ps3_system_bus_device_register(struc
static unsigned int dev_ioc0_count;
static unsigned int dev_sb_count;
static unsigned int dev_vuart_count;
+ static unsigned int dev_lpm_count;
if (!dev->core.parent)
dev->core.parent = &ps3_system_bus;
@@ -737,6 +738,10 @@ int ps3_system_bus_device_register(struc
snprintf(dev->core.bus_id, sizeof(dev->core.bus_id),
"vuart_%02x", ++dev_vuart_count);
break;
+ case PS3_DEVICE_TYPE_LPM:
+ snprintf(dev->core.bus_id, sizeof(dev->core.bus_id),
+ "lpm_%02x", ++dev_lpm_count);
+ break;
default:
BUG();
};
--- a/include/asm-powerpc/ps3.h
+++ b/include/asm-powerpc/ps3.h
@@ -317,6 +317,7 @@ enum ps3_match_id {
PS3_MATCH_ID_STOR_FLASH = 8,
PS3_MATCH_ID_SOUND = 9,
PS3_MATCH_ID_GRAPHICS = 10,
+ PS3_MATCH_ID_LPM = 11,
};
#define PS3_MODULE_ALIAS_EHCI "ps3:1"
@@ -329,11 +330,13 @@ enum ps3_match_id {
#define PS3_MODULE_ALIAS_STOR_FLASH "ps3:8"
#define PS3_MODULE_ALIAS_SOUND "ps3:9"
#define PS3_MODULE_ALIAS_GRAPHICS "ps3:10"
+#define PS3_MODULE_ALIAS_LPM "ps3:11"
enum ps3_system_bus_device_type {
PS3_DEVICE_TYPE_IOC0 = 1,
PS3_DEVICE_TYPE_SB,
PS3_DEVICE_TYPE_VUART,
+ PS3_DEVICE_TYPE_LPM,
};
/**
@@ -350,6 +353,11 @@ struct ps3_system_bus_device {
struct ps3_dma_region *d_region; /* SB, IOC0 */
struct ps3_mmio_region *m_region; /* SB, IOC0*/
unsigned int port_number; /* VUART */
+ struct { /* LPM */
+ u64 node_id;
+ u64 pu_id;
+ u64 rights;
+ } lpm;
/* struct iommu_table *iommu_table; -- waiting for BenH's cleanups */
struct device core;
^ permalink raw reply
* [patch 4/4 v3] PS3: Add logical performance monitor driver support
From: Geoff Levand @ 2008-01-10 1:01 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Takashi Yamamoto
In-Reply-To: <47846B48.5000003@am.sony.com>
From: Takashi Yamamoto <TakashiA.Yamamoto@jp.sony.com>
Add PS3 logical performance monitor (lpm) device driver.
The PS3's LV1 hypervisor provides a Logical Performance Monitor that
abstracts the Cell processor's performance monitor features for use
by guest operating systems.
Signed-off-by: Takashi Yamamoto <TakashiA.Yamamoto@jp.sony.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
v2: o Correct Yamamoto-san's mail addr.
o Text cleanups.
o Added more comments explaining lpm operation.
o Split SRPN_BKMK into separate patch.
o Use get_hard_smp_processor_id() in ps3_get_hw_thread_id().
o Split ps3_copy_trace_buffer() into ps3_lpm_copy_tb() and ps3_lpm_copy_tb_to_user().
o Replace mutex with atomic_t in ps3_lpm_open()/ps3_lpm_close().
o General cleanup of ps3_lpm_open()/ps3_lpm_close().
v3:
o Add BE node_id to struct lpm_priv.
o Change some dev_err() to dev_dbg().
o Fix kzalloc() bug.
o Text fix 'lost' -> 'loss'.
o Use lpm_priv->node_id with lv1_construct_lpm().
arch/powerpc/platforms/ps3/Kconfig | 13
drivers/ps3/Makefile | 1
drivers/ps3/ps3-lpm.c | 1248 +++++++++++++++++++++++++++++++++++++
include/asm-powerpc/ps3.h | 62 +
4 files changed, 1324 insertions(+)
create mode 100644 arch/powerpc/platforms/ps3/ps3-lpm.c
--- a/arch/powerpc/platforms/ps3/Kconfig
+++ b/arch/powerpc/platforms/ps3/Kconfig
@@ -138,4 +138,17 @@ config PS3_FLASH
be disabled on the kernel command line using "ps3flash=off", to
not allocate this fixed buffer.
+config PS3_LPM
+ tristate "PS3 Logical Performance Monitor support"
+ depends on PPC_PS3
+ help
+ Include support for the PS3 Logical Performance Monitor.
+
+ This support is required to use the logical performance monitor
+ of the PS3's LV1 hypervisor.
+
+ If you intend to use the advanced performance monitoring and
+ profiling support of the Cell processor with programs like
+ oprofile and perfmon2, then say Y or M, otherwise say N.
+
endmenu
--- a/drivers/ps3/Makefile
+++ b/drivers/ps3/Makefile
@@ -4,3 +4,4 @@ ps3av_mod-objs += ps3av.o ps3av_cmd.o
obj-$(CONFIG_PPC_PS3) += sys-manager-core.o
obj-$(CONFIG_PS3_SYS_MANAGER) += ps3-sys-manager.o
obj-$(CONFIG_PS3_STORAGE) += ps3stor_lib.o
+obj-$(CONFIG_PS3_LPM) += ps3-lpm.o
--- /dev/null
+++ b/drivers/ps3/ps3-lpm.c
@@ -0,0 +1,1248 @@
+/*
+ * PS3 Logical Performance Monitor.
+ *
+ * Copyright (C) 2007 Sony Computer Entertainment Inc.
+ * Copyright 2007 Sony Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/uaccess.h>
+#include <asm/ps3.h>
+#include <asm/lv1call.h>
+#include <asm/cell-pmu.h>
+
+
+/* BOOKMARK tag macros */
+#define PS3_PM_BOOKMARK_START 0x8000000000000000ULL
+#define PS3_PM_BOOKMARK_STOP 0x4000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_KERNEL 0x1000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_USER 0x3000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_MASK_HI 0xF000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_MASK_LO 0x0F00000000000000ULL
+
+/* CBE PM CONTROL register macros */
+#define PS3_PM_CONTROL_PPU_TH0_BOOKMARK 0x00001000
+#define PS3_PM_CONTROL_PPU_TH1_BOOKMARK 0x00000800
+#define PS3_PM_CONTROL_PPU_COUNT_MODE_MASK 0x000C0000
+#define PS3_PM_CONTROL_PPU_COUNT_MODE_PROBLEM 0x00080000
+#define PS3_WRITE_PM_MASK 0xFFFFFFFFFFFFFFFFULL
+
+/* CBE PM START STOP register macros */
+#define PS3_PM_START_STOP_PPU_TH0_BOOKMARK_START 0x02000000
+#define PS3_PM_START_STOP_PPU_TH1_BOOKMARK_START 0x01000000
+#define PS3_PM_START_STOP_PPU_TH0_BOOKMARK_STOP 0x00020000
+#define PS3_PM_START_STOP_PPU_TH1_BOOKMARK_STOP 0x00010000
+#define PS3_PM_START_STOP_START_MASK 0xFF000000
+#define PS3_PM_START_STOP_STOP_MASK 0x00FF0000
+
+/* CBE PM COUNTER register macres */
+#define PS3_PM_COUNTER_MASK_HI 0xFFFFFFFF00000000ULL
+#define PS3_PM_COUNTER_MASK_LO 0x00000000FFFFFFFFULL
+
+/* BASE SIGNAL GROUP NUMBER macros */
+#define PM_ISLAND2_BASE_SIGNAL_GROUP_NUMBER 0
+#define PM_ISLAND2_SIGNAL_GROUP_NUMBER1 6
+#define PM_ISLAND2_SIGNAL_GROUP_NUMBER2 7
+#define PM_ISLAND3_BASE_SIGNAL_GROUP_NUMBER 7
+#define PM_ISLAND4_BASE_SIGNAL_GROUP_NUMBER 15
+#define PM_SPU_TRIGGER_SIGNAL_GROUP_NUMBER 17
+#define PM_SPU_EVENT_SIGNAL_GROUP_NUMBER 18
+#define PM_ISLAND5_BASE_SIGNAL_GROUP_NUMBER 18
+#define PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER 24
+#define PM_ISLAND7_BASE_SIGNAL_GROUP_NUMBER 49
+#define PM_ISLAND8_BASE_SIGNAL_GROUP_NUMBER 52
+#define PM_SIG_GROUP_SPU 41
+#define PM_SIG_GROUP_SPU_TRIGGER 42
+#define PM_SIG_GROUP_SPU_EVENT 43
+#define PM_SIG_GROUP_MFC_MAX 60
+
+/**
+ * struct ps3_lpm_shadow_regs - Performance monitor shadow registers.
+ *
+ * @pm_control: Shadow of the processor's pm_control register.
+ * @pm_start_stop: Shadow of the processor's pm_start_stop register.
+ * @pm_interval: Shadow of the processor's pm_interval register.
+ * @group_control: Shadow of the processor's group_control register.
+ * @debug_bus_control: Shadow of the processor's debug_bus_control register.
+ *
+ * The logical performance monitor provides a write-only interface to
+ * these processor registers. These shadow variables cache the processor
+ * register values for reading.
+ *
+ * The initial value of the shadow registers at lpm creation is
+ * PS3_LPM_SHADOW_REG_INIT.
+ */
+
+struct ps3_lpm_shadow_regs {
+ u64 pm_control;
+ u64 pm_start_stop;
+ u64 pm_interval;
+ u64 group_control;
+ u64 debug_bus_control;
+};
+
+#define PS3_LPM_SHADOW_REG_INIT 0xFFFFFFFF00000000ULL
+
+/**
+ * struct ps3_lpm_priv - Private lpm device data.
+ *
+ * @open: An atomic variable indicating the lpm driver has been opened.
+ * @rights: The lpm rigths granted by the system policy module. A logical
+ * OR of enum ps3_lpm_rights.
+ * @node_id: The node id of a BE prosessor whos performance monitor this
+ * lpar has the right to use.
+ * @pu_id: The lv1 id of the logical PU.
+ * @lpm_id: The lv1 id of this lpm instance.
+ * @outlet_id: The outlet created by lv1 for this lpm instance.
+ * @tb_count: The number of bytes of data held in the lv1 trace buffer.
+ * @tb_cache: Kernel buffer to receive the data from the lv1 trace buffer.
+ * Must be 128 byte aligned.
+ * @tb_cache_size: Size of the kernel @tb_cache buffer. Must be 128 byte
+ * aligned.
+ * @tb_cache_internal: An unaligned buffer allocated by this driver to be
+ * used for the trace buffer cache when ps3_lpm_open() is called with a
+ * NULL tb_cache argument. Otherwise unused.
+ * @shadow: Processor register shadow of type struct ps3_lpm_shadow_regs.
+ * @sbd: The struct ps3_system_bus_device attached to this driver.
+ *
+ * The trace buffer is a buffer allocated and used internally to the lv1
+ * hypervisor to collect trace data. The trace buffer cache is a guest
+ * buffer that accepts the trace data from the trace buffer.
+ */
+
+struct ps3_lpm_priv {
+ atomic_t open;
+ u64 rights;
+ u64 node_id;
+ u64 pu_id;
+ u64 lpm_id;
+ u64 outlet_id;
+ u64 tb_count;
+ void *tb_cache;
+ u64 tb_cache_size;
+ void *tb_cache_internal;
+ struct ps3_lpm_shadow_regs shadow;
+ struct ps3_system_bus_device *sbd;
+};
+
+enum {
+ PS3_LPM_DEFAULT_TB_CACHE_SIZE = 0x4000,
+};
+
+/**
+ * lpm_priv - Static instance of the lpm data.
+ *
+ * Since the exported routines don't support the notion of a device
+ * instance we need to hold the instance in this static variable
+ * and then only allow at most one instance at a time to be created.
+ */
+
+static struct ps3_lpm_priv *lpm_priv;
+
+static struct device *sbd_core(void)
+{
+ BUG_ON(!lpm_priv || !lpm_priv->sbd);
+ return &lpm_priv->sbd->core;
+}
+
+/**
+ * use_start_stop_bookmark - Enable the PPU bookmark trace.
+ *
+ * And it enables PPU bookmark triggers ONLY if the other triggers are not set.
+ * The start/stop bookmarks are inserted at ps3_enable_pm() and ps3_disable_pm()
+ * to start/stop LPM.
+ *
+ * Used to get good quality of the performance counter.
+ */
+
+enum {use_start_stop_bookmark = 1,};
+
+void ps3_set_bookmark(u64 bookmark)
+{
+ /*
+ * As per the PPE book IV, to avoid bookmark loss there must
+ * not be a traced branch within 10 cycles of setting the
+ * SPRN_BKMK register. The actual text is unclear if 'within'
+ * includes cycles before the call.
+ */
+
+ asm volatile("or 29, 29, 29;"); /* db10cyc */
+ mtspr(SPRN_BKMK, bookmark);
+ asm volatile("or 29, 29, 29;"); /* db10cyc */
+}
+EXPORT_SYMBOL_GPL(ps3_set_bookmark);
+
+void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id)
+{
+ u64 bookmark;
+
+ bookmark = (get_tb() & 0x00000000FFFFFFFFULL) |
+ PS3_PM_BOOKMARK_TAG_KERNEL;
+ bookmark = ((tag << 56) & PS3_PM_BOOKMARK_TAG_MASK_LO) |
+ (incident << 48) | (th_id << 32) | bookmark;
+ ps3_set_bookmark(bookmark);
+}
+EXPORT_SYMBOL_GPL(ps3_set_pm_bookmark);
+
+/**
+ * ps3_read_phys_ctr - Read physical counter registers.
+ *
+ * Each physical counter can act as one 32 bit counter or as two 16 bit
+ * counters.
+ */
+
+u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr)
+{
+ int result;
+ u64 counter0415;
+ u64 counter2637;
+
+ if (phys_ctr >= NR_PHYS_CTRS) {
+ dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
+ __LINE__, phys_ctr);
+ return 0;
+ }
+
+ result = lv1_set_lpm_counter(lpm_priv->lpm_id, 0, 0, 0, 0, &counter0415,
+ &counter2637);
+ if (result) {
+ dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter failed: "
+ "phys_ctr %u, %s\n", __func__, __LINE__, phys_ctr,
+ ps3_result(result));
+ return 0;
+ }
+
+ switch (phys_ctr) {
+ case 0:
+ return counter0415 >> 32;
+ case 1:
+ return counter0415 & PS3_PM_COUNTER_MASK_LO;
+ case 2:
+ return counter2637 >> 32;
+ case 3:
+ return counter2637 & PS3_PM_COUNTER_MASK_LO;
+ default:
+ BUG();
+ }
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_read_phys_ctr);
+
+/**
+ * ps3_write_phys_ctr - Write physical counter registers.
+ *
+ * Each physical counter can act as one 32 bit counter or as two 16 bit
+ * counters.
+ */
+
+void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
+{
+ u64 counter0415;
+ u64 counter0415_mask;
+ u64 counter2637;
+ u64 counter2637_mask;
+ int result;
+
+ if (phys_ctr >= NR_PHYS_CTRS) {
+ dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
+ __LINE__, phys_ctr);
+ return;
+ }
+
+ switch (phys_ctr) {
+ case 0:
+ counter0415 = (u64)val << 32;
+ counter0415_mask = PS3_PM_COUNTER_MASK_HI;
+ counter2637 = 0x0;
+ counter2637_mask = 0x0;
+ break;
+ case 1:
+ counter0415 = (u64)val;
+ counter0415_mask = PS3_PM_COUNTER_MASK_LO;
+ counter2637 = 0x0;
+ counter2637_mask = 0x0;
+ break;
+ case 2:
+ counter0415 = 0x0;
+ counter0415_mask = 0x0;
+ counter2637 = (u64)val << 32;
+ counter2637_mask = PS3_PM_COUNTER_MASK_HI;
+ break;
+ case 3:
+ counter0415 = 0x0;
+ counter0415_mask = 0x0;
+ counter2637 = (u64)val;
+ counter2637_mask = PS3_PM_COUNTER_MASK_LO;
+ break;
+ default:
+ BUG();
+ }
+
+ result = lv1_set_lpm_counter(lpm_priv->lpm_id,
+ counter0415, counter0415_mask,
+ counter2637, counter2637_mask,
+ &counter0415, &counter2637);
+ if (result)
+ dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter failed: "
+ "phys_ctr %u, val %u, %s\n", __func__, __LINE__,
+ phys_ctr, val, ps3_result(result));
+}
+EXPORT_SYMBOL_GPL(ps3_write_phys_ctr);
+
+/**
+ * ps3_read_ctr - Read counter.
+ *
+ * Read 16 or 32 bits depending on the current size of the counter.
+ * Counters 4, 5, 6 & 7 are always 16 bit.
+ */
+
+u32 ps3_read_ctr(u32 cpu, u32 ctr)
+{
+ u32 val;
+ u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
+
+ val = ps3_read_phys_ctr(cpu, phys_ctr);
+
+ if (ps3_get_ctr_size(cpu, phys_ctr) == 16)
+ val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
+
+ return val;
+}
+EXPORT_SYMBOL_GPL(ps3_read_ctr);
+
+/**
+ * ps3_write_ctr - Write counter.
+ *
+ * Write 16 or 32 bits depending on the current size of the counter.
+ * Counters 4, 5, 6 & 7 are always 16 bit.
+ */
+
+void ps3_write_ctr(u32 cpu, u32 ctr, u32 val)
+{
+ u32 phys_ctr;
+ u32 phys_val;
+
+ phys_ctr = ctr & (NR_PHYS_CTRS - 1);
+
+ if (ps3_get_ctr_size(cpu, phys_ctr) == 16) {
+ phys_val = ps3_read_phys_ctr(cpu, phys_ctr);
+
+ if (ctr < NR_PHYS_CTRS)
+ val = (val << 16) | (phys_val & 0xffff);
+ else
+ val = (val & 0xffff) | (phys_val & 0xffff0000);
+ }
+
+ ps3_write_phys_ctr(cpu, phys_ctr, val);
+}
+EXPORT_SYMBOL_GPL(ps3_write_ctr);
+
+/**
+ * ps3_read_pm07_control - Read counter control registers.
+ *
+ * Each logical counter has a corresponding control register.
+ */
+
+u32 ps3_read_pm07_control(u32 cpu, u32 ctr)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_read_pm07_control);
+
+/**
+ * ps3_write_pm07_control - Write counter control registers.
+ *
+ * Each logical counter has a corresponding control register.
+ */
+
+void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val)
+{
+ int result;
+ static const u64 mask = 0xFFFFFFFFFFFFFFFFULL;
+ u64 old_value;
+
+ if (ctr >= NR_CTRS) {
+ dev_dbg(sbd_core(), "%s:%u: ctr too big: %u\n", __func__,
+ __LINE__, ctr);
+ return;
+ }
+
+ result = lv1_set_lpm_counter_control(lpm_priv->lpm_id, ctr, val, mask,
+ &old_value);
+ if (result)
+ dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter_control "
+ "failed: ctr %u, %s\n", __func__, __LINE__, ctr,
+ ps3_result(result));
+}
+EXPORT_SYMBOL_GPL(ps3_write_pm07_control);
+
+/**
+ * ps3_read_pm - Read Other LPM control registers.
+ */
+
+u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg)
+{
+ int result = 0;
+ u64 val = 0;
+
+ switch (reg) {
+ case pm_control:
+ return lpm_priv->shadow.pm_control;
+ case trace_address:
+ return CBE_PM_TRACE_BUF_EMPTY;
+ case pm_start_stop:
+ return lpm_priv->shadow.pm_start_stop;
+ case pm_interval:
+ return lpm_priv->shadow.pm_interval;
+ case group_control:
+ return lpm_priv->shadow.group_control;
+ case debug_bus_control:
+ return lpm_priv->shadow.debug_bus_control;
+ case pm_status:
+ result = lv1_get_lpm_interrupt_status(lpm_priv->lpm_id,
+ &val);
+ if (result) {
+ val = 0;
+ dev_dbg(sbd_core(), "%s:%u: lv1 get_lpm_status failed: "
+ "reg %u, %s\n", __func__, __LINE__, reg,
+ ps3_result(result));
+ }
+ return (u32)val;
+ case ext_tr_timer:
+ return 0;
+ default:
+ dev_dbg(sbd_core(), "%s:%u: unknown reg: %d\n", __func__,
+ __LINE__, reg);
+ BUG();
+ break;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_read_pm);
+
+/**
+ * ps3_write_pm - Write Other LPM control registers.
+ */
+
+void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
+{
+ int result = 0;
+ u64 dummy;
+
+ switch (reg) {
+ case group_control:
+ if (val != lpm_priv->shadow.group_control)
+ result = lv1_set_lpm_group_control(lpm_priv->lpm_id,
+ val,
+ PS3_WRITE_PM_MASK,
+ &dummy);
+ lpm_priv->shadow.group_control = val;
+ break;
+ case debug_bus_control:
+ if (val != lpm_priv->shadow.debug_bus_control)
+ result = lv1_set_lpm_debug_bus_control(lpm_priv->lpm_id,
+ val,
+ PS3_WRITE_PM_MASK,
+ &dummy);
+ lpm_priv->shadow.debug_bus_control = val;
+ break;
+ case pm_control:
+ if (use_start_stop_bookmark)
+ val |= (PS3_PM_CONTROL_PPU_TH0_BOOKMARK |
+ PS3_PM_CONTROL_PPU_TH1_BOOKMARK);
+ if (val != lpm_priv->shadow.pm_control)
+ result = lv1_set_lpm_general_control(lpm_priv->lpm_id,
+ val,
+ PS3_WRITE_PM_MASK,
+ 0, 0, &dummy,
+ &dummy);
+ lpm_priv->shadow.pm_control = val;
+ break;
+ case pm_interval:
+ if (val != lpm_priv->shadow.pm_interval)
+ result = lv1_set_lpm_interval(lpm_priv->lpm_id, val,
+ PS3_WRITE_PM_MASK, &dummy);
+ lpm_priv->shadow.pm_interval = val;
+ break;
+ case pm_start_stop:
+ if (val != lpm_priv->shadow.pm_start_stop)
+ result = lv1_set_lpm_trigger_control(lpm_priv->lpm_id,
+ val,
+ PS3_WRITE_PM_MASK,
+ &dummy);
+ lpm_priv->shadow.pm_start_stop = val;
+ break;
+ case trace_address:
+ case ext_tr_timer:
+ case pm_status:
+ break;
+ default:
+ dev_dbg(sbd_core(), "%s:%u: unknown reg: %d\n", __func__,
+ __LINE__, reg);
+ BUG();
+ break;
+ }
+
+ if (result)
+ dev_err(sbd_core(), "%s:%u: lv1 set_control failed: "
+ "reg %u, %s\n", __func__, __LINE__, reg,
+ ps3_result(result));
+}
+EXPORT_SYMBOL_GPL(ps3_write_pm);
+
+/**
+ * ps3_get_ctr_size - Get the size of a physical counter.
+ *
+ * Returns either 16 or 32.
+ */
+
+u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr)
+{
+ u32 pm_ctrl;
+
+ if (phys_ctr >= NR_PHYS_CTRS) {
+ dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
+ __LINE__, phys_ctr);
+ return 0;
+ }
+
+ pm_ctrl = ps3_read_pm(cpu, pm_control);
+ return (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
+}
+EXPORT_SYMBOL_GPL(ps3_get_ctr_size);
+
+/**
+ * ps3_set_ctr_size - Set the size of a physical counter to 16 or 32 bits.
+ */
+
+void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
+{
+ u32 pm_ctrl;
+
+ if (phys_ctr >= NR_PHYS_CTRS) {
+ dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
+ __LINE__, phys_ctr);
+ return;
+ }
+
+ pm_ctrl = ps3_read_pm(cpu, pm_control);
+
+ switch (ctr_size) {
+ case 16:
+ pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
+ ps3_write_pm(cpu, pm_control, pm_ctrl);
+ break;
+
+ case 32:
+ pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
+ ps3_write_pm(cpu, pm_control, pm_ctrl);
+ break;
+ default:
+ BUG();
+ }
+}
+EXPORT_SYMBOL_GPL(ps3_set_ctr_size);
+
+static u64 pm_translate_signal_group_number_on_island2(u64 subgroup)
+{
+
+ if (subgroup == 2)
+ subgroup = 3;
+
+ if (subgroup <= 6)
+ return PM_ISLAND2_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+ else if (subgroup == 7)
+ return PM_ISLAND2_SIGNAL_GROUP_NUMBER1;
+ else
+ return PM_ISLAND2_SIGNAL_GROUP_NUMBER2;
+}
+
+static u64 pm_translate_signal_group_number_on_island3(u64 subgroup)
+{
+
+ switch (subgroup) {
+ case 2:
+ case 3:
+ case 4:
+ subgroup += 2;
+ break;
+ case 5:
+ subgroup = 8;
+ break;
+ default:
+ break;
+ }
+ return PM_ISLAND3_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static u64 pm_translate_signal_group_number_on_island4(u64 subgroup)
+{
+ return PM_ISLAND4_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static u64 pm_translate_signal_group_number_on_island5(u64 subgroup)
+{
+
+ switch (subgroup) {
+ case 3:
+ subgroup = 4;
+ break;
+ case 4:
+ subgroup = 6;
+ break;
+ default:
+ break;
+ }
+ return PM_ISLAND5_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static u64 pm_translate_signal_group_number_on_island6(u64 subgroup,
+ u64 subsubgroup)
+{
+ switch (subgroup) {
+ case 3:
+ case 4:
+ case 5:
+ subgroup += 1;
+ break;
+ default:
+ break;
+ }
+
+ switch (subsubgroup) {
+ case 4:
+ case 5:
+ case 6:
+ subsubgroup += 2;
+ break;
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ subsubgroup += 4;
+ break;
+ case 11:
+ case 12:
+ case 13:
+ subsubgroup += 5;
+ break;
+ default:
+ break;
+ }
+
+ if (subgroup <= 5)
+ return (PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER + subgroup);
+ else
+ return (PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER + subgroup
+ + subsubgroup - 1);
+}
+
+static u64 pm_translate_signal_group_number_on_island7(u64 subgroup)
+{
+ return PM_ISLAND7_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static u64 pm_translate_signal_group_number_on_island8(u64 subgroup)
+{
+ return PM_ISLAND8_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static u64 pm_signal_group_to_ps3_lv1_signal_group(u64 group)
+{
+ u64 island;
+ u64 subgroup;
+ u64 subsubgroup;
+
+ subgroup = 0;
+ subsubgroup = 0;
+ island = 0;
+ if (group < 1000) {
+ if (group < 100) {
+ if (20 <= group && group < 30) {
+ island = 2;
+ subgroup = group - 20;
+ } else if (30 <= group && group < 40) {
+ island = 3;
+ subgroup = group - 30;
+ } else if (40 <= group && group < 50) {
+ island = 4;
+ subgroup = group - 40;
+ } else if (50 <= group && group < 60) {
+ island = 5;
+ subgroup = group - 50;
+ } else if (60 <= group && group < 70) {
+ island = 6;
+ subgroup = group - 60;
+ } else if (70 <= group && group < 80) {
+ island = 7;
+ subgroup = group - 70;
+ } else if (80 <= group && group < 90) {
+ island = 8;
+ subgroup = group - 80;
+ }
+ } else if (200 <= group && group < 300) {
+ island = 2;
+ subgroup = group - 200;
+ } else if (600 <= group && group < 700) {
+ island = 6;
+ subgroup = 5;
+ subsubgroup = group - 650;
+ }
+ } else if (6000 <= group && group < 7000) {
+ island = 6;
+ subgroup = 5;
+ subsubgroup = group - 6500;
+ }
+
+ switch (island) {
+ case 2:
+ return pm_translate_signal_group_number_on_island2(subgroup);
+ case 3:
+ return pm_translate_signal_group_number_on_island3(subgroup);
+ case 4:
+ return pm_translate_signal_group_number_on_island4(subgroup);
+ case 5:
+ return pm_translate_signal_group_number_on_island5(subgroup);
+ case 6:
+ return pm_translate_signal_group_number_on_island6(subgroup,
+ subsubgroup);
+ case 7:
+ return pm_translate_signal_group_number_on_island7(subgroup);
+ case 8:
+ return pm_translate_signal_group_number_on_island8(subgroup);
+ default:
+ dev_dbg(sbd_core(), "%s:%u: island not found: %lu\n", __func__,
+ __LINE__, group);
+ BUG();
+ break;
+ }
+ return 0;
+}
+
+static u64 pm_bus_word_to_ps3_lv1_bus_word(u8 word)
+{
+
+ switch (word) {
+ case 1:
+ return 0xF000;
+ case 2:
+ return 0x0F00;
+ case 4:
+ return 0x00F0;
+ case 8:
+ default:
+ return 0x000F;
+ }
+}
+
+static int __ps3_set_signal(u64 lv1_signal_group, u64 bus_select,
+ u64 signal_select, u64 attr1, u64 attr2, u64 attr3)
+{
+ int ret;
+
+ ret = lv1_set_lpm_signal(lpm_priv->lpm_id, lv1_signal_group, bus_select,
+ signal_select, attr1, attr2, attr3);
+ if (ret)
+ dev_err(sbd_core(),
+ "%s:%u: error:%d 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx\n",
+ __func__, __LINE__, ret, lv1_signal_group, bus_select,
+ signal_select, attr1, attr2, attr3);
+
+ return ret;
+}
+
+int ps3_set_signal(u64 signal_group, u8 signal_bit, u16 sub_unit,
+ u8 bus_word)
+{
+ int ret;
+ u64 lv1_signal_group;
+ u64 bus_select;
+ u64 signal_select;
+ u64 attr1, attr2, attr3;
+
+ if (signal_group == 0)
+ return __ps3_set_signal(0, 0, 0, 0, 0, 0);
+
+ lv1_signal_group =
+ pm_signal_group_to_ps3_lv1_signal_group(signal_group);
+ bus_select = pm_bus_word_to_ps3_lv1_bus_word(bus_word);
+
+ switch (signal_group) {
+ case PM_SIG_GROUP_SPU_TRIGGER:
+ signal_select = 1;
+ signal_select = signal_select << (63 - signal_bit);
+ break;
+ case PM_SIG_GROUP_SPU_EVENT:
+ signal_select = 1;
+ signal_select = (signal_select << (63 - signal_bit)) | 0x3;
+ break;
+ default:
+ signal_select = 0;
+ break;
+ }
+
+ /*
+ * 0: physical object.
+ * 1: logical object.
+ * This parameter is only used for the PPE and SPE signals.
+ */
+ attr1 = 1;
+
+ /*
+ * This parameter is used to specify the target physical/logical
+ * PPE/SPE object.
+ */
+ if (PM_SIG_GROUP_SPU <= signal_group &&
+ signal_group < PM_SIG_GROUP_MFC_MAX)
+ attr2 = sub_unit;
+ else
+ attr2 = lpm_priv->pu_id;
+
+ /*
+ * This parameter is only used for setting the SPE signal.
+ */
+ attr3 = 0;
+
+ ret = __ps3_set_signal(lv1_signal_group, bus_select, signal_select,
+ attr1, attr2, attr3);
+ if (ret)
+ dev_err(sbd_core(), "%s:%u: __ps3_set_signal failed: %d\n",
+ __func__, __LINE__, ret);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(ps3_set_signal);
+
+u32 ps3_get_hw_thread_id(int cpu)
+{
+ return get_hard_smp_processor_id(cpu);
+}
+EXPORT_SYMBOL_GPL(ps3_get_hw_thread_id);
+
+/**
+ * ps3_enable_pm - Enable the entire performance monitoring unit.
+ *
+ * When we enable the LPM, all pending writes to counters get committed.
+ */
+
+void ps3_enable_pm(u32 cpu)
+{
+ int result;
+ u64 tmp;
+ int insert_bookmark = 0;
+
+ lpm_priv->tb_count = 0;
+
+ if (use_start_stop_bookmark) {
+ if (!(lpm_priv->shadow.pm_start_stop &
+ (PS3_PM_START_STOP_START_MASK
+ | PS3_PM_START_STOP_STOP_MASK))) {
+ result = lv1_set_lpm_trigger_control(lpm_priv->lpm_id,
+ (PS3_PM_START_STOP_PPU_TH0_BOOKMARK_START |
+ PS3_PM_START_STOP_PPU_TH1_BOOKMARK_START |
+ PS3_PM_START_STOP_PPU_TH0_BOOKMARK_STOP |
+ PS3_PM_START_STOP_PPU_TH1_BOOKMARK_STOP),
+ 0xFFFFFFFFFFFFFFFFULL, &tmp);
+
+ if (result)
+ dev_err(sbd_core(), "%s:%u: "
+ "lv1_set_lpm_trigger_control failed: "
+ "%s\n", __func__, __LINE__,
+ ps3_result(result));
+
+ insert_bookmark = !result;
+ }
+ }
+
+ result = lv1_start_lpm(lpm_priv->lpm_id);
+
+ if (result)
+ dev_err(sbd_core(), "%s:%u: lv1_start_lpm failed: %s\n",
+ __func__, __LINE__, ps3_result(result));
+
+ if (use_start_stop_bookmark && !result && insert_bookmark)
+ ps3_set_bookmark(get_tb() | PS3_PM_BOOKMARK_START);
+}
+EXPORT_SYMBOL_GPL(ps3_enable_pm);
+
+/**
+ * ps3_disable_pm - Disable the entire performance monitoring unit.
+ */
+
+void ps3_disable_pm(u32 cpu)
+{
+ int result;
+ u64 tmp;
+
+ ps3_set_bookmark(get_tb() | PS3_PM_BOOKMARK_STOP);
+
+ result = lv1_stop_lpm(lpm_priv->lpm_id, &tmp);
+
+ if (result) {
+ if(result != LV1_WRONG_STATE)
+ dev_err(sbd_core(), "%s:%u: lv1_stop_lpm failed: %s\n",
+ __func__, __LINE__, ps3_result(result));
+ return;
+ }
+
+ lpm_priv->tb_count = tmp;
+
+ dev_dbg(sbd_core(), "%s:%u: tb_count %lu (%lxh)\n", __func__, __LINE__,
+ lpm_priv->tb_count, lpm_priv->tb_count);
+}
+EXPORT_SYMBOL_GPL(ps3_disable_pm);
+
+/**
+ * ps3_lpm_copy_tb - Copy data from the trace buffer to a kernel buffer.
+ * @offset: Offset in bytes from the start of the trace buffer.
+ * @buf: Copy destination.
+ * @count: Maximum count of bytes to copy.
+ * @bytes_copied: Pointer to a variable that will recieve the number of
+ * bytes copied to @buf.
+ *
+ * On error @buf will contain any successfully copied trace buffer data
+ * and bytes_copied will be set to the number of bytes successfully copied.
+ */
+
+int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count,
+ unsigned long *bytes_copied)
+{
+ int result;
+
+ *bytes_copied = 0;
+
+ if (!lpm_priv->tb_cache)
+ return -EPERM;
+
+ if (offset >= lpm_priv->tb_count)
+ return 0;
+
+ count = min(count, lpm_priv->tb_count - offset);
+
+ while (*bytes_copied < count) {
+ const unsigned long request = count - *bytes_copied;
+ u64 tmp;
+
+ result = lv1_copy_lpm_trace_buffer(lpm_priv->lpm_id, offset,
+ request, &tmp);
+ if (result) {
+ dev_dbg(sbd_core(), "%s:%u: 0x%lx bytes at 0x%lx\n",
+ __func__, __LINE__, request, offset);
+
+ dev_err(sbd_core(), "%s:%u: lv1_copy_lpm_trace_buffer "
+ "failed: %s\n", __func__, __LINE__,
+ ps3_result(result));
+ return result == LV1_WRONG_STATE ? -EBUSY : -EINVAL;
+ }
+
+ memcpy(buf, lpm_priv->tb_cache, tmp);
+ buf += tmp;
+ *bytes_copied += tmp;
+ offset += tmp;
+ }
+ dev_dbg(sbd_core(), "%s:%u: copied %lxh bytes\n", __func__, __LINE__,
+ *bytes_copied);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_lpm_copy_tb);
+
+/**
+ * ps3_lpm_copy_tb_to_user - Copy data from the trace buffer to a user buffer.
+ * @offset: Offset in bytes from the start of the trace buffer.
+ * @buf: A __user copy destination.
+ * @count: Maximum count of bytes to copy.
+ * @bytes_copied: Pointer to a variable that will recieve the number of
+ * bytes copied to @buf.
+ *
+ * On error @buf will contain any successfully copied trace buffer data
+ * and bytes_copied will be set to the number of bytes successfully copied.
+ */
+
+int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf,
+ unsigned long count, unsigned long *bytes_copied)
+{
+ int result;
+
+ *bytes_copied = 0;
+
+ if (!lpm_priv->tb_cache)
+ return -EPERM;
+
+ if (offset >= lpm_priv->tb_count)
+ return 0;
+
+ count = min(count, lpm_priv->tb_count - offset);
+
+ while (*bytes_copied < count) {
+ const unsigned long request = count - *bytes_copied;
+ u64 tmp;
+
+ result = lv1_copy_lpm_trace_buffer(lpm_priv->lpm_id, offset,
+ request, &tmp);
+ if (result) {
+ dev_dbg(sbd_core(), "%s:%u: 0x%lx bytes at 0x%lx\n",
+ __func__, __LINE__, request, offset);
+ dev_err(sbd_core(), "%s:%u: lv1_copy_lpm_trace_buffer "
+ "failed: %s\n", __func__, __LINE__,
+ ps3_result(result));
+ return result == LV1_WRONG_STATE ? -EBUSY : -EINVAL;
+ }
+
+ result = copy_to_user(buf, lpm_priv->tb_cache, tmp);
+
+ if (result) {
+ dev_dbg(sbd_core(), "%s:%u: 0x%lx bytes at 0x%p\n",
+ __func__, __LINE__, tmp, buf);
+ dev_err(sbd_core(), "%s:%u: copy_to_user failed: %d\n",
+ __func__, __LINE__, result);
+ return -EFAULT;
+ }
+
+ buf += tmp;
+ *bytes_copied += tmp;
+ offset += tmp;
+ }
+ dev_dbg(sbd_core(), "%s:%u: copied %lxh bytes\n", __func__, __LINE__,
+ *bytes_copied);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_lpm_copy_tb_to_user);
+
+/**
+ * ps3_get_and_clear_pm_interrupts -
+ *
+ * Clearing interrupts for the entire performance monitoring unit.
+ * Reading pm_status clears the interrupt bits.
+ */
+
+u32 ps3_get_and_clear_pm_interrupts(u32 cpu)
+{
+ return ps3_read_pm(cpu, pm_status);
+}
+EXPORT_SYMBOL_GPL(ps3_get_and_clear_pm_interrupts);
+
+/**
+ * ps3_enable_pm_interrupts -
+ *
+ * Enabling interrupts for the entire performance monitoring unit.
+ * Enables the interrupt bits in the pm_status register.
+ */
+
+void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
+{
+ if (mask)
+ ps3_write_pm(cpu, pm_status, mask);
+}
+EXPORT_SYMBOL_GPL(ps3_enable_pm_interrupts);
+
+/**
+ * ps3_enable_pm_interrupts -
+ *
+ * Disabling interrupts for the entire performance monitoring unit.
+ */
+
+void ps3_disable_pm_interrupts(u32 cpu)
+{
+ ps3_get_and_clear_pm_interrupts(cpu);
+ ps3_write_pm(cpu, pm_status, 0);
+}
+EXPORT_SYMBOL_GPL(ps3_disable_pm_interrupts);
+
+/**
+ * ps3_lpm_open - Open the logical performance monitor device.
+ * @tb_type: Specifies the type of trace buffer lv1 sould use for this lpm
+ * instance, specified by one of enum ps3_lpm_tb_type.
+ * @tb_cache: Optional user supplied buffer to use as the trace buffer cache.
+ * If NULL, the driver will allocate and manage an internal buffer.
+ * Unused when when @tb_type is PS3_LPM_TB_TYPE_NONE.
+ * @tb_cache_size: The size in bytes of the user supplied @tb_cache buffer.
+ * Unused when @tb_cache is NULL or @tb_type is PS3_LPM_TB_TYPE_NONE.
+ */
+
+int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache,
+ u64 tb_cache_size)
+{
+ int result;
+ u64 tb_size;
+
+ BUG_ON(!lpm_priv);
+ BUG_ON(tb_type != PS3_LPM_TB_TYPE_NONE
+ && tb_type != PS3_LPM_TB_TYPE_INTERNAL);
+
+ if (tb_type == PS3_LPM_TB_TYPE_NONE && tb_cache)
+ dev_dbg(sbd_core(), "%s:%u: bad in vals\n", __func__, __LINE__);
+
+ if (!atomic_add_unless(&lpm_priv->open, 1, 1)) {
+ dev_dbg(sbd_core(), "%s:%u: busy\n", __func__, __LINE__);
+ return -EBUSY;
+ }
+
+ /* Note tb_cache needs 128 byte alignment. */
+
+ if (tb_type == PS3_LPM_TB_TYPE_NONE) {
+ lpm_priv->tb_cache_size = 0;
+ lpm_priv->tb_cache_internal = NULL;
+ lpm_priv->tb_cache = NULL;
+ } else if (tb_cache) {
+ if (tb_cache != (void *)_ALIGN_UP((unsigned long)tb_cache, 128)
+ || tb_cache_size != _ALIGN_UP(tb_cache_size, 128)) {
+ dev_err(sbd_core(), "%s:%u: unaligned tb_cache\n",
+ __func__, __LINE__);
+ result = -EINVAL;
+ goto fail_align;
+ }
+ lpm_priv->tb_cache_size = tb_cache_size;
+ lpm_priv->tb_cache_internal = NULL;
+ lpm_priv->tb_cache = tb_cache;
+ } else {
+ lpm_priv->tb_cache_size = PS3_LPM_DEFAULT_TB_CACHE_SIZE;
+ lpm_priv->tb_cache_internal = kzalloc(
+ lpm_priv->tb_cache_size + 127, GFP_KERNEL);
+ if (!lpm_priv->tb_cache_internal) {
+ dev_err(sbd_core(), "%s:%u: alloc internal tb_cache "
+ "failed\n", __func__, __LINE__);
+ result = -ENOMEM;
+ goto fail_malloc;
+ }
+ lpm_priv->tb_cache = (void *)_ALIGN_UP(
+ (unsigned long)lpm_priv->tb_cache_internal, 128);
+ }
+
+ result = lv1_construct_lpm(lpm_priv->node_id, tb_type, 0, 0,
+ ps3_mm_phys_to_lpar(__pa(lpm_priv->tb_cache)),
+ lpm_priv->tb_cache_size, &lpm_priv->lpm_id,
+ &lpm_priv->outlet_id, &tb_size);
+
+ if (result) {
+ dev_err(sbd_core(), "%s:%u: lv1_construct_lpm failed: %s\n",
+ __func__, __LINE__, ps3_result(result));
+ result = -EINVAL;
+ goto fail_construct;
+ }
+
+ lpm_priv->shadow.pm_control = PS3_LPM_SHADOW_REG_INIT;
+ lpm_priv->shadow.pm_start_stop = PS3_LPM_SHADOW_REG_INIT;
+ lpm_priv->shadow.pm_interval = PS3_LPM_SHADOW_REG_INIT;
+ lpm_priv->shadow.group_control = PS3_LPM_SHADOW_REG_INIT;
+ lpm_priv->shadow.debug_bus_control = PS3_LPM_SHADOW_REG_INIT;
+
+ dev_dbg(sbd_core(), "%s:%u: lpm_id 0x%lx, outlet_id 0x%lx, "
+ "tb_size 0x%lx\n", __func__, __LINE__, lpm_priv->lpm_id,
+ lpm_priv->outlet_id, tb_size);
+
+ return 0;
+
+fail_construct:
+ kfree(lpm_priv->tb_cache_internal);
+ lpm_priv->tb_cache_internal = NULL;
+fail_malloc:
+fail_align:
+ atomic_dec(&lpm_priv->open);
+ return result;
+}
+EXPORT_SYMBOL_GPL(ps3_lpm_open);
+
+/**
+ * ps3_lpm_close - Close the lpm device.
+ *
+ */
+
+int ps3_lpm_close(void)
+{
+ dev_dbg(sbd_core(), "%s:%u\n", __func__, __LINE__);
+
+ lv1_destruct_lpm(lpm_priv->lpm_id);
+ lpm_priv->lpm_id = 0;
+
+ kfree(lpm_priv->tb_cache_internal);
+ lpm_priv->tb_cache_internal = NULL;
+
+ atomic_dec(&lpm_priv->open);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_lpm_close);
+
+static int __devinit ps3_lpm_probe(struct ps3_system_bus_device *dev)
+{
+ dev_dbg(&dev->core, " -> %s:%u\n", __func__, __LINE__);
+
+ if (lpm_priv) {
+ dev_info(&dev->core, "%s:%u: called twice\n",
+ __func__, __LINE__);
+ return -EBUSY;
+ }
+
+ lpm_priv = kzalloc(sizeof(*lpm_priv), GFP_KERNEL);
+
+ if (!lpm_priv)
+ return -ENOMEM;
+
+ lpm_priv->sbd = dev;
+ lpm_priv->node_id = dev->lpm.node_id;
+ lpm_priv->pu_id = dev->lpm.pu_id;
+ lpm_priv->rights = dev->lpm.rights;
+
+ dev_info(&dev->core, " <- %s:%u:\n", __func__, __LINE__);
+
+ return 0;
+}
+
+static int ps3_lpm_remove(struct ps3_system_bus_device *dev)
+{
+ dev_dbg(&dev->core, " -> %s:%u:\n", __func__, __LINE__);
+
+ ps3_lpm_close();
+
+ kfree(lpm_priv);
+ lpm_priv = NULL;
+
+ dev_info(&dev->core, " <- %s:%u:\n", __func__, __LINE__);
+ return 0;
+}
+
+static struct ps3_system_bus_driver ps3_lpm_driver = {
+ .match_id = PS3_MATCH_ID_LPM,
+ .core.name = "ps3-lpm",
+ .core.owner = THIS_MODULE,
+ .probe = ps3_lpm_probe,
+ .remove = ps3_lpm_remove,
+ .shutdown = ps3_lpm_remove,
+};
+
+static int __init ps3_lpm_init(void)
+{
+ pr_debug("%s:%d:\n", __func__, __LINE__);
+ return ps3_system_bus_driver_register(&ps3_lpm_driver);
+}
+
+static void __exit ps3_lpm_exit(void)
+{
+ pr_debug("%s:%d:\n", __func__, __LINE__);
+ ps3_system_bus_driver_unregister(&ps3_lpm_driver);
+}
+
+module_init(ps3_lpm_init);
+module_exit(ps3_lpm_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PS3 Logical Performance Monitor Driver");
+MODULE_AUTHOR("Sony Corporation");
+MODULE_ALIAS(PS3_MODULE_ALIAS_LPM);
--- a/include/asm-powerpc/ps3.h
+++ b/include/asm-powerpc/ps3.h
@@ -24,6 +24,7 @@
#include <linux/init.h>
#include <linux/types.h>
#include <linux/device.h>
+#include "cell-pmu.h"
union ps3_firmware_version {
u64 raw;
@@ -446,5 +447,66 @@ struct ps3_prealloc {
extern struct ps3_prealloc ps3fb_videomemory;
extern struct ps3_prealloc ps3flash_bounce_buffer;
+/* logical performance monitor */
+
+/**
+ * enum ps3_lpm_rights - Rigths granted by the system policy module.
+ *
+ * @PS3_LPM_RIGHTS_USE_LPM: The right to use the lpm.
+ * @PS3_LPM_RIGHTS_USE_TB: The right to use the internal trace buffer.
+ */
+
+enum ps3_lpm_rights {
+ PS3_LPM_RIGHTS_USE_LPM = 0x001,
+ PS3_LPM_RIGHTS_USE_TB = 0x100,
+};
+
+/**
+ * enum ps3_lpm_tb_type - Type of trace buffer lv1 should use.
+ *
+ * @PS3_LPM_TB_TYPE_NONE: Do not use a trace buffer.
+ * @PS3_LPM_RIGHTS_USE_TB: Use the lv1 internal trace buffer. Must have
+ * rights @PS3_LPM_RIGHTS_USE_TB.
+ */
+
+enum ps3_lpm_tb_type {
+ PS3_LPM_TB_TYPE_NONE = 0,
+ PS3_LPM_TB_TYPE_INTERNAL = 1,
+};
+
+int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache,
+ u64 tb_cache_size);
+int ps3_lpm_close(void);
+int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count,
+ unsigned long *bytes_copied);
+int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf,
+ unsigned long count, unsigned long *bytes_copied);
+void ps3_set_bookmark(u64 bookmark);
+void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id);
+int ps3_set_signal(u64 rtas_signal_group, u8 signal_bit, u16 sub_unit,
+ u8 bus_word);
+
+u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr);
+void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
+u32 ps3_read_ctr(u32 cpu, u32 ctr);
+void ps3_write_ctr(u32 cpu, u32 ctr, u32 val);
+
+u32 ps3_read_pm07_control(u32 cpu, u32 ctr);
+void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val);
+u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg);
+void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
+
+u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr);
+void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
+
+void ps3_enable_pm(u32 cpu);
+void ps3_disable_pm(u32 cpu);
+void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
+void ps3_disable_pm_interrupts(u32 cpu);
+
+u32 ps3_get_and_clear_pm_interrupts(u32 cpu);
+void ps3_sync_irq(int node);
+u32 ps3_get_hw_thread_id(int cpu);
+u64 ps3_get_spe_id(void *arg);
#endif
^ permalink raw reply
* Re: [PATCH 2/3] sbc834x: Add device tree source for Wind River SBC834x board.
From: David Gibson @ 2008-01-10 2:06 UTC (permalink / raw)
To: Paul Gortmaker; +Cc: linuxppc-dev
In-Reply-To: <b9cda8aa586eba852f0763db2347d545a5b31be6.1199850992.git.paul.gortmaker@windriver.com>
On Wed, Jan 09, 2008 at 12:49:31AM -0500, Paul Gortmaker wrote:
> This adds the device tree source for the Wind River SBC834x board.
> It is based on the MPC834x_MDS DTS, with the biggest difference being
> the lack of BCSR and the PCI2 that the MDS gets via the PIB. That,
> and this file is also dts-v1 format.
>
> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
> ---
> arch/powerpc/boot/dts/sbc8349.dts | 247 +++++++++++++++++++++++++++++++++++++
> 1 files changed, 247 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
[snip]
> + wdt@200 {
> + device_type = "watchdog";
> + compatible = "mpc83xx_wdt";
Grah! Hasn't someone fixed this so that the driver doesn't need the
crap device_type?
[snip]
> + spi@7000 {
> + device_type = "spi";
> + compatible = "fsl_spi";
And again here.
[snip]
> + usb@22000 {
> + device_type = "usb";
> + compatible = "fsl-usb2-mph";
And here.
[snip
> + /* May need to remove if on a part without crypto engine */
> + crypto@30000 {
> + device_type = "crypto";
> + model = "SEC2";
> + compatible = "talitos";
I'm almost certain this one was fixed, hasn't it been merged yet?
[snip]
> + ipic: pic@700 {
By generic names best practice this should be
"interrupt-controller@700", although that's probably not your error.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 2/3] [libata] pata_of_platform: OF-Platform PATA device driver
From: Stephen Rothwell @ 2008-01-10 2:17 UTC (permalink / raw)
To: Olof Johansson; +Cc: Paul Mundt, linuxppc-dev, Jeff Garzik, linux-ide
In-Reply-To: <20080110003634.GA19966@lixom.net>
[-- Attachment #1: Type: text/plain, Size: 758 bytes --]
On Wed, 9 Jan 2008 18:36:34 -0600 Olof Johansson <olof@lixom.net> wrote:
>
> On Thu, Jan 10, 2008 at 10:40:48AM +1100, Stephen Rothwell wrote:
> > Hi Anton,
> >
> > Juts one small trivial comment (could be fixed later).
> >
> > On Wed, 9 Jan 2008 22:10:41 +0300 Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> > >
> > > +static struct of_device_id pata_of_platform_match[] = {
> >
> > This could be declared const.
>
> Good point, but let's not hold up merge based on this. Need something
> for janitors to do too, and it's good enough to merge as-is. :)
Absolutely. To me that is what "(could be fixed later)" means. :-)
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH 4/7] Device tree for MPC5121 ADS
From: David Gibson @ 2008-01-10 2:18 UTC (permalink / raw)
To: John Rigby; +Cc: linuxppc-dev
In-Reply-To: <1199808093-15929-5-git-send-email-jrigby@freescale.com>
On Tue, Jan 08, 2008 at 09:01:30AM -0700, John Rigby wrote:
> Bare minimum tree containing only
> what is currently supported.
[snip]
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + PowerPC,5121@0 {
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-line-size = <20>; // 32 bytes
> + i-cache-line-size = <20>; // 32 bytes
> + d-cache-size = <8000>; // L1, 32K
> + i-cache-size = <8000>; // L1, 32K
> + ref-frequency = <3ef1480>; // 66MHz ref clock
> + timebase-frequency = <2f34f60>; // 49.5MHz (396MHz/8) makes time tick correctly
> + bus-frequency = <bcd3d80>; // 198MHz csb bus
> + clock-frequency = <179a7b00>; // 396MHz ppc core ??
> + 32-bit;
The "32-bit" property was only ever added by mistake. Drop it.
[snip]
> + cpld@82000000 {
> + device_type = "board-control";
No device_type here. But you should have a "compatible" property.
[snip]
> + soc5121@80000000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <2>;
> + device_type = "soc";
> + ranges = <0 80000000 400000>;
> + reg = <80000000 400000>;
> + ref-frequency = <3ef1480>; // 66MHz ref
What the hell is ref-frequency? Unfortunately, you have to work with
existing broken practice for SoC nodes here, but the principle clock
frequency for any device should always be encoded in a property called
"clock-frequency".
[snip]
> + ipic: pic@c00 {
Should be "interrupt-controller@c00"
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + reg = <c00 100>;
> + built-in;
> + device_type = "ipic";
Drop this device_type. Should have a compatible value instead.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: add phy-handle property for fec_mpc52xx
From: Paul Mackerras @ 2008-01-10 2:20 UTC (permalink / raw)
To: Olaf Hering; +Cc: linuxppc-dev
In-Reply-To: <20080109140608.GA15673@aepfle.de>
Olaf Hering writes:
> --- a/arch/powerpc/kernel/prom_init.c
> +++ b/arch/powerpc/kernel/prom_init.c
> @@ -1487,6 +1487,34 @@ static void __init prom_find_mmu(void)
> else if (strncmp(version, "FirmWorks,3.", 12) == 0) {
> of_workarounds = OF_WA_CLAIM | OF_WA_LONGTRAIL;
> call_prom("interpret", 1, 1, "dev /memory 0 to allow-reclaim");
> +#ifdef CONFIG_PPC_MPC52xx
> + } else if (strcmp(version, "EFIKA5K2") == 0) {
Why have you added this stuff in prom_find_mmu rather than putting it
in fixup_device_tree_efika()?
Paul.
^ permalink raw reply
* Re: add phy-handle property for fec_mpc52xx
From: Paul Mackerras @ 2008-01-10 2:21 UTC (permalink / raw)
To: David Woodhouse; +Cc: Olaf Hering, linuxppc-dev
In-Reply-To: <1199893757.2978.73.camel@pmac.infradead.org>
David Woodhouse writes:
> It would be much better if the kernel would 'just work'. The ideal way
> of achieving that is for the firmware to be fixed -- but that's been
> promised for a long time now, and we just don't believe you any more. So
> working round it in the kernel seems to be the next best option.
Does the efika use a boot wrapper? If so then putting the fixup in
the boot wrapper might be better.
Paul.
^ permalink raw reply
* Re: [PATCH 1/8] pseries: phyp dump: Docmentation
From: Linas Vepstas @ 2008-01-10 2:33 UTC (permalink / raw)
To: Nathan Lynch; +Cc: mahuja, linuxppc-dev, lkessler, strosake
In-Reply-To: <20080109184437.GU14201@localdomain>
On 09/01/2008, Nathan Lynch <ntl@pobox.com> wrote:
> Hi Linas,
>
> Linas Vepstas wrote:
> >
> > As a side effect, the system is in
> > production *while* the dump is being taken;
>
> A dubious feature IMO.
Hmm. Take it up with Ken Rozendal, this is supposed to be
one of the two main selling points of this thing.
> Seems that the design potentially trades
> reliability of first failure data capture for availability.
> E.g. system crashes, reboots, resumes processing while copying dump,
> crashes again before dump procedure is complete. How is that handled,
> if at all?
Its handled by the hypervisor. phyp maintains the copy of the
RMO of first crash, until such time that the OS declares the
dump of the RMO to be complete. So you'll always have
the RMO of the first crash.
For the rest of RAM, it will come in two parts: some portion
will have been dumped already. The rest has not yet been dumped,
and it will still be there, preserved across the second crash.
So you get both RMO and all of RAM from the first crash.
> > with kdump,
> > you can't go into production until after the dump is finished,
> > and the system has been rebooted a second time. On
> > systems with terabytes of RAM, the time difference can be
> > hours.
>
> The difference in time it takes to resume the normal workload may be
> significant, yes. But the time it takes to get a usable dump image
> would seem to be the basically the same.
Yes.
> Since you bring up large systems... a system with terabytes of RAM is
> practically guaranteed to be a NUMA configuration with dozens of cpus.
> When processing a dump on such a system, I wonder how well we fare:
> can we successfully boot with (say) 128 cpus and 256MB of usable
> memory? Do we have to hot-online nodes as system memory is freed up
> (and does that even work)? We need to be able to restore the system
> to its optimal topology when the dump is finished; if the best we can
> do is a degraded configuration, the workload will suffer and the
> system admin is likely to just reboot the machine again so the kernel
> will have the right NUMA topology.
Heh. That's the elbow-grease of this thing. The easy part is to get
the core function working. The hard part is to test these various configs,
and when they don't work, figure out what went wrong. That will take
perseverence and brains.
--linas
^ permalink raw reply
* Re: [PATCH 2/5] Warp Base Platform - dts
From: David Gibson @ 2008-01-10 2:47 UTC (permalink / raw)
To: Sean MacLennan; +Cc: linuxppc-dev
In-Reply-To: <47852CB3.3000208@pikatech.com>
On Wed, Jan 09, 2008 at 03:21:07PM -0500, Sean MacLennan wrote:
> Signed-off-by: Sean MacLennan <smaclennan@pikatech.com>
> ---
> --- /dev/null 2005-11-20 22:22:37.000000000 -0500
> +++ arch/powerpc/boot/dts/warp.dts 2008-01-08 12:04:10.000000000 -0500
[snip]
> + plb {
> + compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges;
> + clock-frequency = <0>; /* Filled in by zImage */
> +
> + SDRAM0: sdram {
> + compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
> + dcr-reg = <010 2>;
> + };
> +
> + DMA0: dma {
> + compatible = "ibm,dma-440ep", "ibm,dma-440gp";
> + dcr-reg = <100 027>;
> + };
> +
> + FPGA0: fpga {
Surely this must be off the EBC, not directly of the PLB...?
> + compatible = "pika,fpga";
> + reg = <0 80000000 2200>;
> + interrupts = <18 8>;
> + interrupt-parent = <&UIC0>;
> + };
[snip]
> + IIC0: i2c@ef600700 {
> + device_type = "i2c";
Drop this device_type.
> + compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
> + reg = <ef600700 14>;
> + interrupt-parent = <&UIC0>;
> + interrupts = <2 4>;
> + };
> +
> + ZMII0: emac-zmii@ef600d00 {
> + device_type = "zmii-interface";
And this one.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 1/8] pseries: phyp dump: Docmentation
From: Linas Vepstas @ 2008-01-10 2:47 UTC (permalink / raw)
To: michael; +Cc: mahuja, linuxppc-dev, lkessler, Nathan Lynch, strosake
In-Reply-To: <1199919545.7880.11.camel@concordia>
On 09/01/2008, Michael Ellerman <michael@ellerman.id.au> wrote:
>
> > > Only if you can get at rtas, but you can't get at rtas at that point.
>
> AFAICT you don't need to get at RTAS, you just need to look at the
> device tree to see if the property is present, and that is trivial.
>
> You probably just need to add a check in early_init_dt_scan_rtas() which
> sets a flag for the PHYP dump stuff, or add your own scan routine if you
> need.
I no longer remember the details. I do remember spending a lot of time
trying to figure out how to do this. I know I didn't want to write my own scan
routine; maybe that's what stopped me. As it happens, we also did most
of the development on a broken phyp which simply did not even have
this property, no matter what, and so that may have brain-damaged me.
I went for the "most elegant" solution, where "most elegant" is defined
as "fewest lines of code", "least effort", etc.
Manish may need some hands-on help to extract this token during
early boot. Hopefully, he'll let us know.
--linas
^ permalink raw reply
* Re: [PATCH 3/5] Warp Base Platform
From: David Gibson @ 2008-01-10 2:49 UTC (permalink / raw)
To: Sean MacLennan; +Cc: linuxppc-dev
In-Reply-To: <47852D16.2070906@pikatech.com>
On Wed, Jan 09, 2008 at 03:22:46PM -0500, Sean MacLennan wrote:
> Basically the powerpc/boot directory files.
[snip]
> --- /dev/null 2005-11-20 22:22:37.000000000 -0500
> +++ arch/powerpc/boot/cuboot-warp.c 2008-01-08 12:09:39.000000000 -0500
> @@ -0,0 +1,25 @@
> +/*
> + * Copyright (c) 2008 PIKA Technologies
> + * Sean MacLennan <smaclennan@pikatech.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + */
> +
> +#include "ops.h"
> +#include "44x.h"
> +#include "cuboot.h"
> +
> +#define TARGET_44x
> +#include "ppcboot.h"
> +
> +static bd_t bd;
> +
> +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
> + unsigned long r6, unsigned long r7)
> +{
> + CUBOOT_INIT();
> +
> + warp_init(&bd.bi_enetaddr, &bd.bi_enet1addr);
> +}
> --- /dev/null 2005-11-20 22:22:37.000000000 -0500
> +++ arch/powerpc/boot/warp.c 2008-01-08 12:09:54.000000000 -0500
Fold all this into cuboot-warp.c, unless you actually anticipate
adding another wrapper for another firmware which will also use the
functions in warp.c.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 4/7] sbc8560: Add device tree source for Wind River SBC8560 board
From: David Gibson @ 2008-01-10 2:56 UTC (permalink / raw)
To: Paul Gortmaker; +Cc: linuxppc-dev
In-Reply-To: <d10d083bafb978936975111f09669120201072ec.1199715362.git.paul.gortmaker@windriver.com>
On Mon, Jan 07, 2008 at 09:25:29AM -0500, Paul Gortmaker wrote:
> This adds the device tree source for the Wind River SBC8560 board. The
> biggest difference between this and the MPC8560ADS reference platform
> dts is the use of an external 16550 compatible UART instead of the CPM2.
>
> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
> ---
> arch/powerpc/boot/dts/sbc8560.dts | 285 +++++++++++++++++++++++++++++++++++++
[snip]
> + epld@fc000000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "localbus";
This compatible doesn't look specific enough. It should at least have
a vendor prefix.
> + ranges = <0 fc000000 00c00000>;
Typically, we've been doing these external bust controller type
gadgets with address-cells = <2>, the first cell explicitly encoding
the chipselect. This gets us closer to the ideal of the device tree
encoding only hardware information, not how the bridge controller is
configured (although "ranges" will still have to contain configuration
dependent information).
> +
> + serial0: serial@700000 {
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <700000 100>;
> + clock-frequency = <1C2000>;
> + interrupts = <9 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + serial1: serial@800000 {
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <800000 100>;
> + clock-frequency = <1C2000>;
> + interrupts = <a 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + rtc@900000 {
> + compatible = "m48t59";
> + reg = <900000 2000>;
> + };
> + };
> +};
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 1/8] pseries: phyp dump: Docmentation
From: Olof Johansson @ 2008-01-10 3:17 UTC (permalink / raw)
To: Linas Vepstas; +Cc: mahuja, linuxppc-dev, lkessler, Nathan Lynch, strosake
In-Reply-To: <3ae3aa420801091833i6cf32616o2a060579be1f3191@mail.gmail.com>
On Wed, Jan 09, 2008 at 08:33:53PM -0600, Linas Vepstas wrote:
> Heh. That's the elbow-grease of this thing. The easy part is to get
> the core function working. The hard part is to test these various configs,
> and when they don't work, figure out what went wrong. That will take
> perseverence and brains.
This just sounds like a whole lot of extra work to get a feature that
already exists. Also, features like these seem to just get tested when the
next enterprise distro is released, so they're broken for long stretches
of time in mainline.
There's a bunch of problems like the NUMA ones, which would by far be
easiest to solve by just doing another reboot or kexec, wouldn't they?
-Olof
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox