* Re: [PATCH 1/1] [PPC] 8xx swap bug-fix
From: Jochen Friedrich @ 2008-02-02 11:22 UTC (permalink / raw)
To: Yuri Tikhonov; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <200802021047.32055.yur@emcraft.com>
Hi Yuri,
> Here is the patch which makes Linux-2.6 swap routines operate correctly on
> the ppc-8xx-based machines.
is there any 8xx board left which isn't ported to ARCH=powerpc?
Thanks,
Jochen
^ permalink raw reply
* Re: [PATCH 1/1] [PPC] 8xx swap bug-fix
From: Yuri Tikhonov @ 2008-02-02 11:30 UTC (permalink / raw)
To: Jochen Friedrich; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <47A45269.7080403@scram.de>
Hi Jochen,
The board for which this fix was developed is one of these (ivms8). Here are
some other: rpxlite, TQM860L, rpxcllf, bseip, FADS, and etc...
Just do grep -r "CONFIG_8xx=y" arch/ppc/configs/ and grep -r "CONFIG_8xx=y"
arch/powerpc/configs/ :)
Regards, Yuri
On Saturday 02 February 2008 14:22, you wrote:
...
> > Here is the patch which makes Linux-2.6 swap routines operate correctly
on
> > the ppc-8xx-based machines.
>
> is there any 8xx board left which isn't ported to ARCH=powerpc?
>
> Thanks,
> Jochen
>
--
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com
^ permalink raw reply
* Re: PATCH[1/1] 8xx: Add clock-frequency to Adder875 and mpc885ads board ports
From: Bryan O'Donoghue @ 2008-02-02 11:36 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <47A38888.1010901@freescale.com>
On Fri, 2008-02-01 at 15:00 -0600, Scott Wood wrote:
> Bryan O'Donoghue wrote:
> > Redo the addition of the clock-frequency parameter to the Adder875 .dts
> > so that the values are decimal rather then hex.
> >
> >
> > Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie>
> > ---
> >
> > diff --git a/arch/powerpc/boot/dts/adder875-redboot.dts
> > b/arch/powerpc/boot/dts/adder875-redboot.dts
> > index 7c25d96..c508f3c 100644
> > --- a/arch/powerpc/boot/dts/adder875-redboot.dts
> > +++ b/arch/powerpc/boot/dts/adder875-redboot.dts
> > @@ -149,6 +149,7 @@
> > compatible = "fsl,mpc875-brg",
> > "fsl,cpm1-brg",
> > "fsl,cpm-brg";
> > + clock-frequency = <50000000>;
> > reg = <0x9f0 0x10>;
> > };
Actually I was wondering myself why the file was using whitespace
instead of tabs - no doubt something to do with copying between
evolution + gedit.
Will fix this up with vim
^ permalink raw reply
* Re: Kernel oops while duming user core.
From: Clemens Koller @ 2008-02-02 12:05 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, Nathan Lynch
In-Reply-To: <20080201173834.GD671@ld0162-tx32.am.freescale.net>
Scott Wood schrieb:
> On Thu, Jan 31, 2008 at 10:15:27AM -0600, Nathan Lynch wrote:
>> Rune Torgersen wrote:
>>> I get the following kernel core while a user program I have is dumping
>>> core.
>>> Any DIeas at what to look for? (this is runnign 2.6.24, arch/powerpc on
>>> a 8280)
>>> When runnign the program on 2.6.18 arch/ppc, the program gets a sig 11
>>> and dumps core.
>>> On 2.6.24, I ghet the kernel oops, and then the program hangs sround
>>> forever and is unkillable.
>> Hmm, this is the second report of 2.6.24 crashing in
>> __flush_dcache_icache during a core dump; see:
>> http://ozlabs.org/pipermail/linuxppc-dev/2007-December/048662.html
>>
>> Is this easily recreatable?
>
> Yes, this program does it reliably:
>
> #include <pthread.h>
> #include <stdio.h>
> #include <unistd.h>
> #include <signal.h>
>
> void *threadfn(void *arg)
> {
> fprintf(stderr, "threadfn\n");
> fflush(stderr);
> sleep(1);
> *(char *)0=0;
> return NULL;
> }
>
> int main(void)
> {
> pthread_t thread[4];
> int i;
>
> for (i = 0; i < 4; i++)
> pthread_create(&thread[0], NULL, threadfn, NULL);
>
> for (;;);
> }
Ack!
This is a MPC8540ADS arch/powerpc compatible environment here:
Feb 2 12:59:17 fox_1 kernel: Unable to handle kernel paging request for data at address 0x4802f000
Feb 2 12:59:17 fox_1 kernel: Faulting instruction address: 0xc000d5b8
Feb 2 12:59:17 fox_1 kernel: Oops: Kernel access of bad area, sig: 11 [#1]
Feb 2 12:59:17 fox_1 kernel: MPC85xx ADS
Feb 2 12:59:17 fox_1 kernel: Modules linked in:
Feb 2 12:59:17 fox_1 kernel: NIP: c000d5b8 LR: c0010fb8 CTR: 00000080
Feb 2 12:59:17 fox_1 kernel: REGS: c24abb20 TRAP: 0300 Not tainted (2.6.24)
Feb 2 12:59:17 fox_1 kernel: MSR: 00029000 <EE,ME> CR: 22882222 XER: 00000000
Feb 2 12:59:17 fox_1 kernel: DEAR: 4802f000, ESR: 00000000
Feb 2 12:59:17 fox_1 kernel: TASK = cf894d20[942] 'oops' THREAD: c24aa000
Feb 2 12:59:17 fox_1 kernel: GPR00: c22c7680 c24abbd0 cf894d20 4802f000 00000080 000f8b60 4802f000 ffffffff
Feb 2 12:59:17 fox_1 kernel: GPR08: 00000000 c22c7680 000008d1 00000000 22882222 10018a64 00000006 c035a300
Feb 2 12:59:17 fox_1 kernel: GPR16: 00024000 c0380000 c24aa000 c24abc9c c24abc98 c2570480 c22c7680 c0380000
Feb 2 12:59:17 fox_1 kernel: GPR24: c0390420 cf09d000 c0497b60 c5b63948 4802f000 c24aa000 000000bc c0497b60
Feb 2 12:59:17 fox_1 kernel: NIP [c000d5b8] __flush_dcache_icache+0x14/0x40
Feb 2 12:59:17 fox_1 kernel: LR [c0010fb8] update_mmu_cache+0x94/0x98
Feb 2 12:59:17 fox_1 kernel: Call Trace:
Feb 2 12:59:17 fox_1 kernel: [c24abbd0] [c24aa000] 0xc24aa000 (unreliable)
Feb 2 12:59:17 fox_1 kernel: [c24abbe0] [c005d978] handle_mm_fault+0x374/0x6a4
Feb 2 12:59:17 fox_1 kernel: [c24abc30] [c005ddd0] get_user_pages+0x128/0x384
Feb 2 12:59:17 fox_1 kernel: [c24abc90] [c00a80d8] elf_core_dump+0xab8/0xb74
Feb 2 12:59:17 fox_1 kernel: [c24abd30] [c007718c] do_coredump+0x730/0x758
Feb 2 12:59:17 fox_1 kernel: [c24abe30] [c002eeb0] get_signal_to_deliver+0x244/0x3c4
Feb 2 12:59:17 fox_1 kernel: [c24abe80] [c000782c] do_signal+0x48/0x264
Feb 2 12:59:17 fox_1 kernel: [c24abf40] [c000e4ac] do_user_signal+0x74/0xc4
Feb 2 12:59:17 fox_1 kernel: Instruction dump:
Feb 2 12:59:17 fox_1 kernel: 4d820020 7c8903a6 7c001bac 38630020 4200fff8 7c0004ac 4e800020 60000000
Feb 2 12:59:17 fox_1 kernel: 54630026 38800080 7c8903a6 7c661b78 <7c00186c> 38630020 4200fff8 7c0004ac
Feb 2 12:59:17 fox_1 kernel: ---[ end trace a1d91e665173315a ]---
Feb 2 12:59:17 fox_1 kernel: note: oops[942] exited with preempt_count 1
It does not oops when the core dump is disabled.
Regards,
Clemens
^ permalink raw reply
* [PATCH 3/3 2.6.24-git] PPC/LIBATA: Select HAVE_PATA_PLATFORM for ARCH_PPC
From: Ben Dooks @ 2008-02-02 16:21 UTC (permalink / raw)
To: linux-ide, jeff, htejun; +Cc: linuxppc-dev, Ben Dooks
In-Reply-To: <20080202162133.678366209@fluff.org.uk>
Use the new HAVE_PATA_PLATFORM to select PATA_PLATFORM
driver.
CC: linuxppc-dev@ozlabs.org
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Index: linux-2.6.24-git12-pata2/arch/ppc/Kconfig
===================================================================
--- linux-2.6.24-git12-pata2.orig/arch/ppc/Kconfig
+++ linux-2.6.24-git12-pata2/arch/ppc/Kconfig
@@ -41,6 +41,7 @@ config GENERIC_CALIBRATE_DELAY
config PPC
bool
+ select HAVE_PATA_PLATFORM
default y
config PPC32
Index: linux-2.6.24-git12-pata2/drivers/ata/Kconfig
===================================================================
--- linux-2.6.24-git12-pata2.orig/drivers/ata/Kconfig
+++ linux-2.6.24-git12-pata2/drivers/ata/Kconfig
@@ -624,7 +624,7 @@ config HAVE_PATA_PLATFORM
config PATA_PLATFORM
tristate "Generic platform device PATA support"
- depends on EMBEDDED || PPC || HAVE_PATA_PLATFORM
+ depends on EMBEDDED || HAVE_PATA_PLATFORM
help
This option enables support for generic directly connected ATA
devices commonly found on embedded systems.
--
Ben (ben@fluff.org, http://www.fluff.org/)
'a smiley only costs 4 bytes'
^ permalink raw reply
* [PATCH] [POWERPC] Fix storcenter DTS typos, feedback, IRQs.
From: Jon Loeliger @ 2008-02-02 19:02 UTC (permalink / raw)
To: linuxppc-dev; +Cc: andy
Cleaned up IRQ layout and removed unsused ISU allocations.
Fixed RTC address typo from /dts-v1/ conversion.
Incorporated list suggestions to use an "iomega," vendor prefix,
and to use a node reference rather than a hard path.
Signed-off-by: Jon Loeliger <jdl@@jdl.com>
---
Kumar,
I tried to use one large, linear IRQ block and shift the
IRQs up to, like, around 129 or so, but it did not work.
This patch definitely works, so I suspect some issue trying
to setup (non-)IRQs between 0x50000 and 0x51000 or so. Ick.
In any even, this is defintely a valid bug fix. If you
would, please pick up for 2.6.25.
Thanks,
jdl
arch/powerpc/boot/dts/storcenter.dts | 12 +++++-----
arch/powerpc/platforms/embedded6xx/storcenter.c | 25 ++++------------------
2 files changed, 11 insertions(+), 26 deletions(-)
diff --git a/arch/powerpc/boot/dts/storcenter.dts b/arch/powerpc/boot/dts/storcenter.dts
index 2204874..5893816 100644
--- a/arch/powerpc/boot/dts/storcenter.dts
+++ b/arch/powerpc/boot/dts/storcenter.dts
@@ -15,7 +15,7 @@
/ {
model = "StorCenter";
- compatible = "storcenter";
+ compatible = "iomega,storcenter";
#address-cells = <1>;
#size-cells = <1>;
@@ -62,12 +62,12 @@
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
- interrupts = <5 2>;
+ interrupts = <17 2>;
interrupt-parent = <&mpic>;
rtc@68 {
compatible = "dallas,ds1337";
- reg = <68>;
+ reg = <0x68>;
};
};
@@ -78,7 +78,7 @@
reg = <0x4500 0x20>;
clock-frequency = <97553800>; /* Hz */
current-speed = <115200>;
- interrupts = <9 2>;
+ interrupts = <25 2>;
interrupt-parent = <&mpic>;
};
@@ -89,7 +89,7 @@
reg = <0x4600 0x20>;
clock-frequency = <97553800>; /* Hz */
current-speed = <9600>;
- interrupts = <10 2>;
+ interrupts = <26 2>;
interrupt-parent = <&mpic>;
};
@@ -136,6 +136,6 @@
};
chosen {
- linux,stdout-path = "/soc/serial@4500";
+ linux,stdout-path = &serial0;
};
};
diff --git a/arch/powerpc/platforms/embedded6xx/storcenter.c b/arch/powerpc/platforms/embedded6xx/storcenter.c
index e12e9d2..8864e48 100644
--- a/arch/powerpc/platforms/embedded6xx/storcenter.c
+++ b/arch/powerpc/platforms/embedded6xx/storcenter.c
@@ -132,33 +132,18 @@ static void __init storcenter_init_IRQ(void)
paddr = (phys_addr_t)of_translate_address(dnp, prop);
mpic = mpic_alloc(dnp, paddr, MPIC_PRIMARY | MPIC_WANTS_RESET,
- 4, 32, " EPIC ");
+ 16, 32, " OpenPIC ");
of_node_put(dnp);
BUG_ON(mpic == NULL);
- /* PCI IRQs */
/*
- * 2.6.12 patch:
- * openpic_set_sources(0, 5, OpenPIC_Addr + 0x10200);
- * openpic_set_sources(5, 2, OpenPIC_Addr + 0x11120);
- * first_irq, num_irqs, __iomem first_ISR
- * o_ss: i, src: 0, fdf50200
- * o_ss: i, src: 1, fdf50220
- * o_ss: i, src: 2, fdf50240
- * o_ss: i, src: 3, fdf50260
- * o_ss: i, src: 4, fdf50280
- * o_ss: i, src: 5, fdf51120
- * o_ss: i, src: 6, fdf51140
+ * 16 Serial Interrupts followed by 16 Internal Interrupts.
+ * I2C is the second internal, so it is at 17, 0x11020.
*/
mpic_assign_isu(mpic, 0, paddr + 0x10200);
- mpic_assign_isu(mpic, 1, paddr + 0x10220);
- mpic_assign_isu(mpic, 2, paddr + 0x10240);
- mpic_assign_isu(mpic, 3, paddr + 0x10260);
- mpic_assign_isu(mpic, 4, paddr + 0x10280);
- mpic_assign_isu(mpic, 5, paddr + 0x11120);
- mpic_assign_isu(mpic, 6, paddr + 0x11140);
+ mpic_assign_isu(mpic, 1, paddr + 0x11000);
mpic_init(mpic);
}
@@ -178,7 +163,7 @@ static int __init storcenter_probe(void)
{
unsigned long root = of_get_flat_dt_root();
- return of_flat_dt_is_compatible(root, "storcenter");
+ return of_flat_dt_is_compatible(root, "iomega,storcenter");
}
define_machine(storcenter){
--
1.5.4.rc4.25.g81cc
^ permalink raw reply related
* Re: [PATCH 3/3 2.6.24-git] PPC/LIBATA: Select HAVE_PATA_PLATFORM for ARCH_PPC
From: Olof Johansson @ 2008-02-02 19:12 UTC (permalink / raw)
To: Ben Dooks; +Cc: linux-ide, htejun, jeff, linuxppc-dev
In-Reply-To: <20080202162232.212855590@fluff.org.uk>
On Sat, Feb 02, 2008 at 04:21:36PM +0000, Ben Dooks wrote:
> Use the new HAVE_PATA_PLATFORM to select PATA_PLATFORM
> driver.
>
> CC: linuxppc-dev@ozlabs.org
> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
What tree is this against? It doesn't apply to current mainline nor
jgarzik's libata-dev upstream branch.
Anyway: NACK: I like this approach but this needs to be added to
arch/powerpc as well.
It's actually more needed there than arch/ppc, I don't personally care
if arch/ppc can't use pata_platform for the last couple of months it's
still around (it's getting deleted this summer, all platforms should
have moved to powerpc by then).
-Olof
^ permalink raw reply
* Re: [PATCH 3/3 2.6.24-git] PPC/LIBATA: Select HAVE_PATA_PLATFORM for ARCH_PPC
From: Ben Dooks @ 2008-02-02 19:41 UTC (permalink / raw)
To: Olof Johansson; +Cc: linux-ide, htejun, jeff, Ben Dooks, linuxppc-dev
In-Reply-To: <20080202191239.GA29039@lixom.net>
On Sat, Feb 02, 2008 at 01:12:39PM -0600, Olof Johansson wrote:
> On Sat, Feb 02, 2008 at 04:21:36PM +0000, Ben Dooks wrote:
> > Use the new HAVE_PATA_PLATFORM to select PATA_PLATFORM
> > driver.
> >
> > CC: linuxppc-dev@ozlabs.org
> > Signed-off-by: Ben Dooks <ben-linux@fluff.org>
>
> What tree is this against? It doesn't apply to current mainline nor
> jgarzik's libata-dev upstream branch.
It is a series that i've just sent to the linux-ide list, only the ppc
part was cc'd to the ppc list.
> Anyway: NACK: I like this approach but this needs to be added to
> arch/powerpc as well.
I can add that to the series.
> It's actually more needed there than arch/ppc, I don't personally care
> if arch/ppc can't use pata_platform for the last couple of months it's
> still around (it's getting deleted this summer, all platforms should
> have moved to powerpc by then).
Thanks, didn't know that.
--
Ben
Q: What's a light-year?
A: One-third less calories than a regular year.
^ permalink raw reply
* Re: 83xx HDLC Driver Dev - Multiple PHYs?
From: Jochen Friedrich @ 2008-02-02 20:36 UTC (permalink / raw)
To: rmcguire; +Cc: linuxppc-embedded
In-Reply-To: <000001c862fe$5ff16550$6405a8c0@absolut>
Hi Russell,
> I am putting support for multiple PHY's into the HDLC driver, but after
> converting it to use the of_device tree, and inserting a UCC@5000 for a
> single UCC HDLC driver, it occurred to me that if I insert more devices
> (UCC@6000, UCC@7000, UCC@8000) that the driver will attempt to load multiple
> times.
The module should only be loaded once. If the driver attempts to load multiple
times, this looks like a userscpace bug.
Thanks,
Jochen
^ permalink raw reply
* Re: [PATCH 3/3 2.6.24-git] PPC/LIBATA: Select HAVE_PATA_PLATFORM for ARCH_PPC
From: Olof Johansson @ 2008-02-03 0:23 UTC (permalink / raw)
To: Ben Dooks; +Cc: linux-ide, htejun, jeff, linuxppc-dev
In-Reply-To: <20080202194102.GJ26792@trinity.fluff.org>
On Sat, Feb 02, 2008 at 07:41:02PM +0000, Ben Dooks wrote:
> On Sat, Feb 02, 2008 at 01:12:39PM -0600, Olof Johansson wrote:
> > On Sat, Feb 02, 2008 at 04:21:36PM +0000, Ben Dooks wrote:
> > > Use the new HAVE_PATA_PLATFORM to select PATA_PLATFORM
> > > driver.
> > >
> > > CC: linuxppc-dev@ozlabs.org
> > > Signed-off-by: Ben Dooks <ben-linux@fluff.org>
> >
> > What tree is this against? It doesn't apply to current mainline nor
> > jgarzik's libata-dev upstream branch.
>
> It is a series that i've just sent to the linux-ide list, only the ppc
> part was cc'd to the ppc list.
D'oh. Ok, makes more sense now.
Are you planning on adding HAVE_PATA_PLATFORM to the other archs that
use it as well, or keep it under EMBEDDED there?
> > Anyway: NACK: I like this approach but this needs to be added to
> > arch/powerpc as well.
>
> I can add that to the series.
Ok, cool. We can probably move it in under the relevant powerpc
sub-platforms over time, and that's a powerpc-specific change anyway,
no need to get that through linux-ide.
> > It's actually more needed there than arch/ppc, I don't personally care
> > if arch/ppc can't use pata_platform for the last couple of months it's
> > still around (it's getting deleted this summer, all platforms should
> > have moved to powerpc by then).
>
> Thanks, didn't know that.
No problem. :)
-Olof
^ permalink raw reply
* RE: Kernel oops while duming user core.
From: Benjamin Herrenschmidt @ 2008-02-03 7:34 UTC (permalink / raw)
To: Rune Torgersen; +Cc: Scott Wood, linuxppc-dev, Nathan Lynch
In-Reply-To: <DCEAAC0833DD314AB0B58112AD99B93B03EE4A90@ismail.innsys.innovsys.com>
On Thu, 2008-01-31 at 16:10 -0600, Rune Torgersen wrote:
> Scott Wood wrote:
> > Scott Wood wrote:
> >> Nathan Lynch wrote:
> >>> Is the crashing program multithreaded? The first report had firefox
> >>> triggering the oops.
> >>
> >> OK, I've got a test program that triggers it now. I'll see if I can
> >> figure out what's going on.
> >
> > The problem seems to be that update_mmu_cache() is called on a guard
> > page with no access rights.
> >
> > Changing update_mmu_cache() to always call flush_dcache_icache_page()
> > fixes it, though a better performing fix would probably be to add an
> > exception table entry for the dcbst.
>
> I can confirm that this seems to fix it.
Might be better to avoid the flush when the page isn't readable ?
Ben.
^ permalink raw reply
* Re: [PATCH] Fix ext4 bitops
From: Benjamin Herrenschmidt @ 2008-02-03 7:36 UTC (permalink / raw)
To: Bastian Blank; +Cc: linuxppc-dev, akpm, linux-kernel
In-Reply-To: <20080201200240.GA28566@wavehammer.waldi.eu.org>
On Fri, 2008-02-01 at 21:02 +0100, Bastian Blank wrote:
> Fix ext4 bitops.
Please provide a better description, as it's not obvious at first sight.
> Signed-off-by: Bastian Blank <waldi@debian.org>
>
> diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h
> index 220d9a7..d0980df 100644
> --- a/include/asm-powerpc/bitops.h
> +++ b/include/asm-powerpc/bitops.h
> @@ -363,6 +363,8 @@ unsigned long generic_find_next_le_bit(const unsigned long *addr,
> unsigned long size, unsigned long offset);
> /* Bitmap functions for the ext2 filesystem */
>
> +#include <asm-generic/bitops/le.h>
A comment would be useful to indicate that this defines the _le versions
of the bitops as it would be easy to mistake that for something else.
> #define ext2_set_bit(nr,addr) \
> __test_and_set_le_bit((nr), (unsigned long*)addr)
> #define ext2_clear_bit(nr, addr) \
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* [PATCH] MTD support for the AMCC Taishan
From: Imre Kaloz @ 2008-02-03 10:41 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
---
arch/powerpc/boot/dts/taishan.dts | 33 +++++++++++-
arch/powerpc/configs/taishan_defconfig | 89 ++++++++++++++++++++++++++++++--
2 files changed, 116 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts
index 0706a4a..28c14dd 100644
--- a/arch/powerpc/boot/dts/taishan.dts
+++ b/arch/powerpc/boot/dts/taishan.dts
@@ -174,7 +174,38 @@
interrupts = <5 4>;
interrupt-parent = <&UIC1>;
- /* TODO: Add other EBC devices */
+ nor_flash@0,0 {
+ compatible = "cfi-flash";
+ bank-width = <4>;
+ device-width = <2>;
+ reg = <0 000000 4000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "kernel";
+ reg = <0 180000>;
+ };
+ partition@180000 {
+ label = "root";
+ reg = <180000 200000>;
+ };
+ partition@380000 {
+ label = "user";
+ reg = <380000 3a80000>;
+ };
+ partition@3e00000 {
+ label = "kozio";
+ reg = <3e00000 140000>;
+ };
+ partition@3f40000 {
+ label = "env";
+ reg = <3f40000 80000>;
+ };
+ partition@3fc0000 {
+ label = "u-boot";
+ reg = <3fc0000 40000>;
+ };
+ };
};
diff --git a/arch/powerpc/configs/taishan_defconfig b/arch/powerpc/configs/taishan_defconfig
index ade84b9..4d17a5d 100644
--- a/arch/powerpc/configs/taishan_defconfig
+++ b/arch/powerpc/configs/taishan_defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24-rc6
-# Mon Dec 24 11:23:39 2007
+# Linux kernel version: 2.6.24
+# Sun Feb 3 00:40:49 2008
#
# CONFIG_PPC64 is not set
@@ -103,6 +103,7 @@ CONFIG_SLUB_DEBUG=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
@@ -146,7 +147,9 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_TAISHAN=y
# CONFIG_KATMAI is not set
# CONFIG_RAINIER is not set
+# CONFIG_WARP is not set
CONFIG_440GX=y
+# CONFIG_IPIC is not set
# CONFIG_MPIC is not set
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
@@ -330,7 +333,83 @@ CONFIG_FW_LOADER=y
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_BLKDEVS is not set
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
@@ -385,7 +464,6 @@ CONFIG_NETDEVICES=y
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
-# CONFIG_IP1000 is not set
# CONFIG_ARCNET is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
@@ -414,6 +492,7 @@ CONFIG_NETDEV_1000=y
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
@@ -641,6 +720,7 @@ CONFIG_TMPFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
@@ -675,7 +755,6 @@ CONFIG_SUNRPC=y
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
# CONFIG_DLM is not set
-# CONFIG_UCC_SLOW is not set
#
# Library routines
--
1.5.2.5
^ permalink raw reply related
* Re: [PATCH] Fix ext4 bitops
From: Geert Uytterhoeven @ 2008-02-03 12:39 UTC (permalink / raw)
To: Heiko Carstens, aneesh.kumar
Cc: linux-s390, Bastian Blank, Linux Kernel Development,
Linux/PPC Development, Andrew Morton, linux-ext4
In-Reply-To: <20080203121238.GD18211@osiris.ibm.com>
On Sun, 3 Feb 2008, Heiko Carstens wrote:
> On Fri, Feb 01, 2008 at 10:04:04PM +0100, Bastian Blank wrote:
> > On Fri, Feb 01, 2008 at 12:22:57PM -0800, Andrew Morton wrote:
> > > On Fri, 1 Feb 2008 21:02:08 +0100
> > > Bastian Blank <bastian@waldi.eu.org> wrote:
> > >
> > > > Fix ext4 bitops.
> > >
> > > This is incomplete. Please tell us what was "fixed".
> > >
> > > If it was a build error then please quote the compile error output in the
> > > changelog, as well as the usual description of what the problem is, and how
> > > it was fixed.
> >
> > | fs/ext4/mballoc.c: In function 'ext4_mb_generate_buddy':
> > | fs/ext4/mballoc.c:954: error: implicit declaration of function 'generic_find_next_le_bit'
> >
> > The s390 specific bitops uses parts of the generic implementation.
> > Include the correct header.
>
> That doesn't work:
>
> fs/built-in.o: In function `ext4_mb_release_inode_pa':
> mballoc.c:(.text+0x95a8a): undefined reference to `generic_find_next_le_bit'
> fs/built-in.o: In function `ext4_mb_init_cache':
> mballoc.c:(.text+0x967ea): undefined reference to `generic_find_next_le_bit'
>
> This still needs generic_find_next_le_bit which comes
> from lib/find_next_bit.c. That one doesn't get built on s390 since we
> don't set GENERIC_FIND_NEXT_BIT.
> Currently we have the lengthly patch below queued.
Similar issue on m68k. As Bastian also saw it on powerpc, I'm getting the
impression the ext4 people don't (compile) test on big endian machines?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] ADB: Add missing #include <linux/platform_device.h>
From: Geert Uytterhoeven @ 2008-02-03 15:49 UTC (permalink / raw)
To: Linus Torvalds, Andrew Morton, Johannes Berg
Cc: Linux/m68k, Paul Mackerras, Linux Kernel Development,
Linux/PPC Development
ADB: Add missing #include <linux/platform_device.h>
Commit c9f6d3d5c6d4f4cd3a53549a69c92951180e2a76
[POWERPC] adb: Replace sleep notifier with platform driver suspend/resume hooks
introduced compile errors on m68k because <linux/platform_device.h> is not
explicitly included. On powerpc, it's pulled in through <asm/prom.h>.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
drivers/macintosh/adb.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/macintosh/adb.c
+++ b/drivers/macintosh/adb.c
@@ -36,6 +36,7 @@
#include <linux/completion.h>
#include <linux/device.h>
#include <linux/kthread.h>
+#include <linux/platform_device.h>
#include <asm/uaccess.h>
#include <asm/semaphore.h>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* compile quirk linux-2.6.24 (with workaround)
From: Bernhard Reiter @ 2008-02-03 16:29 UTC (permalink / raw)
To: debian-powerpc; +Cc: paulus, linuxppc-dev
[-- Attachment #1.1: Type: text/plain, Size: 2481 bytes --]
Dear linux powerpc Maintainers and Users,
recently I have tried to compile a new kernel on a Debian sarge ppc
system (PowerBook5,6 MacRISC3 Power Macintosh).
The build system bailed out with
BOOTCC arch/powerpc/boot/4xx.o
cc1: error: bad value (440) for -mcpu= switch
make[1]: *** [arch/powerpc/boot/4xx.o] Fehler 1
I have tracked this a few steps and the attached patch made the compile for me
as my compiler gcc-Version 3.3.5 (Debian 1:3.3.5-13)
cannot produce code for 4xx it seems.
The "ARCH=ppc64" I have came about also looked wrong, but I do not know
if this part of the patch is really necessary.
It is just a workaround, as I have no insight of what is really going wrong.
I hope my report is useful,
Bernhard
Details:
I have used "make oldconfig" with a 2.6.17 kernel and answered some questions.
Here is the first section of the .config I've ended up with:
# CONFIG_PPC64 is not set
#
# Processor support
#
CONFIG_6xx=y
# CONFIG_PPC_85xx is not set
# CONFIG_PPC_8xx is not set
# CONFIG_40x is not set
# CONFIG_44x is not set
# CONFIG_E200 is not set
CONFIG_PPC_FPU=y
CONFIG_ALTIVEC=y
CONFIG_PPC_STD_MMU=y
CONFIG_PPC_STD_MMU_32=y
# CONFIG_PPC_MM_SLICES is not set
# CONFIG_SMP is not set
CONFIG_PPC32=y
CONFIG_WORD_SIZE=32
CONFIG_PPC_MERGE=y
CONFIG_MMU=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_IRQ_PER_CPU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_ARCH_HAS_ILOG2_U32=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
CONFIG_PPC=y
CONFIG_EARLY_PRINTK=y
CONFIG_GENERIC_NVRAM=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_PPC_OF=y
CONFIG_OF=y
CONFIG_PPC_UDBG_16550=y
# CONFIG_GENERIC_TBSYNC is not set
CONFIG_AUDIT_ARCH=y
CONFIG_GENERIC_BUG=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
# CONFIG_DEFAULT_UIMAGE is not set
# CONFIG_PPC_DCR_NATIVE is not set
# CONFIG_PPC_DCR_MMIO is not set
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
--
Managing Director - Owner: www.intevation.net (Free Software Company)
Germany Coordinator: fsfeurope.org. Coordinator: www.Kolab-Konsortium.com.
Intevation GmbH, Osnabrück, DE; Amtsgericht Osnabrück, HRB 18998
Geschäftsführer Frank Koormann, Bernhard Reiter, Dr. Jan-Oliver Wagner
[-- Attachment #1.2: linux-2.6.24-rc7.fix.diff --]
[-- Type: text/x-diff, Size: 1960 bytes --]
diff -ur linux-2.6.24-rc7/arch/powerpc/boot/Makefile linux-2.6.24-rc7.new/arch/powerpc/boot/Makefile
--- linux-2.6.24-rc7/arch/powerpc/boot/Makefile 2008-01-20 21:31:13.544357150 +0100
+++ linux-2.6.24-rc7.new/arch/powerpc/boot/Makefile 2008-01-15 00:05:14.935750138 +0100
@@ -49,13 +49,13 @@
src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
ns16550.c serial.c simple_alloc.c div64.S util.S \
gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \
- 4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \
+ mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \
cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
fsl-soc.c mpc8xx.c pq2.c
src-plat := of.c cuboot-52xx.c cuboot-83xx.c cuboot-85xx.c holly.c \
cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
- cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c \
+ cuboot-pq2.c cuboot-sequoia.c cuboot-bamboo.c \
fixed-head.S ep88xc.c cuboot-hpc2.c
src-boot := $(src-wlib) $(src-plat) empty.c
Nur in linux-2.6.24-rc7.new/arch/powerpc/boot: zImage.coff.
Nur in linux-2.6.24-rc7.new/arch/powerpc/boot: zImage.miboot.
Nur in linux-2.6.24-rc7.new/arch/powerpc/kernel: vmlinux.lds.
diff -ur linux-2.6.24-rc7/arch/powerpc/Makefile linux-2.6.24-rc7.new/arch/powerpc/Makefile
--- linux-2.6.24-rc7/arch/powerpc/Makefile 2008-01-20 21:31:13.524359050 +0100
+++ linux-2.6.24-rc7.new/arch/powerpc/Makefile 2008-01-14 23:48:30.583750138 +0100
@@ -165,7 +165,8 @@
boot := arch/$(ARCH)/boot
$(BOOT_TARGETS): vmlinux
- $(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
+ $(Q)$(MAKE) ARCH=powerpc $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
+# $(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
define archhelp
@echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* [RFC PATCH 0/11] Patches needed to support QE USB Host Controller
From: Anton Vorontsov @ 2008-02-03 17:08 UTC (permalink / raw)
To: linuxppc-dev; +Cc: David Brownell, linux-usb
Hi all,
These patches are needed to support "FHCI" host controller.
This includes:
- GPIO LIB support for PowerPC;
- GPIO LIB support for QUICC Engine;
- gpio_set_dedicated() addition to GPIO LIB;
- QE LIB additions: usb, gtm;
- FHCI driver;
- Support for MPC8360E-RDK as an example.
I have already posted GPIO LIB support for PowerPC/QE, but since
patches changed a bit, I thought it's good idea to take a chance
and repost them for the next RFC round.
Thanks,
p.s.
David, I'm Cc:ing you to this patchset (except qe_gtm, and qe_usb
patches -- nothing insteresting), to show the complete picture of
why we need additions to GPIO LIB.
Also will appreciate any comments regarding GPIO LIB support for
PowerPC/QE.
linux-usb Cc'ed only for FHCI driver patch.
--
Anton Vorontsov
email: cbou@mail.ru
backup email: ya-cbou@yandex.ru
irc://irc.freenode.net/bd2
^ permalink raw reply
* [PATCH 01/11] [POWERPC] Implement support for the GPIO LIB API
From: Anton Vorontsov @ 2008-02-03 17:09 UTC (permalink / raw)
To: linuxppc-dev; +Cc: David Brownell
In-Reply-To: <20080203170820.GA18520@localhost.localdomain>
This patch implements support for the GPIO LIB API. Two calls
unimplemented though: irq_to_gpio and gpio_to_irq.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
Documentation/powerpc/booting-without-of.txt | 58 ++++++++
arch/powerpc/Kconfig | 5 +
arch/powerpc/kernel/Makefile | 1 +
arch/powerpc/kernel/gpio.c | 200 ++++++++++++++++++++++++++
include/asm-powerpc/gpio.h | 118 +++++++++++++++
5 files changed, 382 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/kernel/gpio.c
create mode 100644 include/asm-powerpc/gpio.h
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 7b30798..ce77b47 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -64,6 +64,10 @@ Table of Contents
3) OpenPIC Interrupt Controllers
4) ISA Interrupt Controllers
+ VIII - Specifying GPIO information for devices
+ 1) gpios property
+ 2) gpio-controller nodes
+
Appendix A - Sample SOC node for MPC8540
@@ -2858,6 +2862,60 @@ encodings listed below:
2 = high to low edge sensitive type enabled
3 = low to high edge sensitive type enabled
+VIII - Specifying GPIO information for devices
+==============================================
+
+1) gpios property
+-----------------
+
+Nodes that makes use of GPIOs should define them using `gpios' property,
+format of which is: <&gpio-controller1-phandle gpio1-specifier
+ &gpio-controller2-phandle gpio2-specifier
+ ...>;
+
+Note that gpio-specifier length is controller dependent.
+
+gpio-specifier may encode: bank, pin position inside the bank,
+whether pin is open-drain and whether pin is logically inverted.
+
+Example of the node using GPIOs:
+
+ nand-flash@1,0 {
+ compatible = "stmicro,NAND512W3A2BN6E", "fsl,upm-nand";
+ reg = <1 0 1>;
+ width = <1>;
+ upm = "A";
+ upm-addr-offset = <16>;
+ upm-cmd-offset = <8>;
+ gpios = <&qe_pio_e 18 0>;
+ wait-pattern;
+ wait-write;
+ };
+
+In this example gpio-specifier is "18 0" and encodes GPIO pin number,
+and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
+
+2) gpio-controller nodes
+------------------------
+
+Every GPIO controller node must have #gpio-cells property defined,
+this information will be used to translate gpio-specifiers.
+
+Example of two SOC GPIO banks defined as gpio-controller nodes:
+
+ qe_pio_a: gpio-controller@1400 {
+ #gpio-cells = <2>;
+ compatible = "fsl,qe-pario-bank";
+ reg = <0x1400 0x18>;
+ gpio-controller;
+ };
+
+ qe_pio_e: gpio-controller@1460 {
+ #gpio-cells = <2>;
+ compatible = "fsl,qe-pario-bank";
+ reg = <0x1460 0x18>;
+ gpio-controller;
+ };
Appendix A - Sample SOC node for MPC8540
========================================
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 9c44af3..f9ed22b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -81,6 +81,11 @@ config GENERIC_FIND_NEXT_BIT
bool
default y
+config GENERIC_GPIO
+ bool
+ help
+ Generic GPIO API support
+
config ARCH_NO_VIRT_TO_BUS
def_bool PPC64
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 58dbfef..349a52d 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_BOOTX_TEXT) += btext.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_KPROBES) += kprobes.o
obj-$(CONFIG_PPC_UDBG_16550) += legacy_serial.o udbg_16550.o
+obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o
pci64-$(CONFIG_PPC64) += pci_dn.o isa-bridge.o
obj-$(CONFIG_PCI) += pci_$(CONFIG_WORD_SIZE).o $(pci64-y) \
diff --git a/arch/powerpc/kernel/gpio.c b/arch/powerpc/kernel/gpio.c
new file mode 100644
index 0000000..64c567d
--- /dev/null
+++ b/arch/powerpc/kernel/gpio.c
@@ -0,0 +1,200 @@
+/*
+ * OF helpers for the GPIO API
+ *
+ * Copyright (c) 2007 MontaVista Software, Inc.
+ * Copyright (c) 2007 Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <asm/prom.h>
+#include <asm/gpio.h>
+
+int of_get_gpio(struct device_node *np, int index)
+{
+ int ret = -EINVAL;
+ struct device_node *gc;
+ struct of_gpio_chip *of_gc = NULL;
+ int size;
+ const u32 *gpios;
+ u32 nr_cells;
+ int i;
+ const void *gpio_spec;
+ const u32 *gpio_cells;
+ int gpio_index = 0;
+
+ gpios = of_get_property(np, "gpios", &size);
+ if (!gpios) {
+ ret = -ENOENT;
+ goto err0;
+ }
+ nr_cells = size / sizeof(u32);
+
+ for (i = 0; i < nr_cells;) {
+ const phandle *gpio_phandle;
+
+ gpio_phandle = gpios + i;
+ gpio_spec = gpio_phandle + 1;
+
+ /* one cell hole in the gpios = <>; */
+ if (!*gpio_phandle) {
+ if (gpio_index == index)
+ return -ENOENT;
+ i++;
+ gpio_index++;
+ continue;
+ }
+
+ gc = of_find_node_by_phandle(*gpio_phandle);
+ if (!gc) {
+ pr_debug("%s: could not find phandle for gpios\n",
+ np->full_name);
+ goto err0;
+ }
+
+ of_gc = gc->data;
+ if (!of_gc) {
+ pr_debug("%s: gpio controller %s isn't registered\n",
+ np->full_name, gc->full_name);
+ goto err1;
+ }
+
+ gpio_cells = of_get_property(gc, "#gpio-cells", &size);
+ if (!gpio_cells || size != sizeof(*gpio_cells) ||
+ *gpio_cells != of_gc->gpio_cells) {
+ pr_debug("%s: wrong #gpio-cells for %s\n",
+ np->full_name, gc->full_name);
+ goto err1;
+ }
+
+ /* Next phandle is at phandle cells + #gpio-cells */
+ i += sizeof(*gpio_phandle) / sizeof(u32) + *gpio_cells;
+ if (i >= nr_cells + 1) {
+ pr_debug("%s: insufficient gpio-spec length\n",
+ np->full_name);
+ goto err1;
+ }
+
+ if (gpio_index == index)
+ break;
+
+ of_gc = NULL;
+ of_node_put(gc);
+ gpio_index++;
+ }
+
+ if (!of_gc) {
+ ret = -ENOENT;
+ goto err0;
+ }
+
+ ret = of_gc->xlate(of_gc, np, gpio_spec);
+ if (ret < 0)
+ goto err1;
+
+ ret += of_gc->gc.base;
+err1:
+ of_node_put(gc);
+err0:
+ pr_debug("%s exited with status %d\n", __func__, ret);
+ return ret;
+}
+EXPORT_SYMBOL(of_get_gpio);
+
+static int of_gpio_simple_xlate(struct of_gpio_chip *of_gc,
+ struct device_node *np,
+ const void *gpio_spec)
+{
+ const u32 *gpio = gpio_spec;
+
+ if (*gpio > of_gc->gc.ngpio)
+ return -EINVAL;
+
+ return *gpio;
+}
+
+static int of_get_gpiochip_base(struct device_node *np)
+{
+ struct device_node *gc = NULL;
+ int gpiochip_base = 0;
+
+ while ((gc = of_find_all_nodes(gc))) {
+ if (!of_get_property(gc, "gpio-controller", NULL))
+ continue;
+
+ if (gc != np) {
+ gpiochip_base += ARCH_OF_GPIOS_PER_CHIP;
+ continue;
+ }
+
+ of_node_put(gc);
+
+ if (gpiochip_base >= ARCH_OF_GPIOS_END)
+ return -ENOSPC;
+
+ return gpiochip_base;
+ }
+
+ return -ENOENT;
+}
+
+int of_mm_gpiochip_add(struct device_node *np,
+ struct of_mm_gpio_chip *mm_gc)
+{
+ int ret = -ENOMEM;
+ struct of_gpio_chip *of_gc = &mm_gc->of_gc;
+
+ if (of_gc->gc.ngpio > ARCH_OF_GPIOS_PER_CHIP) {
+ ret = -ENOSPC;
+ goto err;
+ }
+
+ mm_gc->of_gc.gc.label = kstrdup(np->full_name, GFP_KERNEL);
+ if (!mm_gc->of_gc.gc.label)
+ goto err;
+
+ mm_gc->regs = of_iomap(np, 0);
+ if (!mm_gc->regs)
+ goto err1;
+
+ ret = of_get_gpiochip_base(np);
+ if (ret < 0)
+ goto err2;
+ mm_gc->of_gc.gc.base = ret;
+
+ if (!of_gc->xlate)
+ of_gc->xlate = of_gpio_simple_xlate;
+
+ if (mm_gc->save_regs)
+ mm_gc->save_regs(mm_gc);
+
+ np->data = &mm_gc->of_gc;
+
+ ret = gpiochip_add(&mm_gc->of_gc.gc);
+ if (ret)
+ goto err3;
+
+ /* We don't want to lose the node and its ->data */
+ of_node_get(np);
+
+ pr_debug("%s: registered as generic GPIO chip, base is %d\n",
+ np->full_name, mm_gc->of_gc.gc.base);
+ return 0;
+err3:
+ np->data = NULL;
+err2:
+ iounmap(mm_gc->regs);
+err1:
+ kfree(mm_gc->of_gc.gc.label);
+err:
+ pr_err("%s: GPIO chip registration failed with status %d\n",
+ np->full_name, ret);
+ return ret;
+}
+EXPORT_SYMBOL(of_mm_gpiochip_add);
diff --git a/include/asm-powerpc/gpio.h b/include/asm-powerpc/gpio.h
new file mode 100644
index 0000000..a97a93c
--- /dev/null
+++ b/include/asm-powerpc/gpio.h
@@ -0,0 +1,118 @@
+/*
+ * Generic GPIO API implementation for PowerPC.
+ *
+ * Copyright (c) 2007 MontaVista Software, Inc.
+ * Copyright (c) 2007 Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_POWERPC_GPIO_H
+#define __ASM_POWERPC_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+#ifdef CONFIG_HAVE_GPIO_LIB
+
+#define ARCH_OF_GPIOS_PER_CHIP 32
+#define ARCH_OF_GPIOS_BASE 0
+#define ARCH_OF_GPIOS_END (ARCH_OF_GPIOS_PER_CHIP * 7)
+#define ARCH_NON_OF_GPIOS_BASE ARCH_OF_GPIOS_END
+#define ARCH_NON_OF_GPIOS_END ARCH_NR_GPIOS
+
+#if ARCH_NON_OF_GPIOS_BASE >= ARCH_NON_OF_GPIOS_END
+#error "Default ARCH_NR_GPIOS isn't sufficient, define yours."
+#endif
+
+/*
+ * We don't (yet) implement inlined/rapid versions for on-chip gpios.
+ * Just call gpiolib.
+ */
+static inline int gpio_get_value(unsigned int gpio)
+{
+ return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+ __gpio_set_value(gpio, value);
+}
+
+/*
+ * Not implemented, yet.
+ */
+static inline int gpio_to_irq(unsigned int gpio)
+{
+ return -ENOSYS;
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+ return -ENOSYS;
+}
+
+/*
+ * Generic OF GPIO chip
+ */
+struct of_gpio_chip {
+ struct gpio_chip gc;
+ int gpio_cells;
+ int (*xlate)(struct of_gpio_chip *of_gc, struct device_node *np,
+ const void *gpio_spec);
+};
+
+#define to_of_gpio_chip(x) container_of(x, struct of_gpio_chip, gc)
+
+/*
+ * OF GPIO chip for memory mapped banks
+ */
+struct of_mm_gpio_chip {
+ struct of_gpio_chip of_gc;
+ void (*save_regs)(struct of_mm_gpio_chip *mm_gc);
+ void __iomem *regs;
+};
+
+#define to_of_mm_gpio_chip(x) container_of(to_of_gpio_chip(x), \
+ struct of_mm_gpio_chip, of_gc)
+
+/**
+ * of_get_gpio - Get a GPIO number from the device tree to use with GPIO API
+ * @np: device node to get GPIO from
+ * @index: index of the GPIO
+ *
+ * Returns GPIO number to use with Linux generic GPIO API, or one of the errno
+ * value on the error condition.
+ */
+extern int of_get_gpio(struct device_node *np, int index);
+
+/**
+ * of_mm_gpiochip_add - Add memory mapped GPIO chip (bank)
+ * @np: device node of the GPIO chip
+ * @mm_gc: pointer to the of_mm_gpio_chip allocated structure
+ *
+ * To use this function you should allocate and fill mm_gc with:
+ *
+ * 1) In the gpio_chip structure:
+ * a) all the callbacks
+ * b) ngpios (GPIOs per bank)
+ *
+ * 2) In the of_gpio_chip structure:
+ * a) gpio_cells
+ * b) xlate callback (optional)
+ *
+ * 3) In the of_mm_gpio_chip structure:
+ * a) save_regs callback (optional)
+ *
+ * If succeeded, this function will map bank's memory and will
+ * do all necessary work for you. Then you'll able to use .regs
+ * to manage GPIOs from the callbacks.
+ */
+extern int of_mm_gpiochip_add(struct device_node *np,
+ struct of_mm_gpio_chip *mm_gc);
+
+#endif /* CONFIG_HAVE_GPIO_LIB */
+
+#endif /* __ASM_POWERPC_GPIO_H */
--
1.5.2.2
^ permalink raw reply related
* [PATCH 02/11] [POWERPC] QE: split par_io_config_pin()
From: Anton Vorontsov @ 2008-02-03 17:09 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20080203170820.GA18520@localhost.localdomain>
This patch splits par_io_config_pin so we can use it with GPIO LIB API.
Also add a comment regarding #ifdef CONFIG_PPC_85xx being legacy.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/sysdev/qe_lib/qe_io.c | 60 +++++++++++++++++++++++------------
1 files changed, 39 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index e53ea4d..aef893b 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -37,6 +37,10 @@ struct port_regs {
__be32 cppar1; /* Pin assignment register */
__be32 cppar2; /* Pin assignment register */
#ifdef CONFIG_PPC_85xx
+ /*
+ * This is needed for legacy support only, should go away,
+ * because we started using per-bank gpio chips.
+ */
u8 pad[8];
#endif
};
@@ -63,28 +67,29 @@ int par_io_init(struct device_node *np)
return 0;
}
-int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
- int assignment, int has_irq)
+static void __par_io_config_pin(struct port_regs __iomem *par_io,
+ u8 pin, int dir, int open_drain,
+ int assignment, int has_irq)
{
- u32 pin_mask1bit, pin_mask2bits, new_mask2bits, tmp_val;
-
- if (!par_io)
- return -1;
+ u32 pin_mask1bit;
+ u32 pin_mask2bits;
+ u32 new_mask2bits;
+ u32 tmp_val;
/* calculate pin location for single and 2 bits information */
pin_mask1bit = (u32) (1 << (NUM_OF_PINS - (pin + 1)));
/* Set open drain, if required */
- tmp_val = in_be32(&par_io[port].cpodr);
+ tmp_val = in_be32(&par_io->cpodr);
if (open_drain)
- out_be32(&par_io[port].cpodr, pin_mask1bit | tmp_val);
+ out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
else
- out_be32(&par_io[port].cpodr, ~pin_mask1bit & tmp_val);
+ out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
/* define direction */
tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
- in_be32(&par_io[port].cpdir2) :
- in_be32(&par_io[port].cpdir1);
+ in_be32(&par_io->cpdir2) :
+ in_be32(&par_io->cpdir1);
/* get all bits mask for 2 bit per port */
pin_mask2bits = (u32) (0x3 << (NUM_OF_PINS -
@@ -96,36 +101,49 @@ int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
/* clear and set 2 bits mask */
if (pin > (NUM_OF_PINS / 2) - 1) {
- out_be32(&par_io[port].cpdir2,
+ out_be32(&par_io->cpdir2,
~pin_mask2bits & tmp_val);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io[port].cpdir2, new_mask2bits | tmp_val);
+ out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
} else {
- out_be32(&par_io[port].cpdir1,
+ out_be32(&par_io->cpdir1,
~pin_mask2bits & tmp_val);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io[port].cpdir1, new_mask2bits | tmp_val);
+ out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
}
/* define pin assignment */
tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
- in_be32(&par_io[port].cppar2) :
- in_be32(&par_io[port].cppar1);
+ in_be32(&par_io->cppar2) :
+ in_be32(&par_io->cppar1);
new_mask2bits = (u32) (assignment << (NUM_OF_PINS -
(pin % (NUM_OF_PINS / 2) + 1) * 2));
/* clear and set 2 bits mask */
if (pin > (NUM_OF_PINS / 2) - 1) {
- out_be32(&par_io[port].cppar2,
+ out_be32(&par_io->cppar2,
~pin_mask2bits & tmp_val);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io[port].cppar2, new_mask2bits | tmp_val);
+ out_be32(&par_io->cppar2, new_mask2bits | tmp_val);
} else {
- out_be32(&par_io[port].cppar1,
+ out_be32(&par_io->cppar1,
~pin_mask2bits & tmp_val);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io[port].cppar1, new_mask2bits | tmp_val);
+ out_be32(&par_io->cppar1, new_mask2bits | tmp_val);
}
+}
+
+/*
+ * This is "legacy" function that takes port number as an argument
+ * instead of pointer to the appropriate bank.
+ */
+int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
+ int assignment, int has_irq)
+{
+ if (!par_io || port >= num_par_io_ports)
+ return -EINVAL;
+ __par_io_config_pin(&par_io[port], pin, dir, open_drain, assignment,
+ has_irq);
return 0;
}
EXPORT_SYMBOL(par_io_config_pin);
--
1.5.2.2
^ permalink raw reply related
* [PATCH 03/11] [POWERPC] QE: implement GPIO LIB API
From: Anton Vorontsov @ 2008-02-03 17:10 UTC (permalink / raw)
To: linuxppc-dev; +Cc: David Brownell
In-Reply-To: <20080203170820.GA18520@localhost.localdomain>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
Documentation/powerpc/booting-without-of.txt | 32 ++++---
arch/powerpc/platforms/Kconfig | 2 +
arch/powerpc/sysdev/qe_lib/qe_io.c | 133 ++++++++++++++++++++++++++
3 files changed, 155 insertions(+), 12 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index ce77b47..c5b6004 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1701,24 +1701,32 @@ platforms are moved over to use the flattened-device-tree model.
information.
Required properties:
- - device_type : should be "par_io".
+ - #gpio-cells : should be "2".
+ - compatible : should be "fsl,qe-pario-bank"
- reg : offset to the register set and its length.
- - num-ports : number of Parallel I/O ports
+ - gpio-controller : node to identify gpio controllers.
- Example:
- par_io@1400 {
- reg = <1400 100>;
- #address-cells = <1>;
- #size-cells = <0>;
- device_type = "par_io";
- num-ports = <7>;
- ucc_pin@01 {
- ......
- };
+ For example, two QE Par I/O banks:
+ qe_pio_a: gpio-controller@1400 {
+ #gpio-cells = <2>;
+ compatible = "fsl,qe-pario-bank";
+ reg = <0x1400 0x18>;
+ gpio-controller;
+ };
+ qe_pio_e: gpio-controller@1460 {
+ #gpio-cells = <2>;
+ compatible = "fsl,qe-pario-bank";
+ reg = <0x1460 0x18>;
+ gpio-controller;
+ };
vi) Pin configuration nodes
+ NOTE: pin configuration nodes are obsolete. Usually, their existance
+ is an evidence of the firmware shortcomings. Such fixups are
+ better handled by the Linux board file, not the device tree.
+
Required properties:
- linux,phandle : phandle of this node; likely referenced by a QE
device.
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index fdce10c..50199cf 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -271,6 +271,8 @@ config QUICC_ENGINE
bool
select PPC_LIB_RHEAP
select CRC32
+ select GENERIC_GPIO
+ select HAVE_GPIO_LIB
help
The QUICC Engine (QE) is a new generation of communications
coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index aef893b..dffb44a 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -20,9 +20,11 @@
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/ioport.h>
+#include <linux/spinlock.h>
#include <asm/io.h>
#include <asm/prom.h>
+#include <asm/gpio.h>
#include <sysdev/fsl_soc.h>
#undef DEBUG
@@ -213,6 +215,137 @@ int par_io_of_config(struct device_node *np)
}
EXPORT_SYMBOL(par_io_of_config);
+/*
+ * GPIO LIB API implementation
+ */
+
+struct qe_gpio_chip {
+ struct of_mm_gpio_chip mm_gc;
+ spinlock_t lock;
+
+ /* shadowed data register to clear/set bits safely */
+ u32 cpdata;
+};
+
+#define to_qe_gpio_chip(x) container_of(x, struct qe_gpio_chip, mm_gc)
+
+static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+ struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
+ struct port_regs __iomem *regs = mm_gc->regs;
+
+ qe_gc->cpdata = in_be32(®s->cpdata);
+}
+
+static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct port_regs __iomem *regs = mm_gc->regs;
+ u32 pin_mask;
+
+ /* calculate pin location */
+ pin_mask = (u32) (1 << (NUM_OF_PINS - 1 - gpio));
+
+ return !!(in_be32(®s->cpdata) & pin_mask);
+}
+
+static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
+ struct port_regs __iomem *regs = mm_gc->regs;
+ unsigned long flags;
+ u32 pin_mask = 1 << (NUM_OF_PINS - 1 - gpio);
+
+ spin_lock_irqsave(&qe_gc->lock, flags);
+
+ if (val)
+ qe_gc->cpdata |= pin_mask;
+ else
+ qe_gc->cpdata &= ~pin_mask;
+
+ out_be32(®s->cpdata, qe_gc->cpdata);
+
+ spin_unlock_irqrestore(&qe_gc->lock, flags);
+}
+
+static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&qe_gc->lock, flags);
+
+ __par_io_config_pin(mm_gc->regs, gpio, 2, 0, 0, 0);
+
+ spin_unlock_irqrestore(&qe_gc->lock, flags);
+
+ return 0;
+}
+
+static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&qe_gc->lock, flags);
+
+ __par_io_config_pin(mm_gc->regs, gpio, 1, 0, 0, 0);
+
+ spin_unlock_irqrestore(&qe_gc->lock, flags);
+
+ qe_gpio_set(gc, gpio, val);
+
+ return 0;
+}
+
+static int __init qe_add_gpiochips(void)
+{
+ int ret;
+ struct device_node *np;
+
+ for_each_compatible_node(np, NULL, "fsl,qe-pario-bank") {
+ struct qe_gpio_chip *qe_gc;
+ struct of_mm_gpio_chip *mm_gc;
+ struct of_gpio_chip *of_gc;
+ struct gpio_chip *gc;
+
+ qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
+ if (!qe_gc) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ spin_lock_init(&qe_gc->lock);
+
+ mm_gc = &qe_gc->mm_gc;
+ of_gc = &mm_gc->of_gc;
+ gc = &of_gc->gc;
+
+ mm_gc->save_regs = qe_gpio_save_regs;
+ of_gc->gpio_cells = 2;
+ gc->ngpio = NUM_OF_PINS;
+ gc->direction_input = qe_gpio_dir_in;
+ gc->direction_output = qe_gpio_dir_out;
+ gc->get = qe_gpio_get;
+ gc->set = qe_gpio_set;
+ gc->set_dedicated = qe_gpio_set_dedicated;
+
+ ret = of_mm_gpiochip_add(np, mm_gc);
+ if (ret)
+ goto err;
+ }
+
+ return 0;
+err:
+ pr_err("%s: registration failed with status %d\n", np->full_name, ret);
+ of_node_put(np);
+ return ret;
+}
+arch_initcall(qe_add_gpiochips);
+
#ifdef DEBUG
static void dump_par_io(void)
{
--
1.5.2.2
^ permalink raw reply related
* [PATCH 04/11] [RFC][GPIOLIB] add gpio_set_dedicated() routine
From: Anton Vorontsov @ 2008-02-03 17:10 UTC (permalink / raw)
To: linuxppc-dev; +Cc: David Brownell
In-Reply-To: <20080203170820.GA18520@localhost.localdomain>
This routine sets dedicated functions of the GPIO pin.
---
Hello David,
Yes, I did read Documentation/gpio.txt's last chapter. :-)
...that says:
One of the biggest things these conventions omit is pin multiplexing,
since this is highly chip-specific and nonportable.
Let me counter: "chip-specific" is a weak argument, IMO. Imagine some
GPIO controller that can't do inputs, or outputs. First one will be
still suitable for gpio_leds, second one will be suitable for gpio_keys.
Or... gpio_to_irq/irq_to_gpio. More than chip-specific, isn't it?
Some GPIO controllers might provide interrupt sources, some might
not.
Or let's put it completely different way: IRQs, they are
chip specific too, some of them can't do EDGE_FALLING or
EDGE_RISING. But these flags still exists for the IRQs,
and drivers use them.
The same for GPIO pin multiplexing: some drivers aren't aware of
GPIO multiplexing, but some are.
With the device tree/OpenFirmware environment it's quite easy
to pass "dedicated functions" flags to the drivers. Platform device
drivers also may accept functions via platform data (or better yet
via IORESOURCE_GPIO and its flags -- yet to be implemented, of course).
Today, there is a driver for the Freescale USB Host Controller, that
needs switching some pins to GPIOs for short period, and then back to
the dedicated functions...
So, down below is the proposal patch: gpio_set_dedicated() routine.
There are other options, tough. But I don't like them:
- Don't use GPIO API for that driver. Bad idea, this driver
completely fits in the current GPIO use cases, except
set_dedicated()...
- Export "gpio_chips", thus we can implement arch-specific functions.
Bad idea, we'll smear "GPIO LIB" across the whole kernel.
- Implement gpio_chip->free() and gpio_chip->request() callbacks,
so controllers could restore pin's functions in the ->free().
Then drivers could do:
gpio_request();
gpio_direction_...();
...do some GPIO work...
gpio_free(); /* and controller will restore dedicated function */
Well, this is viable option. But expensive and it isn't good
idea to release gpios when driver already probed (think someone
might request it meantime). Still viable for my case, though.
Oh, there is no way to pass "func" argument also.
- Another option?
Thanks!
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
drivers/gpio/gpiolib.c | 13 +++++++++++++
include/asm-generic/gpio.h | 3 +++
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index d8db2f8..de6e765 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -440,6 +440,19 @@ void gpio_set_value_cansleep(unsigned gpio, int value)
}
EXPORT_SYMBOL_GPL(gpio_set_value_cansleep);
+int gpio_set_dedicated(unsigned gpio, int func)
+{
+ struct gpio_chip *chip;
+
+ might_sleep_if(extra_checks);
+ chip = gpio_to_chip(gpio);
+ if (chip->set_dedicated)
+ return chip->set_dedicated(chip, gpio - chip->base, func);
+
+ return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(gpio_set_dedicated);
+
#ifdef CONFIG_DEBUG_FS
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 806b86c..cfbeea8 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -61,6 +61,8 @@ struct gpio_chip {
unsigned offset, int value);
void (*set)(struct gpio_chip *chip,
unsigned offset, int value);
+ int (*set_dedicated)(struct gpio_chip *chip,
+ unsigned offset, int func);
void (*dbg_show)(struct seq_file *s,
struct gpio_chip *chip);
int base;
@@ -88,6 +90,7 @@ extern int gpio_direction_output(unsigned gpio, int value);
extern int gpio_get_value_cansleep(unsigned gpio);
extern void gpio_set_value_cansleep(unsigned gpio, int value);
+extern int gpio_set_dedicated(unsigned gpio, int func);
/* A platform's <asm/gpio.h> code may want to inline the I/O calls when
* the GPIO is constant and refers to some always-present controller,
--
1.5.2.2
^ permalink raw reply related
* [PATCH 05/11] [POWERPC] qe_lib: support for gpio_set_dedicated
From: Anton Vorontsov @ 2008-02-03 17:10 UTC (permalink / raw)
To: linuxppc-dev; +Cc: David Brownell
In-Reply-To: <20080203170820.GA18520@localhost.localdomain>
So far we just restore pre-set dedicated function of the pin.
No need for anything else, so far.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/sysdev/qe_lib/qe_io.c | 46 ++++++++++++++++++++++++++++++++++++
1 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index dffb44a..abe02e0 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -225,6 +225,9 @@ struct qe_gpio_chip {
/* shadowed data register to clear/set bits safely */
u32 cpdata;
+
+ /* saved_regs used to restore dedicated functions */
+ struct port_regs saved_regs;
};
#define to_qe_gpio_chip(x) container_of(x, struct qe_gpio_chip, mm_gc)
@@ -235,6 +238,12 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
struct port_regs __iomem *regs = mm_gc->regs;
qe_gc->cpdata = in_be32(®s->cpdata);
+ qe_gc->saved_regs.cpdata = qe_gc->cpdata;
+ qe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1);
+ qe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2);
+ qe_gc->saved_regs.cppar1 = in_be32(®s->cppar1);
+ qe_gc->saved_regs.cppar2 = in_be32(®s->cppar2);
+ qe_gc->saved_regs.cpodr = in_be32(®s->cpodr);
}
static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -301,6 +310,43 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
return 0;
}
+static int qe_gpio_set_dedicated(struct gpio_chip *gc, unsigned int gpio,
+ int func)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
+ struct port_regs __iomem *regs = mm_gc->regs;
+ struct port_regs *sregs = &qe_gc->saved_regs;
+ unsigned long flags;
+ u32 mask1 = 1 << (NUM_OF_PINS - (gpio + 1));
+ u32 mask2 = 0x3 << (NUM_OF_PINS - (gpio % (NUM_OF_PINS / 2) + 1) * 2);
+ bool second_reg = gpio > (NUM_OF_PINS / 2) - 1;
+
+ spin_lock_irqsave(&qe_gc->lock, flags);
+
+ if (second_reg)
+ clrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);
+ else
+ clrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);
+
+ if (second_reg)
+ clrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2);
+ else
+ clrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2);
+
+ if (sregs->cpdata & mask1)
+ qe_gc->cpdata |= mask1;
+ else
+ qe_gc->cpdata &= ~mask1;
+
+ out_be32(®s->cpdata, qe_gc->cpdata);
+ clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
+
+ spin_unlock_irqrestore(&qe_gc->lock, flags);
+
+ return 0;
+}
+
static int __init qe_add_gpiochips(void)
{
int ret;
--
1.5.2.2
^ permalink raw reply related
* [PATCH 06/11] [POWERPC] qe_lib: implement qe_muram_offset
From: Anton Vorontsov @ 2008-02-03 17:10 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20080203170820.GA18520@localhost.localdomain>
qe_muram_offset is the reverse of the qe_muram_addr.
Also, move qe_muram_addr to the qe.h header.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/sysdev/qe_lib/qe.c | 6 ------
include/asm-powerpc/qe.h | 11 ++++++++++-
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 5ef844d..0757def 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -415,12 +415,6 @@ void qe_muram_dump(void)
}
EXPORT_SYMBOL(qe_muram_dump);
-void *qe_muram_addr(unsigned long offset)
-{
- return (void *)&qe_immr->muram[offset];
-}
-EXPORT_SYMBOL(qe_muram_addr);
-
/* The maximum number of RISCs we support */
#define MAX_QE_RISC 2
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 430dc77..df20f73 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -92,7 +92,16 @@ unsigned long qe_muram_alloc(int size, int align);
int qe_muram_free(unsigned long offset);
unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
void qe_muram_dump(void);
-void *qe_muram_addr(unsigned long offset);
+
+static inline void *qe_muram_addr(unsigned long offset)
+{
+ return (void *)&qe_immr->muram[offset];
+}
+
+static inline unsigned long qe_muram_offset(void *addr)
+{
+ return addr - (void *)qe_immr->muram;
+}
/* Structure that defines QE firmware binary files.
*
--
1.5.2.2
^ permalink raw reply related
* [PATCH 07/11] [POWERPC] qe_lib: export qe_get_brg_clk
From: Anton Vorontsov @ 2008-02-03 17:10 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20080203170820.GA18520@localhost.localdomain>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/sysdev/qe_lib/qe.c | 5 +++--
include/asm-powerpc/qe.h | 1 +
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 0757def..a0d0ec0 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -155,7 +155,7 @@ EXPORT_SYMBOL(qe_issue_cmd);
*/
static unsigned int brg_clk = 0;
-unsigned int get_brg_clk(void)
+unsigned int qe_get_brg_clk(void)
{
struct device_node *qe;
unsigned int size;
@@ -180,6 +180,7 @@ unsigned int get_brg_clk(void)
return brg_clk;
}
+EXPORT_SYMBOL(qe_get_brg_clk);
/* Program the BRG to the given sampling rate and multiplier
*
@@ -197,7 +198,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
if ((brg < QE_BRG1) || (brg > QE_BRG16))
return -EINVAL;
- divisor = get_brg_clk() / (rate * multiplier);
+ divisor = qe_get_brg_clk() / (rate * multiplier);
if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
div16 = QE_BRGC_DIV16;
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index df20f73..3487f50 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -85,6 +85,7 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
/* QE internal API */
int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
enum qe_clock qe_clock_source(const char *source);
+unsigned int qe_get_brg_clk(void);
int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
int qe_get_snum(void);
void qe_put_snum(u8 snum);
--
1.5.2.2
^ permalink raw reply related
* [PATCH 08/11] [POWERPC] qe_lib: implement QE GTM support
From: Anton Vorontsov @ 2008-02-03 17:10 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20080203170820.GA18520@localhost.localdomain>
GTM stands for General-purpose Timers Module and able to generate
timer{1,2,3,4} interrupts.
There are several limitations in this support:
1. Cascaded (32 bit) timers unimplemented (1-2, 3-4).
This is straightforward to implement when needed, two timers should
be marked as "requested" and configured as appropriate.
2. Super-cascaded (64 bit) timers unimplemented (1-2-3-4).
This is also straightforward to implement when needed, all timers
should be marked as "requested" and configured as appropriate.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/sysdev/qe_lib/Kconfig | 4 +
arch/powerpc/sysdev/qe_lib/Makefile | 1 +
arch/powerpc/sysdev/qe_lib/gtm.c | 204 +++++++++++++++++++++++++++++++++++
include/asm-powerpc/immap_qe.h | 7 +-
include/asm-powerpc/qe.h | 22 ++++
5 files changed, 236 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/sysdev/qe_lib/gtm.c
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
index adc6621..3966151 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -20,3 +20,7 @@ config UCC
bool
default y if UCC_FAST || UCC_SLOW
+config QE_GTM
+ bool
+ help
+ QE General-Purpose Timers Module support
diff --git a/arch/powerpc/sysdev/qe_lib/Makefile b/arch/powerpc/sysdev/qe_lib/Makefile
index 874fe1a..3297a52 100644
--- a/arch/powerpc/sysdev/qe_lib/Makefile
+++ b/arch/powerpc/sysdev/qe_lib/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_ic.o qe_io.o
obj-$(CONFIG_UCC) += ucc.o
obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
obj-$(CONFIG_UCC_FAST) += ucc_fast.o
+obj-$(CONFIG_QE_GTM) += gtm.o
diff --git a/arch/powerpc/sysdev/qe_lib/gtm.c b/arch/powerpc/sysdev/qe_lib/gtm.c
new file mode 100644
index 0000000..8f5b422
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/gtm.c
@@ -0,0 +1,204 @@
+/*
+ * QE General-Purpose Timers Module
+ *
+ * Copyright (c) Freescale Semicondutor, Inc. 2006.
+ * Shlomi Gridish <gridish@freescale.com>
+ * Jerry Huang <Chang-Ming.Huang@freescale.com>
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/spinlock.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+struct gtm_timer {
+ unsigned int irq;
+ bool requested;
+
+ u8 __iomem *gtcfr;
+ u16 __iomem *gtmdr;
+ u16 __iomem *gtpsr;
+ u16 __iomem *gtcnr;
+ u16 __iomem *gtrfr;
+ u16 __iomem *gtevr;
+};
+
+static struct gtm_timer timers[4];
+static struct qe_timers __iomem *qet;
+static spinlock_t gtm_lock = __SPIN_LOCK_UNLOCKED(gtm_lock);
+
+static int __init qe_init_gtm(void)
+{
+ struct device_node *gtm;
+ int i;
+
+ gtm = of_find_compatible_node(NULL, NULL, "fsl,qe-gtm");
+ if (!gtm)
+ return -ENODEV;
+
+ for (i = 0; i < 3; i++) {
+ int ret;
+ struct resource irq;
+
+ ret = of_irq_to_resource(gtm, i, &irq);
+ if (ret == NO_IRQ) {
+ pr_err("%s: not enough interrupts specified\n",
+ gtm->full_name);
+ of_node_put(gtm);
+ return -EINVAL;
+ }
+ timers[i].irq = irq.start;
+ }
+
+ qet = of_iomap(gtm, 0);
+ of_node_put(gtm);
+ if (!qet) {
+ pr_err("%s: unable to iomap registers\n", gtm->full_name);
+ return -EINVAL;
+ }
+
+ /*
+ * Yeah, I don't like this either, but timers' registers a bit messed,
+ * so we have to provide shortcuts to write timer independent code.
+ */
+ timers[0].gtcfr = &qet->gtcfr1;
+ timers[0].gtmdr = &qet->gtmdr1;
+ timers[0].gtpsr = &qet->gtpsr1;
+ timers[0].gtcnr = &qet->gtcnr1;
+ timers[0].gtrfr = &qet->gtrfr1;
+ timers[0].gtevr = &qet->gtevr1;
+
+ timers[1].gtcfr = &qet->gtcfr1;
+ timers[1].gtmdr = &qet->gtmdr2;
+ timers[1].gtpsr = &qet->gtpsr2;
+ timers[1].gtcnr = &qet->gtcnr2;
+ timers[1].gtrfr = &qet->gtrfr2;
+ timers[1].gtevr = &qet->gtevr2;
+
+ timers[2].gtcfr = &qet->gtcfr2;
+ timers[2].gtmdr = &qet->gtmdr3;
+ timers[2].gtpsr = &qet->gtpsr3;
+ timers[2].gtcnr = &qet->gtcnr3;
+ timers[2].gtrfr = &qet->gtrfr3;
+ timers[2].gtevr = &qet->gtevr3;
+
+ timers[3].gtcfr = &qet->gtcfr2;
+ timers[3].gtmdr = &qet->gtmdr4;
+ timers[3].gtpsr = &qet->gtpsr4;
+ timers[3].gtcnr = &qet->gtcnr4;
+ timers[3].gtrfr = &qet->gtrfr4;
+ timers[3].gtevr = &qet->gtevr4;
+
+ return 0;
+}
+arch_initcall(qe_init_gtm);
+
+int qe_get_timer(int width, unsigned int *irq)
+{
+ int i;
+
+ BUG_ON(!irq);
+ if (!qet)
+ return -ENODEV;
+ if (width != 16)
+ return -ENOSYS;
+
+ spin_lock_irq(>m_lock);
+
+ for (i = 0; i < 3; i++) {
+ if (!timers[i].requested) {
+ timers[i].requested = true;
+ *irq = timers[i].irq;
+ return i;
+ }
+ }
+
+ spin_unlock_irq(>m_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(qe_get_timer);
+
+void qe_put_timer(int num)
+{
+ spin_lock_irq(>m_lock);
+
+ timers[num].requested = false;
+
+ spin_unlock_irq(>m_lock);
+}
+EXPORT_SYMBOL(qe_put_timer);
+
+int qe_reset_ref_timer_16(int num, unsigned int hz, u16 ref)
+{
+ struct gtm_timer *tmr = &timers[num];
+ unsigned long flags;
+ unsigned int prescaler;
+ u8 psr;
+ u8 sps;
+
+ prescaler = qe_get_brg_clk() / hz;
+
+ /*
+ * We have two 8 bit prescalers -- primary and secondary (psr, sps),
+ * so total prescale value is (psr + 1) * (sps + 1).
+ */
+ if (prescaler > 256 * 256) {
+ return -EINVAL;
+ } else if (prescaler > 256) {
+ psr = 256 - 1;
+ sps = prescaler / 256 - 1;
+ } else {
+ psr = prescaler - 1;
+ sps = 1 - 1;
+ }
+
+ spin_lock_irqsave(>m_lock, flags);
+
+ /*
+ * Properly reset timers: stop, reset, set up prescalers, reference
+ * value and clear event register.
+ */
+ clrsetbits_8(tmr->gtcfr, ~(QE_GTCFR_STP(num) | QE_GTCFR_RST(num)),
+ QE_GTCFR_STP(num) | QE_GTCFR_RST(num));
+
+ setbits8(tmr->gtcfr, QE_GTCFR_STP(num));
+
+ out_be16(tmr->gtpsr, psr);
+ setbits16(tmr->gtmdr, QE_GTMDR_SPS(sps) | QE_GTMDR_ICLK_QERF |
+ QE_GTMDR_ORI);
+ out_be16(tmr->gtcnr, 0);
+ out_be16(tmr->gtrfr, ref);
+ out_be16(tmr->gtevr, 0xFFFF);
+
+ /* Let it be. */
+ clrbits8(tmr->gtcfr, QE_GTCFR_STP(num));
+
+ spin_unlock_irqrestore(>m_lock, flags);
+
+ return 0;
+}
+EXPORT_SYMBOL(qe_reset_ref_timer_16);
+
+void qe_stop_timer(int num)
+{
+ struct gtm_timer *tmr = &timers[num];
+ unsigned long flags;
+
+ spin_lock_irqsave(>m_lock, flags);
+
+ setbits8(tmr->gtcfr, QE_GTCFR_STP(num));
+
+ spin_unlock_irqrestore(>m_lock, flags);
+}
+EXPORT_SYMBOL(qe_stop_timer);
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index 82a4526..cfa0d86 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -128,8 +128,11 @@ struct qe_timers {
__be16 gtevr2; /* Timer 2 event register */
__be16 gtevr3; /* Timer 3 event register */
__be16 gtevr4; /* Timer 4 event register */
- __be16 gtps; /* Timer 1 prescale register */
- u8 res2[0x46];
+ __be16 gtpsr1; /* Timer 1 prescale register */
+ __be16 gtpsr2; /* Timer 2 prescale register */
+ __be16 gtpsr3; /* Timer 3 prescale register */
+ __be16 gtpsr4; /* Timer 4 prescale register */
+ u8 res2[0x40];
} __attribute__ ((packed));
/* BRG */
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 3487f50..3664aaa 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -153,6 +153,12 @@ struct qe_firmware_info {
/* Upload a firmware to the QE */
int qe_upload_firmware(const struct qe_firmware *firmware);
+/* QE GTM */
+extern int qe_get_timer(int width, unsigned int *irq);
+extern void qe_put_timer(int num);
+extern int qe_reset_ref_timer_16(int num, unsigned int hz, u16 ref);
+extern void qe_stop_timer(int num);
+
/* Obtain information on the uploaded firmware */
struct qe_firmware_info *qe_get_firmware_info(void);
@@ -255,6 +261,11 @@ enum comm_dir {
#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
#define QE_CMXGCR_USBCS 0x0000000f
+#define QE_CMXGCR_TIMERCS 0x00300000
+#define QE_CMXGCR_TIMERCS_CLK11 0x00000000
+#define QE_CMXGCR_TIMERCS_CLK12 0x00100000
+#define QE_CMXGCR_TIMERCS_BRG11 0x00300000
+
/* QE CECR Commands.
*/
#define QE_CR_FLG 0x00010000
@@ -367,6 +378,17 @@ enum comm_dir {
#define QE_GTCFR1_STP1 0x02
#define QE_GTCFR1_RST1 0x01
+#define QE_GTCFR_STP(x) ((x) & 1 ? 1 << 5 : 1 << 1)
+#define QE_GTCFR_RST(x) ((x) & 1 ? 1 << 4 : 1 << 0)
+
+#define QE_GTMDR_ICLK_MASK (3 << 1)
+#define QE_GTMDR_ICLK_ICAS (0 << 1)
+#define QE_GTMDR_ICLK_QERF (1 << 1)
+#define QE_GTMDR_ICLK_SLGO (2 << 1)
+#define QE_GTMDR_ORI (1 << 4)
+#define QE_GTMDR_SPS_MASK (0xFF << 8)
+#define QE_GTMDR_SPS(x) ((x) << 8)
+
/* SDMA registers */
#define QE_SDSR_BER1 0x02000000
#define QE_SDSR_BER2 0x01000000
--
1.5.2.2
^ permalink raw reply related
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