* Re: [PATCH] PowerPC 44x: use machine_device_initcall() instead of device_initcall() for warp_nand
From: Grant Likely @ 2008-04-04 18:49 UTC (permalink / raw)
To: Valentine Barshak; +Cc: linuxppc-dev
In-Reply-To: <20080404182437.GA18185@ru.mvista.com>
On Fri, Apr 4, 2008 at 12:24 PM, Valentine Barshak
<vbarshak@ru.mvista.com> wrote:
> With a multiplatform kernel, once built we always have warp_setup_nand_flash() called
> and NDFC probed, no matter what machine we actually run on. This potentially can cause
> problems (such as kernel crash), since NDFC is probed at a warp-predefined address.
> Using machine_device_initcall() NAND devices are registered if we run on a warp only.
>
> Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
> ---
> arch/powerpc/platforms/44x/warp-nand.c | 3 ++-
> 1 files changed, 2 insertions(+), 1 deletion(-)
>
> --- linux-2.6.orig/arch/powerpc/platforms/44x/warp-nand.c 2008-03-06 14:39:46.000000000 +0300
> +++ linux-2.6.bld/arch/powerpc/platforms/44x/warp-nand.c 2008-04-04 22:03:36.000000000 +0400
> @@ -11,6 +11,7 @@
> #include <linux/mtd/partitions.h>
> #include <linux/mtd/nand.h>
> #include <linux/mtd/ndfc.h>
> +#include <asm/machdep.h>
>
> #ifdef CONFIG_MTD_NAND_NDFC
>
> @@ -100,6 +101,6 @@ static int warp_setup_nand_flash(void)
>
> return 0;
> }
> -device_initcall(warp_setup_nand_flash);
> +machine_device_initcall(warp, warp_setup_nand_flash);
>
> #endif
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH] PowerPC: MPIC ack interrupts at mpic_teardown_this_cpu()
From: Segher Boessenkool @ 2008-04-04 18:55 UTC (permalink / raw)
To: Olof Johansson; +Cc: linuxppc-dev
In-Reply-To: <20080404180333.GB26693@lixom.net>
>> platforms/maple/setup.c and platforms/powermac/pic.c use
>> MPIC_WANTS_RESET.
>> Is there a reason why we don't do that on every MPIC? If there is
>> such
>> a reason, the default should be to reset, only pseries and chrp and
>> cell
>> and now pasemi do not use it. It's the only sane way to get an MPIC
>> into
>> a sane known state starting from <whatever> state.
>
> I used to have the reset there on pasemi but due to some other issues I
> ended up taking it out.
>
> It's not like doing a final EOI is a big deal, I really don't see why
> there's hassle about this patch.
The patch is fine, don't get me wrong. I'm just saying MPIC_WANTS_RESET
should be the default since pretty much everything wants it. The few
platforms that don't can document why; with the current code, we cannot
see if you just forgot it or not.
Segher
^ permalink raw reply
* Re: [PATCH/RFC] via-pmu: remove mdelays from suspend/resume code
From: Johannes Berg @ 2008-04-04 19:21 UTC (permalink / raw)
To: Brad Boyer; +Cc: linuxppc-dev list
In-Reply-To: <20080404172006.GA13980@cynthia.pants.nu>
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On Fri, 2008-04-04 at 10:20 -0700, Brad Boyer wrote:
> On Thu, Apr 03, 2008 at 05:44:44PM +0200, Johannes Berg wrote:
> > I don't see a reason for either of those mdelay()s, is there any? Works
> > fine for me without them...
>
> Which hardware revisions did you test? I suspect the mdelay calls were
> added to work around timing issues in one of the older PMU chips. Some
> of them are very timing sensitive, and sleep in particular is basically
> a pile of steps that got hacked until they worked on older systems.
Mine's a 5,6 powerbook with PMU firmware 0x0c. The mdelay(100) seems
fairly large though for a point where we're out of pmu code already, and
the other one doesn't really seem too pmu related anyway. In any case,
just wanted to float that, don't see a particular need for it.
johannes
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^ permalink raw reply
* Re: [PATCH] PowerPC: MPIC ack interrupts at mpic_teardown_this_cpu()
From: Olof Johansson @ 2008-04-04 19:39 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev
In-Reply-To: <63defd942bd57ca87cb17334832b615c@kernel.crashing.org>
On Fri, Apr 04, 2008 at 08:55:01PM +0200, Segher Boessenkool wrote:
>>> platforms/maple/setup.c and platforms/powermac/pic.c use
>>> MPIC_WANTS_RESET.
>>> Is there a reason why we don't do that on every MPIC? If there is
>>> such
>>> a reason, the default should be to reset, only pseries and chrp and
>>> cell
>>> and now pasemi do not use it. It's the only sane way to get an MPIC
>>> into
>>> a sane known state starting from <whatever> state.
>>
>> I used to have the reset there on pasemi but due to some other issues I
>> ended up taking it out.
>>
>> It's not like doing a final EOI is a big deal, I really don't see why
>> there's hassle about this patch.
>
> The patch is fine, don't get me wrong. I'm just saying MPIC_WANTS_RESET
> should be the default since pretty much everything wants it. The few
> platforms that don't can document why; with the current code, we cannot
> see if you just forgot it or not.
It was documented in the changeset, see de0c74e7f98d8a06b784e120103eb388da8194f6.
But yeah, that's hard to tell at some point later in time, a short
comment by the call could be useful. I'll add one next time I touch that
code.
-Olof
^ permalink raw reply
* Re: [RFC/PATCH] powerpc: Add irqtrace support to 32-bit powerpc
From: Johannes Berg @ 2008-04-04 19:33 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev, Benjamin Herrenschmidt
In-Reply-To: <1207145738.3957.2.camel@johannes.berg>
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On Wed, 2008-04-02 at 16:15 +0200, Johannes Berg wrote:
> On Fri, 2008-02-01 at 12:50 -0700, Dale Farnsworth wrote:
> > This adds the low level irq tracing hooks for 32-bit powerpc.
> > This patch applies on top of Benjamin Herrenschmidt's patch that
> > provides similar support for 64-bit powerpc. See
> > <http://ozlabs.org/pipermail/linuxppc-dev/2007-October/044361.html>
> >
> > It seems to work on my prpmc2800 board with a ppc7447.
>
> At first it appears to work on my powerbook (with Ben's latest version
> of the 64-bit patch), but then it seems to cause random corruption, I've
> had a crash in the ext3 code and one in console_callback(), both of
> which I cannot otherwise explain.
FWIW, same kernel without the patch works fine.
johannes
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^ permalink raw reply
* Re: [PATCH/RFC] via-pmu: remove mdelays from suspend/resume code
From: Brad Boyer @ 2008-04-04 17:20 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev list
In-Reply-To: <1207237484.3797.2.camel@johannes.berg>
On Thu, Apr 03, 2008 at 05:44:44PM +0200, Johannes Berg wrote:
> I don't see a reason for either of those mdelay()s, is there any? Works
> fine for me without them...
Which hardware revisions did you test? I suspect the mdelay calls were
added to work around timing issues in one of the older PMU chips. Some
of them are very timing sensitive, and sleep in particular is basically
a pile of steps that got hacked until they worked on older systems.
Brad Boyer
flar@allandria.com
^ permalink raw reply
* Re: [PATCH/RFC] via-pmu: remove mdelays from suspend/resume code
From: Benjamin Herrenschmidt @ 2008-04-04 21:16 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev list
In-Reply-To: <1207336864.19189.74.camel@johannes.berg>
On Fri, 2008-04-04 at 21:21 +0200, Johannes Berg wrote:
> On Fri, 2008-04-04 at 10:20 -0700, Brad Boyer wrote:
> > On Thu, Apr 03, 2008 at 05:44:44PM +0200, Johannes Berg wrote:
> > > I don't see a reason for either of those mdelay()s, is there any? Works
> > > fine for me without them...
> >
> > Which hardware revisions did you test? I suspect the mdelay calls were
> > added to work around timing issues in one of the older PMU chips. Some
> > of them are very timing sensitive, and sleep in particular is basically
> > a pile of steps that got hacked until they worked on older systems.
>
> Mine's a 5,6 powerbook with PMU firmware 0x0c. The mdelay(100) seems
> fairly large though for a point where we're out of pmu code already, and
> the other one doesn't really seem too pmu related anyway. In any case,
> just wanted to float that, don't see a particular need for it.
One of those was meant to let devices settle. The reason is that when
waking from sleep, a lot of HW on the mobo is actually powered up (it
was down during sleep). This delay comes from half paranoia / half
experience, and is meant to ensure all those chips got a chance to
settle and complete their power-on reset sequence before we start
banging all over the place.
Cheers,
Ben.
^ permalink raw reply
* Re: [RFC/PATCH] powerpc: Add irqtrace support to 32-bit powerpc
From: Dale Farnsworth @ 2008-04-04 21:29 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev, Benjamin Herrenschmidt
In-Reply-To: <1207337598.19189.77.camel@johannes.berg>
On Fri, Apr 04, 2008 at 09:33:18PM +0200, Johannes Berg wrote:
> On Wed, 2008-04-02 at 16:15 +0200, Johannes Berg wrote:
> > On Fri, 2008-02-01 at 12:50 -0700, Dale Farnsworth wrote:
> > > This adds the low level irq tracing hooks for 32-bit powerpc.
> > > This patch applies on top of Benjamin Herrenschmidt's patch that
> > > provides similar support for 64-bit powerpc. See
> > > <http://ozlabs.org/pipermail/linuxppc-dev/2007-October/044361.html>
> > >
> > > It seems to work on my prpmc2800 board with a ppc7447.
> >
> > At first it appears to work on my powerbook (with Ben's latest version
> > of the 64-bit patch), but then it seems to cause random corruption, I've
> > had a crash in the ext3 code and one in console_callback(), both of
> > which I cannot otherwise explain.
>
> FWIW, same kernel without the patch works fine.
My apologies, Johannes. I made some unwarranted assumptions about
register usage in the lowest-level exception handlers. While it worked
on my 7447 board, I saw similar random failures on the 85xx (booke) system
I tried.
Thanks for testing this.
I'll follow up with a revised patch.
-Dale
^ permalink raw reply
* Re: [RFC/PATCH] powerpc: Add irqtrace support to 32-bit powerpc
From: Johannes Berg @ 2008-04-04 21:35 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev, Benjamin Herrenschmidt
In-Reply-To: <20080404212952.GA15454@farnsworth.org>
[-- Attachment #1: Type: text/plain, Size: 444 bytes --]
> My apologies, Johannes. I made some unwarranted assumptions about
> register usage in the lowest-level exception handlers. While it worked
> on my 7447 board, I saw similar random failures on the 85xx (booke) system
> I tried.
No harm done, just wanted to give it a try and let you know it failed.
> Thanks for testing this.
>
> I'll follow up with a revised patch.
Great, thanks! I'll test that as well then.
johannes
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^ permalink raw reply
* [PATCH v2] powerpc: Add irqtrace support for 32-bit powerpc
From: Dale Farnsworth @ 2008-04-04 21:39 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Johannes Berg
Add the low level irq tracing hooks for 32-bit powerpc needed
to enable full lockdep functionality.
Dale Farnsworth <dale@farnsworth.org>
---
This patch applies on top of Benjamin Herrenschmidt's lockdep patch for
64-bit powerpc. (http://patchwork.ozlabs.org/linuxppc/patch?id=17673)
This version takes care to save and restore *all* the volatile registers
around the call to trace_hardirqs_off in transfer_to_handler, and should
fix the anomalies seen by Johannes Berg. I've tested on 7447- and 8548-
based boards.
arch/powerpc/Kconfig | 1 -
arch/powerpc/kernel/entry_32.S | 90 ++++++++++++++++++++++++++++++++++++++-
arch/powerpc/kernel/setup_32.c | 2 +
include/asm-powerpc/hw_irq.h | 20 ++++----
include/asm-powerpc/system.h | 3 +-
5 files changed, 100 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 6dbf123..99d8e18 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -55,7 +55,6 @@ config STACKTRACE_SUPPORT
config TRACE_IRQFLAGS_SUPPORT
bool
- depends on PPC64
default y
config LOCKDEP_SUPPORT
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 69a91bd..bd3ce0f 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -144,6 +144,47 @@ transfer_to_handler:
.globl transfer_to_handler_cont
transfer_to_handler_cont:
3:
+#ifdef CONFIG_TRACE_IRQFLAGS
+ lis r11,reenable_mmu@h
+ ori r11,r11,reenable_mmu@l
+ mtspr SPRN_SRR0,r11
+ mtspr SPRN_SRR1,r10
+ SYNC
+ RFI
+reenable_mmu: /* re-enable mmu so we can */
+ mflr r9 /* call C code, if necessary */
+ mfmsr r10
+ lwz r11,_MSR(r1)
+ xor r10,r10,r11
+ andi. r10,r10,MSR_EE /* Did EE change? */
+ beq 1f
+ stwu r1,-48(r1) /* Yes, it must have been cleared */
+ stw r9,52(r1)
+ stw r0,16(r1)
+ stw r3,20(r1)
+ stw r4,24(r1)
+ stw r5,28(r1)
+ stw r6,32(r1)
+ stw r7,36(r1)
+ stw r8,40(r1)
+ bl trace_hardirqs_off
+ lwz r0,16(r1)
+ lwz r3,20(r1)
+ lwz r4,24(r1)
+ lwz r5,28(r1)
+ lwz r6,32(r1)
+ lwz r7,36(r1)
+ lwz r8,40(r1)
+ lwz r9,52(r1)
+ addi r1,r1,48
+1:
+ tovirt(r9,r9)
+ lwz r11,0(r9) /* virtual address of handler */
+ lwz r9,4(r9) /* where to go when done */
+ mtctr r11
+ mtlr r9
+ bctr /* jump to handler */
+#else /* CONFIG_TRACE_IRQFLAGS */
mflr r9
lwz r11,0(r9) /* virtual address of handler */
lwz r9,4(r9) /* where to go when done */
@@ -152,6 +193,7 @@ transfer_to_handler_cont:
mtlr r9
SYNC
RFI /* jump to handler, enable MMU */
+#endif /* CONFIG_TRACE_IRQFLAGS */
#ifdef CONFIG_6xx
4: rlwinm r12,r12,0,~_TLF_NAPPING
@@ -220,12 +262,20 @@ ret_from_syscall:
#ifdef SHOW_SYSCALLS
bl do_show_syscall_exit
#endif
- mr r6,r3
rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
/* disable interrupts so current_thread_info()->flags can't change */
LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
SYNC
MTMSRD(r10)
+#ifdef CONFIG_TRACE_IRQFLAGS
+ stwu r1,-16(r1)
+ stw r3,12(r1)
+ bl trace_hardirqs_off
+ lwz r3,12(r1)
+ addi r1,r1,16
+ LOAD_MSR_KERNEL(r10,MSR_KERNEL)
+#endif
+ mr r6,r3
lwz r9,TI_FLAGS(r12)
li r8,-_LAST_ERRNO
andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
@@ -237,6 +287,13 @@ ret_from_syscall:
oris r11,r11,0x1000 /* Set SO bit in CR */
stw r11,_CCR(r1)
syscall_exit_cont:
+#ifdef CONFIG_TRACE_IRQFLAGS
+ stwu r1,-16(r1)
+ stw r3,12(r1)
+ bl trace_hardirqs_on
+ lwz r3,12(r1)
+ addi r1,r1,16
+#endif
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
/* If the process has its own DBCR0 value, load it up. The single
step bit tells us that dbcr0 should be loaded. */
@@ -337,7 +394,10 @@ syscall_exit_work:
4: /* Anything which requires enabling interrupts? */
andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
beq ret_from_except
-
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_on
+ LOAD_MSR_KERNEL(r10,MSR_KERNEL)
+#endif
/* Re-enable interrupts */
ori r10,r10,MSR_EE
SYNC
@@ -646,13 +706,22 @@ ret_from_except_full:
.globl ret_from_except
ret_from_except:
+#ifdef CONFIG_TRACE_IRQFLAGS
+ mfmsr r3
+#endif
/* Hard-disable interrupts so that current_thread_info()->flags
* can't change between when we test it and when we return
* from the interrupt. */
LOAD_MSR_KERNEL(r10,MSR_KERNEL)
SYNC /* Some chip revs have problems here... */
MTMSRD(r10) /* disable interrupts */
-
+#ifdef CONFIG_TRACE_IRQFLAGS
+ andi. r3,r3,MSR_EE
+ beq 1f /* verified */
+ bl trace_hardirqs_off
+ LOAD_MSR_KERNEL(r10,MSR_KERNEL)
+1:
+#endif
lwz r3,_MSR(r1) /* Returning to user mode? */
andi. r0,r3,MSR_PR
beq resume_kernel
@@ -709,6 +778,9 @@ restore:
stw r6,icache_44x_need_flush@l(r4)
1:
#endif /* CONFIG_44x */
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_on
+#endif
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
REST_4GPRS(3, r1)
@@ -900,6 +972,10 @@ do_work: /* r10 contains MSR_KERNEL here */
beq do_user_signal
do_resched: /* r10 contains MSR_KERNEL here */
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_on
+ LOAD_MSR_KERNEL(r10,MSR_KERNEL)
+#endif
ori r10,r10,MSR_EE
SYNC
MTMSRD(r10) /* hard-enable interrupts */
@@ -908,6 +984,10 @@ recheck:
LOAD_MSR_KERNEL(r10,MSR_KERNEL)
SYNC
MTMSRD(r10) /* disable interrupts */
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_off
+ LOAD_MSR_KERNEL(r10,MSR_KERNEL)
+#endif
rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
lwz r9,TI_FLAGS(r9)
andi. r0,r9,_TIF_NEED_RESCHED
@@ -915,6 +995,10 @@ recheck:
andi. r0,r9,_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK
beq restore_user
do_user_signal: /* r10 contains MSR_KERNEL here */
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_on
+ LOAD_MSR_KERNEL(r10,MSR_KERNEL)
+#endif
ori r10,r10,MSR_EE
SYNC
MTMSRD(r10) /* hard-enable interrupts */
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index cd870a8..725dd18 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -120,6 +120,8 @@ unsigned long __init early_init(unsigned long dt_ptr)
*/
void __init machine_init(unsigned long dt_ptr, unsigned long phys)
{
+ lockdep_init();
+
/* Enable early debugging if any specified (see udbg.h) */
udbg_early_init();
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
index ad8c9f7..a5f347a 100644
--- a/include/asm-powerpc/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -63,13 +63,13 @@ extern void iseries_handle_interrupts(void);
#if defined(CONFIG_BOOKE)
#define SET_MSR_EE(x) mtmsr(x)
-#define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
+#define raw_local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
#else
#define SET_MSR_EE(x) mtmsr(x)
-#define local_irq_restore(flags) mtmsr(flags)
+#define raw_local_irq_restore(flags) mtmsr(flags)
#endif
-static inline void local_irq_disable(void)
+static inline void raw_local_irq_disable(void)
{
#ifdef CONFIG_BOOKE
__asm__ __volatile__("wrteei 0": : :"memory");
@@ -81,7 +81,7 @@ static inline void local_irq_disable(void)
#endif
}
-static inline void local_irq_enable(void)
+static inline void raw_local_irq_enable(void)
{
#ifdef CONFIG_BOOKE
__asm__ __volatile__("wrteei 1": : :"memory");
@@ -93,7 +93,7 @@ static inline void local_irq_enable(void)
#endif
}
-static inline void local_irq_save_ptr(unsigned long *flags)
+static inline void raw_local_irq_save_ptr(unsigned long *flags)
{
unsigned long msr;
msr = mfmsr();
@@ -106,12 +106,12 @@ static inline void local_irq_save_ptr(unsigned long *flags)
__asm__ __volatile__("": : :"memory");
}
-#define local_save_flags(flags) ((flags) = mfmsr())
-#define local_irq_save(flags) local_irq_save_ptr(&flags)
-#define irqs_disabled() ((mfmsr() & MSR_EE) == 0)
+#define raw_local_save_flags(flags) ((flags) = mfmsr())
+#define raw_local_irq_save(flags) raw_local_irq_save_ptr(&flags)
+#define raw_irqs_disabled() ((mfmsr() & MSR_EE) == 0)
+#define raw_irqs_disabled_flags(flags) (((flags) & MSR_EE) == 0)
-#define hard_irq_enable() local_irq_enable()
-#define hard_irq_disable() local_irq_disable()
+#define hard_irq_disable() raw_local_irq_disable()
#endif /* CONFIG_PPC64 */
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index 29552ff..e040a48 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -5,8 +5,7 @@
#define _ASM_POWERPC_SYSTEM_H
#include <linux/kernel.h>
-
-#include <asm/hw_irq.h>
+#include <linux/irqflags.h>
/*
* Memory barrier.
--
1.5.4
^ permalink raw reply related
* RE: [PATCH 1/5] [v2][POWERPC] refactor dcr code
From: Stephen Neuendorffer @ 2008-04-04 22:02 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
In-Reply-To: <1206914576.10388.132.camel@pasglop>
Ben,
Any thoughts about device tree bindings for indirect DCR?
Steve
> -----Original Message-----
> From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> Sent: Sunday, March 30, 2008 3:03 PM
> To: Stephen Neuendorffer
> Cc: linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH 1/5] [v2][POWERPC] refactor dcr code
>=20
>=20
> On Fri, 2008-03-28 at 09:23 -0700, Stephen Neuendorffer wrote:
> > Previously, dcr support was configured at compile time to either
using
> > MMIO or native dcr instructions. Although this works for most
> > platforms, it fails on FPGA platforms:
> >
> > 1) Systems may include more than one dcr bus.
> > 2) Systems may be native dcr capable and still use memory mapped dcr
interface.
> >
> > This patch provides runtime support based on the device trees for
the
> > case where CONFIG_PPC_DCR_MMIO and CONFIG_PPC_DCR_NATIVE are both
> > selected. Previously, this was a poorly defined configuration,
which
> > happened to provide NATIVE support. The runtime selection is made
> > based on the dcr slave device having a 'dcr-access-method' attribute
> > in the device tree. If only one of the above options is selected,
> > then the code uses #defines to select only the used code in order to
> > avoid interoducing overhead in existing usage.
> >
> > Signed-off-by: Stephen Neuendorffer
<stephen.neuendorffer@xilinx.com>
>=20
> Looks good. Haven't had a chance to test it yet, but tentatively
>=20
> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>=20
> Initially, I thought about using function pointers but the if/else
will
> probably end up being more efficient. The only thing maybe to ponder
> is whether we could avoid the dcr-generic.h file completely, and have
> the generic wrappers be inline, though considering how slow DCRs are,
> it may not be that useful in practice and less clean...
>=20
> Cheers,
> Ben.
>=20
>=20
> > ---
> > arch/powerpc/sysdev/dcr.c | 91
++++++++++++++++++++++++++++++++-----
> > include/asm-powerpc/dcr-generic.h | 49 ++++++++++++++++++++
> > include/asm-powerpc/dcr-mmio.h | 20 +++++---
> > include/asm-powerpc/dcr-native.h | 16 ++++---
> > include/asm-powerpc/dcr.h | 36 ++++++++++++++-
> > 5 files changed, 186 insertions(+), 26 deletions(-)
> > create mode 100644 include/asm-powerpc/dcr-generic.h
> >
> > diff --git a/arch/powerpc/sysdev/dcr.c b/arch/powerpc/sysdev/dcr.c
> > index 437e48d..d3de0ff 100644
> > --- a/arch/powerpc/sysdev/dcr.c
> > +++ b/arch/powerpc/sysdev/dcr.c
> > @@ -23,6 +23,68 @@
> > #include <asm/prom.h>
> > #include <asm/dcr.h>
> >
> > +#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
> > +
> > +bool dcr_map_ok_generic(dcr_host_t host)
> > +{
> > + if (host.type =3D=3D INVALID)
> > + return 0;
> > + else if (host.type =3D=3D NATIVE)
> > + return dcr_map_ok_native(host.host.native);
> > + else
> > + return dcr_map_ok_mmio(host.host.mmio);
> > +}
> > +EXPORT_SYMBOL_GPL(dcr_map_ok_generic);
> > +
> > +dcr_host_t dcr_map_generic(struct device_node *dev,
> > + unsigned int dcr_n,
> > + unsigned int dcr_c)
> > +{
> > + dcr_host_t host;
> > + const char *prop =3D of_get_property(dev, "dcr-access-method",
NULL);
> > +
> > + if (!strcmp(prop, "native")) {
> > + host.type =3D NATIVE;
> > + host.host.native =3D dcr_map_native(dev, dcr_n, dcr_c);
> > + } else if (!strcmp(prop, "mmio")) {
> > + host.type =3D MMIO;
> > + host.host.mmio =3D dcr_map_mmio(dev, dcr_n, dcr_c);
> > + } else
> > + host.type =3D INVALID;
> > +
> > + return host;
> > +}
> > +EXPORT_SYMBOL_GPL(dcr_map_generic);
> > +
> > +void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c)
> > +{
> > + if (host.type =3D=3D NATIVE)
> > + dcr_unmap_native(host.host.native, dcr_c);
> > + else
> > + dcr_unmap_mmio(host.host.mmio, dcr_c);
> > +}
> > +EXPORT_SYMBOL_GPL(dcr_unmap_generic);
> > +
> > +u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n)
> > +{
> > + if (host.type =3D=3D NATIVE)
> > + return dcr_read_native(host.host.native, dcr_n);
> > + else
> > + return dcr_read_mmio(host.host.mmio, dcr_n);
> > +}
> > +EXPORT_SYMBOL_GPL(dcr_read_generic);
> > +
> > +void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32
value)
> > +{
> > + if (host.type =3D=3D NATIVE)
> > + dcr_write_native(host.host.native, dcr_n, value);
> > + else
> > + dcr_write_mmio(host.host.mmio, dcr_n, value);
> > +}
> > +EXPORT_SYMBOL_GPL(dcr_write_generic);
> > +
> > +#endif /* defined(CONFIG_PPC_DCR_NATIVE) &&
defined(CONFIG_PPC_DCR_MMIO) */
> > +
> > unsigned int dcr_resource_start(struct device_node *np, unsigned
int index)
> > {
> > unsigned int ds;
> > @@ -47,7 +109,7 @@ unsigned int dcr_resource_len(struct device_node
*np, unsigned int index)
> > }
> > EXPORT_SYMBOL_GPL(dcr_resource_len);
> >
> > -#ifndef CONFIG_PPC_DCR_NATIVE
> > +#ifdef CONFIG_PPC_DCR_MMIO
> >
> > static struct device_node * find_dcr_parent(struct device_node *
node)
> > {
> > @@ -101,18 +163,19 @@ u64 of_translate_dcr_address(struct
device_node *dev,
> > return ret;
> > }
> >
> > -dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n,
> > - unsigned int dcr_c)
> > +dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
> > + unsigned int dcr_n,
> > + unsigned int dcr_c)
> > {
> > - dcr_host_t ret =3D { .token =3D NULL, .stride =3D 0, .base =3D =
dcr_n };
> > + dcr_host_mmio_t ret =3D { .token =3D NULL, .stride =3D 0, .base =
=3D
dcr_n };
> > u64 addr;
> >
> > pr_debug("dcr_map(%s, 0x%x, 0x%x)\n",
> > dev->full_name, dcr_n, dcr_c);
> >
> > addr =3D of_translate_dcr_address(dev, dcr_n, &ret.stride);
> > - pr_debug("translates to addr: 0x%lx, stride: 0x%x\n",
> > - addr, ret.stride);
> > + pr_debug("translates to addr: 0x%llx, stride: 0x%x\n",
> > + (unsigned long long) addr, ret.stride);
> > if (addr =3D=3D OF_BAD_ADDR)
> > return ret;
> > pr_debug("mapping 0x%x bytes\n", dcr_c * ret.stride);
> > @@ -124,11 +187,11 @@ dcr_host_t dcr_map(struct device_node *dev,
unsigned int dcr_n,
> > ret.token -=3D dcr_n * ret.stride;
> > return ret;
> > }
> > -EXPORT_SYMBOL_GPL(dcr_map);
> > +EXPORT_SYMBOL_GPL(dcr_map_mmio);
> >
> > -void dcr_unmap(dcr_host_t host, unsigned int dcr_c)
> > +void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c)
> > {
> > - dcr_host_t h =3D host;
> > + dcr_host_mmio_t h =3D host;
> >
> > if (h.token =3D=3D NULL)
> > return;
> > @@ -136,7 +199,11 @@ void dcr_unmap(dcr_host_t host, unsigned int
dcr_c)
> > iounmap(h.token);
> > h.token =3D NULL;
> > }
> > -EXPORT_SYMBOL_GPL(dcr_unmap);
> > -#else /* defined(CONFIG_PPC_DCR_NATIVE) */
> > +EXPORT_SYMBOL_GPL(dcr_unmap_mmio);
> > +
> > +#endif /* defined(CONFIG_PPC_DCR_MMIO) */
> > +
> > +#ifdef CONFIG_PPC_DCR_NATIVE
> > DEFINE_SPINLOCK(dcr_ind_lock);
> > -#endif /* !defined(CONFIG_PPC_DCR_NATIVE) */
> > +#endif /* defined(CONFIG_PPC_DCR_NATIVE) */
> > +
> > diff --git a/include/asm-powerpc/dcr-generic.h
b/include/asm-powerpc/dcr-generic.h
> > new file mode 100644
> > index 0000000..0ee74fb
> > --- /dev/null
> > +++ b/include/asm-powerpc/dcr-generic.h
> > @@ -0,0 +1,49 @@
> > +/*
> > + * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
> > + * <benh@kernel.crashing.org>
> > + *
> > + * This program is free software; you can redistribute it and/or
modify
> > + * it under the terms of the GNU General Public License as
published by
> > + * the Free Software Foundation; either version 2 of the License,
or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be
useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty
of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
> > + * the GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public
License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA
> > + */
> > +
> > +#ifndef _ASM_POWERPC_DCR_GENERIC_H
> > +#define _ASM_POWERPC_DCR_GENERIC_H
> > +#ifdef __KERNEL__
> > +#ifndef __ASSEMBLY__
> > +
> > +enum host_type_t {MMIO, NATIVE, INVALID};
> > +
> > +typedef struct {
> > + enum host_type_t type;
> > + union {
> > + dcr_host_mmio_t mmio;
> > + dcr_host_native_t native;
> > + } host;
> > +} dcr_host_t;
> > +
> > +extern bool dcr_map_ok_generic(dcr_host_t host);
> > +
> > +extern dcr_host_t dcr_map_generic(struct device_node *dev, unsigned
int dcr_n,
> > + unsigned int dcr_c);
> > +extern void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c);
> > +
> > +extern u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n);
> > +
> > +extern void dcr_write_generic(dcr_host_t host, unsigned int dcr_n,
u32 value);
> > +
> > +#endif /* __ASSEMBLY__ */
> > +#endif /* __KERNEL__ */
> > +#endif /* _ASM_POWERPC_DCR_GENERIC_H */
> > +
> > +
> > diff --git a/include/asm-powerpc/dcr-mmio.h
b/include/asm-powerpc/dcr-mmio.h
> > index 08532ff..acd491d 100644
> > --- a/include/asm-powerpc/dcr-mmio.h
> > +++ b/include/asm-powerpc/dcr-mmio.h
> > @@ -27,20 +27,26 @@ typedef struct {
> > void __iomem *token;
> > unsigned int stride;
> > unsigned int base;
> > -} dcr_host_t;
> > +} dcr_host_mmio_t;
> >
> > -#define DCR_MAP_OK(host) ((host).token !=3D NULL)
> > +static inline bool dcr_map_ok_mmio(dcr_host_mmio_t host)
> > +{
> > + return host.token !=3D NULL;
> > +}
> >
> > -extern dcr_host_t dcr_map(struct device_node *dev, unsigned int
dcr_n,
> > - unsigned int dcr_c);
> > -extern void dcr_unmap(dcr_host_t host, unsigned int dcr_c);
> > +extern dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
> > + unsigned int dcr_n,
> > + unsigned int dcr_c);
> > +extern void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int
dcr_c);
> >
> > -static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n)
> > +static inline u32 dcr_read_mmio(dcr_host_mmio_t host, unsigned int
dcr_n)
> > {
> > return in_be32(host.token + ((host.base + dcr_n) *
host.stride));
> > }
> >
> > -static inline void dcr_write(dcr_host_t host, unsigned int dcr_n,
u32 value)
> > +static inline void dcr_write_mmio(dcr_host_mmio_t host,
> > + unsigned int dcr_n,
> > + u32 value)
> > {
> > out_be32(host.token + ((host.base + dcr_n) * host.stride),
value);
> > }
> > diff --git a/include/asm-powerpc/dcr-native.h
b/include/asm-powerpc/dcr-native.h
> > index be6c879..67832e5 100644
> > --- a/include/asm-powerpc/dcr-native.h
> > +++ b/include/asm-powerpc/dcr-native.h
> > @@ -26,14 +26,18 @@
> >
> > typedef struct {
> > unsigned int base;
> > -} dcr_host_t;
> > +} dcr_host_native_t;
> >
> > -#define DCR_MAP_OK(host) (1)
> > +static inline bool dcr_map_ok_native(dcr_host_native_t host)
> > +{
> > + return 1;
> > +}
> >
> > -#define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base =3D (dcr_n)
})
> > -#define dcr_unmap(host, dcr_c) do {} while (0)
> > -#define dcr_read(host, dcr_n) mfdcr(dcr_n + host.base)
> > -#define dcr_write(host, dcr_n, value) mtdcr(dcr_n + host.base,
value)
> > +#define dcr_map_native(dev, dcr_n, dcr_c) \
> > + ((dcr_host_native_t){ .base =3D (dcr_n) })
> > +#define dcr_unmap_native(host, dcr_c) do {} while (0)
> > +#define dcr_read_native(host, dcr_n) mfdcr(dcr_n +
host.base)
> > +#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n +
host.base, value)
> >
> > /* Device Control Registers */
> > void __mtdcr(int reg, unsigned int val);
> > diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h
> > index 9338d50..6b86322 100644
> > --- a/include/asm-powerpc/dcr.h
> > +++ b/include/asm-powerpc/dcr.h
> > @@ -20,14 +20,47 @@
> > #ifndef _ASM_POWERPC_DCR_H
> > #define _ASM_POWERPC_DCR_H
> > #ifdef __KERNEL__
> > +#ifndef __ASSEMBLY__
> > #ifdef CONFIG_PPC_DCR
> >
> > #ifdef CONFIG_PPC_DCR_NATIVE
> > #include <asm/dcr-native.h>
> > -#else
> > +#endif
> > +
> > +#ifdef CONFIG_PPC_DCR_MMIO
> > #include <asm/dcr-mmio.h>
> > #endif
> >
> > +#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
> > +
> > +#include <asm/dcr-generic.h>
> > +
> > +#define DCR_MAP_OK(host) dcr_map_ok_generic(host)
> > +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n,
dcr_c)
> > +#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c)
> > +#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n)
> > +#define dcr_write(host, dcr_n, value) dcr_write_generic(host,
dcr_n, value)
> > +
> > +#else
> > +
> > +#ifdef CONFIG_PPC_DCR_NATIVE
> > +typedef dcr_host_native_t dcr_host_t;
> > +#define DCR_MAP_OK(host) dcr_map_ok_native(host)
> > +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n,
dcr_c)
> > +#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c)
> > +#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n)
> > +#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n,
value)
> > +#else
> > +typedef dcr_host_mmio_t dcr_host_t;
> > +#define DCR_MAP_OK(host) dcr_map_ok_mmio(host)
> > +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c)
> > +#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c)
> > +#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n)
> > +#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n,
value)
> > +#endif
> > +
> > +#endif /* defined(CONFIG_PPC_DCR_NATIVE) &&
defined(CONFIG_PPC_DCR_MMIO) */
> > +
> > /*
> > * On CONFIG_PPC_MERGE, we have additional helpers to read the DCR
> > * base from the device-tree
> > @@ -41,5 +74,6 @@ extern unsigned int dcr_resource_len(struct
device_node *np,
> > #endif /* CONFIG_PPC_MERGE */
> >
> > #endif /* CONFIG_PPC_DCR */
> > +#endif /* __ASSEMBLY__ */
> > #endif /* __KERNEL__ */
> > #endif /* _ASM_POWERPC_DCR_H */
>=20
^ permalink raw reply
* Re: [PATCH v2] powerpc: Add irqtrace support for 32-bit powerpc
From: Benjamin Herrenschmidt @ 2008-04-04 22:07 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev, Johannes Berg
In-Reply-To: <20080404213932.GA15847@farnsworth.org>
> config LOCKDEP_SUPPORT
> diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
> index 69a91bd..bd3ce0f 100644
> --- a/arch/powerpc/kernel/entry_32.S
> +++ b/arch/powerpc/kernel/entry_32.S
> @@ -144,6 +144,47 @@ transfer_to_handler:
> .globl transfer_to_handler_cont
> transfer_to_handler_cont:
> 3:
> +#ifdef CONFIG_TRACE_IRQFLAGS
> + lis r11,reenable_mmu@h
> + ori r11,r11,reenable_mmu@l
> + mtspr SPRN_SRR0,r11
> + mtspr SPRN_SRR1,r10
> + SYNC
> + RFI
I don't think we need that on 4xx/BookE when using AS0 (that is also
true of the existing transfer_to_handler_cont, could be improved there.
> +reenable_mmu: /* re-enable mmu so we can */
> + mflr r9 /* call C code, if necessary */
> + mfmsr r10
> + lwz r11,_MSR(r1)
> + xor r10,r10,r11
> + andi. r10,r10,MSR_EE /* Did EE change? */
> + beq 1f
> + stwu r1,-48(r1) /* Yes, it must have been cleared */
> + stw r9,52(r1)
> + stw r0,16(r1)
> + stw r3,20(r1)
> + stw r4,24(r1)
> + stw r5,28(r1)
> + stw r6,32(r1)
> + stw r7,36(r1)
> + stw r8,40(r1)
> + bl trace_hardirqs_off
> + lwz r0,16(r1)
> + lwz r3,20(r1)
> + lwz r4,24(r1)
> + lwz r5,28(r1)
> + lwz r6,32(r1)
> + lwz r7,36(r1)
> + lwz r8,40(r1)
> + lwz r9,52(r1)
> + addi r1,r1,48
Why do yo save all the volatile regs ? They should have been saved on
the stack already by the exception prolog (the ptregs on the stack).
Also, only the system call really cares about -restoring- them. Maybe
you could stick that in an ifdef CONFIG_TRACE_IRQFLAGS section in
DoSyscall pulling them back off the ptregs in the stackframe.
> + tovirt(r9,r9)
> + lwz r11,0(r9) /* virtual address of handler */
> + lwz r9,4(r9) /* where to go when done */
> + mtctr r11
> + mtlr r9
> + bctr /* jump to handler */
> +#else /* CONFIG_TRACE_IRQFLAGS */
> mflr r9
> lwz r11,0(r9) /* virtual address of handler */
> lwz r9,4(r9) /* where to go when done */
> @@ -152,6 +193,7 @@ transfer_to_handler_cont:
> mtlr r9
> SYNC
> RFI /* jump to handler, enable MMU */
> +#endif /* CONFIG_TRACE_IRQFLAGS */
>
> #ifdef CONFIG_6xx
> 4: rlwinm r12,r12,0,~_TLF_NAPPING
> @@ -220,12 +262,20 @@ ret_from_syscall:
> #ifdef SHOW_SYSCALLS
> bl do_show_syscall_exit
> #endif
> - mr r6,r3
> rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
> /* disable interrupts so current_thread_info()->flags can't change */
> LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
> SYNC
> MTMSRD(r10)
> +#ifdef CONFIG_TRACE_IRQFLAGS
> + stwu r1,-16(r1)
> + stw r3,12(r1)
> + bl trace_hardirqs_off
> + lwz r3,12(r1)
> + addi r1,r1,16
> + LOAD_MSR_KERNEL(r10,MSR_KERNEL)
> +#endif
You may get away with pre-storing r3 in RESULT(r1), I'll have to double
check on monday... the 32 bits syscall exit code is a bit scary :-)
I'm pretty sure there's no need to allocate a stackframe. At worst,
there must be some ptregs field in the existing one that can be used.
That's all for today, I'll have another close look on monday.
Cheers,
Ben.
^ permalink raw reply
* Re: [RFC/PATCH] powerpc: Add irqtrace support to 32-bit powerpc
From: Benjamin Herrenschmidt @ 2008-04-04 22:08 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev, Johannes Berg
In-Reply-To: <20080404212952.GA15454@farnsworth.org>
On Fri, 2008-04-04 at 14:29 -0700, Dale Farnsworth wrote:
> On Fri, Apr 04, 2008 at 09:33:18PM +0200, Johannes Berg wrote:
> > On Wed, 2008-04-02 at 16:15 +0200, Johannes Berg wrote:
> > > On Fri, 2008-02-01 at 12:50 -0700, Dale Farnsworth wrote:
> > > > This adds the low level irq tracing hooks for 32-bit powerpc.
> > > > This patch applies on top of Benjamin Herrenschmidt's patch that
> > > > provides similar support for 64-bit powerpc. See
> > > > <http://ozlabs.org/pipermail/linuxppc-dev/2007-October/044361.html>
> > > >
> > > > It seems to work on my prpmc2800 board with a ppc7447.
> > >
> > > At first it appears to work on my powerbook (with Ben's latest version
> > > of the 64-bit patch), but then it seems to cause random corruption, I've
> > > had a crash in the ext3 code and one in console_callback(), both of
> > > which I cannot otherwise explain.
> >
> > FWIW, same kernel without the patch works fine.
>
> My apologies, Johannes. I made some unwarranted assumptions about
> register usage in the lowest-level exception handlers. While it worked
> on my 7447 board, I saw similar random failures on the 85xx (booke) system
> I tried.
>
> Thanks for testing this.
>
> I'll follow up with a revised patch.
BTW. We don't try to trace the EE changes in the hash code. I suppose
that's fair enough but probably worth putting a comment on somewhere.
Cheers,
Ben.
^ permalink raw reply
* RE: [PATCH 1/5] [v2][POWERPC] refactor dcr code
From: Benjamin Herrenschmidt @ 2008-04-04 22:10 UTC (permalink / raw)
To: Stephen Neuendorffer; +Cc: linuxppc-dev list
In-Reply-To: <20080404220239.DAAC2C6006B@mail222-sin.bigfish.com>
On Fri, 2008-04-04 at 15:02 -0700, Stephen Neuendorffer wrote:
> Ben,
>
> Any thoughts about device tree bindings for indirect DCR?
No, not really. For 44x PCI-E, I've just used something like an
"sdr-base" property to provide the base SDR for the port, simple but not
necessarily the nicest way to do so.
Ben.
^ permalink raw reply
* Re: [PATCH v2] powerpc: Add irqtrace support for 32-bit powerpc
From: Dale Farnsworth @ 2008-04-04 22:35 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Johannes Berg
In-Reply-To: <1207346851.10388.427.camel@pasglop>
On Sat, Apr 05, 2008 at 09:07:31AM +1100, Benjamin Herrenschmidt wrote:
> > diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
> > index 69a91bd..bd3ce0f 100644
> > --- a/arch/powerpc/kernel/entry_32.S
> > +++ b/arch/powerpc/kernel/entry_32.S
> > @@ -144,6 +144,47 @@ transfer_to_handler:
> > .globl transfer_to_handler_cont
> > transfer_to_handler_cont:
> > 3:
> > +#ifdef CONFIG_TRACE_IRQFLAGS
> > + lis r11,reenable_mmu@h
> > + ori r11,r11,reenable_mmu@l
> > + mtspr SPRN_SRR0,r11
> > + mtspr SPRN_SRR1,r10
> > + SYNC
> > + RFI
>
> I don't think we need that on 4xx/BookE when using AS0 (that is also
> true of the existing transfer_to_handler_cont, could be improved there.
Right, it's not needed on 4xx/BookE, but I didn't think it worth
optimizing at this point, since it will split the code into 4xx/BookE
and classic versions. Let's get it working solid first.
> > +reenable_mmu: /* re-enable mmu so we can */
> > + mflr r9 /* call C code, if necessary */
> > + mfmsr r10
> > + lwz r11,_MSR(r1)
> > + xor r10,r10,r11
> > + andi. r10,r10,MSR_EE /* Did EE change? */
> > + beq 1f
> > + stwu r1,-48(r1) /* Yes, it must have been cleared */
> > + stw r9,52(r1)
> > + stw r0,16(r1)
> > + stw r3,20(r1)
> > + stw r4,24(r1)
> > + stw r5,28(r1)
> > + stw r6,32(r1)
> > + stw r7,36(r1)
> > + stw r8,40(r1)
> > + bl trace_hardirqs_off
> > + lwz r0,16(r1)
> > + lwz r3,20(r1)
> > + lwz r4,24(r1)
> > + lwz r5,28(r1)
> > + lwz r6,32(r1)
> > + lwz r7,36(r1)
> > + lwz r8,40(r1)
> > + lwz r9,52(r1)
> > + addi r1,r1,48
>
> Why do yo save all the volatile regs ? They should have been saved on
> the stack already by the exception prolog (the ptregs on the stack).
That's what I originally thought and had in my first version.
However, in the BookE case, we must save at least r3, r4, and r5.
(See data_access: in head_fsl_booke.S.) It isn't clear what the
rules are, and I didn't want to set a trap for when a handler is
added that uses a fourth argument.
If you think it's worth it, I could test a version that saves
r3, r4, and r5 and restores the others from ptregs.
> Also, only the system call really cares about -restoring- them. Maybe
> you could stick that in an ifdef CONFIG_TRACE_IRQFLAGS section in
> DoSyscall pulling them back off the ptregs in the stackframe.
Another optimization that I'm not convinced is worth the trouble
for this tracing code. I'll try to take a look at it though.
As you say below, it's scary code.
> > + tovirt(r9,r9)
> > + lwz r11,0(r9) /* virtual address of handler */
> > + lwz r9,4(r9) /* where to go when done */
> > + mtctr r11
> > + mtlr r9
> > + bctr /* jump to handler */
> > +#else /* CONFIG_TRACE_IRQFLAGS */
> > mflr r9
> > lwz r11,0(r9) /* virtual address of handler */
> > lwz r9,4(r9) /* where to go when done */
> > @@ -152,6 +193,7 @@ transfer_to_handler_cont:
> > mtlr r9
> > SYNC
> > RFI /* jump to handler, enable MMU */
> > +#endif /* CONFIG_TRACE_IRQFLAGS */
> >
> > #ifdef CONFIG_6xx
> > 4: rlwinm r12,r12,0,~_TLF_NAPPING
> > @@ -220,12 +262,20 @@ ret_from_syscall:
> > #ifdef SHOW_SYSCALLS
> > bl do_show_syscall_exit
> > #endif
> > - mr r6,r3
> > rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
> > /* disable interrupts so current_thread_info()->flags can't change */
> > LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
> > SYNC
> > MTMSRD(r10)
> > +#ifdef CONFIG_TRACE_IRQFLAGS
> > + stwu r1,-16(r1)
> > + stw r3,12(r1)
> > + bl trace_hardirqs_off
> > + lwz r3,12(r1)
> > + addi r1,r1,16
> > + LOAD_MSR_KERNEL(r10,MSR_KERNEL)
> > +#endif
>
> You may get away with pre-storing r3 in RESULT(r1), I'll have to double
> check on monday... the 32 bits syscall exit code is a bit scary :-)
It sure is. :-)
> I'm pretty sure there's no need to allocate a stackframe. At worst,
> there must be some ptregs field in the existing one that can be used.
>
> That's all for today, I'll have another close look on monday.
Thanks.
-Dale
^ permalink raw reply
* Re: [PATCH v2] powerpc: Add irqtrace support for 32-bit powerpc
From: Benjamin Herrenschmidt @ 2008-04-04 22:46 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev, Johannes Berg
In-Reply-To: <20080404223522.GA16958@farnsworth.org>
> Right, it's not needed on 4xx/BookE, but I didn't think it worth
> optimizing at this point, since it will split the code into 4xx/BookE
> and classic versions. Let's get it working solid first.
Yup, it's just that I spotted it while reading the code.
> That's what I originally thought and had in my first version.
> However, in the BookE case, we must save at least r3, r4, and r5.
> (See data_access: in head_fsl_booke.S.) It isn't clear what the
> rules are, and I didn't want to set a trap for when a handler is
> added that uses a fourth argument.
Ok, this definitely is worth some rework around the edges. For now, I
suppose keeping it stable will do.
> If you think it's worth it, I could test a version that saves
> r3, r4, and r5 and restores the others from ptregs.
Don't bother for now. I'll see if we can do things differently later.
> > Also, only the system call really cares about -restoring- them. Maybe
> > you could stick that in an ifdef CONFIG_TRACE_IRQFLAGS section in
> > DoSyscall pulling them back off the ptregs in the stackframe.
>
> Another optimization that I'm not convinced is worth the trouble
> for this tracing code. I'll try to take a look at it though.
> As you say below, it's scary code.
Yup. The RESTOREALL case doesn't write the result to the PT_REGS but I'm
not yet sure if that's a big issue to do it regardless or not.
Ben.
^ permalink raw reply
* Re: [PATCH v2] powerpc: Add irqtrace support for 32-bit powerpc
From: Johannes Berg @ 2008-04-04 23:31 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev
In-Reply-To: <20080404213932.GA15847@farnsworth.org>
[-- Attachment #1: Type: text/plain, Size: 462 bytes --]
> This version takes care to save and restore *all* the volatile registers
> around the call to trace_hardirqs_off in transfer_to_handler, and should
> fix the anomalies seen by Johannes Berg. I've tested on 7447- and 8548-
> based boards.
Still has problems on my machine. Maybe to do with non-maskable PMU
interrupts? (saw a patch about something like that float by, don't
really have any idea whether it's related to this work or not)
johannes
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^ permalink raw reply
* Re: [PATCH] [v4] Add idle wait support for 44x platforms
From: Josh Boyer @ 2008-04-05 1:19 UTC (permalink / raw)
To: Jerone Young; +Cc: kvm-ppc-devel, linuxppc-dev, hollisb
In-Reply-To: <bff8b51bd3e1c38518c3.1207326507@thinkpadL>
On Fri, 04 Apr 2008 11:28:27 -0500
Jerone Young <jyoung5@us.ibm.com> wrote:
> 2 files changed, 87 insertions(+), 1 deletion(-)
> arch/powerpc/platforms/44x/Makefile | 2
> arch/powerpc/platforms/44x/idle.c | 86 +++++++++++++++++++++++++++++++++++
>
>
> - adds MSR_DE to MSRs to enable while in wait state
>
> This patch adds the ability for the CPU to go into wait state while in cpu_idle loop. This helps virtulization solutions know when the guest Linux kernel is in an idle state. There are two ways to do it.
>
> 1) Command line
> idle=spin <-- CPU will spin (this is the default)
> idle=wait <-- set CPU into wait state when idle
>
> 2) The device tree will be checked for the "/hypervisor" node
> If this node is seen it will use "wait" for idle, so that
> the hypervisor can know when guest Linux kernel it is in
> an idle state.
>
> This patch, unlike the last, isolates the code to 44x platforms.
>
> Signed-off-by: Jerone Young <jyoung5@us.ibm.com>
This one looks great to me. Thanks for being persistent.
I'll keep it queued up until early next week. I've emailed the CPU
engineers to see what exactly wait state does to the core and if they
know of any issues with it.
If it comes back clean from them and we get good test results with it
enabled, then we can likely reverse the default to use it and remove
the check for the hypervisor node.
josh
^ permalink raw reply
* Re: [PATCH v2] powerpc: Add irqtrace support for 32-bit powerpc
From: Benjamin Herrenschmidt @ 2008-04-05 5:14 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev
In-Reply-To: <1207351869.6675.0.camel@johannes.berg>
On Sat, 2008-04-05 at 01:31 +0200, Johannes Berg wrote:
> > This version takes care to save and restore *all* the volatile registers
> > around the call to trace_hardirqs_off in transfer_to_handler, and should
> > fix the anomalies seen by Johannes Berg. I've tested on 7447- and 8548-
> > based boards.
>
> Still has problems on my machine. Maybe to do with non-maskable PMU
> interrupts? (saw a patch about something like that float by, don't
> really have any idea whether it's related to this work or not)
Or more likely he missed some clobber somewhere, it took me a while to
get that right on ppc64 (well... hopefully it -is- right by now :-)
Ben.
^ permalink raw reply
* Re: [PATCH v2] powerpc: Add irqtrace support for 32-bit powerpc
From: Dale Farnsworth @ 2008-04-05 5:41 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Johannes Berg
In-Reply-To: <1207372496.10388.441.camel@pasglop>
On Sat, Apr 05, 2008 at 04:14:56PM +1100, Benjamin Herrenschmidt wrote:
>
> On Sat, 2008-04-05 at 01:31 +0200, Johannes Berg wrote:
> > > This version takes care to save and restore *all* the volatile registers
> > > around the call to trace_hardirqs_off in transfer_to_handler, and should
> > > fix the anomalies seen by Johannes Berg. I've tested on 7447- and 8548-
> > > based boards.
> >
> > Still has problems on my machine. Maybe to do with non-maskable PMU
> > interrupts? (saw a patch about something like that float by, don't
> > really have any idea whether it's related to this work or not)
>
> Or more likely he missed some clobber somewhere, it took me a while to
> get that right on ppc64 (well... hopefully it -is- right by now :-)
Yep, likely. I'd appreciate help finding it. I'm at a loss. :-)
-Dale
^ permalink raw reply
* Re: Booting Linux Kernel on MPC8560
From: Deepak Gaur @ 2008-04-05 6:56 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20080405063151.M54613@cdotd.ernet.in>
Errata
----------------
Memory Locations
0x1fff0040 nop
...
...
rfi
0x1fff1A40 li r6,0
---------- Forwarded Message -----------
From: "Deepak Gaur" <dgaur@cdotd.ernet.in>
To: linuxppc-embedded@ozlabs.org
Sent: Sat, 5 Apr 2008 13:19:41 +0630
Subject: Booting Linux Kernel on MPC8560
Hi all,
I have a task to boot Mvista kernel on MPC8560 based board. The bootloader in U-boot.
After decompression my final image is located at address 0x1fff0040 in SDRAM (starts
from 0) CCSRBAR register value is 0x000A0000 Bd_t is located at 0x7FFEA0 cmd line :
cmd_start 0x7FFF00 cmd_end 0x800D01 in SDRAM. After the u-boot transfers the control to
kernel it starts executing head_fsl_booke.S file . The execution get struck after
executing a few lines ... on a rfi instruction
---------------------------------------------------------------------------
head_fsl_booke.S First instruction("nop") at 0x1FFF0040 (SDRAM)
---------------------------------------------------------------------------
#include <linux/config.h>
#include <linux/threads.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/mmu.h>
#include <asm/pgtable.h>
#include <asm/cputable.h>
#include <asm/thread_info.h>
#include <asm/ppc_asm.h>
#include <asm/offsets.h>
#include "head_booke.h"
/* As with the other PowerPC ports, it is expected that when code
* execution begins here, the following registers contain valid, yet
* optional, information:
*
* r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
* r4 - Starting address of the init RAM disk
* r5 - Ending address of the init RAM disk
* r6 - Start of kernel command line string (e.g. "mem=128")
* r7 - End of kernel command line string
*
*/
.text
_GLOBAL(_stext)
_GLOBAL(_start)
/*
* Reserve a word at a fixed location to store the address
* of abatron_pteptrs
*/
SD:0x1fff0040: nop
/*
* Save parameters we are passed
*/
mr r31,r3
mr r30,r4
mr r29,r5
mr r28,r6
mr r27,r7
li r24,0 /* CPU number */
/* We try to not make any assumptions about how the boot loader
* setup or used the TLBs. We invalidate all mappings from the
* boot loader and load a single entry in TLB1[0] to map the
* first 16M of kernel memory. Any boot info passed from the
* bootloader needs to live in this first 16M.
*
* Requirement on bootloader:
* - The page we're executing in needs to reside in TLB1 and
* have IPROT=1. If not an invalidate broadcast could
* evict the entry we're currently executing in.
*
* r3 = Index of TLB1 were executing in
* r4 = Current MSR[IS]
* r5 = Index of TLB1 temp mapping
*
* Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
* if needed
*/
/* 1. Find the index of the entry we're executing in */
bl invstr /* Find our address */
invstr: mflr r6 /* Make it accessible */
mfmsr r7
rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
mfspr r7, SPRN_PID0
slwi r7,r7,16
or r7,r7,r4
mtspr SPRN_MAS6,r7
tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
#ifndef CONFIG_E200
mfspr r7,SPRN_MAS1
andis. r7,r7,MAS1_VALID@h
bne match_TLB
mfspr r7,SPRN_PID1
slwi r7,r7,16
or r7,r7,r4
mtspr SPRN_MAS6,r7
tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
mfspr r7,SPRN_MAS1
andis. r7,r7,MAS1_VALID@h
bne match_TLB
mfspr r7, SPRN_PID2
slwi r7,r7,16
or r7,r7,r4
mtspr SPRN_MAS6,r7
tlbsx 0,r6 /* Fall through, we had to match */
#endif
match_TLB:
mfspr r7,SPRN_MAS0
rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
mfspr r7,SPRN_MAS1 /* Insure IPROT set */
oris r7,r7,MAS1_IPROT@h
mtspr SPRN_MAS1,r7
tlbwe
/* 2. Invalidate all entries except the entry we're executing in */
mfspr r9,SPRN_TLB1CFG
andi. r9,r9,0xfff
li r6,0 /* Set Entry counter to 0 */
1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
mtspr SPRN_MAS0,r7
tlbre
mfspr r7,SPRN_MAS1
rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
cmpw r3,r6
beq skpinv /* Dont update the current execution TLB */
mtspr SPRN_MAS1,r7
tlbwe
isync
skpinv: addi r6,r6,1 /* Increment */
cmpw r6,r9 /* Are we done? */
bne 1b /* If not, repeat */
/* Invalidate TLB0 */
li r6,0x04
tlbivax 0,r6
#ifdef CONFIG_SMP
tlbsync
#endif
/* Invalidate TLB1 */
li r6,0x0c
tlbivax 0,r6
#ifdef CONFIG_SMP
tlbsync
#endif
msync
/* 3. Setup a temp mapping and jump to it */
andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
addi r5, r5, 0x1
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
mtspr SPRN_MAS0,r7
tlbre
/* Just modify the entry ID and EPN for the temp mapping */
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
mtspr SPRN_MAS0,r7
xori r6,r4,1 /* Setup TMP mapping in the other Address space */
slwi r6,r6,12
oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
mtspr SPRN_MAS1,r6
mfspr r6,SPRN_MAS2
li r7,0 /* temp EPN = 0 */
rlwimi r7,r6,0,20,31
mtspr SPRN_MAS2,r7
tlbwe
xori r6,r4,1
slwi r6,r6,5 /* setup new context with other address space */
bl 1f /* Find our address */
1: mflr r9
rlwimi r7,r9,0,20,31
addi r7,r7,24
mtspr SRR0,r7 <------------------------ SRR0 1A40
mtspr SRR1,r6 <------------------------ SRR1 20
rfi <------------------------ It goes to LOCATION 0x00001A40
/* 4. Clear out PIDs & Search info */
SD: 0x1fff01A40 li r6,0
mtspr SPRN_PID0,r6
SD memory locattion as reported by ICE
The SRR0 contains 0x00001A40 address for rfi. The memory location of next instruction
happens to be similar to contents of SRR0 . It is 0x1fff01a40. It is that the SRR0
should have contained 0x1fff01A40 or 0x00001A40 is correct. Actually on 0x00001A40 there
no instruction is defined (as reported by ICE it is "undef")
Please help me in understanding this behaviour and more specifically need of "rfi"
instruction in this file.
Thanks
Deepak Gaur
------- End of Forwarded Message -------
Deepak Gaur
^ permalink raw reply
* Booting Linux Kernel on MPC8560
From: Deepak Gaur @ 2008-04-05 6:49 UTC (permalink / raw)
To: linuxppc-embedded
Hi all,
I have a task to boot Mvista kernel on MPC8560 based board. The bootloader in U-boot.
After decompression my final image is located at address 0x1fff0040 in SDRAM (starts
from 0) CCSRBAR register value is 0x000A0000 Bd_t is located at 0x7FFEA0 cmd line :
cmd_start 0x7FFF00 cmd_end 0x800D01 in SDRAM. After the u-boot transfers the control to
kernel it starts executing head_fsl_booke.S file . The execution get struck after
executing a few lines ... on a rfi instruction
---------------------------------------------------------------------------
head_fsl_booke.S First instruction("nop") at 0x1FFF0040 (SDRAM)
---------------------------------------------------------------------------
#include <linux/config.h>
#include <linux/threads.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/mmu.h>
#include <asm/pgtable.h>
#include <asm/cputable.h>
#include <asm/thread_info.h>
#include <asm/ppc_asm.h>
#include <asm/offsets.h>
#include "head_booke.h"
/* As with the other PowerPC ports, it is expected that when code
* execution begins here, the following registers contain valid, yet
* optional, information:
*
* r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
* r4 - Starting address of the init RAM disk
* r5 - Ending address of the init RAM disk
* r6 - Start of kernel command line string (e.g. "mem=128")
* r7 - End of kernel command line string
*
*/
.text
_GLOBAL(_stext)
_GLOBAL(_start)
/*
* Reserve a word at a fixed location to store the address
* of abatron_pteptrs
*/
SD:0x1fff0040: nop
/*
* Save parameters we are passed
*/
mr r31,r3
mr r30,r4
mr r29,r5
mr r28,r6
mr r27,r7
li r24,0 /* CPU number */
/* We try to not make any assumptions about how the boot loader
* setup or used the TLBs. We invalidate all mappings from the
* boot loader and load a single entry in TLB1[0] to map the
* first 16M of kernel memory. Any boot info passed from the
* bootloader needs to live in this first 16M.
*
* Requirement on bootloader:
* - The page we're executing in needs to reside in TLB1 and
* have IPROT=1. If not an invalidate broadcast could
* evict the entry we're currently executing in.
*
* r3 = Index of TLB1 were executing in
* r4 = Current MSR[IS]
* r5 = Index of TLB1 temp mapping
*
* Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
* if needed
*/
/* 1. Find the index of the entry we're executing in */
bl invstr /* Find our address */
invstr: mflr r6 /* Make it accessible */
mfmsr r7
rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
mfspr r7, SPRN_PID0
slwi r7,r7,16
or r7,r7,r4
mtspr SPRN_MAS6,r7
tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
#ifndef CONFIG_E200
mfspr r7,SPRN_MAS1
andis. r7,r7,MAS1_VALID@h
bne match_TLB
mfspr r7,SPRN_PID1
slwi r7,r7,16
or r7,r7,r4
mtspr SPRN_MAS6,r7
tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
mfspr r7,SPRN_MAS1
andis. r7,r7,MAS1_VALID@h
bne match_TLB
mfspr r7, SPRN_PID2
slwi r7,r7,16
or r7,r7,r4
mtspr SPRN_MAS6,r7
tlbsx 0,r6 /* Fall through, we had to match */
#endif
match_TLB:
mfspr r7,SPRN_MAS0
rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
mfspr r7,SPRN_MAS1 /* Insure IPROT set */
oris r7,r7,MAS1_IPROT@h
mtspr SPRN_MAS1,r7
tlbwe
/* 2. Invalidate all entries except the entry we're executing in */
mfspr r9,SPRN_TLB1CFG
andi. r9,r9,0xfff
li r6,0 /* Set Entry counter to 0 */
1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
mtspr SPRN_MAS0,r7
tlbre
mfspr r7,SPRN_MAS1
rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
cmpw r3,r6
beq skpinv /* Dont update the current execution TLB */
mtspr SPRN_MAS1,r7
tlbwe
isync
skpinv: addi r6,r6,1 /* Increment */
cmpw r6,r9 /* Are we done? */
bne 1b /* If not, repeat */
/* Invalidate TLB0 */
li r6,0x04
tlbivax 0,r6
#ifdef CONFIG_SMP
tlbsync
#endif
/* Invalidate TLB1 */
li r6,0x0c
tlbivax 0,r6
#ifdef CONFIG_SMP
tlbsync
#endif
msync
/* 3. Setup a temp mapping and jump to it */
andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
addi r5, r5, 0x1
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
mtspr SPRN_MAS0,r7
tlbre
/* Just modify the entry ID and EPN for the temp mapping */
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
mtspr SPRN_MAS0,r7
xori r6,r4,1 /* Setup TMP mapping in the other Address space */
slwi r6,r6,12
oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
mtspr SPRN_MAS1,r6
mfspr r6,SPRN_MAS2
li r7,0 /* temp EPN = 0 */
rlwimi r7,r6,0,20,31
mtspr SPRN_MAS2,r7
tlbwe
xori r6,r4,1
slwi r6,r6,5 /* setup new context with other address space */
bl 1f /* Find our address */
1: mflr r9
rlwimi r7,r9,0,20,31
addi r7,r7,24
mtspr SRR0,r7 <------------------------ SRR0 1A40
mtspr SRR1,r6 <------------------------ SRR1 20
rfi <------------------------ It goes to LOCATION 0x00001A40
/* 4. Clear out PIDs & Search info */
SD: 0x1fff01A40 li r6,0
mtspr SPRN_PID0,r6
SD memory locattion as reported by ICE
The SRR0 contains 0x00001A40 address for rfi. The memory location of next instruction
happens to be similar to contents of SRR0 . It is 0x1fff01a40. It is that the SRR0
should have contained 0x1fff01A40 or 0x00001A40 is correct. Actually on 0x00001A40 there
no instruction is defined (as reported by ICE it is "undef")
Please help me in understanding this behaviour and more specifically need of "rfi"
instruction in this file.
Thanks
Deepak Gaur
^ permalink raw reply
* MPC8343 - "unable to handle paging request @ 0"
From: André Schwarz @ 2008-04-05 8:19 UTC (permalink / raw)
To: kim.phillips; +Cc: linuxppc-dev
Kim,
sorry for the general questions - but I'm running out of ideas.
We never ever had that many problems getting a PowerPC running during=20
the past 10 years.
I've cross-checked the hardware and design with Freescale FAE.=20
Everything looks fine and is approved.
We're running latest u-boot v1.3.2 and kernel 2.6.25-rc8 from Denx.
A MPC5200B System is up and running fine with this scenario, so=20
hopefully there are no basic problems.
The MPC8343B (rev.3.1) is working pretty fine with u-boot including=20
mtest. Only problem is a the TSECs not working with our RGMII phy - but=20
this can wait.
I've set up a dts based on the MPC834x_mds and removed the 2nd PCI bus=20
and local bus stuff.
Kernel has been build with a new platform "MVBLM7" which is the name of=20
our board - nothing special so far.
u-boot fills out all parameters (clocks, mem, initrd @ chosen, ...)=20
correctly and the kernel is started exactly the same way as the MPC5200B=20
system using "bootm kernel_add initrd_addr dtb_addr".
Kernel starts and crashes with "unable to handle kernel paging request @=20
00000000".
After turning debug on in some files I can see that the initrd memory=20
gets reserved and the dtb is parsed correctly.
PCI memory/io spaces are set up fine.
At first I thought this is a problem with the device tree since the call=20
trace always points to "of_"-functions and "strcmp".
So I removed nearly everything from the kernel and dts including PCI,=20
net, USB and peripherals leaving only a minimum (cpu, mem, soc-node with=20
ipic and serial).
Unfortunately the error is still the same !
I wonder if there are some basic issues regarding MPC8343 or=20
specialities from the Freescale boards not being present on our board.
Major difference is the CPU (MPC8343B), 512MB RAM (using 2 BATs of=20
course) and nothing else on the local bus besides the Nor-Flash.
Of course the MPC8343 has only a single PCI-32 and only one USB.
Do you have any hints on this ?
Do you suggest to wait for the 2.6.25 release ?
Do you know of any MPC8343 based boards already up and running ?
regards,
Andr=E9 Schwarz
MATRIX VISION GmbH, Talstra=DFe 16, DE-71570 Oppenweiler - Registergeric=
ht: Amtsgericht Stuttgart, HRB 271090
Gesch=E4ftsf=FChrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
^ permalink raw reply
* Rameshmrm sent you a friend request on Tagged :)
From: Rameshmrm Mrm @ 2008-04-05 9:55 UTC (permalink / raw)
To: linuxppc-dev
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^ permalink raw reply
* Rameshmrm sent you a friend request on Tagged :)
From: Rameshmrm Mrm @ 2008-04-05 9:55 UTC (permalink / raw)
To: linuxppc-embedded
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^ permalink raw reply
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