* [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth
From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw)
To: linuxppc-dev, galak; +Cc: Haiying Wang
In-Reply-To: <12410288792524-git-send-email-Haiying.Wang@freescale.com>
Change the definition of riscTx and riscRx to unsigned integer instead of enum,
and change their values to support 4 risc allocation if the qe has 4 RISC
engines.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
drivers/net/ucc_geth.c | 14 +++++++++++---
drivers/net/ucc_geth.h | 4 ++--
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index d3f39e8..3e003fe 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -270,7 +270,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
u8 num_entries,
u32 thread_size,
u32 thread_alignment,
- enum qe_risc_allocation risc,
+ unsigned int risc,
int skip_page_for_first_entry)
{
u32 init_enet_offset;
@@ -307,7 +307,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
static int return_init_enet_entries(struct ucc_geth_private *ugeth,
u32 *p_start,
u8 num_entries,
- enum qe_risc_allocation risc,
+ unsigned int risc,
int skip_page_for_first_entry)
{
u32 init_enet_offset;
@@ -342,7 +342,7 @@ static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
u32 __iomem *p_start,
u8 num_entries,
u32 thread_size,
- enum qe_risc_allocation risc,
+ unsigned int risc,
int skip_page_for_first_entry)
{
u32 init_enet_offset;
@@ -2134,6 +2134,14 @@ static int ucc_struct_init(struct ucc_geth_private *ugeth)
return -ENOMEM;
}
+ /* read the number of risc engines, update the riscTx and riscRx
+ * if there are 4 riscs in QE
+ */
+ if (qe_get_num_of_risc() == 4) {
+ ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
+ ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
+ }
+
ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
if (!ugeth->ug_regs) {
if (netif_msg_probe(ugeth))
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h
index 2f8ee7c..46bb1d2 100644
--- a/drivers/net/ucc_geth.h
+++ b/drivers/net/ucc_geth.h
@@ -1120,8 +1120,8 @@ struct ucc_geth_info {
enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
enum ucc_geth_num_of_threads numThreadsTx;
enum ucc_geth_num_of_threads numThreadsRx;
- enum qe_risc_allocation riscTx;
- enum qe_risc_allocation riscRx;
+ unsigned int riscTx;
+ unsigned int riscRx;
};
/* structure representing UCC GETH */
--
1.6.0.2
^ permalink raw reply related
* [PATCH 2/6] powerpc/qe: update risc allocation for QE
From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw)
To: linuxppc-dev, galak; +Cc: Haiying Wang
In-Reply-To: <1241028878175-git-send-email-Haiying.Wang@freescale.com>
Change the RISC allocation to macros instead of enum, add function to read the
number of risc engines from the new property "num-riscs" under qe node in dts.
Add new property "num-riscs" description in qe.txt
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
.../powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 1 +
arch/powerpc/include/asm/qe.h | 18 ++++++++----
arch/powerpc/sysdev/qe_lib/qe.c | 28 ++++++++++++++++++++
3 files changed, 41 insertions(+), 6 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
index 78790d5..b6ea613 100644
--- a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
@@ -21,6 +21,7 @@ Required properties:
Recommended properties
- brg-frequency : the internal clock source frequency for baud-rate
generators in Hz.
+- num-riscs: define how many RISC engines the QE has.
Example:
qe@e0100000 {
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index 2701753..60314ef 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -152,6 +152,8 @@ unsigned int qe_get_brg_clk(void);
int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
int qe_get_snum(void);
void qe_put_snum(u8 snum);
+unsigned int qe_get_num_of_risc(void);
+
/* we actually use cpm_muram implementation, define this for convenience */
#define qe_muram_init cpm_muram_init
#define qe_muram_alloc cpm_muram_alloc
@@ -231,12 +233,16 @@ struct qe_bd {
#define QE_ALIGNMENT_OF_PRAM 64
/* RISC allocation */
-enum qe_risc_allocation {
- QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
- QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
- QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose
- RISC 1 or RISC 2 */
-};
+#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
+#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
+#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
+#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
+#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
+ QE_RISC_ALLOCATION_RISC2)
+#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
+ QE_RISC_ALLOCATION_RISC2 | \
+ QE_RISC_ALLOCATION_RISC3 | \
+ QE_RISC_ALLOCATION_RISC4)
/* QE extended filtering Table Lookup Key Size */
enum qe_fltr_tbl_lookup_key_size {
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 01bce37..31a3bb1 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -575,3 +575,31 @@ struct qe_firmware_info *qe_get_firmware_info(void)
}
EXPORT_SYMBOL(qe_get_firmware_info);
+unsigned int qe_get_num_of_risc(void)
+{
+ struct device_node *qe;
+ int size;
+ unsigned int num_of_risc = 0;
+ const u32 *prop;
+
+ qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
+ if (!qe) {
+ /* Older devices trees did not have an "fsl,qe"
+ * compatible property, so we need to look for
+ * the QE node by name.
+ */
+ qe = of_find_node_by_type(NULL, "qe");
+ if (!qe)
+ return num_of_risc;
+ }
+
+ prop = of_get_property(qe, "num-riscs", &size);
+ if (prop && size == sizeof(*prop))
+ num_of_risc = *prop;
+
+ of_node_put(qe);
+
+ return num_of_risc;
+}
+EXPORT_SYMBOL(qe_get_num_of_risc);
+
--
1.6.0.2
^ permalink raw reply related
* [PATCH 6/6] powerpc/85xx: Add MPC8569MDS board support
From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw)
To: linuxppc-dev, galak; +Cc: Haiying Wang
In-Reply-To: <1241028884406-git-send-email-Haiying.Wang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
arch/powerpc/boot/dts/mpc8569mds.dts | 514 +++++++++++++++++++++++++++++
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 23 ++
2 files changed, 537 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc8569mds.dts
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
new file mode 100644
index 0000000..3ddd8c3
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -0,0 +1,514 @@
+/*
+ * MPC8569E MDS Device Tree Source
+ *
+ * Copyright (C) 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "MPC8569EMDS";
+ compatible = "fsl,MPC8569EMDS";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8569@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xe0005000 0 0x1000>;
+ interrupt = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ ranges = <0x0 0x0 0xfe000000 0x02000000
+ 0x1 0x0 0xf8000000 0x00008000
+ 0x2 0x0 0xf0000000 0x04000000
+ 0x4 0x0 0xf8008000 0x00008000
+ 0x5 0x0 0xf8010000 0x00008000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ bcsr@1,0 {
+ compatible = "fsl,mpc8569mds-bcsr";
+ reg = <1 0 0x8000>;
+ };
+
+ pib@4,0 {
+ compatible = "fsl,mpc8569mds-pib";
+ reg = <4 0 0x8000>;
+ };
+
+ pib@5,0 {
+ compatible = "fsl,mpc8569mds-pib";
+ reg = <5 0 0x8000>;
+ };
+ };
+
+ soc@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8569-immr", "simple-bus";
+ ranges = <0x0 0xe0000000 0x100000>;
+ reg = <0xe0000000 0x1000>;
+ bus-frequency = <0>;
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <10>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,mpc8569-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,mpc8569-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+
+ rtc@68 {
+ compatible = "dallas,ds1374";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,mpc8569-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8569-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8569-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8569-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8569-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ global-utilities@e0000 {
+ compatible = "fsl,mpc8569-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+
+ par_io@e0100 {
+ reg = <0xe0100 0x100>;
+ device_type = "par_io";
+ num-ports = <7>;
+
+ pio1: ucc_pin@01 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
+ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
+ 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
+ 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
+ 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
+ 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
+ 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
+ 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
+ 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
+ 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
+ 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
+ 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
+ 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
+ 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
+ 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
+ };
+
+ pio2: ucc_pin@02 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
+ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
+ 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
+ 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
+ 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
+ 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
+ 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
+ 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
+ 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
+ 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
+ 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
+ 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
+ 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
+ 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
+ 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
+ };
+
+ pio3: ucc_pin@03 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
+ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
+ 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
+ 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
+ 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
+ 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
+ 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
+ 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
+ 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
+ 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
+ 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
+ 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
+ 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
+ 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
+ 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
+ };
+
+ pio4: ucc_pin@04 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
+ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
+ 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
+ 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
+ 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
+ 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
+ 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
+ 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
+ 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
+ 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
+ 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
+ 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
+ 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
+ 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
+ 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
+ };
+ };
+ };
+
+ qe@e0080000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe";
+ ranges = <0x0 0xe0080000 0x40000>;
+ reg = <0xe0080000 0x480>;
+ brg-frequency = <0>;
+ bus-frequency = <0>;
+ num-riscs = <4>;
+ num-snums = <46>;
+
+ qeic: interrupt-controller@80 {
+ interrupt-controller;
+ compatible = "fsl,qe-ic";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x80 0x80>;
+ interrupts = <46 2 46 2>; //high:30 low:30
+ interrupt-parent = <&mpic>;
+ };
+
+ spi@4c0 {
+ cell-index = <0>;
+ compatible = "fsl,spi";
+ reg = <0x4c0 0x40>;
+ interrupts = <2>;
+ interrupt-parent = <&qeic>;
+ mode = "cpu";
+ };
+
+ spi@500 {
+ cell-index = <1>;
+ compatible = "fsl,spi";
+ reg = <0x500 0x40>;
+ interrupts = <1>;
+ interrupt-parent = <&qeic>;
+ mode = "cpu";
+ };
+
+ enet0: ucc@2000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk12";
+ pio-handle = <&pio1>;
+ phy-handle = <&qe_phy0>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ mdio@2120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2120 0x18>;
+ compatible = "fsl,ucc-mdio";
+
+ qe_phy0: ethernet-phy@07 {
+ interrupt-parent = <&mpic>;
+ interrupts = <1 1>;
+ reg = <0x7>;
+ device_type = "ethernet-phy";
+ };
+ qe_phy1: ethernet-phy@01 {
+ interrupt-parent = <&mpic>;
+ interrupts = <2 1>;
+ reg = <0x1>;
+ device_type = "ethernet-phy";
+ };
+ qe_phy2: ethernet-phy@02 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x2>;
+ device_type = "ethernet-phy";
+ };
+ qe_phy3: ethernet-phy@03 {
+ interrupt-parent = <&mpic>;
+ interrupts = <4 1>;
+ reg = <0x3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet2: ucc@2200 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk12";
+ pio-handle = <&pio3>;
+ phy-handle = <&qe_phy2>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet1: ucc@3000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <2>;
+ reg = <0x3000 0x200>;
+ interrupts = <33>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk17";
+ pio-handle = <&pio2>;
+ phy-handle = <&qe_phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet3: ucc@3200 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <4>;
+ reg = <0x3200 0x200>;
+ interrupts = <35>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk17";
+ pio-handle = <&pio4>;
+ phy-handle = <&qe_phy3>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x20000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x20000>;
+ };
+ };
+
+ };
+
+ /* PCI Express */
+ pci1: pcie@e000a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xe000a000 0x1000>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 (PEX) */
+ 00000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 00000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 00000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
+ clock-frequency = <33333333>;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x800000>;
+ };
+ };
+};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index d34d29a..b2c0a43 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -259,6 +259,7 @@ static int __init board_fixups(void)
return 0;
}
machine_arch_initcall(mpc8568_mds, board_fixups);
+machine_arch_initcall(mpc8569_mds, board_fixups);
static struct of_device_id mpc85xx_ids[] = {
{ .type = "soc", },
@@ -278,6 +279,7 @@ static int __init mpc85xx_publish_devices(void)
return 0;
}
machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
+machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
static void __init mpc85xx_mds_pic_init(void)
{
@@ -335,3 +337,24 @@ define_machine(mpc8568_mds) {
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
};
+
+static int __init mpc8569_mds_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
+}
+
+define_machine(mpc8569_mds) {
+ .name = "MPC8569 MDS",
+ .probe = mpc8569_mds_probe,
+ .setup_arch = mpc85xx_mds_setup_arch,
+ .init_IRQ = mpc85xx_mds_pic_init,
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+};
--
1.6.0.2
^ permalink raw reply related
* [PATCH 1/6] powerpc/85xx: clean up for mpc8568_mds name
From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw)
To: linuxppc-dev, galak; +Cc: Haiying Wang
Keep an unique machine def for the MPC8568 MDS board to handle some
subtle differences between the future MDS board. Also set the bcsrs in
setup_arch() only for mpc8568_mds because other mds has different bcsr settings.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 29 +++++++++++++++--------------
1 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 7dd0290..d34d29a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -206,23 +206,24 @@ static void __init mpc85xx_mds_setup_arch(void)
}
if (bcsr_regs) {
+ if (machine_is(mpc8568_mds)) {
#define BCSR_UCC1_GETH_EN (0x1 << 7)
#define BCSR_UCC2_GETH_EN (0x1 << 7)
#define BCSR_UCC1_MODE_MSK (0x3 << 4)
#define BCSR_UCC2_MODE_MSK (0x3 << 0)
- /* Turn off UCC1 & UCC2 */
- clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
- clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+ /* Turn off UCC1 & UCC2 */
+ clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+ clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
- /* Mode is RGMII, all bits clear */
- clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
- BCSR_UCC2_MODE_MSK);
-
- /* Turn UCC1 & UCC2 on */
- setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
- setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+ /* Mode is RGMII, all bits clear */
+ clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
+ BCSR_UCC2_MODE_MSK);
+ /* Turn UCC1 & UCC2 on */
+ setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+ setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+ }
iounmap(bcsr_regs);
}
#endif /* CONFIG_QUICC_ENGINE */
@@ -257,7 +258,7 @@ static int __init board_fixups(void)
return 0;
}
-machine_arch_initcall(mpc85xx_mds, board_fixups);
+machine_arch_initcall(mpc8568_mds, board_fixups);
static struct of_device_id mpc85xx_ids[] = {
{ .type = "soc", },
@@ -276,7 +277,7 @@ static int __init mpc85xx_publish_devices(void)
return 0;
}
-machine_device_initcall(mpc85xx_mds, mpc85xx_publish_devices);
+machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
static void __init mpc85xx_mds_pic_init(void)
{
@@ -321,8 +322,8 @@ static int __init mpc85xx_mds_probe(void)
return of_flat_dt_is_compatible(root, "MPC85xxMDS");
}
-define_machine(mpc85xx_mds) {
- .name = "MPC85xx MDS",
+define_machine(mpc8568_mds) {
+ .name = "MPC8568 MDS",
.probe = mpc85xx_mds_probe,
.setup_arch = mpc85xx_mds_setup_arch,
.init_IRQ = mpc85xx_mds_pic_init,
--
1.6.0.2
^ permalink raw reply related
* [PATCH 4/6] powerpc/qe: update QE Serial Number
From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw)
To: linuxppc-dev, galak; +Cc: Haiying Wang
In-Reply-To: <12410288811793-git-send-email-Haiying.Wang@freescale.com>
The latest QE chip may have more Serial Number(SNUM)s of thread to use. We will
get the number of SNUMs from device tree by reading the new property "num-snums"
, and set 28 as the default number of SNUMs so that it is compatible with the
old QE chips' device trees which don't have this new property.
The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum table which
is 256.
Also we update the snum_init[] array with 18 more new SNUMs which are
confirmed to be useful on new chip.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
.../powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 1 +
arch/powerpc/include/asm/qe.h | 3 +-
arch/powerpc/sysdev/qe_lib/qe.c | 47 ++++++++++++++++++--
3 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
index b6ea613..9f7df90 100644
--- a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
@@ -22,6 +22,7 @@ Recommended properties
- brg-frequency : the internal clock source frequency for baud-rate
generators in Hz.
- num-riscs: define how many RISC engines the QE has.
+- num-snums: define how many serial number(SNUM) the QE can use for the threads.
Example:
qe@e0100000 {
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index 60314ef..e0faf33 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -22,7 +22,7 @@
#include <asm/cpm.h>
#include <asm/immap_qe.h>
-#define QE_NUM_OF_SNUM 28
+#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
#define QE_NUM_OF_BRGS 16
#define QE_NUM_OF_PORTS 1024
@@ -153,6 +153,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
int qe_get_snum(void);
void qe_put_snum(u8 snum);
unsigned int qe_get_num_of_risc(void);
+unsigned int qe_get_num_of_snums(void);
/* we actually use cpm_muram implementation, define this for convenience */
#define qe_muram_init cpm_muram_init
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 31a3bb1..69116d9 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -61,6 +61,7 @@ struct qe_immap __iomem *qe_immr;
EXPORT_SYMBOL(qe_immr);
static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
+static unsigned int qe_num_of_snum;
static phys_addr_t qebase = -1;
@@ -264,10 +265,14 @@ static void qe_snums_init(void)
0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
- 0xD8, 0xD9, 0xE8, 0xE9,
+ 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
+ 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
+ 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
};
- for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+ qe_num_of_snum = qe_get_num_of_snums();
+
+ for (i = 0; i < qe_num_of_snum; i++) {
snums[i].num = snum_init[i];
snums[i].state = QE_SNUM_STATE_FREE;
}
@@ -280,7 +285,7 @@ int qe_get_snum(void)
int i;
spin_lock_irqsave(&qe_lock, flags);
- for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+ for (i = 0; i < qe_num_of_snum; i++) {
if (snums[i].state == QE_SNUM_STATE_FREE) {
snums[i].state = QE_SNUM_STATE_USED;
snum = snums[i].num;
@@ -297,7 +302,7 @@ void qe_put_snum(u8 snum)
{
int i;
- for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+ for (i = 0; i < qe_num_of_snum; i++) {
if (snums[i].num == snum) {
snums[i].state = QE_SNUM_STATE_FREE;
break;
@@ -603,3 +608,37 @@ unsigned int qe_get_num_of_risc(void)
}
EXPORT_SYMBOL(qe_get_num_of_risc);
+unsigned int qe_get_num_of_snums(void)
+{
+ struct device_node *qe;
+ int size;
+ unsigned int num_of_snums;
+ const u32 *prop;
+
+ num_of_snums = 28; /* The default number of snum for threads is 28 */
+ qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
+ if (!qe) {
+ /* Older devices trees did not have an "fsl,qe"
+ * compatible property, so we need to look for
+ * the QE node by name.
+ */
+ qe = of_find_node_by_type(NULL, "qe");
+ if (!qe)
+ return num_of_snums;
+ }
+
+ prop = of_get_property(qe, "num-snums", &size);
+ if (prop && size == sizeof(*prop)) {
+ num_of_snums = *prop;
+ if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
+ /* No QE ever has fewer than 28 SNUMs */
+ pr_err("QE: number of snum is invalid\n");
+ return -EINVAL;
+ }
+ }
+
+ of_node_put(qe);
+
+ return num_of_snums;
+}
+EXPORT_SYMBOL(qe_get_num_of_snums);
--
1.6.0.2
^ permalink raw reply related
* [PATCH 5/6] net/ucc_geth: Assign six threads to Rx for UEC
From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw)
To: linuxppc-dev, galak; +Cc: Haiying Wang
In-Reply-To: <1241028883630-git-send-email-Haiying.Wang@freescale.com>
when there are 46 snums defined in device tree.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
drivers/net/ucc_geth.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 3e003fe..1f6529f 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -3709,7 +3709,10 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma
ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
- ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
+ if (qe_get_num_of_snums() == 46)
+ ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
+ else
+ ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
}
if (netif_msg_probe(&debug))
--
1.6.0.2
^ permalink raw reply related
* Re: Next April 28: boot failure on PowerPC with SLQB
From: Sachin Sant @ 2009-04-29 16:26 UTC (permalink / raw)
To: Nick Piggin
Cc: Stephen Rothwell, Christoph Lameter, linux-kernel, linuxppc-dev,
Pekka Enberg, linux-next
In-Reply-To: <20090429113604.GE3398@wotan.suse.de>
Nick Piggin wrote:
> Does this help?
> ---
With the patch the machine boots past the failure point, but panics
immediately with the following trace...
Unable to handle kernel paging request for data at address 0x00000010
Faulting instruction address: 0xc0000000007d03ec
Oops: Kernel access of bad area, sig: 11 [#1]
SMP NR_CPUS=1024 DEBUG_PAGEALLOC NUMA pSeries
Modules linked in:
NIP: c0000000007d03ec LR: c0000000007b0bbc CTR: 0000000000136f8c
REGS: c000000000a23bd0 TRAP: 0300 Not tainted (2.6.30-rc3-next-20090429)
MSR: 8000000000009032 <EE,ME,IR,DR> CR: 28000084 XER: 00000010
DAR: 0000000000000010, DSISR: 0000000040000000
TASK = c000000000955fc0[0] 'swapper' THREAD: c000000000a20000 CPU: 0
GPR00: 0000000000000001 c000000000a23e50 c000000000a17650 000000000000001f
GPR04: 0000000000000000 ffffffffffffffff 000000000077a4b9 800000000c9b2cc0
GPR08: 0000000000000000 0000000000000010 0000000000000000 c00000000095b0f8
GPR12: 0000000028000082 c000000000af2400 c0000000007f3200 c000000000705c32
GPR16: 00000000014f3138 0000000000000000 c0000000007f3138 0000000002f1fc90
GPR20: c0000000007f3150 c000000000725d11 00000000007bb8e4 0000000002f1fc90
GPR24: 0000000002f1fc90 c0000000007f31f0 0000000000d00000 c000000000b73b10
GPR28: c0000000007f0440 c00000000095db00 c00000000098d5f0 0000000003c90000
NIP [c0000000007d03ec] .pidmap_init+0x28/0x88
LR [c0000000007b0bbc] .start_kernel+0x458/0x51c
Call Trace:
[c000000000a23e50] [c000000000a23ee0] init_thread_union+0x3ee0/0x4000
(unreliable)
[c000000000a23ee0] [c0000000007b0bbc] .start_kernel+0x458/0x51c
[c000000000a23f90] [c0000000000083d8] .start_here_common+0x1c/0x44
Instruction dump:
ebc1fff0 4e800020 fbc1fff0 ebc2b1a8 39200010 7c0802a6 fba1ffe8 f8010010
38000001 ebbe8008 f821ff71 f93d0010 <7d6048a8> 7d6b0378 7d6049ad 40c2fff4
---[ end trace 31fd0ba7d8756001 ]---
Kernel panic - not syncing: Attempted to kill the idle task!
Call Trace:
[c000000000a23820] [c000000000011700] .show_stack+0x6c/0x16c (unreliable)
[c000000000a238d0] [c000000000561f1c] .panic+0x80/0x1a8
[c000000000a23960] [c00000000008dfa4] .do_exit+0x98/0x73c
[c000000000a23a40] [c0000000000293f4] .die+0x280/0x284
[c000000000a23ae0] [c000000000032700] .bad_page_fault+0xb8/0xd4
[c000000000a23b60] [c000000000005798] handle_page_fault+0x3c/0x5c
--- Exception: 300 at .pidmap_init+0x28/0x88
LR = .start_kernel+0x458/0x51c
[c000000000a23e50] [c000000000a23ee0] init_thread_union+0x3ee0/0x4000
(unreliable)
[c000000000a23ee0] [c0000000007b0bbc] .start_kernel+0x458/0x51c
[c000000000a23f90] [c0000000000083d8] .start_here_common+0x1c/0x44
Rebooting in 180 seconds..
The page size is 64K. Config DEBUG_PAGEALLOC is enabled. Let me know
if i can provide any more information.
Thanks
-Sachin
--
---------------------------------
Sachin Sant
IBM Linux Technology Center
India Systems and Technology Labs
Bangalore, India
---------------------------------
^ permalink raw reply
* Re: [PATCH] [MTD] ofpart: Partitions at same address cannot have thesame name v3
From: Segher Boessenkool @ 2009-04-29 13:56 UTC (permalink / raw)
To: Ricardo Ribalda Delgado; +Cc: Scott Wood, linuxppc-dev, David.Woodhouse
In-Reply-To: <aa76a2be0904290041m27d6309eu76d04d294ca9ba3d@mail.gmail.com>
>> Your special "partition" isn't really a partition then, is it.
>> Because of that, device nodes to represent your partitions doesn't
>> work very well.
>
> I think that they work pretty well.
With "real" devices you don't normally have two devices sitting at
the same address. Since you _do_ have that with your partitions,
it doesn't fit the device node abstraction very well.
> Unfortunately, since
> 4b08e149c0e02e97ec49c2a31d14a0d3a02f8074 all the partiton must be
> named "partition"
Ah! After writing my original reply, I read the documentation,
and this had me confused.
4b08e14 looks wrong to me. It also didn't update the documentation.
>> You really want to use something else, a partition table on the
>> flash itself for example. Or maybe the (platform? MTD?) code
>> should create a Linux device for the "full" device.
>
> This wont be very flexible. With the device tree aproach we can define
> partitions not only for the full flash, but also for two partitions
> merged, a partition inside a partition....
Well, except you have problems doing just that :-P
>>> Because two nodes of a device tree cannot have the same name,
>>
>> This isn't true.
>
> Are you sure?
Yes.
> This is what I get if I try to compile a device tree
> with two partitions with the same name starting at the same address.
>
> $ arch/powerpc/boot/dtc -O dtb -b 0 -p 1024
> arch/powerpc/boot/dts/q5-avnet.dts -o /tmp/kk
> DTC: dts->dtb on file "arch/powerpc/boot/dts/q5-avnet.dts"
> ERROR (duplicate_node_names): Duplicate node name
> /plb@0/flash@ff000000/partition@ff000000
> ERROR: Input tree has errors, aborting (use -f to force output)
I think this error is trying to say both the names and the unit
addresses are identical (and the latter exist), which isn't
technically incorrect, but not very useful either.
>>> but all the
>>> partitions must be named "partition",
>>
>> Bad binding, no cookie for you!
>
> Sorry, I dont understand want you want to say here.
I was trying to say that if the "partition" binding says the "name"
of every partition node should be "partition", then it is a very
bad binding. The binding does _not_ say that though, the code is
wrong.
>> You cannot claim a name as generic as "partition" for this. Pick
>> something else if you really must do things this way.
>
> You choose :)
Picking good names is hard work (more than 50% of all programming, heh).
You choose :-) [Hint: something with a comma, maybe
"linux,mtd,partition"
or similar -- I don't really care. OTOH, it seems you won't need this
at all].
Segher
^ permalink raw reply
* Re: [PATCH] i2c-cpm: Pass dev ptr to dma_*_coherent rather than NULL
From: Kumar Gala @ 2009-04-29 13:43 UTC (permalink / raw)
To: Ben Dooks; +Cc: Linuxppc-dev Development, linux-i2c, Mark Ware
In-Reply-To: <20090422215646.GA19997@trinity.fluff.org>
On Apr 22, 2009, at 4:56 PM, Ben Dooks wrote:
> On Tue, Apr 21, 2009 at 10:11:51AM -0500, Kumar Gala wrote:
>>
>> On Apr 21, 2009, at 7:49 AM, Mark Ware wrote:
>>
>>> Recent DMA changes result in a BUG() when NULL is passed to
>>> dma_alloc_coherent in place of a device.
>>>
>>> Signed-off-by: Mark Ware <mware@elphinstone.net>
>>> ---
>>>
>>> This patch fixes the BUG() during boot that has appeared during the
>>> 2.6.30 window. It has been tested and appears correct on my 8280
>>> based
>>> board.
>>> Sent to both linuxppc-dev and linux-i2c, since I'm not sure where it
>>> belongs.
>>>
>>>
>>> drivers/i2c/busses/i2c-cpm.c | 14 ++++++++------
>>> 1 files changed, 8 insertions(+), 6 deletions(-)
>>
>> Acked-by: Kumar Gala <galak@kernel.crashing.org>
>>
>> Ben, I'm expecting you to pick this up unless you tell me otherwise.
>
> Yes.
This go in yet?
- k
^ permalink raw reply
* Re: [PATCH] powerpc: Update MPC5xxx and Xilinx Virtex maintainer entries
From: Grant Likely @ 2009-04-29 13:37 UTC (permalink / raw)
To: Sylvain Munaut; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <49F801AF.1060404@246tNt.com>
On Wed, Apr 29, 2009 at 1:28 AM, Sylvain Munaut <tnt@246tnt.com> wrote:
> Grant Likely wrote:
>> From: Grant Likely <grant.likely@secretlab.ca>
>>
>> - Add git tree URLs
>> - Drop Sylvain from the 5xxx maintainers list. =A0He hasn't been active
>> =A0 for a while now.
>>
>> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
>
> Confirmed.
Thanks Sylvain.
g.
>
>> ---
>>
>> =A0MAINTAINERS | =A0 =A04 ++--
>> =A01 files changed, 2 insertions(+), 2 deletions(-)
>>
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index ef03abe..4a8d367 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -3434,11 +3434,10 @@ L: =A0 =A0linuxppc-dev@ozlabs.org
>> =A0S: =A0 Maintained
>>
>> =A0LINUX FOR POWERPC EMBEDDED MPC5XXX
>> -P: =A0 Sylvain Munaut
>> -M: =A0 tnt@246tNt.com
>> =A0P: =A0 Grant Likely
>> =A0M: =A0 grant.likely@secretlab.ca
>> =A0L: =A0 linuxppc-dev@ozlabs.org
>> +T: =A0 git git://git.secretlab.ca/git/linux-2.6.git
>> =A0S: =A0 Maintained
>>
>> =A0LINUX FOR POWERPC EMBEDDED PPC4XX
>> @@ -3456,6 +3455,7 @@ P: =A0 =A0 =A0Grant Likely
>> =A0M: =A0 grant.likely@secretlab.ca
>> =A0W: =A0 http://wiki.secretlab.ca/index.php/Linux_on_Xilinx_Virtex
>> =A0L: =A0 linuxppc-dev@ozlabs.org
>> +T: =A0 git git://git.secretlab.ca/git/linux-2.6.git
>> =A0S: =A0 Maintained
>>
>> =A0LINUX FOR POWERPC EMBEDDED PPC8XX
>>
>
>
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* [PATCH v6] powerpc/85xx: Add P2020DS board support
From: Kumar Gala @ 2009-04-29 13:29 UTC (permalink / raw)
To: linuxppc-dev
The P2020 is a dual e500v2 core based SOC with:
* 3 PCIe controllers
* 2 General purpose DMA controllers
* 2 sRIO controllers
* 3 eTSECS
* USB 2.0
* SDHC
* SPI, I2C, DUART
* enhanced localbus
* and optional Security (P2020E) security w/XOR acceleration
The p2020 DS reference board is pretty similar to the existing MPC85xx
DS boards and has a ULI 1575 connected on one of the PCIe controllers.
Signed-off-by: Ted Peters <Ted.Peters@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
* Added new ecm bindings
* sorted soc node by address
* added gpio, espi, and sdhci nodes
- k
arch/powerpc/boot/dts/p2020ds.dts | 704 ++++++++++++++++++++++++++++++
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 43 ++-
arch/powerpc/platforms/fsl_uli1575.c | 1 +
arch/powerpc/sysdev/fsl_pci.c | 2 +
include/linux/pci_ids.h | 2 +
5 files changed, 747 insertions(+), 5 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p2020ds.dts
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
new file mode 100644
index 0000000..9982c19
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -0,0 +1,704 @@
+/*
+ * P2020 DS Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = "fsl,P2020";
+ compatible = "fsl,P2020DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P2020@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,P2020@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ localbus@ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
+ 0x1 0x0 0x0 0xe0000000 0x08000000
+ 0x2 0x0 0x0 0xffa00000 0x00040000
+ 0x3 0x0 0x0 0xffdf0000 0x00008000
+ 0x4 0x0 0x0 0xffa40000 0x00040000
+ 0x5 0x0 0x0 0xffa80000 0x00040000
+ 0x6 0x0 0x0 0xffac0000 0x00040000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ ramdisk@0 {
+ reg = <0x0 0x03000000>;
+ read-only;
+ };
+
+ diagnostic@3000000 {
+ reg = <0x03000000 0x00e00000>;
+ read-only;
+ };
+
+ dink@3e00000 {
+ reg = <0x03e00000 0x00200000>;
+ read-only;
+ };
+
+ kernel@4000000 {
+ reg = <0x04000000 0x00400000>;
+ read-only;
+ };
+
+ jffs2@4400000 {
+ reg = <0x04400000 0x03b00000>;
+ };
+
+ dtb@7f00000 {
+ reg = <0x07f00000 0x00080000>;
+ read-only;
+ };
+
+ u-boot@7f80000 {
+ reg = <0x07f80000 0x00080000>;
+ read-only;
+ };
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x2 0x0 0x40000>;
+
+ u-boot@0 {
+ reg = <0x0 0x02000000>;
+ read-only;
+ };
+
+ jffs2@2000000 {
+ reg = <0x02000000 0x10000000>;
+ };
+
+ ramdisk@12000000 {
+ reg = <0x12000000 0x08000000>;
+ read-only;
+ };
+
+ kernel@1a000000 {
+ reg = <0x1a000000 0x04000000>;
+ };
+
+ dtb@1e000000 {
+ reg = <0x1e000000 0x01000000>;
+ read-only;
+ };
+
+ empty@1f000000 {
+ reg = <0x1f000000 0x21000000>;
+ };
+ };
+
+ nand@4,0 {
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x4 0x0 0x40000>;
+ };
+
+ nand@5,0 {
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x5 0x0 0x40000>;
+ };
+
+ nand@6,0 {
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x6 0x0 0x40000>;
+ };
+ };
+
+ soc@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p2020-immr", "simple-bus";
+ ranges = <0x0 0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,p2020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,p2020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ spi@7000 {
+ compatible = "fsl,espi";
+ reg = <0x7000 0x1000>;
+ interrupts = <59 0x2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ dma@c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <76 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <77 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <78 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <79 2>;
+ };
+ };
+
+ gpio: gpio-controller@f000 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x100>;
+ interrupts = <47 0x2>;
+ interrupt-parent = <&mpic>;
+ gpio-controller;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,p2020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512k
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ usb@22000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x22000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <28 0x2>;
+ phy_type = "ulpi";
+ };
+
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x2>;
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet2: ethernet@26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 32 2 33 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy2>;
+ phy-connection-type = "rgmii-id";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi2: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ sdhci@2e000 {
+ compatible = "fsl,mpc8536-esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi@41600 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,p2020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie@ffe08000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe08000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <24 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0x0 0x0 0x1 &mpic 0x8 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x9 0x1
+ 0000 0x0 0x0 0x3 &mpic 0xa 0x1
+ 0000 0x0 0x0 0x4 &mpic 0xb 0x1
+ >;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+
+ pci1: pcie@ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+ interrupt-map = <
+
+ // IDSEL 0x11 func 0 - PCI slot 1
+ 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 1 - PCI slot 1
+ 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 2 - PCI slot 1
+ 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 3 - PCI slot 1
+ 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 4 - PCI slot 1
+ 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 5 - PCI slot 1
+ 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 6 - PCI slot 1
+ 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 7 - PCI slot 1
+ 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x1d Audio
+ 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
+
+ // IDSEL 0x1e Legacy
+ 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+ 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
+
+ // IDSEL 0x1f IDE/SATA
+ 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+ 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
+ >;
+
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ uli1575@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ isa@1e {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <0xf000 0x0 0x0 0x0 0x0>;
+ ranges = <0x1 0x0 0x1000000 0x0 0x0
+ 0x1000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller@20 {
+ reg = <0x1 0x20 0x2
+ 0x1 0xa0 0x2
+ 0x1 0x4d0 0x2>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "chrp,iic";
+ interrupts = <4 1>;
+ interrupt-parent = <&mpic>;
+ };
+
+ i8042@60 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+ interrupts = <1 3 12 3>;
+ interrupt-parent =
+ <&i8259>;
+
+ keyboard@0 {
+ reg = <0x0>;
+ compatible = "pnpPNP,303";
+ };
+
+ mouse@1 {
+ reg = <0x1>;
+ compatible = "pnpPNP,f03";
+ };
+ };
+
+ rtc@70 {
+ compatible = "pnpPNP,b00";
+ reg = <0x1 0x70 0x2>;
+ };
+
+ gpio@400 {
+ reg = <0x1 0x400 0x80>;
+ };
+ };
+ };
+ };
+
+ };
+
+ pci2: pcie@ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x3 0x1
+ >;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index de66de7..53d5851 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -163,7 +163,8 @@ static void __init mpc85xx_ds_setup_arch(void)
#ifdef CONFIG_PCI
for_each_node_by_type(np, "pci") {
if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
- of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
+ of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
+ of_device_is_compatible(np, "fsl,p2020-pcie")) {
struct resource rsrc;
of_address_to_resource(np, 0, &rsrc);
if ((rsrc.start & 0xfffff) == primary_phb_addr)
@@ -195,9 +196,9 @@ static int __init mpc8544_ds_probe(void)
primary_phb_addr = 0xb000;
#endif
return 1;
- } else {
- return 0;
}
+
+ return 0;
}
static struct of_device_id __initdata mpc85xxds_ids[] = {
@@ -214,6 +215,7 @@ static int __init mpc85xxds_publish_devices(void)
}
machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices);
+machine_device_initcall(p2020_ds, mpc85xxds_publish_devices);
/*
* Called very early, device-tree isn't unflattened
@@ -227,9 +229,26 @@ static int __init mpc8572_ds_probe(void)
primary_phb_addr = 0x8000;
#endif
return 1;
- } else {
- return 0;
}
+
+ return 0;
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p2020_ds_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) {
+#ifdef CONFIG_PCI
+ primary_phb_addr = 0x9000;
+#endif
+ return 1;
+ }
+
+ return 0;
}
define_machine(mpc8544_ds) {
@@ -259,3 +278,17 @@ define_machine(mpc8572_ds) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p2020_ds) {
+ .name = "P2020 DS",
+ .probe = p2020_ds_probe,
+ .setup_arch = mpc85xx_ds_setup_arch,
+ .init_IRQ = mpc85xx_ds_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/fsl_uli1575.c b/arch/powerpc/platforms/fsl_uli1575.c
index df83dc9..2437e95 100644
--- a/arch/powerpc/platforms/fsl_uli1575.c
+++ b/arch/powerpc/platforms/fsl_uli1575.c
@@ -55,6 +55,7 @@ static inline bool is_quirk_valid(void)
{
return (machine_is(mpc86xx_hpcn) ||
machine_is(mpc8544_ds) ||
+ machine_is(p2020_ds) ||
machine_is(mpc8572_ds));
}
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 78021d8..36db7b3 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -296,6 +296,8 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
#endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */
#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 06ba90c..36a1dd0 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2286,6 +2286,8 @@
#define PCI_DEVICE_ID_MPC8572 0x0041
#define PCI_DEVICE_ID_MPC8536E 0x0050
#define PCI_DEVICE_ID_MPC8536 0x0051
+#define PCI_DEVICE_ID_P2020E 0x0070
+#define PCI_DEVICE_ID_P2020 0x0071
#define PCI_DEVICE_ID_MPC8641 0x7010
#define PCI_DEVICE_ID_MPC8641D 0x7011
#define PCI_DEVICE_ID_MPC8610 0x7018
--
1.6.0.6
^ permalink raw reply related
* Re: [PATCH 1/6] powerpc: Move #ifdef'ed body of do_IRQ() into a separate function
From: Kumar Gala @ 2009-04-29 12:48 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: linuxppc-dev Development
In-Reply-To: <20090429114448.GA13129@lst.de>
On Apr 29, 2009, at 6:44 AM, Christoph Hellwig wrote:
> On Tue, Apr 28, 2009 at 10:49:07AM +1000, Michael Ellerman wrote:
>> On Sat, 2009-04-25 at 20:18 +0200, Christoph Hellwig wrote:
>>> On Thu, Apr 23, 2009 at 11:31:37AM +1000, Michael Ellerman wrote:
>>>> +#ifdef CONFIG_IRQSTACKS
>>>
>>> Wasn't there a plan to make CONFIG_IRQSTACKS the unconditional
>>> default?
>>
>> Not sure. Looks like the 64-bit configs all turn it on, and all but
>> one
>> or two of the 32-bit configs don't.
>
> Yeah, but do they have a reason not to turn it on? Having irqstacks
> is a lot safer than no having it because the stack useage is a lot
> more
> predictable. And not having to maintain two codepathes is also a
> benefit all by itself.
I think Ben, Paul and I had discussed just universally enabling it.
Can't remember why Ben hadn't done that yet.
- k
^ permalink raw reply
* Re: bug in drivers/edac/mpc85xx_edac.c:mpc85xx_mc_check()
From: Kumar Gala @ 2009-04-29 12:46 UTC (permalink / raw)
To: Andrew Morton
Cc: Jeff Haran, linux-kernel, Dave Jiang, linuxppc-dev, Doug Thompson,
Kumar Gala
In-Reply-To: <20090429003704.1c37d6e1.akpm@linux-foundation.org>
On Apr 29, 2009, at 2:37 AM, Andrew Morton wrote:
> Let's cc the suitable people.
>
> On Tue, 28 Apr 2009 18:23:42 -0700 "Jeff Haran" <jharan@Brocade.COM>
> wrote:
>
>> Hi,
>>
>> Recent versions of this function contain the following snippets:
>>
>> if (err_detect & DDR_EDE_SBE)
>> edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK,
>> syndrome, row_index, 0, mci->ctl_name);
>>
>> if (err_detect & DDR_EDE_MBE)
>> edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK,
>> row_index, mci->ctl_name);
>>
>> I am pretty sure the references to PAGE_MASK should be proceeded by a
>> tilda, as in:
>>
>> if (err_detect & DDR_EDE_SBE)
>> edac_mc_handle_ce(mci, pfn, err_addr & ~PAGE_MASK,
>> syndrome, row_index, 0, mci->ctl_name);
>>
>> if (err_detect & DDR_EDE_MBE)
>> edac_mc_handle_ue(mci, pfn, err_addr & ~PAGE_MASK,
>> row_index, mci->ctl_name);
>>
>
> Could well be. PAGE_MASK is very easy to get wrong. I've _never_
> trusted my own memory of it and I always have to go back to the
> definition when reviewing code :(
This should ~PAGE_MASK to get the offset into the page.
>> Much as I would like to submit a tested patch like the rest of the
>> world, I find myself in the situation where the only Freescale target
>> system I have to test on is running a 3 year old kernel (2.6.14),
>> which
>> preceeds the introduction of EDAC driver support, at least for
>> Freescale. So the best I can do is borrow from the new EDAC driver
>> and
>> backport it to the old kernel.
>>
>> But I have learned a few things in this process and can thus share
>> what
>> I've learned as it may be of help to the EDAC driver developers:
>>
>> 1) Before you read the Freescale 8548 CAPTURE_ADDRESS register, you
>> want
>> to read CAPTURE_ATTRIBUTES first and make sure the VLD bit (least
>> significant bit in the register) is set or else the data in
>> CAPTURE_ADDRESS may not be yet valid.
>>
>> 2) When you are done scrubbing the memory with the single bit
>> error, you
>> want to write 0 to CAPTURE_ATTRIBUTES so as to clear VLD and thus
>> setup
>> the ECC capture logic to capture the next single bit error.
This is a correct description based on how FSL error HW works.
- k
^ permalink raw reply
* Re: [PATCH] powerpc: Keep track of emulated instructions
From: Geert Uytterhoeven @ 2009-04-29 12:43 UTC (permalink / raw)
To: Kumar Gala; +Cc: Linux/PPC Development
In-Reply-To: <alpine.LRH.2.00.0904061430090.11076@vixen.sonytel.be>
On Mon, 6 Apr 2009, Geert Uytterhoeven wrote:
> On Fri, 3 Apr 2009, Kumar Gala wrote:
> > On Apr 3, 2009, at 7:08 AM, Geert Uytterhoeven wrote:
> > >Finally (after ca. 1.5 years), he're an updated version of my patch to keep
> > >track of emulated instructions. In the light of Kumar's `Emulate enough of
> > >SPE
> > >instructions to make gcc happy' patch, he probably also wants to keep track
> > >of
> > >the actual runtime overhead.
> > >
> > >Changes since last version:
> > > - arch/powerpc/kernel/sysfs.c is now compiled on ppc32, so we can provide
> > > counters in sysfs on ppc32, too,
> > > - WARN_EMULATED() is a no-op if CONFIG_SYSCTL is disabled,
> > > - Add warnings for altivec,
> > > - Add warnings for recently introduced emulation of vsx and isel
> > > instructions.
> >
> > pretty cool. Do we think counters should be sysfs or debugfs?
>
> What do you prefer?
>
> On MIPS, unaligned exception handling control is in debugfs.
And probably debugfs is better, so it's disabled on production systems.
But I would drop the per-CPU counters, and keep global counters only, for
simplicity.
> > Also it would be nice to be able to zero out the counters.
>
> By writing to the individual counters, or by writing to a global `clear' file?
With debugfs, it's quite easy to make them writable, so you can easily clear
them by writing zeroes to the virtual files.
If people agree, I'll find a time hole and start updating the code...
With kind regards,
Geert Uytterhoeven
Software Architect
Techsoft Centre
Technology and Software Centre Europe
The Corporate Village · Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium
Phone: +32 (0)2 700 8453
Fax: +32 (0)2 700 8622
E-mail: Geert.Uytterhoeven@sonycom.com
Internet: http://www.sony-europe.com/
A division of Sony Europe (Belgium) N.V.
VAT BE 0413.825.160 · RPR Brussels
Fortis · BIC GEBABEBB · IBAN BE41293037680010
^ permalink raw reply
* Re: [PATCH 2/2] powerpc: Move VSX load/stores into ppc-opcode.h
From: Kumar Gala @ 2009-04-29 12:38 UTC (permalink / raw)
To: Michael Neuling; +Cc: Paul Mackerras, Milton Miller, linuxppc-dev
In-Reply-To: <20090429072040.A3C761222D@localhost.localdomain>
On Apr 29, 2009, at 2:20 AM, Michael Neuling wrote:
> Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
> ===================================================================
> --- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/ppc-opcode.h
> +++ linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
> @@ -49,6 +49,7 @@
> /* macros to insert fields into opcodes */
> #define __PPC_RA(a) (((a) & 0x1f) << 16)
> #define __PPC_RB(b) (((b) & 0x1f) << 11)
> +#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
> #define __PPC_T_TLB(t) (((t) & 0x3) << 21)
> #define __PPC_WC(w) (((w) & 0x3) << 21)
>
> @@ -70,4 +71,12 @@
> #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
> __PPC_WC(w))
>
> +/*
> + * Define what the VSX XX1 form instructions will look like, then add
> + * the 128 bit load store instructions based on that.
> + */
> +#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
> +#define STXVD2X(s, a, b) .long (0x7c000798 | VSX_XX1((s), (a), (b)))
> +#define LXVD2X(s, a, b) .long (0x7c000698 | VSX_XX1((s), (a), (b)))
> +
previous gripe of matching style of file for the .long 0x7c000798
- k
^ permalink raw reply
* Re: [PATCH] therm_windtunnel: Convert to a new-style i2c driver
From: Jean Delvare @ 2009-04-29 12:25 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20090416230101.37f3e84f@hyperion.delvare>
On Thu, 16 Apr 2009 23:01:01 +0200, Jean Delvare wrote:
> The legacy i2c binding model is going away soon, so convert the ppc
> therm_windtunnel driver to the new model or it will break.
>
> Signed-off-by: Jean Delvare <khali@linux-fr.org>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> ---
> Can someone please test this patch for me? I could only build-test it.
>
> Remember that you need this patch applied:
> http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=935298696f469c0e07c73be687bd055878074ce0
Paul, any progress on this?
> Thanks.
>
> drivers/macintosh/therm_windtunnel.c | 126 ++++++++++++++++------------------
> 1 file changed, 60 insertions(+), 66 deletions(-)
>
> --- linux-2.6.30-rc2.orig/drivers/macintosh/therm_windtunnel.c 2009-03-24 13:40:47.000000000 +0100
> +++ linux-2.6.30-rc2/drivers/macintosh/therm_windtunnel.c 2009-04-16 22:56:39.000000000 +0200
> @@ -48,16 +48,6 @@
>
> #define LOG_TEMP 0 /* continously log temperature */
>
> -static int do_probe( struct i2c_adapter *adapter, int addr, int kind);
> -
> -/* scan 0x48-0x4f (DS1775) and 0x2c-2x2f (ADM1030) */
> -static const unsigned short normal_i2c[] = { 0x48, 0x49, 0x4a, 0x4b,
> - 0x4c, 0x4d, 0x4e, 0x4f,
> - 0x2c, 0x2d, 0x2e, 0x2f,
> - I2C_CLIENT_END };
> -
> -I2C_CLIENT_INSMOD;
> -
> static struct {
> volatile int running;
> struct task_struct *poll_task;
> @@ -315,53 +305,54 @@ static int control_loop(void *dummy)
> static int
> do_attach( struct i2c_adapter *adapter )
> {
> - int ret = 0;
> + /* scan 0x48-0x4f (DS1775) and 0x2c-2x2f (ADM1030) */
> + static const unsigned short scan_ds1775[] = {
> + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
> + I2C_CLIENT_END
> + };
> + static const unsigned short scan_adm1030[] = {
> + 0x2c, 0x2d, 0x2e, 0x2f,
> + I2C_CLIENT_END
> + };
>
> if( strncmp(adapter->name, "uni-n", 5) )
> return 0;
>
> if( !x.running ) {
> - ret = i2c_probe( adapter, &addr_data, &do_probe );
> + struct i2c_board_info info;
> +
> + memset(&info, 0, sizeof(struct i2c_board_info));
> + strlcpy(info.type, "therm_ds1775", I2C_NAME_SIZE);
> + i2c_new_probed_device(adapter, &info, scan_ds1775);
> +
> + strlcpy(info.type, "therm_adm1030", I2C_NAME_SIZE);
> + i2c_new_probed_device(adapter, &info, scan_adm1030);
> +
> if( x.thermostat && x.fan ) {
> x.running = 1;
> x.poll_task = kthread_run(control_loop, NULL, "g4fand");
> }
> }
> - return ret;
> + return 0;
> }
>
> static int
> -do_detach( struct i2c_client *client )
> +do_remove(struct i2c_client *client)
> {
> - int err;
> -
> - if( (err=i2c_detach_client(client)) )
> - printk(KERN_ERR "failed to detach thermostat client\n");
> - else {
> - if( x.running ) {
> - x.running = 0;
> - kthread_stop(x.poll_task);
> - x.poll_task = NULL;
> - }
> - if( client == x.thermostat )
> - x.thermostat = NULL;
> - else if( client == x.fan )
> - x.fan = NULL;
> - else {
> - printk(KERN_ERR "g4fan: bad client\n");
> - }
> - kfree( client );
> + if (x.running) {
> + x.running = 0;
> + kthread_stop(x.poll_task);
> + x.poll_task = NULL;
> }
> - return err;
> -}
> + if (client == x.thermostat)
> + x.thermostat = NULL;
> + else if (client == x.fan)
> + x.fan = NULL;
> + else
> + printk(KERN_ERR "g4fan: bad client\n");
>
> -static struct i2c_driver g4fan_driver = {
> - .driver = {
> - .name = "therm_windtunnel",
> - },
> - .attach_adapter = do_attach,
> - .detach_client = do_detach,
> -};
> + return 0;
> +}
>
> static int
> attach_fan( struct i2c_client *cl )
> @@ -374,13 +365,8 @@ attach_fan( struct i2c_client *cl )
> goto out;
> printk("ADM1030 fan controller [@%02x]\n", cl->addr );
>
> - strlcpy( cl->name, "ADM1030 fan controller", sizeof(cl->name) );
> -
> - if( !i2c_attach_client(cl) )
> - x.fan = cl;
> + x.fan = cl;
> out:
> - if( cl != x.fan )
> - kfree( cl );
> return 0;
> }
>
> @@ -412,39 +398,47 @@ attach_thermostat( struct i2c_client *cl
> x.temp = temp;
> x.overheat_temp = os_temp;
> x.overheat_hyst = hyst_temp;
> -
> - strlcpy( cl->name, "DS1775 thermostat", sizeof(cl->name) );
> -
> - if( !i2c_attach_client(cl) )
> - x.thermostat = cl;
> + x.thermostat = cl;
> out:
> - if( cl != x.thermostat )
> - kfree( cl );
> return 0;
> }
>
> +enum chip { ds1775, adm1030 };
> +
> +static const struct i2c_device_id therm_windtunnel_id[] = {
> + { "therm_ds1775", ds1775 },
> + { "therm_adm1030", adm1030 },
> + { }
> +};
> +
> static int
> -do_probe( struct i2c_adapter *adapter, int addr, int kind )
> +do_probe(struct i2c_client *cl, const struct i2c_device_id *id)
> {
> - struct i2c_client *cl;
> + struct i2c_adapter *adapter = cl->adapter;
>
> if( !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA
> | I2C_FUNC_SMBUS_WRITE_BYTE) )
> return 0;
>
> - if( !(cl=kzalloc(sizeof(*cl), GFP_KERNEL)) )
> - return -ENOMEM;
> -
> - cl->addr = addr;
> - cl->adapter = adapter;
> - cl->driver = &g4fan_driver;
> - cl->flags = 0;
> -
> - if( addr < 0x48 )
> + switch (id->driver_data) {
> + case adm1030:
> return attach_fan( cl );
> - return attach_thermostat( cl );
> + case ds1775:
> + return attach_thermostat(cl);
> + }
> + return 0;
> }
>
> +static struct i2c_driver g4fan_driver = {
> + .driver = {
> + .name = "therm_windtunnel",
> + },
> + .attach_adapter = do_attach,
> + .probe = do_probe,
> + .remove = do_remove,
> + .id_table = therm_windtunnel_id,
> +};
> +
>
> /************************************************************************/
> /* initialization / cleanup */
>
>
--
Jean Delvare
^ permalink raw reply
* Re: [PATCH 1/6] powerpc: Move #ifdef'ed body of do_IRQ() into a separate function
From: Christoph Hellwig @ 2009-04-29 11:44 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Christoph Hellwig
In-Reply-To: <1240879747.11027.2.camel@localhost>
On Tue, Apr 28, 2009 at 10:49:07AM +1000, Michael Ellerman wrote:
> On Sat, 2009-04-25 at 20:18 +0200, Christoph Hellwig wrote:
> > On Thu, Apr 23, 2009 at 11:31:37AM +1000, Michael Ellerman wrote:
> > > +#ifdef CONFIG_IRQSTACKS
> >
> > Wasn't there a plan to make CONFIG_IRQSTACKS the unconditional default?
>
> Not sure. Looks like the 64-bit configs all turn it on, and all but one
> or two of the 32-bit configs don't.
Yeah, but do they have a reason not to turn it on? Having irqstacks
is a lot safer than no having it because the stack useage is a lot more
predictable. And not having to maintain two codepathes is also a
benefit all by itself.
^ permalink raw reply
* Re: Next April 28: boot failure on PowerPC with SLQB
From: Nick Piggin @ 2009-04-29 11:36 UTC (permalink / raw)
To: Pekka Enberg
Cc: Stephen Rothwell, Christoph Lameter, linux-kernel, linuxppc-dev,
linux-next
In-Reply-To: <84144f020904280422s6a9a277fjc4619c904f37e5ca@mail.gmail.com>
On Tue, Apr 28, 2009 at 02:22:06PM +0300, Pekka Enberg wrote:
> Nick,
>
> Here's another one. I think we need to either fix these rather quickly
> or make SLUB the defaut for linux-next again so we don't interfere
> with other testing.
>
> Pekka
>
> On Tue, Apr 28, 2009 at 2:10 PM, Sachin Sant <sachinp@in.ibm.com> wrote:
> > Today's next tree fails to boot on variety of powerpc boxes (Power5, power6)
> >
> > Memory: 3882624k/4194304k available (8384k kernel code, 311680k reserved,
> > 2048k data, 4285k bss, 512k init)
> > Kernel panic - not syncing: kmem_cache_create(): failed to create slab
> > `kmalloc'
> >
> > Call Trace:
> > [c000000000a33c30] [c000000000011668] .show_stack+0x6c/0x16c (unreliable)
> > [c000000000a33ce0] [c000000000563c8c] .panic+0x80/0x1a8
> > [c000000000a33d70] [c0000000001410d8] .kmem_cache_open+0x4e8/0x51c
> > [c000000000a33e20] [c0000000007d90b8] .kmem_cache_init+0x264/0x35c
> > [c000000000a33ee0] [c0000000007b0b68] .start_kernel+0x404/0x51c
> > [c000000000a33f90] [c0000000000083d8] .start_here_common+0x1c/0x44
OK I think the problem is that with 64K pages you get a default MAX_ORDER
of 9, and slqb is trying to create slabs which exceed that size..
Does this help?
---
SLQB: fix slab calculation
SLQB didn't consider MAX_ORDER when defining which sizes of kmalloc
slabs to create. It panics at boot if it tries to create a cache
which exceeds MAX_ORDER-1.
Signed-off-by: Nick Piggin <npiggin@suse.de>
---
Index: linux-2.6/include/linux/slqb_def.h
===================================================================
--- linux-2.6.orig/include/linux/slqb_def.h 2009-04-29 21:27:30.000000000 +1000
+++ linux-2.6/include/linux/slqb_def.h 2009-04-29 21:28:13.000000000 +1000
@@ -172,7 +172,8 @@ struct kmem_cache {
#endif
#define KMALLOC_SHIFT_LOW ilog2(KMALLOC_MIN_SIZE)
-#define KMALLOC_SHIFT_SLQB_HIGH (PAGE_SHIFT + 9)
+#define KMALLOC_SHIFT_SLQB_HIGH ((PAGE_SHIFT + 9) < MAX_ORDER ? \
+ (PAGE_SHIFT + 9) : (MAX_ORDER - 1))
extern struct kmem_cache kmalloc_caches[KMALLOC_SHIFT_SLQB_HIGH + 1];
extern struct kmem_cache kmalloc_caches_dma[KMALLOC_SHIFT_SLQB_HIGH + 1];
^ permalink raw reply
* FSL Driver load issues with OF
From: Benjamin Zores @ 2009-04-29 9:45 UTC (permalink / raw)
To: linuxppc-dev
Hi there,
Since the progressive migration of some PPC drivers to use of_platform bus
(typically migrating OF parsing from fsl_soc.c to the device probe/init
functions),
I'm experiencing driver load issues.
Actually, I'm not longer able to load of these drivers as the probe()
function is never called.
Everything goes fine if I put code back to fsl_soc.c with the
arch_initcall() command.
Example of drivers that do no longer load for me: gianfar, talitos ...
Is there something obvious that I've missed ?
Ben
^ permalink raw reply
* Re: [PATCH] [MTD] ofpart: Partitions at same address cannot have thesame name v3
From: Ricardo Ribalda Delgado @ 2009-04-29 7:41 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Scott Wood, linuxppc-dev, David.Woodhouse
In-Reply-To: <0F60D78C-63E2-4A8A-9EBE-80AAFB3B00A0@kernel.crashing.org>
Hello Segher
Thanks for your comments.
>
> Your special "partition" isn't really a partition then, is it.
> Because of that, device nodes to represent your partitions doesn't
> work very well.
I think that they work pretty well. Unfortunately, since
4b08e149c0e02e97ec49c2a31d14a0d3a02f8074 all the partiton must be
named "partition"
>
> You really want to use something else, a partition table on the
> flash itself for example. =A0Or maybe the (platform? MTD?) code
> should create a Linux device for the "full" device.
This wont be very flexible. With the device tree aproach we can define
partitions not only for the full flash, but also for two partitions
merged, a partition inside a partition....
>
>> Because two nodes of a device tree cannot have the same name,
>
> This isn't true.
Are you sure? This is what I get if I try to compile a device tree
with two partitions with the same name starting at the same address.
$ arch/powerpc/boot/dtc -O dtb -b 0 -p 1024
arch/powerpc/boot/dts/q5-avnet.dts -o /tmp/kk
DTC: dts->dtb on file "arch/powerpc/boot/dts/q5-avnet.dts"
ERROR (duplicate_node_names): Duplicate node name
/plb@0/flash@ff000000/partition@ff000000
ERROR: Input tree has errors, aborting (use -f to force output)
>
>> but all the
>> partitions must be named "partition",
>
> Bad binding, no cookie for you!
Sorry, I dont understand want you want to say here.
> You cannot claim a name as generic as "partition" for this. =A0Pick
> something else if you really must do things this way.
You choose :)
Best regards
--=20
Ricardo Ribalda
http://www.eps.uam.es/~rribalda/
^ permalink raw reply
* Re: bug in drivers/edac/mpc85xx_edac.c:mpc85xx_mc_check()
From: Andrew Morton @ 2009-04-29 7:37 UTC (permalink / raw)
To: Jeff Haran
Cc: Doug, linux-kernel, Dave Jiang, linuxppc-dev, Thompson,
Kumar Gala
In-Reply-To: <57AC2FA1761300418C7AB8F3EA493C9702E319DB@HQ-EXCH-5.corp.brocade.com>
Let's cc the suitable people.
On Tue, 28 Apr 2009 18:23:42 -0700 "Jeff Haran" <jharan@Brocade.COM> wrote:
> Hi,
>
> Recent versions of this function contain the following snippets:
>
> if (err_detect & DDR_EDE_SBE)
> edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK,
> syndrome, row_index, 0, mci->ctl_name);
>
> if (err_detect & DDR_EDE_MBE)
> edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK,
> row_index, mci->ctl_name);
>
> I am pretty sure the references to PAGE_MASK should be proceeded by a
> tilda, as in:
>
> if (err_detect & DDR_EDE_SBE)
> edac_mc_handle_ce(mci, pfn, err_addr & ~PAGE_MASK,
> syndrome, row_index, 0, mci->ctl_name);
>
> if (err_detect & DDR_EDE_MBE)
> edac_mc_handle_ue(mci, pfn, err_addr & ~PAGE_MASK,
> row_index, mci->ctl_name);
>
Could well be. PAGE_MASK is very easy to get wrong. I've _never_
trusted my own memory of it and I always have to go back to the
definition when reviewing code :(
> Much as I would like to submit a tested patch like the rest of the
> world, I find myself in the situation where the only Freescale target
> system I have to test on is running a 3 year old kernel (2.6.14), which
> preceeds the introduction of EDAC driver support, at least for
> Freescale. So the best I can do is borrow from the new EDAC driver and
> backport it to the old kernel.
>
> But I have learned a few things in this process and can thus share what
> I've learned as it may be of help to the EDAC driver developers:
>
> 1) Before you read the Freescale 8548 CAPTURE_ADDRESS register, you want
> to read CAPTURE_ATTRIBUTES first and make sure the VLD bit (least
> significant bit in the register) is set or else the data in
> CAPTURE_ADDRESS may not be yet valid.
>
> 2) When you are done scrubbing the memory with the single bit error, you
> want to write 0 to CAPTURE_ATTRIBUTES so as to clear VLD and thus setup
> the ECC capture logic to capture the next single bit error.
>
^ permalink raw reply
* Re: [PATCH] powerpc: Update MPC5xxx and Xilinx Virtex maintainer entries
From: Sylvain Munaut @ 2009-04-29 7:28 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <20090428165015.1410.47926.stgit@localhost.localdomain>
Grant Likely wrote:
> From: Grant Likely <grant.likely@secretlab.ca>
>
> - Add git tree URLs
> - Drop Sylvain from the 5xxx maintainers list. He hasn't been active
> for a while now.
>
> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Confirmed.
> ---
>
> MAINTAINERS | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ef03abe..4a8d367 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3434,11 +3434,10 @@ L: linuxppc-dev@ozlabs.org
> S: Maintained
>
> LINUX FOR POWERPC EMBEDDED MPC5XXX
> -P: Sylvain Munaut
> -M: tnt@246tNt.com
> P: Grant Likely
> M: grant.likely@secretlab.ca
> L: linuxppc-dev@ozlabs.org
> +T: git git://git.secretlab.ca/git/linux-2.6.git
> S: Maintained
>
> LINUX FOR POWERPC EMBEDDED PPC4XX
> @@ -3456,6 +3455,7 @@ P: Grant Likely
> M: grant.likely@secretlab.ca
> W: http://wiki.secretlab.ca/index.php/Linux_on_Xilinx_Virtex
> L: linuxppc-dev@ozlabs.org
> +T: git git://git.secretlab.ca/git/linux-2.6.git
> S: Maintained
>
> LINUX FOR POWERPC EMBEDDED PPC8XX
>
^ permalink raw reply
* [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics
From: Michael Neuling @ 2009-04-29 7:27 UTC (permalink / raw)
To: Michael Neuling, Paul Mackerras, Benjamin Herrenschmidt
Cc: linuxppc-dev, Milton Miller
In-Reply-To: <1240990023.559815.441622408876.qpush@pale>
From: Milton Miller <miltonm@bga.com>
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.
Only useful for bare metal systems.
Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/include/asm/mmu.h | 5 +++++
arch/powerpc/include/asm/ppc-opcode.h | 4 ++++
arch/powerpc/kernel/cputable.c | 6 ++++--
arch/powerpc/mm/hash_native_64.c | 13 +++++++++++--
4 files changed, 24 insertions(+), 4 deletions(-)
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/mmu.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
@@ -52,6 +52,11 @@
*/
#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
+/* This indicates that the processor uses the ISA 2.06 server tlbie
+ * mnemonics
+ */
+#define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000)
+
#ifndef __ASSEMBLY__
#include <asm/cputable.h>
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
@@ -45,10 +45,12 @@
#define PPC_INST_STSWX 0x7c00052a
#define PPC_INST_TLBILX 0x7c000024
#define PPC_INST_WAIT 0x7c00007c
+#define PPC_INST_TLBIE 0x7c000264
/* macros to insert fields into opcodes */
#define __PPC_RA(a) (((a) & 0x1f) << 16)
#define __PPC_RB(b) (((b) & 0x1f) << 11)
+#define __PPC_RS(s) (((s) & 0x1f) << 21)
#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
#define __PPC_WC(w) (((w) & 0x3) << 21)
@@ -70,6 +72,8 @@
#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
__PPC_WC(w))
+#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
+ __PPC_RB(a) | __PPC_RS(lp))
/*
* Define what the VSX XX1 form instructions will look like, then add
Index: linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/cputable.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
@@ -425,7 +425,8 @@ static struct cpu_spec __initdata cpu_sp
.cpu_name = "POWER7 (architected)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTR_HPTE_TABLE |
+ MMU_FTR_TLBIE_206,
.icache_bsize = 128,
.dcache_bsize = 128,
.machine_check = machine_check_generic,
@@ -438,7 +439,8 @@ static struct cpu_spec __initdata cpu_sp
.cpu_name = "POWER7 (raw)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTR_HPTE_TABLE |
+ MMU_FTR_TLBIE_206,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
Index: linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/mm/hash_native_64.c
+++ linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
@@ -27,6 +27,7 @@
#include <asm/cputable.h>
#include <asm/udbg.h>
#include <asm/kexec.h>
+#include <asm/ppc-opcode.h>
#ifdef DEBUG_LOW
#define DBG_LOW(fmt...) udbg_printf(fmt)
@@ -49,14 +50,21 @@ static inline void __tlbie(unsigned long
case MMU_PAGE_4K:
va &= ~0xffful;
va |= ssize << 8;
- asm volatile("tlbie %0,0" : : "r" (va) : "memory");
+ asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0),
+ %2)
+ : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+ : "memory");
break;
default:
penc = mmu_psize_defs[psize].penc;
va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
va |= penc << 12;
va |= ssize << 8;
- asm volatile("tlbie %0,1" : : "r" (va) : "memory");
+ va |= 1; /* L */
+ asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0),
+ %2)
+ : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+ : "memory");
break;
}
}
@@ -80,6 +88,7 @@ static inline void __tlbiel(unsigned lon
va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
va |= penc << 12;
va |= ssize << 8;
+ va |= 1; /* L */
asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
: : "r"(va) : "memory");
break;
^ permalink raw reply
* [PATCH 1/2] powerpc: Enable MMU feature sections for inline asm
From: Michael Neuling @ 2009-04-29 7:27 UTC (permalink / raw)
To: Michael Neuling, Paul Mackerras, Benjamin Herrenschmidt
Cc: linuxppc-dev, Milton Miller
In-Reply-To: <1240990023.559815.441622408876.qpush@pale>
From: Milton Miller <miltonm@bga.com>
powerpc: Enable MMU feature sections for inline asm
This adds the ability to do MMU feature sections for inline asm.
Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/include/asm/feature-fixups.h | 25 ++++++++++++++++++++-----
1 file changed, 20 insertions(+), 5 deletions(-)
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/feature-fixups.h
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/feature-fixups.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/feature-fixups.h
@@ -8,8 +8,6 @@
* 2 of the License, or (at your option) any later version.
*/
-#ifdef __ASSEMBLY__
-
/*
* Feature section common macros
*
@@ -23,10 +21,12 @@
/* 64 bits kernel, 32 bits code (ie. vdso32) */
#define FTR_ENTRY_LONG .llong
#define FTR_ENTRY_OFFSET .long 0xffffffff; .long
+#elif defined(CONFIG_PPC64)
+#define FTR_ENTRY_LONG .llong
+#define FTR_ENTRY_OFFSET .llong
#else
-/* 64 bit kernel 64 bit code, or 32 bit kernel 32 bit code */
-#define FTR_ENTRY_LONG PPC_LONG
-#define FTR_ENTRY_OFFSET PPC_LONG
+#define FTR_ENTRY_LONG .long
+#define FTR_ENTRY_OFFSET .long
#endif
#define START_FTR_SECTION(label) label##1:
@@ -141,6 +141,21 @@ label##5: \
#define ALT_FW_FTR_SECTION_END_IFCLR(msk) \
ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
+#ifndef __ASSEMBLY__
+
+#define ASM_MMU_FTR_IF(section_if, section_else, msk, val) \
+ stringify_in_c(BEGIN_MMU_FTR_SECTION) \
+ section_if "; " \
+ stringify_in_c(MMU_FTR_SECTION_ELSE) \
+ section_else "; " \
+ stringify_in_c(ALT_MMU_FTR_SECTION_END((msk), (val)))
+
+#define ASM_MMU_FTR_IFSET(section_if, section_else, msk) \
+ ASM_MMU_FTR_IF(section_if, section_else, (msk), (msk))
+
+#define ASM_MMU_FTR_IFCLR(section_if, section_else, msk) \
+ ASM_MMU_FTR_IF(section_if, section_else, (msk), 0)
+
#endif /* __ASSEMBLY__ */
/* LWSYNC feature sections */
^ permalink raw reply
* [PATCH 0/2] powerpc: tlbie implementation for PowerPC ISA 2.06
From: Michael Neuling @ 2009-04-29 7:27 UTC (permalink / raw)
To: Michael Neuling, Paul Mackerras, Benjamin Herrenschmidt
Cc: linuxppc-dev, Milton Miller
In-Reply-To: <1240989640.548113.69052602556.qpush@pale>
These patches implement the PowerPC ISA 2.06 tlbie mnemonics
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
Built ontop of ppc-opcode cleanup patches
Renamed somethings to be more logical based on comments from mpe.
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox