* Re: [RFC] Hardware Breakpoint interfaces implementation for PPC64
From: K.Prasad @ 2009-05-14 18:52 UTC (permalink / raw)
To: Josh Boyer, linuxppc-dev, Benjamin Herrenschmidt, paulus
In-Reply-To: <20090513025717.GN24338@yookeroo.seuss>
On Wed, May 13, 2009 at 12:57:17PM +1000, David Gibson wrote:
> On Wed, May 13, 2009 at 01:55:45AM +0530, K.Prasad wrote:
> > On Tue, May 12, 2009 at 07:51:49AM -0400, Josh Boyer wrote:
> > > On Tue, May 12, 2009 at 01:33:55AM +0530, K.Prasad wrote:
> [snip]
>
> It seems to me that a kind of minimal requirement for a sensible
> generic debug interface is that if no processes actually ask to use
> the debug regs, then we should never touch them in the hardware. This
> means that debugging hacks in the kernel can just use the debug regs
> directly and don't have to go through the interface to avoid having
> their stuff clobbered on context switch.
>
All that we do additionally for kernel users (when no process is
currently using the debug regs) is to account for the usage just so that
any new requests (kernel or user-space) are denied.
> --
> David Gibson | I'll have my music baroque, and my code
> david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
> | _way_ _around_!
> http://www.ozlabs.org/~dgibson
Thanks,
K.Prasad
^ permalink raw reply
* Re: [RFC] Using the DMAEngine API for scatter/gather operations
From: Ira Snyder @ 2009-05-14 16:55 UTC (permalink / raw)
To: Dan Williams; +Cc: linuxppc-dev@ozlabs.org, Li Yang, Zhang Wei
In-Reply-To: <1242318437.6797.3.camel@dwillia2-mobl1.amr.corp.intel.com>
On Thu, May 14, 2009 at 09:27:17AM -0700, Dan Williams wrote:
> On Thu, 2009-05-14 at 09:13 -0700, Ira Snyder wrote:
> > Hello all.
> >
> > I'm working on a driver for a custom board (based heavily on the
> > MPC8349EMDS board) to dump data out of onboard FPGA's. I need to use the
> > onboard DMA controller for this, mostly due to data transfer rate and
> > timing requirements.
> >
> > Of course, I'd like to "play nice" with the existing Linux
> > infrastructure in my driver, even though I have no plans to submit the
> > driver upstream (since it is only useful for our custom board).
> >
> > I have been using the DMAEngine API to interact with the DMA controller,
> > and it works without any problems. However it seems that it is missing
> > one of the major features that is supported by almost all DMA
> > controllers: scatter/gather support.
> >
> > What I'd really like to do is give the controller a scatterlist and list
> > of hardware addresses, and have it set up the transfer. The Freescale
> > hardware can handle this, and I could program it by hand to do so, but I
> > don't want to invent my own DMA API.
> >
> > I'm aware that the DMAEngine API was designed to offload memcpy, and
> > pretty much nothing else. Is there any chance that such a change would
> > be accepted into the mainline kernel? Any opinions on what such an API
> > should look like?
> >
>
> Have you taken a look at the 'slave' interface implemented by dw_dmac
> and other drivers? It has the following interface:
>
> struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
> struct dma_chan *chan, struct scatterlist *sgl,
> unsigned int sg_len, enum dma_data_direction direction,
> unsigned long flags);
>
> Haavard uses this interface to do sgl transfers on behalf of the
> atmel-mci driver (drivers/mmc/host/atmel-mci.c).
>
I had started looking at it, though the Freescale device does not
implement DMA_SLAVE support. I was a bit discouraged by the changelog
for commit dc0ee643, which says that the interface is for "DMA with
hardware handshaking", which I do not have. There is not anything
special about accessing the FPGA's, they appear in the processor's
memory map and can be read from/written to just like RAM.
I'll try studying the dw_dmac implementation and atmel-mci example.
Thanks for the response,
Ira
^ permalink raw reply
* Re: [PATCH] i2c-mpc: generate START condition after STOP caused by read i2c_msg
From: Joakim Tjernlund @ 2009-05-14 16:52 UTC (permalink / raw)
To: Esben Haabendal; +Cc: linuxppc-dev
In-Reply-To: <d2b9ea600905140317u7a4b9a70s574568d79a1ce7cc@mail.gmail.com>
Esben Haabendal <esbenhaabendal@gmail.com> wrote on 14/05/2009 12:17:48=
:
> On Thu, May 14, 2009 at 11:58 AM, Joakim Tjernlund
> <joakim.tjernlund@transmode.se> wrote:
> >>
> >> The problem is that after the STOP condition, the following i2c_ms=
g will be
> >> attempted with a repeated START, which according to specification =
will
> >> cause a MAL, which also happens. =A0My MPC8360ERM reads:
> >>
> >> "Attempting a repeated START at the wrong time (or if the bus is o=
wned
> >> by another master), results in loss of arbitration."
> >>
> >> Which I know read as it that we must own the I2C bus when using RS=
TA.
> >
> > I agree with the theory, but isn't the problem here that STOP is pe=
rformed in
> > the middle of this transaction?
> > Remove the STOP and RSTA will work I think.
>
> That was also my first idea.
>
> But at least for my CS4265, reads does not work without a STOP follow=
ing the
> last byte. I guess I am not the first to experience this, as indicate=
d
> by the current
> i2c-mpc.c implementation.
> As far as I can understand the I2C specification, a STOP should not b=
e required
> after reads, but I am not sure.
>
> The cost of the additional STOP is really small. The only issue I ca=
n see,
> is that with the STOP in the midle of an i2c_transfer, the I2C bus is=
released.
> This naturally also happens with the current implementation, so I bel=
ieve
> that this patch is a clean improvement.
>
> Anyways, if someone can figure out how to achive this without STOP,
> I will be happy (re)test with my hardware setup here.
>From just playing a little, I think the below patch will get you far.
However, I had to change this too to make it stable:
static void mpc_i2c_start(struct mpc_i2c *i2c)
{
/* Clear arbitration */
writeb(0, i2c->base + MPC_I2C_SR);
#if 1 // fix, not sure why
writeccr(i2c, 0);
udelay(5);
#endif
/* Start with MEN */
writeccr(i2c, CCR_MEN);
}
PS.
I added back the linuxppc list, let it stay.
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.=
c
index 6c1cddd..d7edcd2 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -189,9 +189,6 @@ static int mpc_write(struct mpc_i2c *i2c, int targe=
t,
unsigned timeout =3D i2c->adap.timeout;
u32 flags =3D restart ? CCR_RSTA : 0;
- /* Start with MEN */
- if (!restart)
- writeccr(i2c, CCR_MEN);
/* Start as master */
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
/* Write target byte */
@@ -220,9 +217,6 @@ static int mpc_read(struct mpc_i2c *i2c, int target=
,
int i, result;
u32 flags =3D restart ? CCR_RSTA : 0;
- /* Start with MEN */
- if (!restart)
- writeccr(i2c, CCR_MEN);
/* Switch to read - restart */
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
/* Write target address byte - this time with the read flag set */
@@ -241,18 +235,15 @@ static int mpc_read(struct mpc_i2c *i2c, int targ=
et,
readb(i2c->base + MPC_I2C_DR);
}
- for (i =3D 0; i < length; i++) {
+ for (i =3D length; i ; --i) {
result =3D i2c_wait(i2c, timeout, 0);
if (result < 0)
return result;
- /* Generate txack on next to last byte */
- if (i =3D=3D length - 2)
+ /* Generate txack on next to last byte(s) */
+ if (i <=3D 2)
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
- /* Generate stop on last byte */
- if (i =3D=3D length - 1)
- writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
- data[i] =3D readb(i2c->base + MPC_I2C_DR);
+ data[length-i] =3D readb(i2c->base + MPC_I2C_DR);
}
return length;
=
^ permalink raw reply related
* Re: Please pull from 'merge' branch for 2.6.30
From: Grant Likely @ 2009-05-14 16:41 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.0905131731260.772@localhost.localdomain>
Hi Ben,
Here are some more commits which got missed in the last merge cycle.
I've based this on top of Kumar's pull request from yesterday to
minimize merge commits.
Note: This pull request replaces my previous pull request. I rebased
the series since some of the commits in my previous request have
already been merged. If you've already pulled my last request then
you don't need to pull this one.
Cheers,
g.
The following changes since commit 2e15eedffaae555085071c68cb94b9eeed2245be=
:
Kumar Gala (1):
powerpc/8xx: Update defconfigs
are available in the git repository at:
git://git.secretlab.ca/git/linux-2.6 merge
Grant Likely (2):
powerpc/boot: add simpleImage.* to clean-files list
powerpc/virtex: Add uImage to the default images list
John Linn (1):
powerpc/virtex: Fix duplicate level irq events.
arch/powerpc/boot/Makefile | 2 +-
arch/powerpc/platforms/40x/Kconfig | 1 +
arch/powerpc/platforms/44x/Kconfig | 1 +
arch/powerpc/sysdev/xilinx_intc.c | 117 ++++++++++++++++++++++++++++++++=
---
4 files changed, 110 insertions(+), 11 deletions(-)
On Wed, May 13, 2009 at 4:31 PM, Kumar Gala <galak@kernel.crashing.org> wro=
te:
> Just added defconfig updates for the normal FSL set of HW.
>
> - k
>
> Please pull from 'merge' branch of
>
> =A0 =A0 =A0 =A0master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.=
git merge
>
> to receive the following updates:
>
> =A0arch/powerpc/configs/83xx/asp8347_defconfig =A0 =A0 =A0 | =A0104 ++++-
> =A0arch/powerpc/configs/83xx/mpc8313_rdb_defconfig =A0 | =A0114 ++++--
> =A0arch/powerpc/configs/83xx/mpc8315_rdb_defconfig =A0 | =A0114 ++++--
> =A0arch/powerpc/configs/83xx/mpc832x_mds_defconfig =A0 | =A0107 ++++--
> =A0arch/powerpc/configs/83xx/mpc832x_rdb_defconfig =A0 | =A0113 ++++--
> =A0arch/powerpc/configs/83xx/mpc834x_itx_defconfig =A0 | =A0108 ++++--
> =A0arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig | =A0108 ++++--
> =A0arch/powerpc/configs/83xx/mpc834x_mds_defconfig =A0 | =A0103 ++++-
> =A0arch/powerpc/configs/83xx/mpc836x_mds_defconfig =A0 | =A0108 ++++--
> =A0arch/powerpc/configs/83xx/mpc836x_rdk_defconfig =A0 | =A0 96 ++++-
> =A0arch/powerpc/configs/83xx/mpc837x_mds_defconfig =A0 | =A0104 ++++-
> =A0arch/powerpc/configs/83xx/mpc837x_rdb_defconfig =A0 | =A0111 ++++--
> =A0arch/powerpc/configs/83xx/sbc834x_defconfig =A0 =A0 =A0 | =A0 96 ++++-
> =A0arch/powerpc/configs/85xx/ksi8560_defconfig =A0 =A0 =A0 | =A0 86 +++-
> =A0arch/powerpc/configs/85xx/mpc8540_ads_defconfig =A0 | =A0 82 +++-
> =A0arch/powerpc/configs/85xx/mpc8560_ads_defconfig =A0 | =A0 89 +++--
> =A0arch/powerpc/configs/85xx/mpc85xx_cds_defconfig =A0 | =A0 88 +++--
> =A0arch/powerpc/configs/85xx/sbc8548_defconfig =A0 =A0 =A0 | =A0 84 +++-
> =A0arch/powerpc/configs/85xx/sbc8560_defconfig =A0 =A0 =A0 | =A0 83 +++-
> =A0arch/powerpc/configs/85xx/socrates_defconfig =A0 =A0 =A0| =A0385 +++++=
+++++++++++------
> =A0arch/powerpc/configs/85xx/stx_gp3_defconfig =A0 =A0 =A0 | =A0105 ++++-=
-
> =A0arch/powerpc/configs/85xx/tqm8540_defconfig =A0 =A0 =A0 | =A0100 ++++-
> =A0arch/powerpc/configs/85xx/tqm8541_defconfig =A0 =A0 =A0 | =A0101 ++++-
> =A0arch/powerpc/configs/85xx/tqm8548_defconfig =A0 =A0 =A0 | =A0 64 ++-
> =A0arch/powerpc/configs/85xx/tqm8555_defconfig =A0 =A0 =A0 | =A0101 ++++-
> =A0arch/powerpc/configs/85xx/tqm8560_defconfig =A0 =A0 =A0 | =A0101 ++++-
> =A0arch/powerpc/configs/86xx/gef_ppc9a_defconfig =A0 =A0 | =A0 92 ++++-
> =A0arch/powerpc/configs/86xx/gef_sbc310_defconfig =A0 =A0| =A0 92 ++++-
> =A0arch/powerpc/configs/86xx/gef_sbc610_defconfig =A0 =A0| =A0122 +++++-
> =A0arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig =A0| =A0100 ++++-
> =A0arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig =A0| =A0211 ++++-----=
---
> =A0arch/powerpc/configs/86xx/sbc8641d_defconfig =A0 =A0 =A0| =A0114 ++++-=
-
> =A0arch/powerpc/configs/adder875_defconfig =A0 =A0 =A0 =A0 =A0 | =A0 65 +=
+-
> =A0arch/powerpc/configs/c2k_defconfig =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =
=A0128 +++++--
> =A0arch/powerpc/configs/ep8248e_defconfig =A0 =A0 =A0 =A0 =A0 =A0| =A0 74=
+++-
> =A0arch/powerpc/configs/ep88xc_defconfig =A0 =A0 =A0 =A0 =A0 =A0 | =A0 63=
++-
> =A0arch/powerpc/configs/linkstation_defconfig =A0 =A0 =A0 =A0| =A0 96 +++=
+-
> =A0arch/powerpc/configs/mgcoge_defconfig =A0 =A0 =A0 =A0 =A0 =A0 | =A0 74=
+++-
> =A0arch/powerpc/configs/mgsuvd_defconfig =A0 =A0 =A0 =A0 =A0 =A0 | =A0 72=
+++-
> =A0arch/powerpc/configs/mpc7448_hpc2_defconfig =A0 =A0 =A0 | =A0 91 +++--
> =A0arch/powerpc/configs/mpc8272_ads_defconfig =A0 =A0 =A0 =A0| =A0 77 +++=
-
> =A0arch/powerpc/configs/mpc83xx_defconfig =A0 =A0 =A0 =A0 =A0 =A0| =A0115=
++++--
> =A0arch/powerpc/configs/mpc866_ads_defconfig =A0 =A0 =A0 =A0 | =A0 77 +++=
-
> =A0arch/powerpc/configs/mpc86xx_defconfig =A0 =A0 =A0 =A0 =A0 =A0| =A0211=
++++--------
> =A0arch/powerpc/configs/mpc885_ads_defconfig =A0 =A0 =A0 =A0 | =A0 63 ++-
> =A0arch/powerpc/configs/pq2fads_defconfig =A0 =A0 =A0 =A0 =A0 =A0| =A0 90=
+++--
> =A0arch/powerpc/configs/prpmc2800_defconfig =A0 =A0 =A0 =A0 =A0| =A0120 +=
++++-
> =A0arch/powerpc/configs/storcenter_defconfig =A0 =A0 =A0 =A0 | =A0 71 ++-=
-
> =A0arch/powerpc/sysdev/fsl_soc.c =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
| =A0 46 --
> =A049 files changed, 3630 insertions(+), 1489 deletions(-)
>
> Anton Vorontsov (1):
> =A0 =A0 =A0powerpc/fsl_soc: Remove mpc83xx_wdt_init, again
>
> Kumar Gala (5):
> =A0 =A0 =A0powerpc/83xx: Update defconfigs
> =A0 =A0 =A0powerpc/85xx: Update defconfigs
> =A0 =A0 =A0powerpc/86xx: Update defconfigs
> =A0 =A0 =A0powerpc/embedded6xx: Update defconfigs
> =A0 =A0 =A0powerpc/8xx: Update defconfigs
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [RFC] Using the DMAEngine API for scatter/gather operations
From: Dan Williams @ 2009-05-14 16:27 UTC (permalink / raw)
To: Ira Snyder; +Cc: linuxppc-dev@ozlabs.org, Li Yang, Zhang Wei
In-Reply-To: <20090514161353.GA4379@ovro.caltech.edu>
On Thu, 2009-05-14 at 09:13 -0700, Ira Snyder wrote:
> Hello all.
>
> I'm working on a driver for a custom board (based heavily on the
> MPC8349EMDS board) to dump data out of onboard FPGA's. I need to use the
> onboard DMA controller for this, mostly due to data transfer rate and
> timing requirements.
>
> Of course, I'd like to "play nice" with the existing Linux
> infrastructure in my driver, even though I have no plans to submit the
> driver upstream (since it is only useful for our custom board).
>
> I have been using the DMAEngine API to interact with the DMA controller,
> and it works without any problems. However it seems that it is missing
> one of the major features that is supported by almost all DMA
> controllers: scatter/gather support.
>
> What I'd really like to do is give the controller a scatterlist and list
> of hardware addresses, and have it set up the transfer. The Freescale
> hardware can handle this, and I could program it by hand to do so, but I
> don't want to invent my own DMA API.
>
> I'm aware that the DMAEngine API was designed to offload memcpy, and
> pretty much nothing else. Is there any chance that such a change would
> be accepted into the mainline kernel? Any opinions on what such an API
> should look like?
>
Have you taken a look at the 'slave' interface implemented by dw_dmac
and other drivers? It has the following interface:
struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
struct dma_chan *chan, struct scatterlist *sgl,
unsigned int sg_len, enum dma_data_direction direction,
unsigned long flags);
Haavard uses this interface to do sgl transfers on behalf of the
atmel-mci driver (drivers/mmc/host/atmel-mci.c).
--
Dan
^ permalink raw reply
* [RFC] Using the DMAEngine API for scatter/gather operations
From: Ira Snyder @ 2009-05-14 16:13 UTC (permalink / raw)
To: Dan Williams, Li Yang, Zhang Wei, linuxppc-dev
Hello all.
I'm working on a driver for a custom board (based heavily on the
MPC8349EMDS board) to dump data out of onboard FPGA's. I need to use the
onboard DMA controller for this, mostly due to data transfer rate and
timing requirements.
Of course, I'd like to "play nice" with the existing Linux
infrastructure in my driver, even though I have no plans to submit the
driver upstream (since it is only useful for our custom board).
I have been using the DMAEngine API to interact with the DMA controller,
and it works without any problems. However it seems that it is missing
one of the major features that is supported by almost all DMA
controllers: scatter/gather support.
What I'd really like to do is give the controller a scatterlist and list
of hardware addresses, and have it set up the transfer. The Freescale
hardware can handle this, and I could program it by hand to do so, but I
don't want to invent my own DMA API.
I'm aware that the DMAEngine API was designed to offload memcpy, and
pretty much nothing else. Is there any chance that such a change would
be accepted into the mainline kernel? Any opinions on what such an API
should look like?
Thanks,
Ira
^ permalink raw reply
* Re: [PATCH v7] introduce macro spin_event_timeout()
From: Grant Likely @ 2009-05-14 16:10 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev, smaclennan, scottwood
In-Reply-To: <4A0C40D4.1090508@freescale.com>
On Thu, May 14, 2009 at 10:03 AM, Timur Tabi <timur@freescale.com> wrote:
> Grant Likely wrote:
>
>> This version looks good to me. =A0Who's the first user? (I'd like to see
>> that something is ready to use this before merging it)
>
> I was going to do it the other way around - wait until this patch is merg=
ed, and then update some code to use it. =A0After all, it's easier to use a=
macro if it already exists in a header file. :-)
Heh, I think you miss my meaning. Of course this patch must be merged
before any users. I just want to hold off merging it until I see
viable patches on the mailing list which depend on it.
In other words, write your patches which use it and submit the lot as
a patch series with this patch as the first. That gives some evidence
that this macro will actually be used and useful.
g.
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH v7] introduce macro spin_event_timeout()
From: Timur Tabi @ 2009-05-14 16:03 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, smaclennan, scottwood
In-Reply-To: <fa686aa40905140813l5caf7085r64bce935be0a22d3@mail.gmail.com>
Grant Likely wrote:
> This version looks good to me. Who's the first user? (I'd like to see
> that something is ready to use this before merging it)
I was going to do it the other way around - wait until this patch is merged, and then update some code to use it. After all, it's easier to use a macro if it already exists in a header file. :-)
Grepping for "while.*in_be" finds lots of candidates.
I was originally planning to use this macro in sound/soc/fsl/fsl_ssi.c, but I eliminated the need to poll on a register with commit a4d11fe50c238a7da5225d1399314c3505cbd792 ("ASoC: remove trigger delay in Freescale MPC8610 sound driver"). So now I need to find a new guinea pig.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [PATCH] powerpc/ftrace: Use pr_devel() in ftrace.c
From: Steven Rostedt @ 2009-05-14 15:49 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
In-Reply-To: <e805665453162bf2eb90b402e41fc7b672fcf639.1242282612.git.michael@ellerman.id.au>
I'm fine with this patch, but it should go via the PPC tree.
Acked-by: Steven Rostedt <rostedt@goodmis.org>
-- Steve
On Thu, 14 May 2009, Michael Ellerman wrote:
> pr_debug() can now result in code being generated even when #DEBUG
> is not defined. That's not really desirable in the ftrace code
> which we want to be snappy.
>
> With CONFIG_DYNAMIC_DEBUG=y:
>
> size before:
> text data bss dec hex filename
> 3334 672 4 4010 faa arch/powerpc/kernel/ftrace.o
>
> size after:
> text data bss dec hex filename
> 2616 360 4 2980 ba4 arch/powerpc/kernel/ftrace.o
>
> Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
> ---
> arch/powerpc/kernel/ftrace.c | 20 ++++++++++----------
> 1 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c
> index 70e2a73..5b078ee 100644
> --- a/arch/powerpc/kernel/ftrace.c
> +++ b/arch/powerpc/kernel/ftrace.c
> @@ -157,7 +157,7 @@ __ftrace_make_nop(struct module *mod,
> * 0xe8, 0x4c, 0x00, 0x28, ld r2,40(r12)
> */
>
> - pr_debug("ip:%lx jumps to %lx r2: %lx", ip, tramp, mod->arch.toc);
> + pr_devel("ip:%lx jumps to %lx r2: %lx", ip, tramp, mod->arch.toc);
>
> /* Find where the trampoline jumps to */
> if (probe_kernel_read(jmp, (void *)tramp, sizeof(jmp))) {
> @@ -165,7 +165,7 @@ __ftrace_make_nop(struct module *mod,
> return -EFAULT;
> }
>
> - pr_debug(" %08x %08x", jmp[0], jmp[1]);
> + pr_devel(" %08x %08x", jmp[0], jmp[1]);
>
> /* verify that this is what we expect it to be */
> if (((jmp[0] & 0xffff0000) != 0x3d820000) ||
> @@ -181,18 +181,18 @@ __ftrace_make_nop(struct module *mod,
> offset = ((unsigned)((unsigned short)jmp[0]) << 16) +
> (int)((short)jmp[1]);
>
> - pr_debug(" %x ", offset);
> + pr_devel(" %x ", offset);
>
> /* get the address this jumps too */
> tramp = mod->arch.toc + offset + 32;
> - pr_debug("toc: %lx", tramp);
> + pr_devel("toc: %lx", tramp);
>
> if (probe_kernel_read(jmp, (void *)tramp, 8)) {
> printk(KERN_ERR "Failed to read %lx\n", tramp);
> return -EFAULT;
> }
>
> - pr_debug(" %08x %08x\n", jmp[0], jmp[1]);
> + pr_devel(" %08x %08x\n", jmp[0], jmp[1]);
>
> ptr = ((unsigned long)jmp[0] << 32) + jmp[1];
>
> @@ -269,7 +269,7 @@ __ftrace_make_nop(struct module *mod,
> * 0x4e, 0x80, 0x04, 0x20 bctr
> */
>
> - pr_debug("ip:%lx jumps to %lx", ip, tramp);
> + pr_devel("ip:%lx jumps to %lx", ip, tramp);
>
> /* Find where the trampoline jumps to */
> if (probe_kernel_read(jmp, (void *)tramp, sizeof(jmp))) {
> @@ -277,7 +277,7 @@ __ftrace_make_nop(struct module *mod,
> return -EFAULT;
> }
>
> - pr_debug(" %08x %08x ", jmp[0], jmp[1]);
> + pr_devel(" %08x %08x ", jmp[0], jmp[1]);
>
> /* verify that this is what we expect it to be */
> if (((jmp[0] & 0xffff0000) != 0x3d600000) ||
> @@ -293,7 +293,7 @@ __ftrace_make_nop(struct module *mod,
> if (tramp & 0x8000)
> tramp -= 0x10000;
>
> - pr_debug(" %lx ", tramp);
> + pr_devel(" %lx ", tramp);
>
> if (tramp != addr) {
> printk(KERN_ERR
> @@ -402,7 +402,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
> /* ld r2,40(r1) */
> op[1] = 0xe8410028;
>
> - pr_debug("write to %lx\n", rec->ip);
> + pr_devel("write to %lx\n", rec->ip);
>
> if (probe_kernel_write((void *)ip, op, MCOUNT_INSN_SIZE * 2))
> return -EPERM;
> @@ -442,7 +442,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
> return -EINVAL;
> }
>
> - pr_debug("write to %lx\n", rec->ip);
> + pr_devel("write to %lx\n", rec->ip);
>
> if (probe_kernel_write((void *)ip, &op, MCOUNT_INSN_SIZE))
> return -EPERM;
> --
> 1.6.2.1
>
>
^ permalink raw reply
* Re: [PATCH v7] introduce macro spin_event_timeout()
From: Grant Likely @ 2009-05-14 15:13 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev, smaclennan, scottwood
In-Reply-To: <1241560385-26868-1-git-send-email-timur@freescale.com>
On Tue, May 5, 2009 at 3:53 PM, Timur Tabi <timur@freescale.com> wrote:
> The macro spin_event_timeout() takes a condition and timeout value
> (in microseconds) as parameters. =A0It spins until either the condition i=
s true
> or the timeout expires. =A0It returns the result of the condition when th=
e loop
> was terminated.
>
> This primary purpose of this macro is to poll on a hardware register unti=
l a
> status bit changes. =A0The timeout ensures that the loop still terminates=
if the
> bit doesn't change as expected. =A0This macro makes it easier for driver
> developers to perform this kind of operation properly.
>
> Signed-off-by: Timur Tabi <timur@freescale.com>
This version looks good to me. Who's the first user? (I'd like to see
that something is ready to use this before merging it)
Acked-by: Grant Likely <grant.likely@secretlab.ca>
> ---
>
> v7: add if-statement to use cpu_relax() if the delay is 0. =A0gcc will op=
timize
> out the if-statement if 'delay' is a constant.
>
> I'm making this a PowerPC-specific patch because I want to use
> tb_ticks_per_usec, which does not exist on all other platforms. =A0I don'=
t want
> to use jiffies because jiffies works only when interrupts are enabled, an=
d
> the resolution may not be fine enough.
>
> =A0arch/powerpc/include/asm/delay.h | =A0 32 ++++++++++++++++++++++++++++=
++++
> =A01 files changed, 32 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/delay.h b/arch/powerpc/include/asm/=
delay.h
> index f9200a6..2bde26f 100644
> --- a/arch/powerpc/include/asm/delay.h
> +++ b/arch/powerpc/include/asm/delay.h
> @@ -2,6 +2,8 @@
> =A0#define _ASM_POWERPC_DELAY_H
> =A0#ifdef __KERNEL__
>
> +#include <asm/time.h>
> +
> =A0/*
> =A0* Copyright 1996, Paul Mackerras.
> =A0*
> @@ -30,5 +32,35 @@ extern void udelay(unsigned long usecs);
> =A0#define mdelay(n) =A0 =A0 =A0udelay((n) * 1000)
> =A0#endif
>
> +/**
> + * spin_event_timeout - spin until a condition gets true or a timeout el=
apses
> + * @condition: a C expression to evalate
> + * @timeout: timeout, in microseconds
> + * @delay: the number of microseconds to delay between eache evaluation =
of
> + * =A0 =A0 =A0 =A0 @condition
> + * @rc: the last value of the condition
> + *
> + * The process spins until the condition evaluates to true (non-zero) or=
the
> + * timeout elapses. =A0Upon exit, @rc contains the value of the conditio=
n. This
> + * allows you to test the condition without incurring any side effects.
> + *
> + * This primary purpose of this macro is to poll on a hardware register
> + * until a status bit changes. =A0The timeout ensures that the loop stil=
l
> + * terminates even if the bit never changes. =A0The delay is for devices=
that
> + * need a delay in between successive reads.
> + *
> + * gcc will optimize out the if-statement if @delay is a constant.
> + */
> +#define spin_event_timeout(condition, timeout, delay, rc) =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 \
> +{ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 \
> + =A0 =A0 =A0 unsigned long __loops =3D tb_ticks_per_usec * timeout; =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0\
> + =A0 =A0 =A0 unsigned long __start =3D get_tbl(); =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0\
> + =A0 =A0 =A0 while (!(rc =3D (condition)) && (tb_ticks_since(__start) <=
=3D __loops)) \
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (delay) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0\
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 udelay(delay); =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0\
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 else =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
\
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cpu_relax(); =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0\
> +}
> +
> =A0#endif /* __KERNEL__ */
> =A0#endif /* _ASM_POWERPC_DELAY_H */
> --
> 1.6.0.6
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [RFC Patch 6/6] Adapt kexec and samples code to recognise PPC64 hardware breakpoint usage
From: Michael Ellerman @ 2009-05-14 14:55 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Neuling, Benjamin Herrenschmidt, linuxppc-dev, paulus,
Alan Stern, K.Prasad, Roland McGrath
In-Reply-To: <alpine.LRH.2.00.0905141617480.2225@vixen.sonytel.be>
[-- Attachment #1: Type: text/plain, Size: 1980 bytes --]
On Thu, 2009-05-14 at 16:18 +0200, Geert Uytterhoeven wrote:
> On Fri, 15 May 2009, Michael Ellerman wrote:
> > On Thu, 2009-05-14 at 15:59 +0200, Geert Uytterhoeven wrote:
> > > On Thu, 14 May 2009, K.Prasad wrote:
> > > > Modify kexec code to disable DABR registers before a reboot. Adapt the samples
> > > > code to populate PPC64-arch specific fields.
> > > >
> > > > Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
> > > > ---
> > > > arch/powerpc/kernel/machine_kexec_64.c | 6
> > > > samples/hw_breakpoint/data_breakpoint.c | 4
> > > >
> > > > Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/machine_kexec_64.c
> > > > ===================================================================
> > > > --- linux-2.6-tip.hbkpt.orig/arch/powerpc/kernel/machine_kexec_64.c 2009-05-14 00:17:24.000000000 +0530
> > > > +++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/machine_kexec_64.c 2009-05-14 09:48:09.000000000 +0530
> > > > @@ -24,6 +24,7 @@
> > > > #include <asm/sections.h> /* _end */
> > > > #include <asm/prom.h>
> > > > #include <asm/smp.h>
> > > > +#include <asm/hw_breakpoint.h>
> > > >
> > > > int default_machine_kexec_prepare(struct kimage *image)
> > > > {
> > > > @@ -214,6 +215,9 @@
> > > > put_cpu();
> > > >
> > > > local_irq_disable();
> > > > +#ifdef CONFIG_PPC64
> > > ^^^^^^^^^^^^^^^^^^^
> > > > + hw_breakpoint_disable();
> > > > +#endif
> > > ^^^^^^
> > >
> > > What about providing a dummy definition of hw_breakpoint_disable()
> > > in <asm/hw_breakpoint.h> if !CONFIG_PPC64?
> >
> > That would be good.
> >
> > What would be better, is to notice that machine_kexec_64.c is only ever
> > built for 64-bit - hence the name. And so no ifdefs or anything else is
> > required.
>
> Right ;-)
>
> But that can't be said for other files, like e.g. arch/powerpc/kernel/ptrace.c.
Yeah you're right, the rest of this series could use lots of #ifdefs in
headers love.
cheers
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: [RFC Patch 4/6] Modify process handling code to handle hardware debug registers
From: Michael Ellerman @ 2009-05-14 14:54 UTC (permalink / raw)
To: K.Prasad
Cc: Michael Neuling, Benjamin Herrenschmidt, linuxppc-dev, Alan Stern,
paulus, Roland McGrath
In-Reply-To: <20090514134528.GE14229@in.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 2069 bytes --]
On Thu, 2009-05-14 at 19:15 +0530, K.Prasad wrote:
> plain text document attachment (ppc64_modify_process_handling_04)
> Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/process.c
> ===================================================================
> --- linux-2.6-tip.hbkpt.orig/arch/powerpc/kernel/process.c
> +++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/process.c
> @@ -50,6 +50,7 @@
> #include <asm/syscalls.h>
> #ifdef CONFIG_PPC64
> #include <asm/firmware.h>
> +#include <asm/hw_breakpoint.h>
> #endif
> #include <linux/kprobes.h>
> #include <linux/kdebug.h>
> @@ -254,8 +255,10 @@ void do_dabr(struct pt_regs *regs, unsig
> 11, SIGSEGV) == NOTIFY_STOP)
> return;
>
> +#ifndef CONFIG_PPC64
> if (debugger_dabr_match(regs))
> return;
> +#endif
>
> /* Clear the DAC and struct entries. One shot trigger */
> #if defined(CONFIG_BOOKE)
> @@ -372,8 +375,13 @@ struct task_struct *__switch_to(struct t
>
> #endif /* CONFIG_SMP */
>
> +#ifdef CONFIG_PPC64
> + if (unlikely(test_tsk_thread_flag(new, TIF_DEBUG)))
> + switch_to_thread_hw_breakpoint(new);
> +#else
To avoid all these ifdefs in the code we need something like this in a
header:
static inline int task_uses_debug_regs(struct task_struct *tsk)
{
#ifdef CONFIG_PPC64
return test_tsk_thread_flag(tsk, TIF_DEBUG);
#else
return 0;
#endif
}
> @@ -605,6 +617,9 @@ int copy_thread(unsigned long clone_flag
> struct pt_regs *childregs, *kregs;
> extern void ret_from_fork(void);
> unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
> +#ifdef CONFIG_PPC64
> + struct task_struct *tsk = current;
> +#endif
>
> CHECK_FULL_REGS(regs);
> /* Copy registers */
> @@ -672,6 +687,9 @@ int copy_thread(unsigned long clone_flag
> * function.
> */
> kregs->nip = *((unsigned long *)ret_from_fork);
> +
> + if (unlikely(test_tsk_thread_flag(tsk, TIF_DEBUG)))
> + copy_thread_hw_breakpoint(tsk, p, clone_flags);
If you just use current here you don't need to define tsk above.
cheers
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* [PATCH] sata_fsl: Fix the command description of FSL SATA controller
From: Kumar Gala @ 2009-05-14 14:47 UTC (permalink / raw)
To: Jeff Garzik; +Cc: linux-ide, linux-kernel, linuxppc-dev
From: Dave Liu <daveliu@freescale.com>
The bit 11 of command description is reserved bit in Freescale
SATA controller and needs to be set to '1'. This is needed to
make sure the last write from the controller to the buffer
descriptor is seen before an interrupt is raised.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
Jeff, please pick this up as a bug fix for 2.6.30
drivers/ata/sata_fsl.c | 8 +++++---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index 5edd654..36b8629 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -205,6 +205,7 @@ struct cmdhdr_tbl_entry {
* Description information bitdefs
*/
enum {
+ CMD_DESC_RES = (1 << 11),
VENDOR_SPECIFIC_BIST = (1 << 10),
CMD_DESC_SNOOP_ENABLE = (1 << 9),
FPDMA_QUEUED_CMD = (1 << 8),
@@ -388,7 +389,7 @@ static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
void __iomem *hcr_base = host_priv->hcr_base;
unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
struct command_desc *cd;
- u32 desc_info = CMD_DESC_SNOOP_ENABLE;
+ u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
u32 num_prde = 0;
u32 ttl_dwords = 0;
dma_addr_t cd_paddr;
@@ -841,7 +842,7 @@ issue_srst:
/* device reset/SRST is a control register update FIS, uses tag0 */
sata_fsl_setup_cmd_hdr_entry(pp, 0,
- SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
+ SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
ata_tf_to_fis(&tf, pmp, 0, cfis);
@@ -887,7 +888,8 @@ issue_srst:
* using ATA signature D2H register FIS to the host controller.
*/
- sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
+ sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
+ 0, 0, 5);
tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
ata_tf_to_fis(&tf, pmp, 0, cfis);
--
1.6.0.6
^ permalink raw reply related
* Re: [RFC Patch 2/6] Introduce PPC64 specific Hardware Breakpoint interfaces
From: Michael Ellerman @ 2009-05-14 14:50 UTC (permalink / raw)
To: K.Prasad
Cc: Michael Neuling, Benjamin Herrenschmidt, linuxppc-dev, Alan Stern,
paulus, Roland McGrath
In-Reply-To: <20090514134439.GC14229@in.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 7522 bytes --]
On Thu, 2009-05-14 at 19:14 +0530, K.Prasad wrote:
> plain text document attachment (ppc64_arch_hwbkpt_implementation_02)
> Introduce PPC64 implementation for the generic hardware breakpoint interfaces
> defined in kernel/hw_breakpoint.c. Enable the HAVE_HW_BREAKPOINT flag and the
> Makefile.
Hi, some comments inline ...
> Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/hw_breakpoint.c
> ===================================================================
> --- /dev/null
> +++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/hw_breakpoint.c
> @@ -0,0 +1,281 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
> + *
> + * Copyright (C) 2009 IBM Corporation
> + */
Don't use (C), either use a proper ©, or just skip it. I don't know
why :)
> +/*
> + * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
> + * using the CPU's debug registers.
> + */
This comment would normally go at the top of the file.
> +
> +#include <linux/notifier.h>
> +#include <linux/kallsyms.h>
> +#include <linux/kprobes.h>
> +#include <linux/percpu.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/sched.h>
> +#include <linux/init.h>
> +#include <linux/smp.h>
> +
> +#include <asm/hw_breakpoint.h>
> +#include <asm/processor.h>
> +#include <asm/sstep.h>
> +
> +/* Store the kernel-space breakpoint address value */
> +static unsigned long kdabr;
> +
> +/*
> + * Temporarily stores address for DABR before it is written by the
> + * single-step handler routine
> + */
> +static DEFINE_PER_CPU(unsigned long, dabr_data);
How does this relate to the existing current_dabr per-cpu variable?
> +void arch_update_kernel_hw_breakpoint(void *unused)
> +{
> + struct hw_breakpoint *bp;
> +
> + /* Check if there is nothing to update */
> + if (hbp_kernel_pos == HBP_NUM)
> + return;
Should that be hbp_kernel_pos >= HBP_NUM, you're checking array bounds
right?
> + bp = hbp_kernel[hbp_kernel_pos];
> + if (bp == NULL)
> + kdabr = 0;
> + else
> + kdabr = bp->info.address | bp->info.type | DABR_TRANSLATION;
> + set_dabr(kdabr);
> +}
> +
> +/*
> + * Install the thread breakpoints in their debug registers.
> + */
> +void arch_install_thread_hw_breakpoint(struct task_struct *tsk)
> +{
> + set_dabr(tsk->thread.dabr);
Can we avoid setting this value if it's not necessary? It might require
an hcall. See for example what we do in __switch_to().
> +/*
> + * Check for virtual address in user space.
> + */
> +static int arch_check_va_in_userspace(unsigned long va)
> +{
> + return (!(is_kernel_addr(va)));
> +}
> +
> +/*
> + * Check for virtual address in kernel space.
> + */
> +static int arch_check_va_in_kernelspace(unsigned long va)
> +{
> + return is_kernel_addr(va);
> +}
You don't need these two routines. Just use is_kernel_addr() directly,
that way people will know what the code is doing without having to
lookup these new functions.
> +/*
> + * Store a breakpoint's encoded address, length, and type.
> + */
This doesn't "store" in the sense I was thinking, it actually does a
lookup and returns info in the arg.
> +int arch_store_info(struct hw_breakpoint *bp)
> +{
> + /*
> + * User-space requests will always have the address field populated
> + * For kernel-addresses, either the address or symbol name can be
> + * specified.
> + */
Do user-space requests never have the name populated? Otherwise aren't
you overwriting the supplied address with the one from kallsyms?
> + if (bp->info.name)
> + bp->info.address = (unsigned long)
> + kallsyms_lookup_name(bp->info.name);
> + if (bp->info.address)
> + return 0;
> + return -EINVAL;
> +}
> +
> +/*
> + * Validate the arch-specific HW Breakpoint register settings
> + */
> +int arch_validate_hwbkpt_settings(struct hw_breakpoint *bp,
> + struct task_struct *tsk)
> +{
> + int ret = -EINVAL;
> +
> + if (!bp)
> + return ret;
> +
> + switch (bp->info.type) {
> + case DABR_DATA_READ:
> + break;
> + case DABR_DATA_WRITE:
> + break;
> + case DABR_DATA_RW:
> + break;
You only need the final break here.
> + default:
> + return ret;
> + }
> +
> + if (bp->triggered)
> + ret = arch_store_info(bp);
Shouldn't you check ret here, bp->info.address might be bogus.
> +
> + /* Check for double word alignment - 8 bytes */
> + if (bp->info.address & HW_BREAKPOINT_ALIGN)
> + return -EINVAL;
> +
> + /* Check that the virtual address is in the proper range */
> + if (tsk) {
> + if (!arch_check_va_in_userspace(bp->info.address))
> + return -EFAULT;
> + } else {
> + if (!arch_check_va_in_kernelspace(bp->info.address))
> + return -EFAULT;
> + }
Which becomes:
is_kernel = is_kernel_addr(bp->info.address);
if (tsk && is_kernel || !tsk && !is_kernel)
return -EFAULT;
> +void arch_update_user_hw_breakpoint(int pos, struct task_struct *tsk)
> +{
> + struct thread_struct *thread = &(tsk->thread);
> + struct hw_breakpoint *bp = thread->hbp[0];
> +
> + if (bp)
> + thread->dabr = bp->info.address | bp->info.type |
> + DABR_TRANSLATION;
2nd place I've seen that pattern.
> + else
> + thread->dabr = 0;
> +}
> +
> +void arch_flush_thread_hw_breakpoint(struct task_struct *tsk)
> +{
> + struct thread_struct *thread = &(tsk->thread);
> +
> + thread->dabr = 0;
> +}
> +
> +/*
> + * Handle debug exception notifications.
> + */
> +int __kprobes hw_breakpoint_handler(struct die_args *args)
> +{
> + int rc = NOTIFY_STOP;
> + struct hw_breakpoint *bp;
> + struct pt_regs *regs = args->regs;
> + unsigned long dar;
> + int cpu, stepped, is_kernel;
> +
> + /* Disable breakpoints during exception handling */
> + set_dabr(0);
> +
> + dar = regs->dar & (~HW_BREAKPOINT_ALIGN);
> + is_kernel = (dar >= TASK_SIZE) ? 1 : 0;
is_kernel_addr() ?
> + if (is_kernel)
> + bp = hbp_kernel[0];
> + else {
> + bp = current->thread.hbp[0];
> + /* Lazy debug register switching */
> + if (!bp)
> + return rc;
What if we keep hitting this case?
> + rc = NOTIFY_DONE;
> + }
> +
> + (bp->triggered)(bp, regs);
> +
> + cpu = get_cpu();
> + if (is_kernel)
> + per_cpu(dabr_data, cpu) = kdabr;
> + else
> + per_cpu(dabr_data, cpu) = current->thread.dabr;
> +
> + stepped = emulate_step(regs, regs->nip);
> + /*
> + * Single-step the causative instruction manually if
> + * emulate_step() could not execute it
> + */
> + if (stepped == 0) {
> + regs->msr |= MSR_SE;
> + goto out;
> + }
> +
> + set_dabr(per_cpu(dabr_data, cpu));
> +out:
> + /* Enable pre-emption only if single-stepping is finished */
> + if (stepped)
> + put_cpu_no_resched();
> + return rc;
> +}
Gotta run, laptop battery running out! :)
cheers
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: [RFC Patch 6/6] Adapt kexec and samples code to recognise PPC64 hardware breakpoint usage
From: Geert Uytterhoeven @ 2009-05-14 14:18 UTC (permalink / raw)
To: Michael Ellerman
Cc: Michael Neuling, Benjamin Herrenschmidt, linuxppc-dev, paulus,
Alan Stern, K.Prasad, Roland McGrath
In-Reply-To: <1242310317.8608.1.camel@concordia>
On Fri, 15 May 2009, Michael Ellerman wrote:
> On Thu, 2009-05-14 at 15:59 +0200, Geert Uytterhoeven wrote:
> > On Thu, 14 May 2009, K.Prasad wrote:
> > > Modify kexec code to disable DABR registers before a reboot. Adapt the samples
> > > code to populate PPC64-arch specific fields.
> > >
> > > Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
> > > ---
> > > arch/powerpc/kernel/machine_kexec_64.c | 6
> > > samples/hw_breakpoint/data_breakpoint.c | 4
> > >
> > > Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/machine_kexec_64.c
> > > ===================================================================
> > > --- linux-2.6-tip.hbkpt.orig/arch/powerpc/kernel/machine_kexec_64.c 2009-05-14 00:17:24.000000000 +0530
> > > +++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/machine_kexec_64.c 2009-05-14 09:48:09.000000000 +0530
> > > @@ -24,6 +24,7 @@
> > > #include <asm/sections.h> /* _end */
> > > #include <asm/prom.h>
> > > #include <asm/smp.h>
> > > +#include <asm/hw_breakpoint.h>
> > >
> > > int default_machine_kexec_prepare(struct kimage *image)
> > > {
> > > @@ -214,6 +215,9 @@
> > > put_cpu();
> > >
> > > local_irq_disable();
> > > +#ifdef CONFIG_PPC64
> > ^^^^^^^^^^^^^^^^^^^
> > > + hw_breakpoint_disable();
> > > +#endif
> > ^^^^^^
> >
> > What about providing a dummy definition of hw_breakpoint_disable()
> > in <asm/hw_breakpoint.h> if !CONFIG_PPC64?
>
> That would be good.
>
> What would be better, is to notice that machine_kexec_64.c is only ever
> built for 64-bit - hence the name. And so no ifdefs or anything else is
> required.
Right ;-)
But that can't be said for other files, like e.g. arch/powerpc/kernel/ptrace.c.
With kind regards,
Geert Uytterhoeven
Software Architect
Techsoft Centre
Technology and Software Centre Europe
The Corporate Village · Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium
Phone: +32 (0)2 700 8453
Fax: +32 (0)2 700 8622
E-mail: Geert.Uytterhoeven@sonycom.com
Internet: http://www.sony-europe.com/
A division of Sony Europe (Belgium) N.V.
VAT BE 0413.825.160 · RPR Brussels
Fortis · BIC GEBABEBB · IBAN BE41293037680010
^ permalink raw reply
* Re: [RFC Patch 6/6] Adapt kexec and samples code to recognise PPC64 hardware breakpoint usage
From: Michael Ellerman @ 2009-05-14 14:11 UTC (permalink / raw)
To: K.Prasad
Cc: Michael Neuling, Benjamin Herrenschmidt, linuxppc-dev, Alan Stern,
Geert Uytterhoeven, paulus, K.Prasad, Roland McGrath
In-Reply-To: <alpine.LRH.2.00.0905141557260.2225@vixen.sonytel.be>
[-- Attachment #1: Type: text/plain, Size: 1518 bytes --]
On Thu, 2009-05-14 at 15:59 +0200, Geert Uytterhoeven wrote:
> On Thu, 14 May 2009, K.Prasad wrote:
> > Modify kexec code to disable DABR registers before a reboot. Adapt the samples
> > code to populate PPC64-arch specific fields.
> >
> > Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
> > ---
> > arch/powerpc/kernel/machine_kexec_64.c | 6
> > samples/hw_breakpoint/data_breakpoint.c | 4
> >
> > Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/machine_kexec_64.c
> > ===================================================================
> > --- linux-2.6-tip.hbkpt.orig/arch/powerpc/kernel/machine_kexec_64.c 2009-05-14 00:17:24.000000000 +0530
> > +++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/machine_kexec_64.c 2009-05-14 09:48:09.000000000 +0530
> > @@ -24,6 +24,7 @@
> > #include <asm/sections.h> /* _end */
> > #include <asm/prom.h>
> > #include <asm/smp.h>
> > +#include <asm/hw_breakpoint.h>
> >
> > int default_machine_kexec_prepare(struct kimage *image)
> > {
> > @@ -214,6 +215,9 @@
> > put_cpu();
> >
> > local_irq_disable();
> > +#ifdef CONFIG_PPC64
> ^^^^^^^^^^^^^^^^^^^
> > + hw_breakpoint_disable();
> > +#endif
> ^^^^^^
>
> What about providing a dummy definition of hw_breakpoint_disable()
> in <asm/hw_breakpoint.h> if !CONFIG_PPC64?
That would be good.
What would be better, is to notice that machine_kexec_64.c is only ever
built for 64-bit - hence the name. And so no ifdefs or anything else is
required.
cheers
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.
From: Grant Likely @ 2009-05-14 14:00 UTC (permalink / raw)
To: Piotr Zięcik
Cc: Becky Bruce, Wolfgang Denk, Detlev Zundel, John Rigby, netdev,
linuxppc-dev, Scott Wood
In-Reply-To: <200905141438.23348.kosmo@semihalf.com>
2009/5/14 Piotr Zi=EAcik <kosmo@semihalf.com>:
> Thursday 07 May 2009 00:39:25 Grant Likely napisa=B3(a):
>> >> 512x are enabled in the same kernel?
>> >
>> > Hm... both architectures look sufficiently different to me that I
>> > don't see sense in trying such a thing. Do you think that needs to be
>> > supported?
>>
>> Yes! =A0:-) =A0It's not hard to do and it keeps the driver cleaner
>> (IMNSHO). =A0I don't think it is quite possible at the moment due to
>> cache coherency issues, but with Becky's recently merged dma ops
>> changes it should be fixable.
>
> Could you elaborate on the cache coherency issues in MPC5121
> FEC context? Especially how these issues are related to the driver
> binary compatibility.
>
> MPC5121 support was added to drivers/net/fs_enet. MPC52xx uses
> drivers/net/fec_mpc52xx.c. Do you think that creating one universal
> driver from these two is now possible? You said that it should be easy,
> however you also said that cache coherency issues makes this imposible.
Not impossible. Hard.
The mpc5200 is a cache coherent part. Bestcomm memory accesses are
noticed (snooped) by the cache, and it will flush out cache lines
appropriately to maintain coherency.
The mpc5121 bus design is non-coherent. The e300 core is essentially
the same as on the 5200, and the core can do snooping, but the
multiport memory controller on the 5121 doesn't support bus snooping
so the cache is not automatically maintained in a consistent state.
On this part Linux needs to manually flush the relevant cache lines
before initiating DMA transfers, and invalidiate them afterwards.
All of this doesn't actually affect the driver code at all. It's all
handled by the kernel and the DMA apis. What it does affect is
multiplatform kernels. The DMA behaviour is set at compile time, not
run time, depending on the setting of CONFIG_NON_COHERENT_CACHE (see
arch/powerpc/platforms/Kconfig.cputype). A kernel which has it on
won't run properly on a platform which has it off, and visa-versa.
So, while the MPC5200 and MPC5121 (and MPC83xx) all have the same
core, it isn't currently possible to build a single kernel which will
boot on both the MPC5200 and the MPC5121. The solution (i think) is
to kill CONFIG_NON_COHERENT_CACHE and have the platform setup code set
the appropriate dmaops at platform init time.
Cheers,
g.
>
> --
> Best Regards.
> Piotr Ziecik
>
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [RFC Patch 6/6] Adapt kexec and samples code to recognise PPC64 hardware breakpoint usage
From: Geert Uytterhoeven @ 2009-05-14 13:59 UTC (permalink / raw)
To: K.Prasad
Cc: Michael Neuling, Benjamin Herrenschmidt, linuxppc-dev, Alan Stern,
paulus, Roland McGrath
In-Reply-To: <20090514134614.GG14229@in.ibm.com>
On Thu, 14 May 2009, K.Prasad wrote:
> Modify kexec code to disable DABR registers before a reboot. Adapt the samples
> code to populate PPC64-arch specific fields.
>
> Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
> ---
> arch/powerpc/kernel/machine_kexec_64.c | 6
> samples/hw_breakpoint/data_breakpoint.c | 4
>
> Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/machine_kexec_64.c
> ===================================================================
> --- linux-2.6-tip.hbkpt.orig/arch/powerpc/kernel/machine_kexec_64.c 2009-05-14 00:17:24.000000000 +0530
> +++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/machine_kexec_64.c 2009-05-14 09:48:09.000000000 +0530
> @@ -24,6 +24,7 @@
> #include <asm/sections.h> /* _end */
> #include <asm/prom.h>
> #include <asm/smp.h>
> +#include <asm/hw_breakpoint.h>
>
> int default_machine_kexec_prepare(struct kimage *image)
> {
> @@ -214,6 +215,9 @@
> put_cpu();
>
> local_irq_disable();
> +#ifdef CONFIG_PPC64
^^^^^^^^^^^^^^^^^^^
> + hw_breakpoint_disable();
> +#endif
^^^^^^
What about providing a dummy definition of hw_breakpoint_disable()
in <asm/hw_breakpoint.h> if !CONFIG_PPC64?
and if you make it safe to always include <asm/hw_breakpoint.h>, you can
get rid of the #ifdef in e.g.
--- linux-2.6-tip.hbkpt.orig/arch/powerpc/kernel/ptrace.c
+++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/ptrace.c
@@ -37,6 +37,9 @@
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
+#ifdef CONFIG_PPC64
+#include <asm/hw_breakpoint.h>
+#endif
With kind regards,
Geert Uytterhoeven
Software Architect
Techsoft Centre
Technology and Software Centre Europe
The Corporate Village · Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium
Phone: +32 (0)2 700 8453
Fax: +32 (0)2 700 8622
E-mail: Geert.Uytterhoeven@sonycom.com
Internet: http://www.sony-europe.com/
A division of Sony Europe (Belgium) N.V.
VAT BE 0413.825.160 · RPR Brussels
Fortis · BIC GEBABEBB · IBAN BE41293037680010
^ permalink raw reply
* [RFC Patch 6/6] Adapt kexec and samples code to recognise PPC64 hardware breakpoint usage
From: K.Prasad @ 2009-05-14 13:46 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michael Neuling, Benjamin Herrenschmidt, Alan Stern, paulus,
K.Prasad, Roland McGrath
In-Reply-To: <20090514133312.360702378@prasadkr_t60p.in.ibm.com>
Modify kexec code to disable DABR registers before a reboot. Adapt the samples
code to populate PPC64-arch specific fields.
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/kernel/machine_kexec_64.c | 6
samples/hw_breakpoint/data_breakpoint.c | 4
Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/machine_kexec_64.c
===================================================================
--- linux-2.6-tip.hbkpt.orig/arch/powerpc/kernel/machine_kexec_64.c 2009-05-14 00:17:24.000000000 +0530
+++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/machine_kexec_64.c 2009-05-14 09:48:09.000000000 +0530
@@ -24,6 +24,7 @@
#include <asm/sections.h> /* _end */
#include <asm/prom.h>
#include <asm/smp.h>
+#include <asm/hw_breakpoint.h>
int default_machine_kexec_prepare(struct kimage *image)
{
@@ -214,6 +215,9 @@
put_cpu();
local_irq_disable();
+#ifdef CONFIG_PPC64
+ hw_breakpoint_disable();
+#endif
}
#else /* ! SMP */
@@ -233,6 +237,9 @@
if (ppc_md.kexec_cpu_down)
ppc_md.kexec_cpu_down(0, 0);
local_irq_disable();
+#ifdef CONFIG_PPC64
+ hw_breakpoint_disable();
+#endif
}
#endif /* SMP */
Index: linux-2.6-tip.hbkpt/samples/hw_breakpoint/data_breakpoint.c
===================================================================
--- linux-2.6-tip.hbkpt.orig/samples/hw_breakpoint/data_breakpoint.c 2009-05-14 00:17:24.000000000 +0530
+++ linux-2.6-tip.hbkpt/samples/hw_breakpoint/data_breakpoint.c 2009-05-14 00:58:06.000000000 +0530
@@ -54,6 +54,10 @@
sample_hbp.info.type = HW_BREAKPOINT_WRITE;
sample_hbp.info.len = HW_BREAKPOINT_LEN_4;
#endif /* CONFIG_X86 */
+#ifdef CONFIG_PPC64
+ sample_hbp.info.name = ksym_name;
+ sample_hbp.info.type = DABR_DATA_WRITE;
+#endif /* CONFIG_PPC64 */
sample_hbp.triggered = (void *)sample_hbp_handler;
^ permalink raw reply
* [RFC Patch 5/6] Modify Data storage exception code to recognise DABR match first
From: K.Prasad @ 2009-05-14 13:45 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michael Neuling, Benjamin Herrenschmidt, Alan Stern, paulus,
K.Prasad, Roland McGrath
In-Reply-To: <20090514133312.360702378@prasadkr_t60p.in.ibm.com>
Modify Data storage exception code to first lookout for a DABR match before
recognising a kprobe or xmon exception.
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/mm/fault.c | 14 -
Index: linux-2.6-tip.hbkpt/arch/powerpc/mm/fault.c
===================================================================
--- linux-2.6-tip.hbkpt.orig/arch/powerpc/mm/fault.c 2009-05-14 00:17:24.000000000 +0530
+++ linux-2.6-tip.hbkpt/arch/powerpc/mm/fault.c 2009-05-14 00:58:05.000000000 +0530
@@ -137,6 +137,12 @@
error_code &= 0x48200000;
else
is_write = error_code & DSISR_ISSTORE;
+
+ if (error_code & DSISR_DABRMATCH) {
+ /* DABR match */
+ do_dabr(regs, address, error_code);
+ return 0;
+ }
#else
is_write = error_code & ESR_DST;
#endif /* CONFIG_4xx || CONFIG_BOOKE */
@@ -151,14 +157,6 @@
if (!user_mode(regs) && (address >= TASK_SIZE))
return SIGSEGV;
-#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
- if (error_code & DSISR_DABRMATCH) {
- /* DABR match */
- do_dabr(regs, address, error_code);
- return 0;
- }
-#endif /* !(CONFIG_4xx || CONFIG_BOOKE)*/
-
if (in_atomic() || mm == NULL) {
if (!user_mode(regs))
return SIGSEGV;
^ permalink raw reply
* [RFC Patch 4/6] Modify process handling code to handle hardware debug registers
From: K.Prasad @ 2009-05-14 13:45 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michael Neuling, Benjamin Herrenschmidt, Alan Stern, paulus,
K.Prasad, Roland McGrath
In-Reply-To: <20090514133312.360702378@prasadkr_t60p.in.ibm.com>
Modify process handling code to recognise hardware debug registers during copy
and flush operations. Introduce a new TIF_DEBUG task flag to indicate a
process's use of debug register.
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/thread_info.h | 2
arch/powerpc/kernel/process.c | 18 +
Index: linux-2.6-tip.hbkpt/arch/powerpc/include/asm/thread_info.h
===================================================================
--- linux-2.6-tip.hbkpt.orig/arch/powerpc/include/asm/thread_info.h
+++ linux-2.6-tip.hbkpt/arch/powerpc/include/asm/thread_info.h
@@ -114,6 +114,7 @@ static inline struct thread_info *curren
#define TIF_FREEZE 14 /* Freezing for suspend */
#define TIF_RUNLATCH 15 /* Is the runlatch enabled? */
#define TIF_ABI_PENDING 16 /* 32/64 bit switch needed */
+#define TIF_DEBUG 17 /* uses debug registers */
/* as above, but as bit values */
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -132,6 +133,7 @@ static inline struct thread_info *curren
#define _TIF_FREEZE (1<<TIF_FREEZE)
#define _TIF_RUNLATCH (1<<TIF_RUNLATCH)
#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
+#define _TIF_DEBUG (1<<TIF_DEBUG)
#define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
#define _TIF_USER_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/process.c
===================================================================
--- linux-2.6-tip.hbkpt.orig/arch/powerpc/kernel/process.c
+++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/process.c
@@ -50,6 +50,7 @@
#include <asm/syscalls.h>
#ifdef CONFIG_PPC64
#include <asm/firmware.h>
+#include <asm/hw_breakpoint.h>
#endif
#include <linux/kprobes.h>
#include <linux/kdebug.h>
@@ -254,8 +255,10 @@ void do_dabr(struct pt_regs *regs, unsig
11, SIGSEGV) == NOTIFY_STOP)
return;
+#ifndef CONFIG_PPC64
if (debugger_dabr_match(regs))
return;
+#endif
/* Clear the DAC and struct entries. One shot trigger */
#if defined(CONFIG_BOOKE)
@@ -372,8 +375,13 @@ struct task_struct *__switch_to(struct t
#endif /* CONFIG_SMP */
+#ifdef CONFIG_PPC64
+ if (unlikely(test_tsk_thread_flag(new, TIF_DEBUG)))
+ switch_to_thread_hw_breakpoint(new);
+#else
if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
set_dabr(new->thread.dabr);
+#endif /* CONFIG_PPC64 */
#if defined(CONFIG_BOOKE)
/* If new thread DAC (HW breakpoint) is the same then leave it */
@@ -550,6 +558,10 @@ void show_regs(struct pt_regs * regs)
void exit_thread(void)
{
discard_lazy_cpu_state();
+#ifdef CONFIG_PPC64
+ if (unlikely(test_tsk_thread_flag(current, TIF_DEBUG)))
+ flush_thread_hw_breakpoint(current);
+#endif /* CONFIG_PPC64 */
}
void flush_thread(void)
@@ -605,6 +617,9 @@ int copy_thread(unsigned long clone_flag
struct pt_regs *childregs, *kregs;
extern void ret_from_fork(void);
unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
+#ifdef CONFIG_PPC64
+ struct task_struct *tsk = current;
+#endif
CHECK_FULL_REGS(regs);
/* Copy registers */
@@ -672,6 +687,9 @@ int copy_thread(unsigned long clone_flag
* function.
*/
kregs->nip = *((unsigned long *)ret_from_fork);
+
+ if (unlikely(test_tsk_thread_flag(tsk, TIF_DEBUG)))
+ copy_thread_hw_breakpoint(tsk, p, clone_flags);
#else
kregs->nip = (unsigned long)ret_from_fork;
#endif
^ permalink raw reply
* [RFC Patch 3/6] Modify ptrace code to use Hardware Breakpoint interfaces
From: K.Prasad @ 2009-05-14 13:45 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michael Neuling, Benjamin Herrenschmidt, Alan Stern, paulus,
K.Prasad, Roland McGrath
In-Reply-To: <20090514133312.360702378@prasadkr_t60p.in.ibm.com>
Modify the ptrace code to use the hardware breakpoint interfaces for user-space.
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/kernel/ptrace.c | 48 +++++
Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/ptrace.c
===================================================================
--- linux-2.6-tip.hbkpt.orig/arch/powerpc/kernel/ptrace.c
+++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/ptrace.c
@@ -37,6 +37,9 @@
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
+#ifdef CONFIG_PPC64
+#include <asm/hw_breakpoint.h>
+#endif
/*
* does not yet catch signals sent when the child dies.
@@ -735,9 +738,22 @@ void user_disable_single_step(struct tas
clear_tsk_thread_flag(task, TIF_SINGLESTEP);
}
+static void ptrace_triggered(struct hw_breakpoint *bp, struct pt_regs *regs)
+{
+ /*
+ * The SIGTRAP signal is generated automatically for us in do_dabr().
+ * We don't have to do anything here
+ */
+}
+
int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
unsigned long data)
{
+#ifdef CONFIG_PPC64
+ struct thread_struct *thread = &(task->thread);
+ struct hw_breakpoint *bp;
+ int ret;
+#endif
/* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
* For embedded processors we support one DAC and no IAC's at the
* moment.
@@ -767,6 +783,38 @@ int ptrace_set_debugreg(struct task_stru
if (data && !(data & DABR_TRANSLATION))
return -EIO;
+#ifdef CONFIG_PPC64
+ bp = thread->hbp[0];
+ if ((data & ~HW_BREAKPOINT_ALIGN) == 0) {
+ if (bp) {
+ unregister_user_hw_breakpoint(task, bp);
+ kfree(bp);
+ thread->hbp[0] = NULL;
+ }
+ return 0;
+ }
+
+ if (bp) {
+ bp->info.type = data & DABR_DATA_RW;
+ task->thread.dabr = bp->info.address =
+ (data & ~HW_BREAKPOINT_ALIGN);
+ return modify_user_hw_breakpoint(task, bp);
+ }
+ bp = kzalloc(sizeof(struct hw_breakpoint), GFP_KERNEL);
+ if (!bp)
+ return -ENOMEM;
+
+ /* Store the type of breakpoint */
+ bp->info.type = data & DABR_DATA_RW;
+ bp->triggered = ptrace_triggered;
+ task->thread.dabr = bp->info.address = (data & ~HW_BREAKPOINT_ALIGN);
+
+ ret = register_user_hw_breakpoint(task, bp);
+ if (ret)
+ return ret;
+ set_tsk_thread_flag(task, TIF_DEBUG);
+#endif /* CONFIG_PPC64 */
+
/* Move contents to the DABR register */
task->thread.dabr = data;
^ permalink raw reply
* [RFC Patch 2/6] Introduce PPC64 specific Hardware Breakpoint interfaces
From: K.Prasad @ 2009-05-14 13:44 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michael Neuling, Benjamin Herrenschmidt, Alan Stern, paulus,
K.Prasad, Roland McGrath
In-Reply-To: <20090514133312.360702378@prasadkr_t60p.in.ibm.com>
Introduce PPC64 implementation for the generic hardware breakpoint interfaces
defined in kernel/hw_breakpoint.c. Enable the HAVE_HW_BREAKPOINT flag and the
Makefile.
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/Kconfig | 1
arch/powerpc/kernel/Makefile | 2
arch/powerpc/kernel/hw_breakpoint.c | 281 ++++++++++++++++++++++++++++++++++++
3 files changed, 283 insertions(+), 1 deletion(-)
Index: linux-2.6-tip.hbkpt/arch/powerpc/Kconfig
===================================================================
--- linux-2.6-tip.hbkpt.orig/arch/powerpc/Kconfig
+++ linux-2.6-tip.hbkpt/arch/powerpc/Kconfig
@@ -125,6 +125,7 @@ config PPC
select USE_GENERIC_SMP_HELPERS if SMP
select HAVE_OPROFILE
select HAVE_SYSCALL_WRAPPERS if PPC64
+ select HAVE_HW_BREAKPOINT if PPC64
config EARLY_PRINTK
bool
Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/Makefile
===================================================================
--- linux-2.6-tip.hbkpt.orig/arch/powerpc/kernel/Makefile
+++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/Makefile
@@ -33,7 +33,7 @@ obj-$(CONFIG_PPC64) += setup_64.o sys_p
signal_64.o ptrace32.o \
paca.o cpu_setup_ppc970.o \
cpu_setup_pa6t.o \
- firmware.o nvram_64.o
+ firmware.o nvram_64.o hw_breakpoint.o
obj64-$(CONFIG_RELOCATABLE) += reloc_64.o
obj-$(CONFIG_PPC64) += vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o
Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/hw_breakpoint.c
===================================================================
--- /dev/null
+++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/hw_breakpoint.c
@@ -0,0 +1,281 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2009 IBM Corporation
+ */
+
+/*
+ * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
+ * using the CPU's debug registers.
+ */
+
+#include <linux/notifier.h>
+#include <linux/kallsyms.h>
+#include <linux/kprobes.h>
+#include <linux/percpu.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+
+#include <asm/hw_breakpoint.h>
+#include <asm/processor.h>
+#include <asm/sstep.h>
+
+/* Store the kernel-space breakpoint address value */
+static unsigned long kdabr;
+
+/*
+ * Temporarily stores address for DABR before it is written by the
+ * single-step handler routine
+ */
+static DEFINE_PER_CPU(unsigned long, dabr_data);
+
+void arch_update_kernel_hw_breakpoint(void *unused)
+{
+ struct hw_breakpoint *bp;
+
+ /* Check if there is nothing to update */
+ if (hbp_kernel_pos == HBP_NUM)
+ return;
+ bp = hbp_kernel[hbp_kernel_pos];
+ if (bp == NULL)
+ kdabr = 0;
+ else
+ kdabr = bp->info.address | bp->info.type | DABR_TRANSLATION;
+ set_dabr(kdabr);
+}
+
+/*
+ * Install the thread breakpoints in their debug registers.
+ */
+void arch_install_thread_hw_breakpoint(struct task_struct *tsk)
+{
+ set_dabr(tsk->thread.dabr);
+}
+
+/*
+ * Install the debug register values for just the kernel, no thread.
+ */
+void arch_uninstall_thread_hw_breakpoint()
+{
+ set_dabr(0);
+}
+
+/*
+ * Check for virtual address in user space.
+ */
+static int arch_check_va_in_userspace(unsigned long va)
+{
+ return (!(is_kernel_addr(va)));
+}
+
+/*
+ * Check for virtual address in kernel space.
+ */
+static int arch_check_va_in_kernelspace(unsigned long va)
+{
+ return is_kernel_addr(va);
+}
+
+/*
+ * Store a breakpoint's encoded address, length, and type.
+ */
+int arch_store_info(struct hw_breakpoint *bp)
+{
+ /*
+ * User-space requests will always have the address field populated
+ * For kernel-addresses, either the address or symbol name can be
+ * specified.
+ */
+ if (bp->info.name)
+ bp->info.address = (unsigned long)
+ kallsyms_lookup_name(bp->info.name);
+ if (bp->info.address)
+ return 0;
+ return -EINVAL;
+}
+
+/*
+ * Validate the arch-specific HW Breakpoint register settings
+ */
+int arch_validate_hwbkpt_settings(struct hw_breakpoint *bp,
+ struct task_struct *tsk)
+{
+ int ret = -EINVAL;
+
+ if (!bp)
+ return ret;
+
+ switch (bp->info.type) {
+ case DABR_DATA_READ:
+ break;
+ case DABR_DATA_WRITE:
+ break;
+ case DABR_DATA_RW:
+ break;
+ default:
+ return ret;
+ }
+
+ if (bp->triggered)
+ ret = arch_store_info(bp);
+
+ /* Check for double word alignment - 8 bytes */
+ if (bp->info.address & HW_BREAKPOINT_ALIGN)
+ return -EINVAL;
+
+ /* Check that the virtual address is in the proper range */
+ if (tsk) {
+ if (!arch_check_va_in_userspace(bp->info.address))
+ return -EFAULT;
+ } else {
+ if (!arch_check_va_in_kernelspace(bp->info.address))
+ return -EFAULT;
+ }
+
+ return ret;
+}
+
+void arch_update_user_hw_breakpoint(int pos, struct task_struct *tsk)
+{
+ struct thread_struct *thread = &(tsk->thread);
+ struct hw_breakpoint *bp = thread->hbp[0];
+
+ if (bp)
+ thread->dabr = bp->info.address | bp->info.type |
+ DABR_TRANSLATION;
+ else
+ thread->dabr = 0;
+}
+
+void arch_flush_thread_hw_breakpoint(struct task_struct *tsk)
+{
+ struct thread_struct *thread = &(tsk->thread);
+
+ thread->dabr = 0;
+}
+
+/*
+ * Handle debug exception notifications.
+ */
+int __kprobes hw_breakpoint_handler(struct die_args *args)
+{
+ int rc = NOTIFY_STOP;
+ struct hw_breakpoint *bp;
+ struct pt_regs *regs = args->regs;
+ unsigned long dar;
+ int cpu, stepped, is_kernel;
+
+ /* Disable breakpoints during exception handling */
+ set_dabr(0);
+
+ dar = regs->dar & (~HW_BREAKPOINT_ALIGN);
+ is_kernel = (dar >= TASK_SIZE) ? 1 : 0;
+
+ if (is_kernel)
+ bp = hbp_kernel[0];
+ else {
+ bp = current->thread.hbp[0];
+ /* Lazy debug register switching */
+ if (!bp)
+ return rc;
+ rc = NOTIFY_DONE;
+ }
+
+ (bp->triggered)(bp, regs);
+
+ cpu = get_cpu();
+ if (is_kernel)
+ per_cpu(dabr_data, cpu) = kdabr;
+ else
+ per_cpu(dabr_data, cpu) = current->thread.dabr;
+
+ stepped = emulate_step(regs, regs->nip);
+ /*
+ * Single-step the causative instruction manually if
+ * emulate_step() could not execute it
+ */
+ if (stepped == 0) {
+ regs->msr |= MSR_SE;
+ goto out;
+ }
+
+ set_dabr(per_cpu(dabr_data, cpu));
+out:
+ /* Enable pre-emption only if single-stepping is finished */
+ if (stepped)
+ put_cpu_no_resched();
+ return rc;
+}
+
+/*
+ * Handle single-step exceptions following a DABR hit.
+ */
+int __kprobes single_step_dabr_instruction(struct die_args *args)
+{
+ struct pt_regs *regs = args->regs;
+ int cpu = get_cpu();
+ int ret = NOTIFY_DONE;
+ siginfo_t info;
+ unsigned long this_dabr_data = per_cpu(dabr_data, cpu);
+
+ /*
+ * Check if we are single-stepping as a result of a
+ * previous HW Breakpoint exception
+ */
+ if (this_dabr_data == 0)
+ goto out;
+
+ regs->msr &= ~MSR_SE;
+ /* Deliver signal to user-space */
+ if (this_dabr_data < TASK_SIZE) {
+ info.si_signo = SIGTRAP;
+ info.si_errno = 0;
+ info.si_code = TRAP_HWBKPT;
+ info.si_addr = (void __user *)(per_cpu(dabr_data, cpu));
+ force_sig_info(SIGTRAP, &info, current);
+ }
+
+ set_dabr(this_dabr_data);
+ per_cpu(dabr_data, cpu) = 0;
+ ret = NOTIFY_STOP;
+ put_cpu_no_resched();
+
+out:
+ put_cpu_no_resched();
+ return ret;
+}
+
+/*
+ * Handle debug exception notifications.
+ */
+int __kprobes hw_breakpoint_exceptions_notify(
+ struct notifier_block *unused, unsigned long val, void *data)
+{
+ int ret = NOTIFY_DONE;
+
+ switch (val) {
+ case DIE_DABR_MATCH:
+ ret = hw_breakpoint_handler(data);
+ break;
+ case DIE_SSTEP:
+ ret = single_step_dabr_instruction(data);
+ break;
+ }
+
+ return ret;
+}
^ permalink raw reply
* [RFC Patch 1/6] Prepare the PowerPC platform for HW Breakpoint infrastructure
From: K.Prasad @ 2009-05-14 13:43 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michael Neuling, Benjamin Herrenschmidt, Alan Stern, paulus,
K.Prasad, Roland McGrath
In-Reply-To: <20090514133312.360702378@prasadkr_t60p.in.ibm.com>
Prepare the PowerPC code for HW Breakpoint infrastructure patches by including
relevant constant definitions and function declarations.
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/hw_breakpoint.h | 49 +++++
arch/powerpc/include/asm/processor.h | 1
arch/powerpc/include/asm/reg.h | 4
Index: linux-2.6-tip.hbkpt/arch/powerpc/include/asm/hw_breakpoint.h
===================================================================
--- /dev/null
+++ linux-2.6-tip.hbkpt/arch/powerpc/include/asm/hw_breakpoint.h
@@ -0,0 +1,49 @@
+#ifndef _PPC64_HW_BREAKPOINT_H
+#define _PPC64_HW_BREAKPOINT_H
+
+#ifdef __KERNEL__
+#define __ARCH_HW_BREAKPOINT_H
+
+struct arch_hw_breakpoint {
+ char *name; /* Contains name of the symbol to set bkpt */
+ unsigned long address;
+ u8 type;
+};
+
+#include <linux/kdebug.h>
+#include <asm/reg.h>
+#include <asm-generic/hw_breakpoint.h>
+
+#define HW_BREAKPOINT_READ DABR_DATA_READ
+#define HW_BREAKPOINT_WRITE DABR_DATA_WRITE
+#define HW_BREAKPOINT_RW DABR_DATA_RW
+
+#define HW_BREAKPOINT_ALIGN 0x7
+#define HW_BREAKPOINT_LEN INSTRUCTION_LEN
+
+extern struct hw_breakpoint *hbp_kernel[HBP_NUM];
+extern unsigned int hbp_user_refcount[HBP_NUM];
+
+extern void arch_install_thread_hw_breakpoint(struct task_struct *tsk);
+extern void arch_uninstall_thread_hw_breakpoint(void);
+extern int arch_validate_hwbkpt_settings(struct hw_breakpoint *bp,
+ struct task_struct *tsk);
+extern void arch_update_user_hw_breakpoint(int pos, struct task_struct *tsk);
+extern void arch_flush_thread_hw_breakpoint(struct task_struct *tsk);
+extern void arch_update_kernel_hw_breakpoint(void *);
+extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+ unsigned long val, void *data);
+
+extern void flush_thread_hw_breakpoint(struct task_struct *tsk);
+extern int copy_thread_hw_breakpoint(struct task_struct *tsk,
+ struct task_struct *child, unsigned long clone_flags);
+extern void switch_to_thread_hw_breakpoint(struct task_struct *tsk);
+
+static inline void hw_breakpoint_disable(void)
+{
+ set_dabr(0);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _PPC64_HW_BREAKPOINT_H */
+
Index: linux-2.6-tip.hbkpt/arch/powerpc/include/asm/processor.h
===================================================================
--- linux-2.6-tip.hbkpt.orig/arch/powerpc/include/asm/processor.h
+++ linux-2.6-tip.hbkpt/arch/powerpc/include/asm/processor.h
@@ -177,6 +177,7 @@ struct thread_struct {
#ifdef CONFIG_PPC64
unsigned long start_tb; /* Start purr when proc switched in */
unsigned long accum_tb; /* Total accumilated purr for process */
+ struct hw_breakpoint *hbp[HBP_NUM];
#endif
unsigned long dabr; /* Data address breakpoint register */
#ifdef CONFIG_ALTIVEC
Index: linux-2.6-tip.hbkpt/arch/powerpc/include/asm/reg.h
===================================================================
--- linux-2.6-tip.hbkpt.orig/arch/powerpc/include/asm/reg.h
+++ linux-2.6-tip.hbkpt/arch/powerpc/include/asm/reg.h
@@ -26,6 +26,8 @@
#include <asm/reg_8xx.h>
#endif /* CONFIG_8xx */
+#define INSTRUCTION_LEN 4 /* Length of any instruction */
+
#define MSR_SF_LG 63 /* Enable 64 bit mode */
#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
#define MSR_HV_LG 60 /* Hypervisor state */
@@ -184,9 +186,11 @@
#define CTRL_TE 0x00c00000 /* thread enable */
#define CTRL_RUNLATCH 0x1
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
+#define HBP_NUM 1 /* Number of physical HW breakpoint registers */
#define DABR_TRANSLATION (1UL << 2)
#define DABR_DATA_WRITE (1UL << 1)
#define DABR_DATA_READ (1UL << 0)
+#define DABR_DATA_RW (3UL << 0)
#define SPRN_DABR2 0x13D /* e300 */
#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
#define DABRX_USER (1UL << 0)
^ permalink raw reply
* [RFC Patch 0/6] PPC64: Hardware Breakpoint interfaces - ver II
From: K.Prasad @ 2009-05-14 13:42 UTC (permalink / raw)
To: linuxppc-dev
Cc: Alan Stern, Michael Neuling, Benjamin Herrenschmidt, paulus,
Roland McGrath
Hi All,
Please find a revised patchset that implement hardware breakpoint
interfaces for PPC64 architecture. The changes over the previous patchset
posted here: http://ozlabs.org/pipermail/linuxppc-dev/2009-May/071942.html
are given below.
Kindly let me know your comments about the same.
Changelog - ver II
------------------
(Ver I: http://ozlabs.org/pipermail/linuxppc-dev/2009-May/071942.html)
- Split the monolithic patch into six logical patches
- Changed the signature of arch_check_va_in_<user><kernel>space functions. They
are now marked static.
- HB_NUM is now called as HBP_NUM (to preserve a consistent short-name
convention)
- Introduced hw_breakpoint_disable() and changes to kexec code to disable
breakpoints before a reboot.
- Minor changes in ptrace code to use macro-defined constants instead of
numbers.
- Introduced a new constant definition INSTRUCTION_LEN in reg.h
Thanks,
K.Prasad
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox