* [PATCH] qe_lib: Set gpio data before changing the direction to output
From: Michael Barkowski @ 2009-08-18 20:59 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Timur Tabi
This avoids having a short glitch if the desired initial value is not
the same as what was previously in the data register.
Signed-off-by: Michael Barkowski <michaelbarkowski@ruggedcom.com>
---
I can't think of a reason not to do this. The data register has no
effect except when the pin is configured as an output, right?
Please enlighten me if this is not correct. The behaviour I see gels
with my thinking, but there may be a case I haven't thought of.
arch/powerpc/sysdev/qe_lib/gpio.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c b/arch/powerpc/sysdev/qe_lib/gpio.c
index 3485288..e7bf136 100644
--- a/arch/powerpc/sysdev/qe_lib/gpio.c
+++ b/arch/powerpc/sysdev/qe_lib/gpio.c
@@ -107,12 +107,11 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
spin_lock_irqsave(&qe_gc->lock, flags);
+ qe_gpio_set(gc, gpio, val);
__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
spin_unlock_irqrestore(&qe_gc->lock, flags);
- qe_gpio_set(gc, gpio, val);
-
return 0;
}
--
1.6.3.3
^ permalink raw reply related
* Re: [PATCH/RFC] powerpc/mm: Cleanup handling of execute permission
From: Josh Boyer @ 2009-08-18 20:56 UTC (permalink / raw)
To: Becky Bruce; +Cc: Kumar Gala, linuxppc-dev list
In-Reply-To: <FBB5798A-EE85-4B18-8883-F6182B203996@kernel.crashing.org>
On Fri, Aug 14, 2009 at 05:39:42PM -0500, Becky Bruce wrote:
> Ben,
>
> This breaks the boot on 8572. I don't know why yet (and I'm probably
> not going to figure it out before I go home, because, frankly, it's late
> on a Friday afternoon and I need a glass of wine or, perhaps, a beer).
>
> Kumar and I will poke into this more and let you know what we find out -
> in the meantime, if you have any brilliant flashes, pony up!
I tested this on a 440EPx NFS rootfs boot too. It doesn't cause init itself
to crap out with a SIGILL like Becky's board, but it does do weird things
and cause a SIGILL elsewhere during my boot.
Reverting this patch from your testing branch allows things to work just fine.
josh
^ permalink raw reply
* Re: [PATCH] mpc8xxx_spi: Fix polarity inversion in chipselect
From: Michael Barkowski @ 2009-08-18 16:02 UTC (permalink / raw)
Cc: linuxppc-dev
In-Reply-To: <4A8AC5D4.9070602@ruggedcom.com>
Anton - thanks for the offline correction.
SPI_CS_HIGH means that the device interprets high as active.
The alow flag means there is an inverter somewhere.
My mistake - patch retracted.
--
Michael
^ permalink raw reply
* [PATCH] net: add Xilinx emac lite device driver
From: John Linn @ 2009-08-18 15:30 UTC (permalink / raw)
To: netdev, linuxppc-dev, jgarzik, davem
Cc: Sadanand M, Michal Simek, John Linn, John Williams
This patch adds support for the Xilinx Ethernet Lite device. The
soft logic core from Xilinx is typically used on Virtex and Spartan
designs attached to either a PowerPC or a Microblaze processor.
CC: Grant Likely <grant.likely@secretlab.ca>
CC: Josh Boyer <jwboyer@linux.vnet.ibm.com>
CC: John Williams <john.williams@petalogix.com>
CC: Michal Simek <michal.simek@petalogix.com>
Signed-off-by: Sadanand M <sadanan@xilinx.com>
Signed-off-by: John Linn <john.linn@xilinx.com>
---
drivers/net/Kconfig | 5 +
drivers/net/Makefile | 1 +
drivers/net/xilinx_emaclite.c | 1040 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 1046 insertions(+), 0 deletions(-)
create mode 100755 drivers/net/xilinx_emaclite.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 5f6509a..84a5120 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1926,6 +1926,11 @@ config ATL2
To compile this driver as a module, choose M here. The module
will be called atl2.
+config XILINX_EMACLITE
+ tristate "Xilinx 10/100 Ethernet Lite support"
+ help
+ This driver supports the 10/100 Ethernet Lite from Xilinx.
+
source "drivers/net/fs_enet/Kconfig"
endif # NET_ETHERNET
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index ead8cab..99ae6d7 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -142,6 +142,7 @@ obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
ll_temac-objs := ll_temac_main.o ll_temac_mdio.o
obj-$(CONFIG_XILINX_LL_TEMAC) += ll_temac.o
+obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
obj-$(CONFIG_QLA3XXX) += qla3xxx.o
obj-$(CONFIG_QLGE) += qlge/
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
new file mode 100755
index 0000000..3716e20
--- /dev/null
+++ b/drivers/net/xilinx_emaclite.c
@@ -0,0 +1,1040 @@
+/*
+ * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device.
+ *
+ * This is a new flat driver which is based on the original emac_lite
+ * driver from John Williams <john.williams@petalogix.com>.
+ *
+ * 2007-2009 (c) Xilinx, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/uaccess.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/io.h>
+
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+
+#define DRIVER_NAME "xilinx_emaclite"
+
+/* Register offsets for the EmacLite Core */
+#define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */
+#define XEL_GIER_OFFSET 0x07F8 /* GIE Register */
+#define XEL_TSR_OFFSET 0x07FC /* Tx status */
+#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
+
+#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
+#define XEL_RPLR_OFFSET 0x100C /* Rx packet length */
+#define XEL_RSR_OFFSET 0x17FC /* Rx status */
+
+#define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */
+
+/* Global Interrupt Enable Register (GIER) Bit Masks */
+#define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */
+
+/* Transmit Status Register (TSR) Bit Masks */
+#define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */
+#define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */
+#define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */
+#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit
+ * only. This is not documented
+ * in the HW spec */
+
+/* Define for programming the MAC address into the EmacLite */
+#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
+
+/* Receive Status Register (RSR) */
+#define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */
+#define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */
+
+/* Transmit Packet Length Register (TPLR) */
+#define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */
+
+/* Receive Packet Length Register (RPLR) */
+#define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */
+
+#define XEL_HEADER_OFFSET 12 /* Offset to length field */
+#define XEL_HEADER_SHIFT 16 /* Shift value for length */
+
+/* General Ethernet Definitions */
+#define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */
+#define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */
+
+
+
+#define TX_TIMEOUT (60*HZ) /* Tx timeout is 60 seconds. */
+#define ALIGNMENT 4
+
+/* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */
+#define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32) adr)) % ALIGNMENT)
+
+/**
+ * struct net_local - Our private per device data
+ * @ndev: instance of the network device
+ * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW
+ * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW
+ * @next_tx_buf_to_use: next Tx buffer to write to
+ * @next_rx_buf_to_use: next Rx buffer to read from
+ * @base_addr: base address of the Emaclite device
+ * @reset_lock: lock used for synchronization
+ * @deferred_skb: holds an skb (for transmission at a later time) when the
+ * Tx buffer is not free
+ */
+struct net_local {
+
+ struct net_device *ndev;
+
+ bool tx_ping_pong;
+ bool rx_ping_pong;
+ u32 next_tx_buf_to_use;
+ u32 next_rx_buf_to_use;
+ void __iomem *base_addr;
+
+ spinlock_t reset_lock;
+ struct sk_buff *deferred_skb;
+};
+
+
+/*************************/
+/* EmacLite driver calls */
+/*************************/
+
+/**
+ * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device
+ * @drvdata: Pointer to the Emaclite device private data
+ *
+ * This function enables the Tx and Rx interrupts for the Emaclite device along
+ * with the Global Interrupt Enable.
+ */
+static void xemaclite_enable_interrupts(struct net_local *drvdata)
+{
+ u32 reg_data;
+
+ /* Enable the Tx interrupts for the first Buffer */
+ reg_data = in_be32(drvdata->base_addr + XEL_TSR_OFFSET);
+ out_be32(drvdata->base_addr + XEL_TSR_OFFSET,
+ reg_data | XEL_TSR_XMIT_IE_MASK);
+
+ /* Enable the Tx interrupts for the second Buffer if
+ * configured in HW */
+ if (drvdata->tx_ping_pong != 0) {
+ reg_data = in_be32(drvdata->base_addr +
+ XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
+ out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
+ XEL_TSR_OFFSET,
+ reg_data | XEL_TSR_XMIT_IE_MASK);
+ }
+
+ /* Enable the Rx interrupts for the first buffer */
+ reg_data = in_be32(drvdata->base_addr + XEL_RSR_OFFSET);
+ out_be32(drvdata->base_addr + XEL_RSR_OFFSET,
+ reg_data | XEL_RSR_RECV_IE_MASK);
+
+ /* Enable the Rx interrupts for the second Buffer if
+ * configured in HW */
+ if (drvdata->rx_ping_pong != 0) {
+ reg_data = in_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
+ XEL_RSR_OFFSET);
+ out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
+ XEL_RSR_OFFSET,
+ reg_data | XEL_RSR_RECV_IE_MASK);
+ }
+
+ /* Enable the Global Interrupt Enable */
+ out_be32(drvdata->base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
+}
+
+/**
+ * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device
+ * @drvdata: Pointer to the Emaclite device private data
+ *
+ * This function disables the Tx and Rx interrupts for the Emaclite device,
+ * along with the Global Interrupt Enable.
+ */
+static void xemaclite_disable_interrupts(struct net_local *drvdata)
+{
+ u32 reg_data;
+
+ /* Disable the Global Interrupt Enable */
+ out_be32(drvdata->base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
+
+ /* Disable the Tx interrupts for the first buffer */
+ reg_data = in_be32(drvdata->base_addr + XEL_TSR_OFFSET);
+ out_be32(drvdata->base_addr + XEL_TSR_OFFSET,
+ reg_data & (~XEL_TSR_XMIT_IE_MASK));
+
+ /* Disable the Tx interrupts for the second Buffer
+ * if configured in HW */
+ if (drvdata->tx_ping_pong != 0) {
+ reg_data = in_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
+ XEL_TSR_OFFSET);
+ out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
+ XEL_TSR_OFFSET,
+ reg_data & (~XEL_TSR_XMIT_IE_MASK));
+ }
+
+ /* Disable the Rx interrupts for the first buffer */
+ reg_data = in_be32(drvdata->base_addr + XEL_RSR_OFFSET);
+ out_be32(drvdata->base_addr + XEL_RSR_OFFSET,
+ reg_data & (~XEL_RSR_RECV_IE_MASK));
+
+ /* Disable the Rx interrupts for the second buffer
+ * if configured in HW */
+ if (drvdata->rx_ping_pong != 0) {
+
+ reg_data = in_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
+ XEL_RSR_OFFSET);
+ out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
+ XEL_RSR_OFFSET,
+ reg_data & (~XEL_RSR_RECV_IE_MASK));
+ }
+}
+
+/**
+ * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address
+ * @src_ptr: Void pointer to the 16-bit aligned source address
+ * @dest_ptr: Pointer to the 32-bit aligned destination address
+ * @length: Number bytes to write from source to destination
+ *
+ * This function writes data from a 16-bit aligned buffer to a 32-bit aligned
+ * address in the EmacLite device.
+ */
+static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr,
+ unsigned length)
+{
+ u32 align_buffer;
+ u32 *to_u32_ptr;
+ u16 *from_u16_ptr, *to_u16_ptr;
+
+ to_u32_ptr = dest_ptr;
+ from_u16_ptr = (u16 *) src_ptr;
+ align_buffer = 0;
+
+ for (; length > 3; length -= 4) {
+ to_u16_ptr = (u16 *) ((void *) &align_buffer);
+ *to_u16_ptr++ = *from_u16_ptr++;
+ *to_u16_ptr++ = *from_u16_ptr++;
+
+ /* Output a word */
+ *to_u32_ptr++ = align_buffer;
+ }
+ if (length) {
+ u8 *from_u8_ptr, *to_u8_ptr;
+
+ /* Set up to output the remaining data */
+ align_buffer = 0;
+ to_u8_ptr = (u8 *) &align_buffer;
+ from_u8_ptr = (u8 *) from_u16_ptr;
+
+ /* Output the remaining data */
+ for (; length > 0; length--)
+ *to_u8_ptr++ = *from_u8_ptr++;
+
+ *to_u32_ptr = align_buffer;
+ }
+}
+
+/**
+ * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer
+ * @src_ptr: Pointer to the 32-bit aligned source address
+ * @dest_ptr: Pointer to the 16-bit aligned destination address
+ * @length: Number bytes to read from source to destination
+ *
+ * This function reads data from a 32-bit aligned address in the EmacLite device
+ * to a 16-bit aligned buffer.
+ */
+static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr,
+ unsigned length)
+{
+ u16 *to_u16_ptr, *from_u16_ptr;
+ u32 *from_u32_ptr;
+ u32 align_buffer;
+
+ from_u32_ptr = src_ptr;
+ to_u16_ptr = (u16 *) dest_ptr;
+
+ for (; length > 3; length -= 4) {
+ /* Copy each word into the temporary buffer */
+ align_buffer = *from_u32_ptr++;
+ from_u16_ptr = (u16 *)&align_buffer;
+
+ /* Read data from source */
+ *to_u16_ptr++ = *from_u16_ptr++;
+ *to_u16_ptr++ = *from_u16_ptr++;
+ }
+
+ if (length) {
+ u8 *to_u8_ptr, *from_u8_ptr;
+
+ /* Set up to read the remaining data */
+ to_u8_ptr = (u8 *) to_u16_ptr;
+ align_buffer = *from_u32_ptr++;
+ from_u8_ptr = (u8 *) &align_buffer;
+
+ /* Read the remaining data */
+ for (; length > 0; length--)
+ *to_u8_ptr = *from_u8_ptr;
+ }
+}
+
+/**
+ * xemaclite_send_data - Send an Ethernet frame
+ * @drvdata: Pointer to the Emaclite device private data
+ * @data: Pointer to the data to be sent
+ * @byte_count: Total frame size, including header
+ *
+ * This function checks if the Tx buffer of the Emaclite device is free to send
+ * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it
+ * returns an error.
+ *
+ * Return: 0 upon success or -1 if the buffer(s) are full.
+ *
+ * Note: The maximum Tx packet size can not be more than Ethernet header
+ * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS.
+ */
+static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
+ unsigned int byte_count)
+{
+ u32 reg_data;
+ void __iomem *addr;
+
+ /* Determine the expected Tx buffer address */
+ addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
+
+ /* If the length is too large, truncate it */
+ if (byte_count > ETH_FRAME_LEN)
+ byte_count = ETH_FRAME_LEN;
+
+ /* Check if the expected buffer is available */
+ reg_data = in_be32(addr + XEL_TSR_OFFSET);
+ if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
+ XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
+
+ /* Switch to next buffer if configured */
+ if (drvdata->tx_ping_pong != 0)
+ drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET;
+ } else if (drvdata->tx_ping_pong != 0) {
+ /* If the expected buffer is full, try the other buffer,
+ * if it is configured in HW */
+
+ addr = (void __iomem __force *)((u32 __force)addr ^
+ XEL_BUFFER_OFFSET);
+ reg_data = in_be32(addr + XEL_TSR_OFFSET);
+
+ if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
+ XEL_TSR_XMIT_ACTIVE_MASK)) != 0)
+ return -1; /* Buffers were full, return failure */
+ } else
+ return -1; /* Buffer was full, return failure */
+
+ /* Write the frame to the buffer */
+ xemaclite_aligned_write(data, (u32 __force *) addr, byte_count);
+
+ out_be32(addr + XEL_TPLR_OFFSET, (byte_count & XEL_TPLR_LENGTH_MASK));
+
+ /* Update the Tx Status Register to indicate that there is a
+ * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which
+ * is used by the interrupt handler to check whether a frame
+ * has been transmitted */
+ reg_data = in_be32(addr + XEL_TSR_OFFSET);
+ reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK);
+ out_be32(addr + XEL_TSR_OFFSET, reg_data);
+
+ return 0;
+}
+
+/**
+ * xemaclite_recv_data - Receive a frame
+ * @drvdata: Pointer to the Emaclite device private data
+ * @data: Address where the data is to be received
+ *
+ * This function is intended to be called from the interrupt context or
+ * with a wrapper which waits for the receive frame to be available.
+ *
+ * Return: Total number of bytes received
+ */
+static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data)
+{
+ void __iomem *addr;
+ u16 length, proto_type;
+ u32 reg_data;
+
+ /* Determine the expected buffer address */
+ addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);
+
+ /* Verify which buffer has valid data */
+ reg_data = in_be32(addr + XEL_RSR_OFFSET);
+
+ if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
+ if (drvdata->rx_ping_pong != 0)
+ drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET;
+ } else {
+ /* The instance is out of sync, try other buffer if other
+ * buffer is configured, return 0 otherwise. If the instance is
+ * out of sync, do not update the 'next_rx_buf_to_use' since it
+ * will correct on subsequent calls */
+ if (drvdata->rx_ping_pong != 0)
+ addr = (void __iomem __force *)((u32 __force)addr ^
+ XEL_BUFFER_OFFSET);
+ else
+ return 0; /* No data was available */
+
+ /* Verify that buffer has valid data */
+ reg_data = in_be32(addr + XEL_RSR_OFFSET);
+ if ((reg_data & XEL_RSR_RECV_DONE_MASK) !=
+ XEL_RSR_RECV_DONE_MASK)
+ return 0; /* No data was available */
+ }
+
+ /* Get the protocol type of the ethernet frame that arrived */
+ proto_type = ((in_be32(addr + XEL_HEADER_OFFSET +
+ XEL_RXBUFF_OFFSET) >> XEL_HEADER_SHIFT) &
+ XEL_RPLR_LENGTH_MASK);
+
+ /* Check if received ethernet frame is a raw ethernet frame
+ * or an IP packet or an ARP packet */
+ if (proto_type > (ETH_FRAME_LEN + ETH_FCS_LEN)) {
+
+ if (proto_type == ETH_P_IP) {
+ length = ((in_be32(addr +
+ XEL_HEADER_IP_LENGTH_OFFSET +
+ XEL_RXBUFF_OFFSET) >>
+ XEL_HEADER_SHIFT) &
+ XEL_RPLR_LENGTH_MASK);
+ length += ETH_HLEN + ETH_FCS_LEN;
+
+ } else if (proto_type == ETH_P_ARP)
+ length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN;
+ else
+ /* Field contains type other than IP or ARP, use max
+ * frame size and let user parse it */
+ length = ETH_FRAME_LEN + ETH_FCS_LEN;
+ } else
+ /* Use the length in the frame, plus the header and trailer */
+ length = proto_type + ETH_HLEN + ETH_FCS_LEN;
+
+ /* Read from the EmacLite device */
+ xemaclite_aligned_read((u32 __force *) (addr + XEL_RXBUFF_OFFSET),
+ data, length);
+
+ /* Acknowledge the frame */
+ reg_data = in_be32(addr + XEL_RSR_OFFSET);
+ reg_data &= ~XEL_RSR_RECV_DONE_MASK;
+ out_be32(addr + XEL_RSR_OFFSET, reg_data);
+
+ return length;
+}
+
+/**
+ * xemaclite_set_mac_address - Set the MAC address for this device
+ * @drvdata: Pointer to the Emaclite device private data
+ * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value)
+ *
+ * Tx must be idle and Rx should be idle for deterministic results.
+ * It is recommended that this function should be called after the
+ * initialization and before transmission of any packets from the device.
+ * The MAC address can be programmed using any of the two transmit
+ * buffers (if configured).
+ */
+static void xemaclite_set_mac_address(struct net_local *drvdata,
+ u8 *address_ptr)
+{
+ void __iomem *addr;
+ u32 reg_data;
+
+ /* Determine the expected Tx buffer address */
+ addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
+
+ xemaclite_aligned_write(address_ptr, (u32 __force *) addr, ETH_ALEN);
+
+ out_be32(addr + XEL_TPLR_OFFSET, ETH_ALEN);
+
+ /* Update the MAC address in the EmacLite */
+ reg_data = in_be32(addr + XEL_TSR_OFFSET);
+ out_be32(addr + XEL_TSR_OFFSET, reg_data | XEL_TSR_PROG_MAC_ADDR);
+
+ /* Wait for EmacLite to finish with the MAC address update */
+ while ((in_be32(addr + XEL_TSR_OFFSET) &
+ XEL_TSR_PROG_MAC_ADDR) != 0)
+ ;
+}
+
+/**
+ * xemaclite_tx_timeout - Callback for Tx Timeout
+ * @dev: Pointer to the network device
+ *
+ * This function is called when Tx time out occurs for Emaclite device.
+ */
+static void xemaclite_tx_timeout(struct net_device *dev)
+{
+ struct net_local *lp = (struct net_local *) netdev_priv(dev);
+ unsigned long flags;
+
+ dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n",
+ TX_TIMEOUT * 1000UL / HZ);
+
+ dev->stats.tx_errors++;
+
+ /* Reset the device */
+ spin_lock_irqsave(&lp->reset_lock, flags);
+
+ /* Shouldn't really be necessary, but shouldn't hurt */
+ netif_stop_queue(dev);
+
+ xemaclite_disable_interrupts(lp);
+ xemaclite_enable_interrupts(lp);
+
+ if (lp->deferred_skb) {
+ dev_kfree_skb(lp->deferred_skb);
+ lp->deferred_skb = NULL;
+ dev->stats.tx_errors++;
+ }
+
+ /* To exclude tx timeout */
+ dev->trans_start = 0xffffffff - TX_TIMEOUT - TX_TIMEOUT;
+
+ /* We're all ready to go. Start the queue */
+ netif_wake_queue(dev);
+ spin_unlock_irqrestore(&lp->reset_lock, flags);
+}
+
+/**********************/
+/* Interrupt Handlers */
+/**********************/
+
+/**
+ * xemaclite_tx_handler - Interrupt handler for frames sent
+ * @dev: Pointer to the network device
+ *
+ * This function updates the number of packets transmitted and handles the
+ * deferred skb, if there is one.
+ */
+static void xemaclite_tx_handler(struct net_device *dev)
+{
+ struct net_local *lp = (struct net_local *) netdev_priv(dev);
+
+ dev->stats.tx_packets++;
+ if (lp->deferred_skb) {
+ if (xemaclite_send_data(lp,
+ (u8 *) lp->deferred_skb->data,
+ lp->deferred_skb->len) != 0)
+ return;
+ else {
+ dev->stats.tx_bytes += lp->deferred_skb->len;
+ dev_kfree_skb_irq(lp->deferred_skb);
+ lp->deferred_skb = NULL;
+ dev->trans_start = jiffies;
+ netif_wake_queue(dev);
+ }
+ }
+}
+
+/**
+ * xemaclite_rx_handler- Interrupt handler for frames received
+ * @dev: Pointer to the network device
+ *
+ * This function allocates memory for a socket buffer, fills it with data
+ * received and hands it over to the TCP/IP stack.
+ */
+static void xemaclite_rx_handler(struct net_device *dev)
+{
+ struct net_local *lp = (struct net_local *) netdev_priv(dev);
+ struct sk_buff *skb;
+ unsigned int align;
+ u32 len;
+
+ len = ETH_FRAME_LEN + ETH_FCS_LEN;
+ skb = dev_alloc_skb(len + ALIGNMENT);
+ if (!skb) {
+ /* Couldn't get memory. */
+ dev->stats.rx_dropped++;
+ dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n");
+ return;
+ }
+
+ /*
+ * A new skb should have the data halfword aligned, but this code is
+ * here just in case that isn't true. Calculate how many
+ * bytes we should reserve to get the data to start on a word
+ * boundary */
+ align = BUFFER_ALIGN(skb->data);
+ if (align)
+ skb_reserve(skb, align);
+
+ skb_reserve(skb, 2);
+
+ len = xemaclite_recv_data(lp, (u8 *) skb->data);
+
+ if (!len) {
+ dev->stats.rx_errors++;
+ dev_kfree_skb_irq(skb);
+ return;
+ }
+
+ skb_put(skb, len); /* Tell the skb how much data we got */
+ skb->dev = dev; /* Fill out required meta-data */
+
+ skb->protocol = eth_type_trans(skb, dev);
+ skb->ip_summed = CHECKSUM_NONE;
+
+ dev->stats.rx_packets++;
+ dev->stats.rx_bytes += len;
+ dev->last_rx = jiffies;
+
+ netif_rx(skb); /* Send the packet upstream */
+}
+
+/**
+ * xemaclite_interrupt - Interrupt handler for this driver
+ * @irq: Irq of the Emaclite device
+ * @dev_id: Void pointer to the network device instance used as callback
+ * reference
+ *
+ * This function handles the Tx and Rx interrupts of the EmacLite device.
+ */
+static irqreturn_t xemaclite_interrupt(int irq, void *dev_id)
+{
+ bool tx_complete = 0;
+ struct net_device *dev = dev_id;
+ struct net_local *lp = (struct net_local *) netdev_priv(dev);
+ void __iomem *base_addr = lp->base_addr;
+ u32 tx_status;
+
+ /* Check if there is Rx Data available */
+ if ((in_be32(base_addr + XEL_RSR_OFFSET) & XEL_RSR_RECV_DONE_MASK) ||
+ (in_be32(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
+ & XEL_RSR_RECV_DONE_MASK))
+
+ xemaclite_rx_handler(dev);
+
+ /* Check if the Transmission for the first buffer is completed */
+ tx_status = in_be32(base_addr + XEL_TSR_OFFSET);
+ if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
+ (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
+
+ tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
+ out_be32(base_addr + XEL_TSR_OFFSET, tx_status);
+
+ tx_complete = 1;
+ }
+
+ /* Check if the Transmission for the second buffer is completed */
+ tx_status = in_be32(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
+ if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
+ (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
+
+ tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
+ out_be32(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET,
+ tx_status);
+
+ tx_complete = 1;
+ }
+
+ /* If there was a Tx interrupt, call the Tx Handler */
+ if (tx_complete != 0)
+ xemaclite_tx_handler(dev);
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * xemaclite_open - Open the network device
+ * @dev: Pointer to the network device
+ *
+ * This function sets the MAC address, requests an IRQ and enables interrupts
+ * for the Emaclite device and starts the Tx queue.
+ */
+static int xemaclite_open(struct net_device *dev)
+{
+ struct net_local *lp = (struct net_local *) netdev_priv(dev);
+ int retval;
+
+ /* Just to be safe, stop the device first */
+ xemaclite_disable_interrupts(lp);
+
+ /* Set the MAC address each time opened */
+ xemaclite_set_mac_address(lp, dev->dev_addr);
+
+ /* Grab the IRQ */
+ retval = request_irq(dev->irq, &xemaclite_interrupt, 0, dev->name, dev);
+ if (retval) {
+ dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n",
+ dev->irq);
+ return retval;
+ }
+
+ /* Enable Interrupts */
+ xemaclite_enable_interrupts(lp);
+
+ /* We're ready to go */
+ netif_start_queue(dev);
+
+ return 0;
+}
+
+/**
+ * xemaclite_close - Close the network device
+ * @dev: Pointer to the network device
+ *
+ * This function stops the Tx queue, disables interrupts and frees the IRQ for
+ * the Emaclite device.
+ */
+static int xemaclite_close(struct net_device *dev)
+{
+ struct net_local *lp = (struct net_local *) netdev_priv(dev);
+
+ netif_stop_queue(dev);
+ xemaclite_disable_interrupts(lp);
+ free_irq(dev->irq, dev);
+
+ return 0;
+}
+
+/**
+ * xemaclite_get_stats - Get the stats for the net_device
+ * @dev: Pointer to the network device
+ *
+ * This function returns the address of the 'net_device_stats' structure for the
+ * given network device. This structure holds usage statistics for the network
+ * device.
+ *
+ * Return: Pointer to the net_device_stats structure.
+ */
+static struct net_device_stats *xemaclite_get_stats(struct net_device *dev)
+{
+ return &dev->stats;
+}
+
+/**
+ * xemaclite_send - Transmit a frame
+ * @orig_skb: Pointer to the socket buffer to be transmitted
+ * @dev: Pointer to the network device
+ *
+ * This function checks if the Tx buffer of the Emaclite device is free to send
+ * data. If so, it fills the Tx buffer with data from socket buffer data,
+ * updates the stats and frees the socket buffer. The Tx completion is signaled
+ * by an interrupt. If the Tx buffer isn't free, then the socket buffer is
+ * deferred and the Tx queue is stopped so that the deferred socket buffer can
+ * be transmitted when the Emaclite device is free to transmit data.
+ *
+ * Return: 0, always.
+ */
+static int xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev)
+{
+ struct net_local *lp = (struct net_local *) netdev_priv(dev);
+ struct sk_buff *new_skb;
+ unsigned int len;
+ unsigned long flags;
+
+ len = orig_skb->len;
+
+ new_skb = orig_skb;
+
+ spin_lock_irqsave(&lp->reset_lock, flags);
+ if (xemaclite_send_data(lp, (u8 *) new_skb->data, len) != 0) {
+ /* If the Emaclite Tx buffer is busy, stop the Tx queue and
+ * defer the skb for transmission at a later point when the
+ * current transmission is complete */
+ netif_stop_queue(dev);
+ lp->deferred_skb = new_skb;
+ spin_unlock_irqrestore(&lp->reset_lock, flags);
+ return 0;
+ }
+ spin_unlock_irqrestore(&lp->reset_lock, flags);
+
+ dev->stats.tx_bytes += len;
+ dev_kfree_skb(new_skb);
+ dev->trans_start = jiffies;
+
+ return 0;
+}
+
+/**
+ * xemaclite_ioctl - Perform IO Control operations on the network device
+ * @dev: Pointer to the network device
+ * @rq: Pointer to the interface request structure
+ * @cmd: IOCTL command
+ *
+ * The only IOCTL operation supported by this function is setting the MAC
+ * address. An error is reported if any other operations are requested.
+ *
+ * Return: 0 to indicate success, or a negative error for failure.
+ */
+static int xemaclite_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+ struct net_local *lp = (struct net_local *) netdev_priv(dev);
+ struct hw_addr_data *hw_addr = (struct hw_addr_data *) &rq->ifr_hwaddr;
+
+ switch (cmd) {
+ case SIOCETHTOOL:
+ return -EIO;
+
+ case SIOCSIFHWADDR:
+ dev_err(&lp->ndev->dev, "SIOCSIFHWADDR\n");
+
+ /* Copy MAC address in from user space */
+ copy_from_user((void __force *) dev->dev_addr,
+ (void __user __force *) hw_addr,
+ IFHWADDRLEN);
+ xemaclite_set_mac_address(lp, dev->dev_addr);
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
+/**
+ * xemaclite_remove_ndev - Free the network device
+ * @ndev: Pointer to the network device to be freed
+ *
+ * This function un maps the IO region of the Emaclite device and frees the net
+ * device.
+ */
+static void xemaclite_remove_ndev(struct net_device *ndev)
+{
+ if (ndev) {
+ struct net_local *lp = (struct net_local *) netdev_priv(ndev);
+
+ if (lp->base_addr)
+ iounmap((void __iomem __force *) (lp->base_addr));
+ free_netdev(ndev);
+ }
+}
+
+/**
+ * get_bool - Get a parameter from the OF device
+ * @ofdev: Pointer to OF device structure
+ * @s: Property to be retrieved
+ *
+ * This function looks for a property in the device node and returns the value
+ * of the property if its found or 0 if the property is not found.
+ *
+ * Return: Value of the parameter if the parameter is found, or 0 otherwise
+ */
+static bool get_bool(struct of_device *ofdev, const char *s)
+{
+ u32 *p = (u32 *)of_get_property(ofdev->node, s, NULL);
+
+ if (p) {
+ return (bool)*p;
+ } else {
+ dev_warn(&ofdev->dev, "Parameter %s not found,"
+ "defaulting to false\n", s);
+ return 0;
+ }
+}
+
+static struct net_device_ops xemaclite_netdev_ops;
+
+/**
+ * xemaclite_of_probe - Probe method for the Emaclite device.
+ * @ofdev: Pointer to OF device structure
+ * @match: Pointer to the structure used for matching a device
+ *
+ * This function probes for the Emaclite device in the device tree.
+ * It initializes the driver data structure and the hardware, sets the MAC
+ * address and registers the network device.
+ *
+ * Return: 0, if the driver is bound to the Emaclite device, or
+ * a negative error if there is failure.
+ */
+static int __devinit xemaclite_of_probe(struct of_device *ofdev,
+ const struct of_device_id *match)
+{
+ struct resource r_irq; /* Interrupt resources */
+ struct resource r_mem; /* IO mem resources */
+ struct net_device *ndev = NULL;
+ struct net_local *lp = NULL;
+ struct device *dev = &ofdev->dev;
+ const void *mac_address;
+
+ int rc = 0;
+
+ dev_info(dev, "Device Tree Probing\n");
+
+ /* Get iospace for the device */
+ rc = of_address_to_resource(ofdev->node, 0, &r_mem);
+ if (rc) {
+ dev_err(dev, "invalid address\n");
+ return rc;
+ }
+
+ /* Get IRQ for the device */
+ rc = of_irq_to_resource(ofdev->node, 0, &r_irq);
+ if (rc == NO_IRQ) {
+ dev_err(dev, "no IRQ found\n");
+ return rc;
+ }
+
+ /* Create an ethernet device instance */
+ ndev = alloc_etherdev(sizeof(struct net_local));
+ if (!ndev) {
+ dev_err(dev, "Could not allocate network device\n");
+ return -ENOMEM;
+ }
+
+ dev_set_drvdata(dev, ndev);
+
+ ndev->irq = r_irq.start;
+ ndev->mem_start = r_mem.start;
+ ndev->mem_end = r_mem.end;
+
+ lp = netdev_priv(ndev);
+ lp->ndev = ndev;
+
+ if (!request_mem_region(ndev->mem_start,
+ ndev->mem_end - ndev->mem_start + 1,
+ DRIVER_NAME)) {
+ dev_err(dev, "Couldn't lock memory region at %p\n",
+ (void *)ndev->mem_start);
+ rc = -EBUSY;
+ goto error2;
+ }
+
+ /* Get the virtual base address for the device */
+ lp->base_addr = ioremap(r_mem.start, r_mem.end - r_mem.start + 1);
+ if (NULL == lp->base_addr) {
+ dev_err(dev, "EmacLite: Could not allocate iomem\n");
+ rc = -EIO;
+ goto error1;
+ }
+
+ lp->next_tx_buf_to_use = 0x0;
+ lp->next_rx_buf_to_use = 0x0;
+ lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong");
+ lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong");
+ mac_address = of_get_mac_address(ofdev->node);
+
+ if (mac_address)
+ /* Set the MAC address. */
+ memcpy(ndev->dev_addr, mac_address, 6);
+ else
+ dev_warn(dev, "No MAC address found\n");
+
+ /* Clear the Tx CSR's in case this is a restart */
+ out_be32(lp->base_addr + XEL_TSR_OFFSET, 0);
+ out_be32(lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET, 0);
+
+ /* Set the MAC address in the EmacLite device */
+ xemaclite_set_mac_address(lp, ndev->dev_addr);
+
+ dev_info(dev,
+ "MAC address is now %2x:%2x:%2x:%2x:%2x:%2x\n",
+ ndev->dev_addr[0], ndev->dev_addr[1],
+ ndev->dev_addr[2], ndev->dev_addr[3],
+ ndev->dev_addr[4], ndev->dev_addr[5]);
+
+ ndev->netdev_ops = &xemaclite_netdev_ops;
+ ndev->flags &= ~IFF_MULTICAST;
+ ndev->watchdog_timeo = TX_TIMEOUT;
+
+ /* Finally, register the device */
+ rc = register_netdev(ndev);
+ if (rc) {
+ dev_err(dev,
+ "Cannot register network device, aborting\n");
+ goto error1;
+ }
+
+ dev_info(dev,
+ "Xilinx EmacLite at 0x%08X mapped to 0x%08X, irq=%d\n",
+ (unsigned int __force)ndev->mem_start,
+ (unsigned int __force)lp->base_addr, ndev->irq);
+ return 0;
+
+error1:
+ release_mem_region(ndev->mem_start, r_mem.end - r_mem.start + 1);
+
+error2:
+ xemaclite_remove_ndev(ndev);
+ return rc;
+}
+
+/**
+ * xemaclite_of_remove - Unbind the driver from the Emaclite device.
+ * @of_dev: Pointer to OF device structure
+ *
+ * This function is called if a device is physically removed from the system or
+ * if the driver module is being unloaded. It frees any resources allocated to
+ * the device.
+ *
+ * Return: 0, always.
+ */
+static int __devexit xemaclite_of_remove(struct of_device *of_dev)
+{
+ struct device *dev = &of_dev->dev;
+ struct net_device *ndev = dev_get_drvdata(dev);
+
+ unregister_netdev(ndev);
+
+ release_mem_region(ndev->mem_start, ndev->mem_end-ndev->mem_start + 1);
+
+ xemaclite_remove_ndev(ndev);
+
+ dev_set_drvdata(dev, NULL);
+
+ return 0;
+}
+
+static struct net_device_ops xemaclite_netdev_ops = {
+ .ndo_open = xemaclite_open,
+ .ndo_stop = xemaclite_close,
+ .ndo_start_xmit = xemaclite_send,
+ .ndo_do_ioctl = xemaclite_ioctl,
+ .ndo_tx_timeout = xemaclite_tx_timeout,
+ .ndo_get_stats = xemaclite_get_stats,
+};
+
+/* Match table for OF platform binding */
+static struct of_device_id xemaclite_of_match[] __devinitdata = {
+ { .compatible = "xlnx,opb-ethernetlite-1.01.a", },
+ { .compatible = "xlnx,opb-ethernetlite-1.01.b", },
+ { .compatible = "xlnx,xps-ethernetlite-1.00.a", },
+ { .compatible = "xlnx,xps-ethernetlite-2.00.a", },
+ { .compatible = "xlnx,xps-ethernetlite-2.01.a", },
+ { /* end of list */ },
+};
+MODULE_DEVICE_TABLE(of, xemaclite_of_match);
+
+static struct of_platform_driver xemaclite_of_driver = {
+ .name = DRIVER_NAME,
+ .match_table = xemaclite_of_match,
+ .probe = xemaclite_of_probe,
+ .remove = __devexit_p(xemaclite_of_remove),
+};
+
+/**
+ * xgpiopss_init - Initial driver registration call
+ *
+ * Return: 0 upon success, or a negative error upon failure.
+ */
+static int __init xemaclite_init(void)
+{
+ /* No kernel boot options used, we just need to register the driver */
+ return of_register_platform_driver(&xemaclite_of_driver);
+}
+
+/**
+ * xemaclite_cleanup - Driver un-registration call
+ */
+static void __exit xemaclite_cleanup(void)
+{
+ of_unregister_platform_driver(&xemaclite_of_driver);
+}
+
+module_init(xemaclite_init);
+module_exit(xemaclite_cleanup);
+
+MODULE_AUTHOR("Xilinx, Inc.");
+MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver");
+MODULE_LICENSE("GPL");
--
1.6.2.1
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^ permalink raw reply related
* Re: [PATCH] mpc8xxx_spi: Fix polarity inversion in chipselect
From: Michael Barkowski @ 2009-08-18 15:16 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <4A8AC3E8.5070301@ruggedcom.com>
Michael Barkowski wrote:
> If we use open firmware, then alow_flags handles active-low
> chipselects, which is the same as SPI_CS_HIGH. This patch fixes the
> double negative.
Hang on - I missed your most recent patches to spi_mpc8xxx
--Michael
^ permalink raw reply
* [PATCH] mpc8xxx_spi: Fix polarity inversion in chipselect
From: Michael Barkowski @ 2009-08-18 15:08 UTC (permalink / raw)
To: linuxppc-dev
If we use open firmware, then alow_flags handles active-low
chipselects, which is the same as SPI_CS_HIGH. This patch fixes the
double negative.
Signed-off-by: Michael Barkowski <michaelbarkowski@ruggedcom.com>
---
Anton,
thanks to your device table matching support patch I can use open firmware
to configure two spi devices on 8360E. I use the gpios node, with flags set
to 1, matching OF_GPIO_ACTIVE_LOW. When I do this I notice that the polarity
was already handled in a different way. Did some searching and didn't find
it had been discussed. Here's what I am doing now - feel free to use it or
abuse it :) (based in galak-powerpc/next plus your patches 1 and 2)
drivers/spi/spi_mpc8xxx.c | 10 ++--------
1 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi_mpc8xxx.c b/drivers/spi/spi_mpc8xxx.c
index 0fd0ec4..36bda94 100644
--- a/drivers/spi/spi_mpc8xxx.c
+++ b/drivers/spi/spi_mpc8xxx.c
@@ -159,14 +159,8 @@ static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
{
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
- bool pol = spi->mode & SPI_CS_HIGH;
struct spi_mpc8xxx_cs *cs = spi->controller_state;
- if (value == BITBANG_CS_INACTIVE) {
- if (pdata->cs_control)
- pdata->cs_control(spi, !pol);
- }
-
if (value == BITBANG_CS_ACTIVE) {
u32 regval = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
@@ -189,9 +183,9 @@ static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
mpc8xxx_spi_write_reg(mode, regval);
local_irq_restore(flags);
}
- if (pdata->cs_control)
- pdata->cs_control(spi, pol);
}
+ if (pdata->cs_control)
+ pdata->cs_control(spi, value);
}
static
--
1.6.3.3
^ permalink raw reply related
* Re: powerpc/405ex: Support cuImage for PPC405EX
From: Josh Boyer @ 2009-08-18 13:28 UTC (permalink / raw)
To: Tiejun Chen; +Cc: linuxppc-dev
In-Reply-To: <1250562484-16415-1-git-send-email-tiejun.chen@windriver.com>
On Tue, Aug 18, 2009 at 10:28:02AM +0800, Tiejun Chen wrote:
>Summary: powerpc/405ex: Support cuImage for PPC405EX
>Reviewers: Benjmain and linux-ppc
>----------------------------------------------------
>These patch series are used to support cuImage on the kilauea board based on PPC405ex.
>
>Tested on the amcc kilauea board:
Hm. The U-Boot version that ships on the AMCC Kilauea board is FDT aware, so
cuImage shouldn't be needed at all. I'm slightly confused why we need this.
Are you using it for some other board derived from 405EX that doesn't have
an FDT aware U-Boot?
josh
^ permalink raw reply
* [RFC/PATCH] Clock binding prototype implementation
From: Benjamin Herrenschmidt @ 2009-08-18 7:45 UTC (permalink / raw)
To: devicetree-discuss; +Cc: linuxppc-dev list
In-Reply-To: <1250569288.19007.15.camel@pasglop>
powerpc: New implementation of the "clk" API with device-tree binding
This replaces the struct clk_interface, as far as I know only ever
used by the mpc512x platforms, with a new scheme:
struct clk is now an object containing function pointers for all the
base API routines. The implementation of those routines call into
those pointers. struct clk is meant to be embedded in the "real"
structure for a given clock type.
clk_get is hooked via ppc_md. A default implementation is provided
that uses the device-tree binding (still being discussed, a patch
to Documentation/* will come when it's final). It can also create
simple objects (no control, working get_rate()) based on nodes that
have a "clock-frequency" property.
Finally, the mpc512x code is adapted. The adaptation is minimal as
I don't have test gear, so I'm not using nor touching the device-tree
on this one, but instead hooking ppc_md.get_clk() and keeping the
old code mostly intact (just some type changes to embed the new
struct clk into the mpc512x specific variants which gets renamed
to struct mpc512x_clk).
No S-O-B yet as this is totally untested and the binding isn't
final yet neither, but gives an idea of where I'm going.
Ben.
Index: linux-work/arch/powerpc/include/asm/clk_interface.h
===================================================================
--- linux-work.orig/arch/powerpc/include/asm/clk_interface.h 2009-02-05 16:22:24.000000000 +1100
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,20 +0,0 @@
-#ifndef __ASM_POWERPC_CLK_INTERFACE_H
-#define __ASM_POWERPC_CLK_INTERFACE_H
-
-#include <linux/clk.h>
-
-struct clk_interface {
- struct clk* (*clk_get) (struct device *dev, const char *id);
- int (*clk_enable) (struct clk *clk);
- void (*clk_disable) (struct clk *clk);
- unsigned long (*clk_get_rate) (struct clk *clk);
- void (*clk_put) (struct clk *clk);
- long (*clk_round_rate) (struct clk *clk, unsigned long rate);
- int (*clk_set_rate) (struct clk *clk, unsigned long rate);
- int (*clk_set_parent) (struct clk *clk, struct clk *parent);
- struct clk* (*clk_get_parent) (struct clk *clk);
-};
-
-extern struct clk_interface clk_functions;
-
-#endif /* __ASM_POWERPC_CLK_INTERFACE_H */
Index: linux-work/arch/powerpc/kernel/clock.c
===================================================================
--- linux-work.orig/arch/powerpc/kernel/clock.c 2009-02-05 16:22:24.000000000 +1100
+++ linux-work/arch/powerpc/kernel/clock.c 2009-08-18 17:38:08.000000000 +1000
@@ -1,82 +1,282 @@
/*
- * Dummy clk implementations for powerpc.
- * These need to be overridden in platform code.
+ * Clock infrastructure for PowerPC platform
+ *
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/module.h>
-#include <asm/clk_interface.h>
+#include <linux/of.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+#include <asm/clk.h>
+#include <asm/machdep.h>
+
+struct clk_provider {
+ struct list_head link;
+ struct device_node *node;
+
+ /* Return NULL if no such clock output, return PTR_ERR for
+ * other errors
+ */
+ struct clk * (*get)(struct device_node *np,
+ const char *output_id,
+ void *data);
+ void *data;
+};
+
+static LIST_HEAD(clk_providers);
+static DEFINE_MUTEX(clk_lock);
+
+int clk_add_provider(struct device_node *np,
+ struct clk *(*clk_src_get)(struct device_node *np,
+ const char *output_id,
+ void *data),
+ void *data)
+{
+ struct clk_provider *cp;
-struct clk_interface clk_functions;
+ cp = kzalloc(sizeof(struct clk_provider), GFP_KERNEL);
+ if (!cp)
+ return -ENOMEM;
+
+ cp->node = of_node_get(np);
+ cp->data = data;
+ cp->get = clk_src_get;
+
+ mutex_lock(&clk_lock);
+ list_add(&cp->link, &clk_providers);
+ mutex_unlock(&clk_lock);
-struct clk *clk_get(struct device *dev, const char *id)
+ return 0;
+}
+
+void clk_del_provider(struct device_node *np,
+ struct clk *(*clk_src_get)(struct device_node *np,
+ const char *output_id,
+ void *data),
+ void *data)
{
- if (clk_functions.clk_get)
- return clk_functions.clk_get(dev, id);
- return ERR_PTR(-ENOSYS);
+ struct clk_provider *cp, *tmp;
+
+ mutex_lock(&clk_lock);
+ list_for_each_entry_safe(cp, tmp, &clk_providers, link) {
+ if (cp->node == np && cp->get == clk_src_get && cp->data == data) {
+ list_del(&cp->link);
+ of_node_put(cp->node);
+ kfree(cp);
+ break;
+ }
+ }
+ mutex_unlock(&clk_lock);
}
-EXPORT_SYMBOL(clk_get);
-void clk_put(struct clk *clk)
+static unsigned long clk_simple_get_rate(struct clk *clk)
{
- if (clk_functions.clk_put)
- clk_functions.clk_put(clk);
+ struct clk_simple *cs = to_clk_simple(clk);
+
+ return cs->rate;
}
-EXPORT_SYMBOL(clk_put);
+
+static void clk_simple_put(struct clk *clk)
+{
+ struct clk_simple *cs = to_clk_simple(clk);
+
+ kfree(cs);
+}
+
+static struct clk *__clk_get_simple(struct device_node *np)
+{
+ const u32 *freq;
+ struct clk_simple *cs;
+
+ freq = of_get_property(np, "clock-frequency", NULL);
+ if (!freq)
+ return ERR_PTR(-ENXIO);
+
+ cs = kzalloc(sizeof(struct clk_simple), GFP_KERNEL);
+ if (!cs)
+ return ERR_PTR(-ENOMEM);
+
+ cs->rate = *freq;
+ cs->clk.get_rate = clk_simple_get_rate;
+ cs->clk.put = clk_simple_put;
+
+ return &cs->clk;
+}
+
+static struct clk *__clk_get_from_provider(struct device_node *np, u32 index)
+{
+ struct clk_provider *provider;
+ const char *names, *id = NULL;
+ int sz, l, i;
+ struct clk *clk = NULL;
+
+ /* Look for "clock-output-names" in the provider's node, if it's missing
+ * we don't bother looking for a clock provider, though we do fallback
+ * to the "simple" clock case
+ */
+ names = of_get_property(np, "clock-output-names", &sz);
+ if (!names)
+ return __clk_get_simple(np);
+
+ /* Lookup index */
+ for (i = 0; sz > 0; i++) {
+ if (index == i) {
+ id = names;
+ break;
+ }
+ l = strlen(names) + 1;
+ sz -= l;
+ names += l;
+ }
+ if (id == NULL)
+ return ERR_PTR(-ENXIO);
+
+ /* Check if we have such a provider in our array */
+ mutex_lock(&clk_lock);
+ list_for_each_entry(provider, &clk_providers, link) {
+ if (provider->node == np)
+ clk = provider->get(np, id, provider->data);
+ if (clk)
+ break;
+ }
+ mutex_unlock(&clk_lock);
+
+ /* Clock not found, return an error */
+ if (clk == NULL)
+ clk = ERR_PTR(-EINVAL);
+
+ return clk;
+}
+
+struct clk *of_clk_get(struct device_node *np, const char *id)
+{
+ int sz, l, index = 0;
+ struct device_node *provnode;
+ const u32 *map;
+ u32 provhandle, provindex;
+ struct clk *clk;
+
+ /* look for an id match in clock-names property */
+ if (id) {
+ const char *names = of_get_property(np, "clock-input-names", &sz);
+
+ /* no such property, fail for now. Maybe in the long run we might
+ * consider allowing "generic" names such as "bus" for the bus
+ * clock, effectively routing to the parent node...
+ */
+ if (!names)
+ return ERR_PTR(-ENXIO);
+ while (sz > 0) {
+ if (strcasecmp(id, names) == 0)
+ break;
+ l = strlen(names) + 1;
+ sz -= l;
+ names += l;
+ index++;
+ }
+ if (sz < 1)
+ return ERR_PTR(-ENOENT);
+ }
+
+ /* now we have an index, lookup in clock-map */
+ map = of_get_property(np, "clock-map", &sz);
+ if (!map)
+ return ERR_PTR(-ENXIO);
+ sz /= sizeof(u32) * 2;
+ if (index >= sz)
+ return ERR_PTR(-EINVAL);
+ provhandle = map[index * 2];
+ provindex = map[index * 2] + 1;
+
+ provnode = of_find_node_by_phandle(provhandle);
+ if (!provnode)
+ return ERR_PTR(-EINVAL);
+
+ clk = __clk_get_from_provider(provnode, provindex);
+ of_node_put(provnode);
+
+ return clk;
+}
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+ if (ppc_md.clk_get)
+ return ppc_md.clk_get(dev, id);
+
+ if (dev->archdata.of_node)
+ return of_clk_get(dev->archdata.of_node, id);
+
+ return ERR_PTR(-ENODEV);
+}
+EXPORT_SYMBOL(clk_get);
+
+/*
+ * clk_* API is just wrappers to the function pointers
+ * inside of struct clk
+ */
int clk_enable(struct clk *clk)
{
- if (clk_functions.clk_enable)
- return clk_functions.clk_enable(clk);
- return -ENOSYS;
+ if (clk->enable)
+ return clk->enable(clk);
+ return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
- if (clk_functions.clk_disable)
- clk_functions.clk_disable(clk);
+ if (clk->disable)
+ clk->disable(clk);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
- if (clk_functions.clk_get_rate)
- return clk_functions.clk_get_rate(clk);
+ if (clk->get_rate)
+ return clk->get_rate(clk);
return 0;
}
EXPORT_SYMBOL(clk_get_rate);
+void clk_put(struct clk *clk)
+{
+ if (clk->put)
+ clk->put(clk);
+}
+EXPORT_SYMBOL(clk_put);
+
long clk_round_rate(struct clk *clk, unsigned long rate)
{
- if (clk_functions.clk_round_rate)
- return clk_functions.clk_round_rate(clk, rate);
+ if (clk->round_rate)
+ return clk->round_rate(clk, rate);
return -ENOSYS;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
- if (clk_functions.clk_set_rate)
- return clk_functions.clk_set_rate(clk, rate);
+ if (clk->set_rate)
+ return clk->set_rate(clk, rate);
return -ENOSYS;
}
EXPORT_SYMBOL(clk_set_rate);
-struct clk *clk_get_parent(struct clk *clk)
-{
- if (clk_functions.clk_get_parent)
- return clk_functions.clk_get_parent(clk);
- return ERR_PTR(-ENOSYS);
-}
-EXPORT_SYMBOL(clk_get_parent);
-
int clk_set_parent(struct clk *clk, struct clk *parent)
{
- if (clk_functions.clk_set_parent)
- return clk_functions.clk_set_parent(clk, parent);
+ if (clk->set_parent)
+ return clk->set_parent(clk, parent);
return -ENOSYS;
}
EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+ if (clk->get_parent)
+ return clk->get_parent(clk);
+ return ERR_PTR(-ENOSYS);
+}
+EXPORT_SYMBOL(clk_get_parent);
Index: linux-work/arch/powerpc/include/asm/clk.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/include/asm/clk.h 2009-08-18 17:38:08.000000000 +1000
@@ -0,0 +1,61 @@
+/*
+ * Clock infrastructure for PowerPC platform
+ */
+#ifndef __ASM_POWERPC_CLK_H
+#define __ASM_POWERPC_CLK_H
+
+struct device_node;
+
+/* The definition of struct clk for arch/powerpc is global, it's
+ * expected that clock providers generate "subclasses" embedding
+ * struct clk
+ */
+struct clk {
+ int (*enable)(struct clk *);
+ void (*disable)(struct clk *);
+ unsigned long (*get_rate)(struct clk *);
+ void (*put)(struct clk *);
+ long (*round_rate)(struct clk *, unsigned long);
+ int (*set_rate)(struct clk *, unsigned long);
+ int (*set_parent)(struct clk *, struct clk *);
+ struct clk* (*get_parent)(struct clk *);
+};
+
+/* The simple clock is exposed here for implementations that want
+ * to re-use it in case they don't need anything else
+ */
+struct clk_simple {
+ struct clk clk;
+ unsigned long rate;
+};
+#define to_clk_simple(n) container_of(n, struct clk_simple, clk)
+
+
+/**
+ * clk_add_provier - Attach a clock provider to a clock source device node
+ * @node: device node of the clock source
+ * @clk_src_get: function pointer called to obtain a struct clk
+ * @data: arbitrary data passed back to clk_src_get() when called
+ *
+ * This will attach the clk_src_get() function to a given device_node,
+ * that function will then be called whenever a drivers does a clk_get()
+ * and that driver's clock-map references that clock source node.
+ */
+extern int clk_add_provider(struct device_node *np,
+ struct clk *(*clk_src_get)(struct device_node *np,
+ const char *output_id,
+ void *data),
+ void *data);
+/**
+ * clk_del_provier - Remove a clock provider from a clock source device node
+ * @node: device node of the clock source
+ * @clk_src_get: function pointer used in clk_add_provider()
+ * @data: data used in clk_add_provider()
+ */
+extern void clk_del_provider(struct device_node *np,
+ struct clk *(*clk_src_get)(struct device_node *np,
+ const char *output_id,
+ void *data),
+ void *data);
+
+#endif /* __ASM_POWERPC_CLK_H */
Index: linux-work/arch/powerpc/include/asm/machdep.h
===================================================================
--- linux-work.orig/arch/powerpc/include/asm/machdep.h 2009-08-18 17:36:53.000000000 +1000
+++ linux-work/arch/powerpc/include/asm/machdep.h 2009-08-18 17:38:08.000000000 +1000
@@ -27,6 +27,8 @@ struct iommu_table;
struct rtc_time;
struct file;
struct pci_controller;
+struct clk;
+struct device;
#ifdef CONFIG_KEXEC
struct kimage;
#endif
@@ -266,7 +268,11 @@ struct machdep_calls {
*/
void (*suspend_disable_irqs)(void);
void (*suspend_enable_irqs)(void);
-#endif
+#endif /* CONFIG_SUSPEND */
+
+#ifdef CONFIG_PPC_CLOCK
+ struct clk *(*clk_get)(struct device *dev, const char *id);
+#endif /* CONFIG_PPC_CLOCK */
};
extern void e500_idle(void);
Index: linux-work/arch/powerpc/platforms/512x/clock.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/512x/clock.c 2009-08-18 17:33:15.000000000 +1000
+++ linux-work/arch/powerpc/platforms/512x/clock.c 2009-08-18 17:38:30.000000000 +1000
@@ -25,7 +25,7 @@
#include <linux/of_platform.h>
#include <asm/mpc5xxx.h>
-#include <asm/clk_interface.h>
+#include <asm/clk.h>
#undef CLK_DEBUG
@@ -34,25 +34,28 @@ static int clocks_initialized;
#define CLK_HAS_RATE 0x1 /* has rate in MHz */
#define CLK_HAS_CTRL 0x2 /* has control reg and bit */
-struct clk {
+struct mpc512x_clk {
+ struct clk clk;
struct list_head node;
char name[32];
int flags;
struct device *dev;
unsigned long rate;
struct module *owner;
- void (*calc) (struct clk *);
- struct clk *parent;
+ void (*calc) (struct mpc512x_clk *);
+ struct mpc512x_clk *parent;
int reg, bit; /* CLK_HAS_CTRL */
int div_shift; /* only used by generic_div_clk_calc */
};
+#define to_mpc512x_clk(n) container_of(n, struct mpc512x_clk, clk)
static LIST_HEAD(clocks);
static DEFINE_MUTEX(clocks_mutex);
static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
{
- struct clk *p, *clk = ERR_PTR(-ENOENT);
+ struct clk *clk = ERR_PTR(-ENOENT);
+ struct mpc512x_clk *p;
int dev_match = 0;
int id_match = 0;
@@ -66,7 +69,7 @@ static struct clk *mpc5121_clk_get(struc
if (strcmp(id, p->name) == 0)
id_match++;
if ((dev_match || id_match) && try_module_get(p->owner)) {
- clk = p;
+ clk = &p->clk;
break;
}
}
@@ -78,7 +81,7 @@ static struct clk *mpc5121_clk_get(struc
#ifdef CLK_DEBUG
static void dump_clocks(void)
{
- struct clk *p;
+ struct mpc512x_clk *p;
mutex_lock(&clocks_mutex);
printk(KERN_INFO "CLOCKS:\n");
@@ -101,7 +104,9 @@ static void dump_clocks(void)
static void mpc5121_clk_put(struct clk *clk)
{
- module_put(clk->owner);
+ struct mpc512x_clk *mpclk = to_mpc512x_clk(clk);
+
+ module_put(mpclk->owner);
}
#define NRPSC 12
@@ -123,31 +128,35 @@ struct mpc512x_clockctl __iomem *clockct
static int mpc5121_clk_enable(struct clk *clk)
{
+ struct mpc512x_clk *mpclk = to_mpc512x_clk(clk);
unsigned int mask;
- if (clk->flags & CLK_HAS_CTRL) {
- mask = in_be32(&clockctl->sccr[clk->reg]);
- mask |= 1 << clk->bit;
- out_be32(&clockctl->sccr[clk->reg], mask);
+ if (mpclk->flags & CLK_HAS_CTRL) {
+ mask = in_be32(&clockctl->sccr[mpclk->reg]);
+ mask |= 1 << mpclk->bit;
+ out_be32(&clockctl->sccr[mpclk->reg], mask);
}
return 0;
}
static void mpc5121_clk_disable(struct clk *clk)
{
+ struct mpc512x_clk *mpclk = to_mpc512x_clk(clk);
unsigned int mask;
- if (clk->flags & CLK_HAS_CTRL) {
- mask = in_be32(&clockctl->sccr[clk->reg]);
- mask &= ~(1 << clk->bit);
- out_be32(&clockctl->sccr[clk->reg], mask);
+ if (mpclk->flags & CLK_HAS_CTRL) {
+ mask = in_be32(&clockctl->sccr[mpclk->reg]);
+ mask &= ~(1 << mpclk->bit);
+ out_be32(&clockctl->sccr[mpclk->reg], mask);
}
}
static unsigned long mpc5121_clk_get_rate(struct clk *clk)
{
- if (clk->flags & CLK_HAS_RATE)
- return clk->rate;
+ struct mpc512x_clk *mpclk = to_mpc512x_clk(clk);
+
+ if (mpclk->flags & CLK_HAS_RATE)
+ return mpclk->rate;
else
return 0;
}
@@ -162,11 +171,21 @@ static int mpc5121_clk_set_rate(struct c
return 0;
}
-static int clk_register(struct clk *clk)
+static int clk_register(struct mpc512x_clk *mpclk)
{
+ mpclk.clk.enable = mpc5121_clk_enable;
+ mpclk.clk.disable = mpc5121_clk_disable;
+ mpclk.clk.get_rate = mpc5121_clk_get_rate;
+ mpclk.clk.put = mpc5121_clk_put;
+ mpclk.clk.round_rate = mpc5121_clk_round_rate;
+ mpclk.clk.set_rate = mpc5121_clk_set_rate;
+ mpclk.clk.set_paqrent = NULL;
+ mpclk.clk.get_parent = NULL;
+
mutex_lock(&clocks_mutex);
- list_add(&clk->node, &clocks);
+ list_add(&mpclk->node, &clocks);
mutex_unlock(&clocks_mutex);
+
return 0;
}
@@ -250,7 +269,7 @@ static unsigned long devtree_getfreq(cha
return val;
}
-static void ref_clk_calc(struct clk *clk)
+static void ref_clk_calc(struct mpc512x_clk *mpclk)
{
unsigned long rate;
@@ -260,26 +279,26 @@ static void ref_clk_calc(struct clk *clk
clk->rate = 0;
return;
}
- clk->rate = ips_to_ref(rate);
+ mpclk->rate = ips_to_ref(rate);
}
-static struct clk ref_clk = {
+static struct mpc512x_clk ref_clk = {
.name = "ref_clk",
.calc = ref_clk_calc,
};
-static void sys_clk_calc(struct clk *clk)
+static void sys_clk_calc(struct mpc512x_clk *clk)
{
clk->rate = ref_to_sys(ref_clk.rate);
}
-static struct clk sys_clk = {
+static struct mpc512x_clk sys_clk = {
.name = "sys_clk",
.calc = sys_clk_calc,
};
-static void diu_clk_calc(struct clk *clk)
+static void diu_clk_calc(struct mpc512x_clk *clk)
{
int diudiv_x_2 = clockctl->scfr1 & 0xff;
unsigned long rate;
@@ -292,30 +311,30 @@ static void diu_clk_calc(struct clk *clk
clk->rate = rate;
}
-static void half_clk_calc(struct clk *clk)
+static void half_clk_calc(struct mpc512x_clk *clk)
{
clk->rate = clk->parent->rate / 2;
}
-static void generic_div_clk_calc(struct clk *clk)
+static void generic_div_clk_calc(struct mpc512x_clk *clk)
{
int div = (clockctl->scfr1 >> clk->div_shift) & 0x7;
clk->rate = clk->parent->rate / div;
}
-static void unity_clk_calc(struct clk *clk)
+static void unity_clk_calc(struct mpc512x_clk *clk)
{
clk->rate = clk->parent->rate;
}
-static struct clk csb_clk = {
+static struct mpc512x_clk csb_clk = {
.name = "csb_clk",
.calc = half_clk_calc,
.parent = &sys_clk,
};
-static void e300_clk_calc(struct clk *clk)
+static void e300_clk_calc(struct mpc512x_clk *clk)
{
int spmf = (clockctl->spmr >> 16) & 0xf;
int ratex2 = clk->parent->rate * spmf;
@@ -323,13 +342,13 @@ static void e300_clk_calc(struct clk *cl
clk->rate = ratex2 / 2;
}
-static struct clk e300_clk = {
+static struct mpc512x_clk e300_clk = {
.name = "e300_clk",
.calc = e300_clk_calc,
.parent = &csb_clk,
};
-static struct clk ips_clk = {
+static struct mpc512x_clk ips_clk = {
.name = "ips_clk",
.calc = generic_div_clk_calc,
.parent = &csb_clk,
@@ -339,7 +358,7 @@ static struct clk ips_clk = {
/*
* Clocks controlled by SCCR1 (.reg = 0)
*/
-static struct clk lpc_clk = {
+static struct mpc512x_clk lpc_clk = {
.name = "lpc_clk",
.flags = CLK_HAS_CTRL,
.reg = 0,
@@ -349,7 +368,7 @@ static struct clk lpc_clk = {
.div_shift = 11,
};
-static struct clk nfc_clk = {
+static struct mpc512x_clk nfc_clk = {
.name = "nfc_clk",
.flags = CLK_HAS_CTRL,
.reg = 0,
@@ -359,7 +378,7 @@ static struct clk nfc_clk = {
.div_shift = 8,
};
-static struct clk pata_clk = {
+static struct mpc512x_clk pata_clk = {
.name = "pata_clk",
.flags = CLK_HAS_CTRL,
.reg = 0,
@@ -373,7 +392,7 @@ static struct clk pata_clk = {
* are setup elsewhere
*/
-static struct clk sata_clk = {
+static struct mpc512x_clk sata_clk = {
.name = "sata_clk",
.flags = CLK_HAS_CTRL,
.reg = 0,
@@ -382,7 +401,7 @@ static struct clk sata_clk = {
.parent = &ips_clk,
};
-static struct clk fec_clk = {
+static struct mpc512x_clk fec_clk = {
.name = "fec_clk",
.flags = CLK_HAS_CTRL,
.reg = 0,
@@ -391,7 +410,7 @@ static struct clk fec_clk = {
.parent = &ips_clk,
};
-static struct clk pci_clk = {
+static struct mpc512x_clk pci_clk = {
.name = "pci_clk",
.flags = CLK_HAS_CTRL,
.reg = 0,
@@ -404,7 +423,7 @@ static struct clk pci_clk = {
/*
* Clocks controlled by SCCR2 (.reg = 1)
*/
-static struct clk diu_clk = {
+static struct mpc512x_clk diu_clk = {
.name = "diu_clk",
.flags = CLK_HAS_CTRL,
.reg = 1,
@@ -412,7 +431,7 @@ static struct clk diu_clk = {
.calc = diu_clk_calc,
};
-static struct clk axe_clk = {
+static struct mpc512x_clk axe_clk = {
.name = "axe_clk",
.flags = CLK_HAS_CTRL,
.reg = 1,
@@ -421,7 +440,7 @@ static struct clk axe_clk = {
.parent = &csb_clk,
};
-static struct clk usb1_clk = {
+static struct mpc512x_clk usb1_clk = {
.name = "usb1_clk",
.flags = CLK_HAS_CTRL,
.reg = 1,
@@ -430,7 +449,7 @@ static struct clk usb1_clk = {
.parent = &csb_clk,
};
-static struct clk usb2_clk = {
+static struct mpc512x_clk usb2_clk = {
.name = "usb2_clk",
.flags = CLK_HAS_CTRL,
.reg = 1,
@@ -439,7 +458,7 @@ static struct clk usb2_clk = {
.parent = &csb_clk,
};
-static struct clk i2c_clk = {
+static struct mpc512x_clk i2c_clk = {
.name = "i2c_clk",
.flags = CLK_HAS_CTRL,
.reg = 1,
@@ -448,7 +467,7 @@ static struct clk i2c_clk = {
.parent = &ips_clk,
};
-static struct clk mscan_clk = {
+static struct mpc512x_clk mscan_clk = {
.name = "mscan_clk",
.flags = CLK_HAS_CTRL,
.reg = 1,
@@ -457,7 +476,7 @@ static struct clk mscan_clk = {
.parent = &ips_clk,
};
-static struct clk sdhc_clk = {
+static struct mpc512x_clk sdhc_clk = {
.name = "sdhc_clk",
.flags = CLK_HAS_CTRL,
.reg = 1,
@@ -466,7 +485,7 @@ static struct clk sdhc_clk = {
.parent = &ips_clk,
};
-static struct clk mbx_bus_clk = {
+static struct mpc512x_clk mbx_bus_clk = {
.name = "mbx_bus_clk",
.flags = CLK_HAS_CTRL,
.reg = 1,
@@ -475,7 +494,7 @@ static struct clk mbx_bus_clk = {
.parent = &csb_clk,
};
-static struct clk mbx_clk = {
+static struct mpc512x_clk mbx_clk = {
.name = "mbx_clk",
.flags = CLK_HAS_CTRL,
.reg = 1,
@@ -484,7 +503,7 @@ static struct clk mbx_clk = {
.parent = &csb_clk,
};
-static struct clk mbx_3d_clk = {
+static struct mpc512x_clk mbx_3d_clk = {
.name = "mbx_3d_clk",
.flags = CLK_HAS_CTRL,
.reg = 1,
@@ -494,44 +513,44 @@ static struct clk mbx_3d_clk = {
.div_shift = 14,
};
-static void psc_mclk_in_calc(struct clk *clk)
+static void psc_mclk_in_calc(struct mpc512x_clk *clk)
{
clk->rate = devtree_getfreq("psc_mclk_in");
if (!clk->rate)
clk->rate = 25000000;
}
-static struct clk psc_mclk_in = {
+static struct mpc512x_clk psc_mclk_in = {
.name = "psc_mclk_in",
.calc = psc_mclk_in_calc,
};
-static struct clk spdif_txclk = {
+static struct mpc512x_clk spdif_txclk = {
.name = "spdif_txclk",
.flags = CLK_HAS_CTRL,
.reg = 1,
.bit = 23,
};
-static struct clk spdif_rxclk = {
+static struct mpc512x_clk spdif_rxclk = {
.name = "spdif_rxclk",
.flags = CLK_HAS_CTRL,
.reg = 1,
.bit = 23,
};
-static void ac97_clk_calc(struct clk *clk)
+static void ac97_clk_calc(struct mpc512x_clk *clk)
{
/* ac97 bit clock is always 24.567 MHz */
clk->rate = 24567000;
}
-static struct clk ac97_clk = {
+static struct mpc512x_clk ac97_clk = {
.name = "ac97_clk_in",
.calc = ac97_clk_calc,
};
-struct clk *rate_clks[] = {
+struct mpc512x_clk *rate_clks[] = {
&ref_clk,
&sys_clk,
&diu_clk,
@@ -560,7 +579,7 @@ struct clk *rate_clks[] = {
NULL
};
-static void rate_clk_init(struct clk *clk)
+static void rate_clk_init(struct mpc512x_clk *clk)
{
if (clk->calc) {
clk->calc(clk);
@@ -575,7 +594,7 @@ static void rate_clk_init(struct clk *cl
static void rate_clks_init(void)
{
- struct clk **cpp, *clk;
+ struct mpc512x_clk **cpp, *clk;
cpp = rate_clks;
while ((clk = *cpp++))
@@ -586,16 +605,16 @@ static void rate_clks_init(void)
* There are two clk enable registers with 32 enable bits each
* psc clocks and device clocks are all stored in dev_clks
*/
-struct clk dev_clks[2][32];
+struct mpc512x_clk dev_clks[2][32];
/*
* Given a psc number return the dev_clk
* associated with it
*/
-static struct clk *psc_dev_clk(int pscnum)
+static struct mpc512x_clk *psc_dev_clk(int pscnum)
{
int reg, bit;
- struct clk *clk;
+ struct mpc512x_clk *clk;
reg = 0;
bit = 27 - pscnum;
@@ -609,7 +628,7 @@ static struct clk *psc_dev_clk(int pscnu
/*
* PSC clock rate calculation
*/
-static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
+static void psc_calc_rate(struct mpc512x_clk *clk, int pscnum, struct device_node *np)
{
unsigned long mclk_src = sys_clk.rate;
unsigned long mclk_div;
@@ -666,7 +685,7 @@ static void psc_clks_init(void)
cell_index = of_get_property(np, "cell-index", NULL);
if (cell_index) {
int pscnum = *cell_index;
- struct clk *clk = psc_dev_clk(pscnum);
+ struct mpc512x_clk *clk = psc_dev_clk(pscnum);
clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
ofdev = of_find_device_by_node(np);
@@ -686,18 +705,6 @@ static void psc_clks_init(void)
}
}
-static struct clk_interface mpc5121_clk_functions = {
- .clk_get = mpc5121_clk_get,
- .clk_enable = mpc5121_clk_enable,
- .clk_disable = mpc5121_clk_disable,
- .clk_get_rate = mpc5121_clk_get_rate,
- .clk_put = mpc5121_clk_put,
- .clk_round_rate = mpc5121_clk_round_rate,
- .clk_set_rate = mpc5121_clk_set_rate,
- .clk_set_parent = NULL,
- .clk_get_parent = NULL,
-};
-
static int
mpc5121_clk_init(void)
{
@@ -721,7 +728,7 @@ mpc5121_clk_init(void)
/*iounmap(clockctl); */
DEBUG_CLK_DUMP();
clocks_initialized++;
- clk_functions = mpc5121_clk_functions;
+ ppc_md.clk_get = mpc5121_clk_get;
return 0;
}
^ permalink raw reply
* Please pull my perfcounters.git tree
From: Paul Mackerras @ 2009-08-18 5:16 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
Ben,
The following changes since commit 64f1607ffbbc772685733ea63e6f7f4183df1b16:
Linus Torvalds (1):
Linux 2.6.31-rc6
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/paulus/perfcounters.git master
Please pull them into your powerpc-next branch. I'll also ask Ingo
Molnar to pull them into the tip tree.
Thanks,
Paul.
Paul Mackerras (3):
powerpc/32: Always order writes to halves of 64-bit PTEs
powerpc: Allow perf_counters to access user memory at interrupt time
perf_counter: powerpc: Add callchain support
arch/powerpc/include/asm/pgtable.h | 6 +-
arch/powerpc/kernel/Makefile | 2 +-
arch/powerpc/kernel/asm-offsets.c | 2 +
arch/powerpc/kernel/exceptions-64s.S | 19 ++
arch/powerpc/kernel/perf_callchain.c | 527 ++++++++++++++++++++++++++++++++++
arch/powerpc/mm/slb.c | 37 ++-
arch/powerpc/mm/stab.c | 11 +-
7 files changed, 588 insertions(+), 16 deletions(-)
create mode 100644 arch/powerpc/kernel/perf_callchain.c
^ permalink raw reply
* Re: simple gpio driver
From: Heiko Schocher @ 2009-08-18 5:25 UTC (permalink / raw)
To: avorontsov; +Cc: linuxppc-dev
In-Reply-To: <20090817233833.GA3685@oksana.dev.rtsoft.ru>
Hello Anton,
Anton Vorontsov wrote:
> Oops, I missed that patch, sorry.
>
> On Mon, Aug 17, 2009 at 03:18:37PM -0600, Grant Likely wrote:
>> On Wed, Aug 12, 2009 at 11:49 PM, Heiko Schocher<hs@denx.de> wrote:
>>> Hello Anton,
>>>
>>> i am trying to use the arch/powerpc/sysdev/simple_gpio.c driver,
>>> for accessing some gpios, and found, that u8_gpio_get()
>>> returns not only a 1 or a 0, instead it returns the real bit
>>> position from the gpio:
>>>
>>> gpio return
>>> base value
>>> 0 0/0x01
>>> 1 0/0x02
>>> 2 0/0x04
>>> 3 0/0x08
>>> 4 0/0x10
>>> 5 0/0x20
>>> 6 0/0x40
>>> 7 0/0x80
>>>
>>> I also use the arch/powerpc/platforms/52xx/mpc52xx_gpio.c and
>>> mpc52xx_gpt.c drivers, they all return for a gpio just a 1 or 0,
>
> There is also arch/powerpc/sysdev/qe_lib/gpio.c and
> arch/powerpc/sysdev/mpc8xxx_gpio.c that don't do that.
Ah, okay.
>>> which seems correct to me, because a gpio can have only 1 or 0
>>> as state ... what do you think?
>> I think returning '1' is perhaps slightly 'better' (however you define
>> that), but I don't think the caller should make any assumptions beyond
>> zero/non-zero.
>
> Yep. So I don't think that the patch is needed.
Yes, if the gpio lib only differs in zero versus non zero.
Thanks for the info
bye
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply
* Re: simple gpio driver
From: Heiko Schocher @ 2009-08-18 5:24 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev
In-Reply-To: <fa686aa40908171418k57ce5ff6iac44a72171bcf14a@mail.gmail.com>
Hello Grant,
Grant Likely wrote:
> On Wed, Aug 12, 2009 at 11:49 PM, Heiko Schocher<hs@denx.de> wrote:
>> Hello Anton,
>>
>> i am trying to use the arch/powerpc/sysdev/simple_gpio.c driver,
>> for accessing some gpios, and found, that u8_gpio_get()
>> returns not only a 1 or a 0, instead it returns the real bit
>> position from the gpio:
>>
>> gpio return
>> base value
>> 0 0/0x01
>> 1 0/0x02
>> 2 0/0x04
>> 3 0/0x08
>> 4 0/0x10
>> 5 0/0x20
>> 6 0/0x40
>> 7 0/0x80
>>
>> I also use the arch/powerpc/platforms/52xx/mpc52xx_gpio.c and
>> mpc52xx_gpt.c drivers, they all return for a gpio just a 1 or 0,
>> which seems correct to me, because a gpio can have only 1 or 0
>> as state ... what do you think?
>
> I think returning '1' is perhaps slightly 'better' (however you define
Yep.
> that), but I don't think the caller should make any assumptions beyond
> zero/non-zero.
Hmm... why? I think a gpio_pin can have as value only 0 or 1.
Ah, if you say zero versus non zero ... hmm... okay.
>> I solved this issue (if it is) with the following patch:
>>
>> diff --git a/arch/powerpc/sysdev/simple_gpio.c b/arch/powerpc/sysdev/simple_gpio.c
>> index 43c4569..bb0d79c 100644
>> --- a/arch/powerpc/sysdev/simple_gpio.c
>> +++ b/arch/powerpc/sysdev/simple_gpio.c
>> @@ -46,7 +46,7 @@ static int u8_gpio_get(struct gpio_chip *gc, unsigned int gpio)
>> {
>> struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
>>
>> - return in_8(mm_gc->regs) & u8_pin2mask(gpio);
>> + return (in_8(mm_gc->regs) & u8_pin2mask(gpio) ? 1 : 0);
>
> For clarity, the brackets should be just around the & operands, and
> "!= 0" instead of "? 1 : 0" might result in slightly smaller code.
>
> return (in_8(mm_gc->regs) & u8_pin2mask(gpio)) != 0;
Yep, you are right, thanks for the info.
bye
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply
* Re: Mailing lists (Was: Re: powerpc/405ex: Support cuImage for PPC405EX)
From: tiejun.chen @ 2009-08-18 4:38 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev
In-Reply-To: <20090818133005.0b021424.sfr@canb.auug.org.au>
Stephen Rothwell wrote:
> Please do *not* send mail to both linuxppc-dev@ozlabs.org and
> linuxppc-dev@lists.ozlabs.org. We all end up with two copies :-(
>
> They are the same list.
Sorry for this inconvenient I bring :(
Best Regards
Tiejun
^ permalink raw reply
* Re: [PATCH 1/3 v3] powerpc/32: Always order writes to halves of 64-bit PTEs
From: Benjamin Herrenschmidt @ 2009-08-18 4:24 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <19081.57584.173693.798535@cargo.ozlabs.ibm.com>
On Tue, 2009-08-18 at 09:00 +1000, Paul Mackerras wrote:
> On 32-bit systems with 64-bit PTEs, the PTEs have to be written in two
> 32-bit halves. On SMP we write the higher-order half and then the
> lower-order half, with a write barrier between the two halves, but on
> UP there was no particular ordering of the writes to the two halves.
>
> This extends the ordering that we already do on SMP to the UP case as
> well. The reason is that with the perf_counter subsystem potentially
> accessing user memory at interrupt time to get stack traces, we have
> to be careful not to create an incorrect but apparently valid PTE even
> on UP.
>
> Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
> ---
> arch/powerpc/include/asm/pgtable.h | 6 +++---
> 1 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
> index eb17da7..2a5da06 100644
> --- a/arch/powerpc/include/asm/pgtable.h
> +++ b/arch/powerpc/include/asm/pgtable.h
> @@ -104,8 +104,8 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
> else
> pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
>
> -#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)
> - /* Second case is 32-bit with 64-bit PTE in SMP mode. In this case, we
> +#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
> + /* Second case is 32-bit with 64-bit PTE. In this case, we
> * can just store as long as we do the two halves in the right order
> * with a barrier in between. This is possible because we take care,
> * in the hash code, to pre-invalidate if the PTE was already hashed,
> @@ -140,7 +140,7 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
>
> #else
> /* Anything else just stores the PTE normally. That covers all 64-bit
> - * cases, and 32-bit non-hash with 64-bit PTEs in UP mode
> + * cases, and 32-bit non-hash with 32-bit PTEs.
> */
> *ptep = pte;
> #endif
^ permalink raw reply
* Re: [PATCH 2/3 v3] powerpc: Allow perf_counters to access user memory at interrupt time
From: Benjamin Herrenschmidt @ 2009-08-18 4:24 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <19081.57621.37210.987830@cargo.ozlabs.ibm.com>
On Tue, 2009-08-18 at 09:00 +1000, Paul Mackerras wrote:
> This provides a mechanism to allow the perf_counters code to access
> user memory in a PMU interrupt routine. Such an access can cause
> various kinds of interrupt: SLB miss, MMU hash table miss, segment
> table miss, or TLB miss, depending on the processor. This commit
> only deals with 64-bit classic/server processors, which use an MMU
> hash table. 32-bit processors are already able to access user memory
> at interrupt time. Since we don't soft-disable on 32-bit, we avoid
> the possibility of reentering hash_page or the TLB miss handlers,
> since they run with interrupts disabled.
.../...
>
> Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
^ permalink raw reply
* Re: [PATCH 3/3 v3] perf_counter: powerpc: Add callchain support
From: Benjamin Herrenschmidt @ 2009-08-18 4:23 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <19081.57647.221116.68329@cargo.ozlabs.ibm.com>
On Tue, 2009-08-18 at 09:01 +1000, Paul Mackerras wrote:
> This adds support for tracing callchains for powerpc, both 32-bit
> and 64-bit, and both in the kernel and userspace, from PMU interrupt
> context.
> Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
^ permalink raw reply
* [RFC] Clock binding
From: Benjamin Herrenschmidt @ 2009-08-18 4:21 UTC (permalink / raw)
To: devicetree-discuss; +Cc: linuxppc-dev list
So here's a followup to my discussion about the clock API.
I'm cooking up a patch that replace our current primitive implementation
in arch/powerpc/kernel/clock.c with something along the lines of what I
described. However, I want a bit more churn here on the device-tree
related bits.
So, basically, the goal here is to define a binding so that we can link
a device clock inputs to a clock provider clock outputs.
In general, in a system, there's actually 3 "names" involved. The clock
provider output name, the clock signal name, and the clock input name on
the device. However, I want to avoid involving the clock signal name as
it's a "global" name and it will just end up being a mess if we start
exposing that.
So basically, it boils down to a device having some clock inputs,
referenced by names, that need to be linked to another node which is a
clock provider, which has outputs, references either by number or names,
see discussion below.
First, why names, and not numbers ? IE. It's the OF "tradition" for
resources to just be an array, like interrupts, or address ranges in
"reg" properties, and one has to know what the Nth interrupt correspond
too.
My answer here is that maybe the tradition but it's crap :-) Names are
much better in the long run, besides it makes it easier to represent if
not all inputs have been wired. Also, to some extent, things like PCI do
encode a "name" with "reg" or "assigned-addresses" properties as part of
the config space offset in the top part of the address, and that has
proved very useful.
Thus I think using names is the way to go, and we should even generalize
that and add a new "interrupt-names" property to name the members of an
"interrupts" :-)
So back to the subject at hand. That leaves us with having to populate
the driver with some kind of map (I call it clock-map). Ideally, if
everything is named, which is the best approach imho, that map would
bind a list of:
- clock input name
- clock provider phandle
- clock output name on provider
However, it's a bit nasty to mix strings and numbers (phandles) in a
single property. It's possible, but would likely lead to the phandle not
being aligned and tools such as lsprop to fail miserably to display
those properties in any kind of readable form.
My earlier emails proposed an approach like this:
- clock input names go into a "clock-names" property
(which I suggest naming instead "clock-input-names" btw)
- the map goes into a "clock-map" property and for each input
provides a phandle and a one cell numerical ID that identifies
the clock on the source.
However, I really dislike that numerical clock ID. Magic numbers suck.
It should be a string. But I don't want to add a 3rd property in there.
Hence my idea below. It's not perfect but it's the less sucky i've come
up with so far. And then we can do some small refinements.
* Device has:
- "clock-input-names" as above
- "clock-map" contains list of phandle,index
* Clock source has:
- "clock-output-names" list of strings
The "index" in the clock map thus would reference the
"clock-output-names" array in the clock provider. That means that the
"magic number" here is entirely local to a given device-tree, doesn't
leak into driver code, which continues using names.
In addition, we can even have some smooth "upgrade" path from existing
"clock-frequency" properties by assuming that if "clock-output-names" is
absent, but "clock-frequency" exist, then index 0 references a fixed
frequency clock source without a driver. This could be generally handy
anyway to represent crystals of fixed bus clocks without having to write
a clock source driver for them.
Any comments ?
I'll post a patch, maybe later today, implementing the above (I may or
may not have time to also convert the existing 512x code to it, we'll
see).
Cheers,
Ben.
^ permalink raw reply
* Re: powerpc/405ex: Support cuImage for PPC405EX
From: Benjamin Herrenschmidt @ 2009-08-18 3:39 UTC (permalink / raw)
To: Tiejun Chen; +Cc: linuxppc-dev, linuxppc-dev
In-Reply-To: <1250562484-16415-1-git-send-email-tiejun.chen@windriver.com>
On Tue, 2009-08-18 at 10:28 +0800, Tiejun Chen wrote:
> Summary: powerpc/405ex: Support cuImage for PPC405EX
> Reviewers: Benjmain and linux-ppc
> ----------------------------------------------------
> These patch series are used to support cuImage on the kilauea board based on PPC405ex.
Thanks !
I'll let Josh pick that up.
Cheers,
Ben.
> Tested on the amcc kilauea board:
> ===
> ...
> => tftp 1000000 cuImage.kilauea
> Waiting for PHY auto negotiation to complete.. done
> ENET Speed is 100 Mbps - FULL duplex connection (EMAC0)
> Using ppc_4xx_eth0 device
> TFTP from server 192.168.1.2; our IP address is 192.168.1.103
> Filename 'cuImage.kilauea'.
> Load address: 0x1000000
> Loading: #################################################################
> #################################################################
> #################################################################
> #################################################################
> #########################################
> done
> Bytes transferred = 1540945 (178351 hex)
> => bootm
> ## Booting kernel from Legacy Image at 01000000 ...
> Image Name: Linux-2.6.31-rc5-57857-g8df7f47-
> Created: 2009-08-17 6:31:13 UTC
> Image Type: PowerPC Linux Kernel Image (gzip compressed)
> Data Size: 1540881 Bytes = 1.5 MB
> Load Address: 00400000
> Entry Point: 00400468
> Verifying Checksum ... OK
> Uncompressing Kernel Image ... OK
> CPU clock-frequency <- 0x23c345fa (600MHz)
> CPU timebase-frequency <- 0x23c345fa (600MHz)
> /plb: clock-frequency <- bebc1fe (200MHz)
> /plb/opb: clock-frequency <- 5f5e0ff (100MHz)
> /plb/opb/ebc: clock-frequency <- 5f5e0ff (100MHz)
> /plb/opb/serial@ef600200: clock-frequency <- a8c000 (11MHz)
> /plb/opb/serial@ef600300: clock-frequency <- a8c000 (11MHz)
> Memory <- <0x0 0x10000000> (256MB)
> ethernet0: local-mac-address <- 00:06:4b:10:22:6c
> ethernet1: local-mac-address <- 00:06:4b:10:22:6d
>
> zImage starting: loaded at 0x00400000 (sp: 0x0fe9ec08)
> Allocating 0x330c70 bytes for kernel ...
> gunzipping (0x00000000 <- 0x0040f000:0x0073a03c)...done 0x31425c bytes
>
> Linux/PowerPC load: root=/dev/nfs rw nfsroot=192.168.1.2:/home/vividfe/rootfsf
> Finalizing device tree... flat tree at 0x747300
> Using PowerPC 40x Platform machine description
> ...
>
> Best Regards
> Tiejun
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
^ permalink raw reply
* Mailing lists (Was: Re: powerpc/405ex: Support cuImage for PPC405EX)
From: Stephen Rothwell @ 2009-08-18 3:30 UTC (permalink / raw)
To: Tiejun Chen; +Cc: linuxppc-dev
In-Reply-To: <1250562484-16415-1-git-send-email-tiejun.chen@windriver.com>
[-- Attachment #1: Type: text/plain, Size: 265 bytes --]
Please do *not* send mail to both linuxppc-dev@ozlabs.org and
linuxppc-dev@lists.ozlabs.org. We all end up with two copies :-(
They are the same list.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* [PATCH 1/2] powerpc/405ex: provide necessary fixup function to support cuImage
From: Tiejun Chen @ 2009-08-18 2:28 UTC (permalink / raw)
To: benh, linuxppc-dev; +Cc: linuxppc-dev
In-Reply-To: <1250562484-16415-1-git-send-email-tiejun.chen@windriver.com>
For cuImage format it's necessary to provide clock fixups since u-boot will
not pass necessary clock frequency into the dtb included into cuImage so we
implement the clock fixups as defined in the technical documentation for the
board and update header file with the basic register definitions.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
---
arch/powerpc/boot/4xx.c | 142 +++++++++++++++++++++++++++++++++++++++++++++++
arch/powerpc/boot/4xx.h | 1 +
arch/powerpc/boot/dcr.h | 12 ++++
3 files changed, 155 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
index 325b310..b5561b3 100644
--- a/arch/powerpc/boot/4xx.c
+++ b/arch/powerpc/boot/4xx.c
@@ -8,6 +8,10 @@
* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
* Copyright (c) 2003, 2004 Zultys Technologies
*
+ * Copyright (C) 2009 Wind River Systems, Inc.
+ * Updated for supporting PPC405EX on Kilauea.
+ * Tiejun Chen <tiejun.chen@windriver.com>
+ *
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
@@ -659,3 +663,141 @@ void ibm405ep_fixup_clocks(unsigned int sys_clk)
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
}
+
+static u8 fwdv_multi_bits[] = {
+ /* values for: 1 - 16 */
+ 0x01, 0x02, 0x0e, 0x09, 0x04, 0x0b, 0x10, 0x0d, 0x0c, 0x05,
+ 0x06, 0x0f, 0x0a, 0x07, 0x08, 0x03
+};
+
+u32 get_fwdva(unsigned long cpr_fwdv)
+{
+ u32 index;
+
+ for (index = 0; index < ARRAY_SIZE(fwdv_multi_bits); index++)
+ if (cpr_fwdv == (u32)fwdv_multi_bits[index])
+ return index + 1;
+
+ return 0;
+}
+
+static u8 fbdv_multi_bits[] = {
+ /* values for: 1 - 100 */
+ 0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,
+ 0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,
+ 0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,
+ 0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,
+ 0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,
+ 0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,
+ 0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,
+ 0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,
+ 0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,
+ 0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,
+ /* values for: 101 - 200 */
+ 0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
+ 0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
+ 0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
+ 0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
+ 0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
+ 0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
+ 0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,
+ 0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,
+ 0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,
+ 0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,
+ /* values for: 201 - 255 */
+ 0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,
+ 0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,
+ 0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,
+ 0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,
+ 0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,
+ 0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */
+};
+
+u32 get_fbdv(unsigned long cpr_fbdv)
+{
+ u32 index;
+
+ for (index = 0; index < ARRAY_SIZE(fbdv_multi_bits); index++)
+ if (cpr_fbdv == (u32)fbdv_multi_bits[index])
+ return index + 1;
+
+ return 0;
+}
+
+void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk)
+{
+ /* PLL config */
+ u32 pllc = CPR0_READ(CPR0_PLLC);
+ u32 plld = CPR0_READ(CPR0_PLLD);
+ u32 cpud = CPR0_READ(CPR0_CPUD);
+ u32 plbd = CPR0_READ(CPR0_PLBD);
+ u32 opbd = CPR0_READ(CPR0_OPBD);
+ u32 perd = CPR0_READ(CPR0_PERD);
+
+ /* Dividers */
+ u32 fbdv = get_fbdv(__fix_zero((plld >> 24) & 0xff, 1));
+
+ u32 fwdva = get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1));
+
+ u32 cpudv0 = __fix_zero((cpud >> 24) & 7, 8);
+
+ /* PLBDV0 is hardwared to 010. */
+ u32 plbdv0 = 2;
+ u32 plb2xdv0 = __fix_zero((plbd >> 16) & 7, 8);
+
+ u32 opbdv0 = __fix_zero((opbd >> 24) & 3, 4);
+
+ u32 perdv0 = __fix_zero((perd >> 24) & 3, 4);
+
+ /* Resulting clocks */
+ u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1;
+
+ /* PLL's VCO is the source for primary forward ? */
+ if (pllc & 0x40000000) {
+ u32 m;
+
+ /* Feedback path */
+ switch ((pllc >> 24) & 7) {
+ case 0:
+ /* PLLOUTx */
+ m = fbdv;
+ break;
+ case 1:
+ /* CPU */
+ m = fbdv * fwdva * cpudv0;
+ break;
+ case 5:
+ /* PERClk */
+ m = fbdv * fwdva * plb2xdv0 * plbdv0 * opbdv0 * perdv0;
+ break;
+ default:
+ printf("WARNING ! Invalid PLL feedback source !\n");
+ goto bypass;
+ }
+
+ vco = (unsigned int)(sys_clk * m);
+ } else {
+bypass:
+ /* Bypass system PLL */
+ vco = 0;
+ }
+
+ /* CPU = VCO / ( FWDVA x CPUDV0) */
+ cpu = vco / (fwdva * cpudv0);
+ /* PLB = VCO / ( FWDVA x PLB2XDV0 x PLBDV0) */
+ plb = vco / (fwdva * plb2xdv0 * plbdv0);
+ /* OPB = PLB / OPBDV0 */
+ opb = plb / opbdv0;
+ /* EBC = OPB / PERDV0 */
+ ebc = opb / perdv0;
+
+ tb = cpu;
+ uart0 = uart1 = uart_clk;
+
+ dt_fixup_cpu_clocks(cpu, tb, 0);
+ dt_fixup_clock("/plb", plb);
+ dt_fixup_clock("/plb/opb", opb);
+ dt_fixup_clock("/plb/opb/ebc", ebc);
+ dt_fixup_clock("/plb/opb/serial@ef600200", uart0);
+ dt_fixup_clock("/plb/opb/serial@ef600300", uart1);
+}
diff --git a/arch/powerpc/boot/4xx.h b/arch/powerpc/boot/4xx.h
index 2606e64..7dc5d45 100644
--- a/arch/powerpc/boot/4xx.h
+++ b/arch/powerpc/boot/4xx.h
@@ -21,6 +21,7 @@ void ibm4xx_fixup_ebc_ranges(const char *ebc);
void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
void ibm405ep_fixup_clocks(unsigned int sys_clk);
+void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk);
void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
unsigned int tmr_clk);
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 95b9f53..ba41624 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -153,6 +153,18 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
#define DCRN_CPC0_PLLMR1 0xf4
#define DCRN_CPC0_UCR 0xf5
+/* 405EX Clocking Control regs */
+#define CPR0_CLKUPD 0x0020
+#define CPR0_PLLC 0x0040
+#define CPR0_PLLD 0x0060
+#define CPR0_CPUD 0x0080
+#define CPR0_PLBD 0x00a0
+#define CPR0_OPBD 0x00c0
+#define CPR0_PERD 0x00e0
+#define CPR0_AHBD 0x0100
+#define CPR0_ICFG 0x0140
+
+
/* 440GX Clock control etc */
--
1.5.6
^ permalink raw reply related
* [PATCH 2/2] powerpc/405ex: support cuImage via included dtb
From: Tiejun Chen @ 2009-08-18 2:28 UTC (permalink / raw)
To: benh, linuxppc-dev; +Cc: linuxppc-dev
In-Reply-To: <1250562484-16415-1-git-send-email-tiejun.chen@windriver.com>
To support cuImage, we need to initialize the required sections and
ensure that it is built.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
---
arch/powerpc/boot/Makefile | 3 +-
arch/powerpc/boot/cuboot-kilauea.c | 50 ++++++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/cuboot-kilauea.c
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 9ae7b7e..44ce95b 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -75,7 +75,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
- cuboot-acadia.c cuboot-amigaone.c
+ cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -192,6 +192,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImage
image-$(CONFIG_EP405) += dtbImage.ep405
image-$(CONFIG_WALNUT) += treeImage.walnut
image-$(CONFIG_ACADIA) += cuImage.acadia
+image-$(CONFIG_KILAUEA) += cuImage.kilauea
# Board ports in arch/powerpc/platform/44x/Kconfig
image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
diff --git a/arch/powerpc/boot/cuboot-kilauea.c b/arch/powerpc/boot/cuboot-kilauea.c
new file mode 100644
index 0000000..7db1b39
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-kilauea.c
@@ -0,0 +1,50 @@
+/*
+ * Old U-boot compatibility for PPC405EX. This image is already included
+ * a dtb.
+ *
+ * Author: Tiejun Chen <tiejun.chen@windriver.com>
+ *
+ * Copyright (C) 2009 Wind River Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "io.h"
+#include "dcr.h"
+#include "stdio.h"
+#include "4xx.h"
+#include "44x.h"
+#include "cuboot.h"
+
+#define TARGET_4xx
+#define TARGET_44x
+#include "ppcboot.h"
+
+#define KILAUEA_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
+
+static bd_t bd;
+
+static void kilauea_fixups(void)
+{
+ /*TODO: Please change this as the real. Note that should be 33MHZ~100MHZ.*/
+ unsigned long sysclk = 33333333;
+
+ ibm405ex_fixup_clocks(sysclk, KILAUEA_SYS_EXT_SERIAL_CLOCK);
+ dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
+ ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
+ dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+ dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ CUBOOT_INIT();
+ platform_ops.fixups = kilauea_fixups;
+ platform_ops.exit = ibm40x_dbcr_reset;
+ fdt_init(_dtb_start);
+ serial_console_init();
+}
--
1.5.6
^ permalink raw reply related
* powerpc/405ex: Support cuImage for PPC405EX
From: Tiejun Chen @ 2009-08-18 2:28 UTC (permalink / raw)
To: benh, linuxppc-dev; +Cc: linuxppc-dev
Summary: powerpc/405ex: Support cuImage for PPC405EX
Reviewers: Benjmain and linux-ppc
----------------------------------------------------
These patch series are used to support cuImage on the kilauea board based on PPC405ex.
Tested on the amcc kilauea board:
===
...
=> tftp 1000000 cuImage.kilauea
Waiting for PHY auto negotiation to complete.. done
ENET Speed is 100 Mbps - FULL duplex connection (EMAC0)
Using ppc_4xx_eth0 device
TFTP from server 192.168.1.2; our IP address is 192.168.1.103
Filename 'cuImage.kilauea'.
Load address: 0x1000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#########################################
done
Bytes transferred = 1540945 (178351 hex)
=> bootm
## Booting kernel from Legacy Image at 01000000 ...
Image Name: Linux-2.6.31-rc5-57857-g8df7f47-
Created: 2009-08-17 6:31:13 UTC
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 1540881 Bytes = 1.5 MB
Load Address: 00400000
Entry Point: 00400468
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
CPU clock-frequency <- 0x23c345fa (600MHz)
CPU timebase-frequency <- 0x23c345fa (600MHz)
/plb: clock-frequency <- bebc1fe (200MHz)
/plb/opb: clock-frequency <- 5f5e0ff (100MHz)
/plb/opb/ebc: clock-frequency <- 5f5e0ff (100MHz)
/plb/opb/serial@ef600200: clock-frequency <- a8c000 (11MHz)
/plb/opb/serial@ef600300: clock-frequency <- a8c000 (11MHz)
Memory <- <0x0 0x10000000> (256MB)
ethernet0: local-mac-address <- 00:06:4b:10:22:6c
ethernet1: local-mac-address <- 00:06:4b:10:22:6d
zImage starting: loaded at 0x00400000 (sp: 0x0fe9ec08)
Allocating 0x330c70 bytes for kernel ...
gunzipping (0x00000000 <- 0x0040f000:0x0073a03c)...done 0x31425c bytes
Linux/PowerPC load: root=/dev/nfs rw nfsroot=192.168.1.2:/home/vividfe/rootfsf
Finalizing device tree... flat tree at 0x747300
Using PowerPC 40x Platform machine description
...
Best Regards
Tiejun
^ permalink raw reply
* Re: [PATCH] powerpc: Fix __flush_icache_range on 44x
From: Benjamin Herrenschmidt @ 2009-08-18 0:54 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <20090818001614.GG3095@hansolo.jdub.homelinux.org>
On Mon, 2009-08-17 at 20:16 -0400, Josh Boyer wrote:
>
> You can if you'd like. My biggest concern is getting time to
> recreate. I
> think I'll have time later in the week if you'd like to wait until
> then.
> I simply didn't want to send out a patch that I wasn't sure fixed the
> issue.
>
That's ok. It's a bug fix so it's less constrained by the upcoming merge
window and we can send it back to -stable later.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Fix __flush_icache_range on 44x
From: Josh Boyer @ 2009-08-18 0:16 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1250545588.4861.5.camel@pasglop>
On Tue, Aug 18, 2009 at 07:46:28AM +1000, Benjamin Herrenschmidt wrote:
>On Mon, 2009-08-17 at 12:07 -0400, Josh Boyer wrote:
>>
>> Olof pointed out that we could probably do the iccci before the icbi loop and
>> just skip that loop entirely on 44x. This is most certainly valid, but at
>> this particular moment I don't have time to try and reproduce the issue with
>> an alternative fix and I wanted to get _something_ out there to fix the issue.
>>
>> I suck for that, I know.
>
>Well, I can massage your patch if you want. The fact is, the icbi loop
>and iccci are definitely redundant :-)
You can if you'd like. My biggest concern is getting time to recreate. I
think I'll have time later in the week if you'd like to wait until then.
I simply didn't want to send out a patch that I wasn't sure fixed the issue.
josh
^ permalink raw reply
* Re: [PATCH 1/3 v3] powerpc/32: Always order writes to halves of 64-bit PTEs
From: Paul Mackerras @ 2009-08-18 0:14 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <6FE668DD-C870-4FBB-A6AE-03CC0882E8EC@kernel.crashing.org>
Kumar Gala writes:
> On Aug 17, 2009, at 6:00 PM, Paul Mackerras wrote:
>
> > On 32-bit systems with 64-bit PTEs, the PTEs have to be written in two
> > 32-bit halves. On SMP we write the higher-order half and then the
> > lower-order half, with a write barrier between the two halves, but on
> > UP there was no particular ordering of the writes to the two halves.
> >
> > This extends the ordering that we already do on SMP to the UP case as
> > well. The reason is that with the perf_counter subsystem potentially
> > accessing user memory at interrupt time to get stack traces, we have
> > to be careful not to create an incorrect but apparently valid PTE even
> > on UP.
> >
> > Signed-off-by: Paul Mackerras <paulus@samba.org>
> > ---
> > arch/powerpc/include/asm/pgtable.h | 6 +++---
> > 1 files changed, 3 insertions(+), 3 deletions(-)
>
> Just out of interest did you end up hitting this in testing?
No. Ben told me he wanted this change, so I did what I was told. :)
Paul.
^ permalink raw reply
* Re: [PATCH 1/3 v3] powerpc/32: Always order writes to halves of 64-bit PTEs
From: Kumar Gala @ 2009-08-18 0:00 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <19081.57584.173693.798535@cargo.ozlabs.ibm.com>
On Aug 17, 2009, at 6:00 PM, Paul Mackerras wrote:
> On 32-bit systems with 64-bit PTEs, the PTEs have to be written in two
> 32-bit halves. On SMP we write the higher-order half and then the
> lower-order half, with a write barrier between the two halves, but on
> UP there was no particular ordering of the writes to the two halves.
>
> This extends the ordering that we already do on SMP to the UP case as
> well. The reason is that with the perf_counter subsystem potentially
> accessing user memory at interrupt time to get stack traces, we have
> to be careful not to create an incorrect but apparently valid PTE even
> on UP.
>
> Signed-off-by: Paul Mackerras <paulus@samba.org>
> ---
> arch/powerpc/include/asm/pgtable.h | 6 +++---
> 1 files changed, 3 insertions(+), 3 deletions(-)
Just out of interest did you end up hitting this in testing?
- k
^ permalink raw reply
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