* Re: [PATCH 3/6] 8xx: invalidate non present TLBs
From: Benjamin Herrenschmidt @ 2009-10-07 21:18 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <1254948364-30074-4-git-send-email-Joakim.Tjernlund@transmode.se>
On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote:
> 8xx sometimes need to load a invalid/non-present TLBs in
> it DTLB asm handler.
> These must be invalidated separaly as linux mm don't.
not sure about the dsisr test here, what is the point ?
Cheers,
Ben.
> ---
> arch/powerpc/mm/fault.c | 8 +++++++-
> 1 files changed, 7 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
> index 7699394..72941c7 100644
> --- a/arch/powerpc/mm/fault.c
> +++ b/arch/powerpc/mm/fault.c
> @@ -39,7 +39,7 @@
> #include <asm/uaccess.h>
> #include <asm/tlbflush.h>
> #include <asm/siginfo.h>
> -
> +#include <mm/mmu_decl.h>
>
> #ifdef CONFIG_KPROBES
> static inline int notify_page_fault(struct pt_regs *regs)
> @@ -243,6 +243,12 @@ good_area:
> goto bad_area;
> #endif /* CONFIG_6xx */
> #if defined(CONFIG_8xx)
> + /* 8xx sometimes need to load a invalid/non-present TLBs.
> + * These must be invalidated separately as linux mm don't.
> + */
> + if (error_code & 0x40000000) /* no translation? */
> + _tlbil_va(address);
> +
> /* The MPC8xx seems to always set 0x80000000, which is
> * "undefined". Of those that can be set, this is the only
> * one which seems bad.
^ permalink raw reply
* Re: [PATCH 2/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
From: Benjamin Herrenschmidt @ 2009-10-07 21:14 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <1254948364-30074-3-git-send-email-Joakim.Tjernlund@transmode.se>
On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote:
> + andi. r11, r10, _PAGE_USER | _PAGE_ACCESSED
> + cmpwi cr0, r11, _PAGE_USER | _PAGE_ACCESSED
> + bne- cr0, 2f
Did you mean _PAGE_PRESENT | _PAGE_ACCESSED ?
> +2:
> + mfspr r11, SRR1
> + rlwinm r11, r11, 0, 5, 3 /* clear guarded */
> + mtspr SRR1, r11
What is the above for ?
> + mfspr r10, SPRN_M_TW /* Restore registers */
> + lwz r11, 0(r0)
> + mtcr r11
> + lwz r11, 4(r0)
> +#ifdef CONFIG_8xx_CPU6
> + lwz r3, 8(r0)
> +#endif
> + b InstructionAccess
>
.../...
> + andi. r11, r10, _PAGE_ACCESSED
> + bne+ cr0, 5f /* branch if access allowed */
> + rlwinm r10, r10, 0, 21, 19 /* Clear _PAGE_USER */
> + ori r10, r10, _PAGE_RW /* Set RW bit for xor below to clear it */
> +5: xori r10, r10, _PAGE_RW /* invert RW bit */
Why are you clearing _PAGE_USER ? One needs to differenciate usr
from kernel pages or user will be access to write to kernel...
Why don't you do the trick I proposed in my email with loading a
constant that contains all the bit combinations and shifting it
by the amount defined by _PAGE_RW and _PAGE_USER used as a two
bits index ?
> /* The Linux PTE won't go exactly into the MMU TLB.
> - * Software indicator bits 21, 22 and 28 must be clear.
> + * Software indicator bits 22 and 28 must be clear.
> * Software indicator bits 24, 25, 26, and 27 must be
> * set. All other Linux PTE bits control the behavior
> * of the MMU.
> @@ -472,8 +470,8 @@ DataTLBError:
> /* First, make sure this was a store operation.
> */
> mfspr r10, SPRN_DSISR
> - andis. r11, r10, 0x4800 /* no translation, no permission. */
> - bne 2f /* branch if either is set */
> + andis. r11, r10, 0x4000 /* no translation */
> + bne 2f /* branch if set */
>
> /* The EA of a data TLB miss is automatically stored in the MD_EPN
> * register. The EA of a data TLB error is automatically stored in
> @@ -522,26 +520,20 @@ DataTLBError:
> mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
> lwz r10, 0(r11) /* Get the pte */
>
> - andi. r11, r10, _PAGE_RW /* Is it writeable? */
> - beq 2f /* Bail out if not */
> -
> - /* Update 'changed', among others.
> - */
> -#ifdef CONFIG_SWAP
> + mfspr r11, DSISR
> + andis. r11, r11, 0x0200 /* store */
> + beq 5f
> + andi. r11, r10, _PAGE_RW /* writeable? */
> + beq 2f /* nope */
> ori r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE
> - /* do not set the _PAGE_ACCESSED bit of a non-present page */
> - andi. r11, r10, _PAGE_PRESENT
> - beq 4f
> - ori r10, r10, _PAGE_ACCESSED
> -4:
> -#else
> - ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
> -#endif
> - mfspr r11, SPRN_MD_TWC /* Get pte address again */
> +5: ori r10, r10, _PAGE_ACCESSED
> + mfspr r11, MD_TWC /* Get pte address again */
> stw r10, 0(r11) /* and update pte in table */
>
> + xori r10, r10, _PAGE_RW /* RW bit is inverted */
> +
> /* The Linux PTE won't go exactly into the MMU TLB.
> - * Software indicator bits 21, 22 and 28 must be clear.
> + * Software indicator bits 22 and 28 must be clear.
> * Software indicator bits 24, 25, 26, and 27 must be
> * set. All other Linux PTE bits control the behavior
> * of the MMU.
I still don't find how any of the above is useful... why not just go
straight to C code ?
Cheers,
Ben.
^ permalink raw reply
* Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
From: David Miller @ 2009-10-07 21:09 UTC (permalink / raw)
To: crn
Cc: sammy, sfr, microblaze-uclinux, devicetree-discuss, sparclinux,
julian.calaby, wmb, linuxppc-dev
In-Reply-To: <Pine.LNX.4.60.0910072148040.11795@mailgate.netunix.com>
From: Chris Newport <crn@netunix.com>
Date: Wed, 7 Oct 2009 21:54:34 +0100 (BST)
> Sun4c has also been broken for a long time and sun4d has never worked
> properly. Is it time to also prune these ?.
> That would leave only Sun4m in the 32bit kernel, which still works and
> has plenty of ongoing user interest.
Chris don't over-exaggerate the state.
The truth is that the whole sparc32 port is in a state of mild
disrepair, and many of the issues apply to all the port rather than
just one family of systems. I think someone suitably motivated
could get most of the bugs sorted out.
There is no reason to drop support for SS1 machines, we already fully
build the software device tree and use all of the generic OF
infrastructure in the Linux kernel on those systems. It is not a road
block at all for the OF genericization work, if that's what you read
into wmb's email.
^ permalink raw reply
* Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
From: Chris Newport @ 2009-10-07 20:54 UTC (permalink / raw)
To: Mitch Bradley
Cc: Sam Creasey, Stephen Rothwell, Julian Calaby, devicetree-discuss,
microblaze-uclinux, sparclinux, linuxppc-dev, davem
In-Reply-To: <4ACCEC67.9070106@firmworks.com>
On Wed, 7 Oct 2009, Mitch Bradley wrote:
> Taking this one step further, I don't see any real good reason to continue
> supporting Sun4 going forward. I got rid of my Sun4 systems long ago because
> it was just too hard to keep them working - after having used them long after
> most people had moved on. Dropping Sun3 and Sun4 eliminates all vestiges of
> the sunmon interface and also allows dropping support for OBP version 1,
> which only shipped on SS1-class machines - the first machines in the Sun4c
> subclass.
Sun4c has also been broken for a long time and sun4d has never worked
properly. Is it time to also prune these ?.
That would leave only Sun4m in the 32bit kernel, which still works and
has plenty of ongoing user interest.
^ permalink raw reply
* [PATCH 4/6] 8xx: Tag DAR with 0x00f0 to catch buggy instructions.
From: Joakim Tjernlund @ 2009-10-07 20:46 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Rex Feany, Scott Wood,
Benjamin Herrenschmidt
In-Reply-To: <1254948364-30074-4-git-send-email-Joakim.Tjernlund@transmode.se>
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
Test for DAR=0x00f0 in DataTLBError and bail
to handle_page_fault().
---
arch/powerpc/kernel/head_8xx.S | 19 ++++++++++++++++---
1 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 3cf1289..37aa7d0 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -206,6 +206,8 @@ MachineCheck:
EXCEPTION_PROLOG
mfspr r4,SPRN_DAR
stw r4,_DAR(r11)
+ li r5,0x00f0
+ mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
mfspr r5,SPRN_DSISR
stw r5,_DSISR(r11)
addi r3,r1,STACK_FRAME_OVERHEAD
@@ -222,6 +224,8 @@ DataAccess:
stw r10,_DSISR(r11)
mr r5,r10
mfspr r4,SPRN_DAR
+ li r10,0x00f0
+ mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
EXC_XFER_EE_LITE(0x300, handle_page_fault)
/* Instruction access exception.
@@ -244,6 +248,8 @@ Alignment:
EXCEPTION_PROLOG
mfspr r4,SPRN_DAR
stw r4,_DAR(r11)
+ li r5,0x00f0
+ mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
mfspr r5,SPRN_DSISR
stw r5,_DSISR(r11)
addi r3,r1,STACK_FRAME_OVERHEAD
@@ -427,6 +433,7 @@ DataStoreTLBMiss:
* of the MMU.
*/
2: li r11, 0x00f0
+ mtspr SPRN_DAR,r11 /* Tag DAR */
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3)
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
@@ -467,10 +474,14 @@ DataTLBError:
stw r10, 0(r0)
stw r11, 4(r0)
+ mfspr r10, SPRN_DAR
+ cmpwi cr0, r10, 0x00f0
+ beq- 2f /* must be a buggy dcbX, icbi insn. */
+
/* First, make sure this was a store operation.
*/
- mfspr r10, SPRN_DSISR
- andis. r11, r10, 0x4000 /* no translation */
+ mfspr r11, SPRN_DSISR
+ andis. r11, r11, 0x4000 /* no translation */
bne 2f /* branch if set */
/* The EA of a data TLB miss is automatically stored in the MD_EPN
@@ -489,7 +500,8 @@ DataTLBError:
* are initialized in mapin_ram(). This will avoid the problem,
* assuming we only use the dcbi instruction on kernel addresses.
*/
- mfspr r10, SPRN_DAR
+
+ /* DAR is in r10 already */
rlwinm r11, r10, 0, 0, 19
ori r11, r11, MD_EVALID
mfspr r10, SPRN_M_CASID
@@ -539,6 +551,7 @@ DataTLBError:
* of the MMU.
*/
li r11, 0x00f0
+ mtspr SPRN_DAR,r11 /* Tag DAR */
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3)
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
--
1.6.4.4
^ permalink raw reply related
* [PATCH 6/6] 8xx: start using dcbX instructions in various copy routines
From: Joakim Tjernlund @ 2009-10-07 20:46 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Rex Feany, Scott Wood,
Benjamin Herrenschmidt
In-Reply-To: <1254948364-30074-6-git-send-email-Joakim.Tjernlund@transmode.se>
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
---
arch/powerpc/kernel/misc_32.S | 18 ------------------
arch/powerpc/lib/copy_32.S | 24 ------------------------
2 files changed, 0 insertions(+), 42 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 15f28e0..b92095e 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -495,15 +495,7 @@ _GLOBAL(clear_pages)
li r0,PAGE_SIZE/L1_CACHE_BYTES
slw r0,r0,r4
mtctr r0
-#ifdef CONFIG_8xx
- li r4, 0
-1: stw r4, 0(r3)
- stw r4, 4(r3)
- stw r4, 8(r3)
- stw r4, 12(r3)
-#else
1: dcbz 0,r3
-#endif
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
blr
@@ -528,15 +520,6 @@ _GLOBAL(copy_page)
addi r3,r3,-4
addi r4,r4,-4
-#ifdef CONFIG_8xx
- /* don't use prefetch on 8xx */
- li r0,4096/L1_CACHE_BYTES
- mtctr r0
-1: COPY_16_BYTES
- bdnz 1b
- blr
-
-#else /* not 8xx, we can prefetch */
li r5,4
#if MAX_COPY_PREFETCH > 1
@@ -577,7 +560,6 @@ _GLOBAL(copy_page)
li r0,MAX_COPY_PREFETCH
li r11,4
b 2b
-#endif /* CONFIG_8xx */
/*
* void atomic_clear_mask(atomic_t mask, atomic_t *addr)
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index c657de5..74a7f41 100644
--- a/arch/powerpc/lib/copy_32.S
+++ b/arch/powerpc/lib/copy_32.S
@@ -98,20 +98,7 @@ _GLOBAL(cacheable_memzero)
bdnz 4b
3: mtctr r9
li r7,4
-#if !defined(CONFIG_8xx)
10: dcbz r7,r6
-#else
-10: stw r4, 4(r6)
- stw r4, 8(r6)
- stw r4, 12(r6)
- stw r4, 16(r6)
-#if CACHE_LINE_SIZE >= 32
- stw r4, 20(r6)
- stw r4, 24(r6)
- stw r4, 28(r6)
- stw r4, 32(r6)
-#endif /* CACHE_LINE_SIZE */
-#endif
addi r6,r6,CACHELINE_BYTES
bdnz 10b
clrlwi r5,r8,32-LG_CACHELINE_BYTES
@@ -200,9 +187,7 @@ _GLOBAL(cacheable_memcpy)
mtctr r0
beq 63f
53:
-#if !defined(CONFIG_8xx)
dcbz r11,r6
-#endif
COPY_16_BYTES
#if L1_CACHE_BYTES >= 32
COPY_16_BYTES
@@ -356,14 +341,6 @@ _GLOBAL(__copy_tofrom_user)
li r11,4
beq 63f
-#ifdef CONFIG_8xx
- /* Don't use prefetch on 8xx */
- mtctr r0
- li r0,0
-53: COPY_16_BYTES_WITHEX(0)
- bdnz 53b
-
-#else /* not CONFIG_8xx */
/* Here we decide how far ahead to prefetch the source */
li r3,4
cmpwi r0,1
@@ -416,7 +393,6 @@ _GLOBAL(__copy_tofrom_user)
li r3,4
li r7,0
bne 114b
-#endif /* CONFIG_8xx */
63: srwi. r0,r5,2
mtctr r0
--
1.6.4.4
^ permalink raw reply related
* [PATCH 5/6] 8xx: Fixup DAR from buggy dcbX instructions.
From: Joakim Tjernlund @ 2009-10-07 20:46 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Rex Feany, Scott Wood,
Benjamin Herrenschmidt
In-Reply-To: <1254948364-30074-5-git-send-email-Joakim.Tjernlund@transmode.se>
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code(default), the other uses
jump table but is much bigger.
---
arch/powerpc/kernel/head_8xx.S | 146 +++++++++++++++++++++++++++++++++++++++-
1 files changed, 145 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 37aa7d0..8c4c416 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -476,7 +476,8 @@ DataTLBError:
mfspr r10, SPRN_DAR
cmpwi cr0, r10, 0x00f0
- beq- 2f /* must be a buggy dcbX, icbi insn. */
+ beq- FixDAR /* must be a buggy dcbX, icbi insn. */
+DARFix: /* Return from dcbx instruction bug workaround, r10 holds value of DAR */
/* First, make sure this was a store operation.
*/
@@ -593,6 +594,149 @@ DataTLBError:
. = 0x2000
+/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
+ * by decoding the registers used by the dcbx instruction and adding them.
+ * DAR is set to the calculated address and r10 also holds the EA on exit.
+ */
+//#define NO_SELF_MODIFYING_CODE /* define if you don't want to use self modifying code */
+ nop /* A few nops to make the modified_instr: space below cache line aligned */
+ nop
+139: /* fetch instruction from userspace memory */
+ DO_8xx_CPU6(0x3780, r3)
+ mtspr SPRN_MD_EPN, r10
+ mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */
+ lwz r11, 0(r11) /* Get the level 1 entry */
+ tophys (r11, r11)
+ DO_8xx_CPU6(0x3b80, r3)
+ mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
+ mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
+ lwz r11, 0(r11) /* Get the pte */
+ /* concat physical page address(r11) and page offset(r10) */
+ rlwimi r11, r10, 0, 20, 31
+ b 140f
+FixDAR: /* Entry point for dcbx workaround. */
+ /* fetch instruction from memory. */
+ mfspr r10, SPRN_SRR0
+ andis. r11, r10, 0x8000
+ tophys (r11, r10)
+ beq- 139b /* Branch if user space address */
+140: lwz r11,0(r11)
+#ifdef CONFIG_8xx_CPU6
+ lwz r3, 8(r0) /* restore r3 from memory */
+#endif
+#ifndef NO_SELF_MODIFYING_CODE
+ andis. r10,r11,0x1f /* test if reg RA is r0 */
+ li r10,modified_instr@l
+ dcbtst r0,r10 /* touch for store */
+ rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
+ oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
+ ori r11,r11,532
+ stw r11,0(r10) /* store add/and instruction */
+ dcbf 0,r10 /* flush new instr. to memory. */
+ icbi 0,r10 /* invalidate instr. cache line */
+ lwz r11, 4(r0) /* restore r11 from memory */
+ mfspr r10, SPRN_M_TW /* restore r10 from M_TW */
+ isync /* Wait until new instr is loaded from memory */
+modified_instr:
+ .space 4 /* this is where the add/and instr. is stored */
+ bne+ 143f
+ subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
+143: mtdar r10 /* store faulting EA in DAR */
+ b DARFix /* Go back to normal TLB handling */
+#else
+ mfctr r10
+ mtdar r10 /* save ctr reg in DAR */
+ rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
+ addi r10, r10, 150f@l /* add start of table */
+ mtctr r10 /* load ctr with jump address */
+ xor r10, r10, r10 /* sum starts at zero */
+ bctr /* jump into table */
+150:
+ add r10, r10, r0
+ b 151f
+ add r10, r10, r1
+ b 151f
+ add r10, r10, r2
+ b 151f
+ add r10, r10, r3
+ b 151f
+ add r10, r10, r4
+ b 151f
+ add r10, r10, r5
+ b 151f
+ add r10, r10, r6
+ b 151f
+ add r10, r10, r7
+ b 151f
+ add r10, r10, r8
+ b 151f
+ add r10, r10, r9
+ b 151f
+ add r10, r10, r10
+ b 151f
+ add r10, r10, r11
+ b 151f
+ add r10, r10, r12
+ b 151f
+ add r10, r10, r13
+ b 151f
+ add r10, r10, r14
+ b 151f
+ add r10, r10, r15
+ b 151f
+ add r10, r10, r16
+ b 151f
+ add r10, r10, r17
+ b 151f
+ add r10, r10, r18
+ b 151f
+ add r10, r10, r19
+ b 151f
+ mtctr r11 /* r10 needs special handling */
+ b 154f
+ mtctr r11 /* r11 needs special handling */
+ b 153f
+ add r10, r10, r22
+ b 151f
+ add r10, r10, r23
+ b 151f
+ add r10, r10, r24
+ b 151f
+ add r10, r10, r25
+ b 151f
+ add r10, r10, r25
+ b 151f
+ add r10, r10, r27
+ b 151f
+ add r10, r10, r28
+ b 151f
+ add r10, r10, r29
+ b 151f
+ add r10, r10, r30
+ b 151f
+ add r10, r10, r31
+151:
+ rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
+ beq 152f /* if reg RA is zero, don't add it */
+ addi r11, r11, 150b@l /* add start of table */
+ mtctr r11 /* load ctr with jump address */
+ rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
+ bctr /* jump into table */
+152:
+ mfdar r11
+ mtctr r11 /* restore ctr reg from DAR */
+ mtdar r10 /* save fault EA to DAR */
+ b DARFix /* Go back to normal TLB handling */
+
+ /* special handling for r10,r11 since these are modified already */
+153: lwz r11, 4(r0) /* load r11 from memory */
+ b 155f
+154: mfspr r11, SPRN_M_TW /* load r10 from M_TW */
+155: add r10, r10, r11 /* add it */
+ mfctr r11 /* restore r11 */
+ b 151b
+#endif
+
.globl giveup_fpu
giveup_fpu:
blr
--
1.6.4.4
^ permalink raw reply related
* [PATCH 2/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
From: Joakim Tjernlund @ 2009-10-07 20:46 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Rex Feany, Scott Wood,
Benjamin Herrenschmidt
In-Reply-To: <1254948364-30074-2-git-send-email-Joakim.Tjernlund@transmode.se>
Update the TLB asm to make proper use of _PAGE_DIRY and _PAGE_ACCESSED.
Pros:
- I/D TLB Miss never needs to write to the linux pte.
- _PAGE_ACCESSED is only set on TLB Error fixing accounting
- _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly
when a page has been made dirty.
- Proper RO/RW mapping of user space.
- Free up 2 SW TLB bits in the linux pte(add back _PAGE_WRITETHRU ?)
Cons:
- 1 more instructions in I/D TLB Miss, but the since the linux pte is
not written anymore, it should still be a big win.
---
arch/powerpc/include/asm/pte-8xx.h | 13 +++---
arch/powerpc/kernel/head_8xx.S | 82 ++++++++++++++++--------------------
2 files changed, 43 insertions(+), 52 deletions(-)
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
index 8c6e312..f23cd15 100644
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -32,22 +32,21 @@
#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
+#define _PAGE_DIRTY 0x0100 /* C: page changed */
-/* These five software bits must be masked out when the entry is loaded
- * into the TLB.
+/* These 3 software bits must be masked out when the entry is loaded
+ * into the TLB, 2 SW bits left.
*/
#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
#define _PAGE_GUARDED 0x0010 /* software: guarded access */
-#define _PAGE_DIRTY 0x0020 /* software: page changed */
-#define _PAGE_RW 0x0040 /* software: user write access allowed */
-#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
+#define _PAGE_ACCESSED 0x0020 /* software: page referenced */
/* Setting any bits in the nibble with the follow two controls will
* require a TLB exception handler change. It is assumed unused bits
* are always zero.
*/
-#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
-#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
+#define _PAGE_RW 0x0400 /* lsb PP bits, inverted in HW */
+#define _PAGE_USER 0x0800 /* msb PP bits */
#define _PMD_PRESENT 0x0001
#define _PMD_BAD 0x0ff0
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 118bb05..3cf1289 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -333,26 +333,18 @@ InstructionTLBMiss:
mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
lwz r10, 0(r11) /* Get the pte */
-#ifdef CONFIG_SWAP
- /* do not set the _PAGE_ACCESSED bit of a non-present page */
- andi. r11, r10, _PAGE_PRESENT
- beq 4f
- ori r10, r10, _PAGE_ACCESSED
- mfspr r11, SPRN_MD_TWC /* get the pte address again */
- stw r10, 0(r11)
-4:
-#else
- ori r10, r10, _PAGE_ACCESSED
- stw r10, 0(r11)
-#endif
+ andi. r11, r10, _PAGE_USER | _PAGE_ACCESSED
+ cmpwi cr0, r11, _PAGE_USER | _PAGE_ACCESSED
+ bne- cr0, 2f
+ /* Dont' bother with PP lsb, bit 21 for now */
/* The Linux PTE won't go exactly into the MMU TLB.
- * Software indicator bits 21, 22 and 28 must be clear.
+ * Software indicator bits 22 and 28 must be clear.
* Software indicator bits 24, 25, 26, and 27 must be
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
-2: li r11, 0x00f0
+ li r11, 0x00f0
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x2d80, r3)
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
@@ -365,6 +357,19 @@ InstructionTLBMiss:
lwz r3, 8(r0)
#endif
rfi
+2:
+ mfspr r11, SRR1
+ rlwinm r11, r11, 0, 5, 3 /* clear guarded */
+ mtspr SRR1, r11
+
+ mfspr r10, SPRN_M_TW /* Restore registers */
+ lwz r11, 0(r0)
+ mtcr r11
+ lwz r11, 4(r0)
+#ifdef CONFIG_8xx_CPU6
+ lwz r3, 8(r0)
+#endif
+ b InstructionAccess
. = 0x1200
DataStoreTLBMiss:
@@ -409,21 +414,14 @@ DataStoreTLBMiss:
DO_8xx_CPU6(0x3b80, r3)
mtspr SPRN_MD_TWC, r11
-#ifdef CONFIG_SWAP
- /* do not set the _PAGE_ACCESSED bit of a non-present page */
- andi. r11, r10, _PAGE_PRESENT
- beq 4f
- ori r10, r10, _PAGE_ACCESSED
-4:
- /* and update pte in table */
-#else
- ori r10, r10, _PAGE_ACCESSED
-#endif
- mfspr r11, SPRN_MD_TWC /* get the pte address again */
- stw r10, 0(r11)
+ andi. r11, r10, _PAGE_ACCESSED
+ bne+ cr0, 5f /* branch if access allowed */
+ rlwinm r10, r10, 0, 21, 19 /* Clear _PAGE_USER */
+ ori r10, r10, _PAGE_RW /* Set RW bit for xor below to clear it */
+5: xori r10, r10, _PAGE_RW /* invert RW bit */
/* The Linux PTE won't go exactly into the MMU TLB.
- * Software indicator bits 21, 22 and 28 must be clear.
+ * Software indicator bits 22 and 28 must be clear.
* Software indicator bits 24, 25, 26, and 27 must be
* set. All other Linux PTE bits control the behavior
* of the MMU.
@@ -472,8 +470,8 @@ DataTLBError:
/* First, make sure this was a store operation.
*/
mfspr r10, SPRN_DSISR
- andis. r11, r10, 0x4800 /* no translation, no permission. */
- bne 2f /* branch if either is set */
+ andis. r11, r10, 0x4000 /* no translation */
+ bne 2f /* branch if set */
/* The EA of a data TLB miss is automatically stored in the MD_EPN
* register. The EA of a data TLB error is automatically stored in
@@ -522,26 +520,20 @@ DataTLBError:
mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
lwz r10, 0(r11) /* Get the pte */
- andi. r11, r10, _PAGE_RW /* Is it writeable? */
- beq 2f /* Bail out if not */
-
- /* Update 'changed', among others.
- */
-#ifdef CONFIG_SWAP
+ mfspr r11, DSISR
+ andis. r11, r11, 0x0200 /* store */
+ beq 5f
+ andi. r11, r10, _PAGE_RW /* writeable? */
+ beq 2f /* nope */
ori r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE
- /* do not set the _PAGE_ACCESSED bit of a non-present page */
- andi. r11, r10, _PAGE_PRESENT
- beq 4f
- ori r10, r10, _PAGE_ACCESSED
-4:
-#else
- ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
-#endif
- mfspr r11, SPRN_MD_TWC /* Get pte address again */
+5: ori r10, r10, _PAGE_ACCESSED
+ mfspr r11, MD_TWC /* Get pte address again */
stw r10, 0(r11) /* and update pte in table */
+ xori r10, r10, _PAGE_RW /* RW bit is inverted */
+
/* The Linux PTE won't go exactly into the MMU TLB.
- * Software indicator bits 21, 22 and 28 must be clear.
+ * Software indicator bits 22 and 28 must be clear.
* Software indicator bits 24, 25, 26, and 27 must be
* set. All other Linux PTE bits control the behavior
* of the MMU.
--
1.6.4.4
^ permalink raw reply related
* [PATCH 0/6] 8xx TLB fixes.
From: Joakim Tjernlund @ 2009-10-07 20:45 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Rex Feany, Scott Wood,
Benjamin Herrenschmidt
OK, here is the next try att fixing the MPC8xx MMU
problems. Pleas add one(or two) patches at a time and
test.
Expect some trivial merge conflicts in 8xx header file, sorry
about that.
Joakim Tjernlund (6):
8xx: DTLB Error must check for more errors.
8xx: get rid of _PAGE_HWWRITE dependency in MMU.
8xx: invalidate non present TLBs
8xx: Tag DAR with 0x00f0 to catch buggy instructions.
8xx: Fixup DAR from buggy dcbX instructions.
8xx: start using dcbX instructions in various copy routines
arch/powerpc/include/asm/pte-8xx.h | 13 +-
arch/powerpc/kernel/head_8xx.S | 243 +++++++++++++++++++++++++++++-------
arch/powerpc/kernel/misc_32.S | 18 ---
arch/powerpc/lib/copy_32.S | 24 ----
arch/powerpc/mm/fault.c | 8 +-
5 files changed, 209 insertions(+), 97 deletions(-)
^ permalink raw reply
* [PATCH 1/6] 8xx: DTLB Error must check for more errors.
From: Joakim Tjernlund @ 2009-10-07 20:45 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Rex Feany, Scott Wood,
Benjamin Herrenschmidt
In-Reply-To: <1254948364-30074-1-git-send-email-Joakim.Tjernlund@transmode.se>
DataTLBError currently does:
if ((err & 0x02000000) == 0)
DSI();
This won't handle a store with no valid translation.
Change this to
if ((err & 0x48000000) != 0)
DSI();
that is, branch to DSI if either !permission or
!translation.
---
arch/powerpc/kernel/head_8xx.S | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 52ff8c5..118bb05 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -472,8 +472,8 @@ DataTLBError:
/* First, make sure this was a store operation.
*/
mfspr r10, SPRN_DSISR
- andis. r11, r10, 0x0200 /* If set, indicates store op */
- beq 2f
+ andis. r11, r10, 0x4800 /* no translation, no permission. */
+ bne 2f /* branch if either is set */
/* The EA of a data TLB miss is automatically stored in the MD_EPN
* register. The EA of a data TLB error is automatically stored in
--
1.6.4.4
^ permalink raw reply related
* [PATCH 3/6] 8xx: invalidate non present TLBs
From: Joakim Tjernlund @ 2009-10-07 20:46 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Rex Feany, Scott Wood,
Benjamin Herrenschmidt
In-Reply-To: <1254948364-30074-3-git-send-email-Joakim.Tjernlund@transmode.se>
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
---
arch/powerpc/mm/fault.c | 8 +++++++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 7699394..72941c7 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -39,7 +39,7 @@
#include <asm/uaccess.h>
#include <asm/tlbflush.h>
#include <asm/siginfo.h>
-
+#include <mm/mmu_decl.h>
#ifdef CONFIG_KPROBES
static inline int notify_page_fault(struct pt_regs *regs)
@@ -243,6 +243,12 @@ good_area:
goto bad_area;
#endif /* CONFIG_6xx */
#if defined(CONFIG_8xx)
+ /* 8xx sometimes need to load a invalid/non-present TLBs.
+ * These must be invalidated separately as linux mm don't.
+ */
+ if (error_code & 0x40000000) /* no translation? */
+ _tlbil_va(address);
+
/* The MPC8xx seems to always set 0x80000000, which is
* "undefined". Of those that can be set, this is the only
* one which seems bad.
--
1.6.4.4
^ permalink raw reply related
* Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
From: Mitch Bradley @ 2009-10-07 19:30 UTC (permalink / raw)
To: Sam Creasey
Cc: Stephen Rothwell, Julian Calaby, devicetree-discuss,
microblaze-uclinux, sparclinux, linuxppc-dev, davem
In-Reply-To: <20091007135243.GC21646@anhedonia>
>
> Sun3 doesn't have OF
When I was first developing Open Boot for the SPARCstation-1, I was also
simultaneously trying to do it for a Sun-3 system that was being built
at the same time.
It proved to be too much to do both jobs at the same time, especially in
light of all the hardware debugging that is part of a new system
bringup. So I gave up on Sun 3 and just focused on SS-1.
That particular Sun-3 machine never sold very well, while the SS-1 was
very popular. That was Sun's last 680x0 machine.
Personally, I think that continuing to support Sun-3 in Linux is not
useful in a practical sense. To the extent that supporting
long-obsolete platforms and devices makes the job harder for current
systems, it is actually harmful. Portability and generality is good in
some theoretical "rightness" sense, but there are practical limits.
Code can become so heavily layered that approaching it requires a huge
commitment of effort to learn all the artificial layers. Sometimes you
have to prune the dead branches so the living ones can get light and air.
Taking this one step further, I don't see any real good reason to
continue supporting Sun4 going forward. I got rid of my Sun4 systems
long ago because it was just too hard to keep them working - after
having used them long after most people had moved on. Dropping Sun3 and
Sun4 eliminates all vestiges of the sunmon interface and also allows
dropping support for OBP version 1, which only shipped on SS1-class
machines - the first machines in the Sun4c subclass.
^ permalink raw reply
* Trouble with canyonlands and PCI-E LSI SAS Controller
From: Ayman El-Khashab @ 2009-10-07 17:30 UTC (permalink / raw)
To: linuxppc-dev
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=unknown-8bit, Size: 26505 bytes --]
Hello, I've got some trouble getting an LSI SAS controller (LSISAS200)
to function. It is at least enumerated correctly in a PC running
ubuntu, so it seems that it must be something particular to the PCI
implementation on the powerpc or the usage of u-boot.
If the board is initialized by u-boot, and the BAR0 is written, then
the board does not seem to respond to cfgrds when linux probes. And
the kernel crashes when the scsi low level are loaded.
If u-boot is inhibited and therefore linux sees the card in its reset
state then it will boot ok, but an lspci will show the card as disabled.
The last issue, is that I am not quite sure exactly which kernel drivers
are needed for this device.
Here is the output from DEBUG=1 in the pci_probe. The first is without
the fusion driver, and the latter is with the fusion driver.
Thanks
Ayman
# dmesg Bus: primary=80, secondary=81, subordinate=bf, sec-latency=0
Using PowerPC 44x Platform machine description
Linux version 2.6.31 (bobe@lablinux) (gcc version 4.2.2) #61 Tue Oct 6 08:25:39 CDT 2009
Found initrd at 0xdfb09000:0xdfe4cc6eidge: 0000000080100000-00000000801fffff
Found legacy serial port 0 for /plb/opb/serial@ef600300
mem=4ef600300, taddr=4ef600300, irq=0, clk=6451612, speed=0
Found legacy serial port 1 for /plb/opb/serial@ef600400: Mask- 64bit+ Queue=0/2 Enable-
mem=4ef600400, taddr=4ef600400, irq=0, clk=6451612, speed=0
Found legacy serial port 2 for /plb/opb/serial@ef600500
mem=4ef600500, taddr=4ef600500, irq=0, clk=6451612, speed=0
Found legacy serial port 3 for /plb/opb/serial@ef600600
mem=4ef600600, taddr=4ef600600, irq=0, clk=6451612, speed=0
Top of RAM: 0x20000000, Total RAM: 0x20000000
Memory hole size: 0MBevsel, IRQ 18
Zone PFN ranges:s at 1000 [disabled] [size=256]
DMA 0x00000000 -> 0x00020000, non-prefetchable) [disabled] [size=16K]
Normal 0x00020000 -> 0x00020000, non-prefetchable) [disabled] [size=256K]
HighMem 0x00020000 -> 0x00020000e80100000 [disabled] [size=512K]
Movable zone start PFN for each nodeagement version 3
early_node_map[1] active PFN rangesEndpoint IRQ 0
0: 0x00000000 -> 0x00020000l Product Data
On node 0 totalpages: 131072essage Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable-
free_area_init_node: node 0, pgdat c0335654, node_mem_map c0363000
DMA zone: 1024 pages used for memmaprror Reporting
DMA zone: 0 pages reservedPower Budgeting
DMA zone: 130048 pages, LIFO batch:31
MMU: Allocated 1088 bytes of context maps for 255 contexts
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048
Kernel command line: root=/dev/ram rw mem=128M mem=512M ip=169.254.0.181:169.254.0.100:169.254.0
PID hash table entries: 2048 (order: 11, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
High memory: 0k
Memory: 512512k/524288k available (3168k kernel code, 11356k reserved, 128k data, 132k bss, 160)
Kernel virtual memory layout:
* 0xfffef000..0xfffff000 : fixmap
* 0xffc00000..0xffe00000 : highmem PTEs
* 0xffa00000..0xffc00000 : consistent mem
* 0xffa00000..0xffa00000 : early ioremap
* 0xe1000000..0xffa00000 : vmalloc & ioremap
SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
NR_IRQS:512
UIC0 (32 IRQ sources) at DCR 0xc0
UIC1 (32 IRQ sources) at DCR 0xd0
irq: irq 30 on host /interrupt-controller0 mapped to virtual irq 30
UIC2 (32 IRQ sources) at DCR 0xe0
irq: irq 10 on host /interrupt-controller0 mapped to virtual irq 16
UIC3 (32 IRQ sources) at DCR 0xf0
irq: irq 16 on host /interrupt-controller0 mapped to virtual irq 17
time_init: decrementer frequency = 800.000010 MHz
time_init: processor frequency = 800.000010 MHz
clocksource: timebase mult[500000] shift[22] registered
clockevent: decrementer mult[ccccccf7] shift[32] cpu[0]
Mount-cache hash table entries: 512
NET: Registered protocol family 16
irq: irq 23 on host /interrupt-controller2 mapped to virtual irq 23
256k L2-cache enabled
PCIE0: Checking link...
PCIE0: No device detected.
PCI host bridge /plb/pciex@d00000000 (primary) ranges:
MEM 0x0000000e00000000..0x0000000e7fffffff -> 0x0000000080000000
IO 0x0000000f80000000..0x0000000f8000ffff -> 0x0000000000000000
4xx PCI DMA offset set to 0x00000000
PCIE0: successfully set as root-complex
PCIE1: Checking link...
PCIE1: Device detected, waiting for link...
PCIE1: link is up !
PCI host bridge /plb/pciex@d20000000 (primary) ranges:
MEM 0x0000000e80000000..0x0000000effffffff -> 0x0000000080000000
IO 0x0000000f80010000..0x0000000f8001ffff -> 0x0000000000000000
4xx PCI DMA offset set to 0x00000000
PCIE1: successfully set as root-complex
PCI host bridge /plb/pci@c0ec00000 (primary) ranges:
MEM 0x0000000d80000000..0x0000000dffffffff -> 0x0000000080000000
IO 0x0000000c08000000..0x0000000c0800ffff -> 0x0000000000000000
4xx PCI DMA offset set to 0x00000000
PCI: Probing PCI hardware
PCI: Scanning bus 0000:40
pci 0000:40:00.0: found [aaa0:bed0] class 000604 header type 01
pci 0000:40:00.0: reg 10 32bit mmio: [0x000000-0x7fffffff]
pci 0000:40:00.0: calling pcibios_fixup_resources+0x0/0x220
pci 0000:40:00.0: calling fixup_ppc4xx_pci_bridge+0x0/0x154
PCI: Hiding 4xx host bridge resources 0000:40:00.0
pci 0000:40:00.0: calling quirk_resource_alignment+0x0/0x200
PCI: Fixups for bus 0000:40
pci 0000:40:00.0: scanning behind bridge, config 7f4140, pass 0
PCI: Scanning bus 0000:41
PCI: Fixups for bus 0000:41
pci 0000:40:00.0: bridge io port: [0x00-0xfff]
pci 0000:40:00.0: bridge 32bit mmio: [0x000000-0x0fffff]
pci 0000:40:00.0: bridge 64bit mmio pref: [0x000000-0x0fffff]
PCI: Bus scan for 0000:41 returning with max=41
pci 0000:40:00.0: scanning behind bridge, config 7f4140, pass 1
PCI: Bus scan for 0000:40 returning with max=7f
PCI: Scanning bus 0001:80
pci 0001:80:00.0: found [aaa1:bed1] class 000604 header type 01
pci 0001:80:00.0: reg 10 32bit mmio: [0x000000-0x7fffffff]
pci 0001:80:00.0: calling pcibios_fixup_resources+0x0/0x220
pci 0001:80:00.0: calling fixup_ppc4xx_pci_bridge+0x0/0x154
PCI: Hiding 4xx host bridge resources 0001:80:00.0
pci 0001:80:00.0: calling quirk_resource_alignment+0x0/0x200
PCI: Fixups for bus 0001:80
pci 0001:80:00.0: scanning behind bridge, config bf8180, pass 0
PCI: Scanning bus 0001:81
pci 0001:81:00.0: found [1000:0070] class 000107 header type 00
pci 0001:81:00.0: reg 10 io port: [0x00-0xff]
pci 0001:81:00.0: reg 14 64bit mmio: [0x000000-0x003fff]
pci 0001:81:00.0: reg 1c 64bit mmio: [0x000000-0x03ffff]
pci 0001:81:00.0: reg 30 32bit mmio: [0x000000-0x07ffff]
pci 0001:81:00.0: calling pcibios_fixup_resources+0x0/0x220
pci 0001:81:00.0: calling fixup_ppc4xx_pci_bridge+0x0/0x154
pci 0001:81:00.0: calling quirk_resource_alignment+0x0/0x200
pci 0001:81:00.0: supports D1 D2
PCI: Fixups for bus 0001:81
pci 0001:80:00.0: bridge io port: [0x00-0xfff]
irq: irq 16 on host /interrupt-controller3 mapped to virtual irq 18
PCI: Bus scan for 0001:81 returning with max=81
pci 0001:80:00.0: scanning behind bridge, config bf8180, pass 1
PCI: Bus scan for 0001:80 returning with max=bf
PCI: Scanning bus 0002:00
PCI: Fixups for bus 0002:00
PCI: Bus scan for 0002:00 returning with max=00
pci 0000:40:00.0: PCI bridge, secondary bus 0000:41
pci 0000:40:00.0: IO window: disabled
pci 0000:40:00.0: MEM window: disabled
pci 0000:40:00.0: PREFETCH window: disabled
pci 0001:81:00.0: BAR 6: got res [0xe80100000-0xe8017ffff] bus [0x80100000-0x8017ffff] flags 0x0
pci 0001:81:00.0: BAR 3: got res [0xe80000000-0xe8003ffff] bus [0x80000000-0x8003ffff] flags 0x4
pci 0001:81:00.0: BAR 3: moved to bus [0x80000000-0x8003ffff] flags 0x120204
pci 0001:81:00.0: BAR 1: got res [0xe80040000-0xe80043fff] bus [0x80040000-0x80043fff] flags 0x4
pci 0001:81:00.0: BAR 1: moved to bus [0x80040000-0x80043fff] flags 0x120204
pci 0001:81:00.0: BAR 0: got res [0xfffe1000-0xfffe10ff] bus [0x1000-0x10ff] flags 0x20020101
pci 0001:81:00.0: BAR 0: moved to bus [0x1000-0x10ff] flags 0x20101
pci 0001:80:00.0: PCI bridge, secondary bus 0001:81
pci 0001:80:00.0: IO window: 0x1000-0x1fff
pci 0001:80:00.0: MEM window: 0x80000000-0x800fffff
pci 0001:80:00.0: PREFETCH window: 0x80100000-0x801fffff
pci_bus 0000:40: resource 0 io: [0xfffc0000-0xfffcffff]
pci_bus 0000:40: resource 1 mem: [0xe00000000-0xe7fffffff]
pci_bus 0000:41: resource 0 mem: [0xfffc0000-0xfffc0fff]
pci_bus 0000:41: resource 1 mem: [0xd80000000-0xd800fffff]
pci_bus 0000:41: resource 2 mem: [0xd80000000-0xd800fffff]
pci_bus 0001:80: resource 0 io: [0xfffe0000-0xfffeffff]
pci_bus 0001:80: resource 1 mem: [0xe80000000-0xeffffffff]
pci_bus 0001:81: resource 0 io: [0xfffe1000-0xfffe1fff]
pci_bus 0001:81: resource 1 mem: [0xe80000000-0xe800fffff]
pci_bus 0001:81: resource 2 pref mem [0xe80100000-0xe801fffff]
pci_bus 0002:00: resource 0 io: [0x00-0xffff]
pci_bus 0002:00: resource 1 mem: [0xd80000000-0xdffffffff]
bio: create slab <bio-0> at 0
SCSI subsystem initialized
libata version 3.00 loaded.
NET: Registered protocol family 2
IP route cache hash table entries: 16384 (order: 4, 65536 bytes)
TCP established hash table entries: 65536 (order: 7, 524288 bytes)
Switched to high resolution mode on CPU 0
TCP bind hash table entries: 65536 (order: 6, 262144 bytes)
TCP: Hash tables configured (established 65536 bind 65536)
TCP reno registered
NET: Registered protocol family 1
Trying to unpack rootfs image as initramfs...
rootfs image is not initramfs (no cpio magic); looks like an initrd
Freeing initrd memory: 3343k freed
irq: irq 1 on host /interrupt-controller1 mapped to virtual irq 19
irq: irq 1 on host /interrupt-controller0 mapped to virtual irq 20
irq: irq 29 on host /interrupt-controller1 mapped to virtual irq 29
irq: irq 30 on host /interrupt-controller1 mapped to virtual irq 21
JFFS2 version 2.2. (NAND) �© 2001-2006 Red Hat, Inc.
msgmni has been set to 1008
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
io scheduler noop registered
io scheduler anticipatory registered (default)
io scheduler deadline registered
io scheduler cfq registered
pci 0000:40:00.0: calling quirk_cardbus_legacy+0x0/0x54
pci 0000:40:00.0: calling quirk_usb_early_handoff+0x0/0x738
pci 0001:80:00.0: calling quirk_cardbus_legacy+0x0/0x54
pci 0001:80:00.0: calling quirk_usb_early_handoff+0x0/0x738
pci 0001:81:00.0: calling quirk_cardbus_legacy+0x0/0x54
pci 0001:81:00.0: calling quirk_usb_early_handoff+0x0/0x738
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
serial8250.0: ttyS0 at MMIO 0x4ef600300 (irq = 19) is a 16550A
console [ttyS0] enabled
serial8250.0: ttyS1 at MMIO 0x4ef600400 (irq = 20) is a 16550A
serial8250.0: ttyS2 at MMIO 0x4ef600500 (irq = 29) is a 16550A
serial8250.0: ttyS3 at MMIO 0x4ef600600 (irq = 21) is a 16550A
4ef600300.serial: ttyS0 at MMIO 0x4ef600300 (irq = 19) is a 16550
4ef600400.serial: ttyS1 at MMIO 0x4ef600400 (irq = 20) is a 16550
4ef600500.serial: ttyS2 at MMIO 0x4ef600500 (irq = 29) is a 16550
4ef600600.serial: ttyS3 at MMIO 0x4ef600600 (irq = 21) is a 16550
brd: module loaded
Uniform Multi-Platform E-IDE driver
ide-gd driver 1.18
Loading iSCSI transport class v2.0-870.
PPC 4xx OCP EMAC driver, version 3.54
irq: irq 6 on host /interrupt-controller2 mapped to virtual irq 22
irq: irq 7 on host /interrupt-controller2 mapped to virtual irq 24
irq: irq 3 on host /interrupt-controller2 mapped to virtual irq 25
irq: irq 4 on host /interrupt-controller2 mapped to virtual irq 26
irq: irq 5 on host /interrupt-controller2 mapped to virtual irq 27
MAL v2 /plb/mcmal, 2 TX channels, 16 RX channels
ZMII /plb/opb/emac-zmii@ef600d00 initialized
RGMII /plb/opb/emac-rgmii@ef601500 initialized with MDIO support
TAH /plb/opb/emac-tah@ef601350 initialized
TAH /plb/opb/emac-tah@ef601450 initialized
irq: irq 16 on host /interrupt-controller2 mapped to virtual irq 28
irq: irq 20 on host /interrupt-controller2 mapped to virtual irq 31
/plb/opb/emac-rgmii@ef601500: input 0 in RGMII mode
eth0: EMAC-0 /plb/opb/ethernet@ef600e00, MAC 00:10:ec:01:02:b9
eth0: found Generic MII PHY (0x00)
irq: irq 17 on host /interrupt-controller2 mapped to virtual irq 32
irq: irq 21 on host /interrupt-controller2 mapped to virtual irq 33
/plb/opb/emac-rgmii@ef601500: input 1 in RGMII mode
eth1: EMAC-1 /plb/opb/ethernet@ef600f00, MAC 00:10:ec:81:02:b9
eth1: found Generic MII PHY (0x01)
4cc000000.nor_flash: Found 1 x16 devices at 0x0 in 16-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
4cc000000.nor_flash: CFI does not contain boot bank location. Assuming top.
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.
RedBoot partition parsing not available
Creating 7 MTD partitions on "4cc000000.nor_flash":
0x000000000000-0x0000001e0000 : "kernel"
0x0000001e0000-0x000000200000 : "dtb"
0x000000200000-0x000001600000 : "ramdisk"
0x000001600000-0x000001a00000 : "jffs2"
0x000001a00000-0x000003f60000 : "user"
0x000003f60000-0x000003fa0000 : "env"
0x000003fa0000-0x000004000000 : "u-boot"
i2c /dev entries driver
irq: irq 2 on host /interrupt-controller0 mapped to virtual irq 34
ibm-iic 4ef600700.i2c: using standard (100 kHz) mode
irq: irq 3 on host /interrupt-controller0 mapped to virtual irq 35
ibm-iic 4ef600800.i2c: using standard (100 kHz) mode
TCP cubic registered
NET: Registered protocol family 17
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
eth0: link is down
IP-Config: Complete:
device=eth0, addr=169.254.0.181, mask=255.255.255.0, gw=169.254.0.100,
host=tanosx, domain=, nis-domain=(none),
bootserver=169.254.0.100, rootserver=169.254.0.100, rootpath=
RAMDISK: gzip image found at block 0
eth0: link is up, 100 FDX, pause enabled
VFS: Mounted root (ext2 filesystem) on device 1:0.
Freeing unused kernel memory: 160k init
#
Using PowerPC 44x Platform machine description
Linux version 2.6.31 (bobe@lablinux) (gcc version 4.2.2) #65 Tue Oct 6 09:25:00 CDT 2009
Found initrd at 0xdfb09000:0xdfe4cc6e
Found legacy serial port 0 for /plb/opb/serial@ef600300
mem=4ef600300, taddr=4ef600300, irq=0, clk=6451612, speed=0
Found legacy serial port 1 for /plb/opb/serial@ef600400
mem=4ef600400, taddr=4ef600400, irq=0, clk=6451612, speed=0
Found legacy serial port 2 for /plb/opb/serial@ef600500
mem=4ef600500, taddr=4ef600500, irq=0, clk=6451612, speed=0
Found legacy serial port 3 for /plb/opb/serial@ef600600
mem=4ef600600, taddr=4ef600600, irq=0, clk=6451612, speed=0
Top of RAM: 0x20000000, Total RAM: 0x20000000
Memory hole size: 0MB
Zone PFN ranges:
DMA 0x00000000 -> 0x00020000
Normal 0x00020000 -> 0x00020000
HighMem 0x00020000 -> 0x00020000
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
0: 0x00000000 -> 0x00020000
On node 0 totalpages: 131072
free_area_init_node: node 0, pgdat c033d9fc, node_mem_map c036c000
DMA zone: 1024 pages used for memmap
DMA zone: 0 pages reserved
DMA zone: 130048 pages, LIFO batch:31
MMU: Allocated 1088 bytes of context maps for 255 contexts
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048
Kernel command line: root=/dev/ram rw mem=128M mem=512M ip=169.254.0.181:169.254.0.100:169.254.0.100:255.255.255.0:tanosx:eth0:off panic=1 console=ttyS0,57600
PID hash table entries: 2048 (order: 11, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
High memory: 0k
Memory: 512512k/524288k available (3200k kernel code, 11392k reserved, 132k data, 128k bss, 156k init)
Kernel virtual memory layout:
* 0xfffef000..0xfffff000 : fixmap
* 0xffc00000..0xffe00000 : highmem PTEs
* 0xffa00000..0xffc00000 : consistent mem
* 0xffa00000..0xffa00000 : early ioremap
* 0xe1000000..0xffa00000 : vmalloc & ioremap
SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
NR_IRQS:512
UIC0 (32 IRQ sources) at DCR 0xc0
UIC1 (32 IRQ sources) at DCR 0xd0
irq: irq 30 on host /interrupt-controller0 mapped to virtual irq 30
UIC2 (32 IRQ sources) at DCR 0xe0
irq: irq 10 on host /interrupt-controller0 mapped to virtual irq 16
UIC3 (32 IRQ sources) at DCR 0xf0
irq: irq 16 on host /interrupt-controller0 mapped to virtual irq 17
time_init: decrementer frequency = 800.000010 MHz
time_init: processor frequency = 800.000010 MHz
clocksource: timebase mult[500000] shift[22] registered
clockevent: decrementer mult[ccccccf7] shift[32] cpu[0]
Mount-cache hash table entries: 512
NET: Registered protocol family 16
irq: irq 23 on host /interrupt-controller2 mapped to virtual irq 23
256k L2-cache enabled
PCIE0: Checking link...
PCIE0: No device detected.
PCI host bridge /plb/pciex@d00000000 (primary) ranges:
MEM 0x0000000e00000000..0x0000000e7fffffff -> 0x0000000080000000
IO 0x0000000f80000000..0x0000000f8000ffff -> 0x0000000000000000
4xx PCI DMA offset set to 0x00000000
PCIE0: successfully set as root-complex
PCIE1: Checking link...
PCIE1: Device detected, waiting for link...
PCIE1: link is up !
PCI host bridge /plb/pciex@d20000000 (primary) ranges:
MEM 0x0000000e80000000..0x0000000effffffff -> 0x0000000080000000
IO 0x0000000f80010000..0x0000000f8001ffff -> 0x0000000000000000
4xx PCI DMA offset set to 0x00000000
PCIE1: successfully set as root-complex
PCI host bridge /plb/pci@c0ec00000 (primary) ranges:
MEM 0x0000000d80000000..0x0000000dffffffff -> 0x0000000080000000
IO 0x0000000c08000000..0x0000000c0800ffff -> 0x0000000000000000
4xx PCI DMA offset set to 0x00000000
PCI: Probing PCI hardware
PCI: Scanning bus 0000:40
pci 0000:40:00.0: found [aaa0:bed0] class 000604 header type 01
pci 0000:40:00.0: reg 10 32bit mmio: [0x000000-0x7fffffff]
pci 0000:40:00.0: calling pcibios_fixup_resources+0x0/0x220
pci 0000:40:00.0: calling fixup_ppc4xx_pci_bridge+0x0/0x154
PCI: Hiding 4xx host bridge resources 0000:40:00.0
pci 0000:40:00.0: calling quirk_resource_alignment+0x0/0x200
PCI: Fixups for bus 0000:40
pci 0000:40:00.0: scanning behind bridge, config 7f4140, pass 0
PCI: Scanning bus 0000:41
PCI: Fixups for bus 0000:41
pci 0000:40:00.0: bridge io port: [0x00-0xfff]
pci 0000:40:00.0: bridge 32bit mmio: [0x000000-0x0fffff]
pci 0000:40:00.0: bridge 64bit mmio pref: [0x000000-0x0fffff]
PCI: Bus scan for 0000:41 returning with max=41
pci 0000:40:00.0: scanning behind bridge, config 7f4140, pass 1
PCI: Bus scan for 0000:40 returning with max=7f
PCI: Scanning bus 0001:80
pci 0001:80:00.0: found [aaa1:bed1] class 000604 header type 01
pci 0001:80:00.0: reg 10 32bit mmio: [0x000000-0x7fffffff]
pci 0001:80:00.0: calling pcibios_fixup_resources+0x0/0x220
pci 0001:80:00.0: calling fixup_ppc4xx_pci_bridge+0x0/0x154
PCI: Hiding 4xx host bridge resources 0001:80:00.0
pci 0001:80:00.0: calling quirk_resource_alignment+0x0/0x200
PCI: Fixups for bus 0001:80
pci 0001:80:00.0: scanning behind bridge, config bf8180, pass 0
PCI: Scanning bus 0001:81
pci 0001:81:00.0: found [1000:0070] class 000107 header type 00
pci 0001:81:00.0: reg 10 io port: [0x00-0xff]
pci 0001:81:00.0: reg 14 64bit mmio: [0x000000-0x003fff]
pci 0001:81:00.0: reg 1c 64bit mmio: [0x000000-0x03ffff]
pci 0001:81:00.0: reg 30 32bit mmio: [0x000000-0x07ffff]
pci 0001:81:00.0: calling pcibios_fixup_resources+0x0/0x220
pci 0001:81:00.0: calling fixup_ppc4xx_pci_bridge+0x0/0x154
pci 0001:81:00.0: calling quirk_resource_alignment+0x0/0x200
pci 0001:81:00.0: supports D1 D2
PCI: Fixups for bus 0001:81
pci 0001:80:00.0: bridge io port: [0x00-0xfff]
irq: irq 16 on host /interrupt-controller3 mapped to virtual irq 18
PCI: Bus scan for 0001:81 returning with max=81
pci 0001:80:00.0: scanning behind bridge, config bf8180, pass 1
PCI: Bus scan for 0001:80 returning with max=bf
PCI: Scanning bus 0002:00
PCI: Fixups for bus 0002:00
PCI: Bus scan for 0002:00 returning with max=00
pci 0000:40:00.0: PCI bridge, secondary bus 0000:41
pci 0000:40:00.0: IO window: disabled
pci 0000:40:00.0: MEM window: disabled
pci 0000:40:00.0: PREFETCH window: disabled
pci 0001:81:00.0: BAR 6: got res [0xe80100000-0xe8017ffff] bus [0x80100000-0x8017ffff] flags 0x20027200
pci 0001:81:00.0: BAR 3: got res [0xe80000000-0xe8003ffff] bus [0x80000000-0x8003ffff] flags 0x20120204
pci 0001:81:00.0: BAR 3: moved to bus [0x80000000-0x8003ffff] flags 0x120204
pci 0001:81:00.0: BAR 1: got res [0xe80040000-0xe80043fff] bus [0x80040000-0x80043fff] flags 0x20120204
pci 0001:81:00.0: BAR 1: moved to bus [0x80040000-0x80043fff] flags 0x120204
pci 0001:81:00.0: BAR 0: got res [0xfffe1000-0xfffe10ff] bus [0x1000-0x10ff] flags 0x20020101
pci 0001:81:00.0: BAR 0: moved to bus [0x1000-0x10ff] flags 0x20101
pci 0001:80:00.0: PCI bridge, secondary bus 0001:81
pci 0001:80:00.0: IO window: 0x1000-0x1fff
pci 0001:80:00.0: MEM window: 0x80000000-0x800fffff
pci 0001:80:00.0: PREFETCH window: 0x80100000-0x801fffff
pci_bus 0000:40: resource 0 io: [0xfffc0000-0xfffcffff]
pci_bus 0000:40: resource 1 mem: [0xe00000000-0xe7fffffff]
pci_bus 0000:41: resource 0 mem: [0xfffc0000-0xfffc0fff]
pci_bus 0000:41: resource 1 mem: [0xd80000000-0xd800fffff]
pci_bus 0000:41: resource 2 mem: [0xd80000000-0xd800fffff]
pci_bus 0001:80: resource 0 io: [0xfffe0000-0xfffeffff]
pci_bus 0001:80: resource 1 mem: [0xe80000000-0xeffffffff]
pci_bus 0001:81: resource 0 io: [0xfffe1000-0xfffe1fff]
pci_bus 0001:81: resource 1 mem: [0xe80000000-0xe800fffff]
pci_bus 0001:81: resource 2 pref mem [0xe80100000-0xe801fffff]
pci_bus 0002:00: resource 0 io: [0x00-0xffff]
pci_bus 0002:00: resource 1 mem: [0xd80000000-0xdffffffff]
bio: create slab <bio-0> at 0
SCSI subsystem initialized
NET: Registered protocol family 2
IP route cache hash table entries: 16384 (order: 4, 65536 bytes)
TCP established hash table entries: 65536 (order: 7, 524288 bytes)
Switched to high resolution mode on CPU 0
TCP bind hash table entries: 65536 (order: 6, 262144 bytes)
TCP: Hash tables configured (established 65536 bind 65536)
TCP reno registered
NET: Registered protocol family 1
Trying to unpack rootfs image as initramfs...
rootfs image is not initramfs (no cpio magic); looks like an initrd
Freeing initrd memory: 3343k freed
irq: irq 1 on host /interrupt-controller1 mapped to virtual irq 19
irq: irq 1 on host /interrupt-controller0 mapped to virtual irq 20
irq: irq 29 on host /interrupt-controller1 mapped to virtual irq 29
irq: irq 30 on host /interrupt-controller1 mapped to virtual irq 21
JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 1008
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
io scheduler noop registered
io scheduler anticipatory registered (default)
io scheduler deadline registered
io scheduler cfq registered
pci 0000:40:00.0: calling quirk_cardbus_legacy+0x0/0x54
pci 0000:40:00.0: calling quirk_usb_early_handoff+0x0/0x738
pci 0001:80:00.0: calling quirk_cardbus_legacy+0x0/0x54
pci 0001:80:00.0: calling quirk_usb_early_handoff+0x0/0x738
pci 0001:81:00.0: calling quirk_cardbus_legacy+0x0/0x54
pci 0001:81:00.0: calling quirk_usb_early_handoff+0x0/0x738
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
serial8250.0: ttyS0 at MMIO 0x4ef600300 (irq = 19) is a 16550A
console [ttyS0] enabled
serial8250.0: ttyS1 at MMIO 0x4ef600400 (irq = 20) is a 16550A
serial8250.0: ttyS2 at MMIO 0x4ef600500 (irq = 29) is a 16550A
serial8250.0: ttyS3 at MMIO 0x4ef600600 (irq = 21) is a 16550A
4ef600300.serial: ttyS0 at MMIO 0x4ef600300 (irq = 19) is a 16550
4ef600400.serial: ttyS1 at MMIO 0x4ef600400 (irq = 20) is a 16550
4ef600500.serial: ttyS2 at MMIO 0x4ef600500 (irq = 29) is a 16550
4ef600600.serial: ttyS3 at MMIO 0x4ef600600 (irq = 21) is a 16550
brd: module loaded
Uniform Multi-Platform E-IDE driver
ide-gd driver 1.18
PPC 4xx OCP EMAC driver, version 3.54
irq: irq 6 on host /interrupt-controller2 mapped to virtual irq 22
irq: irq 7 on host /interrupt-controller2 mapped to virtual irq 24
irq: irq 3 on host /interrupt-controller2 mapped to virtual irq 25
irq: irq 4 on host /interrupt-controller2 mapped to virtual irq 26
irq: irq 5 on host /interrupt-controller2 mapped to virtual irq 27
MAL v2 /plb/mcmal, 2 TX channels, 16 RX channels
ZMII /plb/opb/emac-zmii@ef600d00 initialized
RGMII /plb/opb/emac-rgmii@ef601500 initialized with MDIO support
TAH /plb/opb/emac-tah@ef601350 initialized
TAH /plb/opb/emac-tah@ef601450 initialized
irq: irq 16 on host /interrupt-controller2 mapped to virtual irq 28
irq: irq 20 on host /interrupt-controller2 mapped to virtual irq 31
/plb/opb/emac-rgmii@ef601500: input 0 in RGMII mode
eth0: EMAC-0 /plb/opb/ethernet@ef600e00, MAC 00:10:ec:01:02:b9
eth0: found Generic MII PHY (0x00)
irq: irq 17 on host /interrupt-controller2 mapped to virtual irq 32
irq: irq 21 on host /interrupt-controller2 mapped to virtual irq 33
/plb/opb/emac-rgmii@ef601500: input 1 in RGMII mode
eth1: EMAC-1 /plb/opb/ethernet@ef600f00, MAC 00:10:ec:81:02:b9
eth1: found Generic MII PHY (0x01)
Fusion MPT base driver 3.04.10
Copyright (c) 1999-2008 LSI Corporation
Fusion MPT SPI Host driver 3.04.10
Fusion MPT FC Host driver 3.04.10
Fusion MPT SAS Host driver 3.04.10
Fusion MPT misc device (ioctl) driver 3.04.10
mptctl: Registered with Fusion MPT base driver
mptctl: /dev/mptctl @ (major,minor=10,220)
4cc000000.nor_flash: Found 1 x16 devices at 0x0 in 16-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
4cc000000.nor_flash: CFI does not contain boot bank location. Assuming top.
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.
RedBoot partition parsing not available
Creating 7 MTD partitions on "4cc000000.nor_flash":
0x000000000000-0x0000001e0000 : "kernel"
0x0000001e0000-0x000000200000 : "dtb"
0x000000200000-0x000001600000 : "ramdisk"
0x000001600000-0x000001a00000 : "jffs2"
0x000001a00000-0x000003f60000 : "user"
0x000003f60000-0x000003fa0000 : "env"
0x000003fa0000-0x000004000000 : "u-boot"
i2c /dev entries driver
irq: irq 2 on host /interrupt-controller0 mapped to virtual irq 34
ibm-iic 4ef600700.i2c: using standard (100 kHz) mode
irq: irq 3 on host /interrupt-controller0 mapped to virtual irq 35
ibm-iic 4ef600800.i2c: using standard (100 kHz) mode
TCP cubic registered
NET: Registered protocol family 17
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
eth0: link is down
eth0: link is up, 100 FDX, pause enabled
IP-Config: Complete:
device=eth0, addr=169.254.0.181, mask=255.255.255.0, gw=169.254.0.100,
host=tanosx, domain=, nis-domain=(none),
bootserver=169.254.0.100, rootserver=169.254.0.100, rootpath=
RAMDISK: gzip image found at block 0
VFS: Mounted root (ext2 filesystem) on device 1:0.
Freeing unused kernel memory: 156k init
^ permalink raw reply
* RE: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
From: Stephen Neuendorffer @ 2009-10-07 16:39 UTC (permalink / raw)
To: David Miller, grant.likely
Cc: sparclinux, sfr, devicetree-discuss, linuxppc-dev,
microblaze-uclinux
In-Reply-To: <20091007.002722.168292120.davem@davemloft.net>
> -----Original Message-----
> From:
devicetree-discuss-bounces+stephen.neuendorffer=3Dxilinx.com@lists.ozlabs.
org [mailto:devicetree-
> discuss-bounces+stephen.neuendorffer=3Dxilinx.com@lists.ozlabs.org] On
Behalf Of David Miller
> Sent: Wednesday, October 07, 2009 12:27 AM
> To: grant.likely@secretlab.ca
> Cc: sfr@canb.auug.org.au; devicetree-discuss@lists.ozlabs.org;
microblaze-uclinux@itee.uq.edu.au;
> sparclinux@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree
code
> =
> From: Grant Likely <grant.likely@secretlab.ca>
> Date: Tue, 6 Oct 2009 22:49:04 -0600
> =
> > Also, I'd like to take on responsibility for maintaining the cross-
> > architecture device tree code. If there are no objections, I'll
> > write a patch to add a device tree section to MAINTAINERS.
> =
> Feel free. And also feel free to add my:
> =
> Acked-by: David S. Miller <davem@davemloft.net>
> =
> to your patches.
> =
Thanks for doing this, Grant.... It's definitely needed.
Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Steve
This email and any attachments are intended for the sole use of the named r=
ecipient(s) and contain(s) confidential information that may be proprietary=
, privileged or copyrighted under applicable law. If you are not the intend=
ed recipient, do not read, copy, or forward this email message or any attac=
hments. Delete this email message and any attachments immediately.
^ permalink raw reply
* Re: [v7 PATCH 3/7]: x86: refactor x86 idle power management code and remove all instances of pm_idle.
From: Arun R Bharadwaj @ 2009-10-07 16:45 UTC (permalink / raw)
To: Peter Zijlstra
Cc: linux-arch, Gautham R Shenoy, Venkatesh Pallipadi, linux-kernel,
Paul Mackerras, Arun Bharadwaj, Ingo Molnar, linuxppc-dev
In-Reply-To: <1254926750.26976.253.camel@twins>
* Peter Zijlstra <a.p.zijlstra@chello.nl> [2009-10-07 16:45:50]:
> On Tue, 2009-10-06 at 21:01 +0530, Arun R Bharadwaj wrote:
> > +++ linux.trees.git/arch/x86/kernel/process.c
> > @@ -9,6 +9,7 @@
> > #include <linux/pm.h>
> > #include <linux/clockchips.h>
> > #include <linux/random.h>
> > +#include <linux/cpuidle.h>
> > #include <trace/events/power.h>
> > #include <asm/system.h>
> > #include <asm/apic.h>
> > @@ -244,12 +245,6 @@ int sys_vfork(struct pt_regs *regs)
> > unsigned long boot_option_idle_override = 0;
> > EXPORT_SYMBOL(boot_option_idle_override);
> >
> > -/*
> > - * Powermanagement idle function, if any..
> > - */
> > -void (*pm_idle)(void);
> > -EXPORT_SYMBOL(pm_idle);
> > -
> > #ifdef CONFIG_X86_32
> > /*
> > * This halt magic was a workaround for ancient floppy DMA
> > @@ -329,17 +324,15 @@ static void do_nothing(void *unused)
> > }
> >
> > /*
> > - * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
> > - * pm_idle and update to new pm_idle value. Required while changing pm_idle
> > - * handler on SMP systems.
> > + * cpu_idle_wait - Required while changing idle routine handler on SMP systems.
> > *
> > - * Caller must have changed pm_idle to the new value before the call. Old
> > - * pm_idle value will not be used by any CPU after the return of this function.
> > + * Caller must have changed idle routine to the new value before the call. Old
> > + * value will not be used by any CPU after the return of this function.
> > */
> > void cpu_idle_wait(void)
> > {
> > smp_mb();
> > - /* kick all the CPUs so that they exit out of pm_idle */
> > + /* kick all the CPUs so that they exit out of idle loop */
> > smp_call_function(do_nothing, NULL, 1);
> > }
> > EXPORT_SYMBOL_GPL(cpu_idle_wait);
> > @@ -518,15 +511,59 @@ static void c1e_idle(void)
> > default_idle();
> > }
> >
> > +static void (*local_idle)(void);
> > +DEFINE_PER_CPU(struct cpuidle_device, idle_devices);
> > +
> > +struct cpuidle_driver cpuidle_default_driver = {
> > + .name = "cpuidle_default",
> > +};
> > +
> > +static int local_idle_loop(struct cpuidle_device *dev, struct cpuidle_state *st)
> > +{
> > + ktime_t t1, t2;
> > + s64 diff;
> > + int ret;
> > +
> > + t1 = ktime_get();
> > + local_idle();
> > + t2 = ktime_get();
> > +
> > + diff = ktime_to_us(ktime_sub(t2, t1));
> > + if (diff > INT_MAX)
> > + diff = INT_MAX;
> > + ret = (int) diff;
> > +
> > + return ret;
> > +}
> > +
> > +static int setup_cpuidle_simple(void)
> > +{
> > + struct cpuidle_device *dev;
> > + int cpu;
> > +
> > + if (!cpuidle_curr_driver)
> > + cpuidle_register_driver(&cpuidle_default_driver);
> > +
> > + for_each_online_cpu(cpu) {
> > + dev = &per_cpu(idle_devices, cpu);
> > + dev->cpu = cpu;
> > + dev->states[0].enter = local_idle_loop;
> > + dev->state_count = 1;
> > + cpuidle_register_device(dev);
> > + }
> > + return 0;
> > +}
> > +device_initcall(setup_cpuidle_simple);
> > +
> > void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
> > {
> > #ifdef CONFIG_SMP
> > - if (pm_idle == poll_idle && smp_num_siblings > 1) {
> > + if (local_idle == poll_idle && smp_num_siblings > 1) {
> > printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
> > " performance may degrade.\n");
> > }
> > #endif
> > - if (pm_idle)
> > + if (local_idle)
> > return;
> >
> > if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
> > @@ -534,18 +571,20 @@ void __cpuinit select_idle_routine(const
> > * One CPU supports mwait => All CPUs supports mwait
> > */
> > printk(KERN_INFO "using mwait in idle threads.\n");
> > - pm_idle = mwait_idle;
> > + local_idle = mwait_idle;
> > } else if (check_c1e_idle(c)) {
> > printk(KERN_INFO "using C1E aware idle routine\n");
> > - pm_idle = c1e_idle;
> > + local_idle = c1e_idle;
> > } else
> > - pm_idle = default_idle;
> > + local_idle = default_idle;
> > +
> > + return;
> > }
> >
> > void __init init_c1e_mask(void)
> > {
> > /* If we're using c1e_idle, we need to allocate c1e_mask. */
> > - if (pm_idle == c1e_idle)
> > + if (local_idle == c1e_idle)
> > zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
> > }
> >
> > @@ -556,7 +595,7 @@ static int __init idle_setup(char *str)
> >
> > if (!strcmp(str, "poll")) {
> > printk("using polling idle threads.\n");
> > - pm_idle = poll_idle;
> > + local_idle = poll_idle;
> > } else if (!strcmp(str, "mwait"))
> > force_mwait = 1;
> > else if (!strcmp(str, "halt")) {
> > @@ -567,7 +606,7 @@ static int __init idle_setup(char *str)
> > * To continue to load the CPU idle driver, don't touch
> > * the boot_option_idle_override.
> > */
> > - pm_idle = default_idle;
> > + local_idle = default_idle;
> > idle_halt = 1;
> > return 0;
> > } else if (!strcmp(str, "nomwait")) {
>
>
> What guarantees that the cpuidle bits actually select this
> cpuidle_default driver when you do idle=poll?
>
When we do a idle=poll, it sets boot_option_idle_override = 1, which
is checked during cpuidle_register_device in acpi/processor_idle.c
So cpuidle devices are not even registered if this option is set.
But, in acpi/processor_core.c where cpuidle_register_driver happens,
this check is not made currently. So, I guess this check must be added
before we register acpi_idle driver.
> Also, cpuidle already has a poll loop in it, why duplicate that?
>
Suppose the arch doesnt have a poll loop of its own, it can use the
one provided by cpuidle. I have just retained this from the earlier
implementation.
--arun
^ permalink raw reply
* Re: Nested function in drivers/of/of_mdio.c
From: vb @ 2009-10-07 16:23 UTC (permalink / raw)
To: Grant Likely; +Cc: netdev, linuxppc, Andy Fleming, David S. Miller
In-Reply-To: <fa686aa40910070911x769d7d41u908fbcf6b0980962@mail.gmail.com>
Guys, are there other instances of nested C functions in the codebase
or was this the first attempt?
On Wed, Oct 7, 2009 at 9:11 AM, Grant Likely <grant.likely@secretlab.ca> wr=
ote:
> On Wed, Oct 7, 2009 at 9:15 AM, J=E9r=F4me Pouiller <jezz@sysmic.org> wro=
te:
>> Dear,
>>
>> I have a problem with commit 8bc487d150b939e69830c39322df4ee486efe381
>> in file drivers/of/of_mdio.c in function of_phy_find_device.
>>
>> As you see, this function define match() as a nested function. My
>> compiler (powerpc-e500-linux-gnu-gcc-3.4.1) raise an error during link
>> due to this nested definition:
>> =A0drivers/built-in.o(.text+0x5e2a4): In function `of_phy_find_device': =
/home/jezz/linux-next/drivers/of/of_mdio.c:107:
>> undefined reference to `__trampoline_setup'
>>
>> I am sure I could solve problem by rebuilding my toolchain.
>> Nevertheless, I think nested function definition is not perfectly
>> supported by all compilers. Also, I suggest to place function match()
>> outside of scope of of_phy_find_device as in following patch.
>
> I'm okay with that, but if you're moving code out of the file scope,
> then please rename the function to of_phy_match() to avoid global
> namespace conflicts.
>
> g.
>
>>
>> diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
>> index bacaa53..c7b2e26 100644
>> --- a/drivers/of/of_mdio.c
>> +++ b/drivers/of/of_mdio.c
>> @@ -97,6 +97,10 @@ int of_mdiobus_register(struct mii_bus *mdio, struct =
device_node *np)
>> =A0}
>> =A0EXPORT_SYMBOL(of_mdiobus_register);
>>
>> +static int match(struct device *dev, void *phy_np)
>> +{
>> + =A0 =A0 =A0 return dev_archdata_get_node(&dev->archdata) =3D=3D phy_np=
;
>> +}
>> =A0/**
>> =A0* of_phy_find_device - Give a PHY node, find the phy_device
>> =A0* @phy_np: Pointer to the phy's device tree node
>> @@ -106,11 +110,6 @@ EXPORT_SYMBOL(of_mdiobus_register);
>> =A0struct phy_device *of_phy_find_device(struct device_node *phy_np)
>> =A0{
>> =A0 =A0 =A0 =A0struct device *d;
>> - =A0 =A0 =A0 int match(struct device *dev, void *phy_np)
>> - =A0 =A0 =A0 {
>> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 return dev_archdata_get_node(&dev->archdat=
a) =3D=3D phy_np;
>> - =A0 =A0 =A0 }
>> -
>> =A0 =A0 =A0 =A0if (!phy_np)
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return NULL;
>>
>>
>> What do you think about it?
>>
>> Best regards,
>>
>> --
>> J=E9r=F4me Pouiller (jezz AT sysmic DOT org)
>>
>
>
>
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
* Re: SMU-base PowerMac and server_mode
From: Olof Johansson @ 2009-10-07 16:33 UTC (permalink / raw)
To: Romain Goyet; +Cc: linuxppc-dev
In-Reply-To: <8028e5750910070425v45a3e036p1444a8ee5937a4bb@mail.gmail.com>
On Wed, Oct 07, 2009 at 01:25:13PM +0200, Romain Goyet wrote:
> On Tue, Oct 6, 2009 at 6:07 PM, Olof Johansson <olof@lixom.net> wrote:
> > Yeah, I had one but I have since lost it. I suspect it was on the
> > drive of my second quad that I wiped before I sold it, thinking there
> > was nothing of value on it. :(
>
> Ha, that's too bad. Do you know if it might be online somewhere ? Maybe an
> idea of the right keywords to google ?
I searched for it, couldn't find any trace of it anywhere. I know I
based my little tool on some small smu example that came from Ben or
possibly Segher. I can't even find that any more. It's been a couple of
years since I last touched it. :(
-Olof
^ permalink raw reply
* Re: Nested function in drivers/of/of_mdio.c
From: Grant Likely @ 2009-10-07 16:11 UTC (permalink / raw)
To: Jérôme Pouiller; +Cc: netdev, linuxppc, Andy Fleming, David S. Miller
In-Reply-To: <200910071715.57249.jezz@sysmic.org>
On Wed, Oct 7, 2009 at 9:15 AM, J=E9r=F4me Pouiller <jezz@sysmic.org> wrote=
:
> Dear,
>
> I have a problem with commit 8bc487d150b939e69830c39322df4ee486efe381
> in file drivers/of/of_mdio.c in function of_phy_find_device.
>
> As you see, this function define match() as a nested function. My
> compiler (powerpc-e500-linux-gnu-gcc-3.4.1) raise an error during link
> due to this nested definition:
> =A0drivers/built-in.o(.text+0x5e2a4): In function `of_phy_find_device': /=
home/jezz/linux-next/drivers/of/of_mdio.c:107:
> undefined reference to `__trampoline_setup'
>
> I am sure I could solve problem by rebuilding my toolchain.
> Nevertheless, I think nested function definition is not perfectly
> supported by all compilers. Also, I suggest to place function match()
> outside of scope of of_phy_find_device as in following patch.
I'm okay with that, but if you're moving code out of the file scope,
then please rename the function to of_phy_match() to avoid global
namespace conflicts.
g.
>
> diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
> index bacaa53..c7b2e26 100644
> --- a/drivers/of/of_mdio.c
> +++ b/drivers/of/of_mdio.c
> @@ -97,6 +97,10 @@ int of_mdiobus_register(struct mii_bus *mdio, struct d=
evice_node *np)
> =A0}
> =A0EXPORT_SYMBOL(of_mdiobus_register);
>
> +static int match(struct device *dev, void *phy_np)
> +{
> + =A0 =A0 =A0 return dev_archdata_get_node(&dev->archdata) =3D=3D phy_np;
> +}
> =A0/**
> =A0* of_phy_find_device - Give a PHY node, find the phy_device
> =A0* @phy_np: Pointer to the phy's device tree node
> @@ -106,11 +110,6 @@ EXPORT_SYMBOL(of_mdiobus_register);
> =A0struct phy_device *of_phy_find_device(struct device_node *phy_np)
> =A0{
> =A0 =A0 =A0 =A0struct device *d;
> - =A0 =A0 =A0 int match(struct device *dev, void *phy_np)
> - =A0 =A0 =A0 {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 return dev_archdata_get_node(&dev->archdata=
) =3D=3D phy_np;
> - =A0 =A0 =A0 }
> -
> =A0 =A0 =A0 =A0if (!phy_np)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return NULL;
>
>
> What do you think about it?
>
> Best regards,
>
> --
> J=E9r=F4me Pouiller (jezz AT sysmic DOT org)
>
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Nested function in drivers/of/of_mdio.c
From: Jérôme Pouiller @ 2009-10-07 15:15 UTC (permalink / raw)
To: Grant Likely; +Cc: netdev, linuxppc, Andy Fleming, David S. Miller
Dear,
I have a problem with commit 8bc487d150b939e69830c39322df4ee486efe381=20
in file drivers/of/of_mdio.c in function of_phy_find_device.
As you see, this function define match() as a nested function. My=20
compiler (powerpc-e500-linux-gnu-gcc-3.4.1) raise an error during link=20
due to this nested definition:
drivers/built-in.o(.text+0x5e2a4): In function `of_phy_find_device': /hom=
e/jezz/linux-next/drivers/of/of_mdio.c:107:=20
undefined reference to `__trampoline_setup'
I am sure I could solve problem by rebuilding my toolchain.=20
Nevertheless, I think nested function definition is not perfectly=20
supported by all compilers. Also, I suggest to place function match()=20
outside of scope of of_phy_find_device as in following patch.
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index bacaa53..c7b2e26 100644
=2D-- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -97,6 +97,10 @@ int of_mdiobus_register(struct mii_bus *mdio, struct dev=
ice_node *np)
}
EXPORT_SYMBOL(of_mdiobus_register);
+static int match(struct device *dev, void *phy_np)
+{
+ return dev_archdata_get_node(&dev->archdata) =3D=3D phy_np;
+}
/**
* of_phy_find_device - Give a PHY node, find the phy_device
* @phy_np: Pointer to the phy's device tree node
@@ -106,11 +110,6 @@ EXPORT_SYMBOL(of_mdiobus_register);
struct phy_device *of_phy_find_device(struct device_node *phy_np)
{
struct device *d;
=2D int match(struct device *dev, void *phy_np)
=2D {
=2D return dev_archdata_get_node(&dev->archdata) =3D=3D phy_n=
p;
=2D }
=2D
if (!phy_np)
return NULL;
What do you think about it?
Best regards,
=2D-=20
J=E9r=F4me Pouiller (jezz AT sysmic DOT org)
^ permalink raw reply
* Re: [v7 PATCH 3/7]: x86: refactor x86 idle power management code and remove all instances of pm_idle.
From: Peter Zijlstra @ 2009-10-07 14:45 UTC (permalink / raw)
To: arun
Cc: linux-arch, Gautham R Shenoy, Venkatesh Pallipadi, linux-kernel,
Paul Mackerras, Ingo Molnar, linuxppc-dev
In-Reply-To: <20091006153126.GA7358@linux.vnet.ibm.com>
On Tue, 2009-10-06 at 21:01 +0530, Arun R Bharadwaj wrote:
> +++ linux.trees.git/arch/x86/kernel/process.c
> @@ -9,6 +9,7 @@
> #include <linux/pm.h>
> #include <linux/clockchips.h>
> #include <linux/random.h>
> +#include <linux/cpuidle.h>
> #include <trace/events/power.h>
> #include <asm/system.h>
> #include <asm/apic.h>
> @@ -244,12 +245,6 @@ int sys_vfork(struct pt_regs *regs)
> unsigned long boot_option_idle_override = 0;
> EXPORT_SYMBOL(boot_option_idle_override);
>
> -/*
> - * Powermanagement idle function, if any..
> - */
> -void (*pm_idle)(void);
> -EXPORT_SYMBOL(pm_idle);
> -
> #ifdef CONFIG_X86_32
> /*
> * This halt magic was a workaround for ancient floppy DMA
> @@ -329,17 +324,15 @@ static void do_nothing(void *unused)
> }
>
> /*
> - * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
> - * pm_idle and update to new pm_idle value. Required while changing pm_idle
> - * handler on SMP systems.
> + * cpu_idle_wait - Required while changing idle routine handler on SMP systems.
> *
> - * Caller must have changed pm_idle to the new value before the call. Old
> - * pm_idle value will not be used by any CPU after the return of this function.
> + * Caller must have changed idle routine to the new value before the call. Old
> + * value will not be used by any CPU after the return of this function.
> */
> void cpu_idle_wait(void)
> {
> smp_mb();
> - /* kick all the CPUs so that they exit out of pm_idle */
> + /* kick all the CPUs so that they exit out of idle loop */
> smp_call_function(do_nothing, NULL, 1);
> }
> EXPORT_SYMBOL_GPL(cpu_idle_wait);
> @@ -518,15 +511,59 @@ static void c1e_idle(void)
> default_idle();
> }
>
> +static void (*local_idle)(void);
> +DEFINE_PER_CPU(struct cpuidle_device, idle_devices);
> +
> +struct cpuidle_driver cpuidle_default_driver = {
> + .name = "cpuidle_default",
> +};
> +
> +static int local_idle_loop(struct cpuidle_device *dev, struct cpuidle_state *st)
> +{
> + ktime_t t1, t2;
> + s64 diff;
> + int ret;
> +
> + t1 = ktime_get();
> + local_idle();
> + t2 = ktime_get();
> +
> + diff = ktime_to_us(ktime_sub(t2, t1));
> + if (diff > INT_MAX)
> + diff = INT_MAX;
> + ret = (int) diff;
> +
> + return ret;
> +}
> +
> +static int setup_cpuidle_simple(void)
> +{
> + struct cpuidle_device *dev;
> + int cpu;
> +
> + if (!cpuidle_curr_driver)
> + cpuidle_register_driver(&cpuidle_default_driver);
> +
> + for_each_online_cpu(cpu) {
> + dev = &per_cpu(idle_devices, cpu);
> + dev->cpu = cpu;
> + dev->states[0].enter = local_idle_loop;
> + dev->state_count = 1;
> + cpuidle_register_device(dev);
> + }
> + return 0;
> +}
> +device_initcall(setup_cpuidle_simple);
> +
> void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
> {
> #ifdef CONFIG_SMP
> - if (pm_idle == poll_idle && smp_num_siblings > 1) {
> + if (local_idle == poll_idle && smp_num_siblings > 1) {
> printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
> " performance may degrade.\n");
> }
> #endif
> - if (pm_idle)
> + if (local_idle)
> return;
>
> if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
> @@ -534,18 +571,20 @@ void __cpuinit select_idle_routine(const
> * One CPU supports mwait => All CPUs supports mwait
> */
> printk(KERN_INFO "using mwait in idle threads.\n");
> - pm_idle = mwait_idle;
> + local_idle = mwait_idle;
> } else if (check_c1e_idle(c)) {
> printk(KERN_INFO "using C1E aware idle routine\n");
> - pm_idle = c1e_idle;
> + local_idle = c1e_idle;
> } else
> - pm_idle = default_idle;
> + local_idle = default_idle;
> +
> + return;
> }
>
> void __init init_c1e_mask(void)
> {
> /* If we're using c1e_idle, we need to allocate c1e_mask. */
> - if (pm_idle == c1e_idle)
> + if (local_idle == c1e_idle)
> zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
> }
>
> @@ -556,7 +595,7 @@ static int __init idle_setup(char *str)
>
> if (!strcmp(str, "poll")) {
> printk("using polling idle threads.\n");
> - pm_idle = poll_idle;
> + local_idle = poll_idle;
> } else if (!strcmp(str, "mwait"))
> force_mwait = 1;
> else if (!strcmp(str, "halt")) {
> @@ -567,7 +606,7 @@ static int __init idle_setup(char *str)
> * To continue to load the CPU idle driver, don't touch
> * the boot_option_idle_override.
> */
> - pm_idle = default_idle;
> + local_idle = default_idle;
> idle_halt = 1;
> return 0;
> } else if (!strcmp(str, "nomwait")) {
What guarantees that the cpuidle bits actually select this
cpuidle_default driver when you do idle=poll?
Also, cpuidle already has a poll loop in it, why duplicate that?
^ permalink raw reply
* Re: [microblaze-uclinux] Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
From: Michal Simek @ 2009-10-07 14:21 UTC (permalink / raw)
To: microblaze-uclinux
Cc: Stephen Rothwell, devicetree-discuss, Rob Landley, sparclinux,
linuxppc-dev, davem
In-Reply-To: <fa686aa40910070702j470785d2ka2621122a8e2f1fd@mail.gmail.com>
Grant Likely wrote:
> On Wed, Oct 7, 2009 at 1:09 AM, Rob Landley <rob@landley.net> wrote:
>> On Tuesday 06 October 2009 23:49:04 Grant Likely wrote:
>>> However, I've completely devoted to this work for at least the next
>>> two months, so there are plenty more patches to follow. Once I've
>>> got all the common code merged between Microblaze, PowerPC and Sparc
>>> I'll be fix the endian problems and making it easily usable by other
>>> architectures like ARM and MIPS. Lots of work to be done.
>> Is there any news on getting QEMU to parse a device tree to figure out what
>> hardware to emulate? (I.E. using the device tree code to let qemu provide
>> configurable board emulations instead of hardwiring them in C code?)
>
> Not that I have, but I expect that I will be hacking on QEMU as part
> of this work.
ok great. Just let us know - we will test it.
Thanks,
Michal
>
>> Also, what would be involved in getting x86 to (at least have the option to)
>> use the device tree stuff?
>
> It would be very easy once the endian issues are worked out since the
> device tree is just a data format to be parsed.
>
> g.
>
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
^ permalink raw reply
* Re: [microblaze-uclinux] Re: [RFC PATCH 05/12] of: add common header for flattened device tree representation
From: Michal Simek @ 2009-10-07 14:07 UTC (permalink / raw)
To: microblaze-uclinux; +Cc: sparclinux, devicetree-discuss, linuxppc-dev, davem
In-Reply-To: <fa686aa40910070638v16c1b811w4e5ecb61a9afd836@mail.gmail.com>
Grant Likely wrote:
> On Wed, Oct 7, 2009 at 6:14 AM, Michal Simek <monstr@monstr.eu> wrote:
>>
>> Stephen Rothwell wrote:
>>> Hi Grant,
>>>
>>> Just first obvious thing:
>>>
>>> On Tue, 06 Oct 2009 22:30:59 -0600 Grant Likely <grant.likely@secretlab.ca> wrote:
>>>> diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h
>>>> index 64e8b3a..5f461f0 100644
>>>> --- a/arch/microblaze/include/asm/prom.h
>>>> +++ b/arch/microblaze/include/asm/prom.h
>>>> @@ -17,20 +17,10 @@
>>>> #ifndef _ASM_MICROBLAZE_PROM_H
>>>> #define _ASM_MICROBLAZE_PROM_H
>>>> #ifdef __KERNEL__
>>>> -
>>>> -/* Definitions used by the flattened device tree */
>>>> -#define OF_DT_HEADER 0xd00dfeed /* marker */
>>> This is used in arch/microblaze/kernel/head.S, but you move its
>>> definition inside "#ifndef __ASSEMBLY__" below. You should probably
>>> replace the include of asm/prom.h in arch/microblaze/kernel/head.S with
>>> linux/of_fdt.h (assuming that the comment in there is correct).
>> yes, Stephen is right here. I created one patch (in attachment) which fixed it. I tested your
>> patches on Microblaze (noMMU and MMU) and I have no problem with compilation and simple boot-up
>> works for both versions too.
>>
>> With that my patch: Acked-by: Michal Simek <monstr@monstr.eu>
>
> Thanks. I'll merge your change with my patch so that bisect isn't broken.
if is possible to do it, please do it.
Thanks,
Michal
>
> g.
>
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
^ permalink raw reply
* Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
From: Grant Likely @ 2009-10-07 14:02 UTC (permalink / raw)
To: Rob Landley
Cc: Stephen Rothwell, monstr, devicetree-discuss, microblaze-uclinux,
sparclinux, linuxppc-dev, davem
In-Reply-To: <200910070209.59311.rob@landley.net>
On Wed, Oct 7, 2009 at 1:09 AM, Rob Landley <rob@landley.net> wrote:
> On Tuesday 06 October 2009 23:49:04 Grant Likely wrote:
>>
>> However, I've completely devoted to this work for at least the next
>> two months, so there are plenty more patches to follow. =A0Once I've
>> got all the common code merged between Microblaze, PowerPC and Sparc
>> I'll be fix the endian problems and making it easily usable by other
>> architectures like ARM and MIPS. =A0Lots of work to be done.
>
> Is there any news on getting QEMU to parse a device tree to figure out wh=
at
> hardware to emulate? =A0(I.E. using the device tree code to let qemu prov=
ide
> configurable board emulations instead of hardwiring them in C code?)
Not that I have, but I expect that I will be hacking on QEMU as part
of this work.
> Also, what would be involved in getting x86 to (at least have the option =
to)
> use the device tree stuff?
It would be very easy once the endian issues are worked out since the
device tree is just a data format to be parsed.
g.
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH v3] mpc5200: support for the MAN mpc5200 based board mucmc52
From: Grant Likely @ 2009-10-07 13:57 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linuxppc-dev, Heiko Schocher
In-Reply-To: <20091007094936.GE3177@pengutronix.de>
On Wed, Oct 7, 2009 at 3:49 AM, Wolfram Sang <w.sang@pengutronix.de> wrote:
> On Wed, Oct 07, 2009 at 08:40:37AM +0200, Heiko Schocher wrote:
>> - serial Console on PSC1
>> - 64MB SDRAM
>> - MTD CFI Flash
>> - Ethernet FEC
>> - IDE support
>>
>> Signed-off-by: Heiko Schocher <hs@denx.de>
>
> Sorry for finding things incrementally, but I think there is still one is=
sue
> left. Once this is sorted out, you could add my:
>
> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
>
[...]
>> + =A0 =A0 soc5200@f0000000 {
>> + =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
>> + =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <1>;
>> + =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5200-immr",
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "fsl,mpc5200b-=
immr";
>
> You should decide on the latter one only here.
Besides, the order is wrong. The exact version (mpc5200b) always
appears before the list of backward compatible values (the non-'b'
version). But Wolfram is right. The IMMR node of the mpc5200b is
*not* wholly backwards compatible with fsl,mpc5200-immr, so
'fsl,mpc5200-immr' should not be in the list. fsl,mpc5200-<blah> only
appears in the child nodes when the specific device truly is backwards
compatible. Compare your .dts file line-for-line with one of the
in-tree mpc5200b .dts files.
g.
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
From: Sam Creasey @ 2009-10-07 13:52 UTC (permalink / raw)
To: Julian Calaby
Cc: Sam Creasey, Stephen Rothwell, monstr, devicetree-discuss,
microblaze-uclinux, sparclinux, linuxppc-dev, davem
In-Reply-To: <646765f40910062218s19d540f9q14c9086bedd1d9da@mail.gmail.com>
On Wed, Oct 07, 2009 at 03:18:04PM +1000, Julian Calaby wrote:
> On Wed, Oct 7, 2009 at 14:49, Grant Likely <grant.likely@secretlab.ca> wrote:
> > On Tue, Oct 6, 2009 at 10:29 PM, Grant Likely <grant.likely@secretlab.ca> wrote:
> >>
> >> So here goes. I've begun the work to merge and clean up the OF device
> >> tree handling code and this is my first set of patches. Not fully
> >> tested yet, but I'm getting them out to the lists so that I can start
> >> responding to comments and collecting acks. This first batch isn't
> >> anything exciting, just a merge of common code
>
> Good work, for what it's worth, this all looks good to me.
>
> > However, I've completely devoted to this work for at least the next
> > two months, so there are plenty more patches to follow. Once I've
> > got all the common code merged between Microblaze, PowerPC and Sparc
> > I'll be fix the endian problems and making it easily usable by other
> > architectures like ARM and MIPS. Lots of work to be done.
>
> On the subject of merging code, I know that the SUN3 code in m68k uses
> a similar prom interface to the sparc32 code. (and I've also
> considered unifying that and ... well ... see above) Does anyone know
> if it has an OpenFirmware interface for it's devices? Is OF on SUN3
> even remotely useful? Does Linux on SUN3 even work with modern
> kernels?
Sun3 doesn't have OF, though I've got some dormant patches to add an
OF emulation layer to make it easier to reuse Sparc drivers on
Sun3... Never finished enough to submit, so it probably shouldn't
affect anything you're doing here.
As for recent kernels, I think 2.6.19 was the last sun3 I distributed
patches for, so modern might be pushing it...
-- Sam
^ permalink raw reply
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