* Re: [RFC PATCH v2 09/11] powerpc: gamecube/wii: flipper interrupt controller support
From: Segher Boessenkool @ 2009-12-01 18:35 UTC (permalink / raw)
To: Albert Herranz; +Cc: linuxppc-dev
In-Reply-To: <1259441037-15725-10-git-send-email-albert_herranz@yahoo.es>
> Add support for the interrupt controller included in the "Flipper"
> chipset of the Nintendo GameCube video game console.
> The same interrupt controller is also present in the "Hollywood"
> chipset
> of the Nintendo Wii.
>
> Signed-off-by: Albert Herranz <albert_herranz@yahoo.es>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
> ---
> v1 -> v2
> - Build always Flipper interrupt controller when GAMECUBE_COMMON and
> get rid of FLIPPER_PIC option. Suggestion by Grant Likely.
> - Use NO_IRQ instead of -1. Suggestion by Benjamin Herrenschmidt.
> - Write 0xffffffff instead of ~0 to clear interrupts.
> Suggestion by Segher Boessenkool.
> - Use __fls instead of open coded asm. Suggestion by Segher
> Boessenkool.
> - Use a write instead of a read/modify/write to ack interrupts.
> Suggestion by Segher Boessenkool and Benjamin Herrenschmidt.
> - Use name instead of typename for struct irq_chip.
> - Adapt to updated device tree.
>
> arch/powerpc/platforms/embedded6xx/Makefile | 1 +
> arch/powerpc/platforms/embedded6xx/flipper-pic.c | 263 +++++++++++
> +++++++++++
> arch/powerpc/platforms/embedded6xx/flipper-pic.h | 25 ++
> 3 files changed, 289 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/platforms/embedded6xx/flipper-pic.c
> create mode 100644 arch/powerpc/platforms/embedded6xx/flipper-pic.h
>
> diff --git a/arch/powerpc/platforms/embedded6xx/Makefile b/arch/
> powerpc/platforms/embedded6xx/Makefile
> index 0ab7492..b80f47c 100644
> --- a/arch/powerpc/platforms/embedded6xx/Makefile
> +++ b/arch/powerpc/platforms/embedded6xx/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_PPC_HOLLY) += holly.o
> obj-$(CONFIG_PPC_PRPMC2800) += prpmc2800.o
> obj-$(CONFIG_PPC_C2K) += c2k.o
> obj-$(CONFIG_USBGECKO_UDBG) += usbgecko_udbg.o
> +obj-$(CONFIG_GAMECUBE_COMMON) += flipper-pic.o
> diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/
> arch/powerpc/platforms/embedded6xx/flipper-pic.c
> new file mode 100644
> index 0000000..d596328
> --- /dev/null
> +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
> @@ -0,0 +1,263 @@
> +/*
> + * arch/powerpc/platforms/embedded6xx/flipper-pic.c
> + *
> + * Nintendo GameCube/Wii "Flipper" interrupt controller support.
> + * Copyright (C) 2004-2009 The GameCube Linux Team
> + * Copyright (C) 2007,2008,2009 Albert Herranz
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + */
> +#define DRV_MODULE_NAME "flipper-pic"
> +#define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/irq.h>
> +#include <linux/of.h>
> +#include <asm/io.h>
> +
> +#include "flipper-pic.h"
> +
> +#define FLIPPER_NR_IRQS 32
> +
> +/*
> + * Each interrupt has a corresponding bit in both
> + * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
> + *
> + * Enabling/disabling an interrupt line involves setting/clearing
> + * the corresponding bit in IMR.
> + * Except for the RSW interrupt, all interrupts get deasserted
> automatically
> + * when the source deasserts the interrupt.
> + */
> +#define FLIPPER_ICR 0x00
> +#define FLIPPER_ICR_RSS (1<<16) /* reset switch state */
> +
> +#define FLIPPER_IMR 0x04
> +
> +#define FLIPPER_RESET 0x24
> +
> +
> +/*
> + * IRQ chip hooks.
> + *
> + */
> +
> +static void flipper_pic_mask_and_ack(unsigned int virq)
> +{
> + int irq = virq_to_hw(virq);
> + void __iomem *io_base = get_irq_chip_data(virq);
> + u32 mask = 1 << irq;
> +
> + clrbits32(io_base + FLIPPER_IMR, mask);
> + /* this is at least needed for RSW */
> + out_be32(io_base + FLIPPER_ICR, mask);
> +}
> +
> +static void flipper_pic_ack(unsigned int virq)
> +{
> + int irq = virq_to_hw(virq);
> + void __iomem *io_base = get_irq_chip_data(virq);
> +
> + /* this is at least needed for RSW */
> + out_be32(io_base + FLIPPER_ICR, 1 << irq);
> +}
> +
> +static void flipper_pic_mask(unsigned int virq)
> +{
> + int irq = virq_to_hw(virq);
> + void __iomem *io_base = get_irq_chip_data(virq);
> +
> + clrbits32(io_base + FLIPPER_IMR, 1 << irq);
> +}
> +
> +static void flipper_pic_unmask(unsigned int virq)
> +{
> + int irq = virq_to_hw(virq);
> + void __iomem *io_base = get_irq_chip_data(virq);
> +
> + setbits32(io_base + FLIPPER_IMR, 1 << irq);
> +}
> +
> +
> +static struct irq_chip flipper_pic = {
> + .name = "flipper-pic",
> + .ack = flipper_pic_ack,
> + .mask_ack = flipper_pic_mask_and_ack,
> + .mask = flipper_pic_mask,
> + .unmask = flipper_pic_unmask,
> +};
> +
> +/*
> + * IRQ host hooks.
> + *
> + */
> +
> +static struct irq_host *flipper_irq_host;
> +
> +static int flipper_pic_map(struct irq_host *h, unsigned int virq,
> + irq_hw_number_t hwirq)
> +{
> + set_irq_chip_data(virq, h->host_data);
> + get_irq_desc(virq)->status |= IRQ_LEVEL;
> + set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq);
> + return 0;
> +}
> +
> +static void flipper_pic_unmap(struct irq_host *h, unsigned int irq)
> +{
> + set_irq_chip_data(irq, NULL);
> + set_irq_chip(irq, NULL);
> +}
> +
> +static int flipper_pic_match(struct irq_host *h, struct
> device_node *np)
> +{
> + return 1;
> +}
> +
> +
> +static struct irq_host_ops flipper_irq_host_ops = {
> + .map = flipper_pic_map,
> + .unmap = flipper_pic_unmap,
> + .match = flipper_pic_match,
> +};
> +
> +/*
> + * Platform hooks.
> + *
> + */
> +
> +static void __flipper_quiesce(void __iomem *io_base)
> +{
> + /* mask and ack all IRQs */
> + out_be32(io_base + FLIPPER_IMR, 0x00000000);
> + out_be32(io_base + FLIPPER_ICR, 0xffffffff);
> +}
> +
> +struct irq_host * __init flipper_pic_init(struct device_node *np)
> +{
> + struct device_node *pi;
> + struct irq_host *irq_host = NULL;
> + struct resource res;
> + void __iomem *io_base;
> + int retval;
> +
> + pi = of_get_parent(np);
> + if (!pi) {
> + pr_err("no parent found\n");
> + goto out;
> + }
> + if (!of_device_is_compatible(pi, "nintendo,flipper-pi")) {
> + pr_err("unexpected parent compatible\n");
> + goto out;
> + }
> +
> + retval = of_address_to_resource(pi, 0, &res);
> + if (retval) {
> + pr_err("no io memory range found\n");
> + goto out;
> + }
> + io_base = ioremap(res.start, resource_size(&res));
> +
> + pr_info("controller at 0x%08x mapped to 0x%p\n", res.start,
> io_base);
> +
> + __flipper_quiesce(io_base);
> +
> + irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, FLIPPER_NR_IRQS,
> + &flipper_irq_host_ops, -1);
> + if (!irq_host) {
> + pr_err("failed to allocate irq_host\n");
> + return NULL;
> + }
> +
> + irq_host->host_data = io_base;
> +
> +out:
> + return irq_host;
> +}
> +
> +unsigned int flipper_pic_get_irq(void)
> +{
> + void __iomem *io_base = flipper_irq_host->host_data;
> + int irq;
> + u32 irq_status;
> +
> + irq_status = in_be32(io_base + FLIPPER_ICR) &
> + in_be32(io_base + FLIPPER_IMR);
> + if (irq_status == 0)
> + return NO_IRQ; /* no more IRQs pending */
> +
> + irq = __ffs(irq_status);
> + return irq_linear_revmap(flipper_irq_host, irq);
> +}
> +
> +/*
> + * Probe function.
> + *
> + */
> +
> +void __init flipper_pic_probe(void)
> +{
> + struct device_node *np;
> +
> + np = of_find_compatible_node(NULL, NULL, "nintendo,flipper-pic");
> + BUG_ON(!np);
> +
> + flipper_irq_host = flipper_pic_init(np);
> + BUG_ON(!flipper_irq_host);
> +
> + irq_set_default_host(flipper_irq_host);
> +
> + of_node_put(np);
> +}
> +
> +/*
> + * Misc functions related to the flipper chipset.
> + *
> + */
> +
> +/**
> + * flipper_quiesce() - quiesce flipper irq controller
> + *
> + * Mask and ack all interrupt sources.
> + *
> + */
> +void flipper_quiesce(void)
> +{
> + void __iomem *io_base = flipper_irq_host->host_data;
> +
> + __flipper_quiesce(io_base);
> +}
> +
> +/*
> + * Resets the platform.
> + */
> +void flipper_platform_reset(void)
> +{
> + void __iomem *io_base;
> +
> + if (flipper_irq_host && flipper_irq_host->host_data) {
> + io_base = flipper_irq_host->host_data;
> + out_8(io_base + FLIPPER_RESET, 0x00);
> + }
> +}
> +
> +/*
> + * Returns non-zero if the reset button is pressed.
> + */
> +int flipper_is_reset_button_pressed(void)
> +{
> + void __iomem *io_base;
> + u32 icr;
> +
> + if (flipper_irq_host && flipper_irq_host->host_data) {
> + io_base = flipper_irq_host->host_data;
> + icr = in_be32(io_base + FLIPPER_ICR);
> + return !(icr & FLIPPER_ICR_RSS);
> + }
> + return 0;
> +}
> +
> diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.h b/
> arch/powerpc/platforms/embedded6xx/flipper-pic.h
> new file mode 100644
> index 0000000..e339186
> --- /dev/null
> +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.h
> @@ -0,0 +1,25 @@
> +/*
> + * arch/powerpc/platforms/embedded6xx/flipper-pic.h
> + *
> + * Nintendo GameCube/Wii "Flipper" interrupt controller support.
> + * Copyright (C) 2004-2009 The GameCube Linux Team
> + * Copyright (C) 2007,2008,2009 Albert Herranz
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + */
> +
> +#ifndef __FLIPPER_PIC_H
> +#define __FLIPPER_PIC_H
> +
> +unsigned int flipper_pic_get_irq(void);
> +void __init flipper_pic_probe(void);
> +
> +void flipper_quiesce(void);
> +void flipper_platform_reset(void);
> +int flipper_is_reset_button_pressed(void);
> +
> +#endif
> --
> 1.6.3.3
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 0/8 userland!] systemtap: Add initial support for ppc32
From: Jim Keniston @ 2009-12-01 19:13 UTC (permalink / raw)
To: avorontsov, ananth; +Cc: linuxppc-dev, systemtap
In-Reply-To: <20091127223251.GA17065@oksana.dev.rtsoft.ru>
On Sat, 2009-11-28 at 01:32 +0300, Anton Vorontsov wrote:
> Hi all,
>
> Here are some patches that add systemtap support for ppc32 machines.
>
> This is all pretty straightforward, though I didn't test it much,
> only run few 'hello world' taps and decided that it's good enough. ;-)
>
> I plan to test it more thoughtfully sometime next week, and fix missing
> things (if any). But so far I'm interested in the feedback on this
> initial support.
>
> Thanks!
>
> p.s. I though it would be a good idea to cc linuxppc-dev. At least
> kexec-tools guys tend to do it as well.
I think one thing that got missed was completing the support for ppc32
in tapset/powerpc/registers.stp (functions *_arg and [u_]register). A
lot of the 32-bit code is already in place, having been copied over from
the x86_64 version, but the _reg_offsets[] array and
_stp_get_register_by_offset() work only for 64-bit contexts. A comment
at the end of _stp_register_regs() suggests that you can get the correct
32-bit offsets by dividing the 64-bit offsets by 2; compare pt_regs
structs to verify.
I'm cc-ing Ananth, who did the original ppc64 work on this file.
The *_arg and [u_]register functions are described in the stapfuncs man
page (but not in the Language Reference doc).
testsuite/systemtap.context/num_args.tcl tests some of these functions
(or used to, at least).
Jim Keniston
^ permalink raw reply
* Re: [RFC PATCH v2 09/11] powerpc: gamecube/wii: flipper interrupt controller support
From: Albert Herranz @ 2009-12-01 19:48 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev
In-Reply-To: <A6D0F7F3-74DB-42BE-BC1D-4C251A75CB16@kernel.crashing.org>
Segher Boessenkool wrote:
>> Add support for the interrupt controller included in the "Flipper"
>> chipset of the Nintendo GameCube video game console.
>> The same interrupt controller is also present in the "Hollywood" chipset
>> of the Nintendo Wii.
>>
>> Signed-off-by: Albert Herranz <albert_herranz@yahoo.es>
> Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
>
>> ---
>> v1 -> v2
>> - Build always Flipper interrupt controller when GAMECUBE_COMMON and
>> get rid of FLIPPER_PIC option. Suggestion by Grant Likely.
>> - Use NO_IRQ instead of -1. Suggestion by Benjamin Herrenschmidt.
>> - Write 0xffffffff instead of ~0 to clear interrupts.
>> Suggestion by Segher Boessenkool.
>> - Use __fls instead of open coded asm. Suggestion by Segher Boessenkool.
>> - Use a write instead of a read/modify/write to ack interrupts.
>> Suggestion by Segher Boessenkool and Benjamin Herrenschmidt.
>> - Use name instead of typename for struct irq_chip.
>> - Adapt to updated device tree.
>>
>> arch/powerpc/platforms/embedded6xx/Makefile | 1 +
>> arch/powerpc/platforms/embedded6xx/flipper-pic.c | 263
>> ++++++++++++++++++++++
>> arch/powerpc/platforms/embedded6xx/flipper-pic.h | 25 ++
>> 3 files changed, 289 insertions(+), 0 deletions(-)
>> create mode 100644 arch/powerpc/platforms/embedded6xx/flipper-pic.c
>> create mode 100644 arch/powerpc/platforms/embedded6xx/flipper-pic.h
>>
>> diff --git a/arch/powerpc/platforms/embedded6xx/Makefile
>> b/arch/powerpc/platforms/embedded6xx/Makefile
>> index 0ab7492..b80f47c 100644
>> --- a/arch/powerpc/platforms/embedded6xx/Makefile
>> +++ b/arch/powerpc/platforms/embedded6xx/Makefile
>> @@ -8,3 +8,4 @@ obj-$(CONFIG_PPC_HOLLY) += holly.o
>> obj-$(CONFIG_PPC_PRPMC2800) += prpmc2800.o
>> obj-$(CONFIG_PPC_C2K) += c2k.o
>> obj-$(CONFIG_USBGECKO_UDBG) += usbgecko_udbg.o
>> +obj-$(CONFIG_GAMECUBE_COMMON) += flipper-pic.o
>> diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c
>> b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
>> new file mode 100644
>> index 0000000..d596328
>> --- /dev/null
>> +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
>> @@ -0,0 +1,263 @@
>> +/*
>> + * arch/powerpc/platforms/embedded6xx/flipper-pic.c
>> + *
>> + * Nintendo GameCube/Wii "Flipper" interrupt controller support.
>> + * Copyright (C) 2004-2009 The GameCube Linux Team
>> + * Copyright (C) 2007,2008,2009 Albert Herranz
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation; either version 2
>> + * of the License, or (at your option) any later version.
>> + *
>> + */
>> +#define DRV_MODULE_NAME "flipper-pic"
>> +#define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +#include <linux/irq.h>
>> +#include <linux/of.h>
>> +#include <asm/io.h>
>> +
>> +#include "flipper-pic.h"
>> +
>> +#define FLIPPER_NR_IRQS 32
>> +
>> +/*
>> + * Each interrupt has a corresponding bit in both
>> + * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
>> + *
>> + * Enabling/disabling an interrupt line involves setting/clearing
>> + * the corresponding bit in IMR.
>> + * Except for the RSW interrupt, all interrupts get deasserted
>> automatically
>> + * when the source deasserts the interrupt.
>> + */
>> +#define FLIPPER_ICR 0x00
>> +#define FLIPPER_ICR_RSS (1<<16) /* reset switch state */
>> +
>> +#define FLIPPER_IMR 0x04
>> +
>> +#define FLIPPER_RESET 0x24
>> +
>> +
>> +/*
>> + * IRQ chip hooks.
>> + *
>> + */
>> +
>> +static void flipper_pic_mask_and_ack(unsigned int virq)
>> +{
>> + int irq = virq_to_hw(virq);
>> + void __iomem *io_base = get_irq_chip_data(virq);
>> + u32 mask = 1 << irq;
>> +
>> + clrbits32(io_base + FLIPPER_IMR, mask);
>> + /* this is at least needed for RSW */
>> + out_be32(io_base + FLIPPER_ICR, mask);
>> +}
>> +
>> +static void flipper_pic_ack(unsigned int virq)
>> +{
>> + int irq = virq_to_hw(virq);
>> + void __iomem *io_base = get_irq_chip_data(virq);
>> +
>> + /* this is at least needed for RSW */
>> + out_be32(io_base + FLIPPER_ICR, 1 << irq);
>> +}
>> +
>> +static void flipper_pic_mask(unsigned int virq)
>> +{
>> + int irq = virq_to_hw(virq);
>> + void __iomem *io_base = get_irq_chip_data(virq);
>> +
>> + clrbits32(io_base + FLIPPER_IMR, 1 << irq);
>> +}
>> +
>> +static void flipper_pic_unmask(unsigned int virq)
>> +{
>> + int irq = virq_to_hw(virq);
>> + void __iomem *io_base = get_irq_chip_data(virq);
>> +
>> + setbits32(io_base + FLIPPER_IMR, 1 << irq);
>> +}
>> +
>> +
>> +static struct irq_chip flipper_pic = {
>> + .name = "flipper-pic",
>> + .ack = flipper_pic_ack,
>> + .mask_ack = flipper_pic_mask_and_ack,
>> + .mask = flipper_pic_mask,
>> + .unmask = flipper_pic_unmask,
>> +};
>> +
>> +/*
>> + * IRQ host hooks.
>> + *
>> + */
>> +
>> +static struct irq_host *flipper_irq_host;
>> +
>> +static int flipper_pic_map(struct irq_host *h, unsigned int virq,
>> + irq_hw_number_t hwirq)
>> +{
>> + set_irq_chip_data(virq, h->host_data);
>> + get_irq_desc(virq)->status |= IRQ_LEVEL;
>> + set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq);
>> + return 0;
>> +}
>> +
>> +static void flipper_pic_unmap(struct irq_host *h, unsigned int irq)
>> +{
>> + set_irq_chip_data(irq, NULL);
>> + set_irq_chip(irq, NULL);
>> +}
>> +
>> +static int flipper_pic_match(struct irq_host *h, struct device_node *np)
>> +{
>> + return 1;
>> +}
>> +
>> +
>> +static struct irq_host_ops flipper_irq_host_ops = {
>> + .map = flipper_pic_map,
>> + .unmap = flipper_pic_unmap,
>> + .match = flipper_pic_match,
>> +};
>> +
>> +/*
>> + * Platform hooks.
>> + *
>> + */
>> +
>> +static void __flipper_quiesce(void __iomem *io_base)
>> +{
>> + /* mask and ack all IRQs */
>> + out_be32(io_base + FLIPPER_IMR, 0x00000000);
>> + out_be32(io_base + FLIPPER_ICR, 0xffffffff);
>> +}
>> +
>> +struct irq_host * __init flipper_pic_init(struct device_node *np)
>> +{
>> + struct device_node *pi;
>> + struct irq_host *irq_host = NULL;
>> + struct resource res;
>> + void __iomem *io_base;
>> + int retval;
>> +
>> + pi = of_get_parent(np);
>> + if (!pi) {
>> + pr_err("no parent found\n");
>> + goto out;
>> + }
>> + if (!of_device_is_compatible(pi, "nintendo,flipper-pi")) {
>> + pr_err("unexpected parent compatible\n");
>> + goto out;
>> + }
>> +
>> + retval = of_address_to_resource(pi, 0, &res);
>> + if (retval) {
>> + pr_err("no io memory range found\n");
>> + goto out;
>> + }
>> + io_base = ioremap(res.start, resource_size(&res));
>> +
>> + pr_info("controller at 0x%08x mapped to 0x%p\n", res.start,
>> io_base);
>> +
>> + __flipper_quiesce(io_base);
>> +
>> + irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, FLIPPER_NR_IRQS,
>> + &flipper_irq_host_ops, -1);
This -1 should be NO_IRQ too.
I'll fix this in the next version.
>> + if (!irq_host) {
>> + pr_err("failed to allocate irq_host\n");
>> + return NULL;
>> + }
>> +
>> + irq_host->host_data = io_base;
>> +
>> +out:
>> + return irq_host;
>> +}
>> +
>> +unsigned int flipper_pic_get_irq(void)
>> +{
>> + void __iomem *io_base = flipper_irq_host->host_data;
>> + int irq;
>> + u32 irq_status;
>> +
>> + irq_status = in_be32(io_base + FLIPPER_ICR) &
>> + in_be32(io_base + FLIPPER_IMR);
>> + if (irq_status == 0)
>> + return NO_IRQ; /* no more IRQs pending */
>> +
>> + irq = __ffs(irq_status);
>> + return irq_linear_revmap(flipper_irq_host, irq);
>> +}
>> +
>> +/*
>> + * Probe function.
>> + *
>> + */
>> +
>> +void __init flipper_pic_probe(void)
>> +{
>> + struct device_node *np;
>> +
>> + np = of_find_compatible_node(NULL, NULL, "nintendo,flipper-pic");
>> + BUG_ON(!np);
>> +
>> + flipper_irq_host = flipper_pic_init(np);
>> + BUG_ON(!flipper_irq_host);
>> +
>> + irq_set_default_host(flipper_irq_host);
>> +
>> + of_node_put(np);
>> +}
>> +
>> +/*
>> + * Misc functions related to the flipper chipset.
>> + *
>> + */
>> +
>> +/**
>> + * flipper_quiesce() - quiesce flipper irq controller
>> + *
>> + * Mask and ack all interrupt sources.
>> + *
>> + */
>> +void flipper_quiesce(void)
>> +{
>> + void __iomem *io_base = flipper_irq_host->host_data;
>> +
>> + __flipper_quiesce(io_base);
>> +}
>> +
>> +/*
>> + * Resets the platform.
>> + */
>> +void flipper_platform_reset(void)
>> +{
>> + void __iomem *io_base;
>> +
>> + if (flipper_irq_host && flipper_irq_host->host_data) {
>> + io_base = flipper_irq_host->host_data;
>> + out_8(io_base + FLIPPER_RESET, 0x00);
>> + }
>> +}
>> +
>> +/*
>> + * Returns non-zero if the reset button is pressed.
>> + */
>> +int flipper_is_reset_button_pressed(void)
>> +{
>> + void __iomem *io_base;
>> + u32 icr;
>> +
>> + if (flipper_irq_host && flipper_irq_host->host_data) {
>> + io_base = flipper_irq_host->host_data;
>> + icr = in_be32(io_base + FLIPPER_ICR);
>> + return !(icr & FLIPPER_ICR_RSS);
>> + }
>> + return 0;
>> +}
>> +
>> diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.h
>> b/arch/powerpc/platforms/embedded6xx/flipper-pic.h
>> new file mode 100644
>> index 0000000..e339186
>> --- /dev/null
>> +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.h
>> @@ -0,0 +1,25 @@
>> +/*
>> + * arch/powerpc/platforms/embedded6xx/flipper-pic.h
>> + *
>> + * Nintendo GameCube/Wii "Flipper" interrupt controller support.
>> + * Copyright (C) 2004-2009 The GameCube Linux Team
>> + * Copyright (C) 2007,2008,2009 Albert Herranz
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation; either version 2
>> + * of the License, or (at your option) any later version.
>> + *
>> + */
>> +
>> +#ifndef __FLIPPER_PIC_H
>> +#define __FLIPPER_PIC_H
>> +
>> +unsigned int flipper_pic_get_irq(void);
>> +void __init flipper_pic_probe(void);
>> +
>> +void flipper_quiesce(void);
>> +void flipper_platform_reset(void);
>> +int flipper_is_reset_button_pressed(void);
>> +
>> +#endif
Cheers,
Albert
^ permalink raw reply
* Re: [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Andreas Schwab @ 2009-12-01 20:43 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: tj, linux-ide, linuxppc-dev, jeff
In-Reply-To: <20091201070834.6A840B7B63@ozlabs.org>
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
> This is a libata driver for the "macio" IDE controller used on most Apple
> PowerMac and PowerBooks. It's a libata equivalent of drivers/ide/ppc/pmac.c
Tried it on my iBook G4 and I got an oops during probing, in
pata_macio_common_init+0x378/0x614.
Andreas.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
^ permalink raw reply
* [PATCH 1/3] show_interrupts: use irq_chip::name if available
From: Peter Korsgaard @ 2009-12-01 20:48 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt
struct irq_chip::typename is going away (replaced by name). Use name if
set instead of typename in show_interrupt to make ease transition.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
---
arch/powerpc/kernel/irq.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index e5d1211..33e1130 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -203,7 +203,8 @@ int show_interrupts(struct seq_file *p, void *v)
seq_printf(p, "%10u ", kstat_irqs(i));
#endif /* CONFIG_SMP */
if (desc->chip)
- seq_printf(p, " %s ", desc->chip->typename);
+ seq_printf(p, " %s ", desc->chip->name ?
+ desc->chip->name : desc->chip->typename);
else
seq_puts(p, " None ");
seq_printf(p, "%s", (desc->status & IRQ_LEVEL) ? "Level " : "Edge ");
--
1.6.5
^ permalink raw reply related
* [PATCH 2/3] asm/gpio.h: support gpio_to_irq()
From: Peter Korsgaard @ 2009-12-01 20:48 UTC (permalink / raw)
To: linuxppc-dev, Anton Vorontsov
In-Reply-To: <1259700494-17869-1-git-send-email-jacmet@sunsite.dk>
gpiolib returns -ENXIO if struct gpio_chip::to_irq isn't set, so it's
safe to always call.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
---
arch/powerpc/include/asm/gpio.h | 5 +----
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h
index ea04632..38762ed 100644
--- a/arch/powerpc/include/asm/gpio.h
+++ b/arch/powerpc/include/asm/gpio.h
@@ -38,12 +38,9 @@ static inline int gpio_cansleep(unsigned int gpio)
return __gpio_cansleep(gpio);
}
-/*
- * Not implemented, yet.
- */
static inline int gpio_to_irq(unsigned int gpio)
{
- return -ENOSYS;
+ return __gpio_to_irq(gpio);
}
static inline int irq_to_gpio(unsigned int irq)
--
1.6.5
^ permalink raw reply related
* [PATCH 3/3] mpc8xxx_gpio: add interrupt support
From: Peter Korsgaard @ 2009-12-01 20:48 UTC (permalink / raw)
To: linuxppc-dev, Anton Vorontsov, Kumar Gala
In-Reply-To: <1259700494-17869-2-git-send-email-jacmet@sunsite.dk>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
---
arch/powerpc/sysdev/mpc8xxx_gpio.c | 147 ++++++++++++++++++++++++++++++++++++
1 files changed, 147 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c
index 103eace..b46f28b 100644
--- a/arch/powerpc/sysdev/mpc8xxx_gpio.c
+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c
@@ -15,6 +15,7 @@
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/gpio.h>
+#include <linux/irq.h>
#define MPC8XXX_GPIO_PINS 32
@@ -34,6 +35,7 @@ struct mpc8xxx_gpio_chip {
* open drain mode safely
*/
u32 data;
+ struct irq_host *irq;
};
static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
@@ -111,12 +113,136 @@ static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val
return 0;
}
+static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+{
+ struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
+
+ if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
+ return irq_create_mapping(mpc8xxx_gc->irq, offset);
+ else
+ return -ENXIO;
+}
+
+static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
+{
+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc);
+ struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+ unsigned int mask;
+
+ mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
+ if (mask)
+ generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
+ 32 - ffs(mask)));
+}
+
+static void mpc8xxx_irq_unmask(unsigned int virq)
+{
+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
+ struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+
+ setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq)));
+
+ spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+}
+
+static void mpc8xxx_irq_mask(unsigned int virq)
+{
+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
+ struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+
+ clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq)));
+
+ spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+}
+
+static void mpc8xxx_irq_ack(unsigned int virq)
+{
+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
+ struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+
+ out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(virq)));
+}
+
+static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
+{
+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
+ struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+ unsigned long flags;
+
+ switch (flow_type) {
+ case IRQ_TYPE_EDGE_FALLING:
+ spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+ setbits32(mm->regs + GPIO_ICR,
+ mpc8xxx_gpio2mask(virq_to_hw(virq)));
+ spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ break;
+
+ case IRQ_TYPE_EDGE_BOTH:
+ spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+ clrbits32(mm->regs + GPIO_ICR,
+ mpc8xxx_gpio2mask(virq_to_hw(virq)));
+ spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct irq_chip mpc8xxx_irq_chip = {
+ .name = "mpc8xxx-gpio",
+ .unmask = mpc8xxx_irq_unmask,
+ .mask = mpc8xxx_irq_mask,
+ .ack = mpc8xxx_irq_ack,
+ .set_type = mpc8xxx_irq_set_type,
+};
+
+static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ set_irq_chip_data(virq, h->host_data);
+ set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
+ set_irq_type(virq, IRQ_TYPE_NONE);
+
+ return 0;
+}
+
+static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct,
+ u32 *intspec, unsigned int intsize,
+ irq_hw_number_t *out_hwirq,
+ unsigned int *out_flags)
+
+{
+ /* interrupt sense values coming from the device tree equal either
+ * EDGE_FALLING or EDGE_BOTH
+ */
+ *out_hwirq = intspec[0];
+ *out_flags = intspec[1];
+
+ return 0;
+}
+
+static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
+ .map = mpc8xxx_gpio_irq_map,
+ .xlate = mpc8xxx_gpio_irq_xlate,
+};
+
static void __init mpc8xxx_add_controller(struct device_node *np)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc;
struct of_mm_gpio_chip *mm_gc;
struct of_gpio_chip *of_gc;
struct gpio_chip *gc;
+ unsigned hwirq;
int ret;
mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
@@ -138,11 +264,32 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
gc->direction_output = mpc8xxx_gpio_dir_out;
gc->get = mpc8xxx_gpio_get;
gc->set = mpc8xxx_gpio_set;
+ gc->to_irq = mpc8xxx_gpio_to_irq;
ret = of_mm_gpiochip_add(np, mm_gc);
if (ret)
goto err;
+ hwirq = irq_of_parse_and_map(np, 0);
+ if (hwirq == NO_IRQ)
+ goto skip_irq;
+
+ mpc8xxx_gc->irq =
+ irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS,
+ &mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS);
+ if (!mpc8xxx_gc->irq)
+ goto skip_irq;
+
+ mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
+
+ /* ack and mask all irqs */
+ out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
+ out_be32(mm_gc->regs + GPIO_IMR, 0);
+
+ set_irq_data(hwirq, mpc8xxx_gc);
+ set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
+
+skip_irq:
return;
err:
--
1.6.5
^ permalink raw reply related
* Re: [PATCH] ppc64: re-enable kexec to allow module loads with CONFIG_MODVERSIONS and CONFIG_RELOCATABLE turned on
From: Neil Horman @ 2009-12-01 21:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: paulus, nhorman
In-Reply-To: <20091119195216.GC11414@hmsreliant.think-freely.org>
>> Paul, Ben, given that Rusty hasn't come back with any opinion on this patch,
>do you
>> feel comfortable merging it via the ppc tree? Currently the earlyinit routine
>> is only compiled in and used for your arch, so I think its fairly benign.
>
>Sorry, I *did* track down the archives for linuxppc-dev, then find your post,
>then read your patch. But I didn't actually reply.
>
>Other than minor issues, there's one significant one: you shouldn't be trying
>to change rodata. It might work on PPC today, but it's poor form at least.
>
>How's this? Untested on ppc.
>
I'll try grab a ppc64 system and test this soon.
>Other changes:
>1) I also changed reloc_start to an array; this is a good idea for any
> linker-defined symbols so the compiler can't make assumptions about size.
Ok, I'll certainly trust your linker skill over mine :)
>2) local.h? How about module.h?
Seems good to me
>3) I don't think the extra ". = 0" is necessary.
Its not, I was just trying to be clear about where reloc_start was to be placed.
>4) ARCH_USES_RELOC_ENTRIES isn't clear enough for me; I prefer
> ARCH_RELOCATE_KCRCTAB.
Sounds good to me.
I'll test this as soon as I'm able
Thanks!
Neil
^ permalink raw reply
* Re: [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Benjamin Herrenschmidt @ 2009-12-01 22:34 UTC (permalink / raw)
To: Andreas Schwab; +Cc: tj, linux-ide, linuxppc-dev, jeff
In-Reply-To: <m2hbsazapo.fsf@igel.home>
On Tue, 2009-12-01 at 21:43 +0100, Andreas Schwab wrote:
> Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
>
> > This is a libata driver for the "macio" IDE controller used on most Apple
> > PowerMac and PowerBooks. It's a libata equivalent of drivers/ide/ppc/pmac.c
>
> Tried it on my iBook G4 and I got an oops during probing, in
> pata_macio_common_init+0x378/0x614.
Any chance you can send me the oops log ? (you have a digital
camera ? :-)
What model of ibook ? There's one here I could try on I think but it
might not be the same model.
Cheers,
Ben.
^ permalink raw reply
* EP440XS board boot problem(Note:similart to Sequoia)
From: Allan Wang @ 2009-12-01 22:38 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 1586 bytes --]
I resend my message since my last message has wrong coding.
I am new to the list. I am still newbie to embedded linux. I have bought an ep440xs board which is similar to sequoia board. u-boot is working. I am trying to make it run linux. I have the following problems and need your help. Thank you very much:
I am using linux kernel 2.6.30.4. I encounter 2 problems:
1. After console_init() is called inside start_kernel(), the console starts printing garbage like:
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
serial8250.0: ttyS0 at MMIO 0x1ef600300 (irq = 16) is a 16550A
������������������������������
����������������������������
���������������������������������
������������������������������
�����������������.
2. It pakics when mounting the root file system(NFS):
(gdb) bt
#0 panic (fmt=0xc0290e94 "VFS: Unable to mount root fs on %s")
at kernel/panic.c:70
#1 0xc02d8ce0 in mount_block_root (name=0xc0290de4 "/dev/root", flags=0x8001)
at init/do_mounts.c:272
#2 0xc02d9084 in prepare_namespace () at init/do_mounts.c:415
#3 0xc02d81ec in kernel_init (unused=<value optimized out>) at init/main.c:885
#4 0xc000de60 in kernel_thread ()
There is a patch for Sequoia board to delete /chosen part in sequoia.dts, is /chosen required?
Allan
[-- Attachment #2: Type: text/html, Size: 2096 bytes --]
^ permalink raw reply
* Re: [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Benjamin Herrenschmidt @ 2009-12-01 22:58 UTC (permalink / raw)
To: Andreas Schwab; +Cc: tj, linux-ide, linuxppc-dev, jeff
In-Reply-To: <m2hbsazapo.fsf@igel.home>
On Tue, 2009-12-01 at 21:43 +0100, Andreas Schwab wrote:
> Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
>
> > This is a libata driver for the "macio" IDE controller used on most Apple
> > PowerMac and PowerBooks. It's a libata equivalent of drivers/ide/ppc/pmac.c
>
> Tried it on my iBook G4 and I got an oops during probing, in
> pata_macio_common_init+0x378/0x614.
Bah, I know what it is ... a last minute cleanup that breaks the PCI
variants of the cell. I'll send a new patch later today along with
other fixes.
Cheers,
Ben.
^ permalink raw reply
* Re: EP440XS board boot problem(Note:similart to Sequoia)
From: Wolfgang Denk @ 2009-12-01 23:10 UTC (permalink / raw)
To: Allan Wang; +Cc: linuxppc-dev
In-Reply-To: <401793.31718.qm@web52903.mail.re2.yahoo.com>
Dear Allan Wang,
In message <401793.31718.qm@web52903.mail.re2.yahoo.com> you wrote:
>
> I am new to the list. I am still newbie to embedded linux. I have
> bought an ep440xs board which is similar to sequoia board. u-boot is
> working. I am trying to make it run linux. I have the following
> problems and need your help. Thank you very much:
Which exact version of U-Boot are you running on this board?
I guess this is a out-of-tree port, i. e. not part of the mainline
U-Boot repository - so are you sure that device tree support is
enabled in your version of U-Boot?
>
> I am using linux kernel 2.6.30.4. I encounter 2 problems:
> 1. After console_init() is called inside start_kernel(), the console starts printing garbage like:
> Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
> serial8250.0: ttyS0 at MMIO 0x1ef600300 (irq = 16) is a 16550A
> ������������������������������
...
What is your exact boot command?
Which boot arguments do you pass to the kernel?
What is ytour console baud rate in U-Boot, and what sort of "console="
boot argument do you pass to the Linux kernel?
What does your device tree look like?
> 2. It pakics when mounting the root file system(NFS):
> (gdb) bt
> #0 panic (fmt=0xc0290e94 "VFS: Unable to mount root fs on %s")
So what is the "%s" argument here? Which sort of root file system are
you trying to mount - NFS, ramdisk, UBIFS, ... ?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
"He only drinks when he gets depressed." "Why does he get depressed?"
"Sometimes it's because he hasn't had a drink."
- Terry Pratchett, _Men at Arms_
^ permalink raw reply
* Re: [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Benjamin Herrenschmidt @ 2009-12-01 23:19 UTC (permalink / raw)
To: Tejun Heo; +Cc: linux-ide, Holger Macht, linuxppc-dev, Jeff Garzik
In-Reply-To: <4B14CD22.4020806@kernel.org>
On Tue, 2009-12-01 at 17:00 +0900, Tejun Heo wrote:
> > +#define IDE_WAKEUP_DELAY (1*HZ)
>
> nitpick: In libata, it's common to use msecs for timing values so that
> might be a better option.
Yeah, that's cruft lifted from the old driver, I'll fix it.
> > +static const struct pata_macio_timing *pata_macio_find_timing(
> > + struct pata_macio_priv *priv,
> > + int mode)
> > +{
> > + int i = 0;
> > +
> > + while (priv->timings[i].mode > 0) {
> > + if (priv->timings[i].mode == mode)
> > + return &priv->timings[i];
> > + i++;
> > + }
> > + return NULL;
>
> Wouldn't for (i = 0; ...) look better?
Yeah, I suppose so :-)
> > +static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)
> > +{
> > + struct ata_port *ap = qc->ap;
> > + struct pata_macio_priv *priv = ap->private_data;
> > + struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
> > +
> > + dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
> > +
> > + writel((RUN << 16) | RUN, &dma_regs->control);
> > + /* Make sure it gets to the controller right now */
> > + (void)readl(&dma_regs->control);
>
> Is flushing necessary here? There's no ordering issue here, right?
That's also lifted pretty-much as-is from the old driver. Now I probably
wrote that part of the old driver too ages ago :-) I think I just want
to make sure the DMA starts asap and doesn't sit in some bridge write
posting queue for hundreds of cycles.
> > +static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)
> > +{
> > + struct ata_port *ap = qc->ap;
> > + struct pata_macio_priv *priv = ap->private_data;
> > + struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
> > +
> > + dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
> > +
> > + /* Stop the DMA engine and wait for it to full halt */
> > + writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
> > + while (readl(&dma_regs->status) & RUN)
> > + udelay(1);
>
> Heh... this is a scary looking loop. It would be great if the above
> loop can be capped somehow.
Yeah, again, lifted from the old driver. We do that sort of loops in
various other drivers that use those DBDMA channels and I don't think
ever saw the loop hang, so at least those HW aren't -that- broken but I
suppose a little timeout wouldn't hurt. Not sure what to do if we hit it
tho.
> > +static u8 pata_macio_bmdma_status(struct ata_port *ap)
> > +{
> > + struct pata_macio_priv *priv = ap->private_data;
> > + struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
> > + u32 dstat, rstat = ATA_DMA_INTR;
> > + unsigned long timeout = 0;
> > +
> > + dstat = readl(&dma_regs->status);
> > +
> > + dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);
> > +
> > + /* We have to things to deal with here:
> ^^
> two
Yup.
> > +/* port_start is when we allocate the DMA command list */
> > +static int pata_macio_port_start(struct ata_port *ap)
> > +{
> > + struct pata_macio_priv *priv = ap->private_data;
> > + struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
> > +
> > + if (dma_regs == NULL)
> > + return 0;
> > +
> > + /* Make sure DMA controller is stopped */
> > + writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
> > + while (readl(&dma_regs->status) & RUN)
> > + udelay(1);
>
> Hmmm.... this probably belongs to ->freeze() which is responsible for
> stopping any in-flight operations and masking IRQ and libata will call
> it during initialization before requesting IRQ, so you won't need to
> call it explicitly here.
Well, I'm not sure I really -need- the above thing. It's there mostly
for the sake of paranoia. I suppose in case the firmware left it in some
stange state. Anyway, will move to freeze.
> > +#ifdef CONFIG_PMAC_MEDIABAY
> > +static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
> > +{
> > + struct ata_host *host = macio_get_drvdata(mdev);
> > + struct ata_port *ap;
> > + struct ata_eh_info *ehi;
> > + struct ata_device *dev;
> > + unsigned long flags;
> > +
> > + if (!host)
> > + return;
> > + ap = host->ports[0];
> > + spin_lock_irqsave(ap->lock, flags);
> > + ehi = &ap->link.eh_info;
> > + if (mb_state == MB_CD) {
> > + ata_ehi_push_desc(ehi, "mediabay plug");
> > + ata_ehi_hotplugged(ehi);
> > + ata_port_freeze(ap);
> > + } else {
> > + ata_ehi_push_desc(ehi, "mediabay unplug");
> > + ata_for_each_dev(dev, &ap->link, ALL)
> > + dev->flags |= ATA_DFLAG_DETACH;
> > + ata_port_schedule_eh(ap);
>
> I think you'll need an ata_port_freeze() or abort() here because at
> this point the drive is already gone and all in-flight commands need
> to be failed right away. Holger, do you remember why
> ata_acpi_detach_device() is using ata_port_schedule_eh() instead? Was
> it because ata_port_freeze() might end up poking registers after
> hotunplug happened? ISTR reports where accessing any register there
> causing the whole system to lock up but then why can't it use
> ata_port_abort() instead?
I'll try. Which one ? freeze or abort tho ?
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Tejun Heo @ 2009-12-01 23:27 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linux-ide, Holger Macht, linuxppc-dev, Jeff Garzik
In-Reply-To: <1259709552.2076.1053.camel@pasglop>
Hello,
On 12/02/2009 08:19 AM, Benjamin Herrenschmidt wrote:
>> I think you'll need an ata_port_freeze() or abort() here because at
>> this point the drive is already gone and all in-flight commands need
>> to be failed right away. Holger, do you remember why
>> ata_acpi_detach_device() is using ata_port_schedule_eh() instead? Was
>> it because ata_port_freeze() might end up poking registers after
>> hotunplug happened? ISTR reports where accessing any register there
>> causing the whole system to lock up but then why can't it use
>> ata_port_abort() instead?
>
> I'll try. Which one ? freeze or abort tho ?
Conceptually freeze would be more approriate but the side effect is
that the port is frozen and EH will try to thaw it by resetting it.
So, abort would work better.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Benjamin Herrenschmidt @ 2009-12-01 23:35 UTC (permalink / raw)
To: Tejun Heo; +Cc: linux-ide, Holger Macht, linuxppc-dev, Jeff Garzik
In-Reply-To: <4B15A67C.2030102@kernel.org>
On Wed, 2009-12-02 at 08:27 +0900, Tejun Heo wrote:
> Conceptually freeze would be more approriate but the side effect is
> that the port is frozen and EH will try to thaw it by resetting it.
> So, abort would work better.
BTW. For a plug event, what should I do ? freeze is fine ? Or just
schedule eh ? Right now, when plugging I see an exception Emask 0x10
etc... message in the log when plugging which isn't totally nice :-)
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Tejun Heo @ 2009-12-01 23:44 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linux-ide, Holger Macht, linuxppc-dev, Jeff Garzik
In-Reply-To: <1259710543.2076.1054.camel@pasglop>
On 12/02/2009 08:35 AM, Benjamin Herrenschmidt wrote:
> On Wed, 2009-12-02 at 08:27 +0900, Tejun Heo wrote:
>> Conceptually freeze would be more approriate but the side effect is
>> that the port is frozen and EH will try to thaw it by resetting it.
>> So, abort would work better.
>
> BTW. For a plug event, what should I do ? freeze is fine ? Or just
> schedule eh ? Right now, when plugging I see an exception Emask 0x10
> etc... message in the log when plugging which isn't totally nice :-)
freeze() and please don't fight the EH messages from low level driver.
If it's too much, we need to update core layer but given the variety
of phy related bugs, I think we need those messages.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Benjamin Herrenschmidt @ 2009-12-02 0:00 UTC (permalink / raw)
To: Tejun Heo; +Cc: linux-ide, Holger Macht, linuxppc-dev, Jeff Garzik
In-Reply-To: <4B15AA4F.5040309@kernel.org>
On Wed, 2009-12-02 at 08:44 +0900, Tejun Heo wrote:
> > BTW. For a plug event, what should I do ? freeze is fine ? Or just
> > schedule eh ? Right now, when plugging I see an exception Emask 0x10
> > etc... message in the log when plugging which isn't totally nice :-)
>
> freeze() and please don't fight the EH messages from low level driver.
> If it's too much, we need to update core layer but given the variety
> of phy related bugs, I think we need those messages.
Eh, ok :-) No biggie.
Cheers,
Ben.
^ permalink raw reply
* Serial console under current qemu is still an issue.
From: Rob Landley @ 2009-12-02 0:13 UTC (permalink / raw)
To: linuxppc-dev
Last month I reported a serial console problem:
http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-October/076727.html
And bisected the problem to find the patch to revert that fixed it for me:
http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-October/077059.html
The bug still hasn't been fixed, but reverting the patch stopped working during
this developmpent series (because it no longer cleanly reverse applies).
Would anybody like to comment on this? I can provide a qemu-based test
environment if you'd like, it's easily reproducible...
Rob
--
Latency is more important than throughput. It's that simple. - Linus Torvalds
^ permalink raw reply
* [PATCH 1/5] powerpc/macio: Add devres support to macio_device
From: Benjamin Herrenschmidt @ 2009-12-02 0:36 UTC (permalink / raw)
To: linux-ide; +Cc: tj, linuxppc-dev, jeff
This adds some basic devres support. When enabled via macio_enable_devres()
resources requested by drivers will be automatically released.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/include/asm/macio.h | 2 +
drivers/macintosh/macio_asic.c | 47 +++++++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
--- linux-work.orig/arch/powerpc/include/asm/macio.h 2009-11-30 12:48:33.000000000 +1100
+++ linux-work/arch/powerpc/include/asm/macio.h 2009-11-30 14:16:55.000000000 +1100
@@ -78,6 +78,8 @@ static inline unsigned long macio_resour
return res->end - res->start + 1;
}
+extern int macio_enable_devres(struct macio_dev *dev);
+
extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
extern void macio_release_resource(struct macio_dev *dev, int resource_no);
extern int macio_request_resources(struct macio_dev *dev, const char *name);
Index: linux-work/drivers/macintosh/macio_asic.c
===================================================================
--- linux-work.orig/drivers/macintosh/macio_asic.c 2009-11-30 12:41:12.000000000 +1100
+++ linux-work/drivers/macintosh/macio_asic.c 2009-11-30 14:17:19.000000000 +1100
@@ -538,6 +538,42 @@ void macio_unregister_driver(struct maci
driver_unregister(&drv->driver);
}
+/* Managed MacIO resources */
+struct macio_devres {
+ u32 res_mask;
+};
+
+static void maciom_release(struct device *gendev, void *res)
+{
+ struct macio_dev *dev = to_macio_device(gendev);
+ struct macio_devres *dr = res;
+ int i, max;
+
+ max = min(dev->n_resources, 32);
+ for (i = 0; i < max; i++) {
+ if (dr->res_mask & (1 << i))
+ macio_release_resource(dev, i);
+ }
+}
+
+int macio_enable_devres(struct macio_dev *dev)
+{
+ struct macio_devres *dr;
+
+ dr = devres_find(&dev->ofdev.dev, maciom_release, NULL, NULL);
+ if (!dr) {
+ dr = devres_alloc(maciom_release, sizeof(*dr), GFP_KERNEL);
+ if (!dr)
+ return -ENOMEM;
+ }
+ return devres_get(&dev->ofdev.dev, dr, NULL, NULL) != NULL;
+}
+
+static struct macio_devres * find_macio_dr(struct macio_dev *dev)
+{
+ return devres_find(&dev->ofdev.dev, maciom_release, NULL, NULL);
+}
+
/**
* macio_request_resource - Request an MMIO resource
* @dev: pointer to the device holding the resource
@@ -555,6 +591,8 @@ void macio_unregister_driver(struct maci
int macio_request_resource(struct macio_dev *dev, int resource_no,
const char *name)
{
+ struct macio_devres *dr = find_macio_dr(dev);
+
if (macio_resource_len(dev, resource_no) == 0)
return 0;
@@ -562,6 +600,9 @@ int macio_request_resource(struct macio_
macio_resource_len(dev, resource_no),
name))
goto err_out;
+
+ if (dr && resource_no < 32)
+ dr->res_mask |= 1 << resource_no;
return 0;
@@ -582,10 +623,14 @@ err_out:
*/
void macio_release_resource(struct macio_dev *dev, int resource_no)
{
+ struct macio_devres *dr = find_macio_dr(dev);
+
if (macio_resource_len(dev, resource_no) == 0)
return;
release_mem_region(macio_resource_start(dev, resource_no),
macio_resource_len(dev, resource_no));
+ if (dr && resource_no < 32)
+ dr->res_mask &= ~(1 << resource_no);
}
/**
@@ -744,3 +789,5 @@ EXPORT_SYMBOL(macio_request_resource);
EXPORT_SYMBOL(macio_release_resource);
EXPORT_SYMBOL(macio_request_resources);
EXPORT_SYMBOL(macio_release_resources);
+EXPORT_SYMBOL(macio_enable_devres);
+
^ permalink raw reply
* [PATCH 2/5] powerpc/macio: Add dma_parms support to macio
From: Benjamin Herrenschmidt @ 2009-12-02 0:36 UTC (permalink / raw)
To: linux-ide; +Cc: tj, linuxppc-dev, jeff
This adds dma_parms to macio devices and initializes them with
default values. This will allow pata_macio to setup the appropriate
max segment size for the block layer.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/include/asm/macio.h | 1 +
drivers/macintosh/macio_asic.c | 5 +++++
2 files changed, 6 insertions(+)
--- linux-work.orig/arch/powerpc/include/asm/macio.h 2009-11-27 14:38:05.000000000 +1100
+++ linux-work/arch/powerpc/include/asm/macio.h 2009-11-27 14:38:20.000000000 +1100
@@ -39,6 +39,7 @@ struct macio_dev
struct macio_bus *bus; /* macio bus this device is on */
struct macio_dev *media_bay; /* Device is part of a media bay */
struct of_device ofdev;
+ struct device_dma_parameters dma_parms; /* ide needs that */
int n_resources;
struct resource resource[MACIO_DEV_COUNT_RESOURCES];
int n_interrupts;
Index: linux-work/drivers/macintosh/macio_asic.c
===================================================================
--- linux-work.orig/drivers/macintosh/macio_asic.c 2009-11-27 14:39:24.000000000 +1100
+++ linux-work/drivers/macintosh/macio_asic.c 2009-11-27 16:37:39.000000000 +1100
@@ -379,6 +379,11 @@ static struct macio_dev * macio_add_one_
dev->ofdev.dev.parent = parent;
dev->ofdev.dev.bus = &macio_bus_type;
dev->ofdev.dev.release = macio_release_dev;
+ dev->ofdev.dev.dma_parms = &dev->dma_parms;
+
+ /* Standard DMA paremeters */
+ dma_set_max_seg_size(&dev->ofdev.dev, 65536);
+ dma_set_seg_boundary(&dev->ofdev.dev, 0xffffffff);
#ifdef CONFIG_PCI
/* Set the DMA ops to the ones from the PCI device, this could be
^ permalink raw reply
* [PATCH 3/5] powerpc/macio: Rework hotplug media bay support
From: Benjamin Herrenschmidt @ 2009-12-02 0:36 UTC (permalink / raw)
To: linux-ide; +Cc: tj, linuxppc-dev, jeff
The hotplug mediabay has tendrils deep into drivers/ide code
which makes a libata port reather difficult. In addition it's
ugly and could be done better.
This reworks the interface between the mediabay and the rest
of the world so that:
- Any macio_driver can now have a mediabay_event callback
which will be called when that driver sits on a mediabay and
it's been either plugged or unplugged. The device type is
passed as an argument. We can now move all the IDE cruft
into the IDE driver itself
- A check_media_bay() function can be used to take a peek
at the type of device currently in the bay if any, a cleaner
variant of the previous function with the same name.
- A pair of lock/unlock functions are exposed to allow the
IDE driver to block the hotplug callbacks during the initial
setup and probing of the bay in order to avoid nasty race
conditions.
- The mediabay code no longer needs to spin on the status
register of the IDE interface when it detects an IDE device,
this is done just fine by the IDE code itself
Overall, less code, simpler, and allows for another driver
than our old drivers/ide based one.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2. Fix compile on 64-bit
arch/powerpc/include/asm/macio.h | 3
arch/powerpc/include/asm/mediabay.h | 29 +--
drivers/block/swim3.c | 39 +---
drivers/ide/pmac.c | 90 ++++++---
drivers/macintosh/mediabay.c | 328 +++++++++++++-----------------------
5 files changed, 213 insertions(+), 276 deletions(-)
--- linux-work.orig/arch/powerpc/include/asm/macio.h 2009-12-01 17:57:00.000000000 +1100
+++ linux-work/arch/powerpc/include/asm/macio.h 2009-12-01 18:00:28.000000000 +1100
@@ -134,6 +134,9 @@ struct macio_driver
int (*resume)(struct macio_dev* dev);
int (*shutdown)(struct macio_dev* dev);
+#ifdef CONFIG_PMAC_MEDIABAY
+ void (*mediabay_event)(struct macio_dev* dev, int mb_state);
+#endif
struct device_driver driver;
};
#define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
Index: linux-work/arch/powerpc/include/asm/mediabay.h
===================================================================
--- linux-work.orig/arch/powerpc/include/asm/mediabay.h 2009-12-01 17:57:00.000000000 +1100
+++ linux-work/arch/powerpc/include/asm/mediabay.h 2009-12-01 18:00:28.000000000 +1100
@@ -17,26 +17,31 @@
#define MB_POWER 6 /* media bay contains a Power device (???) */
#define MB_NO 7 /* media bay contains nothing */
-/* Number of bays in the machine or 0 */
-extern int media_bay_count;
+struct macio_dev;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
-#include <linux/ide.h>
+#ifdef CONFIG_PMAC_MEDIABAY
-int check_media_bay_by_base(unsigned long base, int what);
-/* called by IDE PMAC host driver to register IDE controller for media bay */
-int media_bay_set_ide_infos(struct device_node *which_bay, unsigned long base,
- int irq, ide_hwif_t *hwif);
-
-int check_media_bay(struct device_node *which_bay, int what);
+/* Check the content type of the bay, returns MB_NO if the bay is still
+ * transitionning
+ */
+extern int check_media_bay(struct macio_dev *bay);
+
+/* The ATA driver uses the calls below to temporarily hold on the
+ * media bay callbacks while initializing the interface
+ */
+extern void lock_media_bay(struct macio_dev *bay);
+extern void unlock_media_bay(struct macio_dev *bay);
#else
-static inline int check_media_bay(struct device_node *which_bay, int what)
+static inline int check_media_bay(struct macio_dev *bay)
{
- return -ENODEV;
+ return MB_NO;
}
+static inline void lock_media_bay(struct macio_dev *bay) { }
+static inline void unlock_media_bay(struct macio_dev *bay) { }
+
#endif
#endif /* __KERNEL__ */
Index: linux-work/drivers/macintosh/mediabay.c
===================================================================
--- linux-work.orig/drivers/macintosh/mediabay.c 2009-12-01 17:57:00.000000000 +1100
+++ linux-work/drivers/macintosh/mediabay.c 2009-12-01 18:00:28.000000000 +1100
@@ -33,15 +33,6 @@
#include <linux/adb.h>
#include <linux/pmu.h>
-
-#define MB_DEBUG
-
-#ifdef MB_DEBUG
-#define MBDBG(fmt, arg...) printk(KERN_INFO fmt , ## arg)
-#else
-#define MBDBG(fmt, arg...) do { } while (0)
-#endif
-
#define MB_FCR32(bay, r) ((bay)->base + ((r) >> 2))
#define MB_FCR8(bay, r) (((volatile u8 __iomem *)((bay)->base)) + (r))
@@ -76,28 +67,14 @@ struct media_bay_info {
int index;
int cached_gpio;
int sleeping;
+ int user_lock;
struct mutex lock;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- ide_hwif_t *cd_port;
- void __iomem *cd_base;
- int cd_irq;
- int cd_retry;
-#endif
-#if defined(CONFIG_BLK_DEV_IDE_PMAC)
- int cd_index;
-#endif
};
#define MAX_BAYS 2
static struct media_bay_info media_bays[MAX_BAYS];
-int media_bay_count = 0;
-
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
-/* check the busy bit in the media-bay ide interface
- (assumes the media-bay contains an ide device) */
-#define MB_IDE_READY(i) ((readb(media_bays[i].cd_base + 0x70) & 0x80) == 0)
-#endif
+static int media_bay_count = 0;
/*
* Wait that number of ms between each step in normal polling mode
@@ -130,21 +107,11 @@ int media_bay_count = 0;
/*
* Wait this many ticks after an IDE device (e.g. CD-ROM) is inserted
- * (or until the device is ready) before waiting for busy bit to disappear
+ * (or until the device is ready) before calling into the driver
*/
#define MB_IDE_WAIT 1000
/*
- * Timeout waiting for busy bit of an IDE device to go down
- */
-#define MB_IDE_TIMEOUT 5000
-
-/*
- * Max retries of the full power up/down sequence for an IDE device
- */
-#define MAX_CD_RETRIES 3
-
-/*
* States of a media bay
*/
enum {
@@ -153,7 +120,6 @@ enum {
mb_enabling_bay, /* enable bits set, waiting MB_RESET_DELAY */
mb_resetting, /* reset bit unset, waiting MB_SETUP_DELAY */
mb_ide_resetting, /* IDE reset bit unser, waiting MB_IDE_WAIT */
- mb_ide_waiting, /* Waiting for BUSY bit to go away until MB_IDE_TIMEOUT */
mb_up, /* Media bay full */
mb_powering_down /* Powering down (avoid too fast down/up) */
};
@@ -373,12 +339,12 @@ static inline void set_mb_power(struct m
if (onoff) {
bay->ops->power(bay, 1);
bay->state = mb_powering_up;
- MBDBG("mediabay%d: powering up\n", bay->index);
+ pr_debug("mediabay%d: powering up\n", bay->index);
} else {
/* Make sure everything is powered down & disabled */
bay->ops->power(bay, 0);
bay->state = mb_powering_down;
- MBDBG("mediabay%d: powering down\n", bay->index);
+ pr_debug("mediabay%d: powering down\n", bay->index);
}
bay->timer = msecs_to_jiffies(MB_POWER_DELAY);
}
@@ -387,107 +353,118 @@ static void poll_media_bay(struct media_
{
int id = bay->ops->content(bay);
- if (id == bay->last_value) {
- if (id != bay->content_id) {
- bay->value_count += msecs_to_jiffies(MB_POLL_DELAY);
- if (bay->value_count >= msecs_to_jiffies(MB_STABLE_DELAY)) {
- /* If the device type changes without going thru
- * "MB_NO", we force a pass by "MB_NO" to make sure
- * things are properly reset
- */
- if ((id != MB_NO) && (bay->content_id != MB_NO)) {
- id = MB_NO;
- MBDBG("mediabay%d: forcing MB_NO\n", bay->index);
- }
- MBDBG("mediabay%d: switching to %d\n", bay->index, id);
- set_mb_power(bay, id != MB_NO);
- bay->content_id = id;
- if (id == MB_NO) {
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- bay->cd_retry = 0;
-#endif
- printk(KERN_INFO "media bay %d is empty\n", bay->index);
- }
- }
- }
- } else {
+ static char *mb_content_types[] = {
+ "a floppy drive",
+ "a floppy drive",
+ "an unsuported audio device",
+ "an ATA device",
+ "an unsupported PCI device",
+ "an unknown device",
+ };
+
+ if (id != bay->last_value) {
bay->last_value = id;
bay->value_count = 0;
+ return;
}
-}
+ if (id == bay->content_id)
+ return;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
-int check_media_bay(struct device_node *which_bay, int what)
-{
- int i;
-
- for (i=0; i<media_bay_count; i++)
- if (media_bays[i].mdev && which_bay == media_bays[i].mdev->ofdev.node) {
- if ((what == media_bays[i].content_id) && media_bays[i].state == mb_up)
- return 0;
- media_bays[i].cd_index = -1;
- return -EINVAL;
+ bay->value_count += msecs_to_jiffies(MB_POLL_DELAY);
+ if (bay->value_count >= msecs_to_jiffies(MB_STABLE_DELAY)) {
+ /* If the device type changes without going thru
+ * "MB_NO", we force a pass by "MB_NO" to make sure
+ * things are properly reset
+ */
+ if ((id != MB_NO) && (bay->content_id != MB_NO)) {
+ id = MB_NO;
+ pr_debug("mediabay%d: forcing MB_NO\n", bay->index);
}
- return -ENODEV;
+ pr_debug("mediabay%d: switching to %d\n", bay->index, id);
+ set_mb_power(bay, id != MB_NO);
+ bay->content_id = id;
+ if (id >= MB_NO || id < 0)
+ printk(KERN_INFO "mediabay%d: Bay is now empty\n", bay->index);
+ else
+ printk(KERN_INFO "mediabay%d: Bay contains %s\n",
+ bay->index, mb_content_types[id]);
+ }
}
-EXPORT_SYMBOL(check_media_bay);
-int check_media_bay_by_base(unsigned long base, int what)
+int check_media_bay(struct macio_dev *baydev)
{
- int i;
+ struct media_bay_info* bay;
+ int id;
- for (i=0; i<media_bay_count; i++)
- if (media_bays[i].mdev && base == (unsigned long) media_bays[i].cd_base) {
- if ((what == media_bays[i].content_id) && media_bays[i].state == mb_up)
- return 0;
- media_bays[i].cd_index = -1;
- return -EINVAL;
- }
+ if (baydev == NULL)
+ return MB_NO;
- return -ENODEV;
+ /* This returns an instant snapshot, not locking, sine
+ * we may be called with the bay lock held. The resulting
+ * fuzzyness of the result if called at the wrong time is
+ * not actually a huge deal
+ */
+ bay = macio_get_drvdata(baydev);
+ if (bay == NULL)
+ return MB_NO;
+ id = bay->content_id;
+ if (bay->state != mb_up)
+ return MB_NO;
+ if (id == MB_FD1)
+ return MB_FD;
+ return id;
}
-EXPORT_SYMBOL_GPL(check_media_bay_by_base);
+EXPORT_SYMBOL_GPL(check_media_bay);
-int media_bay_set_ide_infos(struct device_node* which_bay, unsigned long base,
- int irq, ide_hwif_t *hwif)
+void lock_media_bay(struct macio_dev *baydev)
{
- int i;
+ struct media_bay_info* bay;
- for (i=0; i<media_bay_count; i++) {
- struct media_bay_info* bay = &media_bays[i];
+ if (baydev == NULL)
+ return;
+ bay = macio_get_drvdata(baydev);
+ if (bay == NULL)
+ return;
+ mutex_lock(&bay->lock);
+ bay->user_lock = 1;
+}
+EXPORT_SYMBOL_GPL(lock_media_bay);
- if (bay->mdev && which_bay == bay->mdev->ofdev.node) {
- int timeout = 5000, index = hwif->index;
-
- mutex_lock(&bay->lock);
-
- bay->cd_port = hwif;
- bay->cd_base = (void __iomem *) base;
- bay->cd_irq = irq;
-
- if ((MB_CD != bay->content_id) || bay->state != mb_up) {
- mutex_unlock(&bay->lock);
- return 0;
- }
- printk(KERN_DEBUG "Registered ide%d for media bay %d\n", index, i);
- do {
- if (MB_IDE_READY(i)) {
- bay->cd_index = index;
- mutex_unlock(&bay->lock);
- return 0;
- }
- mdelay(1);
- } while(--timeout);
- printk(KERN_DEBUG "Timeount waiting IDE in bay %d\n", i);
- mutex_unlock(&bay->lock);
- return -ENODEV;
- }
+void unlock_media_bay(struct macio_dev *baydev)
+{
+ struct media_bay_info* bay;
+
+ if (baydev == NULL)
+ return;
+ bay = macio_get_drvdata(baydev);
+ if (bay == NULL)
+ return;
+ if (bay->user_lock) {
+ bay->user_lock = 0;
+ mutex_unlock(&bay->lock);
}
+}
+EXPORT_SYMBOL_GPL(unlock_media_bay);
- return -ENODEV;
+static int mb_broadcast_hotplug(struct device *dev, void *data)
+{
+ struct media_bay_info* bay = data;
+ struct macio_dev *mdev;
+ struct macio_driver *drv;
+ int state;
+
+ if (dev->bus != &macio_bus_type)
+ return 0;
+
+ state = bay->state == mb_up ? bay->content_id : MB_NO;
+ if (state == MB_FD1)
+ state = MB_FD;
+ mdev = to_macio_device(dev);
+ drv = to_macio_driver(dev->driver);
+ if (dev->driver && drv->mediabay_event)
+ drv->mediabay_event(mdev, state);
+ return 0;
}
-EXPORT_SYMBOL_GPL(media_bay_set_ide_infos);
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
static void media_bay_step(int i)
{
@@ -497,8 +474,8 @@ static void media_bay_step(int i)
if (bay->state != mb_powering_down)
poll_media_bay(bay);
- /* If timer expired or polling IDE busy, run state machine */
- if ((bay->state != mb_ide_waiting) && (bay->timer != 0)) {
+ /* If timer expired run state machine */
+ if (bay->timer != 0) {
bay->timer -= msecs_to_jiffies(MB_POLL_DELAY);
if (bay->timer > 0)
return;
@@ -508,100 +485,50 @@ static void media_bay_step(int i)
switch(bay->state) {
case mb_powering_up:
if (bay->ops->setup_bus(bay, bay->last_value) < 0) {
- MBDBG("mediabay%d: device not supported (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: device not supported (kind:%d)\n",
+ i, bay->content_id);
set_mb_power(bay, 0);
break;
}
bay->timer = msecs_to_jiffies(MB_RESET_DELAY);
bay->state = mb_enabling_bay;
- MBDBG("mediabay%d: enabling (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: enabling (kind:%d)\n", i, bay->content_id);
break;
case mb_enabling_bay:
bay->ops->un_reset(bay);
bay->timer = msecs_to_jiffies(MB_SETUP_DELAY);
bay->state = mb_resetting;
- MBDBG("mediabay%d: waiting reset (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: releasing bay reset (kind:%d)\n",
+ i, bay->content_id);
break;
case mb_resetting:
if (bay->content_id != MB_CD) {
- MBDBG("mediabay%d: bay is up (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: bay is up (kind:%d)\n", i,
+ bay->content_id);
bay->state = mb_up;
+ device_for_each_child(&bay->mdev->ofdev.dev,
+ bay, mb_broadcast_hotplug);
break;
}
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- MBDBG("mediabay%d: waiting IDE reset (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: releasing ATA reset (kind:%d)\n",
+ i, bay->content_id);
bay->ops->un_reset_ide(bay);
bay->timer = msecs_to_jiffies(MB_IDE_WAIT);
bay->state = mb_ide_resetting;
-#else
- printk(KERN_DEBUG "media-bay %d is ide (not compiled in kernel)\n", i);
- set_mb_power(bay, 0);
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
break;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
+
case mb_ide_resetting:
- bay->timer = msecs_to_jiffies(MB_IDE_TIMEOUT);
- bay->state = mb_ide_waiting;
- MBDBG("mediabay%d: waiting IDE ready (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: bay is up (kind:%d)\n", i, bay->content_id);
+ bay->state = mb_up;
+ device_for_each_child(&bay->mdev->ofdev.dev,
+ bay, mb_broadcast_hotplug);
break;
- case mb_ide_waiting:
- if (bay->cd_base == NULL) {
- bay->timer = 0;
- bay->state = mb_up;
- MBDBG("mediabay%d: up before IDE init\n", i);
- break;
- } else if (MB_IDE_READY(i)) {
- bay->timer = 0;
- bay->state = mb_up;
- if (bay->cd_index < 0) {
- printk("mediabay %d, registering IDE...\n", i);
- pmu_suspend();
- ide_port_scan(bay->cd_port);
- if (bay->cd_port->present)
- bay->cd_index = bay->cd_port->index;
- pmu_resume();
- }
- if (bay->cd_index == -1) {
- /* We eventually do a retry */
- bay->cd_retry++;
- printk("IDE register error\n");
- set_mb_power(bay, 0);
- } else {
- printk(KERN_DEBUG "media-bay %d is ide%d\n", i, bay->cd_index);
- MBDBG("mediabay %d IDE ready\n", i);
- }
- break;
- } else if (bay->timer > 0)
- bay->timer -= msecs_to_jiffies(MB_POLL_DELAY);
- if (bay->timer <= 0) {
- printk("\nIDE Timeout in bay %d !, IDE state is: 0x%02x\n",
- i, readb(bay->cd_base + 0x70));
- MBDBG("mediabay%d: nIDE Timeout !\n", i);
- set_mb_power(bay, 0);
- bay->timer = 0;
- }
- break;
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
+
case mb_powering_down:
bay->state = mb_empty;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- if (bay->cd_index >= 0) {
- printk(KERN_DEBUG "Unregistering mb %d ide, index:%d\n", i,
- bay->cd_index);
- ide_port_unregister_devices(bay->cd_port);
- bay->cd_index = -1;
- }
- if (bay->cd_retry) {
- if (bay->cd_retry > MAX_CD_RETRIES) {
- /* Should add an error sound (sort of beep in dmasound) */
- printk("\nmedia-bay %d, IDE device badly inserted or unrecognised\n", i);
- } else {
- /* Force a new power down/up sequence */
- bay->content_id = MB_NO;
- }
- }
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
- MBDBG("mediabay%d: end of power down\n", i);
+ device_for_each_child(&bay->mdev->ofdev.dev,
+ bay, mb_broadcast_hotplug);
+ pr_debug("mediabay%d: end of power down\n", i);
break;
}
}
@@ -676,11 +603,6 @@ static int __devinit media_bay_attach(st
bay->last_value = bay->ops->content(bay);
bay->value_count = msecs_to_jiffies(MB_STABLE_DELAY);
bay->state = mb_empty;
- do {
- msleep(MB_POLL_DELAY);
- media_bay_step(i);
- } while((bay->state != mb_empty) &&
- (bay->state != mb_up));
/* Mark us ready by filling our mdev data */
macio_set_drvdata(mdev, bay);
@@ -725,7 +647,7 @@ static int media_bay_resume(struct macio
set_mb_power(bay, 0);
msleep(MB_POWER_DELAY);
if (bay->ops->content(bay) != bay->content_id) {
- printk("mediabay%d: content changed during sleep...\n", bay->index);
+ printk("mediabay%d: Content changed during sleep...\n", bay->index);
mutex_unlock(&bay->lock);
return 0;
}
@@ -733,9 +655,6 @@ static int media_bay_resume(struct macio
bay->last_value = bay->content_id;
bay->value_count = msecs_to_jiffies(MB_STABLE_DELAY);
bay->timer = msecs_to_jiffies(MB_POWER_DELAY);
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- bay->cd_retry = 0;
-#endif
do {
msleep(MB_POLL_DELAY);
media_bay_step(bay->index);
@@ -823,9 +742,6 @@ static int __init media_bay_init(void)
for (i=0; i<MAX_BAYS; i++) {
memset((char *)&media_bays[i], 0, sizeof(struct media_bay_info));
media_bays[i].content_id = -1;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- media_bays[i].cd_index = -1;
-#endif
}
if (!machine_is(powermac))
return 0;
Index: linux-work/drivers/ide/pmac.c
===================================================================
--- linux-work.orig/drivers/ide/pmac.c 2009-12-01 17:57:00.000000000 +1100
+++ linux-work/drivers/ide/pmac.c 2009-12-02 11:24:46.000000000 +1100
@@ -43,10 +43,7 @@
#include <asm/pmac_feature.h>
#include <asm/sections.h>
#include <asm/irq.h>
-
-#ifndef CONFIG_PPC64
#include <asm/mediabay.h>
-#endif
#define DRV_NAME "ide-pmac"
@@ -59,13 +56,14 @@ typedef struct pmac_ide_hwif {
int irq;
int kind;
int aapl_bus_id;
- unsigned mediabay : 1;
unsigned broken_dma : 1;
unsigned broken_dma_warn : 1;
struct device_node* node;
struct macio_dev *mdev;
u32 timings[4];
volatile u32 __iomem * *kauai_fcr;
+ ide_hwif_t *hwif;
+
/* Those fields are duplicating what is in hwif. We currently
* can't use the hwif ones because of some assumptions that are
* beeing done by the generic code about the kind of dma controller
@@ -854,6 +852,11 @@ sanitize_timings(pmac_ide_hwif_t *pmif)
pmif->timings[2] = pmif->timings[3] = value2;
}
+static int on_media_bay(pmac_ide_hwif_t *pmif)
+{
+ return pmif->mdev && pmif->mdev->media_bay != NULL;
+}
+
/* Suspend call back, should be called after the child devices
* have actually been suspended
*/
@@ -866,7 +869,7 @@ static int pmac_ide_do_suspend(pmac_ide_
disable_irq(pmif->irq);
/* The media bay will handle itself just fine */
- if (pmif->mediabay)
+ if (on_media_bay(pmif))
return 0;
/* Kauai has bus control FCRs directly here */
@@ -889,7 +892,7 @@ static int pmac_ide_do_suspend(pmac_ide_
static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
{
/* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
- if (!pmif->mediabay) {
+ if (!on_media_bay(pmif)) {
ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
msleep(10);
@@ -950,13 +953,11 @@ static void pmac_ide_init_dev(ide_drive_
pmac_ide_hwif_t *pmif =
(pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
- if (pmif->mediabay) {
-#ifdef CONFIG_PMAC_MEDIABAY
- if (check_media_bay_by_base(pmif->regbase, MB_CD) == 0) {
+ if (on_media_bay(pmif)) {
+ if (check_media_bay(pmif->mdev->media_bay) == MB_CD) {
drive->dev_flags &= ~IDE_DFLAG_NOPROBE;
return;
}
-#endif
drive->dev_flags |= IDE_DFLAG_NOPROBE;
}
}
@@ -1072,26 +1073,22 @@ static int __devinit pmac_ide_setup_devi
writel(KAUAI_FCR_UATA_MAGIC |
KAUAI_FCR_UATA_RESET_N |
KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
-
- pmif->mediabay = 0;
/* Make sure we have sane timings */
sanitize_timings(pmif);
+ /* If we are on a media bay, wait for it to settle and lock it */
+ lock_media_bay(pmif->mdev->media_bay);
+
host = ide_host_alloc(&d, hws, 1);
- if (host == NULL)
- return -ENOMEM;
- hwif = host->ports[0];
+ if (host == NULL) {
+ rc = -ENOMEM;
+ goto bail;
+ }
+ hwif = pmif->hwif = host->ports[0];
-#ifndef CONFIG_PPC64
- /* XXX FIXME: Media bay stuff need re-organizing */
- if (np->parent && np->parent->name
- && strcasecmp(np->parent->name, "media-bay") == 0) {
-#ifdef CONFIG_PMAC_MEDIABAY
- media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq,
- hwif);
-#endif /* CONFIG_PMAC_MEDIABAY */
- pmif->mediabay = 1;
+ if (on_media_bay(pmif)) {
+ /* Fixup bus ID for media bay */
if (!bidp)
pmif->aapl_bus_id = 1;
} else if (pmif->kind == controller_ohare) {
@@ -1100,9 +1097,7 @@ static int __devinit pmac_ide_setup_devi
* units, I keep the old way
*/
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
- } else
-#endif
- {
+ } else {
/* This is necessary to enable IDE when net-booting */
ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
@@ -1112,17 +1107,20 @@ static int __devinit pmac_ide_setup_devi
}
printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
- "bus ID %d%s, irq %d\n", model_name[pmif->kind],
- pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
- pmif->mediabay ? " (mediabay)" : "", hw->irq);
+ "bus ID %d%s, irq %d\n", model_name[pmif->kind],
+ pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
+ on_media_bay(pmif) ? " (mediabay)" : "", hw->irq);
rc = ide_host_register(host, &d, hws);
- if (rc) {
- ide_host_free(host);
- return rc;
- }
+ if (rc)
+ pmif->hwif = NULL;
- return 0;
+ unlock_media_bay(pmif->mdev->media_bay);
+
+ bail:
+ if (rc && host)
+ ide_host_free(host);
+ return rc;
}
static void __devinit pmac_ide_init_ports(struct ide_hw *hw, unsigned long base)
@@ -1362,6 +1360,25 @@ pmac_ide_pci_resume(struct pci_dev *pdev
return rc;
}
+#ifdef CONFIG_PMAC_MEDIABAY
+static void pmac_ide_macio_mb_event(struct macio_dev* mdev, int mb_state)
+{
+ pmac_ide_hwif_t *pmif =
+ (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
+
+ switch(mb_state) {
+ case MB_CD:
+ if (!pmif->hwif->present)
+ ide_port_scan(pmif->hwif);
+ break;
+ default:
+ if (pmif->hwif->present)
+ ide_port_unregister_devices(pmif->hwif);
+ }
+}
+#endif /* CONFIG_PMAC_MEDIABAY */
+
+
static struct of_device_id pmac_ide_macio_match[] =
{
{
@@ -1386,6 +1403,9 @@ static struct macio_driver pmac_ide_maci
.probe = pmac_ide_macio_attach,
.suspend = pmac_ide_macio_suspend,
.resume = pmac_ide_macio_resume,
+#ifdef CONFIG_PMAC_MEDIABAY
+ .mediabay_event = pmac_ide_macio_mb_event,
+#endif
};
static const struct pci_device_id pmac_ide_pci_match[] = {
Index: linux-work/drivers/block/swim3.c
===================================================================
--- linux-work.orig/drivers/block/swim3.c 2009-12-01 17:57:00.000000000 +1100
+++ linux-work/drivers/block/swim3.c 2009-12-01 18:00:28.000000000 +1100
@@ -200,7 +200,7 @@ struct floppy_state {
int ejected;
wait_queue_head_t wait;
int wanted;
- struct device_node* media_bay; /* NULL when not in bay */
+ struct macio_dev *mdev;
char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)];
};
@@ -303,14 +303,13 @@ static int swim3_readbit(struct floppy_s
static void do_fd_request(struct request_queue * q)
{
int i;
- for(i=0;i<floppy_count;i++)
- {
-#ifdef CONFIG_PMAC_MEDIABAY
- if (floppy_states[i].media_bay &&
- check_media_bay(floppy_states[i].media_bay, MB_FD))
+
+ for(i=0; i<floppy_count; i++) {
+ struct floppy_state *fs = &floppy_states[i];
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
continue;
-#endif /* CONFIG_PMAC_MEDIABAY */
- start_request(&floppy_states[i]);
+ start_request(fs);
}
}
@@ -849,10 +848,9 @@ static int floppy_ioctl(struct block_dev
if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))
return -EPERM;
-#ifdef CONFIG_PMAC_MEDIABAY
- if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
return -ENXIO;
-#endif
switch (cmd) {
case FDEJECT:
@@ -876,10 +874,9 @@ static int floppy_open(struct block_devi
int n, err = 0;
if (fs->ref_count == 0) {
-#ifdef CONFIG_PMAC_MEDIABAY
- if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
return -ENXIO;
-#endif
out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2);
out_8(&sw->control_bic, 0xff);
out_8(&sw->mode, 0x95);
@@ -963,10 +960,9 @@ static int floppy_revalidate(struct gend
struct swim3 __iomem *sw;
int ret, n;
-#ifdef CONFIG_PMAC_MEDIABAY
- if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
return -ENXIO;
-#endif
sw = fs->swim3;
grab_drive(fs, revalidating, 0);
@@ -1009,7 +1005,6 @@ static const struct block_device_operati
static int swim3_add_device(struct macio_dev *mdev, int index)
{
struct device_node *swim = mdev->ofdev.node;
- struct device_node *mediabay;
struct floppy_state *fs = &floppy_states[index];
int rc = -EBUSY;
@@ -1036,9 +1031,7 @@ static int swim3_add_device(struct macio
}
dev_set_drvdata(&mdev->ofdev.dev, fs);
- mediabay = (strcasecmp(swim->parent->type, "media-bay") == 0) ?
- swim->parent : NULL;
- if (mediabay == NULL)
+ if (mdev->media_bay == NULL)
pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1);
memset(fs, 0, sizeof(*fs));
@@ -1068,7 +1061,7 @@ static int swim3_add_device(struct macio
fs->secpercyl = 36;
fs->secpertrack = 18;
fs->total_secs = 2880;
- fs->media_bay = mediabay;
+ fs->mdev = mdev;
init_waitqueue_head(&fs->wait);
fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space);
@@ -1093,7 +1086,7 @@ static int swim3_add_device(struct macio
init_timer(&fs->timeout);
printk(KERN_INFO "fd%d: SWIM3 floppy controller %s\n", floppy_count,
- mediabay ? "in media bay" : "");
+ mdev->media_bay ? "in media bay" : "");
return 0;
^ permalink raw reply
* [PATCH 4/5] libata/sff: Use ops->bmdma_stop instead of ata_bmdma_stop()
From: Benjamin Herrenschmidt @ 2009-12-02 0:36 UTC (permalink / raw)
To: linux-ide; +Cc: tj, linuxppc-dev, jeff
In libata-sff, ata_sff_post_internal_cmd() directly calls ata_bmdma_stop()
instead of ap->ops->bmdma_stop(). This can be a problem for controllers
that use their own bmdma_stop for which the generic sff one isn't suitable
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
drivers/ata/libata-sff.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- linux-work.orig/drivers/ata/libata-sff.c 2009-12-01 17:48:27.000000000 +1100
+++ linux-work/drivers/ata/libata-sff.c 2009-12-01 17:48:48.000000000 +1100
@@ -2384,7 +2384,7 @@ void ata_sff_post_internal_cmd(struct at
ap->hsm_task_state = HSM_ST_IDLE;
if (ap->ioaddr.bmdma_addr)
- ata_bmdma_stop(qc);
+ ap->ops->bmdma_stop(qc);
spin_unlock_irqrestore(ap->lock, flags);
}
^ permalink raw reply
* [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Benjamin Herrenschmidt @ 2009-12-02 0:36 UTC (permalink / raw)
To: linux-ide; +Cc: tj, linuxppc-dev, jeff
This is a libata driver for the "macio" IDE controller used on most Apple
PowerMac and PowerBooks. It's a libata equivalent of drivers/ide/ppc/pmac.c
It supports all the features of its predecessor, including mediabay hotplug
and suspend/resume. It should also support module load/unload.
The timing calculations have been simplified to use pre-calculated tables
compared to drivers/ide/pmac.c and it uses the new mediabay interface
provided by a previous patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2. Better tested now, seems to be reasonably solid.
Addressed Tejun comments and made remove more robust vs. media-bay,
should also fix Andreas problem.
drivers/ata/Kconfig | 10
drivers/ata/Makefile | 1
drivers/ata/pata_macio.c | 1427 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1438 insertions(+)
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/drivers/ata/pata_macio.c 2009-12-02 11:26:51.000000000 +1100
@@ -0,0 +1,1427 @@
+/*
+ * Libata based driver for Apple "macio" family of PATA controllers
+ *
+ * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp
+ * <benh@kernel.crashing.org>
+ *
+ * Some bits and pieces from drivers/ide/ppc/pmac.c
+ *
+ */
+
+#undef DEBUG
+#undef DEBUG_DMA
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/ata.h>
+#include <linux/libata.h>
+#include <linux/adb.h>
+#include <linux/pmu.h>
+#include <linux/scatterlist.h>
+#include <linux/of.h>
+
+#include <scsi/scsi.h>
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_device.h>
+
+#include <asm/macio.h>
+#include <asm/io.h>
+#include <asm/dbdma.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+#include <asm/pmac_feature.h>
+#include <asm/mediabay.h>
+
+#ifdef DEBUG_DMA
+#define dev_dbgdma(dev, format, arg...) \
+ dev_printk(KERN_DEBUG , dev , format , ## arg)
+#else
+#define dev_dbgdma(dev, format, arg...) \
+ ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
+#endif
+
+#define DRV_NAME "pata_macio"
+#define DRV_VERSION "0.9"
+
+/* Models of macio ATA controller */
+enum {
+ controller_ohare, /* OHare based */
+ controller_heathrow, /* Heathrow/Paddington */
+ controller_kl_ata3, /* KeyLargo ATA-3 */
+ controller_kl_ata4, /* KeyLargo ATA-4 */
+ controller_un_ata6, /* UniNorth2 ATA-6 */
+ controller_k2_ata6, /* K2 ATA-6 */
+ controller_sh_ata6, /* Shasta ATA-6 */
+};
+
+static const char* macio_ata_names[] = {
+ "OHare ATA", /* OHare based */
+ "Heathrow ATA", /* Heathrow/Paddington */
+ "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
+ "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
+ "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
+ "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
+ "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
+};
+
+/*
+ * Extra registers, both 32-bit little-endian
+ */
+#define IDE_TIMING_CONFIG 0x200
+#define IDE_INTERRUPT 0x300
+
+/* Kauai (U2) ATA has different register setup */
+#define IDE_KAUAI_PIO_CONFIG 0x200
+#define IDE_KAUAI_ULTRA_CONFIG 0x210
+#define IDE_KAUAI_POLL_CONFIG 0x220
+
+/*
+ * Timing configuration register definitions
+ */
+
+/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
+#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
+#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
+#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
+#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
+
+/* 133Mhz cell, found in shasta.
+ * See comments about 100 Mhz Uninorth 2...
+ * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just
+ * weird and I don't now why .. at this stage
+ */
+#define TR_133_PIOREG_PIO_MASK 0xff000fff
+#define TR_133_PIOREG_MDMA_MASK 0x00fff800
+#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
+#define TR_133_UDMAREG_UDMA_EN 0x00000001
+
+/* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device
+ * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is
+ * controlled like gem or fw. It appears to be an evolution of keylargo
+ * ATA4 with a timing register extended to 2x32bits registers (one
+ * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
+ * It has it's own local feature control register as well.
+ *
+ * After scratching my mind over the timing values, at least for PIO
+ * and MDMA, I think I've figured the format of the timing register,
+ * though I use pre-calculated tables for UDMA as usual...
+ */
+#define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */
+#define TR_100_PIO_ADDRSETUP_SHIFT 24
+#define TR_100_MDMA_MASK 0x00fff000
+#define TR_100_MDMA_RECOVERY_MASK 0x00fc0000
+#define TR_100_MDMA_RECOVERY_SHIFT 18
+#define TR_100_MDMA_ACCESS_MASK 0x0003f000
+#define TR_100_MDMA_ACCESS_SHIFT 12
+#define TR_100_PIO_MASK 0xff000fff
+#define TR_100_PIO_RECOVERY_MASK 0x00000fc0
+#define TR_100_PIO_RECOVERY_SHIFT 6
+#define TR_100_PIO_ACCESS_MASK 0x0000003f
+#define TR_100_PIO_ACCESS_SHIFT 0
+
+#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
+#define TR_100_UDMAREG_UDMA_EN 0x00000001
+
+
+/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
+ * 40 connector cable and to 4 on 80 connector one.
+ * Clock unit is 15ns (66Mhz)
+ *
+ * 3 Values can be programmed:
+ * - Write data setup, which appears to match the cycle time. They
+ * also call it DIOW setup.
+ * - Ready to pause time (from spec)
+ * - Address setup. That one is weird. I don't see where exactly
+ * it fits in UDMA cycles, I got it's name from an obscure piece
+ * of commented out code in Darwin. They leave it to 0, we do as
+ * well, despite a comment that would lead to think it has a
+ * min value of 45ns.
+ * Apple also add 60ns to the write data setup (or cycle time ?) on
+ * reads.
+ */
+#define TR_66_UDMA_MASK 0xfff00000
+#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
+#define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */
+#define TR_66_PIO_ADDRSETUP_SHIFT 29
+#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
+#define TR_66_UDMA_RDY2PAUS_SHIFT 25
+#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
+#define TR_66_UDMA_WRDATASETUP_SHIFT 21
+#define TR_66_MDMA_MASK 0x000ffc00
+#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
+#define TR_66_MDMA_RECOVERY_SHIFT 15
+#define TR_66_MDMA_ACCESS_MASK 0x00007c00
+#define TR_66_MDMA_ACCESS_SHIFT 10
+#define TR_66_PIO_MASK 0xe00003ff
+#define TR_66_PIO_RECOVERY_MASK 0x000003e0
+#define TR_66_PIO_RECOVERY_SHIFT 5
+#define TR_66_PIO_ACCESS_MASK 0x0000001f
+#define TR_66_PIO_ACCESS_SHIFT 0
+
+/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
+ * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
+ *
+ * The access time and recovery time can be programmed. Some older
+ * Darwin code base limit OHare to 150ns cycle time. I decided to do
+ * the same here fore safety against broken old hardware ;)
+ * The HalfTick bit, when set, adds half a clock (15ns) to the access
+ * time and removes one from recovery. It's not supported on KeyLargo
+ * implementation afaik. The E bit appears to be set for PIO mode 0 and
+ * is used to reach long timings used in this mode.
+ */
+#define TR_33_MDMA_MASK 0x003ff800
+#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
+#define TR_33_MDMA_RECOVERY_SHIFT 16
+#define TR_33_MDMA_ACCESS_MASK 0x0000f800
+#define TR_33_MDMA_ACCESS_SHIFT 11
+#define TR_33_MDMA_HALFTICK 0x00200000
+#define TR_33_PIO_MASK 0x000007ff
+#define TR_33_PIO_E 0x00000400
+#define TR_33_PIO_RECOVERY_MASK 0x000003e0
+#define TR_33_PIO_RECOVERY_SHIFT 5
+#define TR_33_PIO_ACCESS_MASK 0x0000001f
+#define TR_33_PIO_ACCESS_SHIFT 0
+
+/*
+ * Interrupt register definitions. Only present on newer cells
+ * (Keylargo and later afaik) so we don't use it.
+ */
+#define IDE_INTR_DMA 0x80000000
+#define IDE_INTR_DEVICE 0x40000000
+
+/*
+ * FCR Register on Kauai. Not sure what bit 0x4 is ...
+ */
+#define KAUAI_FCR_UATA_MAGIC 0x00000004
+#define KAUAI_FCR_UATA_RESET_N 0x00000002
+#define KAUAI_FCR_UATA_ENABLE 0x00000001
+
+
+/* Allow up to 256 DBDMA commands per xfer */
+#define MAX_DCMDS 256
+
+/* Don't let a DMA segment go all the way to 64K */
+#define MAX_DBDMA_SEG 0xff00
+
+
+/*
+ * Wait 1s for disk to answer on IDE bus after a hard reset
+ * of the device (via GPIO/FCR).
+ *
+ * Some devices seem to "pollute" the bus even after dropping
+ * the BSY bit (typically some combo drives slave on the UDMA
+ * bus) after a hard reset. Since we hard reset all drives on
+ * KeyLargo ATA66, we have to keep that delay around. I may end
+ * up not hard resetting anymore on these and keep the delay only
+ * for older interfaces instead (we have to reset when coming
+ * from MacOS...) --BenH.
+ */
+#define IDE_WAKEUP_DELAY_MS 1000
+
+struct pata_macio_timing;
+
+struct pata_macio_priv {
+ int kind;
+ int aapl_bus_id;
+ int mediabay : 1;
+ struct device_node *node;
+ struct macio_dev *mdev;
+ struct pci_dev *pdev;
+ struct device *dev;
+ int irq;
+ u32 treg[2][2];
+ void __iomem *tfregs;
+ void __iomem *kauai_fcr;
+ struct dbdma_cmd * dma_table_cpu;
+ dma_addr_t dma_table_dma;
+ struct ata_host *host;
+ const struct pata_macio_timing *timings;
+};
+
+/* Previous variants of this driver used to calculate timings
+ * for various variants of the chip and use tables for others.
+ *
+ * Not only was this confusing, but in addition, it isn't clear
+ * whether our calculation code was correct. It didn't entirely
+ * match the darwin code and whatever documentation I could find
+ * on these cells
+ *
+ * I decided to entirely rely on a table instead for this version
+ * of the driver. Also, because I don't really care about derated
+ * modes and really old HW other than making it work, I'm not going
+ * to calculate / snoop timing values for something else than the
+ * standard modes.
+ */
+struct pata_macio_timing {
+ int mode;
+ u32 reg1; /* Bits to set in first timing reg */
+ u32 reg2; /* Bits to set in second timing reg */
+};
+
+static const struct pata_macio_timing pata_macio_ohare_timings[] = {
+ { XFER_PIO_0, 0x00000526, 0, },
+ { XFER_PIO_1, 0x00000085, 0, },
+ { XFER_PIO_2, 0x00000025, 0, },
+ { XFER_PIO_3, 0x00000025, 0, },
+ { XFER_PIO_4, 0x00000025, 0, },
+ { XFER_MW_DMA_0, 0x00074000, 0, },
+ { XFER_MW_DMA_1, 0x00221000, 0, },
+ { XFER_MW_DMA_2, 0x00211000, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_heathrow_timings[] = {
+ { XFER_PIO_0, 0x00000526, 0, },
+ { XFER_PIO_1, 0x00000085, 0, },
+ { XFER_PIO_2, 0x00000025, 0, },
+ { XFER_PIO_3, 0x00000025, 0, },
+ { XFER_PIO_4, 0x00000025, 0, },
+ { XFER_MW_DMA_0, 0x00074000, 0, },
+ { XFER_MW_DMA_1, 0x00221000, 0, },
+ { XFER_MW_DMA_2, 0x00211000, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_kl33_timings[] = {
+ { XFER_PIO_0, 0x00000526, 0, },
+ { XFER_PIO_1, 0x00000085, 0, },
+ { XFER_PIO_2, 0x00000025, 0, },
+ { XFER_PIO_3, 0x00000025, 0, },
+ { XFER_PIO_4, 0x00000025, 0, },
+ { XFER_MW_DMA_0, 0x00084000, 0, },
+ { XFER_MW_DMA_1, 0x00021800, 0, },
+ { XFER_MW_DMA_2, 0x00011800, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_kl66_timings[] = {
+ { XFER_PIO_0, 0x0000038c, 0, },
+ { XFER_PIO_1, 0x0000020a, 0, },
+ { XFER_PIO_2, 0x00000127, 0, },
+ { XFER_PIO_3, 0x000000c6, 0, },
+ { XFER_PIO_4, 0x00000065, 0, },
+ { XFER_MW_DMA_0, 0x00084000, 0, },
+ { XFER_MW_DMA_1, 0x00029800, 0, },
+ { XFER_MW_DMA_2, 0x00019400, 0, },
+ { XFER_UDMA_0, 0x19100000, 0, },
+ { XFER_UDMA_1, 0x14d00000, 0, },
+ { XFER_UDMA_2, 0x10900000, 0, },
+ { XFER_UDMA_3, 0x0c700000, 0, },
+ { XFER_UDMA_4, 0x0c500000, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_kauai_timings[] = {
+ { XFER_PIO_0, 0x08000a92, 0, },
+ { XFER_PIO_1, 0x0800060f, 0, },
+ { XFER_PIO_2, 0x0800038b, 0, },
+ { XFER_PIO_3, 0x05000249, 0, },
+ { XFER_PIO_4, 0x04000148, 0, },
+ { XFER_MW_DMA_0, 0x00618000, 0, },
+ { XFER_MW_DMA_1, 0x00209000, 0, },
+ { XFER_MW_DMA_2, 0x00148000, 0, },
+ { XFER_UDMA_0, 0, 0x000070c1, },
+ { XFER_UDMA_1, 0, 0x00005d81, },
+ { XFER_UDMA_2, 0, 0x00004a61, },
+ { XFER_UDMA_3, 0, 0x00003a51, },
+ { XFER_UDMA_4, 0, 0x00002a31, },
+ { XFER_UDMA_5, 0, 0x00002921, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_shasta_timings[] = {
+ { XFER_PIO_0, 0x0a000c97, 0, },
+ { XFER_PIO_1, 0x07000712, 0, },
+ { XFER_PIO_2, 0x040003cd, 0, },
+ { XFER_PIO_3, 0x0500028b, 0, },
+ { XFER_PIO_4, 0x0400010a, 0, },
+ { XFER_MW_DMA_0, 0x00820800, 0, },
+ { XFER_MW_DMA_1, 0x0028b000, 0, },
+ { XFER_MW_DMA_2, 0x001ca000, 0, },
+ { XFER_UDMA_0, 0, 0x00035901, },
+ { XFER_UDMA_1, 0, 0x000348b1, },
+ { XFER_UDMA_2, 0, 0x00033881, },
+ { XFER_UDMA_3, 0, 0x00033861, },
+ { XFER_UDMA_4, 0, 0x00033841, },
+ { XFER_UDMA_5, 0, 0x00033031, },
+ { XFER_UDMA_6, 0, 0x00033021, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing *pata_macio_find_timing(
+ struct pata_macio_priv *priv,
+ int mode)
+{
+ int i;
+
+ for (i = 0; priv->timings[i].mode > 0; i++) {
+ if (priv->timings[i].mode == mode)
+ return &priv->timings[i];
+ }
+ return NULL;
+}
+
+
+static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+ void __iomem *rbase = ap->ioaddr.cmd_addr;
+
+ if (priv->kind == controller_sh_ata6 ||
+ priv->kind == controller_un_ata6 ||
+ priv->kind == controller_k2_ata6) {
+ writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);
+ writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);
+ } else
+ writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);
+}
+
+static void pata_macio_dev_select(struct ata_port *ap, unsigned int device)
+{
+ ata_sff_dev_select(ap, device);
+
+ /* Apply timings */
+ pata_macio_apply_timings(ap, device);
+}
+
+static void pata_macio_set_timings(struct ata_port *ap,
+ struct ata_device *adev)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+ const struct pata_macio_timing *t;
+
+ dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",
+ adev->devno,
+ adev->pio_mode,
+ ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)),
+ adev->dma_mode,
+ ata_mode_string(ata_xfer_mode2mask(adev->dma_mode)));
+
+ /* First clear timings */
+ priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0;
+
+ /* Now get the PIO timings */
+ t = pata_macio_find_timing(priv, adev->pio_mode);
+ if (t == NULL) {
+ dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n",
+ adev->pio_mode);
+ t = pata_macio_find_timing(priv, XFER_PIO_0);
+ }
+ BUG_ON(t == NULL);
+
+ /* PIO timings only ever use the first treg */
+ priv->treg[adev->devno][0] |= t->reg1;
+
+ /* Now get DMA timings */
+ t = pata_macio_find_timing(priv, adev->dma_mode);
+ if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {
+ dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n");
+ t = pata_macio_find_timing(priv, XFER_MW_DMA_0);
+ }
+ BUG_ON(t == NULL);
+
+ /* DMA timings can use both tregs */
+ priv->treg[adev->devno][0] |= t->reg1;
+ priv->treg[adev->devno][1] |= t->reg2;
+
+ dev_dbg(priv->dev, " -> %08x %08x\n",
+ priv->treg[adev->devno][0],
+ priv->treg[adev->devno][1]);
+
+ /* Apply to hardware */
+ pata_macio_apply_timings(ap, adev->devno);
+}
+
+/*
+ * Blast some well known "safe" values to the timing registers at init or
+ * wakeup from sleep time, before we do real calculation
+ */
+static void pata_macio_default_timings(struct pata_macio_priv *priv)
+{
+ unsigned int value, value2 = 0;
+
+ switch(priv->kind) {
+ case controller_sh_ata6:
+ value = 0x0a820c97;
+ value2 = 0x00033031;
+ break;
+ case controller_un_ata6:
+ case controller_k2_ata6:
+ value = 0x08618a92;
+ value2 = 0x00002921;
+ break;
+ case controller_kl_ata4:
+ value = 0x0008438c;
+ break;
+ case controller_kl_ata3:
+ value = 0x00084526;
+ break;
+ case controller_heathrow:
+ case controller_ohare:
+ default:
+ value = 0x00074526;
+ break;
+ }
+ priv->treg[0][0] = priv->treg[1][0] = value;
+ priv->treg[0][1] = priv->treg[1][1] = value2;
+}
+
+static int pata_macio_cable_detect(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+
+ /* Get cable type from device-tree */
+ if (priv->kind == controller_kl_ata4 ||
+ priv->kind == controller_un_ata6 ||
+ priv->kind == controller_k2_ata6 ||
+ priv->kind == controller_sh_ata6) {
+ const char* cable = of_get_property(priv->node, "cable-type",
+ NULL);
+ struct device_node *root = of_find_node_by_path("/");
+ const char *model = of_get_property(root, "model", NULL);
+
+ if (cable && !strncmp(cable, "80-", 3)) {
+ /* Some drives fail to detect 80c cable in PowerBook
+ * These machine use proprietary short IDE cable
+ * anyway
+ */
+ if (!strncmp(model, "PowerBook", 9))
+ return ATA_CBL_PATA40_SHORT;
+ else
+ return ATA_CBL_PATA80;
+ }
+ }
+
+ /* G5's seem to have incorrect cable type in device-tree.
+ * Let's assume they always have a 80 conductor cable, this seem to
+ * be always the case unless the user mucked around
+ */
+ if (of_device_is_compatible(priv->node, "K2-UATA") ||
+ of_device_is_compatible(priv->node, "shasta-ata"))
+ return ATA_CBL_PATA80;
+
+ /* Anything else is 40 connectors */
+ return ATA_CBL_PATA40;
+}
+
+static void pata_macio_qc_prep(struct ata_queued_cmd *qc)
+{
+ unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE);
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct scatterlist *sg;
+ struct dbdma_cmd *table;
+ unsigned int si, pi;
+
+ dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n",
+ __func__, qc, qc->flags, write, qc->dev->devno);
+
+ if (!(qc->flags & ATA_QCFLAG_DMAMAP))
+ return;
+
+ table = (struct dbdma_cmd *) priv->dma_table_cpu;
+
+ pi = 0;
+ for_each_sg(qc->sg, sg, qc->n_elem, si) {
+ u32 addr, sg_len, len;
+
+ /* determine if physical DMA addr spans 64K boundary.
+ * Note h/w doesn't support 64-bit, so we unconditionally
+ * truncate dma_addr_t to u32.
+ */
+ addr = (u32) sg_dma_address(sg);
+ sg_len = sg_dma_len(sg);
+
+ while (sg_len) {
+ /* table overflow should never happen */
+ BUG_ON (pi++ >= MAX_DCMDS);
+
+ len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;
+ st_le16(&table->command, write ? OUTPUT_MORE: INPUT_MORE);
+ st_le16(&table->req_count, len);
+ st_le32(&table->phy_addr, addr);
+ table->cmd_dep = 0;
+ table->xfer_status = 0;
+ table->res_count = 0;
+ addr += len;
+ sg_len -= len;
+ ++table;
+ }
+ }
+
+ /* Should never happen according to Tejun */
+ BUG_ON(!pi);
+
+ /* Convert the last command to an input/output */
+ table--;
+ st_le16(&table->command, write ? OUTPUT_LAST: INPUT_LAST);
+ table++;
+
+ /* Add the stop command to the end of the list */
+ memset(table, 0, sizeof(struct dbdma_cmd));
+ st_le16(&table->command, DBDMA_STOP);
+
+ dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi);
+}
+
+
+static void pata_macio_freeze(struct ata_port *ap)
+{
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+
+ if (dma_regs) {
+ unsigned int timeout = 1000000;
+
+ /* Make sure DMA controller is stopped */
+ writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
+ while (--timeout && (readl(&dma_regs->status) & RUN))
+ udelay(1);
+ }
+
+ ata_sff_freeze(ap);
+}
+
+
+static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+ int dev = qc->dev->devno;
+
+ dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
+
+ /* Make sure DMA commands updates are visible */
+ writel(priv->dma_table_dma, &dma_regs->cmdptr);
+
+ /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on
+ * UDMA reads
+ */
+ if (priv->kind == controller_kl_ata4 &&
+ (priv->treg[dev][0] & TR_66_UDMA_EN)) {
+ void __iomem *rbase = ap->ioaddr.cmd_addr;
+ u32 reg = priv->treg[dev][0];
+
+ if (!(qc->tf.flags & ATA_TFLAG_WRITE))
+ reg += 0x00800000;
+ writel(reg, rbase + IDE_TIMING_CONFIG);
+ }
+
+ /* issue r/w command */
+ ap->ops->sff_exec_command(ap, &qc->tf);
+}
+
+static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+
+ dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
+
+ writel((RUN << 16) | RUN, &dma_regs->control);
+ /* Make sure it gets to the controller right now */
+ (void)readl(&dma_regs->control);
+}
+
+static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+ unsigned int timeout = 1000000;
+
+ dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
+
+ /* Stop the DMA engine and wait for it to full halt */
+ writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
+ while (--timeout && (readl(&dma_regs->status) & RUN))
+ udelay(1);
+}
+
+static u8 pata_macio_bmdma_status(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+ u32 dstat, rstat = ATA_DMA_INTR;
+ unsigned long timeout = 0;
+
+ dstat = readl(&dma_regs->status);
+
+ dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);
+
+ /* We have two things to deal with here:
+ *
+ * - The dbdma won't stop if the command was started
+ * but completed with an error without transferring all
+ * datas. This happens when bad blocks are met during
+ * a multi-block transfer.
+ *
+ * - The dbdma fifo hasn't yet finished flushing to
+ * to system memory when the disk interrupt occurs.
+ *
+ */
+
+ /* First check for errors */
+ if ((dstat & (RUN|DEAD)) != RUN)
+ rstat |= ATA_DMA_ERR;
+
+ /* If ACTIVE is cleared, the STOP command has been hit and
+ * the transfer is complete. If not, we have to flush the
+ * channel.
+ */
+ if ((dstat & ACTIVE) == 0)
+ return rstat;
+
+ dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__);
+
+ /* If dbdma didn't execute the STOP command yet, the
+ * active bit is still set. We consider that we aren't
+ * sharing interrupts (which is hopefully the case with
+ * those controllers) and so we just try to flush the
+ * channel for pending data in the fifo
+ */
+ udelay(1);
+ writel((FLUSH << 16) | FLUSH, &dma_regs->control);
+ for (;;) {
+ udelay(1);
+ dstat = readl(&dma_regs->status);
+ if ((dstat & FLUSH) == 0)
+ break;
+ if (++timeout > 1000) {
+ dev_warn(priv->dev, "timeout flushing DMA\n");
+ rstat |= ATA_DMA_ERR;
+ break;
+ }
+ }
+ return rstat;
+}
+
+/* port_start is when we allocate the DMA command list */
+static int pata_macio_port_start(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+
+ if (ap->ioaddr.bmdma_addr == NULL)
+ return 0;
+
+ /* Allocate space for the DBDMA commands.
+ *
+ * The +2 is +1 for the stop command and +1 to allow for
+ * aligning the start address to a multiple of 16 bytes.
+ */
+ priv->dma_table_cpu =
+ dmam_alloc_coherent(priv->dev,
+ (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
+ &priv->dma_table_dma, GFP_KERNEL);
+ if (priv->dma_table_cpu == NULL) {
+ dev_err(priv->dev, "Unable to allocate DMA command list\n");
+ ap->ioaddr.bmdma_addr = NULL;
+ }
+ return 0;
+}
+
+static void pata_macio_irq_clear(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+
+ /* Nothing to do here */
+
+ dev_dbgdma(priv->dev, "%s\n", __func__);
+}
+
+static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
+{
+ dev_dbg(priv->dev, "Enabling & resetting... \n");
+
+ if (priv->mediabay)
+ return;
+
+ if (priv->kind == controller_ohare && !resume) {
+ /* The code below is having trouble on some ohare machines
+ * (timing related ?). Until I can put my hand on one of these
+ * units, I keep the old way
+ */
+ ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1);
+ } else {
+ int rc;
+
+ /* Reset and enable controller */
+ rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET,
+ priv->node, priv->aapl_bus_id, 1);
+ ppc_md.feature_call(PMAC_FTR_IDE_ENABLE,
+ priv->node, priv->aapl_bus_id, 1);
+ msleep(10);
+ /* Only bother waiting if there's a reset control */
+ if (rc == 0) {
+ ppc_md.feature_call(PMAC_FTR_IDE_RESET,
+ priv->node, priv->aapl_bus_id, 0);
+ msleep(IDE_WAKEUP_DELAY_MS);
+ }
+ }
+
+ /* If resuming a PCI device, restore the config space here */
+ if (priv->pdev && resume) {
+ int rc;
+
+ pci_restore_state(priv->pdev);
+ rc = pcim_enable_device(priv->pdev);
+ if (rc)
+ dev_printk(KERN_ERR, &priv->pdev->dev,
+ "Failed to enable device after resume (%d)\n", rc);
+ else
+ pci_set_master(priv->pdev);
+ }
+
+ /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really
+ * seem necessary and speeds up the boot process
+ */
+ if (priv->kauai_fcr)
+ writel(KAUAI_FCR_UATA_MAGIC |
+ KAUAI_FCR_UATA_RESET_N |
+ KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr);
+}
+
+/* Hook the standard slave config to fixup some HW related alignment
+ * restrictions
+ */
+static int pata_macio_slave_config(struct scsi_device *sdev)
+{
+ struct ata_port *ap = ata_shost_to_port(sdev->host);
+ struct pata_macio_priv *priv = ap->private_data;
+ struct ata_device *dev;
+ u16 cmd;
+ int rc;
+
+ /* First call original */
+ rc = ata_scsi_slave_config(sdev);
+ if (rc)
+ return rc;
+
+ /* This is lifted from sata_nv */
+ dev = &ap->link.device[sdev->id];
+
+ /* OHare has issues with non cache aligned DMA on some chipsets */
+ if (priv->kind == controller_ohare) {
+ blk_queue_update_dma_alignment(sdev->request_queue, 31);
+ blk_queue_update_dma_pad(sdev->request_queue, 31);
+
+ /* Tell the world about it */
+ ata_dev_printk(dev, KERN_INFO, "OHare alignment limits applied\n");
+ return 0;
+ }
+
+ /* We only have issues with ATAPI */
+ if (dev->class != ATA_DEV_ATAPI)
+ return 0;
+
+ /* Shasta and K2 seem to have "issues" with reads ... */
+ if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {
+ /* Allright these are bad, apply restrictions */
+ blk_queue_update_dma_alignment(sdev->request_queue, 15);
+ blk_queue_update_dma_pad(sdev->request_queue, 15);
+
+ /* We enable MWI and hack cache line size directly here, this
+ * is specific to this chipset and not normal values, we happen
+ * to somewhat know what we are doing here (which is basically
+ * to do the same Apple does and pray they did not get it wrong :-)
+ */
+ BUG_ON(!priv->pdev);
+ pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd);
+ pci_write_config_word(priv->pdev, PCI_COMMAND,
+ cmd | PCI_COMMAND_INVALIDATE);
+
+ /* Tell the world about it */
+ ata_dev_printk(dev, KERN_INFO,
+ "K2/Shasta alignment limits applied\n");
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
+{
+ int rc;
+
+ /* First, core libata suspend to do most of the work */
+ rc = ata_host_suspend(priv->host, mesg);
+ if (rc)
+ return rc;
+
+ /* Restore to default timings */
+ pata_macio_default_timings(priv);
+
+ /* Mask interrupt. Not strictly necessary but old driver did
+ * it and I'd rather not change that here */
+ disable_irq(priv->irq);
+
+ /* The media bay will handle itself just fine */
+ if (priv->mediabay)
+ return 0;
+
+ /* Kauai has bus control FCRs directly here */
+ if (priv->kauai_fcr) {
+ u32 fcr = readl(priv->kauai_fcr);
+ fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
+ writel(fcr, priv->kauai_fcr);
+ }
+
+ /* For PCI, save state and disable DMA. No need to call
+ * pci_set_power_state(), the HW doesn't do D states that
+ * way, the platform code will take care of suspending the
+ * ASIC properly
+ */
+ if (priv->pdev) {
+ pci_save_state(priv->pdev);
+ pci_disable_device(priv->pdev);
+ }
+
+ /* Disable the bus on older machines and the cell on kauai */
+ ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node,
+ priv->aapl_bus_id, 0);
+
+ return 0;
+}
+
+static int pata_macio_do_resume(struct pata_macio_priv *priv)
+{
+ /* Reset and re-enable the HW */
+ pata_macio_reset_hw(priv, 1);
+
+ /* Sanitize drive timings */
+ pata_macio_apply_timings(priv->host->ports[0], 0);
+
+ /* We want our IRQ back ! */
+ enable_irq(priv->irq);
+
+ /* Let the libata core take it from there */
+ ata_host_resume(priv->host);
+
+ return 0;
+}
+
+#endif /* CONFIG_PM */
+
+static struct scsi_host_template pata_macio_sht = {
+ ATA_BASE_SHT(DRV_NAME),
+ .sg_tablesize = MAX_DCMDS,
+ /* We may not need that strict one */
+ .dma_boundary = ATA_DMA_BOUNDARY,
+ .slave_configure = pata_macio_slave_config,
+};
+
+static struct ata_port_operations pata_macio_ops = {
+ .inherits = &ata_sff_port_ops,
+
+ .freeze = pata_macio_freeze,
+ .set_piomode = pata_macio_set_timings,
+ .set_dmamode = pata_macio_set_timings,
+ .cable_detect = pata_macio_cable_detect,
+ .sff_dev_select = pata_macio_dev_select,
+ .qc_prep = pata_macio_qc_prep,
+ .mode_filter = ata_bmdma_mode_filter,
+ .bmdma_setup = pata_macio_bmdma_setup,
+ .bmdma_start = pata_macio_bmdma_start,
+ .bmdma_stop = pata_macio_bmdma_stop,
+ .bmdma_status = pata_macio_bmdma_status,
+ .port_start = pata_macio_port_start,
+ .sff_irq_clear = pata_macio_irq_clear,
+};
+
+static void __devinit pata_macio_invariants(struct pata_macio_priv *priv)
+{
+ const int *bidp;
+
+ /* Identify the type of controller */
+ if (of_device_is_compatible(priv->node, "shasta-ata")) {
+ priv->kind = controller_sh_ata6;
+ priv->timings = pata_macio_shasta_timings;
+ } else if (of_device_is_compatible(priv->node, "kauai-ata")) {
+ priv->kind = controller_un_ata6;
+ priv->timings = pata_macio_kauai_timings;
+ } else if (of_device_is_compatible(priv->node, "K2-UATA")) {
+ priv->kind = controller_k2_ata6;
+ priv->timings = pata_macio_kauai_timings;
+ } else if (of_device_is_compatible(priv->node, "keylargo-ata")) {
+ if (strcmp(priv->node->name, "ata-4") == 0) {
+ priv->kind = controller_kl_ata4;
+ priv->timings = pata_macio_kl66_timings;
+ } else {
+ priv->kind = controller_kl_ata3;
+ priv->timings = pata_macio_kl33_timings;
+ }
+ } else if (of_device_is_compatible(priv->node, "heathrow-ata")) {
+ priv->kind = controller_heathrow;
+ priv->timings = pata_macio_heathrow_timings;
+ } else {
+ priv->kind = controller_ohare;
+ priv->timings = pata_macio_ohare_timings;
+ }
+
+ /* XXX FIXME --- setup priv->mediabay here */
+
+ /* Get Apple bus ID (for clock and ASIC control) */
+ bidp = of_get_property(priv->node, "AAPL,bus-id", NULL);
+ priv->aapl_bus_id = bidp ? *bidp : 0;
+
+ /* Fixup missing Apple bus ID in case of media-bay */
+ if (priv->mediabay && bidp == 0)
+ priv->aapl_bus_id = 1;
+}
+
+static void __devinit pata_macio_setup_ios(struct ata_ioports *ioaddr,
+ void __iomem * base,
+ void __iomem * dma)
+{
+ /* cmd_addr is the base of regs for that port */
+ ioaddr->cmd_addr = base;
+
+ /* taskfile registers */
+ ioaddr->data_addr = base + (ATA_REG_DATA << 4);
+ ioaddr->error_addr = base + (ATA_REG_ERR << 4);
+ ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4);
+ ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4);
+ ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4);
+ ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4);
+ ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4);
+ ioaddr->device_addr = base + (ATA_REG_DEVICE << 4);
+ ioaddr->status_addr = base + (ATA_REG_STATUS << 4);
+ ioaddr->command_addr = base + (ATA_REG_CMD << 4);
+ ioaddr->altstatus_addr = base + 0x160;
+ ioaddr->ctl_addr = base + 0x160;
+ ioaddr->bmdma_addr = dma;
+}
+
+static void __devinit pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
+ struct ata_port_info *pinfo)
+{
+ int i = 0;
+
+ pinfo->pio_mask = 0;
+ pinfo->mwdma_mask = 0;
+ pinfo->udma_mask = 0;
+
+ while (priv->timings[i].mode > 0) {
+ unsigned int mask = 1U << (priv->timings[i].mode & 0x0f);
+ switch(priv->timings[i].mode & 0xf0) {
+ case 0x00: /* PIO */
+ pinfo->pio_mask |= (mask >> 8);
+ break;
+ case 0x20: /* MWDMA */
+ pinfo->mwdma_mask |= mask;
+ break;
+ case 0x40: /* UDMA */
+ pinfo->udma_mask |= mask;
+ break;
+ }
+ i++;
+ }
+ dev_dbg(priv->dev, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n",
+ pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
+}
+
+static int __devinit pata_macio_common_init(struct pata_macio_priv *priv,
+ resource_size_t tfregs,
+ resource_size_t dmaregs,
+ resource_size_t fcregs,
+ unsigned long irq)
+{
+ struct ata_port_info pinfo;
+ const struct ata_port_info *ppi[] = { &pinfo, NULL };
+ void __iomem *dma_regs = NULL;
+
+ /* Fill up privates with various invariants collected from the
+ * device-tree
+ */
+ pata_macio_invariants(priv);
+
+ /* Make sure we have sane initial timings in the cache */
+ pata_macio_default_timings(priv);
+
+ /* Not sure what the real max is but we know it's less than 64K, let's
+ * use 64K minus 256
+ */
+ dma_set_max_seg_size(priv->dev, MAX_DBDMA_SEG);
+
+ /* Allocate libata host for 1 port */
+ memset(&pinfo, 0, sizeof(struct ata_port_info));
+ pmac_macio_calc_timing_masks(priv, &pinfo);
+ pinfo.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO |
+ ATA_FLAG_NO_LEGACY;
+ pinfo.port_ops = &pata_macio_ops;
+ pinfo.private_data = priv;
+
+ priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1);
+ if (priv->host == NULL) {
+ dev_err(priv->dev, "Failed to allocate ATA port structure\n");
+ return -ENOMEM;
+ }
+
+ /* Setup the private data in host too */
+ priv->host->private_data = priv;
+
+ /* Map base registers */
+ priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100);
+ if (priv->tfregs == NULL) {
+ dev_err(priv->dev, "Failed to map ATA ports\n");
+ return -ENOMEM;
+ }
+ priv->host->iomap = &priv->tfregs;
+
+ /* Map DMA regs */
+ if (dmaregs != 0) {
+ dma_regs = devm_ioremap(priv->dev, dmaregs,
+ sizeof(struct dbdma_regs));
+ if (dma_regs == NULL)
+ dev_warn(priv->dev, "Failed to map ATA DMA registers\n");
+ }
+
+ /* If chip has local feature control, map those regs too */
+ if (fcregs != 0) {
+ priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4);
+ if (priv->kauai_fcr == NULL) {
+ dev_err(priv->dev, "Failed to map ATA FCR register\n");
+ return -ENOMEM;
+ }
+ }
+
+ /* Setup port data structure */
+ pata_macio_setup_ios(&priv->host->ports[0]->ioaddr,
+ priv->tfregs, dma_regs);
+ priv->host->ports[0]->private_data = priv;
+
+ /* hard-reset the controller */
+ pata_macio_reset_hw(priv, 0);
+ pata_macio_apply_timings(priv->host->ports[0], 0);
+
+ /* Enable bus master if necessary */
+ if (priv->pdev && dma_regs)
+ pci_set_master(priv->pdev);
+
+ dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n",
+ macio_ata_names[priv->kind], priv->aapl_bus_id);
+
+ /* Start it up */
+ priv->irq = irq;
+ return ata_host_activate(priv->host, irq, ata_sff_interrupt, 0,
+ &pata_macio_sht);
+}
+
+static int __devinit pata_macio_attach(struct macio_dev *mdev,
+ const struct of_device_id *match)
+{
+ struct pata_macio_priv *priv;
+ resource_size_t tfregs, dmaregs = 0;
+ unsigned long irq;
+ int rc;
+
+ /* Check for broken device-trees */
+ if (macio_resource_count(mdev) == 0) {
+ dev_err(&mdev->ofdev.dev,
+ "No addresses for controller\n");
+ return -ENXIO;
+ }
+
+ /* Enable managed resources */
+ macio_enable_devres(mdev);
+
+ /* Allocate and init private data structure */
+ priv = devm_kzalloc(&mdev->ofdev.dev,
+ sizeof(struct pata_macio_priv), GFP_KERNEL);
+ if (priv == NULL) {
+ dev_err(&mdev->ofdev.dev,
+ "Failed to allocate private memory\n");
+ return -ENOMEM;
+ }
+ priv->node = of_node_get(mdev->ofdev.node);
+ priv->mdev = mdev;
+ priv->dev = &mdev->ofdev.dev;
+
+ /* Request memory resource for taskfile registers */
+ if (macio_request_resource(mdev, 0, "pata-macio")) {
+ dev_err(&mdev->ofdev.dev,
+ "Cannot obtain taskfile resource\n");
+ return -EBUSY;
+ }
+ tfregs = macio_resource_start(mdev, 0);
+
+ /* Request resources for DMA registers if any */
+ if (macio_resource_count(mdev) >= 2) {
+ if (macio_request_resource(mdev, 1, "pata-macio-dma"))
+ dev_err(&mdev->ofdev.dev,
+ "Cannot obtain DMA resource\n");
+ else
+ dmaregs = macio_resource_start(mdev, 1);
+ }
+
+ /*
+ * Fixup missing IRQ for some old implementations with broken
+ * device-trees.
+ *
+ * This is a bit bogus, it should be fixed in the device-tree itself,
+ * via the existing macio fixups, based on the type of interrupt
+ * controller in the machine. However, I have no test HW for this case,
+ * and this trick works well enough on those old machines...
+ */
+ if (macio_irq_count(mdev) == 0) {
+ dev_warn(&mdev->ofdev.dev,
+ "No interrupts for controller, using 13\n");
+ irq = irq_create_mapping(NULL, 13);
+ } else
+ irq = macio_irq(mdev, 0);
+
+ /* Prevvent media bay callbacks until fully registered */
+ lock_media_bay(priv->mdev->media_bay);
+
+ /* Get register addresses and call common initialization */
+ rc = pata_macio_common_init(priv,
+ tfregs, /* Taskfile regs */
+ dmaregs, /* DBDMA regs */
+ 0, /* Feature control */
+ irq);
+ unlock_media_bay(priv->mdev->media_bay);
+
+ return rc;
+}
+
+static int __devexit pata_macio_detach(struct macio_dev *mdev)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+ struct pata_macio_priv *priv = host->private_data;
+
+ lock_media_bay(priv->mdev->media_bay);
+
+ /* Make sure the mediabay callback doesn't try to access
+ * dead stuff
+ */
+ priv->host->private_data = NULL;
+
+ ata_host_detach(host);
+
+ unlock_media_bay(priv->mdev->media_bay);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+
+ return pata_macio_do_suspend(host->private_data, mesg);
+}
+
+static int pata_macio_resume(struct macio_dev *mdev)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+
+ return pata_macio_do_resume(host->private_data);
+}
+
+#endif /* CONFIG_PM */
+
+#ifdef CONFIG_PMAC_MEDIABAY
+static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+ struct ata_port *ap;
+ struct ata_eh_info *ehi;
+ struct ata_device *dev;
+ unsigned long flags;
+
+ if (!host || !host->private_data)
+ return;
+ ap = host->ports[0];
+ spin_lock_irqsave(ap->lock, flags);
+ ehi = &ap->link.eh_info;
+ if (mb_state == MB_CD) {
+ ata_ehi_push_desc(ehi, "mediabay plug");
+ ata_ehi_hotplugged(ehi);
+ ata_port_freeze(ap);
+ } else {
+ ata_ehi_push_desc(ehi, "mediabay unplug");
+ ata_for_each_dev(dev, &ap->link, ALL)
+ dev->flags |= ATA_DFLAG_DETACH;
+ ata_port_abort(ap);
+ }
+ spin_unlock_irqrestore(ap->lock, flags);
+
+}
+#endif /* CONFIG_PMAC_MEDIABAY */
+
+
+static int __devinit pata_macio_pci_attach(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ struct pata_macio_priv *priv;
+ struct device_node *np;
+ resource_size_t rbase;
+
+ /* We cannot use a MacIO controller without its OF device node */
+ np = pci_device_to_OF_node(pdev);
+ if (np == NULL) {
+ dev_err(&pdev->dev,
+ "Cannot find OF device node for controller\n");
+ return -ENODEV;
+ }
+
+ /* Check that it can be enabled */
+ if (pcim_enable_device(pdev)) {
+ dev_err(&pdev->dev,
+ "Cannot enable controller PCI device\n");
+ return -ENXIO;
+ }
+
+ /* Allocate and init private data structure */
+ priv = devm_kzalloc(&pdev->dev,
+ sizeof(struct pata_macio_priv), GFP_KERNEL);
+ if (priv == NULL) {
+ dev_err(&pdev->dev,
+ "Failed to allocate private memory\n");
+ return -ENOMEM;
+ }
+ priv->node = of_node_get(np);
+ priv->pdev = pdev;
+ priv->dev = &pdev->dev;
+
+ /* Get MMIO regions */
+ if (pci_request_regions(pdev, "pata-macio")) {
+ dev_err(&pdev->dev,
+ "Cannot obtain PCI resources\n");
+ return -EBUSY;
+ }
+
+ /* Get register addresses and call common initialization */
+ rbase = pci_resource_start(pdev, 0);
+ if (pata_macio_common_init(priv,
+ rbase + 0x2000, /* Taskfile regs */
+ rbase + 0x1000, /* DBDMA regs */
+ rbase, /* Feature control */
+ pdev->irq))
+ return -ENXIO;
+
+ return 0;
+}
+
+static void __devexit pata_macio_pci_detach(struct pci_dev *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+
+ ata_host_detach(host);
+}
+
+#ifdef CONFIG_PM
+
+static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+
+ return pata_macio_do_suspend(host->private_data, mesg);
+}
+
+static int pata_macio_pci_resume(struct pci_dev *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+
+ return pata_macio_do_resume(host->private_data);
+}
+
+#endif /* CONFIG_PM */
+
+static struct of_device_id pata_macio_match[] =
+{
+ {
+ .name = "IDE",
+ },
+ {
+ .name = "ATA",
+ },
+ {
+ .type = "ide",
+ },
+ {
+ .type = "ata",
+ },
+ {},
+};
+
+static struct macio_driver pata_macio_driver =
+{
+ .name = "pata-macio",
+ .match_table = pata_macio_match,
+ .probe = pata_macio_attach,
+ .remove = pata_macio_detach,
+#ifdef CONFIG_PM
+ .suspend = pata_macio_suspend,
+ .resume = pata_macio_resume,
+#endif
+#ifdef CONFIG_PMAC_MEDIABAY
+ .mediabay_event = pata_macio_mb_event,
+#endif
+ .driver = {
+ .owner = THIS_MODULE,
+ },
+};
+
+static const struct pci_device_id pata_macio_pci_match[] = {
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
+ {},
+};
+
+static struct pci_driver pata_macio_pci_driver = {
+ .name = "pata-pci-macio",
+ .id_table = pata_macio_pci_match,
+ .probe = pata_macio_pci_attach,
+ .remove = pata_macio_pci_detach,
+#ifdef CONFIG_PM
+ .suspend = pata_macio_pci_suspend,
+ .resume = pata_macio_pci_resume,
+#endif
+ .driver = {
+ .owner = THIS_MODULE,
+ },
+};
+MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);
+
+
+static int __init pata_macio_init(void)
+{
+ int rc;
+
+ if (!machine_is(powermac))
+ return -ENODEV;
+
+ rc = pci_register_driver(&pata_macio_pci_driver);
+ if (rc)
+ return rc;
+ rc = macio_register_driver(&pata_macio_driver);
+ if (rc) {
+ pci_unregister_driver(&pata_macio_pci_driver);
+ return rc;
+ }
+ return 0;
+}
+
+static void __exit pata_macio_exit(void)
+{
+ macio_unregister_driver(&pata_macio_driver);
+ pci_unregister_driver(&pata_macio_pci_driver);
+}
+
+module_init(pata_macio_init);
+module_exit(pata_macio_exit);
+
+MODULE_AUTHOR("Benjamin Herrenschmidt");
+MODULE_DESCRIPTION("Apple MacIO PATA driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
Index: linux-work/drivers/ata/Kconfig
===================================================================
--- linux-work.orig/drivers/ata/Kconfig 2009-12-02 11:24:34.000000000 +1100
+++ linux-work/drivers/ata/Kconfig 2009-12-02 11:26:51.000000000 +1100
@@ -781,5 +781,15 @@ config PATA_BF54X
If unsure, say N.
+config PATA_MACIO
+ tristate "Apple PowerMac/PowerBook internal 'MacIO' IDE"
+ depends on PPC_PMAC
+ help
+ Most IDE capable PowerMacs have IDE busses driven by a variant
+ of this controller which is part of the Apple chipset used on
+ most PowerMac models. Some models have multiple busses using
+ different chipsets, though generally, MacIO is one of them.
+
+
endif # ATA_SFF
endif # ATA
Index: linux-work/drivers/ata/Makefile
===================================================================
--- linux-work.orig/drivers/ata/Makefile 2009-12-02 11:24:34.000000000 +1100
+++ linux-work/drivers/ata/Makefile 2009-12-02 11:26:51.000000000 +1100
@@ -18,6 +18,7 @@ obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o
obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
obj-$(CONFIG_SATA_FSL) += sata_fsl.o
+obj-$(CONFIG_PATA_MACIO) += pata_macio.o
obj-$(CONFIG_PATA_ALI) += pata_ali.o
obj-$(CONFIG_PATA_AMD) += pata_amd.o
^ permalink raw reply
* Re: [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Tejun Heo @ 2009-12-02 1:07 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linux-ide, linuxppc-dev, jeff
In-Reply-To: <20091202003630.29919100851@ozlabs.org>
On 12/02/2009 09:36 AM, Benjamin Herrenschmidt wrote:
> This is a libata driver for the "macio" IDE controller used on most Apple
> PowerMac and PowerBooks. It's a libata equivalent of drivers/ide/ppc/pmac.c
>
> It supports all the features of its predecessor, including mediabay hotplug
> and suspend/resume. It should also support module load/unload.
>
> The timing calculations have been simplified to use pre-calculated tables
> compared to drivers/ide/pmac.c and it uses the new mediabay interface
> provided by a previous patch.
Other than the media bay locking thing I mentioned before, it looks
good to me and the media bay thing can be dealth with further patches,
so...
Acked-by: Tejun Heo <tj@kernel.org>
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Benjamin Herrenschmidt @ 2009-12-02 1:51 UTC (permalink / raw)
To: Tejun Heo; +Cc: linux-ide, linuxppc-dev, jeff
In-Reply-To: <4B15BDCF.5020000@kernel.org>
On Wed, 2009-12-02 at 10:07 +0900, Tejun Heo wrote:
> On 12/02/2009 09:36 AM, Benjamin Herrenschmidt wrote:
> > This is a libata driver for the "macio" IDE controller used on most Apple
> > PowerMac and PowerBooks. It's a libata equivalent of drivers/ide/ppc/pmac.c
> >
> > It supports all the features of its predecessor, including mediabay hotplug
> > and suspend/resume. It should also support module load/unload.
> >
> > The timing calculations have been simplified to use pre-calculated tables
> > compared to drivers/ide/pmac.c and it uses the new mediabay interface
> > provided by a previous patch.
>
> Other than the media bay locking thing I mentioned before, it looks
> good to me and the media bay thing can be dealth with further patches,
> so...
>
> Acked-by: Tejun Heo <tj@kernel.org>
Thanks.
I'm not sure what media bay locking problem you mentioned tho...
The way the driver does the locking now is that I block the media-bay
thread (lock/unlock_media_bay calls) around initial registration and
driver removal which blocks the callback event. At any other time, the
callback event will just schedule EH so things should be fine.
I've left the debouncing in the mediabay code as well for both insertion
and removal so there should be no issue here with glitches.
Cheers,
Ben.
^ permalink raw reply
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