* Re: [PATCH 09/11] powerpc/fsl-booke64: Use TLB CAMs to cover linear mapping on FSL 64-bit chips
From: Benjamin Herrenschmidt @ 2010-10-13 23:57 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <1286564813-21209-9-git-send-email-galak@kernel.crashing.org>
On Fri, 2010-10-08 at 14:06 -0500, Kumar Gala wrote:
> On Freescale parts typically have TLB array for large mappings that we can
> bolt the linear mapping into. We utilize the code that already exists
> on PPC32 on the 64-bit side to setup the linear mapping to be cover by
> bolted TLB entries. We utilize a quarter of the variable size TLB array
> for this purpose.
>
> Additionally, we limit the amount of memory to what we can cover via
> bolted entries so we don't get secondary faults in the TLB miss
> handlers. We should fix this limitation in the future.
It might be worth investigating then doing simpler TLB miss handlers.
Currently, you use my virtually linear scheme which involves a recursion
to fault in the virtual mappings for the page tables, which means quite
a bit of code to save/restore state for every TLB miss.
With a bolted linear mapping, if you go for a simple tree walk (which
wouldn't fault), you can remove all that prolog/epilog etc...
It may or may not be faster ... depends. You get less code but more
loads, so it depends how well they end up being cached.
Cheers,
Ben.
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/kernel/asm-offsets.c | 4 ++--
> arch/powerpc/mm/Makefile | 2 +-
> arch/powerpc/mm/fsl_booke_mmu.c | 12 +++++++-----
> arch/powerpc/mm/mmu_decl.h | 5 ++++-
> arch/powerpc/mm/tlb_nohash.c | 14 ++++++++++++++
> arch/powerpc/mm/tlb_nohash_low.S | 2 +-
> 6 files changed, 29 insertions(+), 10 deletions(-)
>
> diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
> index c634940..c3e0194 100644
> --- a/arch/powerpc/kernel/asm-offsets.c
> +++ b/arch/powerpc/kernel/asm-offsets.c
> @@ -61,7 +61,7 @@
> #endif
> #endif
>
> -#if defined(CONFIG_FSL_BOOKE)
> +#if defined(CONFIG_PPC_FSL_BOOK3E)
> #include "../mm/mmu_decl.h"
> #endif
>
> @@ -470,7 +470,7 @@ int main(void)
> DEFINE(PGD_T_LOG2, PGD_T_LOG2);
> DEFINE(PTE_T_LOG2, PTE_T_LOG2);
> #endif
> -#ifdef CONFIG_FSL_BOOKE
> +#ifdef CONFIG_PPC_FSL_BOOK3E
> DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
> DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));
> DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));
> diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
> index ce68708..d646f16 100644
> --- a/arch/powerpc/mm/Makefile
> +++ b/arch/powerpc/mm/Makefile
> @@ -25,7 +25,7 @@ obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
> mmu_context_hash$(CONFIG_WORD_SIZE).o
> obj-$(CONFIG_40x) += 40x_mmu.o
> obj-$(CONFIG_44x) += 44x_mmu.o
> -obj-$(CONFIG_FSL_BOOKE) += fsl_booke_mmu.o
> +obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o
> obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o
> obj-$(CONFIG_PPC_MM_SLICES) += slice.o
> ifeq ($(CONFIG_HUGETLB_PAGE),y)
> diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
> index 1b4354d..67bc8a7 100644
> --- a/arch/powerpc/mm/fsl_booke_mmu.c
> +++ b/arch/powerpc/mm/fsl_booke_mmu.c
> @@ -56,11 +56,6 @@
>
> unsigned int tlbcam_index;
>
> -
> -#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
> -#error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
> -#endif
> -
> #define NUM_TLBCAMS (64)
> struct tlbcam TLBCAM[NUM_TLBCAMS];
>
> @@ -185,6 +180,12 @@ unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
> return amount_mapped;
> }
>
> +#ifdef CONFIG_PPC32
> +
> +#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
> +#error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
> +#endif
> +
> unsigned long __init mmu_mapin_ram(unsigned long top)
> {
> return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1;
> @@ -216,3 +217,4 @@ void __init adjust_total_lowmem(void)
>
> __initial_memory_limit_addr = memstart_addr + __max_low_memory;
> }
> +#endif
> diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
> index 63b84a0..dd0a258 100644
> --- a/arch/powerpc/mm/mmu_decl.h
> +++ b/arch/powerpc/mm/mmu_decl.h
> @@ -140,10 +140,13 @@ extern void wii_memory_fixups(void);
> extern void MMU_init_hw(void);
> extern unsigned long mmu_mapin_ram(unsigned long top);
>
> -#elif defined(CONFIG_FSL_BOOKE)
> +#elif defined(CONFIG_PPC_FSL_BOOK3E)
> +extern unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx);
> +#ifdef CONFIG_PPC32
> extern void MMU_init_hw(void);
> extern unsigned long mmu_mapin_ram(unsigned long top);
> extern void adjust_total_lowmem(void);
> +#endif
> extern void loadcam_entry(unsigned int index);
>
> struct tlbcam {
> diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
> index 6651899..61fe32a 100644
> --- a/arch/powerpc/mm/tlb_nohash.c
> +++ b/arch/powerpc/mm/tlb_nohash.c
> @@ -541,6 +541,20 @@ static void __early_init_mmu(int boot_cpu)
> */
> linear_map_top = memblock_end_of_DRAM();
>
> +#ifdef CONFIG_PPC_FSL_BOOK3E
> + if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
> + unsigned int num_cams;
> +
> + /* use a quarter of the TLBCAM for bolted linear map */
> + num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
> + linear_map_top = map_mem_in_cams(linear_map_top, num_cams);
> +
> + /* limit memory so we dont have linear faults */
> + memblock_enforce_memory_limit(linear_map_top);
> + memblock_analyze();
> + }
> +#endif
> +
> /* A sync won't hurt us after mucking around with
> * the MMU configuration
> */
> diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
> index b9d9fed..af405ee 100644
> --- a/arch/powerpc/mm/tlb_nohash_low.S
> +++ b/arch/powerpc/mm/tlb_nohash_low.S
> @@ -367,7 +367,7 @@ _GLOBAL(set_context)
> #error Unsupported processor type !
> #endif
>
> -#if defined(CONFIG_FSL_BOOKE)
> +#if defined(CONFIG_PPC_FSL_BOOK3E)
> /*
> * extern void loadcam_entry(unsigned int index)
> *
^ permalink raw reply
* Re: [PATCH 2/2] ppc: lazy flush_tlb_mm for nohash architectures
From: Benjamin Herrenschmidt @ 2010-10-14 0:52 UTC (permalink / raw)
To: Dave Kleikamp; +Cc: linuxppc-dev list
In-Reply-To: <1285351297-9999-3-git-send-email-shaggy@linux.vnet.ibm.com>
On Fri, 2010-09-24 at 13:01 -0500, Dave Kleikamp wrote:
> On PPC_MMU_NOHASH processors that support a large number of contexts,
> implement a lazy flush_tlb_mm() that switches to a free context, marking
> the old one stale. The tlb is only flushed when no free contexts are
> available.
>
> The lazy tlb flushing is controlled by the global variable tlb_lazy_flush
> which is set during init, dependent upon MMU_FTR_TYPE_47x.
Unless I'm mistaken, there are some issues with that patch... sorry for
the late review, I've been away for a couple of weeks.
> +int tlb_lazy_flush;
> +static int tlb_needs_flush[NR_CPUS];
> +static unsigned long *context_available_map;
> +static unsigned int nr_stale_contexts;
Now I understand what you're doing here, but wouldn't it have been
possible to re-use the existing stale map concept or do you reckon it
would have been too messy ?
At the very least, the "old style" stale map code and "new style" stale
TLB code should be more in sync, you may end up flushing the TLB
twice...
> #define CTX_MAP_SIZE \
> (sizeof(unsigned long) * (last_context / BITS_PER_LONG + 1))
>
> +/*
> + * if another cpu recycled the stale contexts, we need to flush
> + * the local TLB, so that we may re-use those contexts
> + */
> +void flush_recycled_contexts(int cpu)
> +{
> + int i;
> +
> + if (tlb_needs_flush[cpu]) {
> + pr_hard("[%d] flushing tlb\n", cpu);
> + _tlbil_all();
> + for (i = cpu_first_thread_in_core(cpu);
> + i <= cpu_last_thread_in_core(cpu); i++) {
> + tlb_needs_flush[i] = 0;
> + }
> + }
> +}
So far so good :-)
> /* Steal a context from a task that has one at the moment.
> *
> @@ -147,7 +167,7 @@ static unsigned int steal_context_up(unsigned int id)
> pr_hardcont(" | steal %d from 0x%p", id, mm);
>
> /* Flush the TLB for that context */
> - local_flush_tlb_mm(mm);
> + __local_flush_tlb_mm(mm);
>
> /* Mark this mm has having no context anymore */
> mm->context.id = MMU_NO_CONTEXT;
Ok.
> @@ -161,13 +181,19 @@ static unsigned int steal_context_up(unsigned int id)
> #ifdef DEBUG_MAP_CONSISTENCY
> static void context_check_map(void)
> {
> - unsigned int id, nrf, nact;
> + unsigned int id, nrf, nact, nstale;
>
> - nrf = nact = 0;
> + nrf = nact = nstale = 0;
> for (id = first_context; id <= last_context; id++) {
> int used = test_bit(id, context_map);
> - if (!used)
> - nrf++;
> + int allocated = tlb_lazy_flush &&
> + test_bit(id, context_available_map);
> + if (!used) {
> + if (allocated)
> + nstale++;
> + else
> + nrf++;
> + }
> if (used != (context_mm[id] != NULL))
> pr_err("MMU: Context %d is %s and MM is %p !\n",
> id, used ? "used" : "free", context_mm[id]);
> @@ -179,6 +205,11 @@ static void context_check_map(void)
> nr_free_contexts, nrf);
> nr_free_contexts = nrf;
> }
> + if (nstale != nr_stale_contexts) {
> + pr_err("MMU: Stale context count out of sync ! (%d vs %d)\n",
> + nr_stale_contexts, nstale);
> + nr_stale_contexts = nstale;
> + }
> if (nact > num_online_cpus())
> pr_err("MMU: More active contexts than CPUs ! (%d vs %d)\n",
> nact, num_online_cpus());
Cursory glance on the above looks ok.
> @@ -189,6 +220,38 @@ static void context_check_map(void)
> static void context_check_map(void) { }
> #endif
>
> +/*
> + * On architectures that support a large number of contexts, the tlb
> + * can be flushed lazily by picking a new context and making the stale
> + * context unusable until a lazy tlb flush has been issued.
> + *
> + * context_available_map keeps track of both active and stale contexts,
> + * while context_map continues to track only active contexts. When the
> + * lazy tlb flush is triggered, context_map is copied to
> + * context_available_map, making the once-stale contexts available again
> + */
> +static void recycle_stale_contexts(void)
> +{
> + if (nr_free_contexts == 0 && nr_stale_contexts > 0) {
Do an early return and avoid the indentation instead ?
> + unsigned int cpu = smp_processor_id();
> + unsigned int i;
> +
> + pr_hard("[%d] recycling stale contexts\n", cpu);
> + /* Time to flush the TLB's */
> + memcpy(context_available_map, context_map, CTX_MAP_SIZE);
> + nr_free_contexts = nr_stale_contexts;
> + nr_stale_contexts = 0;
> + for_each_online_cpu(i) {
> + if ((i < cpu_first_thread_in_core(cpu)) ||
> + (i > cpu_last_thread_in_core(cpu)))
> + tlb_needs_flush[i] = 1;
> + else
> + tlb_needs_flush[i] = 0; /* This core */
> + }
> + _tlbil_all();
> + }
> +}
> +
> void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
> {
> unsigned int i, id, cpu = smp_processor_id();
> @@ -197,6 +260,8 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
> /* No lockless fast path .. yet */
> raw_spin_lock(&context_lock);
>
> + flush_recycled_contexts(cpu);
> +
Ok so here's the nasty one I think. You need to make sure that whenever
you pick something off the context_available_map, you've done the above
first within the same context_lock section right ? At least before you
actually -use- said context.
So far so good ... but steal_context can drop the lock iirc. So you may
need to re-flush there. Not sure that can happen in practice but better
safe than sorry. I would have preferred seeing that flush near the end
of the function to avoid such problem.
Then, you can end up in cases where you flush the TLB, but your context
is marked stale due to stealing, and flush again. That's one of the
reason I wonder if we can consolidate a bit the two orthogonal
"staleness" concepts we have now.
Granted, stealing on 47x is unlikely, but I have reasons to think that
this lazy flushing will benefit 440 too.
> pr_hard("[%d] activating context for mm @%p, active=%d, id=%d",
> cpu, next, next->context.active, next->context.id);
>
> @@ -227,7 +292,12 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
> id = next_context;
> if (id > last_context)
> id = first_context;
> - map = context_map;
> +
> + if (tlb_lazy_flush) {
> + recycle_stale_contexts();
> + map = context_available_map;
> + } else
> + map = context_map;
>
> /* No more free contexts, let's try to steal one */
> if (nr_free_contexts == 0) {
> @@ -250,6 +320,13 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
> if (id > last_context)
> id = first_context;
> }
> + if (tlb_lazy_flush)
> + /*
> + * In the while loop above, we set the bit in
> + * context_available_map, it also needs to be set in
> + * context_map
> + */
> + __set_bit(id, context_map);
> stolen:
> next_context = id + 1;
> context_mm[id] = next;
> @@ -267,7 +344,7 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
> id, cpu_first_thread_in_core(cpu),
> cpu_last_thread_in_core(cpu));
>
> - local_flush_tlb_mm(next);
> + __local_flush_tlb_mm(next);
>
> /* XXX This clear should ultimately be part of local_flush_tlb_mm */
> for (i = cpu_first_thread_in_core(cpu);
> @@ -317,11 +394,61 @@ void destroy_context(struct mm_struct *mm)
> mm->context.active = 0;
> #endif
> context_mm[id] = NULL;
> - nr_free_contexts++;
> +
> + if (tlb_lazy_flush)
> + nr_stale_contexts++;
> + else
> + nr_free_contexts++;
> }
> raw_spin_unlock_irqrestore(&context_lock, flags);
> }
Now...
> +/*
> + * This is called from flush_tlb_mm(). Mark the current context as stale
> + * and grab an available one. The tlb will be flushed when no more
> + * contexts are available
> + */
> +void lazy_flush_context(struct mm_struct *mm)
> +{
> + unsigned int id;
> + unsigned long flags;
> + unsigned long *map;
> +
> + raw_spin_lock_irqsave(&context_lock, flags);
> +
> + id = mm->context.id;
> + if (unlikely(id == MMU_NO_CONTEXT))
> + goto no_context;
First thing is ... you reproduce quite a bit of logic from
switch_mmu_context() here. Shouldn't it be abstracted in a separate
function ?
The other thing here is that another CPU might have done a
recycle_stale_contexts() before you get here. IE. Your TLB may be stale.
Shouln't you do a flush here ? Since you are picking up a new PID from
the context_available_map, it can potentially be stale if your tlb needs
flushing due to another CPU having just done a recycle.
> + /*
> + * Make the existing context stale. It remains in
> + * context_available_map as long as nr_free_contexts remains non-zero
> + */
> + __clear_bit(id, context_map);
> + context_mm[id] = NULL;
> + nr_stale_contexts++;
> +
> + recycle_stale_contexts();
> + BUG_ON(nr_free_contexts == 0);
> +
> + nr_free_contexts--;
> + id = last_context;
> + map = context_available_map;
> + while (__test_and_set_bit(id, map)) {
> + id = find_next_zero_bit(map, last_context+1, id);
> + if (id > last_context)
> + id = first_context;
> + }
> + set_bit(id, context_map);
> + next_context = id + 1;
> + context_mm[id] = mm;
> + mm->context.id = id;
> + if (current->active_mm == mm)
> + set_context(id, mm->pgd);
> +no_context:
> + raw_spin_unlock_irqrestore(&context_lock, flags);
> +}
> +
> #ifdef CONFIG_SMP
>
> static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
> @@ -407,6 +534,7 @@ void __init mmu_context_init(void)
> } else if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
> first_context = 1;
> last_context = 65535;
> + tlb_lazy_flush = 1;
> } else {
> first_context = 1;
> last_context = 255;
Somebody should measure on 440, might actually improve perfs. Something
like a kernel compile sounds like a good test here.
> @@ -419,6 +547,8 @@ void __init mmu_context_init(void)
> * Allocate the maps used by context management
> */
> context_map = alloc_bootmem(CTX_MAP_SIZE);
> + if (tlb_lazy_flush)
> + context_available_map = alloc_bootmem(CTX_MAP_SIZE);
> context_mm = alloc_bootmem(sizeof(void *) * (last_context + 1));
> stale_map[0] = alloc_bootmem(CTX_MAP_SIZE);
>
> diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
> index 63b84a0..64240f1 100644
> --- a/arch/powerpc/mm/mmu_decl.h
> +++ b/arch/powerpc/mm/mmu_decl.h
> @@ -25,6 +25,14 @@
> #ifdef CONFIG_PPC_MMU_NOHASH
Cheers,
Ben.
^ permalink raw reply
* Re: Please pull 'next' branch of 4xx tree
From: Benjamin Herrenschmidt @ 2010-10-14 0:56 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <20101013131608.GA6154@zod.rchland.ibm.com>
On Wed, 2010-10-13 at 09:16 -0400, Josh Boyer wrote:
> On Tue, Sep 28, 2010 at 09:09:41AM -0400, Josh Boyer wrote:
> >Hi Ben,
> >
> >A few small updates for the next branch. A new board/SoC from AMCC, and
> >some 476 changes from Shaggy. Please pull.
>
> OK, below is a fixed up tree that drops the patch Shaggy said was
> broken, and rebases on top of your new -next branch. Please pull.
please, rebase again without Shaggy's lazy flush patch. I'll handle that
one separately, I think it needs a little bit more massaging.
Cheers,
Ben.
> josh
>
> The following changes since commit 4108d9ba9091c55cfb968d42dd7dcae9a098b876:
>
> powerpc/Makefiles: Change to new flag variables (2010-10-13 16:19:22 +1100)
>
> are available in the git repository at:
> ssh://master.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git next
>
> Dave Kleikamp (1):
> powerpc/476: lazy flush_tlb_mm for nohash architectures
>
> Josh Boyer (1):
> powerpc/44x: Update ppc44x_defconfig
>
> Tirumala Marri (1):
> powerpc/44x: Add support for the AMCC APM821xx SoC
>
> arch/powerpc/boot/dts/bluestone.dts | 254 ++++++++++++++++++++++++++
> arch/powerpc/configs/44x/bluestone_defconfig | 68 +++++++
> arch/powerpc/configs/ppc44x_defconfig | 9 +-
> arch/powerpc/kernel/cpu_setup_44x.S | 1 +
> arch/powerpc/kernel/cputable.c | 15 ++
> arch/powerpc/mm/mmu_context_nohash.c | 154 ++++++++++++++--
> arch/powerpc/mm/mmu_decl.h | 8 +
> arch/powerpc/mm/tlb_nohash.c | 28 +++-
> arch/powerpc/platforms/44x/Kconfig | 16 ++
> arch/powerpc/platforms/44x/ppc44x_simple.c | 1 +
> 10 files changed, 534 insertions(+), 20 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/bluestone.dts
> create mode 100644 arch/powerpc/configs/44x/bluestone_defconfig
^ permalink raw reply
* Re: [git pull] Please pull powerpc.git next branch
From: Benjamin Herrenschmidt @ 2010-10-14 1:02 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.1010131706440.4711@localhost.localdomain>
On Wed, 2010-10-13 at 17:08 -0500, Kumar Gala wrote:
> The following changes since commit 4108d9ba9091c55cfb968d42dd7dcae9a098b876:
>
> powerpc/Makefiles: Change to new flag variables (2010-10-13 16:19:22 +1100)
>
> are available in the git repository at:
> git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Fail :-)
/home/benh/linux-powerpc-test/arch/powerpc/sysdev/fsl_pci.c:494: error: redefinition of 'fsl_pci_immrbar_base'
/home/benh/linux-powerpc-test/arch/powerpc/sysdev/fsl_pci.c:313: note: previous definition of 'fsl_pci_immrbar_base' was here
make[2]: *** [arch/powerpc/sysdev/fsl_pci.o] Error 1
make[2]: *** Waiting for unfinished jobs....
Cheers,
Ben.
> Harninder Rai (1):
> powerpc/fsl: 85xx: add cache-sram support
>
> Ilya Yanok (1):
> powerpc/mpc83xx: Support for MPC8308 P1M board
>
> Kumar Gala (10):
> powerpc/fsl-pci: Fix MSI support on 83xx platforms
> powerpc/mpc8xxx_gpio: Add support for 'qoriq-gpio' controllers
> powerpc/fsl-booke: Add PCI device ids for P2040/P3041/P5010/P5020 QoirQ chips
> powerpc/fsl-booke: Add p3041 DS board support
> powerpc: Fix compile error with paca code on ppc64e
> powerpc/fsl-booke: Add support for FSL 64-bit e5500 core
> powerpc/fsl-booke: Add support for FSL Arch v1.0 MMU in setup_page_sizes
> powerpc/fsl-booke64: Use TLB CAMs to cover linear mapping on FSL 64-bit chips
> powerpc/fsl-booke: Add p5020 DS board support
> powerpc/fsl-booke: Add e55xx (64-bit) smp defconfig
>
> Matthew McClintock (6):
> powerpc/kexec: make masking/disabling interrupts generic
> powerpc/85xx: Remove call to mpic_teardown_this_cpu in kexec
> powerpc/85xx: Minor fixups for kexec on 85xx
> powerpc/85xx: flush dcache before resetting cores
> powerpc/fsl_soc: Search all global-utilities nodes for rstccr
> powerpc/fsl_booke: Add support to boot from core other than 0
>
> Paul Gortmaker (1):
> powerpc: Fix invalid page flags in create TLB CAM path for PTE_64BIT
>
> Scott Wood (1):
> oprofile/fsl emb: Don't set MSR[PMM] until after clearing the interrupt.
>
> Timur Tabi (4):
> powerpc: export ppc_proc_freq and ppc_tb_freq as GPL symbols
> powerpc/watchdog: Allow the Book-E driver to be compiled as a module
> powerpc/p1022: Add probing for individual DMA channels
> powerpc/85xx: add ngPIXIS FPGA device tree node to the P1022DS board
>
> arch/powerpc/boot/dts/mpc8308_p1m.dts | 332 ++++++++++++++++++++++++
> arch/powerpc/boot/dts/p1022ds.dts | 11 +
> arch/powerpc/configs/e55xx_smp_defconfig | 84 ++++++
> arch/powerpc/configs/ppc64e_defconfig | 4 +-
> arch/powerpc/include/asm/fsl_85xx_cache_sram.h | 48 ++++
> arch/powerpc/include/asm/kexec.h | 1 +
> arch/powerpc/include/asm/mmu-book3e.h | 15 +
> arch/powerpc/include/asm/pte-common.h | 7 +
> arch/powerpc/kernel/Makefile | 4 +-
> arch/powerpc/kernel/asm-offsets.c | 4 +-
> arch/powerpc/kernel/cpu_setup_fsl_booke.S | 15 +
> arch/powerpc/kernel/cputable.c | 28 ++-
> arch/powerpc/kernel/crash.c | 13 +-
> arch/powerpc/kernel/head_fsl_booke.S | 10 +-
> arch/powerpc/kernel/machine_kexec.c | 24 ++
> arch/powerpc/kernel/machine_kexec_32.c | 4 +
> arch/powerpc/kernel/paca.c | 2 +-
> arch/powerpc/kernel/setup_32.c | 2 +-
> arch/powerpc/kernel/time.c | 3 +-
> arch/powerpc/kernel/traps.c | 5 +
> arch/powerpc/mm/Makefile | 2 +-
> arch/powerpc/mm/fsl_booke_mmu.c | 15 +-
> arch/powerpc/mm/mmu_decl.h | 5 +-
> arch/powerpc/mm/tlb_nohash.c | 56 ++++-
> arch/powerpc/mm/tlb_nohash_low.S | 2 +-
> arch/powerpc/oprofile/op_model_fsl_emb.c | 15 +-
> arch/powerpc/platforms/83xx/Kconfig | 4 +-
> arch/powerpc/platforms/83xx/mpc830x_rdb.c | 3 +-
> arch/powerpc/platforms/85xx/Kconfig | 28 ++-
> arch/powerpc/platforms/85xx/Makefile | 2 +
> arch/powerpc/platforms/85xx/p1022_ds.c | 2 +
> arch/powerpc/platforms/85xx/p3041_ds.c | 64 +++++
> arch/powerpc/platforms/85xx/p5020_ds.c | 69 +++++
> arch/powerpc/platforms/85xx/smp.c | 76 +++++-
> arch/powerpc/platforms/Kconfig.cputype | 8 +-
> arch/powerpc/sysdev/Makefile | 1 +
> arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h | 101 +++++++
> arch/powerpc/sysdev/fsl_85xx_cache_sram.c | 159 +++++++++++
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 231 ++++++++++++++++
> arch/powerpc/sysdev/fsl_msi.c | 9 +-
> arch/powerpc/sysdev/fsl_pci.c | 51 ++++-
> arch/powerpc/sysdev/fsl_pci.h | 1 +
> arch/powerpc/sysdev/fsl_soc.c | 20 +-
> arch/powerpc/sysdev/mpc8xxx_gpio.c | 3 +
> drivers/watchdog/Kconfig | 5 +-
> drivers/watchdog/booke_wdt.c | 39 +++-
> include/linux/pci_ids.h | 8 +
> 47 files changed, 1516 insertions(+), 79 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/mpc8308_p1m.dts
> create mode 100644 arch/powerpc/configs/e55xx_smp_defconfig
> create mode 100644 arch/powerpc/include/asm/fsl_85xx_cache_sram.h
> create mode 100644 arch/powerpc/platforms/85xx/p3041_ds.c
> create mode 100644 arch/powerpc/platforms/85xx/p5020_ds.c
> create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
> create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_sram.c
> create mode 100644 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
^ permalink raw reply
* Re: Questions on interrupt vector assignment on MPC8641D
From: tiejun.chen @ 2010-10-14 1:39 UTC (permalink / raw)
To: Scott Wood; +Cc: david.hagood, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <20101013102815.2959fcb6@udp111988uds.am.freescale.net>
Scott Wood wrote:
> On Wed, 13 Oct 2010 09:17:01 +0800
> "tiejun.chen" <tiejun.chen@windriver.com> wrote:
>
>> Scott Wood wrote:
>>> The crash is happening somewhere in mpic_set_irq_type():
>> Agreed. That is just where I pointed out on my email replied for OOPS. To enable
>> DBG to figure out 'src' and 'mpic->irq_count' from the file,
>> arch/powerpc/sysdev/mpic.c, .
>> ======
>> int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
>> {
>> ......
>> if (src >= mpic->irq_count)
>> return -EINVAL;
>> ^
>> I think this OOPS may be from here.
>
> No, it's after that. His board code is using the mpic's "isu" remapping
I means OOPS is *from* here. According to David's call trace,
mpic_set_irq_type() is the last issued function. And that corresponding return
value, R3, is '0xffffffea', -22, and also '-EINVAL'. If everything is OK, I
think we should not be failed with returning '-EINVAL' here. Right? So I think
we should dump 'src' (mpic_irq_to_hw(virq)) and 'mpic->irq_count'. Then figure
out why 'src' >= 'mpic->irq_count'. I think this can make our debug life easier.
Tiejun
> mechanism, and the MSIs aren't covered, so those registers aren't
> ioremapped.
>
> -Scott
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
* Re: [PATCH 2/2] [v2] powerpc/85xx: add DIU support to the Freecale P1022DS reference board
From: Tabi Timur-B04825 @ 2010-10-14 1:39 UTC (permalink / raw)
To: Gala Kumar-B11780; +Cc: linuxppc-dev
In-Reply-To: <C692EF20-D7BD-4381-93F8-D1AA58BA89C4@freescale.com>
S3VtYXIgR2FsYSB3cm90ZToNCj4+ID4gIGFyY2gvcG93ZXJwYy9jb25maWdzL21wYzg1eHhfZGVm
Y29uZmlnICAgICB8ICAgIDMgKw0KPj4gPiAgYXJjaC9wb3dlcnBjL2NvbmZpZ3MvbXBjODV4eF9z
bXBfZGVmY29uZmlnIHwgICAgMyArDQo+PiA+ICBhcmNoL3Bvd2VycGMvcGxhdGZvcm1zLzg1eHgv
cDEwMjJfZHMuYyAgICAgfCAgMjEzICsrKysrKysrKysrKysrKysrKysrKysrKysrKy0NCj4+ID4g
IDMgZmlsZXMgY2hhbmdlZCwgMjE3IGluc2VydGlvbnMoKyksIDIgZGVsZXRpb25zKC0pDQo+IEkg
ZHJvcHBlZCB0aGlzIGJlY2F1c2Ugb2YgY2hpY2tlbi9lZ2cgaXNzdWUgd2l0aCBndXRzLmgNCg0K
SWYgeW91IHB1bGwgZnJvbSBhbHNhLW5leHQsIGl0IHNob3VsZCByZXNvbHZlIHRoYXQuDQoNCkVp
dGhlciB0aGF0LCBvciBhc2sgdGhlIGFsc2EgZ3V5cyB0byBhcHBseSB0aGlzIHBhdGNoIGluc3Rl
YWQuDQoNCi0tIA0KVGltdXIgVGFiaQ0KTGludXgga2VybmVsIGRldmVsb3Blcg0K
^ permalink raw reply
* [PATCH 2/3] fsl_rio: fix non-standard HID1 register access
From: Shaohui Xie @ 2010-10-14 2:04 UTC (permalink / raw)
To: linuxppc-dev; +Cc: alexandre.bounine, b21989
From: Li Yang <leoli@freescale.com>
The access to HID1 register is only legitimate for e500 v1/v2 cores.
Also fixes magic number.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
---
arch/powerpc/sysdev/fsl_rio.c | 9 ++++++---
1 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 4127636..dfff3b7 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -1537,9 +1537,12 @@ int fsl_rio_setup(struct platform_device *dev)
#ifdef CONFIG_E500
saved_mcheck_exception = ppc_md.machine_check_exception;
ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
-#endif
- /* Ensure that RFXE is set */
- mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));
+
+#ifndef CONFIG_PPC_E500MC
+ /* Ensure that RFXE is set on e500 v1/v2 */
+ mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | HID1_RFXE));
+#endif /* !PPC_E500MC */
+#endif /* E500 */
return 0;
err:
--
1.6.4
^ permalink raw reply related
* [PATCH 1/3] fsl_rio: Add comments for sRIO registers.
From: Shaohui Xie @ 2010-10-14 2:04 UTC (permalink / raw)
To: linuxppc-dev; +Cc: alexandre.bounine, b21989
Add some comments to make sRIO registers map better readable.
Signed-off-by: Shaohui Xie <b21989@freescale.com>
---
arch/powerpc/sysdev/fsl_rio.c | 65 +++++++++++++++++++++++++----------------
1 files changed, 40 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 3017532..4127636 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -117,44 +117,59 @@ struct rio_atmu_regs {
};
struct rio_msg_regs {
- u32 omr;
- u32 osr;
+ u32 omr; /* 0xD_3000 - Outbound message 0 mode register */
+ u32 osr; /* 0xD_3004 - Outbound message 0 status register */
u32 pad1;
- u32 odqdpar;
+ u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue
+ dequeue pointer address register */
u32 pad2;
- u32 osar;
- u32 odpr;
- u32 odatr;
- u32 odcr;
+ u32 osar; /* 0xD_3014 - Outbound message 0 source address
+ register */
+ u32 odpr; /* 0xD_3018 - Outbound message 0 destination port
+ register */
+ u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes
+ Register*/
+ u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count
+ register */
u32 pad3;
- u32 odqepar;
+ u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue
+ enqueue pointer address register */
u32 pad4[13];
- u32 imr;
- u32 isr;
+ u32 imr; /* 0xD_3060 - Inbound message 0 mode register */
+ u32 isr; /* 0xD_3064 - Inbound message 0 status register */
u32 pad5;
- u32 ifqdpar;
+ u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue
+ pointer address register*/
u32 pad6;
- u32 ifqepar;
+ u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue
+ pointer address register */
u32 pad7[226];
- u32 odmr;
- u32 odsr;
+ u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
+ u32 odsr; /* 0xD_3404 - Outbound doorbell status register */
u32 res0[4];
- u32 oddpr;
- u32 oddatr;
+ u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port
+ register */
+ u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes
+ register */
u32 res1[3];
- u32 odretcr;
+ u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold
+ configuration register */
u32 res2[12];
- u32 dmr;
- u32 dsr;
+ u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */
+ u32 dsr; /* 0xD_3464 - Inbound doorbell status register */
u32 pad8;
- u32 dqdpar;
+ u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer
+ address register */
u32 pad9;
- u32 dqepar;
+ u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
+ address register */
u32 pad10[26];
- u32 pwmr;
- u32 pwsr;
- u32 epwqbar;
- u32 pwqbar;
+ u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */
+ u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */
+ u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address
+ register */
+ u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address
+ register */
};
struct rio_tx_desc {
--
1.6.4
^ permalink raw reply related
* [PATCH 3/3] rapidio, powerpc/85xx: Error interrupt handler for sRIO.
From: Shaohui Xie @ 2010-10-14 2:04 UTC (permalink / raw)
To: linuxppc-dev; +Cc: alexandre.bounine, b21989
The sRIO controller reports errors to the core with one signal, it uses
register EPWISR to provides the core quick access to where the error occurred.
The EPWISR indicates that there are 4 interrupts sources, port1, port2, message
unit and port write receive, but the sRIO driver does not support port2
for now, still the handler takes care of port2.
Currently the handler only clear error status without any recovery.
Signed-off-by: Shaohui Xie <b21989@freescale.com>
---
arch/powerpc/sysdev/fsl_rio.c | 81 ++++++++++++++++++++++++++++++++++++++---
1 files changed, 76 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index dfff3b7..be7cc98 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -10,7 +10,7 @@
* - Added Port-Write message handling
* - Added Machine Check exception handling
*
- * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007, 2008, 2010 Freescale Semiconductor, Inc.
* Zhang Wei <wei.zhang@freescale.com>
*
* Copyright 2005 MontaVista Software, Inc.
@@ -47,10 +47,36 @@
#define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
#define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq)
+/* EPWISR Error match value */
+#define EPWISR_ERR_PINT1 0x80000000
+#define EPWISR_ERR_PINT2 0x40000000
+#define EPWISR_ERR_MU 0x2
+#define EPWISR_ERR_PW 0x1
+
+#define IPWMR_CLEAR_QUEUE 0x00000002
+#define IPWSR_CLEAR 0x98
+#define OMSR_CLEAR 0x1cb3
+#define IMSR_CLEAR 0x491
+#define IDSR_CLEAR 0x91
+#define ODSR_CLEAR 0x1c00
+#define LTLEECSR_ENABLE_ALL 0xFFC000FC
+#define ESCSR_CLEAR 0x07120204
+
+#define RIO_EDCSR 0x0640
+#define PORT2_RIO_EDCSR 0x0680
+#define RIO_IECSR 0x10130
+#define PORT2_RIO_IECSR 0x101B0
+#define RIO_IM0SR 0x13064
+#define RIO_IM1SR 0x13164
+#define RIO_OM0SR 0x13004
+#define RIO_OM1SR 0x13104
+
+#define RIO_EPWISR_OFFSET 0x10010
#define RIO_ATMU_REGS_OFFSET 0x10c00
#define RIO_P_MSG_REGS_OFFSET 0x11000
#define RIO_S_MSG_REGS_OFFSET 0x13000
#define RIO_ESCSR 0x158
+#define PORT2_RIO_ESCSR 0x178
#define RIO_CCSR 0x15c
#define RIO_LTLEDCSR 0x0608
#define RIO_LTLEDCSR_IER 0x80000000
@@ -1007,6 +1033,38 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
return IRQ_HANDLED;
}
+void port_error_handler(struct rio_mport *port, int offset)
+{
+ /*XXX: Error recovery is not implemented, we just clear errors */
+ out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
+
+ if (offset == 0) {
+ out_be32((u32 *)(rio_regs_win + RIO_EDCSR), 0);
+ out_be32((u32 *)(rio_regs_win + RIO_IECSR), 0);
+ out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
+ } else {
+ out_be32((u32 *)(rio_regs_win + PORT2_RIO_EDCSR), 0);
+ out_be32((u32 *)(rio_regs_win + PORT2_RIO_IECSR), 0);
+ out_be32((u32 *)(rio_regs_win + PORT2_RIO_ESCSR), ESCSR_CLEAR);
+ }
+}
+
+void msg_unit_error_handler(struct rio_mport *port)
+{
+ struct rio_priv *priv = port->priv;
+
+ /*XXX: Error recovery is not implemented, we just clear errors */
+ out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR);
+ out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR);
+ out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR);
+ out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR);
+
+ out_be32(&priv->msg_regs->odsr, ODSR_CLEAR);
+ out_be32(&priv->msg_regs->dsr, IDSR_CLEAR);
+
+ out_be32(&priv->msg_regs->pwsr, IPWSR_CLEAR);
+}
+
/**
* fsl_rio_doorbell_init - MPC85xx doorbell interface init
* @mport: Master port implementing the inbound doorbell unit
@@ -1086,13 +1144,24 @@ fsl_rio_port_write_handler(int irq, void *dev_instance)
ipwsr = in_be32(&priv->msg_regs->pwsr);
epwisr = in_be32(priv->regs_win + RIO_EPWISR);
- if (epwisr & 0x80000000) {
+ if (epwisr & EPWISR_ERR_PINT1) {
tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
pr_info("RIO_LTLEDCSR = 0x%x\n", tmp);
out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
+ port_error_handler(port, 0);
+ }
+
+ if (epwisr & EPWISR_ERR_PINT2) {
+ pr_info("RIO: port2 error\n");
+ port_error_handler(port, 1);
+ }
+
+ if (epwisr & EPWISR_ERR_MU) {
+ pr_info("RIO: message unit error\n");
+ msg_unit_error_handler(port);
}
- if (!(epwisr & 0x00000001))
+ if (!(epwisr & EPWISR_ERR_PW))
return IRQ_HANDLED;
#ifdef DEBUG_PW
@@ -1253,12 +1322,14 @@ static int fsl_rio_port_write_init(struct rio_mport *mport)
/* Hook up port-write handler */
- rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0,
- "port-write", (void *)mport);
+ rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler,
+ IRQF_SHARED, "port-write", (void *)mport);
if (rc < 0) {
pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
goto err_out;
}
+ /* Enable Error Interrupt */
+ out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
INIT_WORK(&priv->pw_work, fsl_pw_dpc);
spin_lock_init(&priv->pw_fifo_lock);
--
1.6.4
^ permalink raw reply related
* RE: [PATCH 2/3 v4] P4080/mtd: Only make elbc nand driver detect nand flash partitions
From: Zang Roy-R61911 @ 2010-10-14 3:09 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: dedekind1, Hu Mingkai-B21284, Lan Chunhe-B25806, linuxppc-dev,
linux-mtd, akpm, dwmw2, Gala Kumar-B11780
In-Reply-To: <20101004103813.14d04956@udp111988uds.am.freescale.net>
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Monday, October 04, 2010 23:38 PM
> To: Zang Roy-R61911
> Cc: Anton Vorontsov; linux-mtd@lists.infradead.org;
dwmw2@infradead.org;
> dedekind1@gmail.com; akpm@linux-foundation.org; Lan Chunhe-B25806;
Wood Scott-
> B07421; Gala Kumar-B11780; linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH 2/3 v4] P4080/mtd: Only make elbc nand driver
detect nand
> flash partitions
>=20
> On Sat, 2 Oct 2010 05:36:27 -0700
> "Zang Roy-R61911" <r61911@freescale.com> wrote:
>=20
> >
> >
> > > -----Original Message-----
> > > From: Anton Vorontsov [mailto:cbouatmailru@gmail.com]
> > > Sent: Monday, September 20, 2010 21:19 PM
> > > To: Zang Roy-R61911
> > > Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org;
> dedekind1@gmail.com;
> > > akpm@linux-foundation.org; Lan Chunhe-B25806; Wood Scott-B07421;
Gala
> Kumar-
> > > B11780; linuxppc-dev@ozlabs.org
> > > Subject: Re: [PATCH 2/3 v4] P4080/mtd: Only make elbc nand driver
detect
> nand
> > > flash partitions
> > >
> > > On Fri, Sep 17, 2010 at 03:01:08PM +0800, Roy Zang wrote:
> > > [...]
> > > > +static struct mutex fsl_elbc_nand_mutex;
> > > > +
> > > > +static int __devinit fsl_elbc_nand_probe(struct platform_device
*dev)
> > > > {
> > > > - struct fsl_lbc_regs __iomem *lbc =3D ctrl->regs;
> > > > + struct fsl_lbc_regs __iomem *lbc;
> > > > struct fsl_elbc_mtd *priv;
> > > > struct resource res;
> > > > + struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl =3D NULL;
> > >
> > > No need for =3D NULL.
> > Any harm? Or just personal habit or style? Can you explain about
why?
>=20
> Besides not wanting superfluous code on general principle, it could
> hide a bug if in the future the real initialization is missing on some
> code path. It would become a runtime NULL dereference rather than a
> compiler warning.
Not exactly.
Per my understand, if the pointer will definitely be assigned in code
path,
it is not necessary to init it when define. for example,
char c;
char b;
char *a;
if (condition)
a =3D &c;
else
a =3D &b;
...
for other case, if the path will not ensure the pointer assignment, it
will be inited
when define to avoid warning. for example,
char c;
char *a =3D NULL;
if (condition)
a =3D &c;
...
Thanks.
Roy
^ permalink raw reply
* Re: Questions on interrupt vector assignment on MPC8641D
From: tiejun.chen @ 2010-10-14 3:27 UTC (permalink / raw)
To: tiejun.chen; +Cc: Scott Wood, david.hagood, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <4CB65F6F.1090103@windriver.com>
tiejun.chen wrote:
> Scott Wood wrote:
>> On Wed, 13 Oct 2010 09:17:01 +0800
>> "tiejun.chen" <tiejun.chen@windriver.com> wrote:
>>
>>> Scott Wood wrote:
>>>> The crash is happening somewhere in mpic_set_irq_type():
>>> Agreed. That is just where I pointed out on my email replied for OOPS. To enable
>>> DBG to figure out 'src' and 'mpic->irq_count' from the file,
>>> arch/powerpc/sysdev/mpic.c, .
>>> ======
>>> int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
>>> {
>>> ......
>>> if (src >= mpic->irq_count)
>>> return -EINVAL;
>>> ^
>>> I think this OOPS may be from here.
>> No, it's after that. His board code is using the mpic's "isu" remapping
>
> I means OOPS is *from* here. According to David's call trace,
> mpic_set_irq_type() is the last issued function. And that corresponding return
> value, R3, is '0xffffffea', -22, and also '-EINVAL'. If everything is OK, I
> think we should not be failed with returning '-EINVAL' here. Right? So I think
> we should dump 'src' (mpic_irq_to_hw(virq)) and 'mpic->irq_count'. Then figure
> out why 'src' >= 'mpic->irq_count'. I think this can make our debug life easier.
>
Certainly I'm missing something since I have no any real environment. So maybe
we can use gdb to track this panic as normal :)
# gdb vmlinux
(gdb) list *mpic_set_irq_type+0x188/
Tiejun
> Tiejun
>
>> mechanism, and the MSIs aren't covered, so those registers aren't
>> ioremapped.
>>
>> -Scott
>>
>> _______________________________________________
>> Linuxppc-dev mailing list
>> Linuxppc-dev@lists.ozlabs.org
>> https://lists.ozlabs.org/listinfo/linuxppc-dev
>>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
* RE: [PATCH 2/3] fsl_rio: fix non-standard HID1 register access
From: Li Yang-R58472 @ 2010-10-14 3:23 UTC (permalink / raw)
To: Xie Shaohui-B21989, linuxppc-dev; +Cc: alexandre.bounine
In-Reply-To: <1287021866-22095-1-git-send-email-b21989@freescale.com>
>Subject: [PATCH 2/3] fsl_rio: fix non-standard HID1 register access
>
>From: Li Yang <leoli@freescale.com>
>
>The access to HID1 register is only legitimate for e500 v1/v2 cores.
>Also fixes magic number.
>
>Signed-off-by: Li Yang <leoli@freescale.com>
>Signed-off-by: Shaohui Xie <b21989@freescale.com>
This patch is depending on another patch at
http://patchwork.ozlabs.org/patch/56138/
- Leo
>---
> arch/powerpc/sysdev/fsl_rio.c | 9 ++++++---
> 1 files changed, 6 insertions(+), 3 deletions(-)
>
>diff --git a/arch/powerpc/sysdev/fsl_rio.c =
b/arch/powerpc/sysdev/fsl_rio.c
>index 4127636..dfff3b7 100644
>--- a/arch/powerpc/sysdev/fsl_rio.c
>+++ b/arch/powerpc/sysdev/fsl_rio.c
>@@ -1537,9 +1537,12 @@ int fsl_rio_setup(struct platform_device *dev)
> #ifdef CONFIG_E500
> saved_mcheck_exception =3D ppc_md.machine_check_exception;
> ppc_md.machine_check_exception =3D fsl_rio_mcheck_exception;
>-#endif
>- /* Ensure that RFXE is set */
>- mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));
>+
>+#ifndef CONFIG_PPC_E500MC
>+ /* Ensure that RFXE is set on e500 v1/v2 */
>+ mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | HID1_RFXE));
>+#endif /* !PPC_E500MC */
>+#endif /* E500 */
>
> return 0;
> err:
>--
>1.6.4
^ permalink raw reply
* RE: [PATCH 2/3 v4] P4080/mtd: Only make elbc nand driver detect nand flash partitions
From: Zang Roy-R61911 @ 2010-10-14 4:14 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Wood Scott-B07421, dedekind1, Lan Chunhe-B25806, linuxppc-dev,
linux-mtd, akpm, dwmw2, Gala Kumar-B11780
In-Reply-To: <20100920131907.GA2184@oksana.dev.rtsoft.ru>
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^ permalink raw reply
* Re: ppc405 + MCP23S17
From: tiejun.chen @ 2010-10-14 5:03 UTC (permalink / raw)
To: WANG YiFei; +Cc: linuxppc-dev
In-Reply-To: <BAY158-ds774A2E0B753853E1C0CF0F5550@phx.gbl>
WANG YiFei wrote:
> Hi TieJun,
>
> I saw you name in \arch\powerpc\boot\cuboot-kilauea.c,
> I think I found right person for help, since our board
Unfortunately I'm not do anything for SPI resided on Kilauea.
> is based on Kilauea evaluation board, and currently I
> used 40x/kilauea_defconfig to config kernel. Also I used
> Kilauea.dts as starting point to modify as shown in my
> previous email.
> As you know, Kilauea board doesn't have any spi devices
> on spi bus, however, our board has an mcp23s17 on it. So
> far, I didn't add/change kernel/driver code. Looking at
> mcp23s08.c's probe() routine:
>
> static int mcp23s08_probe(struct spi_device *spi)
> {
> struct mcp23s08_platform_data *pdata;
> unsigned addr;
> unsigned chips = 0;
> struct mcp23s08_driver_data *data;
> int status;
> unsigned base;
>
> pdata = spi->dev.platform_data;
> if (!pdata || !gpio_is_valid(pdata->base)) {
> dev_dbg(&spi->dev, "invalid or missing platform data\n");
> return -EINVAL;
> }
> ......
>
> Obviously, if I don't pass any platform_data to mcp23s08 device,
> it will always fail. That means this mcp23s08 driver always needs
> a platform_data to associate with, I don't know if this is the correct
> behavior. Anyway, so my question is: is my modified dts files(as in
> previous email) correct? what info else do I need to add in to support
The dts should be depended what are used for mcp23s07 at last.
Actually I think you can register spi_board_info with some corresponding
information firstly to begin debugging your driver. When you can run your spi
driver successfully, then generate the real dts according to those appropriate
parameters and implement one parsing hook converted dts info to
spi_board_info/platform_data.
> platform_data in dts file? Or if this dts is correct, then where is the
You should provide one struct mcp23s08_platform_data. But maybe some fields are
not necessary so you should check what are needed by pdata of your mcp23s08_probe().
> right place(which .c file) to set/pass platform_data to?
You can create the file, arch/powerpc/sysdev/ppc4xx_spi.c, like ppc4xx_gpio.c.
As I pointed previously you should check the example file, I think you can refer
to the file, arch/powerpc/platforms/83xx/mpc832x_rdb.c. There is one example to
show how to parse dts to register spi_board_info.
Tiejun
>
>
> Regards,
> YiFei
>
>
> -----Original Message-----
> From: tiejun.chen [mailto:tiejun.chen@windriver.com]
> Sent: Wednesday, 13 October, 2010 3:50 PM
> To: WANG YiFei
> Cc: linuxppc-dev@ozlabs.org
> Subject: Re: ppc405 + MCP23S17
>
> WANG YiFei wrote:
>> Hi TieJun,
>>
>> Thanks a lot for your reply.
>> So far, I can get ppc405 spi to initialize, however
>> failed at MCP23S17's probe() routine, I checked the
>> code, it's due to un-initialized platform data. Here
>> is my part of dts:
>>
>> spi@ef600600 {
>> device_type = "spi";
>> compatible = "ibm,ppc4xx-spi", "ibm,spi";
>> reg = <0xef600600 0x7>;
>> interrupt-parent = <0x2>;
>> interrupts = <0x8 0x4>;
>> #address-cells = <0x1>;
>> #size-cells = <0x0>;
>> gpios = <0>; /* cs */
>>
>> spi_gpio@0 {
>> compatible = "mcp,mcp23s08";
>> spi-max-frequency = <1000000>;
>> reg = <0>;
>> };
>> };
>>
>> I don't know how to provide platform data from dts although
>> I understand the concept from code. Do I only need to modify
>> dts OR I need to write some code to supply platform data? Do
>> you have any URL or sample code to show passing of platform
>> data?
>
> Often you SPI bus driver should call spi_register_master() to register your SPI
> master controller. Then please go to the following path:
> ======
> spi_register_master()
> |
> + scan_boardinfo()
> |
> + spi_new_device()
> ^
> Here refer to the function,
> ------
> struct spi_device *spi_new_device(struct spi_master *master,
> struct spi_board_info *chip)
> {
> struct spi_device *proxy;
> ......
> proxy->dev.platform_data = (void *) chip->platform_data;
> ......
> status = spi_add_device(proxy);
> ......
>
> And as I previously comment 'spi->dev.platform_data' would be passed to your
> platform_data resided in your probe hook within your spi device driver.
>
> So firstly you should register call spi_register_board_info() to register one
> given spi_board_info by parsing your device nodes from your dts.
>
> I think you can refer to the file, arch/powerpc/platforms/83xx/mpc832x_rdb.c.
>
>> Anyway, thanks a lot for guiding me.
>
> You're welcome :)
>
> Tiejun
>
>> YiFei
>>
>> -----Original Message-----
>> From: tiejun.chen [mailto:tiejun.chen@windriver.com]
>> Sent: Wednesday, October 13, 2010 11:09 AM
>> To: WANG YiFei
>> Cc: linuxppc-dev@ozlabs.org
>> Subject: Re: ppc405 + MCP23S17
>>
>> WANG YiFei wrote:
>>> Hi,
>>>
>>>
>>>
>>> I'm a newbie for linux device driver development.
>>>
>>> We have a custom ppc405 board which has MCP23S17
>>>
>>> (16-Bit I/O Expander with SPI Interface) on it.
>>>
>>> I noticed that current kernel has MCP23S08 driver
>>>
>>> support, I'd like to know:
>>>
>>> 1. if passing platform data to MCP23S08 driver, can it make
>>>
>>> MCP23S17 work?
>>>
>> These chips should be same vendor product so I think 16-bit mcp23s17 may be
>> compatible to 8-bit modes. But you have to check the data sheet to confirm this
>> and track how to configure that as 8-bit mode. After that it's possible to run
>> mcp23s17 with mcp23s08.c.
>>
>>> 2. Generally, I'd like to know how to pass platform data to
>>>
>>> a particular device driver. In my mind, platform data should
>>>
>>> not be in driver code, right? However, I don't know where is
>> Firstly you should define this on your dts. Then parse that to register
>> corresponding of_platform_device or platform_device when you setup your target
>> on <your target>.c.
>>
>> When spi_register_driver prober successfully, you can get the platform_data from
>> associated spi device.
>>
>>> the suitable place to pass platform data to driver.
>>>
>>> 3. How to describe this in dts file?
>>>
>> You can get more from the file, Documentation/powerpc/dts-bindings/spi-bus.txt.
>> Or refer to those existed spi nodes on other platform dts.
>>
>> Tiejun
>>
>>>
>>>
>>> Thanks in advance,
>>>
>>> YiFei
>>>
>>>
>>>
>>>
>
>
^ permalink raw reply
* [PATCH v2] powerpc/fsl-pci: Fix MSI support on 83xx platforms
From: Kumar Gala @ 2010-10-14 5:57 UTC (permalink / raw)
To: linuxppc-dev
The following commit broke 83xx because it assumed the 83xx platforms
exposed the "IMMR" address in BAR0 like the 85xx/86xx/QoriQ devices do:
commit 3da34aae03d498ee62f75aa7467de93cce3030fd
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Tue May 12 15:51:56 2009 -0500
powerpc/fsl: Support unique MSI addresses per PCIe Root Complex
However that is not true, so we have to search through the inbound
window settings on 83xx to find which one matches the IMMR address to
determine its PCI address.
Reported-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
* Its possible that we build 83xx and 86xx together and thus
fsl_pci_immrbar_base needs to deal with that. Introduce a simple global
is_mpc83xx_pci that we change for such a case.
arch/powerpc/sysdev/fsl_msi.c | 9 +++----
arch/powerpc/sysdev/fsl_pci.c | 52 +++++++++++++++++++++++++++++++++++++++-
arch/powerpc/sysdev/fsl_pci.h | 1 +
3 files changed, 55 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 87991d3..20cdcd2 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -24,6 +24,7 @@
#include <asm/ppc-pci.h>
#include <asm/mpic.h>
#include "fsl_msi.h"
+#include "fsl_pci.h"
LIST_HEAD(msi_head);
@@ -125,13 +126,11 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
{
struct fsl_msi *msi_data = fsl_msi_data;
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
- u32 base = 0;
+ u64 base = fsl_pci_immrbar_base(hose);
- pci_bus_read_config_dword(hose->bus,
- PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
+ msg->address_lo = msi_data->msi_addr_lo + lower_32_bits(base);
+ msg->address_hi = msi_data->msi_addr_hi + upper_32_bits(base);
- msg->address_lo = msi_data->msi_addr_lo + base;
- msg->address_hi = msi_data->msi_addr_hi;
msg->data = hwirq;
pr_debug("%s: allocated srs: %d, ibs: %d\n",
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4ae9332..505c8f0 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1,7 +1,7 @@
/*
* MPC83xx/85xx/86xx PCI/PCIE support routing.
*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
* Copyright 2008-2009 MontaVista Software, Inc.
*
* Initial author: Xianghua Xiao <x.xiao@freescale.com>
@@ -34,7 +34,7 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
-static int fsl_pcie_bus_fixup;
+static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
{
@@ -430,6 +430,13 @@ struct mpc83xx_pcie_priv {
u32 dev_base;
};
+struct pex_inbound_window {
+ u32 ar;
+ u32 tar;
+ u32 barl;
+ u32 barh;
+};
+
/*
* With the convention of u-boot, the PCIE outbound window 0 serves
* as configuration transactions outbound.
@@ -437,6 +444,8 @@ struct mpc83xx_pcie_priv {
#define PEX_OUTWIN0_BAR 0xCA4
#define PEX_OUTWIN0_TAL 0xCA8
#define PEX_OUTWIN0_TAH 0xCAC
+#define PEX_RC_INWIN_BASE 0xE60
+#define PEX_RCIWARn_EN 0x1
static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
{
@@ -604,6 +613,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
const int *bus_range;
int primary;
+ is_mpc83xx_pci = 1;
+
if (!of_device_is_available(dev)) {
pr_warning("%s: disabled by the firmware.\n",
dev->full_name);
@@ -683,3 +694,40 @@ err0:
return ret;
}
#endif /* CONFIG_PPC_83xx */
+
+u64 fsl_pci_immrbar_base(struct pci_controller *hose)
+{
+#ifdef CONFIG_PPC_83xx
+ if (is_mpc83xx_pci) {
+ struct mpc83xx_pcie_priv *pcie = hose->dn->data;
+ struct pex_inbound_window *in;
+ int i;
+
+ /* Walk the Root Complex Inbound windows to match IMMR base */
+ in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
+ for (i = 0; i < 4; i++) {
+ /* not enabled, skip */
+ if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
+ continue;
+
+ if (get_immrbase() == in_le32(&in[i].tar))
+ return (u64)in_le32(&in[i].barh) << 32 |
+ in_le32(&in[i].barl);
+ }
+
+ printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
+ }
+#endif
+
+#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
+ if (!is_mpc83xx_pci) {
+ u32 base;
+
+ pci_bus_read_config_dword(hose->bus,
+ PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
+ return base;
+ }
+#endif
+
+ return 0;
+}
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index a9d8bbe..8ad72a1 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -88,6 +88,7 @@ struct ccsr_pci {
extern int fsl_add_bridge(struct device_node *dev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
+u64 fsl_pci_immrbar_base(struct pci_controller *hose);
#endif /* __POWERPC_FSL_PCI_H */
#endif /* __KERNEL__ */
--
1.7.2.3
^ permalink raw reply related
* Re: [PATCH] powerpc: change the Book-E watchdog driver default timeout into a Kconfig option
From: Kumar Gala @ 2010-10-14 6:08 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev, linux-watchdog
In-Reply-To: <1286997576-4988-1-git-send-email-timur@freescale.com>
On Oct 13, 2010, at 2:19 PM, Timur Tabi wrote:
> The PowerPC Book-E watchdog driver (booke_wdt.c) defines a default =
timeout
> value in the code based on whether it's a Freescale Book-E part of =
not.
> Instead of having hard-coded values in the driver, make it a Kconfig =
option.
>=20
> As newer chips gets faster, the current default values become less =
appropriate,
> since the timeout sometimes occurs before the kernel finishes booting. =
Making
> the value a Kconfig option allows BSPs to configure a new value with =
requiring
> the wdt_period command-line parameter to be set.
>=20
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> drivers/watchdog/Kconfig | 17 +++++++++++++++++
> drivers/watchdog/booke_wdt.c | 8 +-------
> 2 files changed, 18 insertions(+), 7 deletions(-)
applied to next, fixed commit message.
Also, in general I believe commit messages should be about 75 columns so =
they dont wrap if you do a git log in an 80 column terminal.
- k=
^ permalink raw reply
* Re: [PATCH 1/3] fsl_rio: Add comments for sRIO registers.
From: Kumar Gala @ 2010-10-14 6:08 UTC (permalink / raw)
To: Shaohui Xie; +Cc: alexandre.bounine, linuxppc-dev
In-Reply-To: <1287021842-22015-1-git-send-email-b21989@freescale.com>
On Oct 13, 2010, at 9:04 PM, Shaohui Xie wrote:
> Add some comments to make sRIO registers map better readable.
>=20
> Signed-off-by: Shaohui Xie <b21989@freescale.com>
> ---
> arch/powerpc/sysdev/fsl_rio.c | 65 =
+++++++++++++++++++++++++----------------
> 1 files changed, 40 insertions(+), 25 deletions(-)
applied to next
- k=
^ permalink raw reply
* Re: [PATCH 2/3] fsl_rio: fix non-standard HID1 register access
From: Kumar Gala @ 2010-10-14 6:14 UTC (permalink / raw)
To: Shaohui Xie; +Cc: alexandre.bounine, linuxppc-dev
In-Reply-To: <1287021866-22095-1-git-send-email-b21989@freescale.com>
On Oct 13, 2010, at 9:04 PM, Shaohui Xie wrote:
> From: Li Yang <leoli@freescale.com>
>=20
> The access to HID1 register is only legitimate for e500 v1/v2 cores.
> Also fixes magic number.
>=20
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Shaohui Xie <b21989@freescale.com>
> ---
> arch/powerpc/sysdev/fsl_rio.c | 9 ++++++---
> 1 files changed, 6 insertions(+), 3 deletions(-)
>=20
> diff --git a/arch/powerpc/sysdev/fsl_rio.c =
b/arch/powerpc/sysdev/fsl_rio.c
> index 4127636..dfff3b7 100644
> --- a/arch/powerpc/sysdev/fsl_rio.c
> +++ b/arch/powerpc/sysdev/fsl_rio.c
> @@ -1537,9 +1537,12 @@ int fsl_rio_setup(struct platform_device *dev)
> #ifdef CONFIG_E500
> saved_mcheck_exception =3D ppc_md.machine_check_exception;
> ppc_md.machine_check_exception =3D fsl_rio_mcheck_exception;
> -#endif
> - /* Ensure that RFXE is set */
> - mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));
> +
> +#ifndef CONFIG_PPC_E500MC
> + /* Ensure that RFXE is set on e500 v1/v2 */
> + mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | HID1_RFXE));
> +#endif /* !PPC_E500MC */
> +#endif /* E500 */
I've never really been happy with this code. We really should set =
HID1_RFXE in cpu_setup_fsl_booke.S instead.
- k=
^ permalink raw reply
* Re: [PATCH 2/3] fsl_rio: fix non-standard HID1 register access
From: Kumar Gala @ 2010-10-14 6:17 UTC (permalink / raw)
To: Kumar Gala; +Cc: alexandre.bounine, linuxppc-dev, Shaohui Xie
In-Reply-To: <7F0756F8-8297-43A6-913A-6DA2634E18E5@kernel.crashing.org>
On Oct 14, 2010, at 1:14 AM, Kumar Gala wrote:
>=20
> On Oct 13, 2010, at 9:04 PM, Shaohui Xie wrote:
>=20
>> From: Li Yang <leoli@freescale.com>
>>=20
>> The access to HID1 register is only legitimate for e500 v1/v2 cores.
>> Also fixes magic number.
>>=20
>> Signed-off-by: Li Yang <leoli@freescale.com>
>> Signed-off-by: Shaohui Xie <b21989@freescale.com>
>> ---
>> arch/powerpc/sysdev/fsl_rio.c | 9 ++++++---
>> 1 files changed, 6 insertions(+), 3 deletions(-)
>>=20
>> diff --git a/arch/powerpc/sysdev/fsl_rio.c =
b/arch/powerpc/sysdev/fsl_rio.c
>> index 4127636..dfff3b7 100644
>> --- a/arch/powerpc/sysdev/fsl_rio.c
>> +++ b/arch/powerpc/sysdev/fsl_rio.c
>> @@ -1537,9 +1537,12 @@ int fsl_rio_setup(struct platform_device *dev)
>> #ifdef CONFIG_E500
>> saved_mcheck_exception =3D ppc_md.machine_check_exception;
>> ppc_md.machine_check_exception =3D fsl_rio_mcheck_exception;
>> -#endif
>> - /* Ensure that RFXE is set */
>> - mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));
>> +
>> +#ifndef CONFIG_PPC_E500MC
>> + /* Ensure that RFXE is set on e500 v1/v2 */
>> + mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | HID1_RFXE));
>> +#endif /* !PPC_E500MC */
>> +#endif /* E500 */
>=20
> I've never really been happy with this code. We really should set =
HID1_RFXE in cpu_setup_fsl_booke.S instead.
We should also change this so we just call fsl_rio_mcheck_exception() =
from machine_check_e500 & machine_check_e500mc and get rid of this =
ppc_md.machine_check_exception manipulation.
- k=
^ permalink raw reply
* Re: [git pull] Please pull powerpc.git next branch (updated)
From: Kumar Gala @ 2010-10-14 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1287018131.2205.50.camel@pasglop>
[ should fix the compile issue and pulled in 2 other minor patches ]
The following changes since commit 4108d9ba9091c55cfb968d42dd7dcae9a098b876:
powerpc/Makefiles: Change to new flag variables (2010-10-13 16:19:22 +1100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Harninder Rai (1):
powerpc/85xx: add cache-sram support
Ilya Yanok (1):
powerpc/mpc83xx: Support for MPC8308 P1M board
Kumar Gala (10):
powerpc/fsl-pci: Fix MSI support on 83xx platforms
powerpc/mpc8xxx_gpio: Add support for 'qoriq-gpio' controllers
powerpc/fsl-booke: Add PCI device ids for P2040/P3041/P5010/P5020 QoirQ chips
powerpc/fsl-booke: Add p3041 DS board support
powerpc: Fix compile error with paca code on ppc64e
powerpc/fsl-booke: Add support for FSL 64-bit e5500 core
powerpc/fsl-booke: Add support for FSL Arch v1.0 MMU in setup_page_sizes
powerpc/fsl-booke64: Use TLB CAMs to cover linear mapping on FSL 64-bit chips
powerpc/fsl-booke: Add p5020 DS board support
powerpc/fsl-booke: Add e55xx (64-bit) smp defconfig
Matthew McClintock (6):
powerpc/kexec: make masking/disabling interrupts generic
powerpc/85xx: Remove call to mpic_teardown_this_cpu in kexec
powerpc/85xx: Minor fixups for kexec on 85xx
powerpc/85xx: flush dcache before resetting cores
powerpc/fsl_soc: Search all global-utilities nodes for rstccr
powerpc/fsl_booke: Add support to boot from core other than 0
Paul Gortmaker (1):
powerpc: Fix invalid page flags in create TLB CAM path for PTE_64BIT
Scott Wood (1):
oprofile/fsl emb: Don't set MSR[PMM] until after clearing the interrupt.
Shaohui Xie (1):
fsl_rio: Add comments for sRIO registers.
Timur Tabi (5):
powerpc: export ppc_proc_freq and ppc_tb_freq as GPL symbols
powerpc/watchdog: Allow the Book-E driver to be compiled as a module
powerpc/p1022: Add probing for individual DMA channels
powerpc/85xx: add ngPIXIS FPGA device tree node to the P1022DS board
powerpc/watchdog: Make default timeout for Book-E watchdog a Kconfig option
arch/powerpc/boot/dts/mpc8308_p1m.dts | 332 ++++++++++++++++++++++++
arch/powerpc/boot/dts/p1022ds.dts | 11 +
arch/powerpc/configs/e55xx_smp_defconfig | 84 ++++++
arch/powerpc/configs/ppc64e_defconfig | 4 +-
arch/powerpc/include/asm/fsl_85xx_cache_sram.h | 48 ++++
arch/powerpc/include/asm/kexec.h | 1 +
arch/powerpc/include/asm/mmu-book3e.h | 15 +
arch/powerpc/include/asm/pte-common.h | 7 +
arch/powerpc/kernel/Makefile | 4 +-
arch/powerpc/kernel/asm-offsets.c | 4 +-
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 15 +
arch/powerpc/kernel/cputable.c | 28 ++-
arch/powerpc/kernel/crash.c | 13 +-
arch/powerpc/kernel/head_fsl_booke.S | 10 +-
arch/powerpc/kernel/machine_kexec.c | 24 ++
arch/powerpc/kernel/machine_kexec_32.c | 4 +
arch/powerpc/kernel/paca.c | 2 +-
arch/powerpc/kernel/setup_32.c | 2 +-
arch/powerpc/kernel/time.c | 3 +-
arch/powerpc/kernel/traps.c | 5 +
arch/powerpc/mm/Makefile | 2 +-
arch/powerpc/mm/fsl_booke_mmu.c | 15 +-
arch/powerpc/mm/mmu_decl.h | 5 +-
arch/powerpc/mm/tlb_nohash.c | 56 ++++-
arch/powerpc/mm/tlb_nohash_low.S | 2 +-
arch/powerpc/oprofile/op_model_fsl_emb.c | 15 +-
arch/powerpc/platforms/83xx/Kconfig | 4 +-
arch/powerpc/platforms/83xx/mpc830x_rdb.c | 3 +-
arch/powerpc/platforms/85xx/Kconfig | 28 ++-
arch/powerpc/platforms/85xx/Makefile | 2 +
arch/powerpc/platforms/85xx/p1022_ds.c | 2 +
arch/powerpc/platforms/85xx/p3041_ds.c | 64 +++++
arch/powerpc/platforms/85xx/p5020_ds.c | 69 +++++
arch/powerpc/platforms/85xx/smp.c | 76 +++++-
arch/powerpc/platforms/Kconfig.cputype | 8 +-
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h | 101 +++++++
arch/powerpc/sysdev/fsl_85xx_cache_sram.c | 159 +++++++++++
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 231 ++++++++++++++++
arch/powerpc/sysdev/fsl_msi.c | 9 +-
arch/powerpc/sysdev/fsl_pci.c | 60 ++++-
arch/powerpc/sysdev/fsl_pci.h | 1 +
arch/powerpc/sysdev/fsl_rio.c | 65 +++--
arch/powerpc/sysdev/fsl_soc.c | 20 +-
arch/powerpc/sysdev/mpc8xxx_gpio.c | 3 +
drivers/watchdog/Kconfig | 22 ++-
drivers/watchdog/booke_wdt.c | 47 +++-
include/linux/pci_ids.h | 8 +
48 files changed, 1582 insertions(+), 112 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc8308_p1m.dts
create mode 100644 arch/powerpc/configs/e55xx_smp_defconfig
create mode 100644 arch/powerpc/include/asm/fsl_85xx_cache_sram.h
create mode 100644 arch/powerpc/platforms/85xx/p3041_ds.c
create mode 100644 arch/powerpc/platforms/85xx/p5020_ds.c
create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_sram.c
create mode 100644 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
^ permalink raw reply
* RE: [PATCH 1/3 v4] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
From: Zang Roy-R61911 @ 2010-10-14 6:43 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Wood Scott-B07421, dedekind1, Lan Chunhe-B25806, linuxppc-dev,
linux-mtd, akpm, dwmw2, Gala Kumar-B11780
In-Reply-To: <20100920153718.GA4411@oksana.dev.rtsoft.ru>
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^ permalink raw reply
* RE: [PATCH 2/3] fsl_rio: fix non-standard HID1 register access
From: Li Yang-R58472 @ 2010-10-14 7:10 UTC (permalink / raw)
To: Kumar Gala, Xie Shaohui-B21989; +Cc: alexandre.bounine, linuxppc-dev
In-Reply-To: <7F0756F8-8297-43A6-913A-6DA2634E18E5@kernel.crashing.org>
>Subject: Re: [PATCH 2/3] fsl_rio: fix non-standard HID1 register access
>
>
>On Oct 13, 2010, at 9:04 PM, Shaohui Xie wrote:
>
>> From: Li Yang <leoli@freescale.com>
>>
>> The access to HID1 register is only legitimate for e500 v1/v2 cores.
>> Also fixes magic number.
>>
>> Signed-off-by: Li Yang <leoli@freescale.com>
>> Signed-off-by: Shaohui Xie <b21989@freescale.com>
>> ---
>> arch/powerpc/sysdev/fsl_rio.c | 9 ++++++---
>> 1 files changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/powerpc/sysdev/fsl_rio.c
>> b/arch/powerpc/sysdev/fsl_rio.c index 4127636..dfff3b7 100644
>> --- a/arch/powerpc/sysdev/fsl_rio.c
>> +++ b/arch/powerpc/sysdev/fsl_rio.c
>> @@ -1537,9 +1537,12 @@ int fsl_rio_setup(struct platform_device *dev)
>> #ifdef CONFIG_E500
>> saved_mcheck_exception =3D ppc_md.machine_check_exception;
>> ppc_md.machine_check_exception =3D fsl_rio_mcheck_exception; -#endif
>> - /* Ensure that RFXE is set */
>> - mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));
>> +
>> +#ifndef CONFIG_PPC_E500MC
>> + /* Ensure that RFXE is set on e500 v1/v2 */
>> + mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | HID1_RFXE)); #endif /*
>> +!PPC_E500MC */ #endif /* E500 */
>
>I've never really been happy with this code. We really should set
>HID1_RFXE in cpu_setup_fsl_booke.S instead.
But this bit is not recommended to be set unless necessary. And it is =
only required by SRIO for now.
- Leo
^ permalink raw reply
* Re: [PATCH][v2] powerpc/fsl: 85xx: add cache-sram support
From: Li Yang @ 2010-10-14 10:08 UTC (permalink / raw)
To: harninder.rai, Kumar Gala; +Cc: linuxppc-dev, Vivek Mahajan
In-Reply-To: <1286971256-22878-1-git-send-email-harninder.rai@freescale.com>
Oct 13, 2010 at 8:00 PM, <harninder.rai@freescale.com> wrote:
> From: Harninder Rai <harninder.rai@freescale.com>
>
> It adds cache-sram support in P1/P2 QorIQ platforms as under:
>
> =C2=A0 =C2=A0* A small abstraction over powerpc's remote heap allocator
> =C2=A0 =C2=A0* Exports mpc85xx_cache_sram_alloc()/free() APIs
> =C2=A0 =C2=A0* Supports only one contiguous SRAM window
> =C2=A0 =C2=A0* Drivers can do the following in Kconfig to use these APIs
> =C2=A0 =C2=A0 =C2=A0 =C2=A0"select FSL_85XX_CACHE_SRAM if MPC85xx"
You are missing the definition of this option in Kconfig like:
+config FSL_85XX_CACHE_SRAM
+ bool
+ select PPC_LIB_RHEAP
+
The select won't work actually.
Furthermore, MPC85xx config has been changed to FSL_SOC_BOOKE
- Leo
^ permalink raw reply
* Re: Please pull 'next' branch of 4xx tree
From: Josh Boyer @ 2010-10-14 10:35 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1287017775.2205.49.camel@pasglop>
On Thu, Oct 14, 2010 at 11:56:15AM +1100, Benjamin Herrenschmidt wrote:
>On Wed, 2010-10-13 at 09:16 -0400, Josh Boyer wrote:
>> On Tue, Sep 28, 2010 at 09:09:41AM -0400, Josh Boyer wrote:
>> >Hi Ben,
>> >
>> >A few small updates for the next branch. A new board/SoC from AMCC, and
>> >some 476 changes from Shaggy. Please pull.
>>
>> OK, below is a fixed up tree that drops the patch Shaggy said was
>> broken, and rebases on top of your new -next branch. Please pull.
>
>please, rebase again without Shaggy's lazy flush patch. I'll handle that
>one separately, I think it needs a little bit more massaging.
The following changes since commit 4108d9ba9091c55cfb968d42dd7dcae9a098b876:
powerpc/Makefiles: Change to new flag variables (2010-10-13 16:19:22 +1100)
are available in the git repository at:
ssh://master.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git next
Josh Boyer (1):
powerpc/44x: Update ppc44x_defconfig
Tirumala Marri (1):
powerpc/44x: Add support for the AMCC APM821xx SoC
arch/powerpc/boot/dts/bluestone.dts | 254 ++++++++++++++++++++++++++
arch/powerpc/configs/44x/bluestone_defconfig | 68 +++++++
arch/powerpc/configs/ppc44x_defconfig | 9 +-
arch/powerpc/kernel/cpu_setup_44x.S | 1 +
arch/powerpc/kernel/cputable.c | 15 ++
arch/powerpc/platforms/44x/Kconfig | 16 ++
arch/powerpc/platforms/44x/ppc44x_simple.c | 1 +
7 files changed, 360 insertions(+), 4 deletions(-)
create mode 100644 arch/powerpc/boot/dts/bluestone.dts
create mode 100644 arch/powerpc/configs/44x/bluestone_defconfig
^ permalink raw reply
* Re: [PATCH 2/3] fsl_rio: fix non-standard HID1 register access
From: Kumar Gala @ 2010-10-14 12:57 UTC (permalink / raw)
To: Li Yang-R58472; +Cc: alexandre.bounine, linuxppc-dev, Xie Shaohui-B21989
In-Reply-To: <F9BD3E0A8083BE4ABAA94D7EDD7E3F633346A7@zch01exm26.fsl.freescale.net>
On Oct 14, 2010, at 2:10 AM, Li Yang-R58472 wrote:
>> Subject: Re: [PATCH 2/3] fsl_rio: fix non-standard HID1 register =
access
>>=20
>>=20
>> On Oct 13, 2010, at 9:04 PM, Shaohui Xie wrote:
>>=20
>>> From: Li Yang <leoli@freescale.com>
>>>=20
>>> The access to HID1 register is only legitimate for e500 v1/v2 cores.
>>> Also fixes magic number.
>>>=20
>>> Signed-off-by: Li Yang <leoli@freescale.com>
>>> Signed-off-by: Shaohui Xie <b21989@freescale.com>
>>> ---
>>> arch/powerpc/sysdev/fsl_rio.c | 9 ++++++---
>>> 1 files changed, 6 insertions(+), 3 deletions(-)
>>>=20
>>> diff --git a/arch/powerpc/sysdev/fsl_rio.c
>>> b/arch/powerpc/sysdev/fsl_rio.c index 4127636..dfff3b7 100644
>>> --- a/arch/powerpc/sysdev/fsl_rio.c
>>> +++ b/arch/powerpc/sysdev/fsl_rio.c
>>> @@ -1537,9 +1537,12 @@ int fsl_rio_setup(struct platform_device =
*dev)
>>> #ifdef CONFIG_E500
>>> saved_mcheck_exception =3D ppc_md.machine_check_exception;
>>> ppc_md.machine_check_exception =3D fsl_rio_mcheck_exception; =
-#endif
>>> - /* Ensure that RFXE is set */
>>> - mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));
>>> +
>>> +#ifndef CONFIG_PPC_E500MC
>>> + /* Ensure that RFXE is set on e500 v1/v2 */
>>> + mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | HID1_RFXE)); #endif /*
>>> +!PPC_E500MC */ #endif /* E500 */
>>=20
>> I've never really been happy with this code. We really should set
>> HID1_RFXE in cpu_setup_fsl_booke.S instead.
>=20
> But this bit is not recommended to be set unless necessary. And it is =
only required by SRIO for now.
Than wrap it in a CONFIG_RAPIDIO in cpu_setup_fsl_booke.S
- k
^ permalink raw reply
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