* Re: [bg-linux] [PATCH 5/7] [RFC] force 32-byte aligned kmallocs
From: Benjamin Herrenschmidt @ 2011-05-20 2:13 UTC (permalink / raw)
To: Kazutomo Yoshii; +Cc: linuxppc-dev, linux-kernel, bg-linux
In-Reply-To: <1305857301.7481.121.camel@pasglop>
On Fri, 2011-05-20 at 12:08 +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2011-05-19 at 20:32 -0500, Kazutomo Yoshii wrote:
> >
> > Actually DMA sends invalidate requests to the snoop unit(L2 level).
> > BGP SoC is a bit different from other 4xx base.
>
> Well, some other 44x also have a snooping L2 (more or less), but L1 is
> usually the problem.
Hrm... looking at the doco you pointed me to, it looks like the L1 -is-
coherent, it gets snoop kills from the L2.
Ok so we do need to make this non-coherent cache stuff a runtime option
(well, we need that for 440+476 too anyways so may as well do it now).
As for the alignment of kmalloc, it looks like a hack that should be
done in the torus code itself.
Cheers,
Ben.
^ permalink raw reply
* Re: [bg-linux] [PATCH 5/7] [RFC] force 32-byte aligned kmallocs
From: Benjamin Herrenschmidt @ 2011-05-20 3:13 UTC (permalink / raw)
To: Kazutomo Yoshii; +Cc: Kazutomo Yoshii, linuxppc-dev, linux-kernel, bg-linux
In-Reply-To: <4DD5D9C9.3020000@mcs.anl.gov>
On Thu, 2011-05-19 at 22:02 -0500, Kazutomo Yoshii wrote:
> On 05/19/2011 09:13 PM, Benjamin Herrenschmidt wrote:
> > On Fri, 2011-05-20 at 12:08 +1000, Benjamin Herrenschmidt wrote:
> >
> >> On Thu, 2011-05-19 at 20:32 -0500, Kazutomo Yoshii wrote:
> >>
> >>> Actually DMA sends invalidate requests to the snoop unit(L2 level).
> >>> BGP SoC is a bit different from other 4xx base.
> >>>
> >> Well, some other 44x also have a snooping L2 (more or less), but L1 is
> >> usually the problem.
> >>
> > Hrm... looking at the doco you pointed me to, it looks like the L1 -is-
> > coherent, it gets snoop kills from the L2.
> >
> Right, L1D is coherent if write throug is set.
> L1I(virtually tagged) is not coherent, btw.
Yes, I wrote the horrid hack to ping pong the pages between writable and
executable afaik :-)
> > Ok so we do need to make this non-coherent cache stuff a runtime option
> > (well, we need that for 440+476 too anyways so may as well do it now).
> >
> What sort of runtime option do you mean?
I've asked Tony to give it a go since he's taking over the 476 stuff.
The idea is to make it a MMU feature and call into the cache flush
conditionally on it rather than under the control of a ifdef.
I want it to be possible to build a unified kernel that supports
multiple 44x and 47x platforms including BGP if we can make it happen.
There's still some roadblocks to support 47x and 44x in the same kernel,
most notably the cache line size, but I have hopes I'll get Tony to fix
them soon :-)
Cheers,
Ben.
> - kaz
> > As for the alignment of kmalloc, it looks like a hack that should be
> > done in the torus code itself.
> >
> > Cheers,
> > Ben.
> >
> > _______________________________________________
> > bg-linux mailing list
> > bg-linux@lists.anl-external.org
> > https://lists.anl-external.org/mailman/listinfo/bg-linux
> > http://bg-linux.anl-external.org/wiki
> >
^ permalink raw reply
* Re: [bg-linux] [PATCH 5/7] [RFC] force 32-byte aligned kmallocs
From: Kazutomo Yoshii @ 2011-05-20 3:02 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Kazutomo Yoshii, linuxppc-dev, linux-kernel, bg-linux
In-Reply-To: <1305857610.7481.124.camel@pasglop>
On 05/19/2011 09:13 PM, Benjamin Herrenschmidt wrote:
> On Fri, 2011-05-20 at 12:08 +1000, Benjamin Herrenschmidt wrote:
>
>> On Thu, 2011-05-19 at 20:32 -0500, Kazutomo Yoshii wrote:
>>
>>> Actually DMA sends invalidate requests to the snoop unit(L2 level).
>>> BGP SoC is a bit different from other 4xx base.
>>>
>> Well, some other 44x also have a snooping L2 (more or less), but L1 is
>> usually the problem.
>>
> Hrm... looking at the doco you pointed me to, it looks like the L1 -is-
> coherent, it gets snoop kills from the L2.
>
Right, L1D is coherent if write throug is set.
L1I(virtually tagged) is not coherent, btw.
> Ok so we do need to make this non-coherent cache stuff a runtime option
> (well, we need that for 440+476 too anyways so may as well do it now).
>
What sort of runtime option do you mean?
- kaz
> As for the alignment of kmalloc, it looks like a hack that should be
> done in the torus code itself.
>
> Cheers,
> Ben.
>
> _______________________________________________
> bg-linux mailing list
> bg-linux@lists.anl-external.org
> https://lists.anl-external.org/mailman/listinfo/bg-linux
> http://bg-linux.anl-external.org/wiki
>
^ permalink raw reply
* [GIT PULL] Please pull powerpc.git next branch
From: Kumar Gala @ 2011-05-20 3:31 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
The following changes since commit f38aa708776aefd9e3ba7ec1211c07efe9fa3227:
powerpc: Remove last piece of GEMINI (2011-05-19 17:32:29 +1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Bhaskar Upadhaya (1):
powerpc: Adding bindings for flexcan controller
Dipen Dudhat (1):
powerpc: Integrated Flash controller device tree bindings
Geert Uytterhoeven (1):
powerpc/mpc8610_hpcd: Do not use "/" in interrupt names
Kumar Gala (1):
powerpc/fsl-booke64: Add support for Debug Level exception handler
Prabhakar Kushwaha (4):
powerpc/85xx: P1020 DTS : re-organize dts files
powerpc/85xx: P2020 DTS: re-organize dts files
powerpc/85xx: Fix PCIe IDSEL for Px020RDB
powerpc/85xx: Create dts of each core in CAMP mode for P1020RDB
Scott Wood (7):
powerpc/e5500: set non-base IVORs
powerpc: Add fsl mpic timer binding
powerpc/p1022ds: fix broken mpic timer node
powerpc/mpic: parse 4-cell intspec types other than zero
powerpc/mpic: add the mpic global timer support
powerpc/e5500: add networking to defconfig
powerpc/fsl: enable verbose bug output
Shengzhou Liu (1):
powerpc/fsl_lbc: Add workaround for ELBC-A001 erratum
Timur Tabi (1):
powerpc/86xx: don't pretend that we support 8-bit pixels on the MPC8610 HPCD
.../devicetree/bindings/net/can/fsl-flexcan.txt | 61 +++
.../devicetree/bindings/powerpc/fsl/ifc.txt | 76 ++++
.../devicetree/bindings/powerpc/fsl/mpic-timer.txt | 38 ++
.../devicetree/bindings/powerpc/fsl/mpic.txt | 2 +-
arch/powerpc/boot/dts/p1020rdb.dts | 332 +----------------
arch/powerpc/boot/dts/p1020rdb_camp_core0.dts | 213 +++++++++++
arch/powerpc/boot/dts/p1020rdb_camp_core1.dts | 148 ++++++++
arch/powerpc/boot/dts/p1020si.dtsi | 377 +++++++++++++++++++
arch/powerpc/boot/dts/p1022ds.dts | 106 +++---
arch/powerpc/boot/dts/p2020ds.dts | 374 ++------------------
arch/powerpc/boot/dts/p2020rdb.dts | 378 +++-----------------
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts | 245 +++-----------
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts | 150 +++++---
arch/powerpc/boot/dts/p2020si.dtsi | 382 ++++++++++++++++++++
arch/powerpc/configs/83xx/mpc8313_rdb_defconfig | 1 -
arch/powerpc/configs/83xx/mpc8315_rdb_defconfig | 1 -
arch/powerpc/configs/85xx/mpc8540_ads_defconfig | 1 -
arch/powerpc/configs/85xx/mpc8560_ads_defconfig | 1 -
arch/powerpc/configs/85xx/mpc85xx_cds_defconfig | 1 -
arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig | 1 -
arch/powerpc/configs/e55xx_smp_defconfig | 39 ++-
arch/powerpc/configs/mpc85xx_defconfig | 1 -
arch/powerpc/configs/mpc85xx_smp_defconfig | 1 -
arch/powerpc/configs/mpc86xx_defconfig | 1 -
arch/powerpc/include/asm/cputable.h | 4 +-
arch/powerpc/include/asm/fsl_lbc.h | 2 +
arch/powerpc/include/asm/mpic.h | 5 +-
arch/powerpc/include/asm/reg_booke.h | 4 +
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 3 +
arch/powerpc/kernel/exceptions-64e.S | 112 ++++++-
arch/powerpc/kernel/setup_64.c | 8 +
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 99 ++++--
arch/powerpc/sysdev/fsl_lbc.c | 9 +-
arch/powerpc/sysdev/mpic.c | 129 +++++++-
34 files changed, 1944 insertions(+), 1361 deletions(-)
create mode 100755 Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
create mode 100644 arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
create mode 100644 arch/powerpc/boot/dts/p1020si.dtsi
create mode 100644 arch/powerpc/boot/dts/p2020si.dtsi
^ permalink raw reply
* Re: [bg-linux] [PATCH 6/7] [RFC] enable early TLBs for BG/P
From: Kazutomo Yoshii @ 2011-05-20 3:38 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, linux-kernel, bg-linux
In-Reply-To: <1305856442.7481.120.camel@pasglop>
On 05/19/2011 08:54 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2011-05-19 at 20:21 -0500, Eric Van Hensbergen wrote:
>
>> On Thu, May 19, 2011 at 7:39 PM, Benjamin Herrenschmidt
>> <benh@kernel.crashing.org> wrote:
>>
>>> On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
>>>
>>>> BG/P maps firmware with an early TLB
>>>>
>>> That's a bit gross. How often do you call that firmware in practice ?
>>> Aren't you better off instead inserting a TLB entry for it when you call
>>> it instead ? A simple tlbsx. + tlbwe sequence would do. That would free
>>> up a TLB entry for normal use.
>>>
>>>
>> Well, it depends on who you talk to. The production software BG/P
>> guys use the firmware constantly, its the primary interface to the networks, the console,
>> and the management software which runs the machine.
>>
> Yuck.
>
Unfortunately, the firmware is also required:
- to configure Blue Gene Interrupt Controller(BIC)
- to configure Torus DMA unit. e.g. fifo
- to configure global interrupt (even we don't use, we need to disable
some channel correctly)
- to access node personality information (node id, DDR size, HZ, etc) or
maybe we can directly access SRAM?
etc, etc.
>> As such the IO Node guys, the Compute Node Kernel guys and the
>> ZeptoOS guys use it quite a bit. The kittyhawk guys on the other hand
>> barely use it at all, in fact I believe they do all the interaction with
>> it during uboot and then shut it off.
>>
>
(I'm one of the ZeptoOS guys, btw)
As a regular ppc linux usage, our firmware dependency is minimum as well.
However, with our HPC extension, the firmware functions are called when
it configures BGP specific network hardware.
We are not planning to submit our HPC extension here anytime soon
because our work is very special purpose and includes lots of dirty hack
right now.
Thanks,
Kaz
> I would prefer that approach.
>
>
>> IIRC, the sticky question is RAS support, there are certain things it
>> wants to jump to firmware to deal with and expects things to be mapped
>> an pinned into memory.
>>
>> Furthermore, I think it may make assumptions about where in the TLB the
>> mappings are.
>>
> This is gross, especially on a system with only 64 SW loaded TLB
> entries :-(
>
>
>> Since the kittyhawk guys
>> obviously ignore this by shutting it down, its not clear just how
>> important this is. I'm game to
>> try the dynamic mapping as you suggest if you would prefer it.
>>
> I would yes, we can sort things out later for RAS.
>
>
>> Its worth mentioning that I believe with BG/Q, the plan is to rely on
>> the firmware even more extensively, but I haven't looked at any of the code yet to verify
>> whether or not this is true.
>>
> This is tantamount to linking a binary blob with the kernel ... it's a
> fine line. At some point we might refuse the patches if they go too far
> in that direction.
>
> Cheers,
> Ben.
>
>
>> -eric
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>> Please read the FAQ at http://www.tux.org/lkml/
>>
>
> _______________________________________________
> bg-linux mailing list
> bg-linux@lists.anl-external.org
> https://lists.anl-external.org/mailman/listinfo/bg-linux
> http://bg-linux.anl-external.org/wiki
>
^ permalink raw reply
* Re: [bg-linux] [PATCH 6/7] [RFC] enable early TLBs for BG/P
From: Benjamin Herrenschmidt @ 2011-05-20 3:52 UTC (permalink / raw)
To: Kazutomo Yoshii; +Cc: linuxppc-dev, linux-kernel, bg-linux
In-Reply-To: <4DD5E218.5030508@mcs.anl.gov>
> Unfortunately, the firmware is also required:
> - to configure Blue Gene Interrupt Controller(BIC)
Can't we just write bare metal code for that ?
> - to configure Torus DMA unit. e.g. fifo
Same
> - to configure global interrupt (even we don't use, we need to disable
> some channel correctly)
Same
> - to access node personality information (node id, DDR size, HZ, etc) or
> maybe we can directly access SRAM?
That should be turned into device-tree at boot, possibly from a
bootloader or from the zImage wrapper.
> etc, etc.
>
> >> As such the IO Node guys, the Compute Node Kernel guys and the
> >> ZeptoOS guys use it quite a bit. The kittyhawk guys on the other hand
> >> barely use it at all, in fact I believe they do all the interaction with
> >> it during uboot and then shut it off.
> >>
> >
> (I'm one of the ZeptoOS guys, btw)
Heh ok.
> As a regular ppc linux usage, our firmware dependency is minimum as well.
> However, with our HPC extension, the firmware functions are called when
> it configures BGP specific network hardware.
>
> We are not planning to submit our HPC extension here anytime soon
> because our work is very special purpose and includes lots of dirty hack
> right now.
Ok.
Cheers,
Ben.
> Thanks,
> Kaz
> > I would prefer that approach.
> >
> >
> >> IIRC, the sticky question is RAS support, there are certain things it
> >> wants to jump to firmware to deal with and expects things to be mapped
> >> an pinned into memory.
> >>
> >> Furthermore, I think it may make assumptions about where in the TLB the
> >> mappings are.
> >>
> > This is gross, especially on a system with only 64 SW loaded TLB
> > entries :-(
> >
> >
> >> Since the kittyhawk guys
> >> obviously ignore this by shutting it down, its not clear just how
> >> important this is. I'm game to
> >> try the dynamic mapping as you suggest if you would prefer it.
> >>
> > I would yes, we can sort things out later for RAS.
> >
> >
> >> Its worth mentioning that I believe with BG/Q, the plan is to rely on
> >> the firmware even more extensively, but I haven't looked at any of the code yet to verify
> >> whether or not this is true.
> >>
> > This is tantamount to linking a binary blob with the kernel ... it's a
> > fine line. At some point we might refuse the patches if they go too far
> > in that direction.
> >
> > Cheers,
> > Ben.
> >
> >
> >> -eric
> >> --
> >> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> >> the body of a message to majordomo@vger.kernel.org
> >> More majordomo info at http://vger.kernel.org/majordomo-info.html
> >> Please read the FAQ at http://www.tux.org/lkml/
> >>
> >
> > _______________________________________________
> > bg-linux mailing list
> > bg-linux@lists.anl-external.org
> > https://lists.anl-external.org/mailman/listinfo/bg-linux
> > http://bg-linux.anl-external.org/wiki
> >
^ permalink raw reply
* linux-next: manual merge of the tip tree with the powerpc tree
From: Stephen Rothwell @ 2011-05-20 4:14 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Peter Zijlstra
Cc: linux-kernel, Milton Miller, linux-next, Paul Mackerras,
linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 525 bytes --]
Hi all,
Today's linux-next merge of the tip tree got a conflict in
arch/powerpc/kernel/smp.c between commit 23d72bfd8f9f ("powerpc:
Consolidate ipi message mux and demux") from the powerpc tree and commit
184748cc50b2 ("sched: Provide scheduler_ipi() callback in response to
smp_send_reschedule()") from the tip tree.
The former superceded part of the latter's changes, so I just used the
former for that.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 490 bytes --]
^ permalink raw reply
* Re: [PATCH 2/2][v3] rapidio, powerpc/85xx: Error interrupt handler for sRIO.
From: Kumar Gala @ 2011-05-20 4:28 UTC (permalink / raw)
To: Bounine, Alexandre
Cc: Li Yang-R58472, Xie Shaohui-B21989, Zang Roy-R61911, akpm,
linuxppc-dev, Gala Kumar-B11780
In-Reply-To: <0CE8B6BE3C4AD74AB97D9D29BD24E5520162CA22@CORPEXCH1.na.ads.idt.com>
Alex,
What are we doing with this patch?
- k
On Dec 3, 2010, at 12:04 PM, Bounine, Alexandre wrote:
> I think they should follow the previous two that are in Kumar=92s =
tree.
> Probably Kumar may give you a better timeline estimate for this. =20
>=20
> Alex.
>=20
> From: linuxppc-dev-bounces+alexandre.bounine=3Didt.com@lists.ozlabs.org =
[mailto:linuxppc-dev-bounces+alexandre.bounine=3Didt.com@lists.ozlabs.org]=
On Behalf Of Xie Shaohui-B21989
> Sent: Thursday, December 02, 2010 10:29 PM
> To: Bounine, Alexandre; linuxppc-dev@lists.ozlabs.org
> Cc: akpm@linux-foundation.org; Gala Kumar-B11780; Li Yang-R58472; Zang =
Roy-R61911
> Subject: RE: [PATCH 2/2][v3] rapidio,powerpc/85xx: Error interrupt =
handler for sRIO.
>=20
> Hi Alex,
>=20
> May I ask when would these patches be applied to mainline?
>=20
>=20
> Best Regards,=20
> Shaohui Xie
>=20
> From: Bounine, Alexandre [mailto:Alexandre.Bounine@idt.com]=20
> Sent: Wednesday, December 01, 2010 4:49 AM
> To: Xie Shaohui-B21989; linuxppc-dev@lists.ozlabs.org
> Cc: akpm@linux-foundation.org; Li Yang-R58472; Gala Kumar-B11780; Zang =
Roy-R61911
> Subject: RE: [PATCH 2/2][v3] rapidio, powerpc/85xx: Error interrupt =
handler for sRIO.
>=20
> Applies correctly now. Lab tested on 8548/RIO setup.
>=20
> Alex.
>=20
>> -----Original Message-----
>> From: Shaohui Xie [mailto:b21989@freescale.com]
>> Sent: Thursday, November 18, 2010 1:58 AM
>> To: linuxppc-dev@lists.ozlabs.org
>> Cc: akpm@linux-foundation.org; Shaohui Xie; Li Yang; Kumar Gala; Roy
> Zang; Bounine, Alexandre
>> Subject: [PATCH 2/2][v3] rapidio, powerpc/85xx: Error interrupt
> handler for sRIO.
>>=20
>> The sRIO controller reports errors to the core with one signal, it
> uses
>> register EPWISR to provides the core quick access to where the error
> occurred.
>> The EPWISR indicates that there are 4 interrupts sources, port1,
> port2, message
>> unit and port write receive, but the sRIO driver does not support
> port2
>> for now, still the handler takes care of port2.
>> Currently the handler only clear error status without any recovery.
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [GIT PULL] Please pull powerpc.git next branch
From: Kumar Gala @ 2011-05-20 4:38 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Linuxppc-dev list
In-Reply-To: <alpine.LFD.2.00.1105192230380.2641@right.am.freescale.net>
On May 19, 2011, at 10:31 PM, Kumar Gala wrote:
> The following changes since commit =
f38aa708776aefd9e3ba7ec1211c07efe9fa3227:
>=20
> powerpc: Remove last piece of GEMINI (2011-05-19 17:32:29 +1000)
>=20
> are available in the git repository at:
> git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
>=20
> Bhaskar Upadhaya (1):
> powerpc: Adding bindings for flexcan controller
>=20
> Dipen Dudhat (1):
> powerpc: Integrated Flash controller device tree bindings
>=20
> Geert Uytterhoeven (1):
> powerpc/mpc8610_hpcd: Do not use "/" in interrupt names
>=20
> Kumar Gala (1):
> powerpc/fsl-booke64: Add support for Debug Level exception =
handler
>=20
> Prabhakar Kushwaha (4):
> powerpc/85xx: P1020 DTS : re-organize dts files
> powerpc/85xx: P2020 DTS: re-organize dts files
> powerpc/85xx: Fix PCIe IDSEL for Px020RDB
> powerpc/85xx: Create dts of each core in CAMP mode for P1020RDB
>=20
> Scott Wood (7):
> powerpc/e5500: set non-base IVORs
> powerpc: Add fsl mpic timer binding
> powerpc/p1022ds: fix broken mpic timer node
> powerpc/mpic: parse 4-cell intspec types other than zero
> powerpc/mpic: add the mpic global timer support
> powerpc/e5500: add networking to defconfig
> powerpc/fsl: enable verbose bug output
>=20
> Shengzhou Liu (1):
> powerpc/fsl_lbc: Add workaround for ELBC-A001 erratum
>=20
> Timur Tabi (1):
> powerpc/86xx: don't pretend that we support 8-bit pixels on the =
MPC8610 HPCD
I might have 2 RIO patches that have been on the list for several =
months. Waiting to hear back from Alex.
- k=
^ permalink raw reply
* RE: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows for PM
From: Kushwaha Prabhakar-B32579 @ 2011-05-20 4:41 UTC (permalink / raw)
To: Kumar Gala
Cc: meet2prabhu@gmail.com, linuxppc-dev@lists.ozlabs.org,
Jiang Yutang-B14898
In-Reply-To: <EFA5CCD8-07AE-4AD3-A067-4E79F61B3886@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Thursday, May 19, 2011 6:53 PM
> To: Kushwaha Prabhakar-B32579
> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang Yutang-
> B14898
> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows for
> PM
>=20
>=20
> On May 19, 2011, at 6:22 AM, Kushwaha Prabhakar-B32579 wrote:
>=20
> > Hi Kumar,
> > Please find my answer in-lined
> >
> >> -----Original Message-----
> >> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> >> Sent: Thursday, May 19, 2011 12:00 PM
> >> To: Kushwaha Prabhakar-B32579
> >> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang
> >> Yutang-
> >> B14898
> >> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows
> >> for PM
> >>
> >>
> >> On Apr 28, 2011, at 1:38 AM, Prabhakar Kushwaha wrote:
> >>
> >>> D3-cold state indicates removal of the clock and power. however
> >>> auxiliary (AUX) Power may remain available even after the main power
> >> rails are powered down.
> >>>
> >>> wakeup from D3-cold state requires full context restore. Other
> >>> things are taken care in pci-driver except ATMUs.
> >>> ATMU windows needs to be saved and restored during suspend and
> resume.
> >>>
> >>> Signed-off-by: Jiang Yutang <b14898@freescale.com>
> >>> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> >>> ---
> >>> Based upon
> >>> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
> >>> (b
> >>> ranch master)
> >>>
> >>> arch/powerpc/sysdev/fsl_pci.c | 116
> >> +++++++++++++++++++++++++++++++++++++++++
> >>> arch/powerpc/sysdev/fsl_pci.h | 7 ++-
> >>> 2 files changed, 121 insertions(+), 2 deletions(-)
> >>
> >> Is this patch for when we are a host or agent?
> >
> > This patch is independent of host or agent. It is for supporting D3
> cold state for P1022.
> > These functions are called during System level suspend and resume.
> >
> > --Prabhakar
>=20
> I'm trying to figure out why this is limited to P1022.
Till now, No SOC was supporting D3 cold state. First time P1022 supporting =
it.
Note: D3 cold state =3D=3D PCIe block Power down
--Prabhakar=20
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows for PM
From: Kumar Gala @ 2011-05-20 4:46 UTC (permalink / raw)
To: Kushwaha Prabhakar-B32579
Cc: meet2prabhu@gmail.com, linuxppc-dev@lists.ozlabs.org,
Jiang Yutang-B14898
In-Reply-To: <071A08F2C6A57E4E94D980ECA553F8741D8D46@039-SN1MPN1-005.039d.mgd.msft.net>
On May 19, 2011, at 11:41 PM, Kushwaha Prabhakar-B32579 wrote:
>=20
>=20
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>> Sent: Thursday, May 19, 2011 6:53 PM
>> To: Kushwaha Prabhakar-B32579
>> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang =
Yutang-
>> B14898
>> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows =
for
>> PM
>>=20
>>=20
>> On May 19, 2011, at 6:22 AM, Kushwaha Prabhakar-B32579 wrote:
>>=20
>>> Hi Kumar,
>>> Please find my answer in-lined
>>>=20
>>>> -----Original Message-----
>>>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>>>> Sent: Thursday, May 19, 2011 12:00 PM
>>>> To: Kushwaha Prabhakar-B32579
>>>> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang
>>>> Yutang-
>>>> B14898
>>>> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU =
windows
>>>> for PM
>>>>=20
>>>>=20
>>>> On Apr 28, 2011, at 1:38 AM, Prabhakar Kushwaha wrote:
>>>>=20
>>>>> D3-cold state indicates removal of the clock and power. however
>>>>> auxiliary (AUX) Power may remain available even after the main =
power
>>>> rails are powered down.
>>>>>=20
>>>>> wakeup from D3-cold state requires full context restore. Other
>>>>> things are taken care in pci-driver except ATMUs.
>>>>> ATMU windows needs to be saved and restored during suspend and
>> resume.
>>>>>=20
>>>>> Signed-off-by: Jiang Yutang <b14898@freescale.com>
>>>>> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
>>>>> ---
>>>>> Based upon
>>>>> =
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
>>>>> (b
>>>>> ranch master)
>>>>>=20
>>>>> arch/powerpc/sysdev/fsl_pci.c | 116
>>>> +++++++++++++++++++++++++++++++++++++++++
>>>>> arch/powerpc/sysdev/fsl_pci.h | 7 ++-
>>>>> 2 files changed, 121 insertions(+), 2 deletions(-)
>>>>=20
>>>> Is this patch for when we are a host or agent?
>>>=20
>>> This patch is independent of host or agent. It is for supporting D3
>> cold state for P1022.
>>> These functions are called during System level suspend and resume.
>>>=20
>>> --Prabhakar
>>=20
>> I'm trying to figure out why this is limited to P1022.
>=20
> Till now, No SOC was supporting D3 cold state. First time P1022 =
supporting it.
> Note: D3 cold state =3D=3D PCIe block Power down
>=20
> --Prabhakar=20
how do we test this ?
- k=
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows for PM
From: Kumar Gala @ 2011-05-20 4:48 UTC (permalink / raw)
To: Kushwaha Prabhakar-B32579
Cc: meet2prabhu@gmail.com, linuxppc-dev@lists.ozlabs.org,
Jiang Yutang-B14898
In-Reply-To: <071A08F2C6A57E4E94D980ECA553F8741D8D46@039-SN1MPN1-005.039d.mgd.msft.net>
On May 19, 2011, at 11:41 PM, Kushwaha Prabhakar-B32579 wrote:
>=20
>=20
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>> Sent: Thursday, May 19, 2011 6:53 PM
>> To: Kushwaha Prabhakar-B32579
>> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang =
Yutang-
>> B14898
>> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows =
for
>> PM
>>=20
>>=20
>> On May 19, 2011, at 6:22 AM, Kushwaha Prabhakar-B32579 wrote:
>>=20
>>> Hi Kumar,
>>> Please find my answer in-lined
>>>=20
>>>> -----Original Message-----
>>>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>>>> Sent: Thursday, May 19, 2011 12:00 PM
>>>> To: Kushwaha Prabhakar-B32579
>>>> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang
>>>> Yutang-
>>>> B14898
>>>> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU =
windows
>>>> for PM
>>>>=20
>>>>=20
>>>> On Apr 28, 2011, at 1:38 AM, Prabhakar Kushwaha wrote:
>>>>=20
>>>>> D3-cold state indicates removal of the clock and power. however
>>>>> auxiliary (AUX) Power may remain available even after the main =
power
>>>> rails are powered down.
>>>>>=20
>>>>> wakeup from D3-cold state requires full context restore. Other
>>>>> things are taken care in pci-driver except ATMUs.
>>>>> ATMU windows needs to be saved and restored during suspend and
>> resume.
>>>>>=20
>>>>> Signed-off-by: Jiang Yutang <b14898@freescale.com>
>>>>> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
>>>>> ---
>>>>> Based upon
>>>>> =
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
>>>>> (b
>>>>> ranch master)
>>>>>=20
>>>>> arch/powerpc/sysdev/fsl_pci.c | 116
>>>> +++++++++++++++++++++++++++++++++++++++++
>>>>> arch/powerpc/sysdev/fsl_pci.h | 7 ++-
>>>>> 2 files changed, 121 insertions(+), 2 deletions(-)
>>>>=20
>>>> Is this patch for when we are a host or agent?
>>>=20
>>> This patch is independent of host or agent. It is for supporting D3
>> cold state for P1022.
>>> These functions are called during System level suspend and resume.
>>>=20
>>> --Prabhakar
>>=20
>> I'm trying to figure out why this is limited to P1022.
>=20
> Till now, No SOC was supporting D3 cold state. First time P1022 =
supporting it.
> Note: D3 cold state =3D=3D PCIe block Power down
>=20
I'm wondering a few things:
1. Is there any reason not to do this for ALL FSL PCIe SoCs?
2. why do bother saving state, we don't we re-parse the .dts and =
reconfigure ATMUs that way?
- k
^ permalink raw reply
* Re: [PATCH] Powerpc/fsl_lbc: Add workaround for ELBC-A001 erratum
From: Kumar Gala @ 2011-05-20 4:52 UTC (permalink / raw)
To: Shengzhou Liu; +Cc: scottwood, linuxppc-dev
In-Reply-To: <1305802081-19733-1-git-send-email-Shengzhou.Liu@freescale.com>
On May 19, 2011, at 5:48 AM, Shengzhou Liu wrote:
> Simultaneous FCM and GPCM or UPM operation may erroneously trigger
> bus monitor timeout.
>
> Set the local bus monitor timeout value to the maximum by setting
> LBCR[BMT] = 0 and LBCR[BMTPS] = 0xF.
>
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> Signed-off-by: Gala Kumar <kumar.gala@freescale.com>
> ---
> arch/powerpc/include/asm/fsl_lbc.h | 2 ++
> arch/powerpc/sysdev/fsl_lbc.c | 9 +++++++--
> 2 files changed, 9 insertions(+), 2 deletions(-)
applied to next
- k
^ permalink raw reply
* RE: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows for PM
From: Kushwaha Prabhakar-B32579 @ 2011-05-20 5:01 UTC (permalink / raw)
To: Kumar Gala
Cc: meet2prabhu@gmail.com, linuxppc-dev@lists.ozlabs.org,
Jiang Yutang-B14898
In-Reply-To: <0CF50C76-D9D0-4966-87B9-CD4EDF6ABC07@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Friday, May 20, 2011 10:19 AM
> To: Kushwaha Prabhakar-B32579
> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang Yutang-
> B14898
> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows for
> PM
>=20
>=20
> On May 19, 2011, at 11:41 PM, Kushwaha Prabhakar-B32579 wrote:
>=20
> >
> >
> >> -----Original Message-----
> >> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> >> Sent: Thursday, May 19, 2011 6:53 PM
> >> To: Kushwaha Prabhakar-B32579
> >> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang
> >> Yutang-
> >> B14898
> >> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows
> >> for PM
> >>
> >>
> >> On May 19, 2011, at 6:22 AM, Kushwaha Prabhakar-B32579 wrote:
> >>
> >>> Hi Kumar,
> >>> Please find my answer in-lined
> >>>
> >>>> -----Original Message-----
> >>>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> >>>> Sent: Thursday, May 19, 2011 12:00 PM
> >>>> To: Kushwaha Prabhakar-B32579
> >>>> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang
> >>>> Yutang-
> >>>> B14898
> >>>> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU
> >>>> windows for PM
> >>>>
> >>>>
> >>>> On Apr 28, 2011, at 1:38 AM, Prabhakar Kushwaha wrote:
> >>>>
> >>>>> D3-cold state indicates removal of the clock and power. however
> >>>>> auxiliary (AUX) Power may remain available even after the main
> >>>>> power
> >>>> rails are powered down.
> >>>>>
> >>>>> wakeup from D3-cold state requires full context restore. Other
> >>>>> things are taken care in pci-driver except ATMUs.
> >>>>> ATMU windows needs to be saved and restored during suspend and
> >> resume.
> >>>>>
> >>>>> Signed-off-by: Jiang Yutang <b14898@freescale.com>
> >>>>> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> >>>>> ---
> >>>>> Based upon
> >>>>> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.g
> >>>>> it
> >>>>> (b
> >>>>> ranch master)
> >>>>>
> >>>>> arch/powerpc/sysdev/fsl_pci.c | 116
> >>>> +++++++++++++++++++++++++++++++++++++++++
> >>>>> arch/powerpc/sysdev/fsl_pci.h | 7 ++-
> >>>>> 2 files changed, 121 insertions(+), 2 deletions(-)
> >>>>
> >>>> Is this patch for when we are a host or agent?
> >>>
> >>> This patch is independent of host or agent. It is for supporting D3
> >> cold state for P1022.
> >>> These functions are called during System level suspend and resume.
> >>>
> >>> --Prabhakar
> >>
> >> I'm trying to figure out why this is limited to P1022.
> >
> > Till now, No SOC was supporting D3 cold state. First time P1022
> supporting it.
> > Note: D3 cold state =3D=3D PCIe block Power down
> >
>=20
> I'm wondering a few things:
>=20
> 1. Is there any reason not to do this for ALL FSL PCIe SoCs?
Yes, I am agree with you. It can be done.=20
But as only P1022 SOC supporting it. There is no use of handling it.=20
> 2. why do bother saving state, we don't we re-parse the .dts and
> reconfigure ATMUs that way?
I also thought of this case. But Agent use case scenario forbid me to do th=
is.=20
As ATMU's are programmed by host depending upon different use case . And th=
is information is never stored in the dts.
--Prabhakar
=20
^ permalink raw reply
* linux-next: build warning after merge of the final tree (tip/powerpc tree related)
From: Stephen Rothwell @ 2011-05-20 5:14 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Peter Zijlstra
Cc: linux-next, Paul Mackerras, linux-kernel, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 1530 bytes --]
Hi all,
After merging the final tree, today's linux-next build (powerpc allnoconfig)
produced these warnings:
kernel/time/clocksource.c: In function '__clocksource_updatefreq_scale':
kernel/time/clocksource.c:655: warning: comparison of distinct pointer types lacks a cast
kernel/time/clocksource.c:655: warning: right shift count >= width of type
kernel/time/clocksource.c:655: warning: passing argument 1 of '__div64_32' from incompatible pointer type
include/asm-generic/div64.h:35: note: expected 'uint64_t *' but argument is of type 'long unsigned int *'
kernel/time/clocksource.c:656: warning: comparison of distinct pointer types lacks a cast
kernel/time/clocksource.c:656: warning: right shift count >= width of type
kernel/time/clocksource.c:656: warning: passing argument 1 of '__div64_32' from incompatible pointer type
include/asm-generic/div64.h:35: note: expected 'uint64_t *' but argument is of type 'long unsigned int *'
kernel/time/clockevents.c: In function 'clockevents_config':
kernel/time/clockevents.c:211: warning: comparison of distinct pointer types lacks a cast
kernel/time/clockevents.c:211: warning: right shift count >= width of type
kernel/time/clockevents.c:211: warning: passing argument 1 of '__div64_32' from incompatible pointer type
include/asm-generic/div64.h:35: note: expected 'uint64_t *' but argument is of type 'long unsigned int *'
This is a 32 bit build.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 490 bytes --]
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows for PM
From: Kumar Gala @ 2011-05-20 5:15 UTC (permalink / raw)
To: Kushwaha Prabhakar-B32579
Cc: meet2prabhu@gmail.com, linuxppc-dev@lists.ozlabs.org,
Jiang Yutang-B14898
In-Reply-To: <071A08F2C6A57E4E94D980ECA553F8741D9670@039-SN1MPN1-005.039d.mgd.msft.net>
On May 20, 2011, at 12:01 AM, Kushwaha Prabhakar-B32579 wrote:
>=20
>=20
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>> Sent: Friday, May 20, 2011 10:19 AM
>> To: Kushwaha Prabhakar-B32579
>> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang =
Yutang-
>> B14898
>> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows =
for
>> PM
>>=20
>>=20
>> On May 19, 2011, at 11:41 PM, Kushwaha Prabhakar-B32579 wrote:
>>=20
>>>=20
>>>=20
>>>> -----Original Message-----
>>>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>>>> Sent: Thursday, May 19, 2011 6:53 PM
>>>> To: Kushwaha Prabhakar-B32579
>>>> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang
>>>> Yutang-
>>>> B14898
>>>> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU =
windows
>>>> for PM
>>>>=20
>>>>=20
>>>> On May 19, 2011, at 6:22 AM, Kushwaha Prabhakar-B32579 wrote:
>>>>=20
>>>>> Hi Kumar,
>>>>> Please find my answer in-lined
>>>>>=20
>>>>>> -----Original Message-----
>>>>>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>>>>>> Sent: Thursday, May 19, 2011 12:00 PM
>>>>>> To: Kushwaha Prabhakar-B32579
>>>>>> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang
>>>>>> Yutang-
>>>>>> B14898
>>>>>> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU
>>>>>> windows for PM
>>>>>>=20
>>>>>>=20
>>>>>> On Apr 28, 2011, at 1:38 AM, Prabhakar Kushwaha wrote:
>>>>>>=20
>>>>>>> D3-cold state indicates removal of the clock and power. however
>>>>>>> auxiliary (AUX) Power may remain available even after the main
>>>>>>> power
>>>>>> rails are powered down.
>>>>>>>=20
>>>>>>> wakeup from D3-cold state requires full context restore. Other
>>>>>>> things are taken care in pci-driver except ATMUs.
>>>>>>> ATMU windows needs to be saved and restored during suspend and
>>>> resume.
>>>>>>>=20
>>>>>>> Signed-off-by: Jiang Yutang <b14898@freescale.com>
>>>>>>> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
>>>>>>> ---
>>>>>>> Based upon
>>>>>>> =
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.g
>>>>>>> it
>>>>>>> (b
>>>>>>> ranch master)
>>>>>>>=20
>>>>>>> arch/powerpc/sysdev/fsl_pci.c | 116
>>>>>> +++++++++++++++++++++++++++++++++++++++++
>>>>>>> arch/powerpc/sysdev/fsl_pci.h | 7 ++-
>>>>>>> 2 files changed, 121 insertions(+), 2 deletions(-)
>>>>>>=20
>>>>>> Is this patch for when we are a host or agent?
>>>>>=20
>>>>> This patch is independent of host or agent. It is for supporting =
D3
>>>> cold state for P1022.
>>>>> These functions are called during System level suspend and resume.
>>>>>=20
>>>>> --Prabhakar
>>>>=20
>>>> I'm trying to figure out why this is limited to P1022.
>>>=20
>>> Till now, No SOC was supporting D3 cold state. First time P1022
>> supporting it.
>>> Note: D3 cold state =3D=3D PCIe block Power down
>>>=20
>>=20
>> I'm wondering a few things:
>>=20
>> 1. Is there any reason not to do this for ALL FSL PCIe SoCs?
>=20
> Yes, I am agree with you. It can be done.=20
> But as only P1022 SOC supporting it. There is no use of handling it.
I'm also not clear if the DECLARE_PCI_FIXUP_SUSPEND() is the right way =
for us to connect up these suspend/resume functions.
>> 2. why do bother saving state, we don't we re-parse the .dts and
>> reconfigure ATMUs that way?
>=20
> I also thought of this case. But Agent use case scenario forbid me to =
do this.=20
> As ATMU's are programmed by host depending upon different use case . =
And this information is never stored in the dts.
Fair point, but in agent mode will this code ever really be called? It =
seems like we'd never register ourselves with the PCI subsystem so how =
would this get called?
- k=
^ permalink raw reply
* Re: linux-next: manual merge of the tip tree with the powerpc tree
From: Benjamin Herrenschmidt @ 2011-05-20 5:38 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Peter Zijlstra, linux-kernel, Milton Miller, linux-next,
Paul Mackerras, H. Peter Anvin, Thomas Gleixner, linuxppc-dev,
Ingo Molnar
In-Reply-To: <20110520141425.dd38cb7d.sfr@canb.auug.org.au>
On Fri, 2011-05-20 at 14:14 +1000, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the tip tree got a conflict in
> arch/powerpc/kernel/smp.c between commit 23d72bfd8f9f ("powerpc:
> Consolidate ipi message mux and demux") from the powerpc tree and commit
> 184748cc50b2 ("sched: Provide scheduler_ipi() callback in response to
> smp_send_reschedule()") from the tip tree.
>
> The former superceded part of the latter's changes, so I just used the
> former for that.
I've done the merge and resolved the conflict properly (it's actually
non trivial due to some other changes) in the powerpc tree, I'll send a
pull request to Linus later today.
Cheers,
Ben.
^ permalink raw reply
* [PATCH 02/14] powerpc: Add a defconfig for 'corenet' 32-bit platforms
From: Kumar Gala @ 2011-05-20 6:09 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1305871771-16334-1-git-send-email-galak@kernel.crashing.org>
The e500mc and e5500 based cores are only available on corenet based
SoCs. We use this name for the P204x, P3040, P4040, P4080, P50x0 SoCs
and any future processors in these families.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/configs/corenet32_smp_defconfig | 183 ++++++++++++++++++++++++++
1 files changed, 183 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/configs/corenet32_smp_defconfig
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
new file mode 100644
index 0000000..59269a6
--- /dev/null
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -0,0 +1,183 @@
+CONFIG_PPC_85xx=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=8
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_AUDIT=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_RCU_TRACE=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_P3041_DS=y
+CONFIG_P4080_DS=y
+CONFIG_P5020_DS=y
+CONFIG_HIGHMEM=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_MISC=m
+CONFIG_MATH_EMULATION=y
+CONFIG_FORCE_MAX_ZONEORDER=13
+CONFIG_FSL_LBC=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIEASPM is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_ARPD=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6=y
+CONFIG_IP_SCTP=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_MISC_DEVICES=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_FSL=y
+CONFIG_SATA_SIL24=y
+CONFIG_SATA_SIL=y
+CONFIG_PATA_SIL680=y
+CONFIG_NETDEVICES=y
+CONFIG_VITESSE_PHY=y
+CONFIG_FIXED_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_FSL_PQ_MDIO=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_HW_RANDOM=y
+CONFIG_NVRAM=y
+CONFIG_I2C=y
+CONFIG_I2C_MPC=y
+CONFIG_SPI=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_FSL_SPI=y
+CONFIG_SPI_FSL_ESPI=y
+# CONFIG_HWMON is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_USB_HID=m
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
+CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_MPC85XX=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_CMOS=y
+CONFIG_UIO=y
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MAC_PARTITION=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_INFO=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
--
1.7.3.4
^ permalink raw reply related
* [PATCH 01/14] powerpc: Rename e55xx_smp_defconfig to corenet64_smp_defconfig
From: Kumar Gala @ 2011-05-20 6:09 UTC (permalink / raw)
To: linuxppc-dev
Rather than trying to use the core name we use corenet to distinquish
the platform/core combo. corenet64 will be a 64-bit kernel build and
we'll add a new defconfig for corenet32 for a 32-bit platforms.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/configs/corenet64_smp_defconfig | 104 ++++++++++++++++++++++++++
arch/powerpc/configs/e55xx_smp_defconfig | 104 --------------------------
2 files changed, 104 insertions(+), 104 deletions(-)
create mode 100644 arch/powerpc/configs/corenet64_smp_defconfig
delete mode 100644 arch/powerpc/configs/e55xx_smp_defconfig
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
new file mode 100644
index 0000000..d322835
--- /dev/null
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -0,0 +1,104 @@
+CONFIG_PPC64=y
+CONFIG_PPC_BOOK3E_64=y
+# CONFIG_VIRT_CPU_ACCOUNTING is not set
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EXPERT=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_P5020_DS=y
+# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BINFMT_MISC=m
+# CONFIG_PCI is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_ARPD=y
+CONFIG_INET_ESP=y
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6=y
+CONFIG_IP_SCTP=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_LEGACY=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_I2C=y
+# CONFIG_HWMON is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_FSL_DMA=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MAC_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_UTF8=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=m
+CONFIG_FRAME_WARN=1024
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_VIRQ_DEBUG=y
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/configs/e55xx_smp_defconfig b/arch/powerpc/configs/e55xx_smp_defconfig
deleted file mode 100644
index d322835..0000000
--- a/arch/powerpc/configs/e55xx_smp_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_PPC64=y
-CONFIG_PPC_BOOK3E_64=y
-# CONFIG_VIRT_CPU_ACCOUNTING is not set
-CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_P5020_DS=y
-# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_BINFMT_MISC=m
-# CONFIG_PCI is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_ARPD=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IP_SCTP=m
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_PROC_DEVICETREE=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=131072
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_LEGACY=y
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_I2C=y
-# CONFIG_HWMON is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_DMADEVICES=y
-CONFIG_FSL_DMA=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_UTF8=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=m
-CONFIG_FRAME_WARN=1024
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_VIRQ_DEBUG=y
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_DEV_TALITOS=y
--
1.7.3.4
^ permalink raw reply related
* [PATCH 03/14] powerpc/85xx: Add P5020DS device tree
From: Kumar Gala @ 2011-05-20 6:09 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1305871771-16334-2-git-send-email-galak@kernel.crashing.org>
Add basic device tree for P5020DS board. This device tree excludes
support for DPAA and RapidIO nodes.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/boot/dts/p5020ds.dts | 745 +++++++++++++++++++++++++++++++++++++
1 files changed, 745 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p5020ds.dts
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts
new file mode 100644
index 0000000..419e208
--- /dev/null
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -0,0 +1,745 @@
+/*
+ * P5020DS Device Tree Source
+ *
+ * Copyright 2010-2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "fsl,P5020DS";
+ compatible = "fsl,P5020DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ pci3 = &pci3;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ dma0 = &dma0;
+ dma1 = &dma1;
+ sdhc = &sdhc;
+ msi0 = &msi0;
+ msi1 = &msi1;
+ msi2 = &msi2;
+
+ crypto = &crypto;
+ sec_jr0 = &sec_jr0;
+ sec_jr1 = &sec_jr1;
+ sec_jr2 = &sec_jr2;
+ sec_jr3 = &sec_jr3;
+ rtic_a = &rtic_a;
+ rtic_b = &rtic_b;
+ rtic_c = &rtic_c;
+ rtic_d = &rtic_d;
+ sec_mon = &sec_mon;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e5500@0 {
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu1: PowerPC,e5500@1 {
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ soc: soc@ffe000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 29>;
+ };
+
+ corenet-law@0 {
+ compatible = "fsl,corenet-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <32>;
+ };
+
+ memory-controller@8000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+ reg = <0x8000 0x1000>;
+ interrupts = <16 2 1 23>;
+ };
+
+ memory-controller@9000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+ reg = <0x9000 0x1000>;
+ interrupts = <16 2 1 22>;
+ };
+
+ cpc: l3-cache-controller@10000 {
+ compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000
+ 0x11000 0x1000>;
+ interrupts = <16 2 1 27
+ 16 2 1 26>;
+ };
+
+ corenet-cf@18000 {
+ compatible = "fsl,corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 31>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
+
+ iommu@20000 {
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x4000>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 30>;
+ };
+
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi0: msi@41600 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0>;
+ };
+
+ msi1: msi@41800 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41800 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe8 0 0 0
+ 0xe9 0 0 0
+ 0xea 0 0 0
+ 0xeb 0 0 0
+ 0xec 0 0 0
+ 0xed 0 0 0
+ 0xee 0 0 0
+ 0xef 0 0 0>;
+ };
+
+ msi2: msi@41a00 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41a00 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xf0 0 0 0
+ 0xf1 0 0 0
+ 0xf2 0 0 0
+ 0xf3 0 0 0
+ 0xf4 0 0 0
+ 0xf5 0 0 0
+ 0xf6 0 0 0
+ 0xf7 0 0 0>;
+ };
+
+ guts: global-utilities@e0000 {
+ compatible = "fsl,qoriq-device-config-1.0";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ #sleep-cells = <1>;
+ fsl,liodn-bits = <12>;
+ };
+
+ pins: global-utilities@e0e00 {
+ compatible = "fsl,qoriq-pin-control-1.0";
+ reg = <0xe0e00 0x200>;
+ #sleep-cells = <2>;
+ };
+
+ clockgen: global-utilities@e1000 {
+ compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+ reg = <0xe1000 0x1000>;
+ clock-frequency = <0>;
+ };
+
+ rcpm: global-utilities@e2000 {
+ compatible = "fsl,qoriq-rcpm-1.0";
+ reg = <0xe2000 0x1000>;
+ #sleep-cells = <1>;
+ };
+
+ sfp: sfp@e8000 {
+ compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
+ reg = <0xe8000 0x1000>;
+ };
+
+ serdes: serdes@ea000 {
+ compatible = "fsl,p5020-serdes";
+ reg = <0xea000 0x1000>;
+ };
+
+ dma0: dma@100300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
+ reg = <0x100300 0x4>;
+ ranges = <0x0 0x100100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <28 2 0 0>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <29 2 0 0>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <30 2 0 0>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <31 2 0 0>;
+ };
+ };
+
+ dma1: dma@101300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
+ reg = <0x101300 0x4>;
+ ranges = <0x0 0x101100 0x200>;
+ cell-index = <1>;
+ dma-channel@0 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <32 2 0 0>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <33 2 0 0>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <34 2 0 0>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <35 2 0 0>;
+ };
+ };
+
+ spi@110000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
+ reg = <0x110000 0x1000>;
+ interrupts = <53 0x2 0 0>;
+ fsl,espi-num-chipselects = <4>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25sl12801";
+ reg = <0>;
+ spi-max-frequency = <40000000>; /* input clock */
+ partition@u-boot {
+ label = "u-boot";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+ partition@kernel {
+ label = "kernel";
+ reg = <0x00100000 0x00500000>;
+ read-only;
+ };
+ partition@dtb {
+ label = "dtb";
+ reg = <0x00600000 0x00100000>;
+ read-only;
+ };
+ partition@fs {
+ label = "file system";
+ reg = <0x00700000 0x00900000>;
+ };
+ };
+ };
+
+ sdhc: sdhc@114000 {
+ compatible = "fsl,p5020-esdhc", "fsl,esdhc";
+ reg = <0x114000 0x1000>;
+ interrupts = <48 2 0 0>;
+ sdhci,auto-cmd12;
+ clock-frequency = <0>;
+ };
+
+ i2c@118000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x118000 0x100>;
+ interrupts = <38 2 0 0>;
+ dfsrr;
+ };
+
+ i2c@118100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x118100 0x100>;
+ interrupts = <38 2 0 0>;
+ dfsrr;
+ eeprom@51 {
+ compatible = "at24,24c256";
+ reg = <0x51>;
+ };
+ eeprom@52 {
+ compatible = "at24,24c256";
+ reg = <0x52>;
+ };
+ };
+
+ i2c@119000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <2>;
+ compatible = "fsl-i2c";
+ reg = <0x119000 0x100>;
+ interrupts = <39 2 0 0>;
+ dfsrr;
+ };
+
+ i2c@119100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <3>;
+ compatible = "fsl-i2c";
+ reg = <0x119100 0x100>;
+ interrupts = <39 2 0 0>;
+ dfsrr;
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ interrupts = <0x1 0x1 0 0>;
+ };
+ };
+
+ serial0: serial@11c500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11c500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+ };
+
+ serial1: serial@11c600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11c600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+ };
+
+ serial2: serial@11d500 {
+ cell-index = <2>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11d500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+ };
+
+ serial3: serial@11d600 {
+ cell-index = <3>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11d600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+ };
+
+ gpio0: gpio@130000 {
+ compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
+ reg = <0x130000 0x1000>;
+ interrupts = <55 2 0 0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ usb0: usb@210000 {
+ compatible = "fsl,p5020-usb2-mph",
+ "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+ reg = <0x210000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <44 0x2 0 0>;
+ phy_type = "utmi";
+ port0;
+ };
+
+ usb1: usb@211000 {
+ compatible = "fsl,p5020-usb2-dr",
+ "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+ reg = <0x211000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <45 0x2 0 0>;
+ dr_mode = "host";
+ phy_type = "utmi";
+ };
+
+ sata@220000 {
+ compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
+ reg = <0x220000 0x1000>;
+ interrupts = <68 0x2 0 0>;
+ };
+
+ sata@221000 {
+ compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
+ reg = <0x221000 0x1000>;
+ interrupts = <69 0x2 0 0>;
+ };
+
+ crypto: crypto@300000 {
+ compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.2-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+ };
+
+ sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+ };
+ };
+
+ localbus@ffe124000 {
+ compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
+ reg = <0xf 0xfe124000 0 0x1000>;
+ interrupts = <25 2 0 0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0xf 0xe8000000 0x08000000
+ 3 0 0xf 0xffdf0000 0x00008000>;
+
+ flash@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x08000000>;
+ bank-width = <2>;
+ device-width = <2>;
+ };
+
+ board-control@3,0 {
+ compatible = "fsl,p5020ds-pixis";
+ reg = <3 0 0x20>;
+ };
+ };
+
+ pci0: pcie@ffe200000 {
+ compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf 0xfe200000 0 0x1000>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi0>;
+ interrupts = <16 2 1 15>;
+
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 15>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 40 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci1: pcie@ffe201000 {
+ compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf 0xfe201000 0 0x1000>;
+ bus-range = <0 0xff>;
+ ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+ 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi1>;
+ interrupts = <16 2 1 14>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 14>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 41 1 0 0
+ 0000 0 0 2 &mpic 5 1 0 0
+ 0000 0 0 3 &mpic 6 1 0 0
+ 0000 0 0 4 &mpic 7 1 0 0
+ >;
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci2: pcie@ffe202000 {
+ compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf 0xfe202000 0 0x1000>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi2>;
+ interrupts = <16 2 1 13>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 13>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 42 1 0 0
+ 0000 0 0 2 &mpic 9 1 0 0
+ 0000 0 0 3 &mpic 10 1 0 0
+ 0000 0 0 4 &mpic 11 1 0 0
+ >;
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci3: pcie@ffe203000 {
+ compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf 0xfe203000 0 0x1000>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi2>;
+ interrupts = <16 2 1 12>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 12>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 43 1 0 0
+ 0000 0 0 2 &mpic 0 1 0 0
+ 0000 0 0 3 &mpic 4 1 0 0
+ 0000 0 0 4 &mpic 8 1 0 0
+ >;
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+};
--
1.7.3.4
^ permalink raw reply related
* [PATCH 04/14] powerpc/85xx: Add P3041DS device tree
From: Kumar Gala @ 2011-05-20 6:09 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1305871771-16334-3-git-send-email-galak@kernel.crashing.org>
Add basic device tree for P3041DS board. This device tree excludes
support for DPAA and RapidIO nodes.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/boot/dts/p3041ds.dts | 752 +++++++++++++++++++++++++++++++++++++
1 files changed, 752 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p3041ds.dts
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
new file mode 100644
index 0000000..1773571
--- /dev/null
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -0,0 +1,752 @@
+/*
+ * P3041DS Device Tree Source
+ *
+ * Copyright 2010-2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "fsl,P3041DS";
+ compatible = "fsl,P3041DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ pci3 = &pci3;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ dma0 = &dma0;
+ dma1 = &dma1;
+ sdhc = &sdhc;
+ msi0 = &msi0;
+ msi1 = &msi1;
+ msi2 = &msi2;
+
+ crypto = &crypto;
+ sec_jr0 = &sec_jr0;
+ sec_jr1 = &sec_jr1;
+ sec_jr2 = &sec_jr2;
+ sec_jr3 = &sec_jr3;
+ rtic_a = &rtic_a;
+ rtic_b = &rtic_b;
+ rtic_c = &rtic_c;
+ rtic_d = &rtic_d;
+ sec_mon = &sec_mon;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e500mc@0 {
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu1: PowerPC,e500mc@1 {
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu2: PowerPC,e500mc@2 {
+ device_type = "cpu";
+ reg = <2>;
+ next-level-cache = <&L2_2>;
+ L2_2: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu3: PowerPC,e500mc@3 {
+ device_type = "cpu";
+ reg = <3>;
+ next-level-cache = <&L2_3>;
+ L2_3: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ soc: soc@ffe000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 29>;
+ };
+
+ corenet-law@0 {
+ compatible = "fsl,corenet-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <32>;
+ };
+
+ memory-controller@8000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+ reg = <0x8000 0x1000>;
+ interrupts = <16 2 1 23>;
+ };
+
+ cpc: l3-cache-controller@10000 {
+ compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000>;
+ interrupts = <16 2 1 27>;
+ };
+
+ corenet-cf@18000 {
+ compatible = "fsl,corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 31>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
+
+ iommu@20000 {
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x4000>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 30>;
+ };
+
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi0: msi@41600 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0>;
+ };
+
+ msi1: msi@41800 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41800 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe8 0 0 0
+ 0xe9 0 0 0
+ 0xea 0 0 0
+ 0xeb 0 0 0
+ 0xec 0 0 0
+ 0xed 0 0 0
+ 0xee 0 0 0
+ 0xef 0 0 0>;
+ };
+
+ msi2: msi@41a00 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41a00 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xf0 0 0 0
+ 0xf1 0 0 0
+ 0xf2 0 0 0
+ 0xf3 0 0 0
+ 0xf4 0 0 0
+ 0xf5 0 0 0
+ 0xf6 0 0 0
+ 0xf7 0 0 0>;
+ };
+
+ guts: global-utilities@e0000 {
+ compatible = "fsl,qoriq-device-config-1.0";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ #sleep-cells = <1>;
+ fsl,liodn-bits = <12>;
+ };
+
+ pins: global-utilities@e0e00 {
+ compatible = "fsl,qoriq-pin-control-1.0";
+ reg = <0xe0e00 0x200>;
+ #sleep-cells = <2>;
+ };
+
+ clockgen: global-utilities@e1000 {
+ compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
+ reg = <0xe1000 0x1000>;
+ clock-frequency = <0>;
+ };
+
+ rcpm: global-utilities@e2000 {
+ compatible = "fsl,qoriq-rcpm-1.0";
+ reg = <0xe2000 0x1000>;
+ #sleep-cells = <1>;
+ };
+
+ sfp: sfp@e8000 {
+ compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
+ reg = <0xe8000 0x1000>;
+ };
+
+ serdes: serdes@ea000 {
+ compatible = "fsl,p3041-serdes";
+ reg = <0xea000 0x1000>;
+ };
+
+ dma0: dma@100300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
+ reg = <0x100300 0x4>;
+ ranges = <0x0 0x100100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <28 2 0 0>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <29 2 0 0>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <30 2 0 0>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <31 2 0 0>;
+ };
+ };
+
+ dma1: dma@101300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
+ reg = <0x101300 0x4>;
+ ranges = <0x0 0x101100 0x200>;
+ cell-index = <1>;
+ dma-channel@0 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <32 2 0 0>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <33 2 0 0>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <34 2 0 0>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <35 2 0 0>;
+ };
+ };
+
+ spi@110000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,p3041-espi", "fsl,mpc8536-espi";
+ reg = <0x110000 0x1000>;
+ interrupts = <53 0x2 0 0>;
+ fsl,espi-num-chipselects = <4>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25sl12801";
+ reg = <0>;
+ spi-max-frequency = <40000000>; /* input clock */
+ partition@u-boot {
+ label = "u-boot";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+ partition@kernel {
+ label = "kernel";
+ reg = <0x00100000 0x00500000>;
+ read-only;
+ };
+ partition@dtb {
+ label = "dtb";
+ reg = <0x00600000 0x00100000>;
+ read-only;
+ };
+ partition@fs {
+ label = "file system";
+ reg = <0x00700000 0x00900000>;
+ };
+ };
+ };
+
+ sdhc: sdhc@114000 {
+ compatible = "fsl,p3041-esdhc", "fsl,esdhc";
+ reg = <0x114000 0x1000>;
+ interrupts = <48 2 0 0>;
+ sdhci,auto-cmd12;
+ clock-frequency = <0>;
+ };
+
+ i2c@118000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x118000 0x100>;
+ interrupts = <38 2 0 0>;
+ dfsrr;
+ };
+
+ i2c@118100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x118100 0x100>;
+ interrupts = <38 2 0 0>;
+ dfsrr;
+ eeprom@51 {
+ compatible = "at24,24c256";
+ reg = <0x51>;
+ };
+ eeprom@52 {
+ compatible = "at24,24c256";
+ reg = <0x52>;
+ };
+ };
+
+ i2c@119000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <2>;
+ compatible = "fsl-i2c";
+ reg = <0x119000 0x100>;
+ interrupts = <39 2 0 0>;
+ dfsrr;
+ };
+
+ i2c@119100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <3>;
+ compatible = "fsl-i2c";
+ reg = <0x119100 0x100>;
+ interrupts = <39 2 0 0>;
+ dfsrr;
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ interrupts = <0x1 0x1 0 0>;
+ };
+ };
+
+ serial0: serial@11c500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11c500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+ };
+
+ serial1: serial@11c600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11c600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+ };
+
+ serial2: serial@11d500 {
+ cell-index = <2>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11d500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+ };
+
+ serial3: serial@11d600 {
+ cell-index = <3>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11d600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+ };
+
+ gpio0: gpio@130000 {
+ compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio";
+ reg = <0x130000 0x1000>;
+ interrupts = <55 2 0 0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ usb0: usb@210000 {
+ compatible = "fsl,p3041-usb2-mph",
+ "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+ reg = <0x210000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <44 0x2 0 0>;
+ phy_type = "utmi";
+ port0;
+ };
+
+ usb1: usb@211000 {
+ compatible = "fsl,p3041-usb2-dr",
+ "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+ reg = <0x211000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <45 0x2 0 0>;
+ dr_mode = "host";
+ phy_type = "utmi";
+ };
+
+ sata@220000 {
+ compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
+ reg = <0x220000 0x1000>;
+ interrupts = <68 0x2 0 0>;
+ };
+
+ sata@221000 {
+ compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
+ reg = <0x221000 0x1000>;
+ interrupts = <69 0x2 0 0>;
+ };
+
+ crypto: crypto@300000 {
+ compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.2-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+ };
+
+ sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+ };
+ };
+
+ localbus@ffe124000 {
+ compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
+ reg = <0xf 0xfe124000 0 0x1000>;
+ interrupts = <25 2 0 0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0xf 0xe8000000 0x08000000
+ 3 0 0xf 0xffdf0000 0x00008000>;
+
+ flash@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x08000000>;
+ bank-width = <2>;
+ device-width = <2>;
+ };
+
+ board-control@3,0 {
+ compatible = "fsl,p3041ds-pixis";
+ reg = <3 0 0x20>;
+ };
+ };
+
+ pci0: pcie@ffe200000 {
+ compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf 0xfe200000 0 0x1000>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi0>;
+ interrupts = <16 2 1 15>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 15>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 40 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci1: pcie@ffe201000 {
+ compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf 0xfe201000 0 0x1000>;
+ bus-range = <0 0xff>;
+ ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+ 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi1>;
+ interrupts = <16 2 1 14>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 14>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 41 1 0 0
+ 0000 0 0 2 &mpic 5 1 0 0
+ 0000 0 0 3 &mpic 6 1 0 0
+ 0000 0 0 4 &mpic 7 1 0 0
+ >;
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci2: pcie@ffe202000 {
+ compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf 0xfe202000 0 0x1000>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi2>;
+ interrupts = <16 2 1 13>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 13>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 42 1 0 0
+ 0000 0 0 2 &mpic 9 1 0 0
+ 0000 0 0 3 &mpic 10 1 0 0
+ 0000 0 0 4 &mpic 11 1 0 0
+ >;
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci3: pcie@ffe203000 {
+ compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf 0xfe203000 0 0x1000>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi2>;
+ interrupts = <16 2 1 12>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 12>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 43 1 0 0
+ 0000 0 0 2 &mpic 0 1 0 0
+ 0000 0 0 3 &mpic 4 1 0 0
+ 0000 0 0 4 &mpic 8 1 0 0
+ >;
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+};
--
1.7.3.4
^ permalink raw reply related
* [PATCH 05/14] powerpc/85xx: Updates to P4080DS device tree
From: Kumar Gala @ 2011-05-20 6:09 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1305871771-16334-4-git-send-email-galak@kernel.crashing.org>
* Added BSD dual-license
* Moved mpic-parent to root so we dont need to duplicate everywhere
* Added next level cache from L2 to CPC
* Moved to 4-cell MPIC interrupt properties
* Added 3 MSI banks
* Added numerous missing nodes: soc-sram-error, guts, pins, clockgen,
rcpm, sfp, serdes, etc.
* Reworked PCIe interrupts to be at virtual bridge level
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/boot/dts/p4080ds.dts | 319 +++++++++++++++++++++++++------------
1 files changed, 217 insertions(+), 102 deletions(-)
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 5b7fc29..6f60a0d 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -1,12 +1,35 @@
/*
* P4080DS Device Tree Source
*
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
@@ -16,6 +39,7 @@
compatible = "fsl,P4080DS";
#address-cells = <2>;
#size-cells = <2>;
+ interrupt-parent = <&mpic>;
aliases {
ccsr = &soc;
@@ -32,6 +56,9 @@
dma0 = &dma0;
dma1 = &dma1;
sdhc = &sdhc;
+ msi0 = &msi0;
+ msi1 = &msi1;
+ msi2 = &msi2;
rio0 = &rapidio0;
};
@@ -45,6 +72,7 @@
reg = <0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
+ next-level-cache = <&cpc>;
};
};
cpu1: PowerPC,4080@1 {
@@ -52,6 +80,7 @@
reg = <1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
+ next-level-cache = <&cpc>;
};
};
cpu2: PowerPC,4080@2 {
@@ -59,6 +88,7 @@
reg = <2>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
+ next-level-cache = <&cpc>;
};
};
cpu3: PowerPC,4080@3 {
@@ -66,6 +96,7 @@
reg = <3>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
+ next-level-cache = <&cpc>;
};
};
cpu4: PowerPC,4080@4 {
@@ -73,6 +104,7 @@
reg = <4>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
+ next-level-cache = <&cpc>;
};
};
cpu5: PowerPC,4080@5 {
@@ -80,6 +112,7 @@
reg = <5>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
+ next-level-cache = <&cpc>;
};
};
cpu6: PowerPC,4080@6 {
@@ -87,6 +120,7 @@
reg = <6>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
+ next-level-cache = <&cpc>;
};
};
cpu7: PowerPC,4080@7 {
@@ -94,6 +128,7 @@
reg = <7>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
+ next-level-cache = <&cpc>;
};
};
};
@@ -110,6 +145,11 @@
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 29>;
+ };
+
corenet-law@0 {
compatible = "fsl,corenet-law";
reg = <0x0 0x1000>;
@@ -117,42 +157,132 @@
};
memory-controller@8000 {
- compatible = "fsl,p4080-memory-controller";
+ compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <0x12 2>;
+ interrupts = <16 2 1 23>;
};
memory-controller@9000 {
- compatible = "fsl,p4080-memory-controller";
+ compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
reg = <0x9000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <0x12 2>;
+ interrupts = <16 2 1 22>;
+ };
+
+ cpc: l3-cache-controller@10000 {
+ compatible = "fsl,p4080-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000
+ 0x11000 0x1000>;
+ interrupts = <16 2 1 27
+ 16 2 1 26>;
};
corenet-cf@18000 {
compatible = "fsl,corenet-cf";
reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;
fsl,ccf-num-snoopids = <32>;
};
iommu@20000 {
- compatible = "fsl,p4080-pamu";
- reg = <0x20000 0x10000>;
- interrupts = <24 2>;
- interrupt-parent = <&mpic>;
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x5000>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 30>;
};
mpic: pic@40000 {
+ clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
- #interrupt-cells = <2>;
+ #interrupt-cells = <4>;
reg = <0x40000 0x40000>;
- compatible = "chrp,open-pic";
+ compatible = "fsl,mpic", "chrp,open-pic";
device_type = "open-pic";
};
+ msi0: msi@41600 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0>;
+ };
+
+ msi1: msi@41800 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41800 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe8 0 0 0
+ 0xe9 0 0 0
+ 0xea 0 0 0
+ 0xeb 0 0 0
+ 0xec 0 0 0
+ 0xed 0 0 0
+ 0xee 0 0 0
+ 0xef 0 0 0>;
+ };
+
+ msi2: msi@41a00 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41a00 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xf0 0 0 0
+ 0xf1 0 0 0
+ 0xf2 0 0 0
+ 0xf3 0 0 0
+ 0xf4 0 0 0
+ 0xf5 0 0 0
+ 0xf6 0 0 0
+ 0xf7 0 0 0>;
+ };
+
+ guts: global-utilities@e0000 {
+ compatible = "fsl,qoriq-device-config-1.0";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ #sleep-cells = <1>;
+ fsl,liodn-bits = <12>;
+ };
+
+ pins: global-utilities@e0e00 {
+ compatible = "fsl,qoriq-pin-control-1.0";
+ reg = <0xe0e00 0x200>;
+ #sleep-cells = <2>;
+ };
+
+ clockgen: global-utilities@e1000 {
+ compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
+ reg = <0xe1000 0x1000>;
+ clock-frequency = <0>;
+ };
+
+ rcpm: global-utilities@e2000 {
+ compatible = "fsl,qoriq-rcpm-1.0";
+ reg = <0xe2000 0x1000>;
+ #sleep-cells = <1>;
+ };
+
+ sfp: sfp@e8000 {
+ compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
+ reg = <0xe8000 0x1000>;
+ };
+
+ serdes: serdes@ea000 {
+ compatible = "fsl,p4080-serdes";
+ reg = <0xea000 0x1000>;
+ };
+
dma0: dma@100300 {
#address-cells = <1>;
#size-cells = <1>;
@@ -165,32 +295,28 @@
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
- interrupt-parent = <&mpic>;
- interrupts = <28 2>;
+ interrupts = <28 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
- interrupt-parent = <&mpic>;
- interrupts = <29 2>;
+ interrupts = <29 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
- interrupt-parent = <&mpic>;
- interrupts = <30 2>;
+ interrupts = <30 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
- interrupt-parent = <&mpic>;
- interrupts = <31 2>;
+ interrupts = <31 2 0 0>;
};
};
@@ -206,32 +332,28 @@
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
- interrupt-parent = <&mpic>;
- interrupts = <32 2>;
+ interrupts = <32 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
- interrupt-parent = <&mpic>;
- interrupts = <33 2>;
+ interrupts = <33 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
- interrupt-parent = <&mpic>;
- interrupts = <34 2>;
+ interrupts = <34 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
- interrupt-parent = <&mpic>;
- interrupts = <35 2>;
+ interrupts = <35 2 0 0>;
};
};
@@ -240,8 +362,7 @@
#size-cells = <0>;
compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
reg = <0x110000 0x1000>;
- interrupts = <53 0x2>;
- interrupt-parent = <&mpic>;
+ interrupts = <53 0x2 0 0>;
fsl,espi-num-chipselects = <4>;
flash@0 {
@@ -275,10 +396,10 @@
sdhc: sdhc@114000 {
compatible = "fsl,p4080-esdhc", "fsl,esdhc";
reg = <0x114000 0x1000>;
- interrupts = <48 2>;
- interrupt-parent = <&mpic>;
+ interrupts = <48 2 0 0>;
voltage-ranges = <3300 3300>;
sdhci,auto-cmd12;
+ clock-frequency = <0>;
};
i2c@118000 {
@@ -287,8 +408,7 @@
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x118000 0x100>;
- interrupts = <38 2>;
- interrupt-parent = <&mpic>;
+ interrupts = <38 2 0 0>;
dfsrr;
};
@@ -298,8 +418,7 @@
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x118100 0x100>;
- interrupts = <38 2>;
- interrupt-parent = <&mpic>;
+ interrupts = <38 2 0 0>;
dfsrr;
eeprom@51 {
compatible = "at24,24c256";
@@ -312,8 +431,7 @@
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
- interrupts = <0 0x1>;
- interrupt-parent = <&mpic>;
+ interrupts = <0x1 0x1 0 0>;
};
};
@@ -323,8 +441,7 @@
cell-index = <2>;
compatible = "fsl-i2c";
reg = <0x119000 0x100>;
- interrupts = <39 2>;
- interrupt-parent = <&mpic>;
+ interrupts = <39 2 0 0>;
dfsrr;
};
@@ -334,8 +451,7 @@
cell-index = <3>;
compatible = "fsl-i2c";
reg = <0x119100 0x100>;
- interrupts = <39 2>;
- interrupt-parent = <&mpic>;
+ interrupts = <39 2 0 0>;
dfsrr;
};
@@ -345,8 +461,7 @@
compatible = "ns16550";
reg = <0x11c500 0x100>;
clock-frequency = <0>;
- interrupts = <36 2>;
- interrupt-parent = <&mpic>;
+ interrupts = <36 2 0 0>;
};
serial1: serial@11c600 {
@@ -355,8 +470,7 @@
compatible = "ns16550";
reg = <0x11c600 0x100>;
clock-frequency = <0>;
- interrupts = <36 2>;
- interrupt-parent = <&mpic>;
+ interrupts = <36 2 0 0>;
};
serial2: serial@11d500 {
@@ -365,8 +479,7 @@
compatible = "ns16550";
reg = <0x11d500 0x100>;
clock-frequency = <0>;
- interrupts = <37 2>;
- interrupt-parent = <&mpic>;
+ interrupts = <37 2 0 0>;
};
serial3: serial@11d600 {
@@ -375,15 +488,13 @@
compatible = "ns16550";
reg = <0x11d600 0x100>;
clock-frequency = <0>;
- interrupts = <37 2>;
- interrupt-parent = <&mpic>;
+ interrupts = <37 2 0 0>;
};
gpio0: gpio@130000 {
- compatible = "fsl,p4080-gpio";
+ compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
reg = <0x130000 0x1000>;
- interrupts = <55 2>;
- interrupt-parent = <&mpic>;
+ interrupts = <55 2 0 0>;
#gpio-cells = <2>;
gpio-controller;
};
@@ -394,8 +505,7 @@
reg = <0x210000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupt-parent = <&mpic>;
- interrupts = <44 0x2>;
+ interrupts = <44 0x2 0 0>;
phy_type = "ulpi";
};
@@ -405,8 +515,7 @@
reg = <0x211000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupt-parent = <&mpic>;
- interrupts = <45 0x2>;
+ interrupts = <45 0x2 0 0>;
dr_mode = "host";
phy_type = "ulpi";
};
@@ -417,17 +526,21 @@
#size-cells = <2>;
compatible = "fsl,rapidio-delta";
reg = <0xf 0xfe0c0000 0 0x20000>;
- ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
- interrupt-parent = <&mpic>;
- /* err_irq bell_outb_irq bell_inb_irq
- msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
- interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
+ ranges = <0 0 0xc 0x20000000 0 0x01000000>;
+ interrupts = <
+ 16 2 1 11 /* err_irq */
+ 56 2 0 0 /* bell_outb_irq */
+ 57 2 0 0 /* bell_inb_irq */
+ 60 2 0 0 /* msg1_tx_irq */
+ 61 2 0 0 /* msg1_rx_irq */
+ 62 2 0 0 /* msg2_tx_irq */
+ 63 2 0 0>; /* msg2_rx_irq */
};
localbus@ffe124000 {
compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
reg = <0xf 0xfe124000 0 0x1000>;
- interrupts = <25 2>;
+ interrupts = <25 2 0 0>;
#address-cells = <2>;
#size-cells = <1>;
@@ -444,7 +557,6 @@
pci0: pcie@ffe200000 {
compatible = "fsl,p4080-pcie";
device_type = "pci";
- #interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf 0xfe200000 0 0x1000>;
@@ -452,22 +564,23 @@
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
clock-frequency = <0x1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
-
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 40 1
- 0000 0 0 2 &mpic 1 1
- 0000 0 0 3 &mpic 2 1
- 0000 0 0 4 &mpic 3 1
- >;
+ fsl,msi = <&msi0>;
+ interrupts = <16 2 1 15>;
pcie@0 {
reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
+ interrupts = <16 2 1 15>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 40 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
@@ -481,7 +594,6 @@
pci1: pcie@ffe201000 {
compatible = "fsl,p4080-pcie";
device_type = "pci";
- #interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf 0xfe201000 0 0x1000>;
@@ -489,21 +601,23 @@
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
clock-frequency = <0x1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 41 1
- 0000 0 0 2 &mpic 5 1
- 0000 0 0 3 &mpic 6 1
- 0000 0 0 4 &mpic 7 1
- >;
+ fsl,msi = <&msi1>;
+ interrupts = <16 2 1 14>;
pcie@0 {
reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
+ interrupts = <16 2 1 14>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 41 1 0 0
+ 0000 0 0 2 &mpic 5 1 0 0
+ 0000 0 0 3 &mpic 6 1 0 0
+ 0000 0 0 4 &mpic 7 1 0 0
+ >;
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
@@ -517,7 +631,6 @@
pci2: pcie@ffe202000 {
compatible = "fsl,p4080-pcie";
device_type = "pci";
- #interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf 0xfe202000 0 0x1000>;
@@ -525,21 +638,23 @@
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
clock-frequency = <0x1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 42 1
- 0000 0 0 2 &mpic 9 1
- 0000 0 0 3 &mpic 10 1
- 0000 0 0 4 &mpic 11 1
- >;
+ fsl,msi = <&msi2>;
+ interrupts = <16 2 1 13>;
pcie@0 {
reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
+ interrupts = <16 2 1 13>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 42 1 0 0
+ 0000 0 0 2 &mpic 9 1 0 0
+ 0000 0 0 3 &mpic 10 1 0 0
+ 0000 0 0 4 &mpic 11 1 0 0
+ >;
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
--
1.7.3.4
^ permalink raw reply related
* [PATCH 06/14] powerpc/85xx: Cleanup PCIe support on corenet_ds boards
From: Kumar Gala @ 2011-05-20 6:09 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1305871771-16334-5-git-send-email-galak@kernel.crashing.org>
Several changes on PCIe support on P3041DS/P4080DS/P5020DS boards:
* Add support for "fsl,qoriq-pcie-v2.2" needed by P3041 & P5020
* Removed support for setting primary_phb_addr as we have no ISA need
* Add PCI controller to of_platform_bus_probe (for EDAC)
* Cleanup building w/SWIOTLB off on P4080DS (not stricly PCIe related)
Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com>
Signed-off-by: Laurentiu TUDOR <Laurentiu.Tudor@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/platforms/85xx/corenet_ds.c | 29 ++++++++++++++---------------
arch/powerpc/platforms/85xx/p4080_ds.c | 18 +++---------------
2 files changed, 17 insertions(+), 30 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index 2ab338c..10af3c7 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -3,7 +3,7 @@
*
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
*
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -61,10 +61,6 @@ void __init corenet_ds_pic_init(void)
mpic_init(mpic);
}
-#ifdef CONFIG_PCI
-static int primary_phb_addr;
-#endif
-
/*
* Setup the architecture
*/
@@ -85,17 +81,14 @@ void __init corenet_ds_setup_arch(void)
#endif
#ifdef CONFIG_PCI
- for_each_compatible_node(np, "pci", "fsl,p4080-pcie") {
- struct resource rsrc;
- of_address_to_resource(np, 0, &rsrc);
- if ((rsrc.start & 0xfffff) == primary_phb_addr)
- fsl_add_bridge(np, 1);
- else
+ for_each_node_by_type(np, "pci") {
+ if (of_device_is_compatible(np, "fsl,p4080-pcie") ||
+ of_device_is_compatible(np, "fsl,qoriq-pcie-v2.2")) {
fsl_add_bridge(np, 0);
-
- hose = pci_find_hose_for_OF_device(np);
- max = min(max, hose->dma_window_base_cur +
- hose->dma_window_size);
+ hose = pci_find_hose_for_OF_device(np);
+ max = min(max, hose->dma_window_base_cur +
+ hose->dma_window_size);
+ }
}
#endif
@@ -116,6 +109,12 @@ static const struct of_device_id of_device_ids[] __devinitconst = {
{
.compatible = "fsl,rapidio-delta",
},
+ {
+ .compatible = "fsl,p4080-pcie",
+ },
+ {
+ .compatible = "fsl,qoriq-pcie-v2.2",
+ },
{}
};
diff --git a/arch/powerpc/platforms/85xx/p4080_ds.c b/arch/powerpc/platforms/85xx/p4080_ds.c
index 8417046..ec8320c 100644
--- a/arch/powerpc/platforms/85xx/p4080_ds.c
+++ b/arch/powerpc/platforms/85xx/p4080_ds.c
@@ -32,10 +32,6 @@
#include "corenet_ds.h"
-#ifdef CONFIG_PCI
-static int primary_phb_addr;
-#endif
-
/*
* Called very early, device-tree isn't unflattened
*/
@@ -43,17 +39,7 @@ static int __init p4080_ds_probe(void)
{
unsigned long root = of_get_flat_dt_root();
- if (of_flat_dt_is_compatible(root, "fsl,P4080DS")) {
-#ifdef CONFIG_PCI
- /* treat PCIe1 as primary,
- * shouldn't matter as we have no ISA on the board
- */
- primary_phb_addr = 0x0000;
-#endif
- return 1;
- } else {
- return 0;
- }
+ return of_flat_dt_is_compatible(root, "fsl,P4080DS");
}
define_machine(p4080_ds) {
@@ -71,4 +57,6 @@ define_machine(p4080_ds) {
};
machine_device_initcall(p4080_ds, corenet_ds_publish_devices);
+#ifdef CONFIG_SWIOTLB
machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier);
+#endif
--
1.7.3.4
^ permalink raw reply related
* [PATCH 07/14] powerpc/fsl_pci: Simplify matching logic for PCI_FIXUP_HEADER
From: Kumar Gala @ 2011-05-20 6:09 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1305871771-16334-6-git-send-email-galak@kernel.crashing.org>
We fixup every FSL PCIe Root Complex we need to fixup a few things.
Rather than adding every device under the sun we move to just matching
only on the vendor (PCI_VENDOR_ID_FREESCALE) and than check that we are
a PCIe controller in host mode in the fixup.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/sysdev/fsl_pci.c | 70 +++++-----------------------------------
1 files changed, 9 insertions(+), 61 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 68ca929..b4d6046d 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -38,10 +38,17 @@ static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
{
+ u8 progif;
+
/* if we aren't a PCIe don't bother */
if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
return;
+ /* if we aren't in host mode don't bother */
+ pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
+ if (progif & 0x1)
+ return;
+
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
fsl_pcie_bus_fixup = 1;
return;
@@ -380,70 +387,11 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
return 0;
}
-
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020, quirk_fsl_pcie_header);
#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
-#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
+#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
struct mpc83xx_pcie_priv {
void __iomem *cfg_type0;
void __iomem *cfg_type1;
--
1.7.3.4
^ permalink raw reply related
* [PATCH 11/14] powerpc/book3e: Clarify HW table walk enable/disable message
From: Kumar Gala @ 2011-05-20 6:09 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1305871771-16334-10-git-send-email-galak@kernel.crashing.org>
Before if we didn't support or enable HW table walk we'd get a messaage
like:
MMU: Book3E Page Tables Disabled
Which is a bit misleading. Now it will say:
MMU: Book3E HW tablewalk not supported
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/mm/tlb_nohash.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 2a030d8..97e6193 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -476,8 +476,8 @@ static void setup_mmu_htw(void)
(unsigned long)&exc_instruction_tlb_miss_htw_book3e, 0);
book3e_htw_enabled = 1;
}
- pr_info("MMU: Book3E Page Tables %s\n",
- book3e_htw_enabled ? "Enabled" : "Disabled");
+ pr_info("MMU: Book3E HW tablewalk %s\n",
+ book3e_htw_enabled ? "enabled" : "not supported");
}
/*
--
1.7.3.4
^ permalink raw reply related
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