* Re: Mapping an executable page
From: Scott Wood @ 2011-06-14 20:26 UTC (permalink / raw)
To: Thomas De Schampheleire; +Cc: linuxppc-dev, Tabi Timur-B04825
In-Reply-To: <BANLkTimhKOvY8XA=_20rjtkZ0Um45o2Bow@mail.gmail.com>
On Tue, 14 Jun 2011 10:56:31 +0200
Thomas De Schampheleire <patrickdepinguin+linuxppc@gmail.com> wrote:
> * Therefore, to make sure that the mapping I intended with __ioremap()
> is actually reflected in the TLB tables, I added dummy reads of each
> page in the TLB, prior to jumping to the boot code, as follows:
> /* make sure memory is read, once every 4Kbyte is enough */
> for (p = vaddr; p < vaddr + map_size; p += 0x1000) {
> unsigned long dummy = *(volatile unsigned long *)p;
> (void)dummy;
> }
>
> * After these changes (make sure all code is mapped + make sure to
> read all pages so that the TLBs are updated), my scenario works fine.
This is fragile -- you are assuming that it's possible to fit this
set of pages in TLB0 all at once, and that none of them will be
evicted/invalidated by the time you're done.
If you really need to do this, I sugest using settlbcam() from
arch/powerpc/mm/fsl_booke_mmu.c to create TLB1 entries with IPROT set.
Better still if you could live with whatever memory the kernel has already
pinned.
-Scott
^ permalink raw reply
* Re: [RFC,PATCH] Cleanup PC parallel port Kconfig
From: Arnd Bergmann @ 2011-06-14 20:22 UTC (permalink / raw)
To: linuxppc-dev
Cc: linux-mips, linux-m68k, linux-ia64, linux-sh, Chen Liqin,
Paul Mackerras, H. Peter Anvin, sparclinux, Guan Xuetao,
Lennox Wu, linux-arch, Jesper Nilsson, Russell King,
Yoshinori Sato, Helge Deller, x86, James E.J. Bottomley,
Ingo Molnar, Geert Uytterhoeven, Matt Turner, Fenghua Yu,
microblaze-uclinux, Chris Metcalf, Mikael Starvik,
Ivan Kokshaysky, Thomas Gleixner, linux-arm-kernel,
Richard Henderson, Chris Zankel, Michal Simek, Tony Luck,
linux-cris-kernel, linux-parisc, linux-kernel, Ralf Baechle,
Kyle McMartin, Paul Mundt, linux-alpha, David S. Miller
In-Reply-To: <20110614190850.GA13526@linux-mips.org>
On Tuesday 14 June 2011 21:08:50 Ralf Baechle wrote:
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 9adc278..2968751f 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -21,6 +21,7 @@ config ARM
> select HAVE_KERNEL_LZO
> select HAVE_KERNEL_LZMA
> select HAVE_IRQ_WORK
> + select HAVE_PC_PARPORT
> select HAVE_PERF_EVENTS
> select PERF_USE_VMALLOC
> select HAVE_REGS_AND_STACK_ACCESS_API
On arm that should only be set on a couple of subarchitectures, but
we can fan that out after your patch goes in, just like you do for Mips
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 2729c66..b8328df 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -128,6 +128,7 @@ config PPC
> select HAVE_REGS_AND_STACK_ACCESS_API
> select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
> select HAVE_GENERIC_HARDIRQS
> + select HAVE_PC_PARPORT
> select HAVE_SPARSE_IRQ
> select IRQ_PER_CPU
> select GENERIC_IRQ_SHOW
Similar to ARM and Mips.
> index e446bab..ceac9b5 100644
> --- a/arch/microblaze/Kconfig
> +++ b/arch/microblaze/Kconfig
> @@ -15,6 +15,7 @@ config MICROBLAZE
> select OF
> select OF_EARLY_FLATTREE
> select HAVE_GENERIC_HARDIRQS
> + select HAVE_PC_PARPORT
> select GENERIC_IRQ_PROBE
> select GENERIC_IRQ_SHOW
>
Highly unlikely, except through PCI.
> diff --git a/arch/score/Kconfig b/arch/score/Kconfig
> index 288add8..ba078d0 100644
> --- a/arch/score/Kconfig
> +++ b/arch/score/Kconfig
> @@ -1,9 +1,10 @@
> menu "Machine selection"
>
> config SCORE
> - def_bool y
> - select HAVE_GENERIC_HARDIRQS
> - select GENERIC_IRQ_SHOW
> + def_bool y
> + select HAVE_GENERIC_HARDIRQS
> + select HAVE_PC_PARPORT
> + select GENERIC_IRQ_SHOW
>
> choice
> prompt "System type"
Certainly not, no PIO support
> diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
> index 0249b8b..3e96eff 100644
> --- a/arch/tile/Kconfig
> +++ b/arch/tile/Kconfig
> @@ -8,6 +8,7 @@ config TILE
> select USE_GENERIC_SMP_HELPERS
> select CC_OPTIMIZE_FOR_SIZE
> select HAVE_GENERIC_HARDIRQS
> + select HAVE_PC_PARPORT
> select GENERIC_IRQ_PROBE
> select GENERIC_PENDING_IRQ if SMP
> select GENERIC_IRQ_SHOW
Only through PCI
> diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
> index e57dcce..3832e7e 100644
> --- a/arch/unicore32/Kconfig
> +++ b/arch/unicore32/Kconfig
> @@ -8,6 +8,7 @@ config UNICORE32
> select HAVE_KERNEL_BZIP2
> select HAVE_KERNEL_LZO
> select HAVE_KERNEL_LZMA
> + select HAVE_PC_PARPORT
> select GENERIC_FIND_FIRST_BIT
> select GENERIC_IRQ_PROBE
> select GENERIC_IRQ_SHOW
Probably not.
I think you can leave these four out right away, provided you add
the section below:
> --- a/drivers/parport/Kconfig
> +++ b/drivers/parport/Kconfig
> @@ -35,8 +35,7 @@ if PARPORT
>
> config PARPORT_PC
>
> tristate "PC-style hardware"
>
> - depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && \
> - (!M68K || ISA) && !MN10300 && !AVR32 && !BLACKFIN
> + depends on HAVE_PC_PARPORT
>
> ---help---
>
> You should say Y here if you have a PC-style parallel port. All
> IBM PC compatible computers and some Alphas have PC-style
>
> @@ -48,6 +47,9 @@ config PARPORT_PC
>
> If unsure, say Y.
>
> +config HAVE_PC_PARPORT
> + bool
> +
As you write, anything that has PCI can theoretically take parallel ports,
so I would always list PCI here as a way to get it anyway. Probably also
ISA and PCMCIA. How about adding this?
config HAVE_PC_PARPORT
bool
default (PCI || ISA || PCMCIA)
Arnd
^ permalink raw reply
* Re: Mapping an executable page
From: Timur Tabi @ 2011-06-14 20:07 UTC (permalink / raw)
To: Thomas De Schampheleire; +Cc: linuxppc-dev
In-Reply-To: <4DF7BE43.1010407@freescale.com>
Timur Tabi wrote:
> Hmmm.... I find that surprising. Memory allocated via ioremap() is supposed to
> be available in interrupt handlers, where TLB mappings can't be created
> on-the-fly. I'm not sure that your observation is correct.
Ok, it turns out I'm wrong. As long as the page is in the page tables (i.e.
physically present in RAM), you can take a TLB miss in an interrupt handler, and
the TLB miss handler will create a TLB for you.
This means that ...
> unsigned long dummy = *(volatile unsigned long *)p;
> (void)dummy;
> }
>
> * After these changes (make sure all code is mapped + make sure to
> read all pages so that the TLBs are updated), my scenario works fine.
is not going to work reliably, because it assumes that the TLBs created by your
multiple ioremap() calls will still be there when your code is called.
If you use just a single ioremap() call, but still touch every page, that should
work for you just as well.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: Mapping an executable page
From: Timur Tabi @ 2011-06-14 20:02 UTC (permalink / raw)
To: Thomas De Schampheleire; +Cc: linuxppc-dev
In-Reply-To: <BANLkTimhKOvY8XA=_20rjtkZ0Um45o2Bow@mail.gmail.com>
Thomas De Schampheleire wrote:
> * However, if you jump to an address in that page, you'll have to make
> sure that the entire code that executes is mapped (make map_size large
> enough).
Well, that seems obvious.
> * When that range spanned multiple pages, I faced the issue of only
> one page being actually mapped in the TLBs. My assumption is that the
> call to __ioremap not necessarily updates the TLBs, but mainly some
> kernel-internal tables. The actual TLB mapping presumably happens when
> a data exception occurs.
Hmmm.... I find that surprising. Memory allocated via ioremap() is supposed to
be available in interrupt handlers, where TLB mappings can't be created
on-the-fly. I'm not sure that your observation is correct.
> * Therefore, to make sure that the mapping I intended with __ioremap()
> is actually reflected in the TLB tables, I added dummy reads of each
> page in the TLB, prior to jumping to the boot code, as follows:
> /* make sure memory is read, once every 4Kbyte is enough */
> for (p = vaddr; p < vaddr + map_size; p += 0x1000) {
You should at least use PAGE_SIZE instead of 0x1000.
> unsigned long dummy = *(volatile unsigned long *)p;
> (void)dummy;
> }
>
> * After these changes (make sure all code is mapped + make sure to
> read all pages so that the TLBs are updated), my scenario works fine.
I still find it hard to believe that this is necessary.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [PATCH 00/15] Backport 8xx TLB to 2.4
From: Willy Tarreau @ 2011-06-14 19:31 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
Hi Joakim,
On Tue, Jun 14, 2011 at 03:54:45PM +0200, Joakim Tjernlund wrote:
> This is a backport from 2.6 which I did to overcome 8xx CPU
> bugs. 8xx does not update the DAR register when taking a TLB
> error caused by dcbX and icbi insns which makes it very
> tricky to use these insns. Also the dcbst wrongly sets the
> the store bit when faulting into DTLB error.
> A few more bugs very found during development.
>
> I know 2.4 is in strict maintenance mode and 8xx is obsolete
> but as it is still in use I wanted 8xx to age with grace.
OK, I'm not opposed to merge these patches and I really welcome your
work and want to thank you for having done it. However, I have
absolutely *zero* skills on ppc, so I want to ensure that someone
(possibly you) will be able to back me up in case of reported
regressions once these patches are merged. Since you say that the
code works on your board, I'm not much worried but at least Dan's
comment about the risk of performance regression has to be considered.
If we all agree that it's a tradeoff between performance and stability
or security, then that's a different matter of course !
Thanks !
Willy
^ permalink raw reply
* [RFC,PATCH] Cleanup PC parallel port Kconfig
From: Ralf Baechle @ 2011-06-14 19:08 UTC (permalink / raw)
To: linux-arch, Benjamin Herrenschmidt, Chen Liqin, Chris Metcalf,
Chris Zankel, David S. Miller, Fenghua Yu, Geert Uytterhoeven,
Guan Xuetao, Helge Deller, H. Peter Anvin, Ingo Molnar,
Ivan Kokshaysky, James E.J. Bottomley, Jesper Nilsson,
Kyle McMartin, Lennox Wu, Matt Turner, Michal Simek,
Mikael Starvik, Paul Mackerras, Paul Mundt, Ralf Baechle,
Richard Henderson, Russell King, sparclinux, Thomas Gleixner,
Tony Luck, x86, Yoshinori Sato
Cc: linux-mips, linux-m68k, linux-ia64, linux-parisc,
linux-cris-kernel, linux-sh, microblaze-uclinux, linux-kernel,
linux-alpha, linuxppc-dev, linux-arm-kernel
The PC parallel port Kconfig as acquired one of those messy terms to
describe it's architecture dependencies:
depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && \
(!M68K || ISA) && !MN10300 && !AVR32 && !BLACKFIN
This isn't just ugly - it also almost certainly describes the dependencies
too coarse grainedly. This is an attempt at cleaing the mess up.
I tried to faithfully aproximate the old behaviour but the existing
behaviour seems inacurate if not wrong for some architectures or platforms.
To improve on this I rely on comments from other arch and platforms
maintainers. Any system that can take PCI multi-IO card or has a PC-style
parallel port on the mainboard should probably should now do a
select HAVE_PC_PARPORT. And some arch Kconfig files should further
restrict the use of HAVE_PC_PARPORT to only those platforms that actually
need it.
Thanks,
Ralf
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/alpha/Kconfig | 1 +
arch/arm/Kconfig | 1 +
arch/cris/Kconfig | 1 +
arch/h8300/Kconfig | 1 +
arch/ia64/Kconfig | 1 +
arch/m68k/Kconfig.mmu | 1 +
arch/microblaze/Kconfig | 1 +
arch/mips/Kconfig | 16 ++++++++++++++++
arch/parisc/Kconfig | 1 +
arch/powerpc/Kconfig | 1 +
arch/score/Kconfig | 7 ++++---
arch/sh/Kconfig | 1 +
arch/sparc/Kconfig | 1 +
arch/tile/Kconfig | 1 +
arch/unicore32/Kconfig | 1 +
arch/x86/Kconfig | 1 +
arch/xtensa/Kconfig | 1 +
drivers/parport/Kconfig | 6 ++++--
18 files changed, 39 insertions(+), 5 deletions(-)
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 60219bf..2ba8dd7 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -9,6 +9,7 @@ config ALPHA
select HAVE_PERF_EVENTS
select HAVE_DMA_ATTRS
select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
select GENERIC_IRQ_PROBE
select AUTO_IRQ_AFFINITY if SMP
select GENERIC_IRQ_SHOW
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9adc278..2968751f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -21,6 +21,7 @@ config ARM
select HAVE_KERNEL_LZO
select HAVE_KERNEL_LZMA
select HAVE_IRQ_WORK
+ select HAVE_PC_PARPORT
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
select HAVE_REGS_AND_STACK_ACCESS_API
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index 17addac..2eda6cf 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -51,6 +51,7 @@ config CRIS
default y
select HAVE_IDE
select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
select GENERIC_IRQ_SHOW
config HZ
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 091ed61..da08646 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -3,6 +3,7 @@ config H8300
default y
select HAVE_IDE
select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
select GENERIC_IRQ_SHOW
config SYMBOL_PREFIX
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 38280ef..849805a 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -23,6 +23,7 @@ config IA64
select HAVE_ARCH_TRACEHOOK
select HAVE_DMA_API_DEBUG
select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
select GENERIC_IRQ_PROBE
select GENERIC_PENDING_IRQ if SMP
select IRQ_PER_CPU
diff --git a/arch/m68k/Kconfig.mmu b/arch/m68k/Kconfig.mmu
index 16539b1..6db5a3e 100644
--- a/arch/m68k/Kconfig.mmu
+++ b/arch/m68k/Kconfig.mmu
@@ -399,6 +399,7 @@ config ISA
bool
depends on Q40 || AMIGA_PCMCIA
default y
+ select PARPORT_PC
help
Find out whether you have ISA slots on your motherboard. ISA is the
name of a bus system, i.e. the way the CPU talks to the other stuff
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index e446bab..ceac9b5 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -15,6 +15,7 @@ config MICROBLAZE
select OF
select OF_EARLY_FLATTREE
select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 653da62..51170ba 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -39,6 +39,7 @@ config MIPS_ALCHEMY
select 64BIT_PHYS_ADDR
select CEVT_R4K_LIB
select CSRC_R4K_LIB
+ select HAVE_PC_PARPORT
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
@@ -127,6 +128,7 @@ config MIPS_COBALT
select CSRC_R4K
select CEVT_GT641XX
select DMA_NONCOHERENT
+ select HAVE_PC_PARPORT
select HW_HAS_PCI
select I8253
select I8259
@@ -185,6 +187,7 @@ config MACH_JAZZ
select CSRC_R4K
select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
select GENERIC_ISA_DMA
+ select HAVE_PC_PARPORT
select IRQ_CPU
select I8253
select I8259
@@ -266,6 +269,7 @@ config MIPS_MALTA
select CSRC_R4K
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
+ select HAVE_PC_PARPORT
select IRQ_CPU
select IRQ_GIC
select HW_HAS_PCI
@@ -421,6 +425,7 @@ config SGI_IP22
select CSRC_R4K
select DEFAULT_SGI_PARTITION
select DMA_NONCOHERENT
+ select HAVE_PC_PARPORT
select HW_HAS_EISA
select I8253
select I8259
@@ -483,6 +488,7 @@ config SGI_IP28
select DEFAULT_SGI_PARTITION
select DMA_NONCOHERENT
select GENERIC_ISA_DMA_SUPPORT_BROKEN
+ select HAVE_PC_PARPORT
select IRQ_CPU
select HW_HAS_EISA
select I8253
@@ -517,6 +523,7 @@ config SGI_IP32
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
+ select HAVE_PC_PARPORT
select HW_HAS_PCI
select IRQ_CPU
select R5000_CPU_SCACHE
@@ -535,6 +542,7 @@ config SIBYTE_CRHINE
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
+ select HAVE_PC_PARPORT
select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
@@ -546,6 +554,7 @@ config SIBYTE_CARMEL
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
+ select HAVE_PC_PARPORT
select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
@@ -557,6 +566,7 @@ config SIBYTE_CRHONE
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
+ select HAVE_PC_PARPORT
select SIBYTE_BCM1125
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
@@ -569,6 +579,7 @@ config SIBYTE_RHONE
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
+ select HAVE_PC_PARPORT
select SIBYTE_BCM1125H
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
@@ -580,6 +591,7 @@ config SIBYTE_SWARM
select BOOT_ELF32
select DMA_COHERENT
select HAVE_PATA_PLATFORM
+ select HAVE_PC_PARPORT
select NR_CPUS_DEFAULT_2
select SIBYTE_SB1250
select SWAP_IO_SPACE
@@ -595,6 +607,7 @@ config SIBYTE_LITTLESUR
select BOOT_ELF32
select DMA_COHERENT
select HAVE_PATA_PLATFORM
+ select HAVE_PC_PARPORT
select NR_CPUS_DEFAULT_2
select SIBYTE_SB1250
select SWAP_IO_SPACE
@@ -608,6 +621,7 @@ config SIBYTE_SENTOSA
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
+ select HAVE_PC_PARPORT
select NR_CPUS_DEFAULT_2
select SIBYTE_SB1250
select SWAP_IO_SPACE
@@ -619,6 +633,7 @@ config SIBYTE_BIGSUR
bool "Sibyte BCM91480B-BigSur"
select BOOT_ELF32
select DMA_COHERENT
+ select HAVE_PC_PARPORT
select NR_CPUS_DEFAULT_4
select SIBYTE_BCM1x80
select SWAP_IO_SPACE
@@ -640,6 +655,7 @@ config SNI_RM
select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
+ select HAVE_PC_PARPORT
select HW_HAS_EISA
select HW_HAS_PCI
select IRQ_CPU
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 65adc86..1be72d9 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -13,6 +13,7 @@ config PARISC
select HAVE_PERF_EVENTS
select GENERIC_ATOMIC64 if !64BIT
select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
select GENERIC_IRQ_PROBE
select IRQ_PER_CPU
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 2729c66..b8328df 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -128,6 +128,7 @@ config PPC
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
select HAVE_SPARSE_IRQ
select IRQ_PER_CPU
select GENERIC_IRQ_SHOW
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index 288add8..ba078d0 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -1,9 +1,10 @@
menu "Machine selection"
config SCORE
- def_bool y
- select HAVE_GENERIC_HARDIRQS
- select GENERIC_IRQ_SHOW
+ def_bool y
+ select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
+ select GENERIC_IRQ_SHOW
choice
prompt "System type"
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index f03338c..daa65f3 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -20,6 +20,7 @@ config SUPERH
select HAVE_SYSCALL_TRACEPOINTS
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
select HAVE_SPARSE_IRQ
select IRQ_FORCED_THREADING
select RTC_LIB
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 253986b..3679d7c 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -520,6 +520,7 @@ config PCI
CONFIG_PCI is needed for all JavaStation's (including MrCoffee),
CP-1200, JavaEngine-1, Corona, Red October, and Serengeti SGSC.
All of these platforms are extremely obscure, so say N if unsure.
+ select HAVE_PC_PARPORT if SPARC64
config PCI_DOMAINS
def_bool PCI if SPARC64
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 0249b8b..3e96eff 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -8,6 +8,7 @@ config TILE
select USE_GENERIC_SMP_HELPERS
select CC_OPTIMIZE_FOR_SIZE
select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
select GENERIC_IRQ_PROBE
select GENERIC_PENDING_IRQ if SMP
select GENERIC_IRQ_SHOW
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
index e57dcce..3832e7e 100644
--- a/arch/unicore32/Kconfig
+++ b/arch/unicore32/Kconfig
@@ -8,6 +8,7 @@ config UNICORE32
select HAVE_KERNEL_BZIP2
select HAVE_KERNEL_LZO
select HAVE_KERNEL_LZMA
+ select HAVE_PC_PARPORT
select GENERIC_FIND_FIRST_BIT
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index da34972..750f584 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -70,6 +70,7 @@ config X86
select IRQ_FORCED_THREADING
select USE_GENERIC_SMP_HELPERS if SMP
select HAVE_BPF_JIT if (X86_64 && NET)
+ select HAVE_PC_PARPORT
config INSTRUCTION_DECODER
def_bool (KPROBES || PERF_EVENTS)
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 5d43c1f..d4c3040 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -8,6 +8,7 @@ config XTENSA
def_bool y
select HAVE_IDE
select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
select GENERIC_IRQ_SHOW
help
Xtensa processors are 32-bit RISC machines designed by Tensilica
diff --git a/drivers/parport/Kconfig b/drivers/parport/Kconfig
index d92185a..095a8c7 100644
--- a/drivers/parport/Kconfig
+++ b/drivers/parport/Kconfig
@@ -35,8 +35,7 @@ if PARPORT
config PARPORT_PC
tristate "PC-style hardware"
- depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && \
- (!M68K || ISA) && !MN10300 && !AVR32 && !BLACKFIN
+ depends on HAVE_PC_PARPORT
---help---
You should say Y here if you have a PC-style parallel port. All
IBM PC compatible computers and some Alphas have PC-style
@@ -48,6 +47,9 @@ config PARPORT_PC
If unsure, say Y.
+config HAVE_PC_PARPORT
+ bool
+
config PARPORT_SERIAL
tristate "Multi-IO cards (parallel and serial)"
depends on SERIAL_8250_PCI && PARPORT_PC && PCI
^ permalink raw reply related
* [PATCH] powerpc/85xx: add hypervisor config entries to corenet_smp_defconfig
From: Timur Tabi @ 2011-06-14 19:06 UTC (permalink / raw)
To: kumar.gala, linuxppc-dev
CONFIG_PPC_EPAPR_HV_BYTECHAN adds support for the Freescale hypervisor
byte channel tty driver.
CONFIG_VIRT_DRIVERS and CONFIG_FSL_HV_MANAGER add support for the Freescale
hypervisor management driver.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
arch/powerpc/configs/corenet32_smp_defconfig | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index de9bd16..75fd124 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -108,6 +108,7 @@ CONFIG_FSL_PQ_MDIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_LEGACY_PTYS is not set
+CONFIG_PPC_EPAPR_HV_BYTECHAN=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
@@ -149,6 +150,8 @@ CONFIG_STAGING=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
# CONFIG_STAGING_EXCLUDE_BUILD is not set
+CONFIG_VIRT_DRIVERS=y
+CONFIG_FSL_HV_MANAGER=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
--
1.7.4.4
^ permalink raw reply related
* Re: [PATCH] powerpc/mm: add devmem_is_allowed() for STRICT_DEVMEM checking
From: Scott Wood @ 2011-06-14 19:04 UTC (permalink / raw)
To: Steve Best; +Cc: linuxppc-dev, Nathan Lynch
In-Reply-To: <1308075422.13495.8.camel@dhcp-100-2-27.bos.redhat.com>
On Tue, 14 Jun 2011 14:17:01 -0400
Steve Best <sfbest@us.ibm.com> wrote:
> On Tue, 2011-06-14 at 12:30 -0500, Nathan Lynch wrote:
> > Hi Steve,
> >
> > On Tue, 2011-06-14 at 12:58 -0400, Steve Best wrote:
> > > +/*
> > > + * devmem_is_allowed() checks to see if /dev/mem access to a certain address
> > > + * is valid. The argument is a physical page number.
> > > + *
> > > + * On PowerPC, access has to be given to data regions used by X. We have to
> > > + * disallow access to device-exclusive MMIO regions and system RAM.
> > > + */
> > > +int devmem_is_allowed(unsigned long pfn)
> > > +{
> > > + if ((pfn >= 57360 || pfn <= 57392))
> > > + return 1;
> >
> > That seems... fragile. Where do these numbers come from, and are they
> > appropriate for all platforms and configurations?
>
> This is the range I got from testing pseries blades and servers. maybe
> there is a better way to get this range anyone know of a way?
Use iomem_is_exclusive(), as other architectures (e.g. x86, arm) do.
Anything else is both platform-specific, and inappropriate hardcoding of
policy.
-Scott
^ permalink raw reply
* g4 cube [off topic query]
From: kevin diggs @ 2011-06-14 18:23 UTC (permalink / raw)
To: linuxppc-dev
Hi,
Sorry for the noise ... But if anyone knows what a "Cube power button
gasket" is made of please share! Is it conductive?
Again, sorry for the noise. But I figured there might be some cube
owners out here.
Thanks!
kevin
^ permalink raw reply
* Re: [PATCH 06/15] 8xx: Always pin kernel instruction TLB
From: Joakim Tjernlund @ 2011-06-14 18:19 UTC (permalink / raw)
To: Dan Malek; +Cc: Scott Wood, linuxppc-dev, Willy Tarreau
In-Reply-To: <792A171E-D1E1-4F35-8AC2-40C5A7519D78@digitaldans.com>
Dan Malek <ppc6dev@digitaldans.com> wrote on 2011/06/14 20:11:18:
>
>
> Hi Joakim.
>
> On Jun 14, 2011, at 11:00 AM, Joakim Tjernlund wrote:
>
> > I don't have a mpc850, do you?
>
> I have to say I do :-)
Good, you get to beat the crap out of it then :)
>
> > Probably but that is another matter. You could continue with that
> > if you like but I am stopping here ATM.
>
> Oh, come on... I've been thinking about this for years, wouldn't
> you like to work on it? It will be fun :-)
Me too, but I didn't get very far though. Just had it in my mind but
never got to actually looking at the code. Do you have some pointers?
Jocke
^ permalink raw reply
* Re: [PATCH] powerpc/mm: add devmem_is_allowed() for STRICT_DEVMEM checking
From: Steve Best @ 2011-06-14 18:17 UTC (permalink / raw)
To: Nathan Lynch; +Cc: linuxppc-dev
In-Reply-To: <1308072658.2452.10.camel@orca.stoopid.dyndns.org>
On Tue, 2011-06-14 at 12:30 -0500, Nathan Lynch wrote:
> Hi Steve,
>
> On Tue, 2011-06-14 at 12:58 -0400, Steve Best wrote:
> > diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
> > index e72dcf6..e1aab6b 100644
> > --- a/arch/powerpc/Kconfig.debug
> > +++ b/arch/powerpc/Kconfig.debug
> > @@ -283,4 +283,15 @@ config PPC_EARLY_DEBUG_CPM_ADDR
> > platform probing is done, all platforms selected must
> > share the same address.
> >
> > +config STRICT_DEVMEM
> > + def_bool y
>
> Default new config items to n, please.
ok
>
>
> > --- a/arch/powerpc/mm/mem.c
> > +++ b/arch/powerpc/mm/mem.c
> > @@ -520,3 +520,21 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
> > hash_preload(vma->vm_mm, address, access, trap);
> > #endif /* CONFIG_PPC_STD_MMU */
> > }
> > +
> > +/*
> > + * devmem_is_allowed() checks to see if /dev/mem access to a certain address
> > + * is valid. The argument is a physical page number.
> > + *
> > + * On PowerPC, access has to be given to data regions used by X. We have to
> > + * disallow access to device-exclusive MMIO regions and system RAM.
> > + */
> > +int devmem_is_allowed(unsigned long pfn)
> > +{
> > + if ((pfn >= 57360 || pfn <= 57392))
> > + return 1;
>
> That seems... fragile. Where do these numbers come from, and are they
> appropriate for all platforms and configurations?
This is the range I got from testing pseries blades and servers. maybe
there is a better way to get this range anyone know of a way?
>
>
-Steve
^ permalink raw reply
* Re: [PATCH 06/15] 8xx: Always pin kernel instruction TLB
From: Dan Malek @ 2011-06-14 18:11 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev, Willy Tarreau
In-Reply-To: <OF75A64D65.5ABAA9A9-ONC12578AF.0062124A-C12578AF.0062E416@transmode.se>
Hi Joakim.
On Jun 14, 2011, at 11:00 AM, Joakim Tjernlund wrote:
> I don't have a mpc850, do you?
I have to say I do :-)
> Probably but that is another matter. You could continue with that
> if you like but I am stopping here ATM.
Oh, come on... I've been thinking about this for years, wouldn't
you like to work on it? It will be fun :-)
Thanks.
-- Dan
^ permalink raw reply
* Re: [PATCH 00/15] Backport 8xx TLB to 2.4
From: Joakim Tjernlund @ 2011-06-14 18:10 UTC (permalink / raw)
To: Dan Malek; +Cc: Scott Wood, linuxppc-dev, Willy Tarreau
In-Reply-To: <3BAC0423-7BD1-4BF2-8E5F-FCA7333CFCF5@digitaldans.com>
Dan Malek <digitaldans@digitaldans.com> wrote on 2011/06/14 18:11:51:
>
>
> Hi Joakim.
>
> On Jun 14, 2011, at 6:54 AM, Joakim Tjernlund wrote:
>
> > I know 2.4 is in strict maintenance mode and 8xx is obsolete
> > but as it is still in use I wanted 8xx to age with grace.
>
> Thanks for your continued support. I have recently become
> involved in some 8xx development again, and have noticed
> it is still used more than some may realize.
hehe, 8xx is still hanging on here to. The app. is still in development.
I hope you will give these patches a go and let us know how it went?
Jocke
^ permalink raw reply
* Re: [PATCH 06/15] 8xx: Always pin kernel instruction TLB
From: Joakim Tjernlund @ 2011-06-14 18:00 UTC (permalink / raw)
To: Dan Malek; +Cc: Scott Wood, linuxppc-dev, Willy Tarreau
In-Reply-To: <53DBBA1E-BD8C-4856-9E35-028C8BB0911F@digitaldans.com>
Dan Malek <ppc6dev@digitaldans.com> wrote on 2011/06/14 18:06:45:
>
>
> Hi Joakim.
>
> On Jun 14, 2011, at 6:54 AM, Joakim Tjernlund wrote:
>
> > Various kernel asm modifies SRR0/SRR1 just before executing
> > a rfi. .....
>
> I'm going to argue we can easily visually inspect for this
> since the code is static with just a couple of RFIs in these
> exception handlers.
Yes, but then you also miss out on 8xx: Optimize ITLBMiss handler.
>
> Some 8xx processors have few TLB entries, and always taking
> one for the kernel, especially if it isn't needed, could have a
> detrimental effect on the application performance. Even the
> "big" 8xx processors don't have that many entries. Some
> benchmarks run on an MPC850 would likely show this.
I don't have a mpc850, do you?
>
> Anyone making modifications to this level of software should
> know of this problem, or make it known in a comment. If you
> are making changes, just compile the code and manually
> check it with the couple of configuration options that affect
> the placement of the instructions.
Very fragile but then again, not much are expected to change
in this area for 8xx.
>
> The better solution would be supporting large page sizes,
> at least for the kernel.
Probably but that is another matter. You could continue with that
if you like but I am stopping here ATM.
^ permalink raw reply
* Re: [PATCH] powerpc/mm: add devmem_is_allowed() for STRICT_DEVMEM checking
From: Nathan Lynch @ 2011-06-14 17:30 UTC (permalink / raw)
To: Steve Best; +Cc: linuxppc-dev
In-Reply-To: <20110614165011.23034.66685.sendpatchset@squad5-lp1.lab.bos.redhat.com>
Hi Steve,
On Tue, 2011-06-14 at 12:58 -0400, Steve Best wrote:
> diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
> index e72dcf6..e1aab6b 100644
> --- a/arch/powerpc/Kconfig.debug
> +++ b/arch/powerpc/Kconfig.debug
> @@ -283,4 +283,15 @@ config PPC_EARLY_DEBUG_CPM_ADDR
> platform probing is done, all platforms selected must
> share the same address.
>
> +config STRICT_DEVMEM
> + def_bool y
Default new config items to n, please.
> --- a/arch/powerpc/mm/mem.c
> +++ b/arch/powerpc/mm/mem.c
> @@ -520,3 +520,21 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
> hash_preload(vma->vm_mm, address, access, trap);
> #endif /* CONFIG_PPC_STD_MMU */
> }
> +
> +/*
> + * devmem_is_allowed() checks to see if /dev/mem access to a certain address
> + * is valid. The argument is a physical page number.
> + *
> + * On PowerPC, access has to be given to data regions used by X. We have to
> + * disallow access to device-exclusive MMIO regions and system RAM.
> + */
> +int devmem_is_allowed(unsigned long pfn)
> +{
> + if ((pfn >= 57360 || pfn <= 57392))
> + return 1;
That seems... fragile. Where do these numbers come from, and are they
appropriate for all platforms and configurations?
^ permalink raw reply
* [PATCH] powerpc/mm: add devmem_is_allowed() for STRICT_DEVMEM checking
From: Steve Best @ 2011-06-14 16:58 UTC (permalink / raw)
To: Steve Best, linuxppc-dev; +Cc: Steve Best
Provide devmem_is_allowed() routine to restrict access to kernel
memory from userspace.
Set CONFIG_STRICT_DEVMEM config option to switch on checking.
Signed-off-by: Steve Best <sfbest@us.ibm.com>
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index e72dcf6..e1aab6b 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -283,4 +283,15 @@ config PPC_EARLY_DEBUG_CPM_ADDR
platform probing is done, all platforms selected must
share the same address.
+config STRICT_DEVMEM
+ def_bool y
+ prompt "Filter access to /dev/mem"
+ ---help---
+ This option restricts access to /dev/mem. If this option is
+ disabled, you allow userspace access to all memory, including
+ kernel and userspace memory.
+ Memory access is required for experts who want to debug the kernel.
+
+ If you are unsure, say Y.
+
endmenu
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index 2cd664e..dc2ec96 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -261,6 +261,7 @@ extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
extern void copy_user_page(void *to, void *from, unsigned long vaddr,
struct page *p);
extern int page_is_ram(unsigned long pfn);
+extern int devmem_is_allowed(unsigned long pfn);
#ifdef CONFIG_PPC_SMLPAR
void arch_free_page(struct page *page, int order);
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 29d4dde..b1a6233 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -520,3 +520,21 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
hash_preload(vma->vm_mm, address, access, trap);
#endif /* CONFIG_PPC_STD_MMU */
}
+
+/*
+ * devmem_is_allowed() checks to see if /dev/mem access to a certain address
+ * is valid. The argument is a physical page number.
+ *
+ * On PowerPC, access has to be given to data regions used by X. We have to
+ * disallow access to device-exclusive MMIO regions and system RAM.
+ */
+int devmem_is_allowed(unsigned long pfn)
+{
+ if ((pfn >= 57360 || pfn <= 57392))
+ return 1;
+ if (iomem_is_exclusive(pfn << PAGE_SHIFT))
+ return 0;
+ if (!page_is_ram(pfn))
+ return 1;
+ return 0;
+}
^ permalink raw reply related
* Re: [PATCH 00/15] Backport 8xx TLB to 2.4
From: Dan Malek @ 2011-06-14 16:11 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev, Willy Tarreau
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
Hi Joakim.
On Jun 14, 2011, at 6:54 AM, Joakim Tjernlund wrote:
> I know 2.4 is in strict maintenance mode and 8xx is obsolete
> but as it is still in use I wanted 8xx to age with grace.
Thanks for your continued support. I have recently become
involved in some 8xx development again, and have noticed
it is still used more than some may realize.
-- Dan
^ permalink raw reply
* Re: [PATCH 06/15] 8xx: Always pin kernel instruction TLB
From: Dan Malek @ 2011-06-14 16:06 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev, Willy Tarreau
In-Reply-To: <1308059700-10839-7-git-send-email-Joakim.Tjernlund@transmode.se>
Hi Joakim.
On Jun 14, 2011, at 6:54 AM, Joakim Tjernlund wrote:
> Various kernel asm modifies SRR0/SRR1 just before executing
> a rfi. .....
I'm going to argue we can easily visually inspect for this
since the code is static with just a couple of RFIs in these
exception handlers.
Some 8xx processors have few TLB entries, and always taking
one for the kernel, especially if it isn't needed, could have a
detrimental effect on the application performance. Even the
"big" 8xx processors don't have that many entries. Some
benchmarks run on an MPC850 would likely show this.
Anyone making modifications to this level of software should
know of this problem, or make it known in a comment. If you
are making changes, just compile the code and manually
check it with the couple of configuration options that affect
the placement of the instructions.
The better solution would be supporting large page sizes,
at least for the kernel.
Thanks.
-- Dan
^ permalink raw reply
* [PATCH 01/15] 8xx: Use a macro to simpliy CPU6 errata code.
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 84 +++++++++++--------------------------------
1 files changed, 22 insertions(+), 62 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index f9a30f3..ba05a57 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -31,6 +31,15 @@
#include <asm/ppc_asm.h>
#include "ppc_defs.h"
+/* Macro to make the code more readable. */
+#ifdef CONFIG_8xx_CPU6
+ #define DO_8xx_CPU6(val, reg) \
+ li reg, val; \
+ stw reg, 12(r0); \
+ lwz reg, 12(r0);
+#else
+ #define DO_8xx_CPU6(val, reg)
+#endif
.text
.globl _stext
_stext:
@@ -310,20 +319,14 @@ SystemCall:
InstructionTLBMiss:
#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
- li r3, 0x3f80
- stw r3, 12(r0)
- lwz r3, 12(r0)
#endif
+ DO_8xx_CPU6(0x3f80, r3)
mtspr M_TW, r20 /* Save a couple of working registers */
mfcr r20
stw r20, 0(r0)
stw r21, 4(r0)
mfspr r20, SRR0 /* Get effective address of fault */
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3780
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
+ DO_8xx_CPU6(0x3780, r3)
mtspr MD_EPN, r20 /* Have to use MD_EPN for walk, MI_EPN can't */
mfspr r20, M_TWB /* Get level 1 table entry address */
@@ -345,17 +348,9 @@ InstructionTLBMiss:
tophys(r21,r21)
ori r21,r21,1 /* Set valid bit */
beq- 2f /* If zero, don't try to find a pte */
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x2b80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
+ DO_8xx_CPU6(0x2b80, r3)
mtspr MI_TWC, r21 /* Set segment attributes */
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3b80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
+ DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21 /* Load pte table base address */
mfspr r21, MD_TWC /* ....and get the pte address */
lwz r20, 0(r21) /* Get the pte */
@@ -371,12 +366,7 @@ InstructionTLBMiss:
*/
2: li r21, 0x00f0
rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
-
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x2d80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
+ DO_8xx_CPU6(0x2d80, r3)
mtspr MI_RPN, r20 /* Update TLB entry */
mfspr r20, M_TW /* Restore registers */
@@ -392,10 +382,8 @@ InstructionTLBMiss:
DataStoreTLBMiss:
#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
- li r3, 0x3f80
- stw r3, 12(r0)
- lwz r3, 12(r0)
#endif
+ DO_8xx_CPU6(0x3f80, r3)
mtspr M_TW, r20 /* Save a couple of working registers */
mfcr r20
stw r20, 0(r0)
@@ -419,11 +407,7 @@ DataStoreTLBMiss:
tophys(r21, r21)
ori r21, r21, 1 /* Set valid bit in physical L2 page */
beq- 2f /* If zero, don't try to find a pte */
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3b80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
+ DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21 /* Load pte table base address */
mfspr r20, MD_TWC /* ....and get the pte address */
lwz r20, 0(r20) /* Get the pte */
@@ -435,11 +419,7 @@ DataStoreTLBMiss:
* above.
*/
rlwimi r21, r20, 0, 27, 27
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3b80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
+ DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21
mfspr r21, MD_TWC /* get the pte address again */
@@ -454,12 +434,7 @@ DataStoreTLBMiss:
*/
2: li r21, 0x00f0
rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
-
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3d80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
+ DO_8xx_CPU6(0x3d80, r3)
mtspr MD_RPN, r20 /* Update TLB entry */
mfspr r20, M_TW /* Restore registers */
@@ -491,10 +466,8 @@ InstructionTLBError:
DataTLBError:
#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
- li r3, 0x3f80
- stw r3, 12(r0)
- lwz r3, 12(r0)
#endif
+ DO_8xx_CPU6(0x3f80, r3)
mtspr M_TW, r20 /* Save a couple of working registers */
mfcr r20
stw r20, 0(r0)
@@ -527,11 +500,7 @@ DataTLBError:
ori r21, r21, MD_EVALID
mfspr r20, M_CASID
rlwimi r21, r20, 0, 28, 31
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3780
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
+ DO_8xx_CPU6(0x3780, r3)
mtspr MD_EPN, r21
mfspr r20, M_TWB /* Get level 1 table entry address */
@@ -553,11 +522,7 @@ DataTLBError:
*/
tophys(r21, r21)
ori r21, r21, 1 /* Set valid bit in physical L2 page */
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3b80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
+ DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21 /* Load pte table base address */
mfspr r21, MD_TWC /* ....and get the pte address */
lwz r20, 0(r21) /* Get the pte */
@@ -579,12 +544,7 @@ DataTLBError:
*/
li r21, 0x00f0
rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
-
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3d80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
+ DO_8xx_CPU6(0x3d80, r3)
mtspr MD_RPN, r20 /* Update TLB entry */
mfspr r20, M_TW /* Restore registers */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 11/15] 8xx: Set correct HW pte flags in DTLB Error too
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
DTLB Error needs to adjust the HW PTE bits as DTLB Miss
does.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index a29a011..d701542 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -592,7 +592,12 @@ DARFixed:
mfspr r21, MD_TWC /* get the pte address again */
ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
stw r20, 0(r21) /* and update pte in table */
- xori r20, r20, _PAGE_RW /* RW bit is inverted */
+ rlwimi r20, r20, 32-2, _PAGE_USER>>2 /* Copy USER to Encoding */
+ /* r21 = (r20 & _PAGE_RW) >> 1 */
+ rlwinm r21, r20, 32-1, _PAGE_RW>>1
+ or r20, r21, r20
+ /* invert RW and 0x200 bits */
+ xori r20, r20, _PAGE_RW | 0x200
b finish_DTLB
2:
mfspr r20, M_TW /* Restore registers */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 12/15] 8xx: start using dcbX instructions in various copy routines
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/misc.S | 18 ------------------
arch/ppc/lib/string.S | 17 -----------------
2 files changed, 0 insertions(+), 35 deletions(-)
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index c616098..c291005 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -662,15 +662,7 @@ _GLOBAL(__flush_dcache_icache)
_GLOBAL(clear_page)
li r0,4096/L1_CACHE_LINE_SIZE
mtctr r0
-#ifdef CONFIG_8xx
- li r4, 0
-1: stw r4, 0(r3)
- stw r4, 4(r3)
- stw r4, 8(r3)
- stw r4, 12(r3)
-#else
1: dcbz 0,r3
-#endif
addi r3,r3,L1_CACHE_LINE_SIZE
bdnz 1b
blr
@@ -695,15 +687,6 @@ _GLOBAL(copy_page)
addi r3,r3,-4
addi r4,r4,-4
-#ifdef CONFIG_8xx
- /* don't use prefetch on 8xx */
- li r0,4096/L1_CACHE_LINE_SIZE
- mtctr r0
-1: COPY_16_BYTES
- bdnz 1b
- blr
-
-#else /* not 8xx, we can prefetch */
li r5,4
#if MAX_COPY_PREFETCH > 1
@@ -744,7 +727,6 @@ _GLOBAL(copy_page)
li r0,MAX_COPY_PREFETCH
li r11,4
b 2b
-#endif /* CONFIG_8xx */
/*
* Atomic [test&set] exchange
diff --git a/arch/ppc/lib/string.S b/arch/ppc/lib/string.S
index 6ca54b4..b6ea44b 100644
--- a/arch/ppc/lib/string.S
+++ b/arch/ppc/lib/string.S
@@ -159,14 +159,7 @@ _GLOBAL(cacheable_memzero)
bdnz 4b
3: mtctr r9
li r7,4
-#if !defined(CONFIG_8xx)
10: dcbz r7,r6
-#else
-10: stw r4, 4(r6)
- stw r4, 8(r6)
- stw r4, 12(r6)
- stw r4, 16(r6)
-#endif
addi r6,r6,CACHELINE_BYTES
bdnz 10b
clrlwi r5,r8,32-LG_CACHELINE_BYTES
@@ -261,9 +254,7 @@ _GLOBAL(cacheable_memcpy)
mtctr r0
beq 63f
53:
-#if !defined(CONFIG_8xx)
dcbz r11,r6
-#endif
COPY_16_BYTES
#if L1_CACHE_LINE_SIZE >= 32
COPY_16_BYTES
@@ -443,13 +434,6 @@ _GLOBAL(__copy_tofrom_user)
li r11,4
beq 63f
-#ifdef CONFIG_8xx
- /* Don't use prefetch on 8xx */
- mtctr r0
-53: COPY_16_BYTES_WITHEX(0)
- bdnz 53b
-
-#else /* not CONFIG_8xx */
/* Here we decide how far ahead to prefetch the source */
li r3,4
cmpwi r0,1
@@ -502,7 +486,6 @@ _GLOBAL(__copy_tofrom_user)
li r3,4
li r7,0
bne 114b
-#endif /* CONFIG_8xx */
63: srwi. r0,r5,2
mtctr r0
--
1.7.3.4
^ permalink raw reply related
* [PATCH 04/15] 8xx: Fix CONFIG_PIN_TLB
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
The wrong register was loaded into MD_RPN.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index b3aff21..9d8a1b5 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -848,13 +848,13 @@ initial_mmu:
mtspr MD_TWC, r9
li r11, MI_BOOTINIT /* Create RPN for address 0 */
addis r11, r11, 0x0080 /* Add 8M */
- mtspr MD_RPN, r8
+ mtspr MD_RPN, r11
addis r8, r8, 0x0080 /* Add 8M */
mtspr MD_EPN, r8
mtspr MD_TWC, r9
addis r11, r11, 0x0080 /* Add 8M */
- mtspr MD_RPN, r8
+ mtspr MD_RPN, r11
#endif
/* Since the cache is enabled according to the information we
--
1.7.3.4
^ permalink raw reply related
* [PATCH 10/15] 8xx: Restore _PAGE_WRITETHRU
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 8 ++++++++
include/asm-ppc/pgtable.h | 5 +++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 199ede5..a29a011 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -443,6 +443,10 @@ DataStoreTLBMiss:
* above.
*/
rlwimi r21, r20, 0, 27, 27
+ /* Insert the WriteThru flag into the TWC from the Linux PTE.
+ * It is bit 25 in the Linux PTE and bit 30 in the TWC
+ */
+ rlwimi r21, r20, 32-5, 30, 30
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21
@@ -579,6 +583,10 @@ DARFixed:
* It is bit 27 of both the Linux PTE and the TWC
*/
rlwimi r21, r20, 0, 27, 27
+ /* Insert the WriteThru flag into the TWC from the Linux PTE.
+ * It is bit 25 in the Linux PTE and bit 30 in the TWC
+ */
+ rlwimi r21, r20, 32-5, 30, 30
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21
mfspr r21, MD_TWC /* get the pte address again */
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index 2ba37d3..6cfc5fc 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -298,12 +298,13 @@ extern unsigned long vmalloc_start;
#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
-/* These three software bits must be masked out when the entry is loaded
- * into the TLB, 2 SW bits free.
+/* These four software bits must be masked out when the entry is loaded
+ * into the TLB, 1 SW bits left(0x0080).
*/
#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
#define _PAGE_GUARDED 0x0010 /* software: guarded access */
#define _PAGE_ACCESSED 0x0020 /* software: page referenced */
+#define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */
/* Setting any bits in the nibble with the follow two controls will
* require a TLB exception handler change. It is assumed unused bits
--
1.7.3.4
^ permalink raw reply related
* [PATCH 13/15] 8xx: Use symbolic constants in TLB asm
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
Use the PTE #defines where possible instead of
hardcoded constants.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index d701542..a4290b5 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -442,11 +442,11 @@ DataStoreTLBMiss:
* this into the Linux pgd/pmd and load it in the operation
* above.
*/
- rlwimi r21, r20, 0, 27, 27
+ rlwimi r21, r20, 0, _PAGE_GUARDED
/* Insert the WriteThru flag into the TWC from the Linux PTE.
* It is bit 25 in the Linux PTE and bit 30 in the TWC
*/
- rlwimi r21, r20, 32-5, 30, 30
+ rlwimi r21, r20, 32-5, _PAGE_WRITETHRU>>5
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21
@@ -460,9 +460,9 @@ DataStoreTLBMiss:
/* Honour kernel RO, User NA */
/* 0x200 == Extended encoding, bit 22 */
/* r20 |= (r20 & _PAGE_USER) >> 2 */
- rlwimi r20, r20, 32-2, 0x200
+ rlwimi r20, r20, 32-2, _PAGE_USER>>2 /* Copy USER to Encoding */
/* r21 = (r20 & _PAGE_RW) >> 1 */
- rlwinm r21, r20, 32-1, 0x200
+ rlwinm r21, r20, 32-1, _PAGE_RW>>1
or r20, r21, r20
/* invert RW and 0x200 bits */
xori r20, r20, _PAGE_RW | 0x200
@@ -582,11 +582,11 @@ DARFixed:
/* Insert the Guarded flag into the TWC from the Linux PTE.
* It is bit 27 of both the Linux PTE and the TWC
*/
- rlwimi r21, r20, 0, 27, 27
+ rlwimi r21, r20, 0, _PAGE_GUARDED
/* Insert the WriteThru flag into the TWC from the Linux PTE.
* It is bit 25 in the Linux PTE and bit 30 in the TWC
*/
- rlwimi r21, r20, 32-5, 30, 30
+ rlwimi r21, r20, 32-5, _PAGE_WRITETHRU>>5
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21
mfspr r21, MD_TWC /* get the pte address again */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 14/15] 8xx: Optimize ITLBMiss handler.
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
Don't check for kernel space if no modules.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index a4290b5..7f9e647 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -355,12 +355,17 @@ InstructionTLBMiss:
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
+#ifdef CONFIG_MODULES
+ /* Since we PIN the first 8MB text, we only get ITLB misses
+ * for modules
+ */
andi. r21, r20, 0x0800 /* Address >= 0x80000000 */
beq 3f
lis r21, swapper_pg_dir@h
ori r21, r21, swapper_pg_dir@l
rlwimi r20, r21, 0, 2, 19
3:
+#endif
lwz r21, 0(r20) /* Get the level 1 entry */
rlwinm. r20, r21,0,0,19 /* Extract page descriptor page address */
--
1.7.3.4
^ permalink raw reply related
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