* Re: [PATCH] [v2] ASoC: claim the IRQ when the fsl_ssi device is probed, not opened
From: Mark Brown @ 2011-08-17 1:04 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev, alsa-devel, lrg
In-Reply-To: <1313534865-7795-1-git-send-email-timur@freescale.com>
On Tue, Aug 16, 2011 at 06:47:45PM -0400, Timur Tabi wrote:
> The PowerPC Freescale SSI driver is claiming the IRQ when the IRQ when
> the device is opened, which means that the /proc/interrupts entry for
> the SSI exists only during playback or capture. This also meant that
> the user won't know that the IRQ number is wrong until he tries to use
> the device. Instead, we should claim the IRQ when the device is probed.
Applied, thanks.
^ permalink raw reply
* Re: [PATCH] RapidIO: Add mport driver for Tsi721 bridge
From: Andrew Morton @ 2011-08-16 23:01 UTC (permalink / raw)
To: Alexandre Bounine; +Cc: Chul Kim, linux-kernel, linuxppc-dev
In-Reply-To: <1313178334-6964-1-git-send-email-alexandre.bounine@idt.com>
On Fri, 12 Aug 2011 15:45:34 -0400
Alexandre Bounine <alexandre.bounine@idt.com> wrote:
> Add RapidIO mport driver for IDT TSI721 PCI Express-to-SRIO bridge device.
> The driver provides full set of callback functions defined for mport devices
> in RapidIO subsystem. It also is compatible with current version of RIONET
> driver (Ethernet over RapidIO messaging services).
>
> This patch is applicable to kernel versions starting from 2.6.39.
What a huge driver.
>
> ...
>
> --- /dev/null
> +++ b/drivers/rapidio/devices/Kconfig
> @@ -0,0 +1,10 @@
> +#
> +# RapidIO master port configuration
> +#
> +
> +config RAPIDIO_TSI721
> + bool "IDT Tsi721 PCI Express SRIO Controller support"
> + depends on RAPIDIO && PCI && PCIEPORTBUS
The dependency on PCI is redundant - PCIEPORTBUS already depends on
PCI. Doesn't matter much though.
> + default "n"
> + ---help---
> + Include support for IDT Tsi721 PCI Express Serial RapidIO controller.
>
> ...
>
> +static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
> + u16 destid, u8 hopcount, u32 offset, int len,
> + u32 *data, int do_wr)
> +{
> + struct tsi721_dma_desc *bd_ptr;
> + u32 rd_count, swr_ptr, ch_stat;
> + int i, err = 0;
> + u32 op = do_wr ? MAINT_WR : MAINT_RD;
> +
> + if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32)))
> + return -EINVAL;
> +
> + bd_ptr = priv->bdma[TSI721_DMACH_MAINT].bd_base;
> +
> + rd_count = ioread32(
> + priv->regs + TSI721_DMAC_DRDCNT(TSI721_DMACH_MAINT));
> +
> + /* Initialize DMA descriptor */
> + bd_ptr[0].type_id = cpu_to_le32((DTYPE2 << 29) | (op << 19) | destid);
> + bd_ptr[0].bcount = cpu_to_le32((sys_size << 26) | 0x04);
> + bd_ptr[0].raddr_lo = cpu_to_le32((hopcount << 24) | offset);
> + bd_ptr[0].raddr_hi = 0;
> + if (do_wr)
> + bd_ptr[0].data[0] = cpu_to_be32p(data);
> + else
> + bd_ptr[0].data[0] = 0xffffffff;
> +
> + mb();
> +
> + /* Start DMA operation */
> + iowrite32(rd_count + 2,
> + priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
> + (void)ioread32(priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
> + i = 0;
> +
> + /* Wait until DMA transfer is finished */
> + while ((ch_stat = ioread32(priv->regs +
> + TSI721_DMAC_STS(TSI721_DMACH_MAINT))) & TSI721_DMAC_STS_RUN) {
> + udelay(10);
> + i++;
> + if (i >= 5000000) {
> + dev_dbg(&priv->pdev->dev,
> + "%s : DMA[%d] read timeout ch_status=%x\n",
> + __func__, TSI721_DMACH_MAINT, ch_stat);
> + if (!do_wr)
> + *data = 0xffffffff;
> + err = -EFAULT;
> + goto err_out;
> + }
> + }
Fifty seconds!?!?
EFAULT seems an inappropriate errno.
> + if (ch_stat & TSI721_DMAC_STS_ABORT) {
> + /* If DMA operation aborted due to error,
> + * reinitialize DMA channel
> + */
> + dev_dbg(&priv->pdev->dev, "%s : DMA ABORT ch_stat=%x\n",
> + __func__, ch_stat);
> + dev_dbg(&priv->pdev->dev, "OP=%d : destid=%x hc=%x off=%x\n",
> + do_wr ? MAINT_WR : MAINT_RD, destid, hopcount, offset);
> + iowrite32(TSI721_DMAC_INT_ALL,
> + priv->regs + TSI721_DMAC_INT(TSI721_DMACH_MAINT));
> + iowrite32(TSI721_DMAC_CTL_INIT,
> + priv->regs + TSI721_DMAC_CTL(TSI721_DMACH_MAINT));
> + udelay(10);
> + iowrite32(0, priv->regs +
> + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
> + udelay(1);
> + if (!do_wr)
> + *data = 0xffffffff;
> + err = -EFAULT;
> + goto err_out;
> + }
> +
> + if (!do_wr)
> + *data = be32_to_cpu(bd_ptr[0].data[0]);
> +
> + /*
> + * Update descriptor status FIFO RD pointer.
> + * NOTE: Skipping check and clear FIFO entries because we are waiting
> + * for transfer to be completed.
> + */
> + swr_ptr = ioread32(priv->regs + TSI721_DMAC_DSWP(TSI721_DMACH_MAINT));
> + iowrite32(swr_ptr, priv->regs + TSI721_DMAC_DSRP(TSI721_DMACH_MAINT));
> +err_out:
> +
> + return err;
> +}
>
> ...
>
> +static int
> +tsi721_pw_handler(struct rio_mport *mport)
> +{
> + struct tsi721_device *priv = mport->priv;
> + u32 pw_stat;
> + u32 pw_buf[TSI721_RIO_PW_MSG_SIZE/sizeof(u32)];
> +
> +
> + pw_stat = ioread32(priv->regs + TSI721_RIO_PW_RX_STAT);
> +
> + if (pw_stat & TSI721_RIO_PW_RX_STAT_PW_VAL) {
> + pw_buf[0] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(0));
> + pw_buf[1] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(1));
> + pw_buf[2] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(2));
> + pw_buf[3] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(3));
> +
> + /* Queue PW message (if there is room in FIFO),
> + * otherwise discard it.
> + */
> + spin_lock(&priv->pw_fifo_lock);
> + if (kfifo_avail(&priv->pw_fifo) >= TSI721_RIO_PW_MSG_SIZE)
> + kfifo_in(&priv->pw_fifo, pw_buf,
> + TSI721_RIO_PW_MSG_SIZE);
> + else
> + priv->pw_discard_count++;
> + spin_unlock(&priv->pw_fifo_lock);
> + }
> +
> + /* Clear pending PW interrupts */
> + iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
> + priv->regs + TSI721_RIO_PW_RX_STAT);
> +
> + schedule_work(&priv->pw_work);
I see scheduled work being done, but no flush_scheduled_work() or
similar. This is often a bug, leading to code being executed after
device shutdown or even after rmmod.
> + return 0;
> +}
> +
> +static void tsi721_pw_dpc(struct work_struct *work)
> +{
> + struct tsi721_device *priv = container_of(work, struct tsi721_device,
> + pw_work);
> + unsigned long flags;
> + u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; /* Use full size PW message
> + buffer for RIO layer */
> +
> + /*
> + * Process port-write messages
> + */
> + spin_lock_irqsave(&priv->pw_fifo_lock, flags);
> + while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
> + TSI721_RIO_PW_MSG_SIZE)) {
> + /* Process one message */
> + spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
> +#ifdef DEBUG_PW
> + {
> + u32 i;
> + pr_debug("%s : Port-Write Message:", __func__);
> + for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); ) {
> + pr_debug("0x%02x: %08x %08x %08x %08x", i*4,
> + msg_buffer[i], msg_buffer[i + 1],
> + msg_buffer[i + 2], msg_buffer[i + 3]);
> + i += 4;
> + }
> + pr_debug("\n");
> + }
> +#endif
> + /* Pass the port-write message to RIO core for processing */
> + rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
> + spin_lock_irqsave(&priv->pw_fifo_lock, flags);
> + }
> + spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
> +}
The lock handling in this function is pretty ugly-looking. Is it correct?
>
> ...
>
> +static void tsi721_db_dpc(struct work_struct *work)
> +{
> + struct tsi721_device *priv = container_of(work, struct tsi721_device,
> + idb_work);
> + struct rio_mport *mport;
> + struct rio_dbell *dbell;
> + int found = 0;
> + u32 wr_ptr, rd_ptr;
> + u64 *idb_entry;
> + u32 regval;
> + union {
> + u64 msg;
> + u8 bytes[8];
> + } idb;
> +
> + /*
> + * Process queued inbound doorbells
> + */
> + mport = priv->mport;
> +
> + wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE));
> + rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
> +
> + while (wr_ptr != rd_ptr) {
> + idb_entry = (u64 *)(priv->idb_base +
> + (TSI721_IDB_ENTRY_SIZE * rd_ptr));
> + rd_ptr++;
> + idb.msg = *idb_entry;
Is this code correct on both little-endian and big-endian hardware?
> + *idb_entry = 0;
> +
> + /* Process one doorbell */
> + list_for_each_entry(dbell, &mport->dbells, node) {
> + if ((dbell->res->start <= DBELL_INF(idb.bytes)) &&
> + (dbell->res->end >= DBELL_INF(idb.bytes))) {
> + found = 1;
> + break;
> + }
> + }
> +
> + if (found) {
> + dbell->dinb(mport, dbell->dev_id, DBELL_SID(idb.bytes),
> + DBELL_TID(idb.bytes), DBELL_INF(idb.bytes));
> + } else {
> + dev_dbg(&priv->pdev->dev,
> + "spurious inb doorbell, sid %2.2x tid %2.2x"
> + " info %4.4x\n", DBELL_SID(idb.bytes),
> + DBELL_TID(idb.bytes), DBELL_INF(idb.bytes));
> + }
> + }
> +
> + iowrite32(rd_ptr & (IDB_QSIZE - 1),
> + priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
> +
> + /* Re-enable IDB interrupts */
> + regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
> + regval |= TSI721_SR_CHINT_IDBQRCV;
> + iowrite32(regval,
> + priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
> +}
> +
>
> ...
>
> +static void tsi721_interrupts_init(struct tsi721_device *priv)
> +{
> + u32 intr;
> +
> + /* Enable IDB interrupts */
> + iowrite32(TSI721_SR_CHINT_ALL,
> + priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
> + iowrite32(TSI721_SR_CHINT_IDBQRCV,
> + priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
> + iowrite32(TSI721_INT_SR2PC_CHAN(IDB_QUEUE),
> + priv->regs + TSI721_DEV_CHAN_INTE);
> +
> + /* Enable SRIO MAC interrupts */
> + iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT,
> + priv->regs + TSI721_RIO_EM_DEV_INT_EN);
> +
> + if (priv->flags & TSI721_USING_MSIX)
> + intr = TSI721_DEV_INT_SRIO;
> + else
> + intr = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
> + TSI721_DEV_INT_SMSG_CH;
> +
> + iowrite32(intr, priv->regs + TSI721_DEV_INTE);
> + (void)ioread32(priv->regs + TSI721_DEV_INTE);
Why include all of these void casts, btw?
> +}
> +
> +/**
> + * tsi721_request_msix - register interrupt service for MSI-X mode.
> + * @mport: RapidIO master port structure
> + *
> + * Registers MSI-X interrupt service routines for interrupts that are active
> + * immediately after mport initialization. Messaging interrupt service routines
> + * should be registered during corresponding open requests.
> + */
> +static int tsi721_request_msix(struct rio_mport *mport)
> +{
> + struct tsi721_device *priv = mport->priv;
> + int err = 0;
> +
> + err = request_irq(priv->msix[TSI721_VECT_IDB].vector,
> + tsi721_sr2pc_ch_msix, 0,
> + priv->msix[TSI721_VECT_IDB].irq_name, (void *)mport);
> + if (err)
> + goto out;
> +
> + err = request_irq(priv->msix[TSI721_VECT_PWRX].vector,
> + tsi721_srio_msix, 0,
> + priv->msix[TSI721_VECT_PWRX].irq_name, (void *)mport);
Did we leak the first IRQ here?
> +out:
> + return err;
> +}
> +
>
> ...
>
> +static int tsi721_enable_msix(struct tsi721_device *priv)
> +{
> + struct msix_entry entries[TSI721_VECT_MAX];
> + int err;
> + int i;
> +
> + entries[TSI721_VECT_IDB].entry = TSI721_MSIX_SR2PC_IDBQ_RCV(IDB_QUEUE);
> + entries[TSI721_VECT_PWRX].entry = TSI721_MSIX_SRIO_MAC_INT;
> +
> + /*
> + * Initialize MSI-X entries for Messaging Engine:
> + * this driver supports four RIO mailboxes (inbound and outbound)
> + * NOTE: Inbound message MBOX 0...4 use IB channels 4...7. Therefore
> + * offset +4 is added to IB MBOX number.
> + */
> + for (i = 0; i < RIO_MAX_MBOX; i++) {
> + entries[TSI721_VECT_IMB0_RCV + i].entry =
> + TSI721_MSIX_IMSG_DQ_RCV(i + 4);
> + entries[TSI721_VECT_IMB0_INT + i].entry =
> + TSI721_MSIX_IMSG_INT(i + 4);
> + entries[TSI721_VECT_OMB0_DONE + i].entry =
> + TSI721_MSIX_OMSG_DONE(i);
> + entries[TSI721_VECT_OMB0_INT + i].entry =
> + TSI721_MSIX_OMSG_INT(i);
> + }
> +
> + err = pci_enable_msix(priv->pdev, entries, ARRAY_SIZE(entries));
> + if (err) {
> + if (err > 0)
> + dev_info(&priv->pdev->dev,
> + "Only %d MSI-X vectors available, "
> + "not using MSI-X\n", err);
> + return err;
> + }
> +
> + /*
> + * Copy MSI-X vector information into tsi721 private structure
> + */
> + priv->msix[TSI721_VECT_IDB].vector = entries[TSI721_VECT_IDB].vector;
> + snprintf(priv->msix[TSI721_VECT_IDB].irq_name, IRQ_DEVICE_NAME_MAX,
> + DRV_NAME "-idb@pci:%s", pci_name(priv->pdev));
> + priv->msix[TSI721_VECT_PWRX].vector = entries[TSI721_VECT_PWRX].vector;
> + snprintf(priv->msix[TSI721_VECT_PWRX].irq_name, IRQ_DEVICE_NAME_MAX,
> + DRV_NAME "-pwrx@pci:%s", pci_name(priv->pdev));
> +
> + for (i = 0; i < RIO_MAX_MBOX; i++) {
> + priv->msix[TSI721_VECT_IMB0_RCV + i].vector =
> + entries[TSI721_VECT_IMB0_RCV + i].vector;
> + snprintf(priv->msix[TSI721_VECT_IMB0_RCV + i].irq_name,
> + IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbr%d@pci:%s",
> + i, pci_name(priv->pdev));
> +
> + priv->msix[TSI721_VECT_IMB0_INT + i].vector =
> + entries[TSI721_VECT_IMB0_INT + i].vector;
> + snprintf(priv->msix[TSI721_VECT_IMB0_INT + i].irq_name,
> + IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbi%d@pci:%s",
> + i, pci_name(priv->pdev));
> +
> + priv->msix[TSI721_VECT_OMB0_DONE + i].vector =
> + entries[TSI721_VECT_OMB0_DONE + i].vector;
> + snprintf(priv->msix[TSI721_VECT_OMB0_DONE + i].irq_name,
> + IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombd%d@pci:%s",
> + i, pci_name(priv->pdev));
> +
> + priv->msix[TSI721_VECT_OMB0_INT + i].vector =
> + entries[TSI721_VECT_OMB0_INT + i].vector;
> + snprintf(priv->msix[TSI721_VECT_OMB0_INT + i].irq_name,
> + IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombi%d@pci:%s",
> + i, pci_name(priv->pdev));
> + }
Did we need a dependency on CONFIG_PCI_MSI?
> + return 0;
> +}
> +
>
> ...
>
> +static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
> +{
> + struct tsi721_dma_desc *bd_ptr;
> + u64 *sts_ptr;
> + dma_addr_t bd_phys, sts_phys;
> + int sts_size;
> + int bd_num = priv->bdma[chnum].bd_num;
> +
> + dev_dbg(&priv->pdev->dev, "Init Block DMA Engine, CH%d\n", chnum);
> +
> + /*
> + * Initialize DMA channel for maintenance requests
> + */
> +
> + /* Allocate space for DMA descriptors */
> + bd_ptr = dma_alloc_coherent(&priv->pdev->dev,
> + bd_num * sizeof(struct tsi721_dma_desc),
> + &bd_phys, GFP_KERNEL);
> + if (!bd_ptr)
> + return -ENOMEM;
> +
> + priv->bdma[chnum].bd_phys = bd_phys;
> + priv->bdma[chnum].bd_base = bd_ptr;
> +
> + memset(bd_ptr, 0, bd_num * sizeof(struct tsi721_dma_desc));
There it is again. Perhaps we need a dma_zalloc_coherent().
> + dev_dbg(&priv->pdev->dev, "DMA descriptors @ %p (phys = %llx)\n",
> + bd_ptr, (unsigned long long)bd_phys);
> +
> + /* Allocate space for descriptor status FIFO */
> + sts_size = (bd_num >= TSI721_DMA_MINSTSSZ) ?
> + bd_num : TSI721_DMA_MINSTSSZ;
> + sts_size = roundup_pow_of_two(sts_size);
> + sts_ptr = dma_alloc_coherent(&priv->pdev->dev,
> + sts_size * sizeof(struct tsi721_dma_sts),
> + &sts_phys, GFP_KERNEL);
> + if (!sts_ptr) {
> + /* Free space allocated for DMA descriptors */
> + dma_free_coherent(&priv->pdev->dev,
> + bd_num * sizeof(struct tsi721_dma_desc),
> + bd_ptr, bd_phys);
> + priv->bdma[chnum].bd_base = NULL;
> + return -ENOMEM;
> + }
> +
> + priv->bdma[chnum].sts_phys = sts_phys;
> + priv->bdma[chnum].sts_base = sts_ptr;
> + priv->bdma[chnum].sts_size = sts_size;
> +
> + memset(sts_ptr, 0, sts_size);
and again.
> + dev_dbg(&priv->pdev->dev,
> + "desc status FIFO @ %p (phys = %llx) size=0x%x\n",
> + sts_ptr, (unsigned long long)sts_phys, sts_size);
> +
> + /* Initialize DMA descriptors ring */
> + bd_ptr[bd_num - 1].type_id = cpu_to_le32(DTYPE3 << 29);
> + bd_ptr[bd_num - 1].next_lo = cpu_to_le32((u64)bd_phys &
> + TSI721_DMAC_DPTRL_MASK);
> + bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32);
> +
> + /* Setup DMA descriptor pointers */
> + iowrite32(((u64)bd_phys >> 32),
> + priv->regs + TSI721_DMAC_DPTRH(chnum));
> + iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK),
> + priv->regs + TSI721_DMAC_DPTRL(chnum));
> +
> + /* Setup descriptor status FIFO */
> + iowrite32(((u64)sts_phys >> 32),
> + priv->regs + TSI721_DMAC_DSBH(chnum));
> + iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK),
> + priv->regs + TSI721_DMAC_DSBL(chnum));
> + iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size),
> + priv->regs + TSI721_DMAC_DSSZ(chnum));
> +
> + /* Clear interrupt bits */
> + iowrite32(TSI721_DMAC_INT_ALL,
> + priv->regs + TSI721_DMAC_INT(chnum));
> +
> + (void)ioread32(priv->regs + TSI721_DMAC_INT(chnum));
> +
> + /* Toggle DMA channel initialization */
> + iowrite32(TSI721_DMAC_CTL_INIT, priv->regs + TSI721_DMAC_CTL(chnum));
> + (void)ioread32(priv->regs + TSI721_DMAC_CTL(chnum));
> + udelay(10);
> +
> + return 0;
> +}
> +
>
> ...
>
> +struct tsi721_dma_desc {
> + __le32 type_id;
> +
> +#define TSI721_DMAD_DEVID 0x0000ffff
> +#define TSI721_DMAD_CRF 0x00010000
> +#define TSI721_DMAD_PRIO 0x00060000
> +#define TSI721_DMAD_RTYPE 0x00780000
> +#define TSI721_DMAD_IOF 0x08000000
> +#define TSI721_DMAD_DTYPE 0xe0000000
> +
> + __le32 bcount;
> +
> +#define TSI721_DMAD_BCOUNT1 0x03ffffff /* if DTYPE == 1 */
> +#define TSI721_DMAD_BCOUNT2 0x0000000f /* if DTYPE == 2 */
> +#define TSI721_DMAD_TT 0x0c000000
> +#define TSI721_DMAD_RADDR0 0xc0000000
> +
> + union {
> + __le32 raddr_lo; /* if DTYPE == (1 || 2) */
> + __le32 next_lo; /* if DTYPE == 3 */
> + };
> +
> +#define TSI721_DMAD_CFGOFF 0x00ffffff
> +#define TSI721_DMAD_HOPCNT 0xff000000
> +
> + union {
> + __le32 raddr_hi; /* if DTYPE == (1 || 2) */
> + __le32 next_hi; /* if DTYPE == 3 */
> + };
> +
> + union {
> + struct { /* if DTYPE == 1 */
> + __le32 bufptr_lo;
> + __le32 bufptr_hi;
> + __le32 s_dist;
> + __le32 s_size;
> + } t1;
> + __le32 data[4]; /* if DTYPE == 2 */
> + u32 reserved[4]; /* if DTYPE == 3 */
> + };
> +} __attribute__((aligned(32)));
We have the __aligned helper for this. (more below)
>
> ...
>
^ permalink raw reply
* [PATCH] [v2] ASoC: claim the IRQ when the fsl_ssi device is probed, not opened
From: Timur Tabi @ 2011-08-16 22:47 UTC (permalink / raw)
To: broonie, lrg, linuxppc-dev, alsa-devel
The PowerPC Freescale SSI driver is claiming the IRQ when the IRQ when
the device is opened, which means that the /proc/interrupts entry for
the SSI exists only during playback or capture. This also meant that
the user won't know that the IRQ number is wrong until he tries to use
the device. Instead, we should claim the IRQ when the device is probed.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
sound/soc/fsl/fsl_ssi.c | 61 ++++++++++++++++++++++++++++------------------
1 files changed, 37 insertions(+), 24 deletions(-)
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index d48afea..06ac2b9 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -289,16 +289,6 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
*/
if (!ssi_private->playback && !ssi_private->capture) {
struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
- int ret;
-
- /* The 'name' should not have any slashes in it. */
- ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0,
- ssi_private->name, ssi_private);
- if (ret < 0) {
- dev_err(substream->pcm->card->dev,
- "could not claim irq %u\n", ssi_private->irq);
- return ret;
- }
/*
* Section 16.5 of the MPC8610 reference manual says that the
@@ -522,15 +512,12 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
ssi_private->second_stream = NULL;
/*
- * If this is the last active substream, disable the SSI and release
- * the IRQ.
+ * If this is the last active substream, disable the SSI.
*/
if (!ssi_private->playback && !ssi_private->capture) {
struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
-
- free_irq(ssi_private->irq, ssi_private);
}
}
@@ -675,17 +662,30 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
ret = of_address_to_resource(np, 0, &res);
if (ret) {
dev_err(&pdev->dev, "could not determine device resources\n");
- kfree(ssi_private);
- return ret;
+ goto error_kmalloc;
}
ssi_private->ssi = of_iomap(np, 0);
if (!ssi_private->ssi) {
dev_err(&pdev->dev, "could not map device resources\n");
- kfree(ssi_private);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto error_kmalloc;
}
ssi_private->ssi_phys = res.start;
+
ssi_private->irq = irq_of_parse_and_map(np, 0);
+ if (ssi_private->irq == NO_IRQ) {
+ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
+ ret = -ENXIO;
+ goto error_iomap;
+ }
+
+ /* The 'name' should not have any slashes in it. */
+ ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, ssi_private->name,
+ ssi_private);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "could not claim irq %u\n", ssi_private->irq);
+ goto error_irqmap;
+ }
/* Are the RX and the TX clocks locked? */
if (of_find_property(np, "fsl,ssi-asynchronous", NULL))
@@ -711,7 +711,7 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
if (ret) {
dev_err(&pdev->dev, "could not create sysfs %s file\n",
ssi_private->dev_attr.attr.name);
- goto error;
+ goto error_irq;
}
/* Register with ASoC */
@@ -720,7 +720,7 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
ret = snd_soc_register_dai(&pdev->dev, &ssi_private->cpu_dai_drv);
if (ret) {
dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
- goto error;
+ goto error_dev;
}
/* Trigger the machine driver's probe function. The platform driver
@@ -741,18 +741,28 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
if (IS_ERR(ssi_private->pdev)) {
ret = PTR_ERR(ssi_private->pdev);
dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
- goto error;
+ goto error_dai;
}
return 0;
-error:
+error_dai:
snd_soc_unregister_dai(&pdev->dev);
+
+error_dev:
dev_set_drvdata(&pdev->dev, NULL);
- if (dev_attr)
- device_remove_file(&pdev->dev, dev_attr);
+ device_remove_file(&pdev->dev, dev_attr);
+
+error_irq:
+ free_irq(ssi_private->irq, ssi_private);
+
+error_irqmap:
irq_dispose_mapping(ssi_private->irq);
+
+error_iomap:
iounmap(ssi_private->ssi);
+
+error_kmalloc:
kfree(ssi_private);
return ret;
@@ -766,6 +776,9 @@ static int fsl_ssi_remove(struct platform_device *pdev)
snd_soc_unregister_dai(&pdev->dev);
device_remove_file(&pdev->dev, &ssi_private->dev_attr);
+ free_irq(ssi_private->irq, ssi_private);
+ irq_dispose_mapping(ssi_private->irq);
+
kfree(ssi_private);
dev_set_drvdata(&pdev->dev, NULL);
--
1.7.4.4
^ permalink raw reply related
* [PATCH] [v2] powerpc/85xx: enable the audio drivers in the defconfigs
From: Timur Tabi @ 2011-08-16 22:44 UTC (permalink / raw)
To: kumar.gala, linuxppc-dev
Enable the audio drivers in the non-corenet 85xx defconfigs so that audio
is enabled on the Freescale P1022DS reference board.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
arch/powerpc/configs/mpc85xx_defconfig | 1 +
arch/powerpc/configs/mpc85xx_smp_defconfig | 1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index fcd85d2..a3467bf 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -139,6 +139,7 @@ CONFIG_SND=y
CONFIG_SND_INTEL8X0=y
# CONFIG_SND_PPC is not set
# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 908c941..9693f6e 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -140,6 +140,7 @@ CONFIG_SND=y
CONFIG_SND_INTEL8X0=y
# CONFIG_SND_PPC is not set
# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
--
1.7.4.4
^ permalink raw reply related
* Re: [PATCH] ASoC: claim the IRQ when the fsl_ssi device is probed, not opened
From: Tabi Timur-B04825 @ 2011-08-16 22:41 UTC (permalink / raw)
To: Tabi Timur-B04825
Cc: linuxppc-dev@ozlabs.org, alsa-devel@alsa-project.org,
broonie@opensource.wolfsonmicro.com, lrg@ti.com
In-Reply-To: <1313534150-6642-1-git-send-email-timur@freescale.com>
Timur Tabi wrote:
> The PowerPC Freescale SSI driver is claiming the IRQ when the IRQ when
> the device is opened, which means that the /proc/interrupts entry for
> the SSI exists only during playback or capture. This also meant that
> the user won't know that the IRQ number is wrong until he tries to use
> the device. Instead, we should claim the IRQ when the device is probed.
>
> Signed-off-by: Timur Tabi<timur@freescale.com>
Ugh, somehow I got my patches criss-crossed. Ignore this, please. I'll=20
post a V2 in just a minute.=
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: enable the audio drivers in the defconfigs
From: Tabi Timur-B04825 @ 2011-08-16 22:40 UTC (permalink / raw)
To: Tabi Timur-B04825; +Cc: linuxppc-dev@ozlabs.org, Gala Kumar-B11780
In-Reply-To: <1313534167-6698-1-git-send-email-timur@freescale.com>
Timur Tabi wrote:
> Enable the audio drivers in the non-corenet 85xx defconfigs so that audio
> is enabled on the Freescale P1022DS reference board.
>
> Signed-off-by: Timur Tabi<timur@freescale.com>
Ugh, somehow I got my patches criss-crossed. Ignore this, please. I'll=20
post a V2 in just a minute.=
^ permalink raw reply
* [PATCH] powerpc/85xx: enable the audio drivers in the defconfigs
From: Timur Tabi @ 2011-08-16 22:36 UTC (permalink / raw)
To: kumar.gala, linuxppc-dev
Enable the audio drivers in the non-corenet 85xx defconfigs so that audio
is enabled on the Freescale P1022DS reference board.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
sound/soc/fsl/fsl_ssi.c | 61 ++++++++++++++++++++++++++++------------------
1 files changed, 37 insertions(+), 24 deletions(-)
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index d48afea..06ac2b9 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -289,16 +289,6 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
*/
if (!ssi_private->playback && !ssi_private->capture) {
struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
- int ret;
-
- /* The 'name' should not have any slashes in it. */
- ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0,
- ssi_private->name, ssi_private);
- if (ret < 0) {
- dev_err(substream->pcm->card->dev,
- "could not claim irq %u\n", ssi_private->irq);
- return ret;
- }
/*
* Section 16.5 of the MPC8610 reference manual says that the
@@ -522,15 +512,12 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
ssi_private->second_stream = NULL;
/*
- * If this is the last active substream, disable the SSI and release
- * the IRQ.
+ * If this is the last active substream, disable the SSI.
*/
if (!ssi_private->playback && !ssi_private->capture) {
struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
-
- free_irq(ssi_private->irq, ssi_private);
}
}
@@ -675,17 +662,30 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
ret = of_address_to_resource(np, 0, &res);
if (ret) {
dev_err(&pdev->dev, "could not determine device resources\n");
- kfree(ssi_private);
- return ret;
+ goto error_kmalloc;
}
ssi_private->ssi = of_iomap(np, 0);
if (!ssi_private->ssi) {
dev_err(&pdev->dev, "could not map device resources\n");
- kfree(ssi_private);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto error_kmalloc;
}
ssi_private->ssi_phys = res.start;
+
ssi_private->irq = irq_of_parse_and_map(np, 0);
+ if (ssi_private->irq == NO_IRQ) {
+ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
+ ret = -ENXIO;
+ goto error_iomap;
+ }
+
+ /* The 'name' should not have any slashes in it. */
+ ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, ssi_private->name,
+ ssi_private);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "could not claim irq %u\n", ssi_private->irq);
+ goto error_irqmap;
+ }
/* Are the RX and the TX clocks locked? */
if (of_find_property(np, "fsl,ssi-asynchronous", NULL))
@@ -711,7 +711,7 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
if (ret) {
dev_err(&pdev->dev, "could not create sysfs %s file\n",
ssi_private->dev_attr.attr.name);
- goto error;
+ goto error_irq;
}
/* Register with ASoC */
@@ -720,7 +720,7 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
ret = snd_soc_register_dai(&pdev->dev, &ssi_private->cpu_dai_drv);
if (ret) {
dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
- goto error;
+ goto error_dev;
}
/* Trigger the machine driver's probe function. The platform driver
@@ -741,18 +741,28 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
if (IS_ERR(ssi_private->pdev)) {
ret = PTR_ERR(ssi_private->pdev);
dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
- goto error;
+ goto error_dai;
}
return 0;
-error:
+error_dai:
snd_soc_unregister_dai(&pdev->dev);
+
+error_dev:
dev_set_drvdata(&pdev->dev, NULL);
- if (dev_attr)
- device_remove_file(&pdev->dev, dev_attr);
+ device_remove_file(&pdev->dev, dev_attr);
+
+error_irq:
+ free_irq(ssi_private->irq, ssi_private);
+
+error_irqmap:
irq_dispose_mapping(ssi_private->irq);
+
+error_iomap:
iounmap(ssi_private->ssi);
+
+error_kmalloc:
kfree(ssi_private);
return ret;
@@ -766,6 +776,9 @@ static int fsl_ssi_remove(struct platform_device *pdev)
snd_soc_unregister_dai(&pdev->dev);
device_remove_file(&pdev->dev, &ssi_private->dev_attr);
+ free_irq(ssi_private->irq, ssi_private);
+ irq_dispose_mapping(ssi_private->irq);
+
kfree(ssi_private);
dev_set_drvdata(&pdev->dev, NULL);
--
1.7.4.4
^ permalink raw reply related
* [PATCH] ASoC: claim the IRQ when the fsl_ssi device is probed, not opened
From: Timur Tabi @ 2011-08-16 22:35 UTC (permalink / raw)
To: alsa-devel, linuxppc-dev, broonie, lrg
The PowerPC Freescale SSI driver is claiming the IRQ when the IRQ when
the device is opened, which means that the /proc/interrupts entry for
the SSI exists only during playback or capture. This also meant that
the user won't know that the IRQ number is wrong until he tries to use
the device. Instead, we should claim the IRQ when the device is probed.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
arch/powerpc/configs/mpc85xx_defconfig | 1 +
arch/powerpc/configs/mpc85xx_smp_defconfig | 1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index fcd85d2..a3467bf 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -139,6 +139,7 @@ CONFIG_SND=y
CONFIG_SND_INTEL8X0=y
# CONFIG_SND_PPC is not set
# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 908c941..9693f6e 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -140,6 +140,7 @@ CONFIG_SND=y
CONFIG_SND_INTEL8X0=y
# CONFIG_SND_PPC is not set
# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
--
1.7.4.4
^ permalink raw reply related
* Re: [PATCH] mtd/nand: Don't add disabled nand flash devices
From: Scott Wood @ 2011-08-16 21:46 UTC (permalink / raw)
To: Chunhe Lan; +Cc: dwmw2, kumar.gala, linux-mtd, akpm, linuxppc-dev
In-Reply-To: <1313486855-15233-1-git-send-email-Chunhe.Lan@freescale.com>
On 08/16/2011 04:27 AM, Chunhe Lan wrote:
> Nand flash nodes with the property status=3D"disabled" are not
> usable and so avoid adding "disabled" nand flash devices with
> the system.
>=20
> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
> ---
> drivers/mtd/nand/fsl_elbc_nand.c | 5 ++++-
> 1 files changed, 4 insertions(+), 1 deletions(-)
>=20
> diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_el=
bc_nand.c
> index 33d8aad..8212c12 100644
> --- a/drivers/mtd/nand/fsl_elbc_nand.c
> +++ b/drivers/mtd/nand/fsl_elbc_nand.c
> @@ -1,6 +1,6 @@
> /* Freescale Enhanced Local Bus Controller NAND driver
> *
> - * Copyright =C2=A9 2006-2007, 2010 Freescale Semiconductor
> + * Copyright =C2=A9 2006-2007, 2010-2011 Freescale Semiconductor
> *
> * Authors: Nick Spence <nick.spence@freescale.com>,
> * Scott Wood <scottwood@freescale.com>
> @@ -849,6 +849,9 @@ static int __devinit fsl_elbc_nand_probe(struct pla=
tform_device *pdev)
> struct device *dev;
> struct device_node *node =3D pdev->dev.of_node;
> =20
> + if (!of_device_is_available(node))
> + return -ENODEV;
> +
> if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
> return -ENODEV;
> lbc =3D fsl_lbc_ctrl_dev->regs;
Same comment as the other patch -- unavailable devices should already
not be getting probed. Also, this subject line makes it sound like this
is a NAND subsystem change rather than a change in one specific driver.
-Scott
^ permalink raw reply
* Re: [PATCH] mtd/physmap_of: Don't add disabled flash devices
From: Scott Wood @ 2011-08-16 21:44 UTC (permalink / raw)
To: Chunhe Lan; +Cc: dwmw2, kumar.gala, linux-mtd, akpm, linuxppc-dev
In-Reply-To: <1313486750-15211-1-git-send-email-Chunhe.Lan@freescale.com>
On 08/16/2011 04:25 AM, Chunhe Lan wrote:
> Flash(cfi-flash, jedec-flash, and so on) nodes with the
> property status="disabled" are not usable and so avoid
> adding "disabled" flash devices with the system.
>
> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
> ---
> drivers/mtd/maps/physmap_of.c | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c
> index d251d1d..812e6dc 100644
> --- a/drivers/mtd/maps/physmap_of.c
> +++ b/drivers/mtd/maps/physmap_of.c
> @@ -219,6 +219,9 @@ static int __devinit of_flash_probe(struct platform_device *dev)
> struct mtd_info **mtd_list = NULL;
> resource_size_t res_size;
>
> + if (!of_device_is_available(dp))
> + return -ENODEV;
> +
> match = of_match_device(of_flash_match, &dev->dev);
> if (!match)
> return -EINVAL;
Are you actually seeing unavailable devices get probed? I thought the
upper layers were supposed to prevent that.
-Scott
^ permalink raw reply
* Re: [PATCH] mtd-utils: fix corrupt cleanmarker with flash_erase -j command
From: Brian Norris @ 2011-08-16 19:42 UTC (permalink / raw)
To: dedekind1; +Cc: b35362, linuxppc-dev, linuxppc-dev, linux-mtd, dwmw2
In-Reply-To: <1313507201.2679.2.camel@sauron>
On Tue, Aug 16, 2011 at 8:06 AM, Artem Bityutskiy <dedekind1@gmail.com> wrote:
> On Wed, 2011-08-03 at 13:50 +0800, b35362@freescale.com wrote:
>> From: Liu Shuo <b35362@freescale.com>
>>
>> Flash_erase -j should fill discrete freeoob areas with required bytes
>> of JFFS2 cleanmarker in jffs2_check_nand_cleanmarker(). Not just fill
>> the first freeoob area.
>
> Hmm, shouldn't we instead make MTD_OOB_AUTO be available for userspace
> via an ioctl instead and make flash_eraseall use it instead?
`nandwrite -o' does a similar thing, where it uses MEMGETOOBSEL to
find open spaces in OOB. Both MEMGETOOBSEL and ECCGETLAYOUT have been
declared obsolete. Plus, the code that uses any of these is somewhat
complicated and duplicated, so I agree that new code probably should
use some form of the internal MTD_OOB_AUTO.
Perhaps this can just be integrated into the new ioctl I'm writing as
a "mode" choice? See the thread:
http://lists.infradead.org/pipermail/linux-mtd/2011-August/037316.html
Brian
^ permalink raw reply
* Re: [PATCH] mtd-utils: fix corrupt cleanmarker with flash_erase -j command
From: Artem Bityutskiy @ 2011-08-16 15:06 UTC (permalink / raw)
To: b35362; +Cc: linuxppc-dev, dwmw2, linux-mtd, linuxppc-dev
In-Reply-To: <1312350638-25566-1-git-send-email-b35362@freescale.com>
On Wed, 2011-08-03 at 13:50 +0800, b35362@freescale.com wrote:
> From: Liu Shuo <b35362@freescale.com>
>
> Flash_erase -j should fill discrete freeoob areas with required bytes
> of JFFS2 cleanmarker in jffs2_check_nand_cleanmarker(). Not just fill
> the first freeoob area.
>
> Signed-off-by: Liu Shuo <b35362@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
...
> /*
> * Process user arguments
> @@ -197,15 +198,40 @@ int main(int argc, char *argv[])
> if (ioctl(fd, MEMGETOOBSEL, &oobinfo) != 0)
> return sys_errmsg("%s: unable to get NAND oobinfo", mtd_device);
>
> + cleanmarker.totlen = cpu_to_je32(8);
> /* Check for autoplacement */
> if (oobinfo.useecc == MTD_NANDECC_AUTOPLACE) {
> + struct nand_ecclayout_user ecclayout;
> /* Get the position of the free bytes */
> - if (!oobinfo.oobfree[0][1])
> + if (ioctl(fd, ECCGETLAYOUT, &ecclayout) != 0)
> + return sys_errmsg("%s: unable to get NAND ecclayout", mtd_device);
> +
Hmm, shouldn't we instead make MTD_OOB_AUTO be available for userspace
via an ioctl instead and make flash_eraseall use it instead?
--
Best Regards,
Artem Bityutskiy
^ permalink raw reply
* [PATCH] mtd/nand: Don't add disabled nand flash devices
From: Chunhe Lan @ 2011-08-16 9:27 UTC (permalink / raw)
To: linux-mtd; +Cc: kumar.gala, linuxppc-dev, scottwood, akpm, dwmw2, Chunhe Lan
Nand flash nodes with the property status="disabled" are not
usable and so avoid adding "disabled" nand flash devices with
the system.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
---
drivers/mtd/nand/fsl_elbc_nand.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 33d8aad..8212c12 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -1,6 +1,6 @@
/* Freescale Enhanced Local Bus Controller NAND driver
*
- * Copyright © 2006-2007, 2010 Freescale Semiconductor
+ * Copyright © 2006-2007, 2010-2011 Freescale Semiconductor
*
* Authors: Nick Spence <nick.spence@freescale.com>,
* Scott Wood <scottwood@freescale.com>
@@ -849,6 +849,9 @@ static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev)
struct device *dev;
struct device_node *node = pdev->dev.of_node;
+ if (!of_device_is_available(node))
+ return -ENODEV;
+
if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
return -ENODEV;
lbc = fsl_lbc_ctrl_dev->regs;
--
1.5.6.5
^ permalink raw reply related
* [PATCH] mtd/physmap_of: Don't add disabled flash devices
From: Chunhe Lan @ 2011-08-16 9:25 UTC (permalink / raw)
To: linux-mtd; +Cc: kumar.gala, linuxppc-dev, scottwood, akpm, dwmw2, Chunhe Lan
Flash(cfi-flash, jedec-flash, and so on) nodes with the
property status="disabled" are not usable and so avoid
adding "disabled" flash devices with the system.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
---
drivers/mtd/maps/physmap_of.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c
index d251d1d..812e6dc 100644
--- a/drivers/mtd/maps/physmap_of.c
+++ b/drivers/mtd/maps/physmap_of.c
@@ -219,6 +219,9 @@ static int __devinit of_flash_probe(struct platform_device *dev)
struct mtd_info **mtd_list = NULL;
resource_size_t res_size;
+ if (!of_device_is_available(dp))
+ return -ENODEV;
+
match = of_match_device(of_flash_match, &dev->dev);
if (!match)
return -EINVAL;
--
1.5.6.5
^ permalink raw reply related
* Re: [PATCH 8/9] arch/powerpc/sysdev/ehv_pic.c: add missing kfree
From: Tabi Timur-B04825 @ 2011-08-15 22:55 UTC (permalink / raw)
To: Julia Lawall, Benjamin Herrenschmidt, Kumar Gala
Cc: Paul Mackerras, kernel-janitors@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
In-Reply-To: <1312802283-9107-8-git-send-email-julia@diku.dk>
On Mon, Aug 8, 2011 at 7:18 AM, Julia Lawall <julia@diku.dk> wrote:
> diff --git a/arch/powerpc/sysdev/ehv_pic.c b/arch/powerpc/sysdev/ehv_pic.=
c
> index af1a5df..b6731e4 100644
> --- a/arch/powerpc/sysdev/ehv_pic.c
> +++ b/arch/powerpc/sysdev/ehv_pic.c
> @@ -280,6 +280,7 @@ void __init ehv_pic_init(void)
>
> =A0 =A0 =A0 =A0if (!ehv_pic->irqhost) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0of_node_put(np);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 kfree(ehv_pic);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return;
> =A0 =A0 =A0 =A0}
Although the fix is correct, I think there is another bug in this
function. 'np' is not released when the function finishes
successfully. I've looked at other functions that use
irq_alloc_host(), and most of them do the same thing: they don't call
of_node_put() on the device node pointer. The only exception I've
found is mpc5121_ads_cpld_pic_init().
Ben, Kumar: am I missing something? irq_alloc_host() calls of_node_get():
host->of_node =3D of_node_get(of_node);
so doesn't that mean that the caller of irq_alloc_host() should
release the device node pointer?
--=20
Timur Tabi
Linux kernel developer at Freescale=
^ permalink raw reply
* Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip
From: Artem Bityutskiy @ 2011-08-15 16:24 UTC (permalink / raw)
To: Scott Wood; +Cc: dwmw2, b35362, linux-mtd, linuxppc-dev
In-Reply-To: <4E494520.7050509@freescale.com>
On Mon, 2011-08-15 at 11:11 -0500, Scott Wood wrote:
> On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
> > On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
> >> + /*
> >> + * Hack for supporting the flash chip whose writesize is
> >> + * larger than 2K bytes.
> >> + */
> >> + if (mtd->writesize > 2048) {
> >> + elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
> >> + elbc_fcm_ctrl->subpage_mask =
> >> + (1 << elbc_fcm_ctrl->subpage_shift) - 1;
> >> + /*
> >> + * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
> >> + * and chip->pagemask.
> >> + */
> >> + mtd->writesize = 2048;
> >> + mtd->oobsize = 64;
> >> + chip->page_shift = ffs(mtd->writesize) - 1;
> >> + chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
> >> + }
> >
> > So basically if the flash has 4KiB NAND pages, you are considering it as
> > a flash with 2KiB NAND pages. But surely this will work only if the
> > underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
> > and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
> > writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?
>
> Right. The set of chips that work with this controller is still larger
> with this than without this.
>
> It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
> MLC with this controller anyway as it only does 1-bit ECC.
>
> > Isn't it an ugly hack?
>
> Less ugly than some other approaches that were considered. :-)
>
> But yes, it's a hack (even says so in the comment). The other option is
> "it doesn't work".
Could there be at least a fat comment that NANDs with 4KiB pages have to
be at least NOP4? And probably NANDs with 8KiB pages and larger should
simply be rejected?
--
Best Regards,
Artem Bityutskiy
^ permalink raw reply
* Re: [PATCH v12 3/6] flexcan: Fix up fsl-flexcan device tree binding.
From: Marc Kleine-Budde @ 2011-08-15 16:13 UTC (permalink / raw)
To: Robin Holt
Cc: socketcan-core, netdev, devicetree-discuss, U Bhaskar-B22300,
Scott Wood, PPC list
In-Reply-To: <20110815150357.GM4926@sgi.com>
[-- Attachment #1: Type: text/plain, Size: 1648 bytes --]
On 08/15/2011 05:03 PM, Robin Holt wrote:
> Earlier, you had asked for a more specific name for the compatible
> property of the Freescale flexcan device. I still have not gotten a
> more specific answer. Hopefully Marc can give you more details about
> the flexcan implementations.
There are at least 2 versions of the flexcan ip core in the wild. Due to
lack of version numbers or other names I call them old and new here :).
The newer one supports rx fifo mode, whereas the older one doesn't. The
mainline flexcan driver just supports the new core [1]. The older core
is found on coldfire processors. I don't know if there are coldfire cpus
with the new flexcan core, too. The driver can be adopted to the old
core if needed.
The first cpus with the new core I got in touch with was the mx35
(arm11) and mx25 (arm9) both at the same time. Ask fsl which one was
released first. After this there was mx28 (arm9) and there should be an
mx53 (coretexa8) with flexcan too.
> Other than an agreement on the compatible property, I believe we have
> agreement on all the other code changes in these patches. Is this change
> acceptable as is and if we get a better resolution on the fsl,flexcan
> name later, we can update the documentation and driver then?
cheers, Marc
[1] http://lxr.linux.no/linux+v3.0.1/drivers/net/can/flexcan.c#L871
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 262 bytes --]
^ permalink raw reply
* Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip
From: Scott Wood @ 2011-08-15 16:11 UTC (permalink / raw)
To: dedekind1; +Cc: dwmw2, b35362, linux-mtd, linuxppc-dev
In-Reply-To: <1313423954.8691.17.camel@sauron>
On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
> On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
>> + /*
>> + * Hack for supporting the flash chip whose writesize is
>> + * larger than 2K bytes.
>> + */
>> + if (mtd->writesize > 2048) {
>> + elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
>> + elbc_fcm_ctrl->subpage_mask =
>> + (1 << elbc_fcm_ctrl->subpage_shift) - 1;
>> + /*
>> + * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
>> + * and chip->pagemask.
>> + */
>> + mtd->writesize = 2048;
>> + mtd->oobsize = 64;
>> + chip->page_shift = ffs(mtd->writesize) - 1;
>> + chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
>> + }
>
> So basically if the flash has 4KiB NAND pages, you are considering it as
> a flash with 2KiB NAND pages. But surely this will work only if the
> underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
> and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
> writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?
Right. The set of chips that work with this controller is still larger
with this than without this.
It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
MLC with this controller anyway as it only does 1-bit ECC.
> Isn't it an ugly hack?
Less ugly than some other approaches that were considered. :-)
But yes, it's a hack (even says so in the comment). The other option is
"it doesn't work".
-Scott
^ permalink raw reply
* Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip
From: Artem Bityutskiy @ 2011-08-15 15:59 UTC (permalink / raw)
To: b35362; +Cc: scottwood, linuxppc-dev, dwmw2, linux-mtd
In-Reply-To: <1310446122-18050-1-git-send-email-b35362@freescale.com>
On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
> + /*
> + * Hack for supporting the flash chip whose writesize is
> + * larger than 2K bytes.
> + */
> + if (mtd->writesize > 2048) {
> + elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
> + elbc_fcm_ctrl->subpage_mask =
> + (1 << elbc_fcm_ctrl->subpage_shift) - 1;
> + /*
> + * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
> + * and chip->pagemask.
> + */
> + mtd->writesize = 2048;
> + mtd->oobsize = 64;
> + chip->page_shift = ffs(mtd->writesize) - 1;
> + chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
> + }
So basically if the flash has 4KiB NAND pages, you are considering it as
a flash with 2KiB NAND pages. But surely this will work only if the
underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes? Isn't it
an ugly hack?
--
Best Regards,
Artem Bityutskiy
^ permalink raw reply
* Re: [PATCH v12 3/6] flexcan: Fix up fsl-flexcan device tree binding.
From: Robin Holt @ 2011-08-15 15:25 UTC (permalink / raw)
To: Grant Likely
Cc: netdev, devicetree-discuss, U Bhaskar-B22300, socketcan-core,
Robin Holt, Scott Wood, PPC list
In-Reply-To: <CACxGe6vafc6mYyKCAO+HqkRPsZ3GmeVJnK+z8=BX_wQQMG4LmQ@mail.gmail.com>
On Mon, Aug 15, 2011 at 09:13:50AM -0600, Grant Likely wrote:
> On Mon, Aug 15, 2011 at 9:03 AM, Robin Holt <holt@sgi.com> wrote:
> > Grant,
> >
> > Earlier, you had asked for a more specific name for the compatible
> > property of the Freescale flexcan device. I still have not gotten a
> > more specific answer. Hopefully Marc can give you more details about
> > the flexcan implementations.
>
> If there is no ip core version, then just stick with the
> fsl,<soc>-flexcan name and drop "fsl,flexcan". Marketing may say
> flexcan is flexcan, but hardware engineers like to change things.
> Trying to be too generic in compatible values will just lead to
> problems in the future.
Thanks,
Robin
^ permalink raw reply
* Re: [PATCH v12 3/6] flexcan: Fix up fsl-flexcan device tree binding.
From: Grant Likely @ 2011-08-15 15:13 UTC (permalink / raw)
To: Robin Holt
Cc: netdev, devicetree-discuss, U Bhaskar-B22300, socketcan-core,
Scott Wood, PPC list
In-Reply-To: <20110815150357.GM4926@sgi.com>
On Mon, Aug 15, 2011 at 9:03 AM, Robin Holt <holt@sgi.com> wrote:
> Grant,
>
> Earlier, you had asked for a more specific name for the compatible
> property of the Freescale flexcan device. =A0I still have not gotten a
> more specific answer. =A0Hopefully Marc can give you more details about
> the flexcan implementations.
If there is no ip core version, then just stick with the
fsl,<soc>-flexcan name and drop "fsl,flexcan". Marketing may say
flexcan is flexcan, but hardware engineers like to change things.
Trying to be too generic in compatible values will just lead to
problems in the future.
g.
^ permalink raw reply
* Re: [PATCH v12 3/6] flexcan: Fix up fsl-flexcan device tree binding.
From: Robin Holt @ 2011-08-15 15:03 UTC (permalink / raw)
To: Grant Likely, Marc Kleine-Budde
Cc: netdev, devicetree-discuss, U Bhaskar-B22300, socketcan-core,
Robin Holt, Scott Wood, PPC list
In-Reply-To: <1313138752-24006-4-git-send-email-holt@sgi.com>
Grant,
Earlier, you had asked for a more specific name for the compatible
property of the Freescale flexcan device. I still have not gotten a
more specific answer. Hopefully Marc can give you more details about
the flexcan implementations.
Other than an agreement on the compatible property, I believe we have
agreement on all the other code changes in these patches. Is this change
acceptable as is and if we get a better resolution on the fsl,flexcan
name later, we can update the documentation and driver then?
Thanks,
Robin
On Fri, Aug 12, 2011 at 03:45:49AM -0500, Robin Holt wrote:
> This patch cleans up the documentation of the device-tree binding for
> the Flexcan devices on Freescale's PowerPC and ARM cores. Extra
> properties are not used by the driver so we are removing them.
>
> Signed-off-by: Robin Holt <holt@sgi.com>
> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>,
> To: Wolfgang Grandegger <wg@grandegger.com>,
> To: U Bhaskar-B22300 <B22300@freescale.com>
> To: Scott Wood <scottwood@freescale.com>
> To: Grant Likely <grant.likely@secretlab.ca>
> To: Kumar Gala <galak@kernel.crashing.org>
> Cc: socketcan-core@lists.berlios.de,
> Cc: netdev@vger.kernel.org,
> Cc: PPC list <linuxppc-dev@lists.ozlabs.org>
> Cc: devicetree-discuss@lists.ozlabs.org
> ---
> .../devicetree/bindings/net/can/fsl-flexcan.txt | 61 ++++----------------
> arch/powerpc/boot/dts/p1010rdb.dts | 10 +---
> arch/powerpc/boot/dts/p1010si.dtsi | 10 +--
> 3 files changed, 17 insertions(+), 64 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
> index 1a729f0..80a78a9 100644
> --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
> +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
> @@ -1,61 +1,22 @@
> -CAN Device Tree Bindings
> -------------------------
> -2011 Freescale Semiconductor, Inc.
> +Flexcan CAN contoller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
>
> -fsl,flexcan-v1.0 nodes
> ------------------------
> -In addition to the required compatible-, reg- and interrupt-properties, you can
> -also specify which clock source shall be used for the controller.
> +Required properties:
>
> -CPI Clock- Can Protocol Interface Clock
> - This CLK_SRC bit of CTRL(control register) selects the clock source to
> - the CAN Protocol Interface(CPI) to be either the peripheral clock
> - (driven by the PLL) or the crystal oscillator clock. The selected clock
> - is the one fed to the prescaler to generate the Serial Clock (Sclock).
> - The PRESDIV field of CTRL(control register) controls a prescaler that
> - generates the Serial Clock (Sclock), whose period defines the
> - time quantum used to compose the CAN waveform.
> +- compatible : Should be "fsl,<processor>-flexcan" and "fsl,flexcan"
>
> -Can Engine Clock Source
> - There are two sources for CAN clock
> - - Platform Clock It represents the bus clock
> - - Oscillator Clock
> + An implementation should also claim any of the following compatibles
> + that it is fully backwards compatible with:
>
> - Peripheral Clock (PLL)
> - --------------
> - |
> - --------- -------------
> - | |CPI Clock | Prescaler | Sclock
> - | |---------------->| (1.. 256) |------------>
> - --------- -------------
> - | |
> - -------------- ---------------------CLK_SRC
> - Oscillator Clock
> + - fsl,p1010-flexcan
>
> -- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects
> - the peripheral clock. PLL clock is fed to the
> - prescaler to generate the Serial Clock (Sclock).
> - Valid values are "oscillator" and "platform"
> - "oscillator": CAN engine clock source is oscillator clock.
> - "platform" The CAN engine clock source is the bus clock
> - (platform clock).
> +- reg : Offset and length of the register set for this device
> +- interrupts : Interrupt tuple for this device
>
> -- fsl,flexcan-clock-divider : for the reference and system clock, an additional
> - clock divider can be specified.
> -- clock-frequency: frequency required to calculate the bitrate for FlexCAN.
> +Example:
>
> -Note:
> - - v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC.
> - - P1010 does not have oscillator as the Clock Source.So the default
> - Clock Source is platform clock.
> -Examples:
> -
> - can0@1c000 {
> - compatible = "fsl,flexcan-v1.0";
> + can@1c000 {
> + compatible = "fsl,p1010-flexcan", "fsl,flexcan";
> reg = <0x1c000 0x1000>;
> interrupts = <48 0x2>;
> interrupt-parent = <&mpic>;
> - fsl,flexcan-clock-source = "platform";
> - fsl,flexcan-clock-divider = <2>;
> - clock-frequency = <fixed by u-boot>;
> };
> diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
> index 6b33b73..d6c669c 100644
> --- a/arch/powerpc/boot/dts/p1010rdb.dts
> +++ b/arch/powerpc/boot/dts/p1010rdb.dts
> @@ -23,6 +23,8 @@
> ethernet2 = &enet2;
> pci0 = &pci0;
> pci1 = &pci1;
> + can0 = &can0;
> + can1 = &can1;
> };
>
> memory {
> @@ -169,14 +171,6 @@
> };
> };
>
> - can0@1c000 {
> - fsl,flexcan-clock-source = "platform";
> - };
> -
> - can1@1d000 {
> - fsl,flexcan-clock-source = "platform";
> - };
> -
> usb@22000 {
> phy_type = "utmi";
> };
> diff --git a/arch/powerpc/boot/dts/p1010si.dtsi b/arch/powerpc/boot/dts/p1010si.dtsi
> index 7f51104..f00076b 100644
> --- a/arch/powerpc/boot/dts/p1010si.dtsi
> +++ b/arch/powerpc/boot/dts/p1010si.dtsi
> @@ -140,20 +140,18 @@
> interrupt-parent = <&mpic>;
> };
>
> - can0@1c000 {
> - compatible = "fsl,flexcan-v1.0";
> + can0: can@1c000 {
> + compatible = "fsl,p1010-flexcan", "fsl,flexcan";
> reg = <0x1c000 0x1000>;
> interrupts = <48 0x2>;
> interrupt-parent = <&mpic>;
> - fsl,flexcan-clock-divider = <2>;
> };
>
> - can1@1d000 {
> - compatible = "fsl,flexcan-v1.0";
> + can1: can@1d000 {
> + compatible = "fsl,p1010-flexcan", "fsl,flexcan";
> reg = <0x1d000 0x1000>;
> interrupts = <61 0x2>;
> interrupt-parent = <&mpic>;
> - fsl,flexcan-clock-divider = <2>;
> };
>
> L2: l2-cache-controller@20000 {
> --
> 1.7.2.1
^ permalink raw reply
* Re: [PATCH v3] mtd: eLBC NAND: update ecc_stats.corrected when lteccr available
From: Artem Bityutskiy @ 2011-08-15 14:53 UTC (permalink / raw)
To: MichaelHench; +Cc: scottwood, linuxppc-dev, linux-mtd, mlcreech, mhench
In-Reply-To: <CAHyXW61rWcoE0Wcd9K7BsP3+VKzmQo=RPMM9+1DTw+QdF9MVew@mail.gmail.com>
On Tue, 2011-07-26 at 15:07 -0500, Michael Hench wrote:
> update ecc_stats.corrected if LTECCR register is available.
>
> v2: kernel standard C formatting
>
> v3: kernel standard C formatting again, changed a comment to get under 80 chars
>
> Signed-off-by: Michael Hench <MichaelHench@gmail.com>
Pushed to l2-mtd-2.6.git, thanks.
--
Best Regards,
Artem Bityutskiy
^ permalink raw reply
* [PATCH] mcu_mpc8349emitx.c: add shutdown request support
From: Fabio Baltieri @ 2011-08-15 14:19 UTC (permalink / raw)
To: Anton Vorontsov, Kumar Gala; +Cc: Fabio Baltieri, linuxppc-dev, linux-kernel
This patch add support for calling ctrl_alt_del() when the power button is
pressed for more than about 2 seconds on some freescale MPC83xx
evaluation boards and reference design.
The code uses a kthread to poll the CTRL_BTN bit each second.
Also change Kconfig entry of the driver to bool, as device's gpio
registration is broken when loading as module.
Tested on an MPC8315E RDB board.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
---
arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c | 58 +++++++++++++++++++++++-
arch/powerpc/platforms/Kconfig | 2 +-
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
index 70798ac..ef6537b 100644
--- a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
+++ b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
@@ -21,6 +21,8 @@
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>
+#include <linux/kthread.h>
+#include <linux/reboot.h>
#include <asm/prom.h>
#include <asm/machdep.h>
@@ -30,6 +32,7 @@
*/
#define MCU_REG_CTRL 0x20
#define MCU_CTRL_POFF 0x40
+#define MCU_CTRL_BTN 0x80
#define MCU_NUM_GPIO 2
@@ -42,13 +45,55 @@ struct mcu {
static struct mcu *glob_mcu;
+struct task_struct *shutdown_thread;
+static int shutdown_thread_fn(void *data)
+{
+ int ret;
+ struct mcu *mcu = glob_mcu;
+
+ while (!kthread_should_stop()) {
+ ret = i2c_smbus_read_byte_data(mcu->client, MCU_REG_CTRL);
+ if (ret < 0)
+ pr_err("MCU status reg read failed.\n");
+ mcu->reg_ctrl = ret;
+
+
+ if (mcu->reg_ctrl & MCU_CTRL_BTN) {
+ i2c_smbus_write_byte_data(mcu->client, MCU_REG_CTRL,
+ mcu->reg_ctrl & ~MCU_CTRL_BTN);
+
+ ctrl_alt_del();
+ }
+
+ set_current_state(TASK_INTERRUPTIBLE);
+ schedule_timeout(HZ);
+ }
+
+ return 0;
+}
+
+static ssize_t show_status(struct device *d,
+ struct device_attribute *attr, char *buf)
+{
+ int ret;
+ struct mcu *mcu = glob_mcu;
+
+ ret = i2c_smbus_read_byte_data(mcu->client, MCU_REG_CTRL);
+ if (ret < 0)
+ return -ENODEV;
+ mcu->reg_ctrl = ret;
+
+ return sprintf(buf, "%02x\n", ret);
+}
+static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
+
static void mcu_power_off(void)
{
struct mcu *mcu = glob_mcu;
pr_info("Sending power-off request to the MCU...\n");
mutex_lock(&mcu->lock);
- i2c_smbus_write_byte_data(glob_mcu->client, MCU_REG_CTRL,
+ i2c_smbus_write_byte_data(mcu->client, MCU_REG_CTRL,
mcu->reg_ctrl | MCU_CTRL_POFF);
mutex_unlock(&mcu->lock);
}
@@ -130,6 +175,13 @@ static int __devinit mcu_probe(struct i2c_client *client,
dev_info(&client->dev, "will provide power-off service\n");
}
+ if (device_create_file(&client->dev, &dev_attr_status))
+ dev_err(&client->dev,
+ "couldn't create device file for status\n");
+
+ shutdown_thread = kthread_run(shutdown_thread_fn, NULL,
+ "mcu-i2c-shdn");
+
return 0;
err:
kfree(mcu);
@@ -141,6 +193,10 @@ static int __devexit mcu_remove(struct i2c_client *client)
struct mcu *mcu = i2c_get_clientdata(client);
int ret;
+ kthread_stop(shutdown_thread);
+
+ device_remove_file(&client->dev, &dev_attr_status);
+
if (glob_mcu == mcu) {
ppc_md.power_off = NULL;
glob_mcu = NULL;
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index b9ba861..7bfd30e 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -355,7 +355,7 @@ config SIMPLE_GPIO
on-board peripherals.
config MCU_MPC8349EMITX
- tristate "MPC8349E-mITX MCU driver"
+ bool "MPC8349E-mITX MCU driver"
depends on I2C && PPC_83xx
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
--
1.7.5.1
^ permalink raw reply related
* [PATCH] powerpc/p1023rds: Add nand flash node support in the dts
From: Chunhe Lan @ 2011-08-15 8:43 UTC (permalink / raw)
To: linuxppc-dev; +Cc: scottwood, kumar.gala, Chunhe Lan
In the p1023rds, accessing exclusively nor flash or nand flash
device by BR0/OR0. When booting from nor flash, nand node is
disabled and nor node is enabled in the default dts. So, when
booting from nand flash, u-boot should do some operations:
o The "status" property of nand node should be enabled.
o The "status" property of nor node should be disabled.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
---
arch/powerpc/boot/dts/p1023rds.dts | 46 +++++++++++++++++++++++++++++++++--
1 files changed, 43 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
index d9b7767..aa63b81 100644
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ b/arch/powerpc/boot/dts/p1023rds.dts
@@ -58,6 +58,9 @@
rtic_b = &rtic_b;
rtic_c = &rtic_c;
rtic_d = &rtic_d;
+
+ nor_flash = &nor_flash;
+ nand_flash = &nand_flash;
};
cpus {
@@ -378,11 +381,12 @@
interrupts = <19 2>;
interrupt-parent = <&mpic>;
- /* NOR Flash, BCSR */
+ /* NOR Flash, BCSR, NAND Flash */
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
- 0x1 0x0 0x0 0xe0000000 0x00008000>;
+ 0x1 0x0 0x0 0xe0000000 0x00008000
+ 0x2 0x0 0x0 0xffa00000 0x00040000>;
- nor@0,0 {
+ nor_flash: nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
@@ -425,6 +429,42 @@
reg = <0x20 0x20>;
};
};
+
+ nand_flash: nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p1023-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x2 0x0 0x00040000>;
+ status = "disabled";
+
+ u-boot-nand@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = <0x0 0x00100000>;
+ read-only;
+ };
+
+ dtb-nand@100000 {
+ /* 1MB for DTB Image */
+ reg = <0x00100000 0x00100000>;
+ };
+
+ kernel-nand@200000 {
+ /* 4MB for Linux Kernel Image */
+ reg = <0x00200000 0x00400000>;
+ };
+
+ ramdisk-nand@600000 {
+ /* 57MB for Compressed Root file System Image */
+ reg = <0x00600000 0x03900000>;
+ };
+
+ empty-nand@3f00000 {
+ /* 1MB for reserved space */
+ reg = <0x03f00000 0x00100000>;
+ };
+ };
};
pci0: pcie@ff60a000 {
--
1.5.6.5
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