* Re: [PATCH 01/16 v3] pmac_zilog: fix unexpected irq
From: Benjamin Herrenschmidt @ 2011-12-08 3:17 UTC (permalink / raw)
To: Finn Thain; +Cc: linuxppc-dev, linux-m68k, Geert Uytterhoeven, linux-serial
In-Reply-To: <alpine.LNX.2.00.1112071427280.28552@nippy.intranet>
On Wed, 2011-12-07 at 14:49 +1100, Finn Thain wrote:
> On most 68k Macs the SCC IRQ is an autovector interrupt and cannot be
> masked. This can be a problem when pmac_zilog starts up.
Thanks. I'll test it on a powermac or two and will merge it via the
powerpc -next tree if it works out allright.
Cheers,
Ben.
> For example, the serial debugging code in arch/m68k/kernel/head.S may be
> used beforehand. It disables the SCC interrupts at the chip but doesn't
> ack them. Then when a pmac_zilog port is used, the machine locks up with
> "unexpected interrupt".
>
> This can happen in pmz_shutdown() since the irq is freed before the
> channel interrupts are disabled.
>
> Fix this by clearing interrupt enable bits before the handler is
> uninstalled. Also move the interrupt control bit flipping into a separate
> pmz_interrupt_control() routine. Replace all instances of these operations
> with calls to this routine. Omit the zssync() calls that seem to serve no
> purpose.
>
> Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
> Acked-by: Alan Cox <alan@linux.intel.com>
>
> ---
>
> Re-implemented as v2 using a simpler approach that avoids messing with the
> Master Interrupt Enable bit. As well as the ifdef problem, it turns out
> that v1 was not sufficient to entirely fix the problem.
>
> v3 avoids needless changes to the logic and locking in the suspend and
> shutdown code and tries to keep register writes closer to their original
> sequence.
>
> This patch has been tested on a PowerBook 520 but no PowerMacs yet.
>
>
> Index: linux-git/drivers/tty/serial/pmac_zilog.c
> ===================================================================
> --- linux-git.orig/drivers/tty/serial/pmac_zilog.c 2011-12-07 12:36:32.000000000 +1100
> +++ linux-git/drivers/tty/serial/pmac_zilog.c 2011-12-07 14:29:21.000000000 +1100
> @@ -216,6 +216,18 @@ static void pmz_maybe_update_regs(struct
> }
> }
>
> +static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
> +{
> + if (enable) {
> + uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
> + if (!ZS_IS_EXTCLK(uap))
> + uap->curregs[1] |= EXT_INT_ENAB;
> + } else {
> + uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
> + }
> + write_zsreg(uap, R1, uap->curregs[1]);
> +}
> +
> static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap)
> {
> struct tty_struct *tty = NULL;
> @@ -339,9 +351,7 @@ static struct tty_struct *pmz_receive_ch
>
> return tty;
> flood:
> - uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
> - write_zsreg(uap, R1, uap->curregs[R1]);
> - zssync(uap);
> + pmz_interrupt_control(uap, 0);
> pmz_error("pmz: rx irq flood !\n");
> return tty;
> }
> @@ -990,12 +1000,9 @@ static int pmz_startup(struct uart_port
> if (ZS_IS_IRDA(uap))
> pmz_irda_reset(uap);
>
> - /* Enable interrupts emission from the chip */
> + /* Enable interrupt requests for the channel */
> spin_lock_irqsave(&port->lock, flags);
> - uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
> - if (!ZS_IS_EXTCLK(uap))
> - uap->curregs[R1] |= EXT_INT_ENAB;
> - write_zsreg(uap, R1, uap->curregs[R1]);
> + pmz_interrupt_control(uap, 1);
> spin_unlock_irqrestore(&port->lock, flags);
>
> pmz_debug("pmz: startup() done.\n");
> @@ -1015,6 +1022,25 @@ static void pmz_shutdown(struct uart_por
>
> mutex_lock(&pmz_irq_mutex);
>
> + spin_lock_irqsave(&port->lock, flags);
> +
> + if (!ZS_IS_ASLEEP(uap)) {
> + /* Disable interrupt requests for the channel */
> + pmz_interrupt_control(uap, 0);
> +
> + if (!ZS_IS_CONS(uap)) {
> + /* Disable receiver and transmitter */
> + uap->curregs[R3] &= ~RxENABLE;
> + uap->curregs[R5] &= ~TxENABLE;
> +
> + /* Disable break assertion */
> + uap->curregs[R5] &= ~SND_BRK;
> + pmz_maybe_update_regs(uap);
> + }
> + }
> +
> + spin_unlock_irqrestore(&port->lock, flags);
> +
> /* Release interrupt handler */
> free_irq(uap->port.irq, uap);
>
> @@ -1025,29 +1051,8 @@ static void pmz_shutdown(struct uart_por
> if (!ZS_IS_OPEN(uap->mate))
> pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
>
> - /* Disable interrupts */
> - if (!ZS_IS_ASLEEP(uap)) {
> - uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
> - write_zsreg(uap, R1, uap->curregs[R1]);
> - zssync(uap);
> - }
> -
> - if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
> - spin_unlock_irqrestore(&port->lock, flags);
> - mutex_unlock(&pmz_irq_mutex);
> - return;
> - }
> -
> - /* Disable receiver and transmitter. */
> - uap->curregs[R3] &= ~RxENABLE;
> - uap->curregs[R5] &= ~TxENABLE;
> -
> - /* Disable all interrupts and BRK assertion. */
> - uap->curregs[R5] &= ~SND_BRK;
> - pmz_maybe_update_regs(uap);
> -
> - /* Shut the chip down */
> - pmz_set_scc_power(uap, 0);
> + if (!ZS_IS_ASLEEP(uap) && !ZS_IS_CONS(uap))
> + pmz_set_scc_power(uap, 0); /* Shut the chip down */
>
> spin_unlock_irqrestore(&port->lock, flags);
>
> @@ -1352,19 +1357,15 @@ static void pmz_set_termios(struct uart_
> spin_lock_irqsave(&port->lock, flags);
>
> /* Disable IRQs on the port */
> - uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
> - write_zsreg(uap, R1, uap->curregs[R1]);
> + pmz_interrupt_control(uap, 0);
>
> /* Setup new port configuration */
> __pmz_set_termios(port, termios, old);
>
> /* Re-enable IRQs on the port */
> - if (ZS_IS_OPEN(uap)) {
> - uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
> - if (!ZS_IS_EXTCLK(uap))
> - uap->curregs[R1] |= EXT_INT_ENAB;
> - write_zsreg(uap, R1, uap->curregs[R1]);
> - }
> + if (ZS_IS_OPEN(uap))
> + pmz_interrupt_control(uap, 1);
> +
> spin_unlock_irqrestore(&port->lock, flags);
> }
>
> @@ -1671,14 +1672,17 @@ static int pmz_suspend(struct macio_dev
> spin_lock_irqsave(&uap->port.lock, flags);
>
> if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
> - /* Disable receiver and transmitter. */
> + /* Disable interrupt requests for the channel */
> + pmz_interrupt_control(uap, 0);
> +
> + /* Disable receiver and transmitter */
> uap->curregs[R3] &= ~RxENABLE;
> uap->curregs[R5] &= ~TxENABLE;
>
> - /* Disable all interrupts and BRK assertion. */
> - uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
> + /* Disable break assertion */
> uap->curregs[R5] &= ~SND_BRK;
> pmz_load_zsregs(uap, uap->curregs);
> +
> uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
> mb();
> }
> @@ -1738,14 +1742,6 @@ static int pmz_resume(struct macio_dev *
> /* Take care of config that may have changed while asleep */
> __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
>
> - if (ZS_IS_OPEN(uap)) {
> - /* Enable interrupts */
> - uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
> - if (!ZS_IS_EXTCLK(uap))
> - uap->curregs[R1] |= EXT_INT_ENAB;
> - write_zsreg(uap, R1, uap->curregs[R1]);
> - }
> -
> spin_unlock_irqrestore(&uap->port.lock, flags);
>
> if (ZS_IS_CONS(uap))
> @@ -1757,6 +1753,12 @@ static int pmz_resume(struct macio_dev *
> enable_irq(uap->port.irq);
> }
>
> + if (ZS_IS_OPEN(uap)) {
> + spin_lock_irqsave(&uap->port.lock, flags);
> + pmz_interrupt_control(uap, 1);
> + spin_unlock_irqrestore(&uap->port.lock, flags);
> + }
> +
> bail:
> mutex_unlock(&state->port.mutex);
> mutex_unlock(&pmz_irq_mutex);
^ permalink raw reply
* RE: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller
From: Liu Shengzhou-B36685 @ 2011-12-08 3:06 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org
In-Reply-To: <4EDF9F6A.9000407@freescale.com>
DQoNCkJlc3QgUmVnYXJkcywNClNoZW5nemhvdSBMaXUNCg0KDQo+IC0tLS0tT3JpZ2luYWwgTWVz
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ZWNlbWJlciAwOCwgMjAxMSAxOjE2IEFNDQo+IFRvOiBMaXUgU2hlbmd6aG91LUIzNjY4NQ0KPiBD
YzogV29vZCBTY290dC1CMDc0MjE7IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOyBsaW51
eC0NCj4gbXRkQGxpc3RzLmluZnJhZGVhZC5vcmc7IGR3bXcyQGluZnJhZGVhZC5vcmc7IEdhbGEg
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MjAxMSAwOToxNiBQTSwgTGl1IFNoZW5nemhvdS1CMzY2ODUgd3JvdGU6DQo+ID4+PiArCQkJb3V0
X2JlMzIoJmxiYy0+ZmJjciwgOCk7DQo+ID4+PiArCQkJZWxiY19mY21fY3RybC0+cmVhZF9ieXRl
cyA9IDg7DQo+ID4+PiArCQl9IGVsc2Ugew0KPiA+Pj4gKwkJCW91dF9iZTMyKCZsYmMtPmZiY3Is
IDI1Nik7DQo+ID4+PiArCQkJZWxiY19mY21fY3RybC0+cmVhZF9ieXRlcyA9IDI1NjsNCj4gPj4+
ICsJCX0NCj4gPj4NCj4gPj4gQW55IGhhcm0gaW4gYWx3YXlzIHVzaW5nIDI1Nj8NCj4gPj4NCj4g
Pj4gLVNjb3R0DQo+ID4gW1NoZW5nemhvdV0gRm9yIE5BTkRfQ01EX1JFQURJRCBjb21tYW5kLCB0
aGUgdG90YWwgYnl0ZXMgb2YgZW50aXJlIElEDQo+IHN0cmluZyBhcmUgOCwgdGhlcmUgYXJlIG5v
dCAyNTYgYnl0ZXMgc28gbWFueSwgaXQncyB1bm5lY2Vzc2FyeSBhbmQgbG9va3MNCj4gbm90IHNv
IHdlbGwgbG9naWNhbGx5IHRvIGFsd2F5cyB1c2luZyAyNTYsIHRob3VnaCBpdCB3b3Jrcy4NCj4g
DQo+IEl0J3Mgbm90IHBlcmZvcm1hbmNlIGNyaXRpY2FsLCBhbmQgYWx3YXlzIHVzaW5nIDI1NiBr
ZWVwcyB0aGluZ3Mgc2ltcGxlciwNCj4gYW5kIG1vcmUgcm9idXN0IGlmIHRoZSBsZW5ndGggb2Yg
dGhlIElEIHN0cmluZyBncm93cyBpbiB0aGUgZnV0dXJlICh3ZQ0KPiB1c2VkIHRvIGFzc3VtZSBp
dCB3YXMgNSBieXRlcy4uLikuDQo+IA0KPiAtU2NvdHQNCltTaGVuZ3pob3VdIE9LLg0K
^ permalink raw reply
* Re: [PATCH 2/2] powerpc/85xx: create 32-bit DTS for the P1022DS
From: Tabi Timur-B04825 @ 2011-12-08 1:05 UTC (permalink / raw)
To: Wood Scott-B07421; +Cc: linuxppc-dev@ozlabs.org, Gala Kumar-B11780
In-Reply-To: <4EDFFFEA.5030603@freescale.com>
Scott Wood wrote:
>> + interrupts =3D<8 8 0 0>;
>> > + };
> It's not new to this patch, but... what does "8" mean in the second cell
> of an mpic interrupt specifier?
I have no idea.
> And why does the indirect pixis node
> not have the interrupt?
Hmmm... I suppose I could add it, but I don't know what good it would do.=20
The code that's looking for the interrupt is probing on "fsl,p1022ds-fpga=
".
--=20
Timur Tabi
Linux kernel developer at Freescale=
^ permalink raw reply
* Re: [PATCH 2/2] powerpc/85xx: create 32-bit DTS for the P1022DS
From: Scott Wood @ 2011-12-08 0:08 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev, kumar.gala
In-Reply-To: <1323302665-26461-2-git-send-email-timur@freescale.com>
On 12/07/2011 06:04 PM, Timur Tabi wrote:
> + /*
> + * This node is used to access the pixis via "indirect" mode,
> + * which is done by writing the pixis register index to chip
> + * select 0 and the value to/from chip select 1. Indirect
> + * mode is the only way to access the pixis when DIU video
> + * is enabled. Note that this assumes that the first column
> + * of the 'ranges' property above is the chip select number.
> + */
> + board-control@0,0 {
> + compatible = "fsl,p1022ds-indirect-pixis";
> + reg = <0x0 0x0 1 /* CS0 */
> + 0x1 0x0 1>; /* CS1 */
> + };
[snip]
> + board-control@3,0 {
> + compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
> + reg = <3 0 0x30>;
> + interrupt-parent = <&mpic>;
> + /*
> + * IRQ8 is generated if the "EVENT" switch is pressed
> + * and PX_CTL[EVESEL] is set to 00.
> + */
> + interrupts = <8 8 0 0>;
> + };
It's not new to this patch, but... what does "8" mean in the second cell
of an mpic interrupt specifier? And why does the indirect pixis node
not have the interrupt?
-Scott
^ permalink raw reply
* [PATCH 2/2] powerpc/85xx: create 32-bit DTS for the P1022DS
From: Timur Tabi @ 2011-12-08 0:04 UTC (permalink / raw)
To: kumar.gala, linuxppc-dev
In-Reply-To: <1323302665-26461-1-git-send-email-timur@freescale.com>
Create a 32-bit address space version of p1022ds.dts. To avoid confusion,
p1022ds.dts is renamed to p1022ds_36b.dts. We also create p1022ds.dtsi
to store some common nodes.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
arch/powerpc/boot/dts/p1022ds.dts | 270 ---------------------------------
arch/powerpc/boot/dts/p1022ds.dtsi | 112 ++++++++++++++
arch/powerpc/boot/dts/p1022ds_32b.dts | 218 ++++++++++++++++++++++++++
arch/powerpc/boot/dts/p1022ds_36b.dts | 218 ++++++++++++++++++++++++++
4 files changed, 548 insertions(+), 270 deletions(-)
delete mode 100644 arch/powerpc/boot/dts/p1022ds.dts
create mode 100644 arch/powerpc/boot/dts/p1022ds.dtsi
create mode 100644 arch/powerpc/boot/dts/p1022ds_32b.dts
create mode 100644 arch/powerpc/boot/dts/p1022ds_36b.dts
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
deleted file mode 100644
index a54dd13..0000000
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * P1022 DS 36Bit Physical Address Map Device Tree Source
- *
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/include/ "fsl/p1022si-pre.dtsi"
-/ {
- model = "fsl,P1022DS";
- compatible = "fsl,P1022DS";
-
- memory {
- device_type = "memory";
- };
-
- lbc: localbus@fffe05000 {
- reg = <0xf 0xffe05000 0 0x1000>;
- ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
- 0x1 0x0 0xf 0xe0000000 0x08000000
- 0x2 0x0 0xf 0xff800000 0x00040000
- 0x3 0x0 0xf 0xffdf0000 0x00008000>;
-
- /*
- * This node is used to access the pixis via "indirect" mode,
- * which is done by writing the pixis register index to chip
- * select 0 and the value to/from chip select 1. Indirect
- * mode is the only way to access the pixis when DIU video
- * is enabled. Note that this assumes that the first column
- * of the 'ranges' property above is the chip select number.
- */
- board-control@0,0 {
- compatible = "fsl,p1022ds-indirect-pixis";
- reg = <0x0 0x0 1 /* CS0 */
- 0x1 0x0 1>; /* CS1 */
- };
-
- nor@0,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "cfi-flash";
- reg = <0x0 0x0 0x8000000>;
- bank-width = <2>;
- device-width = <1>;
-
- partition@0 {
- reg = <0x0 0x03000000>;
- label = "ramdisk-nor";
- read-only;
- };
-
- partition@3000000 {
- reg = <0x03000000 0x00e00000>;
- label = "diagnostic-nor";
- read-only;
- };
-
- partition@3e00000 {
- reg = <0x03e00000 0x00200000>;
- label = "dink-nor";
- read-only;
- };
-
- partition@4000000 {
- reg = <0x04000000 0x00400000>;
- label = "kernel-nor";
- read-only;
- };
-
- partition@4400000 {
- reg = <0x04400000 0x03b00000>;
- label = "jffs2-nor";
- };
-
- partition@7f00000 {
- reg = <0x07f00000 0x00080000>;
- label = "dtb-nor";
- read-only;
- };
-
- partition@7f80000 {
- reg = <0x07f80000 0x00080000>;
- label = "u-boot-nor";
- read-only;
- };
- };
-
- nand@2,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,elbc-fcm-nand";
- reg = <0x2 0x0 0x40000>;
-
- partition@0 {
- reg = <0x0 0x02000000>;
- label = "u-boot-nand";
- read-only;
- };
-
- partition@2000000 {
- reg = <0x02000000 0x10000000>;
- label = "jffs2-nand";
- };
-
- partition@12000000 {
- reg = <0x12000000 0x10000000>;
- label = "ramdisk-nand";
- read-only;
- };
-
- partition@22000000 {
- reg = <0x22000000 0x04000000>;
- label = "kernel-nand";
- };
-
- partition@26000000 {
- reg = <0x26000000 0x01000000>;
- label = "dtb-nand";
- read-only;
- };
-
- partition@27000000 {
- reg = <0x27000000 0x19000000>;
- label = "reserved-nand";
- };
- };
-
- board-control@3,0 {
- compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
- reg = <3 0 0x30>;
- interrupt-parent = <&mpic>;
- /*
- * IRQ8 is generated if the "EVENT" switch is pressed
- * and PX_CTL[EVESEL] is set to 00.
- */
- interrupts = <8 8 0 0>;
- };
- };
-
- soc: soc@fffe00000 {
- ranges = <0x0 0xf 0xffe00000 0x100000>;
-
- i2c@3100 {
- wm8776:codec@1a {
- compatible = "wlf,wm8776";
- reg = <0x1a>;
- /*
- * clock-frequency will be set by U-Boot if
- * the clock is enabled.
- */
- };
- };
-
- spi@7000 {
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spansion,s25sl12801";
- reg = <0>;
- spi-max-frequency = <40000000>; /* input clock */
-
- partition@0 {
- label = "u-boot-spi";
- reg = <0x00000000 0x00100000>;
- read-only;
- };
- partition@100000 {
- label = "kernel-spi";
- reg = <0x00100000 0x00500000>;
- read-only;
- };
- partition@600000 {
- label = "dtb-spi";
- reg = <0x00600000 0x00100000>;
- read-only;
- };
- partition@700000 {
- label = "file system-spi";
- reg = <0x00700000 0x00900000>;
- };
- };
- };
-
- ssi@15000 {
- fsl,mode = "i2s-slave";
- codec-handle = <&wm8776>;
- fsl,ssi-asynchronous;
- };
-
- usb@22000 {
- phy_type = "ulpi";
- };
-
- usb@23000 {
- status = "disabled";
- };
-
- mdio@24000 {
- phy0: ethernet-phy@0 {
- interrupts = <3 1 0 0>;
- reg = <0x1>;
- };
- phy1: ethernet-phy@1 {
- interrupts = <9 1 0 0>;
- reg = <0x2>;
- };
- };
-
- ethernet@b0000 {
- phy-handle = <&phy0>;
- phy-connection-type = "rgmii-id";
- };
-
- ethernet@b1000 {
- phy-handle = <&phy1>;
- phy-connection-type = "rgmii-id";
- };
- };
-
- pci0: pcie@fffe09000 {
- reg = <0xf 0xffe09000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
- 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
- pcie@0 {
- ranges = <0x2000000 0x0 0xe0000000
- 0x2000000 0x0 0xe0000000
- 0x0 0x20000000
-
- 0x1000000 0x0 0x0
- 0x1000000 0x0 0x0
- 0x0 0x100000>;
- };
- };
-
- pci1: pcie@fffe0a000 {
- reg = <0xf 0xffe0a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
- 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
- pcie@0 {
- reg = <0x0 0x0 0x0 0x0 0x0>;
- ranges = <0x2000000 0x0 0xe0000000
- 0x2000000 0x0 0xe0000000
- 0x0 0x20000000
-
- 0x1000000 0x0 0x0
- 0x1000000 0x0 0x0
- 0x0 0x100000>;
- };
- };
-
- pci2: pcie@fffe0b000 {
- reg = <0xf 0xffe0b000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
- 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
- pcie@0 {
- ranges = <0x2000000 0x0 0xe0000000
- 0x2000000 0x0 0xe0000000
- 0x0 0x20000000
-
- 0x1000000 0x0 0x0
- 0x1000000 0x0 0x0
- 0x0 0x100000>;
- };
- };
-};
-
-/include/ "fsl/p1022si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi b/arch/powerpc/boot/dts/p1022ds.dtsi
new file mode 100644
index 0000000..8a5d91a
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -0,0 +1,112 @@
+/*
+ * P1022 DS Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&board_soc {
+ i2c@3100 {
+ wm8776:codec@1a {
+ compatible = "wlf,wm8776";
+ reg = <0x1a>;
+ /*
+ * clock-frequency will be set by U-Boot if
+ * the clock is enabled.
+ */
+ };
+ };
+
+ spi@7000 {
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25sl12801";
+ reg = <0>;
+ spi-max-frequency = <40000000>; /* input clock */
+
+ partition@0 {
+ label = "u-boot-spi";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+ partition@100000 {
+ label = "kernel-spi";
+ reg = <0x00100000 0x00500000>;
+ read-only;
+ };
+ partition@600000 {
+ label = "dtb-spi";
+ reg = <0x00600000 0x00100000>;
+ read-only;
+ };
+ partition@700000 {
+ label = "file system-spi";
+ reg = <0x00700000 0x00900000>;
+ };
+ };
+ };
+
+ ssi@15000 {
+ fsl,mode = "i2s-slave";
+ codec-handle = <&wm8776>;
+ fsl,ssi-asynchronous;
+ };
+
+ usb@22000 {
+ phy_type = "ulpi";
+ };
+
+ usb@23000 {
+ status = "disabled";
+ };
+
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ interrupts = <3 1 0 0>;
+ reg = <0x1>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupts = <9 1 0 0>;
+ reg = <0x2>;
+ };
+ };
+
+ ethernet@b0000 {
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ ethernet@b1000 {
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+};
+
diff --git a/arch/powerpc/boot/dts/p1022ds_32b.dts b/arch/powerpc/boot/dts/p1022ds_32b.dts
new file mode 100644
index 0000000..14cadd5
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds_32b.dts
@@ -0,0 +1,218 @@
+/*
+ * P1022 DS 32-bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1022si-pre.dtsi"
+/ {
+ model = "fsl,P1022DS";
+ compatible = "fsl,P1022DS";
+
+ memory {
+ device_type = "memory";
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = <0x0 0xffe05000 0 0x1000>;
+ ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
+ 0x1 0x0 0x0 0xe0000000 0x08000000
+ 0x2 0x0 0x0 0xff800000 0x00040000
+ 0x3 0x0 0x0 0xffdf0000 0x00008000>;
+
+ /*
+ * This node is used to access the pixis via "indirect" mode,
+ * which is done by writing the pixis register index to chip
+ * select 0 and the value to/from chip select 1. Indirect
+ * mode is the only way to access the pixis when DIU video
+ * is enabled. Note that this assumes that the first column
+ * of the 'ranges' property above is the chip select number.
+ */
+ board-control@0,0 {
+ compatible = "fsl,p1022ds-indirect-pixis";
+ reg = <0x0 0x0 1 /* CS0 */
+ 0x1 0x0 1>; /* CS1 */
+ };
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ reg = <0x0 0x03000000>;
+ label = "ramdisk-nor";
+ read-only;
+ };
+
+ partition@3000000 {
+ reg = <0x03000000 0x00e00000>;
+ label = "diagnostic-nor";
+ read-only;
+ };
+
+ partition@3e00000 {
+ reg = <0x03e00000 0x00200000>;
+ label = "dink-nor";
+ read-only;
+ };
+
+ partition@4000000 {
+ reg = <0x04000000 0x00400000>;
+ label = "kernel-nor";
+ read-only;
+ };
+
+ partition@4400000 {
+ reg = <0x04400000 0x03b00000>;
+ label = "jffs2-nor";
+ };
+
+ partition@7f00000 {
+ reg = <0x07f00000 0x00080000>;
+ label = "dtb-nor";
+ read-only;
+ };
+
+ partition@7f80000 {
+ reg = <0x07f80000 0x00080000>;
+ label = "u-boot-nor";
+ read-only;
+ };
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x2 0x0 0x40000>;
+
+ partition@0 {
+ reg = <0x0 0x02000000>;
+ label = "u-boot-nand";
+ read-only;
+ };
+
+ partition@2000000 {
+ reg = <0x02000000 0x10000000>;
+ label = "jffs2-nand";
+ };
+
+ partition@12000000 {
+ reg = <0x12000000 0x10000000>;
+ label = "ramdisk-nand";
+ read-only;
+ };
+
+ partition@22000000 {
+ reg = <0x22000000 0x04000000>;
+ label = "kernel-nand";
+ };
+
+ partition@26000000 {
+ reg = <0x26000000 0x01000000>;
+ label = "dtb-nand";
+ read-only;
+ };
+
+ partition@27000000 {
+ reg = <0x27000000 0x19000000>;
+ label = "reserved-nand";
+ };
+ };
+
+ board-control@3,0 {
+ compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
+ reg = <3 0 0x30>;
+ interrupt-parent = <&mpic>;
+ /*
+ * IRQ8 is generated if the "EVENT" switch is pressed
+ * and PX_CTL[EVESEL] is set to 00.
+ */
+ interrupts = <8 8 0 0>;
+ };
+ };
+
+ board_soc: soc: soc@ffe00000 {
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ };
+
+ pci0: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xe0000000
+ 0x2000000 0x0 0xe0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ reg = <0 0xffe0a000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xe0000000
+ 0x2000000 0x0 0xe0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci2: pcie@ffe0b000 {
+ reg = <0 0xffe0b000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xe0000000
+ 0x2000000 0x0 0xe0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
+
+/include/ "fsl/p1022si-post.dtsi"
+/include/ "p1022ds.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds_36b.dts b/arch/powerpc/boot/dts/p1022ds_36b.dts
new file mode 100644
index 0000000..7547a6c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds_36b.dts
@@ -0,0 +1,218 @@
+/*
+ * P1022 DS 36-bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1022si-pre.dtsi"
+/ {
+ model = "fsl,P1022DS";
+ compatible = "fsl,P1022DS";
+
+ memory {
+ device_type = "memory";
+ };
+
+ lbc: localbus@fffe05000 {
+ reg = <0xf 0xffe05000 0 0x1000>;
+ ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
+ 0x1 0x0 0xf 0xe0000000 0x08000000
+ 0x2 0x0 0xf 0xff800000 0x00040000
+ 0x3 0x0 0xf 0xffdf0000 0x00008000>;
+
+ /*
+ * This node is used to access the pixis via "indirect" mode,
+ * which is done by writing the pixis register index to chip
+ * select 0 and the value to/from chip select 1. Indirect
+ * mode is the only way to access the pixis when DIU video
+ * is enabled. Note that this assumes that the first column
+ * of the 'ranges' property above is the chip select number.
+ */
+ board-control@0,0 {
+ compatible = "fsl,p1022ds-indirect-pixis";
+ reg = <0x0 0x0 1 /* CS0 */
+ 0x1 0x0 1>; /* CS1 */
+ };
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ reg = <0x0 0x03000000>;
+ label = "ramdisk-nor";
+ read-only;
+ };
+
+ partition@3000000 {
+ reg = <0x03000000 0x00e00000>;
+ label = "diagnostic-nor";
+ read-only;
+ };
+
+ partition@3e00000 {
+ reg = <0x03e00000 0x00200000>;
+ label = "dink-nor";
+ read-only;
+ };
+
+ partition@4000000 {
+ reg = <0x04000000 0x00400000>;
+ label = "kernel-nor";
+ read-only;
+ };
+
+ partition@4400000 {
+ reg = <0x04400000 0x03b00000>;
+ label = "jffs2-nor";
+ };
+
+ partition@7f00000 {
+ reg = <0x07f00000 0x00080000>;
+ label = "dtb-nor";
+ read-only;
+ };
+
+ partition@7f80000 {
+ reg = <0x07f80000 0x00080000>;
+ label = "u-boot-nor";
+ read-only;
+ };
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x2 0x0 0x40000>;
+
+ partition@0 {
+ reg = <0x0 0x02000000>;
+ label = "u-boot-nand";
+ read-only;
+ };
+
+ partition@2000000 {
+ reg = <0x02000000 0x10000000>;
+ label = "jffs2-nand";
+ };
+
+ partition@12000000 {
+ reg = <0x12000000 0x10000000>;
+ label = "ramdisk-nand";
+ read-only;
+ };
+
+ partition@22000000 {
+ reg = <0x22000000 0x04000000>;
+ label = "kernel-nand";
+ };
+
+ partition@26000000 {
+ reg = <0x26000000 0x01000000>;
+ label = "dtb-nand";
+ read-only;
+ };
+
+ partition@27000000 {
+ reg = <0x27000000 0x19000000>;
+ label = "reserved-nand";
+ };
+ };
+
+ board-control@3,0 {
+ compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
+ reg = <3 0 0x30>;
+ interrupt-parent = <&mpic>;
+ /*
+ * IRQ8 is generated if the "EVENT" switch is pressed
+ * and PX_CTL[EVESEL] is set to 00.
+ */
+ interrupts = <8 8 0 0>;
+ };
+ };
+
+ board_soc: soc: soc@fffe00000 {
+ ranges = <0x0 0xf 0xffe00000 0x100000>;
+ };
+
+ pci0: pcie@fffe09000 {
+ reg = <0xf 0xffe09000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xe0000000
+ 0x2000000 0x0 0xe0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci1: pcie@fffe0a000 {
+ reg = <0xf 0xffe0a000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xe0000000
+ 0x2000000 0x0 0xe0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci2: pcie@fffe0b000 {
+ reg = <0xf 0xffe0b000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xe0000000
+ 0x2000000 0x0 0xe0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
+
+/include/ "fsl/p1022si-post.dtsi"
+/include/ "p1022ds.dtsi"
--
1.7.3.4
^ permalink raw reply related
* [PATCH 1/2] [v2] powerpc/85xx: p1022ds: disable the NOR flash node if video is enabled
From: Timur Tabi @ 2011-12-08 0:04 UTC (permalink / raw)
To: kumar.gala, linuxppc-dev
The Freescale P1022 has a unique pin muxing "feature" where the DIU video
controller's video signals are muxed with 24 of the local bus address signals.
When the DIU is enabled, the bulk of the local bus is disabled, preventing
access to memory-mapped devices like NOR flash and the pixis FPGA.
Therefore, if the DIU is going to be enabled, then memory-mapped devices on
the localbus, like NOR flash, need to be disabled.
This also means that the localbus is not a 'simple-bus' any more, so remove
that string from the compatible node.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
arch/powerpc/boot/dts/fsl/p1022si-post.dtsi | 6 ++-
arch/powerpc/platforms/85xx/p1022_ds.c | 71 +++++++++++++++++++++++++++
2 files changed, 76 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
index 16239b1..2a62edd 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -35,7 +35,11 @@
&lbc {
#address-cells = <2>;
#size-cells = <1>;
- compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
+ /*
+ * The localbus on the P1022 is not a simple-bus because of the eLBC
+ * pin muxing when the DIU is enabled.
+ */
+ compatible = "fsl,p1022-elbc", "fsl,elbc";
interrupts = <19 2 0 0>;
};
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 2ec39f4..6c9638c 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -360,6 +360,49 @@ void __init p1022_ds_pic_init(void)
void __init mpc85xx_smp_init(void);
#endif
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+
+/*
+ * Disables a node in the device tree.
+ *
+ * This function is called before kmalloc() is available, so the 'new' object
+ * should be allocated in the global area. The easiest way is to do that is
+ * to allocate one static local variable for each call to this function.
+ */
+static void __init disable_one_node(struct device_node *np, struct property *new)
+{
+ struct property *old;
+
+ old = of_find_property(np, new->name, NULL);
+ if (old)
+ prom_update_property(np, new, old);
+ else
+ prom_add_property(np, new);
+}
+
+/* TRUE if there is a "video=fslfb" command-line parameter. */
+static bool fslfb;
+
+/*
+ * Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
+ * true if we find it.
+ *
+ * We need to use early_param() instead of __setup() because the normal
+ * __setup() gets called to late. However, early_param() gets called very
+ * early, before the device tree is unflattened, so all we can do now is set a
+ * global variable. Later on, p1022_ds_setup_arch() will use that variable
+ * to determine if we need to update the device tree.
+ */
+static int __init early_video_setup(char *options)
+{
+ fslfb = (strncmp(options, "fslfb:", 6) == 0);
+
+ return 0;
+}
+early_param("video", early_video_setup);
+
+#endif
+
/*
* Setup the architecture
*/
@@ -397,6 +440,34 @@ static void __init p1022_ds_setup_arch(void)
diu_ops.set_monitor_port = p1022ds_set_monitor_port;
diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
+
+ /*
+ * Disable the NOR flash node if there is video=fslfb... command-line
+ * parameter. When the DIU is active, NOR flash is unavailable, so we
+ * have to delete the node before the MTD driver loads.
+ */
+ if (fslfb) {
+ struct device_node *np =
+ of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
+
+ if (np) {
+ np = of_find_compatible_node(np, NULL, "cfi-flash");
+ if (np) {
+ static struct property nor_status = {
+ .name = "status",
+ .value = "disabled",
+ .length = sizeof("disabled"),
+ };
+
+ pr_info("p1022ds: disabling %s node",
+ np->full_name);
+ disable_one_node(np, &nor_status);
+ of_node_put(np);
+ }
+ }
+
+ }
+
#endif
#ifdef CONFIG_SMP
--
1.7.3.4
^ permalink raw reply related
* Re: ibm_newemac tx problem with jumbo frame enabled
From: Benjamin Herrenschmidt @ 2011-12-07 22:03 UTC (permalink / raw)
To: Prashant Bhole; +Cc: linuxppc-dev
In-Reply-To: <CAD6p20chCnh+PN5ekPz20BJQMdTaisb5toLA9rySaYJTeivRfQ@mail.gmail.com>
On Wed, 2011-12-07 at 13:35 +0530, Prashant Bhole wrote:
> Still couldn't find anything like fifo overflow...
> I noticed one more thing, this problem happens only when mtu size on
> the initiator (the other end) is set to 4088, regardless of any mtu
> size set for EMAC.
Did you check all the registers that may carry errors ? Nothing showed
up ? Did you check that things like Pause frames were properly
negociated on both sides ? Tried playing with the pause and FIFO
thresholds ?
Other than using the tx timeout to perform resets I don't see a good way
to fix that problem.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH net-next v6 4/4] powerpc: tqm8548/tqm8xx: add and update CAN device nodes
From: Benjamin Herrenschmidt @ 2011-12-07 22:01 UTC (permalink / raw)
To: Wolfgang Grandegger
Cc: linuxppc-dev, netdev, devicetree-discuss, socketcan-users,
linux-can
In-Reply-To: <4EDF22DF.5020001@grandegger.com>
On Wed, 2011-12-07 at 09:25 +0100, Wolfgang Grandegger wrote:
> > Also there have been at least 3 versions in a couple of days already
> > without comments nor indication of what was changed...
>
> Unfortunately, no response from those sub-system guys.
>
> > Can you clarify things a bit please ? It looks like they really should
> > go to linuxppc-dev (and you can probably drop a bunch of other lists) or
> > am I missing an important piece of the puzzle ? (Such as patch 1/4 and
> > 2/4 ...)
>
> I have not sent the whole series. The changes are documented in the
> cover-letter, which I have not sent for those patches. Well, I think
> it's better to sent the whole series to all parties instead?
Well at least for linuxppc-dev, don't bother now that I know what this
is about :-)
> > Let me know if I should just remove them from powerpc patchwork.
>
> Dave has already applied all patches.
>
> Sorry for the confusion. Any advice on how to handle multi subsystem
> series of patches properly is welcome.
No specific advice. Ideally, if patchwork could track cover letters it
would help but I don't see a non-nasty way to do it so ... :-)
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Add TBI PHY node to first MDIO bus
From: Kumar Gala @ 2011-12-07 21:52 UTC (permalink / raw)
To: David Miller; +Cc: netdev, afleming, linuxppc-dev
In-Reply-To: <20111207.150208.588206951117780997.davem@davemloft.net>
On Dec 7, 2011, at 2:02 PM, David Miller wrote:
> From: Andy Fleming <afleming@freescale.com>
> Date: Wed, 7 Dec 2011 13:50:57 -0600
>
>> Systems which use the fsl_pq_mdio driver need to specify an
>> address for TBI PHY transactions such that the address does
>> not conflict with any PHYs on the bus (all transactions to
>> that address are directed to the onboard TBI PHY). The driver
>> used to scan for a free address if no address was specified,
>> however this ran into issues when the PHY Lib was fixed so
>> that all MDIO transactions were protected by a mutex. As it
>> is, the code was meant to serve as a transitional tool until
>> the device trees were all updated to specify the TBI address.
>>
>> The best fix for the mutex issue was to remove the scanning code,
>> but it turns out some of the newer SoCs have started to omit
>> the tbi-phy node when SGMII is not being used. As such, these
>> devices will now fail unless we add a tbi-phy node to the first
>> mdio controller.
>>
>> Signed-off-by: Andy Fleming <afleming@freescale.com>
>> ---
>>
>> This requires fsl_pq_mdio: Clean up tbi address configuration from
>> the net tree in order to achieve its full effect.
>>
>> This needs to go into 3.2.
>
> I'm fine if the powerpc tree takes this one:
>
> Acked-by: David S. Miller <davem@davemloft.net>
Will pull in via PPC tree.
- k
^ permalink raw reply
* Re: Multi-OS on P1022RDK Failing
From: Scott Wood @ 2011-12-07 21:24 UTC (permalink / raw)
To: Arshad, Farrukh; +Cc: Linuxppc-dev@lists.ozlabs.org
In-Reply-To: <93CD5F41FDBC6042A6B449764F3B35CC050C38FB@EU-MBX-03.mgc.mentorg.com>
On 12/07/2011 08:57 AM, Arshad, Farrukh wrote:
> Core 0 kernel
>=20
> CONFIG_LOWMEM_SIZE =3D 0x10000000
>=20
> CONFIG_PHYSICAL_START =3D 0x00000000
>=20
> =20
>=20
> Core 1 kernel
>=20
> CONFIG_LOWMEM_SIZE =3D 0x10000000
>=20
> CONFIG_PHYSICAL_START =3D 0x10000000
Why are you messing with CONFIG_LOWMEM_SIZE? That adjusts the
lowmem/highmem split, not the total amount of memory that this instance
of Linux will use (though you may get that behavior as a side effect if
highmem is disabled). U-boot should set the memory node in the device
tree based on the bootm_low/bootm_size environment variables.
> # Boot from NFS
>=20
> setenv core0nfsbootargs root=3D/dev/nfs nfsroot=3D$serverip:/$core0root=
fs
> ip=3D<dev_ip>::<nfs_server_ip>:::eth0:off rw debug
> console=3D$consoledev0,$baudrate maxcpus=3D1
>=20
> setenv core1nfsbootargs root=3D/dev/nfs nfsroot=3D$serverip:/$core1root=
fs
> ip=3D<dev_ip_2>::<nfs_server_ip>:::eth0:off rw debug
> console=3D$consoledev0,$baudrate maxcpus=3D1
maxcpus should be unnecessary -- there will only be one cpu in the
device tree for each partition.
> My problem is Core 0 kernel is booting successfully but Core 1 kernel
> hangs after uncompressing kernel image, and after that I don=92t see
> anything on the console.
>=20
> =20
>=20
> Any thoughts on what I am missing or doing incorrect?
The "cpu 1 release" command should be using the address of the
decompressed kernel (should be $bootm_low), not where the uImage was load=
ed.
Also, the two serial ports you're using share an interrupt -- this
shouldn't stop kernel message output, but it's going to be a problem for
userspace usage of the port. You should remove the interrupts property
from the serial node in both partitions, so Linux will poll instead.
-Scott
^ permalink raw reply
* Re: [PATCH -resend 1/1] SPI: disable CONFIG_SPI_FSL_ESPI=m build
From: Wolfram Sang @ 2011-12-07 20:33 UTC (permalink / raw)
To: Jiri Slaby; +Cc: linuxppc-dev, linux-kernel, jirislaby
In-Reply-To: <1323289096-13599-1-git-send-email-jslaby@suse.cz>
[-- Attachment #1: Type: text/plain, Size: 980 bytes --]
On Wed, Dec 07, 2011 at 09:18:16PM +0100, Jiri Slaby wrote:
> When spi_fsl_espi is chosen to be built as a module, there is a build
> error because we test only CONFIG_SPI_FSL_ESPI in declaration of
> struct mpc8xxx_spi in drivers/spi/spi_fsl_lib.h. Also some called
> functions are not exported.
>
> So we forbid CONFIG_SPI_FSL_ESPI to be tristate here.
>
> The error looks like:
> drivers/spi/spi_fsl_espi.c: In function 'fsl_espi_bufs':
> drivers/spi/spi_fsl_espi.c:232: error: 'struct mpc8xxx_spi' has no member named 'len'
> ...
>
> Signed-off-by: Jiri Slaby <jslaby@suse.cz>
> Acked-by: Kumar Gala <galak@kernel.crashing.org>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> ---
> Maybe Grant is back already?
I just picked it up in the for-linus branch I am preparing while Grant
is away.
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply
* [PATCH RESEND] rapidio/tsi721: modify PCIe capability settings
From: Alexandre Bounine @ 2011-12-07 20:31 UTC (permalink / raw)
To: akpm, linux-kernel, linuxppc-dev; +Cc: Alexandre Bounine
In-Reply-To: <1323289875-25559-1-git-send-email-alexandre.bounine@idt.com>
Modify initialization of PCIe capability registers in Tsi721 mport driver:
- change Completion Timeout value to avoid unexpected data transfer aborts
during intensive traffic.
- replace hardcoded offset of PCIe capability block by getting it using
the common function.
This patch is applicable to kernel versions starting from 3.2-rc1.
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
---
[Resending this patch with updated commit comment]
drivers/rapidio/devices/tsi721.c | 20 +++++++++++++++-----
drivers/rapidio/devices/tsi721.h | 2 ++
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/rapidio/devices/tsi721.c b/drivers/rapidio/devices/tsi721.c
index 83ac8728..691b1ab 100644
--- a/drivers/rapidio/devices/tsi721.c
+++ b/drivers/rapidio/devices/tsi721.c
@@ -2154,7 +2154,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct tsi721_device *priv;
- int i;
+ int i, cap;
int err;
u32 regval;
@@ -2262,10 +2262,20 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
}
- /* Clear "no snoop" and "relaxed ordering" bits. */
- pci_read_config_dword(pdev, 0x40 + PCI_EXP_DEVCTL, ®val);
- regval &= ~(PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN);
- pci_write_config_dword(pdev, 0x40 + PCI_EXP_DEVCTL, regval);
+ cap = pci_pcie_cap(pdev);
+ BUG_ON(cap == 0);
+
+ /* Clear "no snoop" and "relaxed ordering" bits, use default MRRS. */
+ pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, ®val);
+ regval &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |
+ PCI_EXP_DEVCTL_NOSNOOP_EN);
+ regval |= 0x2 << MAX_READ_REQUEST_SZ_SHIFT;
+ pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL, regval);
+
+ /* Adjust PCIe completion timeout. */
+ pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL2, ®val);
+ regval &= ~(0x0f);
+ pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL2, regval | 0x2);
/*
* FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block
diff --git a/drivers/rapidio/devices/tsi721.h b/drivers/rapidio/devices/tsi721.h
index 58be4de..822e54c 100644
--- a/drivers/rapidio/devices/tsi721.h
+++ b/drivers/rapidio/devices/tsi721.h
@@ -72,6 +72,8 @@
#define TSI721_MSIXPBA_OFFSET 0x2a000
#define TSI721_PCIECFG_EPCTL 0x400
+#define MAX_READ_REQUEST_SZ_SHIFT 12
+
/*
* Event Management Registers
*/
--
1.7.6
^ permalink raw reply related
* [PATCH RESEND] rapidio/tsi721: Fix mailbox resource reporting
From: Alexandre Bounine @ 2011-12-07 20:31 UTC (permalink / raw)
To: akpm, linux-kernel, linuxppc-dev; +Cc: Alexandre Bounine
Bug fix for Tsi721 RapidIO mport driver:
Tsi721 supports four RapidIO mailboxes (MBOX0 - MBOX3) as defined by RapidIO
specification. Mailbox resources has to be properly reported to allow use
of all available mailboxes (initial version reports only MBOX0).
This patch is applicable to kernel versions staring from 3.2-rc1.
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
---
[Resending this patch with updated commit comment]
drivers/rapidio/devices/tsi721.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/rapidio/devices/tsi721.c b/drivers/rapidio/devices/tsi721.c
index 514c28c..83ac8728 100644
--- a/drivers/rapidio/devices/tsi721.c
+++ b/drivers/rapidio/devices/tsi721.c
@@ -2107,8 +2107,8 @@ static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
INIT_LIST_HEAD(&mport->dbells);
rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
- rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
- rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
+ rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 3);
+ rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 3);
strcpy(mport->name, "Tsi721 mport");
/* Hook up interrupt handler */
--
1.7.6
^ permalink raw reply related
* [PATCH -resend 1/1] SPI: disable CONFIG_SPI_FSL_ESPI=m build
From: Jiri Slaby @ 2011-12-07 20:18 UTC (permalink / raw)
To: grant.likely; +Cc: linuxppc-dev, linux-kernel, jirislaby
When spi_fsl_espi is chosen to be built as a module, there is a build
error because we test only CONFIG_SPI_FSL_ESPI in declaration of
struct mpc8xxx_spi in drivers/spi/spi_fsl_lib.h. Also some called
functions are not exported.
So we forbid CONFIG_SPI_FSL_ESPI to be tristate here.
The error looks like:
drivers/spi/spi_fsl_espi.c: In function 'fsl_espi_bufs':
drivers/spi/spi_fsl_espi.c:232: error: 'struct mpc8xxx_spi' has no member named 'len'
...
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
---
Maybe Grant is back already?
drivers/spi/Kconfig | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9c90a7a..3d292be 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -198,7 +198,7 @@ config SPI_FSL_LIB
depends on FSL_SOC
config SPI_FSL_SPI
- tristate "Freescale SPI controller"
+ bool "Freescale SPI controller"
depends on FSL_SOC
select SPI_FSL_LIB
help
@@ -207,7 +207,7 @@ config SPI_FSL_SPI
MPC8569 uses the controller in QE mode, MPC8610 in cpu mode.
config SPI_FSL_ESPI
- tristate "Freescale eSPI controller"
+ bool "Freescale eSPI controller"
depends on FSL_SOC
select SPI_FSL_LIB
help
--
1.7.7.3
^ permalink raw reply related
* Re: [PATCH] powerpc: Add TBI PHY node to first MDIO bus
From: David Miller @ 2011-12-07 20:02 UTC (permalink / raw)
To: afleming; +Cc: netdev, linuxppc-dev
In-Reply-To: <1323287457-6085-1-git-send-email-afleming@freescale.com>
From: Andy Fleming <afleming@freescale.com>
Date: Wed, 7 Dec 2011 13:50:57 -0600
> Systems which use the fsl_pq_mdio driver need to specify an
> address for TBI PHY transactions such that the address does
> not conflict with any PHYs on the bus (all transactions to
> that address are directed to the onboard TBI PHY). The driver
> used to scan for a free address if no address was specified,
> however this ran into issues when the PHY Lib was fixed so
> that all MDIO transactions were protected by a mutex. As it
> is, the code was meant to serve as a transitional tool until
> the device trees were all updated to specify the TBI address.
>
> The best fix for the mutex issue was to remove the scanning code,
> but it turns out some of the newer SoCs have started to omit
> the tbi-phy node when SGMII is not being used. As such, these
> devices will now fail unless we add a tbi-phy node to the first
> mdio controller.
>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> ---
>
> This requires fsl_pq_mdio: Clean up tbi address configuration from
> the net tree in order to achieve its full effect.
>
> This needs to go into 3.2.
I'm fine if the powerpc tree takes this one:
Acked-by: David S. Miller <davem@davemloft.net>
^ permalink raw reply
* [PATCH] powerpc: Add TBI PHY node to first MDIO bus
From: Andy Fleming @ 2011-12-07 19:50 UTC (permalink / raw)
To: Kumar Gala, David Miller; +Cc: netdev, linuxppc-dev
Systems which use the fsl_pq_mdio driver need to specify an
address for TBI PHY transactions such that the address does
not conflict with any PHYs on the bus (all transactions to
that address are directed to the onboard TBI PHY). The driver
used to scan for a free address if no address was specified,
however this ran into issues when the PHY Lib was fixed so
that all MDIO transactions were protected by a mutex. As it
is, the code was meant to serve as a transitional tool until
the device trees were all updated to specify the TBI address.
The best fix for the mutex issue was to remove the scanning code,
but it turns out some of the newer SoCs have started to omit
the tbi-phy node when SGMII is not being used. As such, these
devices will now fail unless we add a tbi-phy node to the first
mdio controller.
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
This requires fsl_pq_mdio: Clean up tbi address configuration from
the net tree in order to achieve its full effect.
This needs to go into 3.2.
arch/powerpc/boot/dts/p1010rdb.dts | 5 +++++
arch/powerpc/boot/dts/p1020rdb.dts | 5 +++++
arch/powerpc/boot/dts/p1020rdb_camp_core0.dts | 5 +++++
arch/powerpc/boot/dts/p1021mds.dts | 4 ++++
arch/powerpc/boot/dts/p1022ds.dts | 4 ++++
arch/powerpc/boot/dts/p2020rdb.dts | 8 ++++++--
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts | 4 ++++
7 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
index d6c669c..e1f9683 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dts
+++ b/arch/powerpc/boot/dts/p1010rdb.dts
@@ -193,6 +193,11 @@
interrupts = <2 1>;
reg = <0x2>;
};
+
+ tbi-phy@3 {
+ device-type = "tbi-phy";
+ reg = <0x3>;
+ };
};
enet0: ethernet@b0000 {
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index d6a8ae4..72e4fc4 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -209,6 +209,11 @@
interrupts = <2 1>;
reg = <0x1>;
};
+
+ tbi-phy@2 {
+ device_type = "tbi-phy";
+ reg = <0x2>;
+ };
};
mdio@25000 {
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
index f0bf7f4..ad805a1 100644
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
@@ -112,6 +112,11 @@
interrupts = <2 1>;
reg = <0x1>;
};
+
+ tbi-phy@2 {
+ device-type = "tbi-phy";
+ reg = <0x2>;
+ };
};
mdio@25000 {
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
index ad5b852..ba53b4b 100644
--- a/arch/powerpc/boot/dts/p1021mds.dts
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -338,6 +338,10 @@
interrupt-parent = <&mpic>;
reg = <0x4>;
};
+ tbi-phy@5 {
+ device_type = "tbi-phy";
+ reg = <0x5>;
+ };
};
mdio@25000 {
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
index 89ca93e..4bf382d 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -391,6 +391,10 @@
interrupts = <9 1 0 0>;
reg = <0x2>;
};
+ tbi-phy@2 {
+ device_type = "tbi-phy";
+ reg = <0x2>;
+ };
};
mdio@25000 {
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index 1d7a05f..9e4ae85 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -205,12 +205,16 @@
interrupt-parent = <&mpic>;
interrupts = <3 1>;
reg = <0x0>;
- };
+ };
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <3 1>;
reg = <0x1>;
- };
+ };
+ tbi-phy@2 {
+ device_type = "tbi-phy";
+ reg = <0x2>;
+ };
};
mdio@25520 {
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index fc8dddd..8e5bda1 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -122,6 +122,10 @@
interrupts = <3 1>;
reg = <0x1>;
};
+ tbi-phy@2 {
+ device_type = "tbi-phy";
+ reg = <0x2>;
+ };
};
mdio@25520 {
--
1.7.3.4
^ permalink raw reply related
* Re: pata_sl82c105 is unable to properly handle dma (indeed it try to use mwdma2)
From: acrux @ 2011-12-07 19:30 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linux-ide, linuxppc-dev
In-Reply-To: <1323224488.660.33.camel@pasglop>
On Wed, 07 Dec 2011 13:21:28 +1100
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> On Wed, 2011-12-07 at 02:15 +0100, acrux_it@libero.it wrote:
> > New pata_sl82c105 is unable to properly handle dma (indeed it try to use
> > mwdma2).
> > Old ide driver instead worked fine.
> >
> > Tested on IBM 9114-275 where to use it i must boot with dma disabled i.e. with
> > libata.dma=0
>
> Adding the linux-ide list on CC. Can you also send a dmesg with the old
> IDE driver ? It might be useful to compare the values programmed by the
> 2 versions of the driver in the timing registers.
>
hi Ben,
booting with a CRUX PPC (64bit) 2.6 with kernel linux-2.6.32.3 with old sl82c105 ide driver.
Here topic section from lspci -vvv
0000:00:03.0 ISA bridge: Symphony Labs W83C553F/W83C554F (rev 10)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
0000:00:03.1 IDE interface: Symphony Labs SL82c105 (rev 05) (prog-if 8f [Master SecP SecO PriP PriO])
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 72 (500ns min, 10000ns max), Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 165
Region 0: I/O ports at f000 [size=8]
Region 1: I/O ports at f010 [size=4]
Region 2: I/O ports at f020 [size=8]
Region 3: I/O ports at f030 [size=4]
Region 4: I/O ports at f040 [size=16]
Region 5: I/O ports at <unassigned>
Kernel driver in use: W82C105_IDE
An here it is the dmesg:
[...]
early_node_map[1] active PFN ranges
0: 0x00000000 -> 0x00100000
[boot]0015 Setup Done
PERCPU: Embedded 12 pages/cpu @c000000000a00000 s17480 r0 d31672 u524288
pcpu-alloc: s17480 r0 d31672 u524288 alloc=1*1048576
pcpu-alloc: [0] 0 1
Built 1 zonelists in Node order, mobility grouping on. Total pages: 1034240
Policy zone: DMA
Kernel command line: root=/dev/hda ro console=ttyS0,9600
PID hash table entries: 4096 (order: 3, 32768 bytes)
freeing bootmem node 0
Memory: 4033656k/4194304k available (7844k kernel code, 160648k reserved, 1308k)
SLUB: Genslabs=14, HWalign=128, Order=0-3, MinObjects=0, CPUs=2, Nodes=256
Hierarchical RCU implementation.
NR_IRQS:512
[boot]0020 XICS Init
[boot]0021 XICS Done
i8259 legacy interrupt controller initialized
clocksource: timebase mult[160a04b] shift[22] registered
Console: colour dummy device 80x25
Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
Mount-cache hash table entries: 256
Processor 1 found.
Brought up 2 CPUs
NET: Registered protocol family 16
IBM eBus Device Driver
PCI: Probing PCI hardware
pci 0000:00:02.0: PME# supported from D1 D2 D3hot
pci 0000:00:02.0: PME# disabled
pci 0000:00:02.2: PME# supported from D1 D2 D3hot
pci 0000:00:02.2: PME# disabled
pci 0000:00:02.4: PME# supported from D1 D2 D3hot
pci 0000:00:02.4: PME# disabled
pci 0000:00:02.6: PME# supported from D1 D2 D3hot
pci 0000:00:02.6: PME# disabled
Using INTC for W82c105 IDE controller.
IOMMU table initialized, virtual merging enabled
pci 0000:01:01.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:01:01.0: PME# disabled
pci 0000:21:01.0: PME# supported from D0 D1 D2 D3hot D3cold
pci 0000:21:01.0: PME# disabled
pci 0001:00:02.0: PME# supported from D1 D2 D3hot
pci 0001:00:02.0: PME# disabled
pci 0001:00:02.2: PME# supported from D1 D2 D3hot
pci 0001:00:02.2: PME# disabled
pci 0001:00:02.3: PME# supported from D1 D2 D3hot
pci 0001:00:02.3: PME# disabled
pci 0001:00:02.4: PME# supported from D1 D2 D3hot
pci 0001:00:02.4: PME# disabled
pci 0001:00:02.6: PME# supported from D1 D2 D3hot
pci 0001:00:02.6: PME# disabled
pci 0001:21:01.0: PME# supported from D0 D1 D2 D3hot
pci 0001:21:01.0: PME# disabled
pci 0001:31:01.0: PME# supported from D0 D1 D2 D3hot
pci 0001:31:01.0: PME# disabled
pci 0001:31:01.1: PME# supported from D0 D1 D2 D3hot
pci 0001:31:01.1: PME# disabled
pci 0001:41:01.0: PME# supported from D0 D3hot D3cold
pci 0001:41:01.0: PME# disabled
PCI: Cannot allocate resource region 2 of PCI bridge 1, will remap
PCI: Cannot allocate resource region 2 of PCI bridge 33, will remap
PCI: Cannot allocate resource region 2 of PCI bridge 65, will remap
PCI: Cannot allocate resource region 2 of PCI bridge 97, will remap
PCI: Cannot allocate resource region 2 of PCI bridge 1, will remap
PCI: Cannot allocate resource region 2 of PCI bridge 33, will remap
PCI: Cannot allocate resource region 2 of PCI bridge 49, will remap
PCI: Cannot allocate resource region 2 of PCI bridge 65, will remap
PCI: Cannot allocate resource region 2 of PCI bridge 97, will remap
PCI: Cannot allocate resource region 0 of device 0000:00:02.2, will remap
PCI: Cannot allocate resource region 0 of device 0000:00:02.4, will remap
PCI: Cannot allocate resource region 0 of device 0000:00:02.6, will remap
PCI: Cannot allocate resource region 0 of device 0001:00:02.2, will remap
PCI: Cannot allocate resource region 0 of device 0001:00:02.3, will remap
PCI: Cannot allocate resource region 0 of device 0001:00:02.4, will remap
PCI: Cannot allocate resource region 0 of device 0001:00:02.6, will remap
bio: create slab <bio-0> at 0
vgaarb: device added: PCI:0000:02:00.0,decodes=io+mem,owns=none,locks=none
vgaarb: device added: PCI:0001:61:01.0,decodes=io+mem,owns=none,locks=none
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Switching to clocksource timebase
NET: Registered protocol family 2
Switched to NOHz mode on CPU #1
Switched to NOHz mode on CPU #0
IP route cache hash table entries: 131072 (order: 8, 1048576 bytes)
TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
TCP: Hash tables configured (established 524288 bind 65536)
TCP reno registered
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
VFS: Disk quotas dquot_6.5.2
Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
JFS: nTxBlock = 8192, nTxLock = 65536
SGI XFS with security attributes, large block/inode numbers, no debug enabled
msgmni has been set to 7878
alg: No test for cipher_null (cipher_null-generic)
alg: No test for ecb(cipher_null) (ecb-cipher_null)
alg: No test for digest_null (digest_null-generic)
alg: No test for compress_null (compress_null-generic)
alg: No test for stdrng (krng)
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
io scheduler noop registered
io scheduler cfq registered (default)
matroxfb: Matrox G450 detected
PInS data found at offset 31168
PInS memtype = 5
matroxfb: 640x480x8bpp (virtual: 640x26214)
matroxfb: framebuffer at 0x3FD80000000, mapped to 0xd000080080080000, size 16776
Console: switching to colour frame buffer device 80x30
fb0: MATROX frame buffer device
matroxfb_crtc2: secondary head of fb0 was registered as fb1
fb2: IBM GXT6500P frame buffer device
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
serial8250.0: ttyS0 at I/O 0x103f8 (irq = 4) is a 16550A
console [ttyS0] enabled, bootconsole disabled
console [ttyS0] enabled, bootconsole disabled
serial8250.0: ttyS1 at I/O 0x102f8 (irq = 3) is a 16550A
serial8250.0: ttyS2 at I/O 0x10898 (irq = 10) is a 16550A
Floppy drive(s): fd0 is 2.88M
FDC 0 is a National Semiconductor PC87306
brd: module loaded
loop: module loaded
nbd: registered device at major 43
Uniform Multi-Platform E-IDE driver
sl82c105 0000:00:03.1: IDE controller (0x10ad:0x0105 rev 0x05)
pci 0000:00:03.1: enabling device (0144 -> 0145)
sl82c105 0000:00:03.1: 100% native mode on irq 165
ide0: BM-DMA at 0x1f040-0x1f047
ide1: BM-DMA at 0x1f048-0x1f04f
hda: IBM DROM00205, ATAPI CD/DVD-ROM drive
hda: MWDMA2 mode selected
ide0 at 0x1f000-0x1f007,0x1f012 on irq 165 (serialized)
ide1 at 0x1f020-0x1f027,0x1f032 on irq 165 (serialized)
ide-gd driver 1.18
ide-cd driver 5.00
ide-cd: hda: ATAPI 24X DVD-ROM drive, 256kB Cache
Uniform CD-ROM driver Revision: 3.20
megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
megasas: 00.00.04.01 Thu July 24 11:41:51 PST 2008
3ware 9000 Storage Controller device driver for Linux v2.26.02.012.
ipr: IBM Power RAID SCSI Device Driver version: 2.4.3 (June 10, 2009)
ipr 0000:41:01.0: Found IOA with IRQ: 167
ipr 0000:41:01.0: Starting IOA initialization sequence.
ipr 0000:41:01.0: Adapter firmware version: 070A0011
ipr 0000:41:01.0: IOA initialized.
scsi0 : IBM 570B Storage Adapter
scsi 0:0:3:0: Direct-Access IBM IC35L073UCDY10-0 S2AA PQ: 0 ANSI: 3
scsi 0:0:15:0: Enclosure IBM VSBPD4E1 U4SCSI 4610 PQ: 0 ANSI: 2
scsi: unknown device type 31
scsi 0:255:255:255: No Device IBM 570B001 0150 PQ: 0 ANSI0
st: Version 20081215, fixed bufsize 32768, s/g segs 256
sd 0:0:3:0: Attached scsi generic sg0 type 0
scsi 0:0:15:0: Attached scsi generic sg1 type 13
sd 0:0:3:0: [sda] 143374650 512-byte logical blocks: (73.4 GB/68.3 GiB)
scsi 0:255:255:255: Attached scsi generic sg2 type 31
sd 0:0:3:0: [sda] Write Protect is off
sd 0:0:3:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DA
console [netcon0] enabled
netconsole: network logging started
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
ohci_hcd 0001:31:01.0: OHCI Host Controller
ohci_hcd 0001:31:01.0: new USB bus registered, assigned bus number 1
ohci_hcd 0001:31:01.0: irq 182, io mem 0x3fdd5001000
sda: sda1 sda2 sda3 sda4 < sda5 sda6 >
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
ohci_hcd 0001:31:01.1: OHCI Host Controller
ohci_hcd 0001:31:01.1: new USB bus registered, assigned bus number 2
sd 0:0:3:0: [sda] Attached SCSI disk
ohci_hcd 0001:31:01.1: irq 182, io mem 0x3fdd5000000
usb usb2: configuration #1 chosen from 1 choice
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 1 port detected
uhci_hcd: USB Universal Host Controller Interface driver
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
serio: i8042 KBD port at 0x60,0x64 irq 1
serio: i8042 AUX port at 0x60,0x64 irq 12
mice: PS/2 mouse device common for all mice
device-mapper: ioctl: 4.15.0-ioctl (2009-04-01) initialised: dm-devel@redhat.com
atkbd.c: keyboard reset failed on isa0060/serio0
usbcore: registered new interface driver hiddev
atkbd.c: keyboard reset failed on isa0060/serio1
usbcore: registered new interface driver usbhid
usbhid: v2.6:USB HID core driver
TCP cubic registered
NET: Registered protocol family 10
NET: Registered protocol family 17
md: Waiting for all devices to be available before autodetect
md: If you don't use raid, use raid=noautodetect
md: Autodetecting RAID arrays.
md: Scanned 0 and added 0 devices.
md: autorun ...
md: ... autorun DONE.
VFS: Mounted root (iso9660 filesystem) readonly on device 3:0.
Freeing unused kernel memory: 328k freed
INIT: version 2.86 booting
The system is coming up. Please wait.
Intel(R) PRO/1000 Network Driver - version 7.3.21-k5-NAPI
e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
e100: Copyright(c) 1999-2006 Intel Corporation
e100 0000:21:01.0: enabling device (0140 -> 0143)
e100 0000:21:01.0: PME# disabled
e100: eth0: e100_probe: addr 0x3fd88030000, irq 166, MAC addr 00:09:6b:2e:ab:53
Copyright (c) 1999-2006 Intel Corporation.
e1000 0001:41:01.0: enabling device (0140 -> 0143)
e1000: 0001:41:01.0: e1000_probe: (PCI-X:133MHz:64-bit) 00:09:6b:be:a8:77
e1000: eth1: e1000_probe: Intel(R) PRO/1000 Network Connection
INIT: Entering runlevel: 2
CRUX PPC (64bit) (ttyS0)
(none) login:
cheers,
--nico
--
acrux <acrux_it@libero.it>
^ permalink raw reply
* Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to support large-page Nand chip
From: Scott Wood @ 2011-12-07 19:11 UTC (permalink / raw)
To: LiuShuo
Cc: Artem.Bityutskiy, linuxppc-dev, linux-kernel, shuo.liu, linux-mtd,
akpm, dwmw2
In-Reply-To: <4EDEE3AC.7060000@freescale.com>
On 12/06/2011 09:55 PM, LiuShuo wrote:
> =E4=BA=8E 2011=E5=B9=B412=E6=9C=8807=E6=97=A5 08:09, Scott Wood =E5=86=99=
=E9=81=93:
>> On 12/03/2011 10:31 PM, shuo.liu@freescale.com wrote:
>>> From: Liu Shuo<shuo.liu@freescale.com>
>>>
>>> Freescale FCM controller has a 2K size limitation of buffer RAM. In
>>> order
>>> to support the Nand flash chip whose page size is larger than 2K byte=
s,
>>> we read/write 2k data repeatedly by issuing FIR_OP_RB/FIR_OP_WB and s=
ave
>>> them to a large buffer.
>>>
>>> Signed-off-by: Liu Shuo<shuo.liu@freescale.com>
>>> ---
>>> v3:
>>> -remove page_size of struct fsl_elbc_mtd.
>>> -do a oob write by NAND_CMD_RNDIN.
>>>
>>> drivers/mtd/nand/fsl_elbc_nand.c | 243
>>> ++++++++++++++++++++++++++++++++++----
>>> 1 files changed, 218 insertions(+), 25 deletions(-)
>> What is the plan for bad block marker migration?
> This patch has been ported to uboot now, I think we can make a special
> uboot image for bad
> block marker migration when first use the chip.
It should not be a special image, and there should be some way to mark
that the migration has happened. Even if we do the migration in U-Boot,
Linux could check for the marker and if absent, disallow access and tell
the user to run the migration tool.
>>> @@ -473,13 +568,72 @@ static void fsl_elbc_cmdfunc(struct mtd_info
>>> *mtd, unsigned int command,
>>> * write so the HW generates the ECC.
>>> */
>>> if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column !=3D 0 ||
>>> - elbc_fcm_ctrl->index !=3D mtd->writesize + mtd->oobsize)
>>> - out_be32(&lbc->fbcr,
>>> - elbc_fcm_ctrl->index - elbc_fcm_ctrl->column);
>>> - else
>>> + elbc_fcm_ctrl->index !=3D mtd->writesize + mtd->oobsize)=
{
>>> + if (elbc_fcm_ctrl->oob&& mtd->writesize> 2048) {
>>> + out_be32(&lbc->fbcr, 64);
>>> + } else {
>>> + out_be32(&lbc->fbcr, elbc_fcm_ctrl->index
>>> + - elbc_fcm_ctrl->column);
>>> + }
>> We need to limit ourselves to the regions that have actually been
>> written to in the buffer. fbcr needs to be set separately for first a=
nd
>> last subpages, with intermediate subpages having 0, 64, or 2112 as
>> appropriate. Subpages that are entirely before column or entirely aft=
er
>> column + index should be skipped.
>=20
> I have considered this case, but I don't think it is useful.
> 1.There isn't a 'length' parameter in driver interface, although we
> can get it from 'index - column'.
Right. column is start, and index is end + 1. We have the bounds of
what has been written.
> 2.To see nand_do_write_oob() in nand_base.c, it fill '0xff' to
> entire oob area first and write the user data by nand_fill_oob(), then
> call ecc.write_oob (default is nand_write_oob_std()).
Do we really want to assume that that's what it will always do?
And if we do want to make such assumptions, we could rip out all usage
of index/column here, and just handle "oob" and "full page" cases.
-Scott
^ permalink raw reply
* Re: [PATCH 1/2] [hw-breakpoint] Use generic hw-breakpoint interfaces for new PPC ptrace flags
From: Thiago Jung Bauermann @ 2011-12-07 19:01 UTC (permalink / raw)
To: prasad; +Cc: linuxppc-dev, Edjunior Barbosa Machado, David Gibson
In-Reply-To: <20111201102000.GB2632@in.ibm.com>
On Thu, 2011-12-01 at 15:50 +0530, K.Prasad wrote:
> On Mon, Nov 28, 2011 at 02:11:11PM +1100, David Gibson wrote:
> > [snip]
> > On Wed, Oct 12, 2011 at 11:09:48PM +0530, K.Prasad wrote:
> > > diff --git a/Documentation/powerpc/ptrace.txt b/Documentation/powerpc/ptrace.txt
> > > index f4a5499..f2a7a39 100644
> > > --- a/Documentation/powerpc/ptrace.txt
> > > +++ b/Documentation/powerpc/ptrace.txt
> > > @@ -127,6 +127,22 @@ Some examples of using the structure to:
> > > p.addr2 = (uint64_t) end_range;
> > > p.condition_value = 0;
> > >
> > > +- set a watchpoint in server processors (BookS)
> > > +
> > > + p.version = 1;
> > > + p.trigger_type = PPC_BREAKPOINT_TRIGGER_RW;
> > > + p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
> > > + or
> > > + p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
> > > +
> > > + p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
> > > + p.addr = (uint64_t) begin_range;
> >
> > You should probably document the alignment constraint on the address
> > here, too.
> >
>
> Alignment constraints will be learnt by the user-space during runtime.
> We provide that as part of 'struct ppc_debug_info' in
> 'data_bp_alignment' field.
>
> While the alignment is always 8-bytes for BookS, I think userspace
> should be left to learn it through PTRACE_PPC_GETHWDEBUGINFO.
Right. In particular, BookE doesn't have alignment constraints.
> > > + attr.bp_len = len;
> > > + ret = modify_user_hw_breakpoint(bp, &attr);
> > > + if (ret) {
> > > + ptrace_put_breakpoints(child);
> > > + return ret;
> > > + }
> >
> > If a bp already exists, you're modifying it. I thought the semantics
> > of the new interface meant that you shoul return ENOSPC in this case,
> > and a DEL would be necessary before adding another breakpoint.
> >
>
> I'm not too sure what would be the desired behaviour for this interface,
> either way is fine with me. I'd like to hear from the GDB folks (copied
> in this email) to know what would please them.
ENOSPC should be returned. The interface doesn't have provisions for
modifying breakpoints. The client should delete/create instead of trying
to modify.
Since PTRACE_PPC_GETHWDEBUGINFO returns the number of available
breakpoint registers, the client shouldn't (and GDB doesn't) try to set
more breakpoints than possible.
> > > @@ -1426,10 +1488,24 @@ static long ppc_del_hwdebug(struct task_struct *child, long addr, long data)
> > > #else
> > > if (data != 1)
> > > return -EINVAL;
> > > +
> > > +#ifdef CONFIG_HAVE_HW_BREAKPOINT
> > > + if (ptrace_get_breakpoints(child) < 0)
> > > + return -ESRCH;
> > > +
> > > + bp = thread->ptrace_bps[0];
> > > + if (bp) {
> > > + unregister_hw_breakpoint(bp);
> > > + thread->ptrace_bps[0] = NULL;
> > > + }
> > > + ptrace_put_breakpoints(child);
> > > + return 0;
> >
> > Shouldn't DEL return an error if there is no existing bp.
> >
>
> Same comment as above. We'd like to know what behaviour would help the
> GDB use this interface better as there's no right or wrong way here.
GDB expects DEL to return ENOENT is there's no existing bp.
--
[]'s
Thiago Jung Bauermann
IBM Linux Technology Center
^ permalink raw reply
* [PATCH] powerpc: Fix swiotlb ops for ppc64
From: Kumar Gala @ 2011-12-07 17:19 UTC (permalink / raw)
To: linuxppc-dev
We assumed before that alloc_coherent & free_coherent ops would always
be direct because of 32-bit systems and how we utilize highmem & lowmem.
However, on 64-bit systems we typically treat all memory as lowmem so
the same assumptions are not valid. We need to utilze the swiotlb
versions of alloc_coherent & free_coherent on 64-bit systems.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/kernel/dma-swiotlb.c | 9 +++++++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index 1ebc918..5000fd4 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -40,15 +40,20 @@ static u64 swiotlb_powerpc_get_required(struct device *dev)
}
/*
- * At the moment, all platforms that use this code only require
- * swiotlb to be used if we're operating on HIGHMEM. Since
+ * We assume that 32-bit systems will utilize HIGHMEM and that we're
+ * able to DMA directly to anything in the LOWMEM region. Since
* we don't ever call anything other than map_sg, unmap_sg,
* map_page, and unmap_page on highmem, use normal dma_ops
* for everything else.
*/
struct dma_map_ops swiotlb_dma_ops = {
+#ifdef CONFIG_PPC64
+ .alloc_coherent = swiotlb_alloc_coherent,
+ .free_coherent = swiotlb_free_coherent,
+#else
.alloc_coherent = dma_direct_alloc_coherent,
.free_coherent = dma_direct_free_coherent,
+#endif
.map_sg = swiotlb_map_sg_attrs,
.unmap_sg = swiotlb_unmap_sg_attrs,
.dma_supported = swiotlb_dma_supported,
--
1.7.3.4
^ permalink raw reply related
* Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller
From: Scott Wood @ 2011-12-07 17:17 UTC (permalink / raw)
To: Liu Shengzhou-B36685
Cc: Wood Scott-B07421, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org,
linux-mtd@lists.infradead.org
In-Reply-To: <3F453DDFF675A64A89321A1F352810216B0787@039-SN1MPN1-005.039d.mgd.msft.net>
On 12/07/2011 12:30 AM, Liu Shengzhou-B36685 wrote:
>
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Wednesday, December 07, 2011 1:16 AM
>> To: Liu Shengzhou-B36685
>> Cc: linuxppc-dev@lists.ozlabs.org; linux-mtd@lists.infradead.org;
>> dwmw2@infradead.org; Gala Kumar-B11780
>> Subject: Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of
>> Freescale NAND controller
>>
>> On 12/06/2011 02:54 AM, Shengzhou Liu wrote:
>>> There was a bug for fmr initialization, which lead to fmr was always
>>> 0x100 in fsl_elbc_chip_init() and caused FCM command timeout before
>>> calling fsl_elbc_chip_init_tail(), now we initialize CWTO to maximum
>>> timeout value and not relying on the setting of bootloader.
>>>
>>> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
>>> ---
>>> v2: make fmr not relying on the setting of bootloader.
>>>
>>> drivers/mtd/nand/fsl_elbc_nand.c | 10 +++++-----
>>> 1 files changed, 5 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/mtd/nand/fsl_elbc_nand.c
>>> b/drivers/mtd/nand/fsl_elbc_nand.c
>>> index eedd8ee..4f405a0 100644
>>> --- a/drivers/mtd/nand/fsl_elbc_nand.c
>>> +++ b/drivers/mtd/nand/fsl_elbc_nand.c
>>> @@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info
>> *mtd)
>>> if (chip->pagemask & 0xff000000)
>>> al++;
>>>
>>> - /* add to ECCM mode set in fsl_elbc_init */
>>> - priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
>>> - (al << FMR_AL_SHIFT);
>>> + priv->fmr |= al << FMR_AL_SHIFT;
>>>
>>> dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
>>> chip->numchips);
>>> @@ -764,8 +762,10 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd
>> *priv)
>>> priv->mtd.priv = chip;
>>> priv->mtd.owner = THIS_MODULE;
>>>
>>> - /* Set the ECCM according to the settings in bootloader.*/
>>> - priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM;
>>> + /* set timeout to maximum */
>>> + priv->fmr = 15 << FMR_CWTO_SHIFT;
>>> + if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
>>> + priv->fmr |= FMR_ECCM;
>>
>> Please do not change the way ECCM is handled. We probably should have
>> done it this way from the start, but at this point it breaks
>> compatibility if you have a large page flash and the firmware didn't
>> touch NAND.
>>
>> -Scott
> [Shengzhou] This patch doesn't change the way ECCM is handled, it's still same as before, just make sure CWTO timeout is set to maximum.
It does change it. It used to use the existing value in FMR, and now it
sets it based on ORn[PGS].
-Scott
^ permalink raw reply
* Re: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller
From: Scott Wood @ 2011-12-07 17:16 UTC (permalink / raw)
To: Liu Shengzhou-B36685
Cc: Wood Scott-B07421, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org,
linux-mtd@lists.infradead.org
In-Reply-To: <3F453DDFF675A64A89321A1F352810216B074A@039-SN1MPN1-005.039d.mgd.msft.net>
On 12/06/2011 09:16 PM, Liu Shengzhou-B36685 wrote:
>>> + out_be32(&lbc->fbcr, 8);
>>> + elbc_fcm_ctrl->read_bytes = 8;
>>> + } else {
>>> + out_be32(&lbc->fbcr, 256);
>>> + elbc_fcm_ctrl->read_bytes = 256;
>>> + }
>>
>> Any harm in always using 256?
>>
>> -Scott
> [Shengzhou] For NAND_CMD_READID command, the total bytes of entire ID string are 8, there are not 256 bytes so many, it's unnecessary and looks not so well logically to always using 256, though it works.
It's not performance critical, and always using 256 keeps things
simpler, and more robust if the length of the ID string grows in the
future (we used to assume it was 5 bytes...).
-Scott
^ permalink raw reply
* Re: [linuxppc-release] [powerpc] boot up problem
From: Timur Tabi @ 2011-12-07 15:13 UTC (permalink / raw)
To: Jia Hongtao-B38951
Cc: Fleming Andy-AFLEMING, linuxppc-dev@lists.ozlabs.org,
Li Yang-R58472
In-Reply-To: <412C8208B4A0464FA894C5F0C278CD5DFE170A@039-SN1MPN1-005.039d.mgd.msft.net>
On Dec 7, 2011, at 1:27 AM, Jia Hongtao-B38951 <B38951@freescale.com> wrote:=
> Is this the patch you mentioned?
> http://patchwork.ozlabs.org/patch/128806/
>=20
> I applied this patch but the issue was still there.
This is not the patch I am talking about. Unfortunately, I can't find the r=
ight patch in patchwork anywhere.
Andy, what about patch "fsl_pq_mdio: Clean up tbi address configuration"? =20=
^ permalink raw reply
* Multi-OS on P1022RDK Failing
From: Arshad, Farrukh @ 2011-12-07 14:57 UTC (permalink / raw)
To: Linuxppc-dev@lists.ozlabs.org
[-- Attachment #1.1: Type: text/plain, Size: 3265 bytes --]
Greetings All,
I am trying to boot multi-OS on P1022RDK platform. As per my understating I only need to partition peripherals in DTS file of both kernels and configure memory start address of the kernel and load each kernel from uboot. No specific kernel configuration is required or any specific patch is required for this.
Given is my configuration
Core0: Linux kernel 1
Core1: Linux kernel 2
I compiled two different kernels with following configuration (rest is default for P1022RDK comes in LTIB)
Core 0 kernel
CONFIG_LOWMEM_SIZE = 0x10000000
CONFIG_PHYSICAL_START = 0x00000000
Core 1 kernel
CONFIG_LOWMEM_SIZE = 0x10000000
CONFIG_PHYSICAL_START = 0x10000000
In the DTS file I have partitioned peripherals & cpu to each kernel. Cpu 0 to Core 0 kernel & cpu 1 to Core 1 kernel and compiled DTS file with -b 1 switch of Core 1 DTB. My DTS files are attached. Given is my Uboot script which I am using to boot both cores.
-------------- Uboot load script -----------------
# General environment setting
setenv consoledev0 ttyS0
# Set kernel loading environment
setenv core1kernelbase 0x00000000
setenv core0kernelbase 0x10000000
setenv kernelsize 0x10000000
setenv kerneloffset 0x1000000
setenv fdtoffset 0x00c00000
setexpr load0addr $core0kernelbase + $kerneloffset
setexpr fdt0addr $core0kernelbase + $fdtoffset
setexpr load1addr $core1kernelbase + $kerneloffset
setexpr fdt1addr $core1kernelbase + $fdtoffset
setenv core0kernel uImage-custom-mel-p1022rdk-core0.bin
setenv core1kernel uImage-custom-ltib-p1022rdk-core1.bin
setenv core0fdt p1022rdk-core0.dtb
setenv core1fdt p1022rdk-core1.dtb
setenv core0rootfs /home/farshad/melfs/core0
setenv core1rootfs /home/farshad/melfs/core1
# Boot from NFS
setenv core0nfsbootargs root=/dev/nfs nfsroot=$serverip:/$core0rootfs ip=<dev_ip>::<nfs_server_ip>:::eth0:off rw debug console=$consoledev0,$baudrate maxcpus=1
setenv core1nfsbootargs root=/dev/nfs nfsroot=$serverip:/$core1rootfs ip=<dev_ip_2>::<nfs_server_ip>:::eth0:off rw debug console=$consoledev0,$baudrate maxcpus=1
echo == Transfer images on board ==
tftp $load0addr $core0kernel
tftp $fdt0addr $core0fdt
tftp $load1addr $core1kernel
tftp $fdt1addr $core1fdt
echo == Start loading Core 1 with LTIB Kernel ==
setenv bootm_low $core1kernelbase
setenv bootm_size $kernelsize
setenv bootargs $core1nfsbootargs
interrupts off
bootm start $load1addr - $fdt1addr
bootm loados
bootm fdt
fdt boardsetup
fdt chosen
bootm prep
cpu 1 release $load1addr - $fdt1addr -
echo == Start loading Core 0 with MEL Kernel ==
setenv bootargs $core0nfsbootargs
setenv bootm_low $core0kernelbase
setenv bootm_size $kernelsize
bootm $load0addr - $fdt0addr
-------------- Uboot load script ends -----------------
My problem is Core 0 kernel is booting successfully but Core 1 kernel hangs after uncompressing kernel image, and after that I don't see anything on the console.
Any thoughts on what I am missing or doing incorrect?
Best Regards
Farrukh Arshad
Sr. Software Development Engineer
Mentor Graphics Pakistan
Ph: +92 - 423 - 609 - 92 - 09
Cell: +92 - 303 - 444 - 77 - 05
[-- Attachment #1.2: Type: text/html, Size: 12063 bytes --]
[-- Attachment #2: p1022rdk-core0.dts --]
[-- Type: application/octet-stream, Size: 15610 bytes --]
/*
* P1022 RDK - Core 0 Device Tree Source
*
*/
/dts-v1/;
/ {
model = "fsl,P1022";
compatible = "fsl,P1022DS";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &enet0;
serial0 = &serial1;
msgr-block0 = &msgr_block0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P1022@0 {
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
};
mcomm {
compatible = "ment,mcomm";
//reg = <0 0x70000000 0 0x10000000>;
//reg = <0 0x18000000 0 0x080000000>;
reg = <0 0x18000000 0 0x008000000>;
notifications = <
1 1 // Core 1, Msg Reg 1
0 0 // Core 0, Msg Reg 0
>;
};
//localbus@ffe05000 {
// #address-cells = <2>;
// #size-cells = <1>;
// compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
// reg = <0 0xffe05000 0 0x1000>;
// interrupts = <19 2>;
// interrupt-parent = <&mpic>;
// ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
// 0x1 0x0 0x0 0xe0000000 0x08000000
// 0x2 0x0 0x0 0xffa00000 0x00040000
// 0x3 0x0 0x0 0xffdf0000 0x00008000>;
// nor@0,0 {
// #address-cells = <1>;
// #size-cells = <1>;
// compatible = "cfi-flash";
// reg = <0x0 0x0 0x8000000>;
// bank-width = <2>;
// device-width = <1>;
// partition@0 {
// reg = <0x0 0x03000000>;
// label = "ramdisk-nor";
// read-only;
// };
// partition@3000000 {
// reg = <0x03000000 0x00e00000>;
// label = "diagnostic-nor";
// read-only;
// };
// partition@3e00000 {
// reg = <0x03e00000 0x00200000>;
// label = "dink-nor";
// read-only;
// };
// partition@4000000 {
// reg = <0x04000000 0x00400000>;
// label = "kernel-nor";
// read-only;
// };
// partition@4400000 {
// reg = <0x04400000 0x03b00000>;
// label = "jffs2-nor";
// };
// partition@7f00000 {
// reg = <0x07f00000 0x00080000>;
// label = "dtb-nor";
// read-only;
// };
// partition@7f80000 {
// reg = <0x07f80000 0x00080000>;
// label = "u-boot-nor";
// read-only;
// };
// };
// nand@2,0 {
// #address-cells = <1>;
// #size-cells = <1>;
// compatible = "fsl,elbc-fcm-nand";
// reg = <0x2 0x0 0x40000>;
// partition@0 {
// reg = <0x0 0x02000000>;
// label = "u-boot-nand";
// read-only;
// };
// partition@2000000 {
// reg = <0x02000000 0x10000000>;
// label = "jffs2-nand";
// };
// partition@12000000 {
// reg = <0x12000000 0x10000000>;
// label = "ramdisk-nand";
// read-only;
// };
// partition@22000000 {
// reg = <0x22000000 0x04000000>;
// label = "kernel-nand";
// };
// partition@26000000 {
// reg = <0x26000000 0x01000000>;
// label = "dtb-nand";
// read-only;
// };
// partition@27000000 {
// reg = <0x27000000 0x19000000>;
// label = "reserved-nand";
// };
// };
//};
soc@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p1022-immr", "simple-bus";
ranges = <0x0 0 0xffe00000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
//ecm-law@0 {
// compatible = "fsl,ecm-law";
// reg = <0x0 0x1000>;
// fsl,num-laws = <12>;
//};
//ecm@1000 {
// compatible = "fsl,p1022-ecm", "fsl,ecm";
// reg = <0x1000 0x1000>;
// interrupts = <16 2>;
// interrupt-parent = <&mpic>;
//};
//memory-controller@2000 {
// compatible = "fsl,p1022-memory-controller";
// reg = <0x2000 0x1000>;
// interrupt-parent = <&mpic>;
// interrupts = <16 2>;
//};
//i2c@3000 {
// #address-cells = <1>;
// #size-cells = <0>;
// cell-index = <0>;
// compatible = "fsl-i2c";
// reg = <0x3000 0x100>;
// interrupts = <43 2>;
// interrupt-parent = <&mpic>;
// dfsrr;
//};
//ssi@15000 {
// compatible = "fsl,p1022-ssi";
// cell-index = <0>;
// reg = <0x15000 0x100>;
// interrupt-parent = <&mpic>;
// interrupts = <75 2>;
// fsl,mode = "i2s-slave";
// codec-handle = <&wm8776>;
// fsl,playback-dma = <&dma00>;
// fsl,capture-dma = <&dma01>;
// fsl,fifo-depth = <15>;
// fsl,ssi-asynchronous = <1>;
//};
//i2c@3100 {
// #address-cells = <1>;
// #size-cells = <0>;
// cell-index = <1>;
// compatible = "fsl-i2c";
// reg = <0x3100 0x100>;
// interrupts = <43 2>;
// interrupt-parent = <&mpic>;
// dfsrr;
// rtc@68{
// compatible = "dallas,ds3232";
// reg = <0x68>;
// interrupts = <16 0x2>;
// interrupt-parent = <&mpic>;
// };
// adt7461@4c{
// compatible = "adi,adt7461";
// reg = <0x4c>;
// };
// zl6100@21{
// compatible = "intersil,zl6100";
// reg = <0x21>;
// };
// zl6100@24{
// compatible = "intersil,zl6100";
// reg = <0x24>;
// };
// zl6100@26{
// compatible = "intersil,zl6100";
// reg = <0x26>;
// };
// zl6100@29{
// compatible = "intersil,zl6100";
// reg = <0x29>;
// };
// wm8776:codec@1a {
// compatible = "wolfson,wm8776";
// reg = <0x1a>;
// clock-frequency = <0xbb8000>;
// };
//};
//serial0: serial@4500 {
// cell-index = <0>;
// device_type = "serial";
// compatible = "ns16550";
// reg = <0x4500 0x100>;
// clock-frequency = <0>;
// interrupts = <42 2>;
// interrupt-parent = <&mpic>;
//};
serial1: serial@4600 {
cell-index = <1>;
device-type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
//spi@7000 {
// cell-index = <0>;
// #address-cells = <1>;
// #size-cells = <0>;
// compatible = "fsl,espi";
// reg = <0x7000 0x1000>;
// interrupts = <59 0x2>;
// interrupt-parent = <&mpic>;
// espi,num-ss-bits = <4>;
// mode = "cpu";
// fsl_m25p80@0 {
// #address-cells = <1>;
// #size-cells = <1>;
// compatible = "fsl,espi-flash";
// reg = <0>;
// linux,modalias = "fsl_m25p80";
// spi-max-frequency = <40000000>; /* input clock */
// partition@0 {
// label = "u-boot-spi";
// reg = <0x00000000 0x00100000>;
// read-only;
// };
// partition@100000 {
// label = "kernel-spi";
// reg = <0x00100000 0x00500000>;
// read-only;
// };
// partition@600000 {
// label = "dtb-spi";
// reg = <0x00600000 0x00100000>;
// read-only;
// };
// partition@700000 {
// label = "file system-spi";
// reg = <0x00700000 0x00900000>;
// };
// };
//};
//gpio: gpio-controller@f000 {
// #gpio-cells = <2>;
// compatible = "fsl,mpc8572-gpio";
// reg = <0xf000 0x100>;
// interrupts = <47 0x2>;
// interrupt-parent = <&mpic>;
// gpio-controller;
//};
L2: l2-cache-controller@20000 {
compatible = "fsl,p1022-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
//dma@21300 {
// #address-cells = <1>;
// #size-cells = <1>;
// compatible = "fsl,eloplus-dma";
// reg = <0x21300 0x4>;
// ranges = <0x0 0x21100 0x200>;
// cell-index = <0>;
// dma00: dma-channel@0 {
// compatible = "fsl,ssi-dma-channel";
// reg = <0x0 0x80>;
// cell-index = <0>;
// interrupt-parent = <&mpic>;
// interrupts = <20 2>;
// };
// dma01: dma-channel@80 {
// compatible = "fsl,ssi-dma-channel";
// reg = <0x80 0x80>;
// cell-index = <1>;
// interrupt-parent = <&mpic>;
// interrupts = <21 2>;
// };
// dma-channel@100 {
// compatible = "fsl,eloplus-dma-channel";
// reg = <0x100 0x80>;
// cell-index = <2>;
// interrupt-parent = <&mpic>;
// interrupts = <22 2>;
// };
// dma-channel@180 {
// compatible = "fsl,eloplus-dma-channel";
// reg = <0x180 0x80>;
// cell-index = <3>;
// interrupt-parent = <&mpic>;
// interrupts = <23 2>;
// };
//};
//usb@22000 {
// #address-cells = <1>;
// #size-cells = <0>;
// compatible = "fsl-usb2-dr";
// reg = <0x22000 0x1000>;
// interrupt-parent = <&mpic>;
// interrupts = <28 0x2>;
// phy_type = "ulpi";
//};
mdio@24000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x24000 0x1000 0xb0030 0x4>;
phy0: ethernet-phy@0 {
interrupts = <3 1>;
reg = <0x1>;
};
//phy1: ethernet-phy@1 {
// interrupts = <9 1>;
// reg = <0x2>;
//};
};
//mdio@25000 {
// #address-cells = <1>;
// #size-cells = <0>;
// compatible = "fsl,etsec2-mdio";
// reg = <0x25000 0x1000 0xb1030 0x4>;
//};
enet0: ethernet@B0000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
fsl,magic-packet;
fsl,wake-on-filer;
clk-handle = <&etsec1_clk>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
queue-group@0{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB0000 0x1000>;
interrupts = <29 2 30 2 34 2>;
};
queue-group@1{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB4000 0x1000>;
interrupts = <17 2 18 2 24 2>;
};
};
//sdhci@2e000 {
// compatible = "fsl,p1022-esdhc", "fsl,esdhc";
// reg = <0x2e000 0x1000>;
// interrupts = <72 0x2>;
// interrupt-parent = <&mpic>;
// fsl,sdhci-auto-cmd12;
// /* Filled in by U-Boot */
// clock-frequency = <0>;
//};
//crypto@30000 {
// compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
// "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
// reg = <0x30000 0x10000>;
// interrupts = <45 2 58 2>;
// interrupt-parent = <&mpic>;
// fsl,num-channels = <4>;
// fsl,channel-fifo-len = <24>;
// fsl,exec-units-mask = <0xbfe>;
// fsl,descriptor-types-mask = <0x3ab0ebf>;
// fsl,multi-host-mode = "primary";
// fsl,channel-remap = <0x3>;
//};
//sata@18000 {
// compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
// reg = <0x18000 0x1000>;
// cell-index = <1>;
// interrupts = <74 0x2>;
// interrupt-parent = <&mpic>;
//};
//sata@19000 {
// compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
// reg = <0x19000 0x1000>;
// cell-index = <2>;
// interrupts = <41 0x2>;
// interrupt-parent = <&mpic>;
//};
//display@10000 {
// compatible = "fsl,diu", "fsl,p1022-diu";
// reg = <0x10000 1000>;
// interrupts = <64 2>;
// interrupt-parent = <&mpic>;
//};
power@e0070{
compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
"fsl,p1022-pmc";
reg = <0xe0070 0x20>;
etsec1_clk: soc-clk@B0{
fsl,pmcdr-mask = <0x00000080>;
};
etsec2_clk: soc-clk@B1{
fsl,pmcdr-mask = <0x00000040>;
};
};
//timer@41100 {
// compatible = "fsl,mpic-global-timer";
// reg = <0x41100 0x204>;
// interrupts = <0xf7 0x2>;
// interrupt-parent = <&mpic>;
//};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
pic-no-reset;
protected-sources = <
19 // localbus@ffe0500
42 // serial@4600
16 // ecm@1000
// memory-controller@20000
// rtc@68
43 // i2c@3000, i2c@3100
75 // ssi@15000
59 // spi@7000
47 // gpio@f000
20 // dma-channel@0
21 // dma-channel@80
22 // dma-channel@100
23 // dma-channel@180
28 // usb@22000
9 // ethernet-phy@1
35 36 40 // queue-group@0
51 52 67 // queue-group@1
58 // crypto@30000
41 // sata@19000
74 // sata@18000
64 // display@10000
0xF7 // timer@41100
0xb1 // message@41400
16 // pci@ffe09000
// pci@ffe0a000
// pci@ffe0b000
0xe0 0xe1 0xe2 0xe3 // msi@41600
>;
};
msgr_block0: message@41400 {
compatible = "fsl,p1022-msg","fsl,mpic-msg",
"fsl,mpic-v3.1-msgr";
reg = <0x41400 0x200>;
cell-index = <1>;
interrupts = <0xb0 2 0xb2 2 0xb3 2>;
msg-receive-mask = <0xd>;
interrupt-parent = < &mpic >;
};
//msgr_block0: message@41400 {
// compatible = "fsl,p1022-msg","fsl,mpic-msg",
// "fsl,mpic-v3.1-msgr";
// reg = <0x41400 0x200>;
// interrupts = <0xb0 0x2 0xb1 0x2 0xb2 0x2 0xb3 2>;
// interrupt-parent = < &mpic >;
//};
//msi@41600 {
// compatible = "fsl,mpic-msi";
// reg = <0x41600 0x80>;
// msi-available-ranges = <0 0x100>;
// interrupts = <
// 0xe0 0
// 0xe1 0
// 0xe2 0
// 0xe3 0
// 0xe4 0
// 0xe5 0
// 0xe6 0
// 0xe7 0>;
// interrupt-parent = <&mpic>;
//};
//global-utilities@e0000 { //global utilities block
// compatible = "fsl,p1022-guts";
// reg = <0xe0000 0x1000>;
// fsl,has-rstcr;
//};
};
//pci0: pcie@ffe09000 {
// cell-index = <2>;
// compatible = "fsl,p1022-pcie";
// device_type = "pci";
// #interrupt-cells = <1>;
// #size-cells = <2>;
// #address-cells = <3>;
// reg = <0 0xffe09000 0 0x1000>;
// bus-range = <0 255>;
// ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
// 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
// clock-frequency = <33333333>;
// interrupt-parent = <&mpic>;
// interrupts = <16 2>;
// interrupt-map-mask = <0xf800 0 0 7>;
// interrupt-map = <
// /* IDSEL 0x0 */
// 0000 0 0 1 &mpic 4 1
// 0000 0 0 2 &mpic 5 1
// 0000 0 0 3 &mpic 6 1
// 0000 0 0 4 &mpic 7 1
// >;
// pcie@0 {
// reg = <0x0 0x0 0x0 0x0 0x0>;
// #size-cells = <2>;
// #address-cells = <3>;
// device_type = "pci";
// ranges = <0x2000000 0x0 0xa0000000
// 0x2000000 0x0 0xa0000000
// 0x0 0x20000000
// 0x1000000 0x0 0x0
// 0x1000000 0x0 0x0
// 0x0 0x100000>;
// };
//};
//pci1: pcie@ffe0a000 {
// cell-index = <1>;
// compatible = "fsl,p1022-pcie";
// device_type = "pci";
// #interrupt-cells = <1>;
// #size-cells = <2>;
// #address-cells = <3>;
// reg = <0 0xffe0a000 0 0x1000>;
// bus-range = <0 255>;
// ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
// 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
// clock-frequency = <33333333>;
// interrupt-parent = <&mpic>;
// interrupts = <16 2>;
// interrupt-map-mask = <0xf800 0 0 7>;
// interrupt-map = <
// /* IDSEL 0x0 */
// 0000 0 0 1 &mpic 0 1
// 0000 0 0 2 &mpic 1 1
// 0000 0 0 3 &mpic 2 1
// 0000 0 0 4 &mpic 3 1
// >;
// pcie@0 {
// reg = <0x0 0x0 0x0 0x0 0x0>;
// #size-cells = <2>;
// #address-cells = <3>;
// device_type = "pci";
// ranges = <0x2000000 0x0 0xc0000000
// 0x2000000 0x0 0xc0000000
// 0x0 0x20000000
// 0x1000000 0x0 0x0
// 0x1000000 0x0 0x0
// 0x0 0x100000>;
// };
//};
//pci2: pcie@ffe0b000 {
// cell-index = <3>;
// compatible = "fsl,p1022-pcie";
// device_type = "pci";
// #interrupt-cells = <1>;
// #size-cells = <2>;
// #address-cells = <3>;
// reg = <0 0xffe0b000 0 0x1000>;
// bus-range = <0 255>;
// ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
// 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
// clock-frequency = <33333333>;
// interrupt-parent = <&mpic>;
// interrupts = <16 2>;
// interrupt-map-mask = <0xf800 0 0 7>;
// interrupt-map = <
// /* IDSEL 0x0 */
// 0000 0 0 1 &mpic 8 1
// 0000 0 0 2 &mpic 9 1
// 0000 0 0 3 &mpic 10 1
// 0000 0 0 4 &mpic 11 1
// >;
// pcie@0 {
// reg = <0x0 0x0 0x0 0x0 0x0>;
// #size-cells = <2>;
// #address-cells = <3>;
// device_type = "pci";
// ranges = <0x2000000 0x0 0x80000000
// 0x2000000 0x0 0x80000000
// 0x0 0x20000000
// 0x1000000 0x0 0x0
// 0x1000000 0x0 0x0
// 0x0 0x100000>;
// };
//};
};
[-- Attachment #3: p1022rdk-core1.dts --]
[-- Type: application/octet-stream, Size: 15964 bytes --]
/*
* P1022 RDK - Core 1 Device Tree Source
*
*/
/dts-v1/;
/ {
model = "fsl,P1022";
compatible = "fsl,P1022DS";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet1 = &enet1;
serial0 = &serial0;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
//PowerPC,P1022@0 {
// device_type = "cpu";
// reg = <0x0>;
// next-level-cache = <&L2>;
//};
PowerPC,P1022@1 {
device_type = "cpu";
reg = <0x1>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
};
localbus@ffe05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
reg = <0 0xffe05000 0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
0x1 0x0 0x0 0xe0000000 0x08000000
0x2 0x0 0x0 0xffa00000 0x00040000
0x3 0x0 0x0 0xffdf0000 0x00008000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
reg = <0x0 0x03000000>;
label = "ramdisk-nor";
read-only;
};
partition@3000000 {
reg = <0x03000000 0x00e00000>;
label = "diagnostic-nor";
read-only;
};
partition@3e00000 {
reg = <0x03e00000 0x00200000>;
label = "dink-nor";
read-only;
};
partition@4000000 {
reg = <0x04000000 0x00400000>;
label = "kernel-nor";
read-only;
};
partition@4400000 {
reg = <0x04400000 0x03b00000>;
label = "jffs2-nor";
};
partition@7f00000 {
reg = <0x07f00000 0x00080000>;
label = "dtb-nor";
read-only;
};
partition@7f80000 {
reg = <0x07f80000 0x00080000>;
label = "u-boot-nor";
read-only;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,elbc-fcm-nand";
reg = <0x2 0x0 0x40000>;
partition@0 {
reg = <0x0 0x02000000>;
label = "u-boot-nand";
read-only;
};
partition@2000000 {
reg = <0x02000000 0x10000000>;
label = "jffs2-nand";
};
partition@12000000 {
reg = <0x12000000 0x10000000>;
label = "ramdisk-nand";
read-only;
};
partition@22000000 {
reg = <0x22000000 0x04000000>;
label = "kernel-nand";
};
partition@26000000 {
reg = <0x26000000 0x01000000>;
label = "dtb-nand";
read-only;
};
partition@27000000 {
reg = <0x27000000 0x19000000>;
label = "reserved-nand";
};
};
};
soc@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p1022-immr", "simple-bus";
ranges = <0x0 0 0xffe00000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,p1022-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <16 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,p1022-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
ssi@15000 {
compatible = "fsl,p1022-ssi";
cell-index = <0>;
reg = <0x15000 0x100>;
interrupt-parent = <&mpic>;
interrupts = <75 2>;
fsl,mode = "i2s-slave";
codec-handle = <&wm8960>;
fsl,playback-dma = <&dma00>;
fsl,capture-dma = <&dma01>;
fsl,fifo-depth = <15>;
fsl,ssi-asynchronous = <1>;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
rtc@68{
compatible = "dallas,ds3232";
reg = <0x68>;
interrupts = <16 0x2>;
interrupt-parent = <&mpic>;
};
adt7461@4c{
compatible = "adi,adt7461";
reg = <0x4c>;
};
zl6100@21{
compatible = "intersil,zl6100";
reg = <0x21>;
};
zl6100@24{
compatible = "intersil,zl6100";
reg = <0x24>;
};
zl6100@26{
compatible = "intersil,zl6100";
reg = <0x26>;
};
zl6100@29{
compatible = "intersil,zl6100";
reg = <0x29>;
};
wm8960:codec@1a {
compatible = "wolfson,wm8960";
reg = <0x1a>;
clock-frequency = <0xbb8000>;
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
//serial1: serial@4600 {
// cell-index = <1>;
// device_type = "serial";
// compatible = "ns16550";
// reg = <0x4600 0x100>;
// clock-frequency = <0>;
// interrupts = <42 2>;
// interrupt-parent = <&mpic>;
//};
spi@7000 {
cell-index = <0>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,espi";
reg = <0x7000 0x1000>;
interrupts = <59 0x2>;
interrupt-parent = <&mpic>;
espi,num-ss-bits = <4>;
mode = "cpu";
fsl_m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,espi-flash";
reg = <0>;
linux,modalias = "fsl_m25p80";
spi-max-frequency = <40000000>; /* input clock */
partition@0 {
label = "u-boot-spi";
reg = <0x00000000 0x00100000>;
read-only;
};
partition@100000 {
label = "kernel-spi";
reg = <0x00100000 0x00500000>;
read-only;
};
partition@600000 {
label = "dtb-spi";
reg = <0x00600000 0x00100000>;
read-only;
};
partition@700000 {
label = "file system-spi";
reg = <0x00700000 0x00900000>;
};
};
};
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0xc300 0x4>;
ranges = <0x0 0xc100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <76 2>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <77 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <78 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <79 2>;
};
};
gpio: gpio-controller@f000 {
#gpio-cells = <2>;
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x100>;
interrupts = <47 0x2>;
interrupt-parent = <&mpic>;
gpio-controller;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,p1022-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
//interrupts = <16 2>;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma00: dma-channel@0 {
compatible = "fsl,ssi-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma01: dma-channel@80 {
compatible = "fsl,ssi-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
usb@22000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x22000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <28 0x2>;
phy_type = "ulpi";
};
usb@23000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <46 0x2>;
phy_type = "ulpi";
};
mdio@24000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x24000 0x1000 0xb0030 0x4>;
//phy0: ethernet-phy@0 {
// interrupt-parent = <&mpic>;
// interrupts = <3 1>;
// reg = <0x1>;
//};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <9 1>;
reg = <0x2>;
};
};
mdio@25000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x25000 0x1000 0xb1030 0x4>;
};
//enet0: ethernet@B0000 {
// #address-cells = <1>;
// #size-cells = <1>;
// cell-index = <0>;
// device_type = "network";
// model = "eTSEC";
// compatible = "fsl,etsec2";
// fsl,num_rx_queues = <0x8>;
// fsl,num_tx_queues = <0x8>;
// fsl,magic-packet;
// fsl,wake-on-filer;
// clk-handle = <&etsec1_clk>;
// local-mac-address = [ 00 00 00 00 00 00 ];
// interrupt-parent = <&mpic>;
// fixed-link = <1 1 1000 0 0>;
// phy-handle = <&phy0>;
// phy-connection-type = "rgmii-id";
// queue-group@0{
// #address-cells = <1>;
// #size-cells = <1>;
// reg = <0xB0000 0x1000>;
// interrupts = <29 2 30 2 34 2>;
// };
// queue-group@1{
// #address-cells = <1>;
// #size-cells = <1>;
// reg = <0xB4000 0x1000>;
// interrupts = <17 2 18 2 24 2>;
// };
//};
enet1: ethernet@B1000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
clk-handle = <&etsec2_clk>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
fixed-link = <1 1 1000 0 0>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
queue-group@0{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB1000 0x1000>;
interrupts = <35 2 36 2 40 2>;
};
queue-group@1{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB5000 0x1000>;
interrupts = <51 2 52 2 67 2>;
};
};
sdhci@2e000 {
compatible = "fsl,p1022-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
fsl,sdhci-auto-cmd12;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
crypto@30000 {
compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
"fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x97c>;
fsl,descriptor-types-mask = <0x3a30abf>;
// fsl,multi-host-mode = "dual";
fsl,channel-remap = <0x3>;
};
sata@18000 {
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
cell-index = <1>;
interrupts = <74 0x2>;
interrupt-parent = <&mpic>;
};
sata@19000 {
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
reg = <0x19000 0x1000>;
cell-index = <2>;
interrupts = <41 0x2>;
interrupt-parent = <&mpic>;
};
display@10000 {
compatible = "fsl,diu", "fsl,p1022-diu";
reg = <0x10000 1000>;
interrupts = <64 2>;
interrupt-parent = <&mpic>;
};
power@e0070{
compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
"fsl,p1022-pmc";
reg = <0xe0070 0x20>;
etsec1_clk: soc-clk@B0{
fsl,pmcdr-mask = <0x00000080>;
};
etsec2_clk: soc-clk@B1{
fsl,pmcdr-mask = <0x00000040>;
};
};
timer@41100 {
compatible = "fsl,mpic-global-timer";
reg = <0x41100 0x204>;
interrupts = <0xf7 0x2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
//compatible = "fsl,mpic";
device_type = "open-pic";
pic-no-reset;
protected-sources = <
16 // l2-cache-controller@20000
3 // ethernet-phy@0
29 30 34 // queue-group@0
17 18 24 // gueue-group@1
42 // serial@4500
>;
};
message@41400 {
compatible = "fsl,p1022-msg","fsl,mpic-msg";
reg = <0x41400 0x200>;
cell-index = <1>;
interrupts = <0xb0 2 0xb1 2 0xb2 2 0xb3 2>;
interrupt-parent = < &mpic >;
};
message@42400 {
compatible = "fsl,p1022-msg","fsl,mpic-msg";
reg = <0x42400 0x200>;
cell-index = <2>;
interrupts = <0xb4 2 0xb5 2 0xb6 2 0xb7 2>;
interrupt-parent = < &mpic >;
};
msi@41600 {
compatible = "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,p1022-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
pci0: pcie@ffe09000 {
cell-index = <2>;
compatible = "fsl,p1022-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe09000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
cell-index = <1>;
compatible = "fsl,p1022-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe0a000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci2: pcie@ffe0b000 {
cell-index = <3>;
compatible = "fsl,p1022-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe0b000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 8 1
0000 0 0 2 &mpic 9 1
0000 0 0 3 &mpic 10 1
0000 0 0 4 &mpic 11 1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
^ permalink raw reply
* Re: [linuxppc-release] [powerpc] boot up problem
From: Kumar Gala @ 2011-12-07 14:53 UTC (permalink / raw)
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org, Fleming Andy-AFLEMING,
Tabi Timur-B04825, Li Yang-R58472
In-Reply-To: <412C8208B4A0464FA894C5F0C278CD5DFE170A@039-SN1MPN1-005.039d.mgd.msft.net>
This still needs a dts fix from Andy.
- k
On Dec 7, 2011, at 1:27 AM, Jia Hongtao-B38951 wrote:
> Is this the patch you mentioned?
> http://patchwork.ozlabs.org/patch/128806/
>=20
> I applied this patch but the issue was still there.
>=20
> -----Original Message-----
> From: Tabi Timur-B04825=20
> Sent: Friday, December 02, 2011 11:56 AM
> To: Jia Hongtao-B38951
> Cc: Kumar Gala; linuxppc-dev@lists.ozlabs.org; Li Yang-R58472; Fleming =
Andy-AFLEMING
> Subject: Re: [linuxppc-release] [powerpc] boot up problem
>=20
> Jia Hongtao-B38951 wrote:
>> Hi
>>=20
>> I just found that the 'next' branch you mentioned have problem to =
boot up.
>> I test it in p1022ds and p1010rdb boards and the result are both the =
same.
>> Note that for p1022ds I use "make p1022ds.dtb" to make the dtb =
file(36bit) with 36bit-uboot.
>> And for p1010rdb I use all 32bit image.
>> The problem list below:
>>=20
>> scsi0 : sata_fsl
>> ata1: SATA max UDMA/133 irq 74
>> fsl-sata fffe19000.sata: Sata FSL Platform/CSB Driver init
>> scsi1 : sata_fsl
>> ata2: SATA max UDMA/133 irq 41
>> Fixed MDIO Bus: probed
>> Unable to handle kernel paging request for data at address 0x00000000=20=
>> Faulting instruction address: 0xc0451630
>> Oops: Kernel access of bad area, sig: 11 [#1]
>=20
> Andy has phy driver patch that fixes this.
>=20
> --
> Timur Tabi
> Linux kernel developer at Freescale
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