* Re: [PATCH] powerpc/fsl: Distribute interrupts on all CPUs by default
From: Kumar Gala @ 2012-06-29 19:59 UTC (permalink / raw)
To: Kim Phillips; +Cc: linuxppc-dev
In-Reply-To: <20120413172615.136b60077051430253bb5d0a@freescale.com>
On Apr 13, 2012, at 5:26 PM, Kim Phillips wrote:
> At least for crypto/IPSec, doing so provides users with a better
> performance experience out of the box.
>
> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
> ---
> arch/powerpc/configs/corenet32_smp_defconfig | 1 +
> arch/powerpc/configs/corenet64_smp_defconfig | 1 +
> arch/powerpc/configs/mpc85xx_smp_defconfig | 1 +
> 3 files changed, 3 insertions(+)
applied
- k
^ permalink raw reply
* Re: RFC [PATCH] fsl pci quirk to __devinit Re: PCIe end-point on FPGA doesn't show up on PCI bus when configured
From: Kumar Gala @ 2012-06-29 19:55 UTC (permalink / raw)
To: Matias Garcia; +Cc: linuxppc-dev, Elie De Brauwer
In-Reply-To: <1316446511.10785.34.camel@matias-lnx-host>
On Sep 19, 2011, at 10:35 AM, Matias Garcia wrote:
>
> Here's the patch against 2.6.37:
>
> Change quirk_fsl_pcie_header from __init to __devinit.
>
> Signed-off-by: Matias Garcia <mgarcia@rossvideo.com>
applied
- k
^ permalink raw reply
* Re: [PATCH] P1021: set IReady in QE Microcode Upload
From: Timur Tabi @ 2012-06-29 19:26 UTC (permalink / raw)
To: Kumar Gala
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Kokoris, Ioannis
In-Reply-To: <9508ABD9-607F-4D41-A169-743ADE625F4A@kernel.crashing.org>
Kumar Gala wrote:
>
> On Mar 16, 2012, at 11:07 AM, Timur Tabi wrote:
>
>> Kumar Gala wrote:
>>>>> Haiying said it should be ok, but I haven't tried it yet. I'll try it on Monday.
>>
>>> Did you ever test this?
>>
>> No, I forgot all about it. I'll try it today, assuming the lone 8323
>> board in the board farm still works.
>
> Do you remember if you ever tested this?
No, I forgot again. Ugh, sorry. I'll do it now.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [PATCH] P1021: set IReady in QE Microcode Upload
From: Kumar Gala @ 2012-06-29 19:23 UTC (permalink / raw)
To: Timur Tabi
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Kokoris, Ioannis
In-Reply-To: <4F63652C.3050108@freescale.com>
On Mar 16, 2012, at 11:07 AM, Timur Tabi wrote:
> Kumar Gala wrote:
>>>> Haiying said it should be ok, but I haven't tried it yet. I'll try =
it on Monday.
>=20
>> Did you ever test this?
>=20
> No, I forgot all about it. I'll try it today, assuming the lone 8323
> board in the board farm still works.
Do you remember if you ever tested this?
- k=
^ permalink raw reply
* Re: [PATCH -V1 2/9] arch/powerpc: Convert virtual address to a struct
From: Cody P Schafer @ 2012-06-29 17:44 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev, paulus, anton
In-Reply-To: <1340979457-26018-3-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
> diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
> index 1c65a59..5ff936b 100644
> --- a/arch/powerpc/include/asm/mmu-hash64.h
> +++ b/arch/powerpc/include/asm/mmu-hash64.h
> @@ -143,6 +143,10 @@ struct mmu_psize_def
> unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
> };
>
> +struct virt_addr {
> + unsigned long addr;
> +};
> +
> #endif /* __ASSEMBLY__ */
>
> /*
> @@ -1153,13 +1153,13 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
> /* WARNING: This is called from hash_low_64.S, if you change this prototype,
> * do not forget to update the assembly call site !
> */
I'd suggest having a similar warning next to the definition of struct
virt_addr, as any changes to it mean we'll need to adjust hash_low_64.S
> -void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
> +void flush_hash_page(struct virt_addr va, real_pte_t pte, int psize, int ssize,
> int local)
> {
> unsigned long hash, index, shift, hidx, slot;
>
> - DBG_LOW("flush_hash_page(va=%016lx)\n", va);
> - pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
> + DBG_LOW("flush_hash_page(va=%016lx)\n", va.addr);
> + pte_iterate_hashed_subpages(pte, psize, va.addr, index, shift) {
> hash = hpt_hash(va, shift, ssize);
> hidx = __rpte_to_hidx(pte, index);
> if (hidx & _PTEIDX_SECONDARY)
--
Cody
^ permalink raw reply
* Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
From: Scott Wood @ 2012-06-29 17:10 UTC (permalink / raw)
To: Timur Tabi
Cc: Wood Scott-B07421, Li Yang-R58472, Zhao Chenhui-B35336,
linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <4FEDD3EB.7090606@freescale.com>
On 06/29/2012 11:12 AM, Timur Tabi wrote:
> Scott Wood wrote:
>> Why is this different from anywhere else where we have a list of
>> compatibles to match, often based on various SoCs? Note that we
>> explicitly want to match only certain SoCs here.
>
> I was just hoping to find a way to avoid an ever increasing list of
> compatible strings.
PCI drivers have to put up with it, why should we be different? :-)
> Other posts on this thread imply that this code could
> work for all multi-core e500 parts.
That list covers all multi-core e500v2 parts that I know of. Corenet
based chips will need a slightly different implementation, since the
registers are different.
-Scott
^ permalink raw reply
* Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
From: Scott Wood @ 2012-06-29 16:59 UTC (permalink / raw)
To: Li Yang-R58472
Cc: Wood Scott-B07421, agraf@suse.de, linuxppc-dev@lists.ozlabs.org,
Jia Hongtao-B38951
In-Reply-To: <94F013E7935FF44C83EBE7784D62AD3F09348F0B@039-SN2MPN1-022.039d.mgd.msft.net>
On 06/29/2012 11:18 AM, Li Yang-R58472 wrote:
>
>
>> -----Original Message----- From: Wood Scott-B07421 Sent: Friday,
>> June 29, 2012 11:02 AM To: Kumar Gala Cc: Jia Hongtao-B38951; Wood
>> Scott-B07421; Li Yang-R58472; agraf@suse.de;
>> linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 0/3] powerpc/fsl:
>> PCI refactoring and QEMU paravirt platform
>>
>> On 06/29/2012 10:57 AM, Kumar Gala wrote:
>>> Pretty sure the boards have ISA, if you see the .dts has
>>> references to
>> 'ISA bridge' & 'i8259' PIC.
>>
>> OK. How about looking for an i8259 node as well?
>
> That could work, but looks hackish. Our proposal for adding a new
> device tree property is a generic solution.
Yes, all *new* boards should have an isa node. But we want to remain
compatible with existing device trees.
> The only problem is that
> new kernels would work with old device trees. I think we can use
> your solution for transitional period. And go for a well defined
> device tree binding for this in long run.
The "transitional period" is until we no longer care about these
specific boards, or any out-of-tree derivatives.
-Scott
^ permalink raw reply
* Re: Build regressions/improvements in v3.5-rc4
From: Geert Uytterhoeven @ 2012-06-29 16:36 UTC (permalink / raw)
To: Paul Mundt
Cc: the arch/x86 maintainers, linuxppc-dev, linux-kernel,
Linux-sh list
In-Reply-To: <20120628082009.GC21764@linux-sh.org>
Hi Paul,
On Thu, Jun 28, 2012 at 10:20 AM, Paul Mundt <lethal@linux-sh.org> wrote:
> On Tue, Jun 26, 2012 at 10:06:27PM +0200, Geert Uytterhoeven wrote:
>> On Tue, Jun 26, 2012 at 9:59 PM, Geert Uytterhoeven
>> <geert@linux-m68k.org> wrote:
>> > JFYI, when comparing v3.5-rc4 to v3.5-rc3[3], the summaries are:
>> > ??- build errors: +11/-219
>>
>> 11 regressions:
>> =C2=A0 + arch/sh/include/asm/fixmap.h: error: implicit declaration of
>> function 'BUG_ON' [-Werror=3Dimplicit-function-declaration]: =C2=A0=3D> =
133:2
>> =C2=A0 + arch/sh/include/asm/thread_info.h: error: implicit declaration =
of
>> function 'WARN_ON' [-Werror=3Dimplicit-function-declaration]: =C2=A0=3D>=
172:2
>> =C2=A0 + include/linux/huge_mm.h: error: implicit declaration of functio=
n
>> 'BUG' [-Werror=3Dimplicit-function-declaration]: =C2=A0=3D> 185:2
>>
>> shmin_defconfig, se7712_defconfig, se7721_defconfig, sh-allnoconfig
>>
> I'm unable to reproduce any of these, is there some specific compiler
> version or warning flag configuration I'm supposed to be using? I'm
> building with 4.5.1 at the moment.
Mine (from Tony) is:
sh4-linux-gcc -v
Using built-in specs.
COLLECT_GCC=3D/usr/local/gcc-4.6.3-nolibc/sh4-linux/bin/sh4-linux-gcc
COLLECT_LTO_WRAPPER=3D/usr/local/gcc-4.6.3-nolibc/sh4-linux/bin/../libexec/=
gcc/sh4-linux/4.6.3/lto-wrapper
Target: sh4-linux
Configured with: /home/tony/buildall/src/gcc/configure
--target=3Dsh4-linux --host=3Dx86_64-linux-gnu --build=3Dx86_64-linux-gnu
--enable-targets=3Dall --prefix=3D/opt/cross/gcc-4.6.3-nolibc/sh4-linux/
--enable-languages=3Dc --with-newlib --without-headers --disable-nls
--disable-threads --disable-shared --disable-libmudflap
--disable-libssp --disable-libgomp --disable-decimal-float
--enable-checking=3Drelease --with-multilib-list=3Dm4,m4-nofpu
--with-mpfr=3D/home/tony/buildall/src/sys-x86_64
--with-gmp=3D/home/tony/buildall/src/sys-x86_64 --disable-bootstrap
--disable-libquadmath
Thread model: single
gcc version 4.6.3 (GCC)
Using v3.5-rc4:
se7721_defconfig:
sh4-linux-gcc -Wp,-MD,arch/sh/kernel/.asm-offsets.s.d -nostdinc
-isystem /usr/local/gcc-4.6.3-nolibc/sh4-linux/bin/../lib/gcc/sh4-linux/4.6=
.3/include
-Iarch/sh/include -Iarch/sh/include/generated -Iinclude -include
include/linux/kconfig.h -D__KERNEL__ -m4-nofpu -ml -Wa,-isa=3Dany
-ffreestanding -Iarch/sh/include/cpu-sh3 -Iarch/sh/include/cpu-common
-Iarch/sh/include/mach-se -Iarch/sh/include/mach-common -Wall -Wundef
-Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common
-Werror-implicit-function-declaration -Wno-format-security
-fno-delete-null-pointer-checks -O2 -pipe -m4-nofpu -ml -Wa,-isa=3Dany
-ffreestanding -Iarch/sh/include/cpu-sh3 -Iarch/sh/include/cpu-common
-Iarch/sh/include/mach-se -Iarch/sh/include/mach-common
-Wframe-larger-than=3D1024 -fno-stack-protector
-Wno-unused-but-set-variable -fno-omit-frame-pointer
-fno-optimize-sibling-calls -g -Wdeclaration-after-statement
-Wno-pointer-sign -fno-strict-overflow -fconserve-stack
-DCC_HAVE_ASM_GOTO -D"KBUILD_STR(s)=3D#s"
-D"KBUILD_BASENAME=3DKBUILD_STR(asm_offsets)"
-D"KBUILD_MODNAME=3DKBUILD_STR(asm_offsets)" -fverbose-asm -S -o
arch/sh/kernel/asm-offsets.s arch/sh/kernel/asm-offsets.c
In file included from include/linux/thread_info.h:54:0,
from include/linux/preempt.h:9,
from include/linux/spinlock.h:50,
from include/linux/mmzone.h:7,
from include/linux/gfp.h:4,
from include/linux/mm.h:8,
from arch/sh/kernel/asm-offsets.c:13:
arch/sh/include/asm/thread_info.h: In function 'set_restore_sigmask':
arch/sh/include/asm/thread_info.h:172:2: error: implicit declaration
of function 'WARN_ON' [-Werror=3Dimplicit-function-declaration]
In file included from arch/sh/include/asm/pgtable.h:25:0,
from include/linux/mm.h:44,
from arch/sh/kernel/asm-offsets.c:13:
arch/sh/include/asm/fixmap.h: In function 'virt_to_fix':
arch/sh/include/asm/fixmap.h:133:2: error: implicit declaration of
function 'BUG_ON' [-Werror=3Dimplicit-function-declaration]
In file included from arch/sh/include/asm/pgtable.h:164:0,
from include/linux/mm.h:44,
from arch/sh/kernel/asm-offsets.c:13:
include/asm-generic/pgtable.h: In function 'pmdp_test_and_clear_young':
include/asm-generic/pgtable.h:56:2: error: implicit declaration of
function 'BUG' [-Werror=3Dimplicit-function-declaration]
cc1: some warnings being treated as errors
make[1]: *** [arch/sh/kernel/asm-offsets.s] Error 1
allnoconfig:
sh4-linux-gcc -Wp,-MD,arch/sh/kernel/.asm-offsets.s.d -nostdinc
-isystem /usr/local/gcc-4.6.3-nolibc/sh4-linux/bin/../lib/gcc/sh4-linux/4.6=
.3/include
-Iarch/sh/include -Iarch/sh/include/generated -Iinclude -include
include/linux/kconfig.h -D__KERNEL__ -m4-nofpu -ml -Wa,-isa=3Dany
-ffreestanding -Iarch/sh/include/cpu-sh2 -Iarch/sh/include/cpu-common
-Iarch/sh/include/mach-common -Wall -Wundef -Wstrict-prototypes
-Wno-trigraphs -fno-strict-aliasing -fno-common
-Werror-implicit-function-declaration -Wno-format-security
-fno-delete-null-pointer-checks -O2 -pipe -m4-nofpu -ml -Wa,-isa=3Dany
-ffreestanding -Iarch/sh/include/cpu-sh2 -Iarch/sh/include/cpu-common
-Iarch/sh/include/mach-common -Wframe-larger-than=3D1024
-fno-stack-protector -Wno-unused-but-set-variable -fomit-frame-pointer
-Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow
-fconserve-stack -DCC_HAVE_ASM_GOTO -D"KBUILD_STR(s)=3D#s"
-D"KBUILD_BASENAME=3DKBUILD_STR(asm_offsets)"
-D"KBUILD_MODNAME=3DKBUILD_STR(asm_offsets)" -fverbose-asm -S -o
arch/sh/kernel/asm-offsets.s arch/sh/kernel/asm-offsets.c
In file included from include/linux/thread_info.h:54:0,
from include/linux/preempt.h:9,
from include/linux/spinlock.h:50,
from include/linux/mmzone.h:7,
from include/linux/gfp.h:4,
from include/linux/mm.h:8,
from arch/sh/kernel/asm-offsets.c:13:
arch/sh/include/asm/thread_info.h: In function 'set_restore_sigmask':
arch/sh/include/asm/thread_info.h:172:2: error: implicit declaration
of function 'WARN_ON' [-Werror=3Dimplicit-function-declaration]
In file included from arch/sh/include/asm/pgtable.h:25:0,
from include/linux/mm.h:44,
from arch/sh/kernel/asm-offsets.c:13:
arch/sh/include/asm/fixmap.h: In function 'virt_to_fix':
arch/sh/include/asm/fixmap.h:133:2: error: implicit declaration of
function 'BUG_ON' [-Werror=3Dimplicit-function-declaration]
In file included from include/linux/mm.h:257:0,
from arch/sh/kernel/asm-offsets.c:13:
include/linux/huge_mm.h: In function 'hugepage_madvise':
include/linux/huge_mm.h:185:2: error: implicit declaration of function
'BUG' [-Werror=3Dimplicit-function-declaration]
cc1: some warnings being treated as errors
make[1]: *** [arch/sh/kernel/asm-offsets.s] Error 1
Gr{oetje,eeting}s,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k=
.org
In personal conversations with technical people, I call myself a hacker. Bu=
t
when I'm talking to journalists I just say "programmer" or something like t=
hat.
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0=C2=A0 =C2=A0=C2=A0 -- Linus Torvalds
^ permalink raw reply
* RE: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
From: Li Yang-R58472 @ 2012-06-29 16:18 UTC (permalink / raw)
To: Wood Scott-B07421, Kumar Gala
Cc: linuxppc-dev@lists.ozlabs.org, agraf@suse.de, Jia Hongtao-B38951
In-Reply-To: <4FEDD15E.10706@freescale.com>
DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0
MjENCj4gU2VudDogRnJpZGF5LCBKdW5lIDI5LCAyMDEyIDExOjAyIEFNDQo+IFRvOiBLdW1hciBH
YWxhDQo+IENjOiBKaWEgSG9uZ3Rhby1CMzg5NTE7IFdvb2QgU2NvdHQtQjA3NDIxOyBMaSBZYW5n
LVI1ODQ3MjsgYWdyYWZAc3VzZS5kZTsNCj4gbGludXhwcGMtZGV2QGxpc3RzLm96bGFicy5vcmcN
Cj4gU3ViamVjdDogUmU6IFtQQVRDSCAwLzNdIHBvd2VycGMvZnNsOiBQQ0kgcmVmYWN0b3Jpbmcg
YW5kIFFFTVUgcGFyYXZpcnQNCj4gcGxhdGZvcm0NCj4gDQo+IE9uIDA2LzI5LzIwMTIgMTA6NTcg
QU0sIEt1bWFyIEdhbGEgd3JvdGU6DQo+ID4NCj4gPiBPbiBKdW4gMjgsIDIwMTIsIGF0IDk6MzYg
UE0sIEppYSBIb25ndGFvLUIzODk1MSB3cm90ZToNCj4gPg0KPiA+Pg0KPiA+Pg0KPiA+Pj4gLS0t
LS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gPj4+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIxDQo+
ID4+PiBTZW50OiBGcmlkYXksIEp1bmUgMjksIDIwMTIgMTI6MzEgQU0NCj4gPj4+IFRvOiBKaWEg
SG9uZ3Rhby1CMzg5NTENCj4gPj4+IENjOiBXb29kIFNjb3R0LUIwNzQyMTsgZ2FsYWtAa2VybmVs
LmNyYXNoaW5nLm9yZzsgTGkgWWFuZy1SNTg0NzI7DQo+ID4+PiBhZ3JhZkBzdXNlLmRlOyBsaW51
eHBwYy1kZXZAbGlzdHMub3psYWJzLm9yZw0KPiA+Pj4gU3ViamVjdDogUmU6IFtQQVRDSCAwLzNd
IHBvd2VycGMvZnNsOiBQQ0kgcmVmYWN0b3JpbmcgYW5kIFFFTVUNCj4gPj4+IHBhcmF2aXJ0IHBs
YXRmb3JtDQo+ID4+Pg0KPiA+Pj4gT24gMDYvMjcvMjAxMiAxMTowNiBQTSwgSmlhIEhvbmd0YW8t
QjM4OTUxIHdyb3RlOg0KPiA+Pj4+DQo+ID4+Pj4NCj4gPj4+Pj4gLS0tLS1PcmlnaW5hbCBNZXNz
YWdlLS0tLS0NCj4gPj4+Pj4gRnJvbTogV29vZCBTY290dC1CMDc0MjENCj4gPj4+Pj4gU2VudDog
VGh1cnNkYXksIEp1bmUgMjgsIDIwMTIgNzo0OSBBTQ0KPiA+Pj4+PiBUbzogZ2FsYWtAa2VybmVs
LmNyYXNoaW5nLm9yZw0KPiA+Pj4+PiBDYzogYWdyYWZAc3VzZS5kZTsgbGludXhwcGMtZGV2QGxp
c3RzLm96bGFicy5vcmc7IEppYQ0KPiA+Pj4+PiBIb25ndGFvLUIzODk1MQ0KPiA+Pj4+PiBTdWJq
ZWN0OiBbUEFUQ0ggMC8zXSBwb3dlcnBjL2ZzbDogUENJIHJlZmFjdG9yaW5nIGFuZCBRRU1VDQo+
ID4+Pj4+IHBhcmF2aXJ0IHBsYXRmb3JtDQo+ID4+Pj4+DQo+ID4+Pj4+IFRoZSBRRU1VIHN0dWZm
IGlzIHJlbGF0ZWQgdG8gdGhlIFBDSSByZWZhY3RvcmluZyBiZWNhdXNlIGN1cnJlbnRseQ0KPiA+
Pj4+PiB3ZSBoYXZlIGEgaGFyZCB0aW1lIHNlbGVjdGluZyBhIHByaW1hcnkgYnVzIHVuZGVyIFFF
TVUsIGFuZCBhbHNvDQo+ID4+PiBiZWNhdXNlDQo+ID4+Pj4+IHRoZSBnZW5lcmljIHFlbXUgZTUw
MCBwbGF0Zm9ybSB3YW50cyBhIGZ1bGwgbGlzdCBvZiBGU0wgUENJDQo+ID4+PiBjb21wYXRpYmxl
cw0KPiA+Pj4+PiB0byBjaGVjay4NCj4gPj4+Pj4NCj4gPj4+Pg0KPiA+Pj4+IEl0IHNlZW1zIHRo
YXQgbm90IGFsbCBwcmltYXJ5IGJ1cyBoYXMgImlzYSIgbm9kZSBsaWtlIDg1NDEgYW5kIDg1NTUu
DQo+ID4+Pg0KPiA+Pj4gRG8gdGhvc2UgYm9hcmRzIChpdCdzIHRoZSBib2FyZHMgdGhhdCBtYXR0
ZXIsIG5vdCBjaGlwcy4uLikgaGF2ZQ0KPiA+Pj4gbGVnYWN5IElTQT8gIElmIHRoZXkgZG8sIGFu
ZCBpdCdzIG5vdCBpbiB0aGUgZGV2aWNlIHRyZWUsIHRoZW4gd2UNCj4gPj4+IHNob3VsZCBmaXgg
dGhlIGRldmljZSB0cmVlIGZvciBjb25zaXN0ZW5jeSwgYnV0IGFsc28gcmV0YWluIHNvbWUNCj4g
Pj4+IHNvcnQgb2YgaGFjayB0byByZW1haW4gY29tcGF0aWJsZSB3aXRoIG9sZCBkZXZpY2UgdHJl
ZXMuDQo+ID4+Pg0KPiA+Pj4gQSBib2FyZCBjYW4gcmVmcmFpbiBmcm9tIHVzaW5nIHRoZSBuZXcg
Y29tbW9uIGluZnJhc3RydWN0dXJlIGlmIGl0DQo+ID4+PiBoYXMgYSBnb29kIHJlYXNvbiB0by4N
Cj4gPj4NCj4gPj4gSSdtIG5vdCBzdXJlIHRoYXQgTVBDODU0MUNEUyAob3IgODU1NSkgaGFzIGxl
Z2FjeSBJU0EuIEkganVzdCBjaGVja2VkDQo+ID4+IGluIGtlcm5lbCBhbmQgZHRzIHdoaWNoIGlt
cGxpZXMgdGhlIGJvYXJkIGhhcyBwcmltYXJ5IGJ1cyBhbmQgbm8gImlzYSINCj4gbm9kZS4NCj4g
Pj4gSSB3aWxsIGZpbmQgb3V0IHRoZSBmYWN0cyBsYXRlci4NCj4gPg0KPiA+IFByZXR0eSBzdXJl
IHRoZSBib2FyZHMgaGF2ZSBJU0EsIGlmIHlvdSBzZWUgdGhlIC5kdHMgaGFzIHJlZmVyZW5jZXMg
dG8NCj4gJ0lTQSBicmlkZ2UnICYgJ2k4MjU5JyBQSUMuDQo+IA0KPiBPSy4gIEhvdyBhYm91dCBs
b29raW5nIGZvciBhbiBpODI1OSBub2RlIGFzIHdlbGw/DQoNClRoYXQgY291bGQgd29yaywgYnV0
IGxvb2tzIGhhY2tpc2guICBPdXIgcHJvcG9zYWwgZm9yIGFkZGluZyBhIG5ldyBkZXZpY2UgdHJl
ZSBwcm9wZXJ0eSBpcyBhIGdlbmVyaWMgc29sdXRpb24uICBUaGUgb25seSBwcm9ibGVtIGlzIHRo
YXQgbmV3IGtlcm5lbHMgd291bGQgd29yayB3aXRoIG9sZCBkZXZpY2UgdHJlZXMuICBJIHRoaW5r
IHdlIGNhbiB1c2UgeW91ciBzb2x1dGlvbiBmb3IgdHJhbnNpdGlvbmFsIHBlcmlvZC4gIEFuZCBn
byBmb3IgYSB3ZWxsIGRlZmluZWQgZGV2aWNlIHRyZWUgYmluZGluZyBmb3IgdGhpcyBpbiBsb25n
IHJ1bi4NCg0KLSBMZW8NCg==
^ permalink raw reply
* Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
From: Timur Tabi @ 2012-06-29 16:12 UTC (permalink / raw)
To: Scott Wood
Cc: Wood Scott-B07421, Li Yang-R58472, Zhao Chenhui-B35336,
linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <4FEDD383.40804@freescale.com>
Scott Wood wrote:
> Why is this different from anywhere else where we have a list of
> compatibles to match, often based on various SoCs? Note that we
> explicitly want to match only certain SoCs here.
I was just hoping to find a way to avoid an ever increasing list of
compatible strings. Other posts on this thread imply that this code could
work for all multi-core e500 parts.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
From: Scott Wood @ 2012-06-29 16:10 UTC (permalink / raw)
To: Timur Tabi
Cc: Wood Scott-B07421, Li Yang-R58472, Zhao Chenhui-B35336,
linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <4FEDD1F0.1060000@freescale.com>
On 06/29/2012 11:04 AM, Timur Tabi wrote:
> Scott Wood wrote:
>
>>> I wonder if it's possible to dynamically generate the compatible
>>> string by using the SOC name?
>>
>> Where are you going to get the SoC name from?
>
> Well, that is why I said "I wonder". I'm disappointed that the "cpus"
> node doesn't help much. You'd think the name of the CPU would be in the
> CPU node somewhere.
The SoC is not the CPU. The CPU is e500v2.
Why is this different from anywhere else where we have a list of
compatibles to match, often based on various SoCs? Note that we
explicitly want to match only certain SoCs here.
-Scott
^ permalink raw reply
* RE: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
From: Zang Roy-R61911 @ 2012-06-29 16:06 UTC (permalink / raw)
To: Kumar Gala, Jia Hongtao-B38951
Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org, Li Yang-R58472,
agraf@suse.de
In-Reply-To: <34D617F2-54CD-46DA-A110-E44CE081B99B@kernel.crashing.org>
> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> fei.zang=3Dfreescale.com@lists.ozlabs.org] On Behalf Of Kumar Gala
> Sent: Friday, June 29, 2012 23:58 PM
> To: Jia Hongtao-B38951
> Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Li Yang-R58472;
> agraf@suse.de
> Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt
> platform
>=20
>=20
> On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote:
>=20
> >
> >
> >> -----Original Message-----
> >> From: Wood Scott-B07421
> >> Sent: Friday, June 29, 2012 12:31 AM
> >> To: Jia Hongtao-B38951
> >> Cc: Wood Scott-B07421; galak@kernel.crashing.org; Li Yang-R58472;
> >> agraf@suse.de; linuxppc-dev@lists.ozlabs.org
> >> Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravir=
t
> >> platform
> >>
> >> On 06/27/2012 11:06 PM, Jia Hongtao-B38951 wrote:
> >>>
> >>>
> >>>> -----Original Message-----
> >>>> From: Wood Scott-B07421
> >>>> Sent: Thursday, June 28, 2012 7:49 AM
> >>>> To: galak@kernel.crashing.org
> >>>> Cc: agraf@suse.de; linuxppc-dev@lists.ozlabs.org; Jia Hongtao-B38951
> >>>> Subject: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt
> >>>> platform
> >>>>
> >>>> The QEMU stuff is related to the PCI refactoring because currently
> >>>> we have a hard time selecting a primary bus under QEMU, and also
> >> because
> >>>> the generic qemu e500 platform wants a full list of FSL PCI
> >> compatibles
> >>>> to check.
> >>>>
> >>>
> >>> It seems that not all primary bus has "isa" node like 8541 and 8555.
> >>
> >> Do those boards (it's the boards that matter, not chips...) have legac=
y
> >> ISA? If they do, and it's not in the device tree, then we should fix
> >> the device tree for consistency, but also retain some sort of hack to
> >> remain compatible with old device trees.
> >>
> >> A board can refrain from using the new common infrastructure if it has=
a
> >> good reason to.
> >
> > I'm not sure that MPC8541CDS (or 8555) has legacy ISA. I just checked i=
n
> > kernel and dts which implies the board has primary bus and no "isa" nod=
e.
> > I will find out the facts later.
>=20
> Pretty sure the boards have ISA, if you see the .dts has references to 'I=
SA
> bridge' & 'i8259' PIC.
It is on the VIA south bridge.
Roy
^ permalink raw reply
* Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
From: Kumar Gala @ 2012-06-29 16:04 UTC (permalink / raw)
To: Scott Wood
Cc: Wood Scott-B07421, agraf@suse.de, linuxppc-dev@lists.ozlabs.org,
Li Yang-R58472, Jia Hongtao-B38951
In-Reply-To: <4FEDD15E.10706@freescale.com>
On Jun 29, 2012, at 11:01 AM, Scott Wood wrote:
> On 06/29/2012 10:57 AM, Kumar Gala wrote:
>>=20
>> On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote:
>>=20
>>>=20
>>>=20
>>>> -----Original Message-----
>>>> From: Wood Scott-B07421
>>>> Sent: Friday, June 29, 2012 12:31 AM
>>>> To: Jia Hongtao-B38951
>>>> Cc: Wood Scott-B07421; galak@kernel.crashing.org; Li Yang-R58472;
>>>> agraf@suse.de; linuxppc-dev@lists.ozlabs.org
>>>> Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU =
paravirt
>>>> platform
>>>>=20
>>>> On 06/27/2012 11:06 PM, Jia Hongtao-B38951 wrote:
>>>>>=20
>>>>>=20
>>>>>> -----Original Message-----
>>>>>> From: Wood Scott-B07421
>>>>>> Sent: Thursday, June 28, 2012 7:49 AM
>>>>>> To: galak@kernel.crashing.org
>>>>>> Cc: agraf@suse.de; linuxppc-dev@lists.ozlabs.org; Jia =
Hongtao-B38951
>>>>>> Subject: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU =
paravirt
>>>>>> platform
>>>>>>=20
>>>>>> The QEMU stuff is related to the PCI refactoring because =
currently
>>>>>> we have a hard time selecting a primary bus under QEMU, and also
>>>> because
>>>>>> the generic qemu e500 platform wants a full list of FSL PCI
>>>> compatibles
>>>>>> to check.
>>>>>>=20
>>>>>=20
>>>>> It seems that not all primary bus has "isa" node like 8541 and =
8555.
>>>>=20
>>>> Do those boards (it's the boards that matter, not chips...) have =
legacy
>>>> ISA? If they do, and it's not in the device tree, then we should =
fix
>>>> the device tree for consistency, but also retain some sort of hack =
to
>>>> remain compatible with old device trees.
>>>>=20
>>>> A board can refrain from using the new common infrastructure if it =
has a
>>>> good reason to.
>>>=20
>>> I'm not sure that MPC8541CDS (or 8555) has legacy ISA. I just =
checked in
>>> kernel and dts which implies the board has primary bus and no "isa" =
node.
>>> I will find out the facts later.
>>=20
>> Pretty sure the boards have ISA, if you see the .dts has references =
to 'ISA bridge' & 'i8259' PIC.
>=20
> OK. How about looking for an i8259 node as well?
>=20
> -Scott
Works for me, saves us having to waste time on figuring out how to =
update .dts for the boards.
- k
^ permalink raw reply
* Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
From: Timur Tabi @ 2012-06-29 16:04 UTC (permalink / raw)
To: Scott Wood
Cc: Wood Scott-B07421, Li Yang-R58472, Zhao Chenhui-B35336,
linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <4FEDD07D.3090103@freescale.com>
Scott Wood wrote:
>> I wonder if it's possible to dynamically generate the compatible
>> string by using the SOC name?
>
> Where are you going to get the SoC name from?
Well, that is why I said "I wonder". I'm disappointed that the "cpus"
node doesn't help much. You'd think the name of the CPU would be in the
CPU node somewhere.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
From: Scott Wood @ 2012-06-29 15:57 UTC (permalink / raw)
To: Tabi Timur-B04825
Cc: Wood Scott-B07421, Li Yang-R58472, Zhao Chenhui-B35336,
linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <CAOZdJXWiGOCtP1iJYR2S48XwR2Wpry8+VswctctdVfY9Z+QTiQ@mail.gmail.com>
On 06/29/2012 10:39 AM, Tabi Timur-B04825 wrote:
> On Tue, Jun 26, 2012 at 5:25 AM, Zhao Chenhui
> <chenhui.zhao@freescale.com> wrote:
>> +static void mpc85xx_give_timebase(void)
>> +{
>> + unsigned long flags;
>> +
>> + local_irq_save(flags);
>> +
>> + while (!tb_req)
>> + barrier();
>
> I think tb_req and tb_valid need to be 'volatile'.
No, barrier() and mb() take care of that.
>> +static const struct of_device_id mpc85xx_smp_guts_ids[] = {
>> + { .compatible = "fsl,mpc8572-guts", },
>> + { .compatible = "fsl,p1020-guts", },
>> + { .compatible = "fsl,p1021-guts", },
>> + { .compatible = "fsl,p1022-guts", },
>> + { .compatible = "fsl,p1023-guts", },
>> + { .compatible = "fsl,p2020-guts", },
>> + {},
>> +};
>
> I wonder if it's possible to dynamically generate the compatible
> string by using the SOC name?
Where are you going to get the SoC name from?
-Scott
^ permalink raw reply
* Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
From: Scott Wood @ 2012-06-29 16:01 UTC (permalink / raw)
To: Kumar Gala
Cc: Wood Scott-B07421, agraf@suse.de, linuxppc-dev@lists.ozlabs.org,
Li Yang-R58472, Jia Hongtao-B38951
In-Reply-To: <34D617F2-54CD-46DA-A110-E44CE081B99B@kernel.crashing.org>
On 06/29/2012 10:57 AM, Kumar Gala wrote:
>
> On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote:
>
>>
>>
>>> -----Original Message-----
>>> From: Wood Scott-B07421
>>> Sent: Friday, June 29, 2012 12:31 AM
>>> To: Jia Hongtao-B38951
>>> Cc: Wood Scott-B07421; galak@kernel.crashing.org; Li Yang-R58472;
>>> agraf@suse.de; linuxppc-dev@lists.ozlabs.org
>>> Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt
>>> platform
>>>
>>> On 06/27/2012 11:06 PM, Jia Hongtao-B38951 wrote:
>>>>
>>>>
>>>>> -----Original Message-----
>>>>> From: Wood Scott-B07421
>>>>> Sent: Thursday, June 28, 2012 7:49 AM
>>>>> To: galak@kernel.crashing.org
>>>>> Cc: agraf@suse.de; linuxppc-dev@lists.ozlabs.org; Jia Hongtao-B38951
>>>>> Subject: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt
>>>>> platform
>>>>>
>>>>> The QEMU stuff is related to the PCI refactoring because currently
>>>>> we have a hard time selecting a primary bus under QEMU, and also
>>> because
>>>>> the generic qemu e500 platform wants a full list of FSL PCI
>>> compatibles
>>>>> to check.
>>>>>
>>>>
>>>> It seems that not all primary bus has "isa" node like 8541 and 8555.
>>>
>>> Do those boards (it's the boards that matter, not chips...) have legacy
>>> ISA? If they do, and it's not in the device tree, then we should fix
>>> the device tree for consistency, but also retain some sort of hack to
>>> remain compatible with old device trees.
>>>
>>> A board can refrain from using the new common infrastructure if it has a
>>> good reason to.
>>
>> I'm not sure that MPC8541CDS (or 8555) has legacy ISA. I just checked in
>> kernel and dts which implies the board has primary bus and no "isa" node.
>> I will find out the facts later.
>
> Pretty sure the boards have ISA, if you see the .dts has references to 'ISA bridge' & 'i8259' PIC.
OK. How about looking for an i8259 node as well?
-Scott
^ permalink raw reply
* Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
From: Kumar Gala @ 2012-06-29 15:57 UTC (permalink / raw)
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org, Li Yang-R58472,
agraf@suse.de
In-Reply-To: <412C8208B4A0464FA894C5F0C278CD5D01A13620@039-SN1MPN1-002.039d.mgd.msft.net>
On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote:
>=20
>=20
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Friday, June 29, 2012 12:31 AM
>> To: Jia Hongtao-B38951
>> Cc: Wood Scott-B07421; galak@kernel.crashing.org; Li Yang-R58472;
>> agraf@suse.de; linuxppc-dev@lists.ozlabs.org
>> Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU =
paravirt
>> platform
>>=20
>> On 06/27/2012 11:06 PM, Jia Hongtao-B38951 wrote:
>>>=20
>>>=20
>>>> -----Original Message-----
>>>> From: Wood Scott-B07421
>>>> Sent: Thursday, June 28, 2012 7:49 AM
>>>> To: galak@kernel.crashing.org
>>>> Cc: agraf@suse.de; linuxppc-dev@lists.ozlabs.org; Jia =
Hongtao-B38951
>>>> Subject: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt
>>>> platform
>>>>=20
>>>> The QEMU stuff is related to the PCI refactoring because currently
>>>> we have a hard time selecting a primary bus under QEMU, and also
>> because
>>>> the generic qemu e500 platform wants a full list of FSL PCI
>> compatibles
>>>> to check.
>>>>=20
>>>=20
>>> It seems that not all primary bus has "isa" node like 8541 and 8555.
>>=20
>> Do those boards (it's the boards that matter, not chips...) have =
legacy
>> ISA? If they do, and it's not in the device tree, then we should fix
>> the device tree for consistency, but also retain some sort of hack to
>> remain compatible with old device trees.
>>=20
>> A board can refrain from using the new common infrastructure if it =
has a
>> good reason to.
>=20
> I'm not sure that MPC8541CDS (or 8555) has legacy ISA. I just checked =
in
> kernel and dts which implies the board has primary bus and no "isa" =
node.
> I will find out the facts later.
Pretty sure the boards have ISA, if you see the .dts has references to =
'ISA bridge' & 'i8259' PIC.
- k
^ permalink raw reply
* Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
From: Tabi Timur-B04825 @ 2012-06-29 15:39 UTC (permalink / raw)
To: Zhao Chenhui-B35336
Cc: Wood Scott-B07421, Li Yang-R58472, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org
In-Reply-To: <1340706359-9455-1-git-send-email-chenhui.zhao@freescale.com>
On Tue, Jun 26, 2012 at 5:25 AM, Zhao Chenhui
<chenhui.zhao@freescale.com> wrote:
> Do hardware timebase sync. Firstly, stop all timebases, and transfer
> the timebase value of the boot core to the other core. Finally,
> start all timebases.
>
> Only apply to dual-core chips, such as MPC8572, P2020, etc.
>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> Changes for v6:
> =A0* added 85xx_TB_SYNC
> =A0* added isync() after set_tb()
> =A0* removed extra entries from mpc85xx_smp_guts_ids
>
> =A0arch/powerpc/include/asm/fsl_guts.h | =A0 =A02 +
> =A0arch/powerpc/platforms/85xx/Kconfig | =A0 =A05 ++
> =A0arch/powerpc/platforms/85xx/smp.c =A0 | =A0 84 +++++++++++++++++++++++=
++++++++++++
> =A03 files changed, 91 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/a=
sm/fsl_guts.h
> index aa4c488..dd5ba2c 100644
> --- a/arch/powerpc/include/asm/fsl_guts.h
> +++ b/arch/powerpc/include/asm/fsl_guts.h
> @@ -48,6 +48,8 @@ struct ccsr_guts {
> =A0 =A0 =A0 =A0 __be32 =A0dmuxcr; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* 0x.00=
68 - DMA Mux Control Register */
> =A0 =A0 =A0 =A0 u8 =A0 =A0 res06c[0x70 - 0x6c];
> =A0 =A0 =A0 =A0__be32 =A0devdisr; =A0 =A0 =A0 =A0/* 0x.0070 - Device Disa=
ble Control */
> +#define CCSR_GUTS_DEVDISR_TB1 =A00x00001000
> +#define CCSR_GUTS_DEVDISR_TB0 =A00x00004000
> =A0 =A0 =A0 =A0__be32 =A0devdisr2; =A0 =A0 =A0 /* 0x.0074 - Device Disabl=
e Control 2 */
> =A0 =A0 =A0 =A0u8 =A0 =A0 =A0res078[0x7c - 0x78];
> =A0 =A0 =A0 =A0__be32 =A0pmjcr; =A0 =A0 =A0 =A0 =A0/* 0x.007c - 4 Power M=
anagement Jog Control Register */
> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms=
/85xx/Kconfig
> index f000d81..8dd7147 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -8,6 +8,7 @@ menuconfig FSL_SOC_BOOKE
> =A0 =A0 =A0 =A0select FSL_PCI if PCI
> =A0 =A0 =A0 =A0select SERIAL_8250_EXTENDED if SERIAL_8250
> =A0 =A0 =A0 =A0select SERIAL_8250_SHARE_IRQ if SERIAL_8250
> + =A0 =A0 =A0 select 85xx_TB_SYNC if KEXEC
> =A0 =A0 =A0 =A0default y
>
> =A0if FSL_SOC_BOOKE
> @@ -267,3 +268,7 @@ endif # FSL_SOC_BOOKE
>
> =A0config TQM85xx
> =A0 =A0 =A0 =A0bool
> +
> +config 85xx_TB_SYNC
> + =A0 =A0 =A0 bool
> + =A0 =A0 =A0 default n
> diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/8=
5xx/smp.c
> index ff42490..edb0cad 100644
> --- a/arch/powerpc/platforms/85xx/smp.c
> +++ b/arch/powerpc/platforms/85xx/smp.c
> @@ -24,6 +24,7 @@
> =A0#include <asm/mpic.h>
> =A0#include <asm/cacheflush.h>
> =A0#include <asm/dbell.h>
> +#include <asm/fsl_guts.h>
>
> =A0#include <sysdev/fsl_soc.h>
> =A0#include <sysdev/mpic.h>
> @@ -42,6 +43,69 @@ extern void __early_start(void);
> =A0#define NUM_BOOT_ENTRY =A0 =A0 =A0 =A0 8
> =A0#define SIZE_BOOT_ENTRY =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(NUM_BOOT_ENTRY=
* sizeof(u32))
>
> +#ifdef CONFIG_85xx_TB_SYNC
> +static struct ccsr_guts __iomem *guts;
> +static u64 timebase;
> +static int tb_req;
> +static int tb_valid;
> +
> +static void mpc85xx_timebase_freeze(int freeze)
> +{
> + =A0 =A0 =A0 unsigned int mask;
'mask' should be uint32_t
> +
> + =A0 =A0 =A0 if (!guts)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return;
This function should never be called if guts is NULL, so this check
should be unnecessary.
> +
> + =A0 =A0 =A0 mask =3D CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
> + =A0 =A0 =A0 if (freeze)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 setbits32(&guts->devdisr, mask);
> + =A0 =A0 =A0 else
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 clrbits32(&guts->devdisr, mask);
> +
> + =A0 =A0 =A0 in_be32(&guts->devdisr);
> +}
> +
> +static void mpc85xx_give_timebase(void)
> +{
> + =A0 =A0 =A0 unsigned long flags;
> +
> + =A0 =A0 =A0 local_irq_save(flags);
> +
> + =A0 =A0 =A0 while (!tb_req)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 barrier();
I think tb_req and tb_valid need to be 'volatile'.
> + =A0 =A0 =A0 tb_req =3D 0;
> +
> + =A0 =A0 =A0 mpc85xx_timebase_freeze(1);
> + =A0 =A0 =A0 timebase =3D get_tb();
> + =A0 =A0 =A0 mb();
> + =A0 =A0 =A0 tb_valid =3D 1;
> +
> + =A0 =A0 =A0 while (tb_valid)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 barrier();
> +
> + =A0 =A0 =A0 mpc85xx_timebase_freeze(0);
> +
> + =A0 =A0 =A0 local_irq_restore(flags);
> +}
> +
> +static void mpc85xx_take_timebase(void)
> +{
> + =A0 =A0 =A0 unsigned long flags;
> +
> + =A0 =A0 =A0 local_irq_save(flags);
> +
> + =A0 =A0 =A0 tb_req =3D 1;
> + =A0 =A0 =A0 while (!tb_valid)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 barrier();
> +
> + =A0 =A0 =A0 set_tb(timebase >> 32, timebase & 0xffffffff);
> + =A0 =A0 =A0 isync();
> + =A0 =A0 =A0 tb_valid =3D 0;
> +
> + =A0 =A0 =A0 local_irq_restore(flags);
> +}
> +#endif
> +
> =A0static int __init
> =A0smp_85xx_kick_cpu(int nr)
> =A0{
> @@ -228,6 +292,16 @@ smp_85xx_setup_cpu(int cpu_nr)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0doorbell_setup_this_cpu();
> =A0}
>
> +static const struct of_device_id mpc85xx_smp_guts_ids[] =3D {
> + =A0 =A0 =A0 { .compatible =3D "fsl,mpc8572-guts", },
> + =A0 =A0 =A0 { .compatible =3D "fsl,p1020-guts", },
> + =A0 =A0 =A0 { .compatible =3D "fsl,p1021-guts", },
> + =A0 =A0 =A0 { .compatible =3D "fsl,p1022-guts", },
> + =A0 =A0 =A0 { .compatible =3D "fsl,p1023-guts", },
> + =A0 =A0 =A0 { .compatible =3D "fsl,p2020-guts", },
> + =A0 =A0 =A0 {},
> +};
I wonder if it's possible to dynamically generate the compatible
string by using the SOC name?
> +
> =A0void __init mpc85xx_smp_init(void)
> =A0{
> =A0 =A0 =A0 =A0struct device_node *np;
> @@ -249,6 +323,16 @@ void __init mpc85xx_smp_init(void)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0smp_85xx_ops.cause_ipi =3D doorbell_cause_=
ipi;
> =A0 =A0 =A0 =A0}
>
> + =A0 =A0 =A0 np =3D of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
> + =A0 =A0 =A0 if (np) {
> +#ifdef CONFIG_85xx_TB_SYNC
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 guts =3D of_iomap(np, 0);
You need to test the return value of of_iomap(). smp_85xx_ops should
be set only if guts is not NULL.
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 smp_85xx_ops.give_timebase =3D mpc85xx_give=
_timebase;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 smp_85xx_ops.take_timebase =3D mpc85xx_take=
_timebase;
> +#endif
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 of_node_put(np);
> + =A0 =A0 =A0 }
> +
> =A0 =A0 =A0 =A0smp_ops =3D &smp_85xx_ops;
>
> =A0#ifdef CONFIG_KEXEC
> --
> 1.6.4.1
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" i=
n
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at =A0http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at =A0http://www.tux.org/lkml/
--=20
Timur Tabi
Linux kernel developer at Freescale=
^ permalink raw reply
* [PATCH -V1 9/9] arch/powerpc: Add 64TB support
From: Aneesh Kumar K.V @ 2012-06-29 14:17 UTC (permalink / raw)
To: benh, paulus, michael, anton; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1340979457-26018-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Increase max addressable range to 64TB. This is not tested on
real hardware yet.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 8 ++++----
arch/powerpc/include/asm/pgtable-ppc64-4k.h | 2 +-
arch/powerpc/include/asm/pgtable-ppc64-64k.h | 2 +-
arch/powerpc/include/asm/processor.h | 4 ++--
arch/powerpc/include/asm/sparsemem.h | 4 ++--
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 47ddfa1..bf042ba 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -367,16 +367,16 @@ extern void slb_set_size(u16 size);
*/
#define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */
-#define VSID_BITS_256M 36
+#define VSID_BITS_256M 38
#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
-#define VSID_BITS_1T 24
+#define VSID_BITS_1T 26
#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
#define CONTEXT_BITS 19
-#define USER_ESID_BITS 16
-#define USER_ESID_BITS_1T 4
+#define USER_ESID_BITS 18
+#define USER_ESID_BITS_1T 6
#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-4k.h b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
index 6eefdcf..b3eccf2 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-4k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
@@ -7,7 +7,7 @@
*/
#define PTE_INDEX_SIZE 9
#define PMD_INDEX_SIZE 7
-#define PUD_INDEX_SIZE 7
+#define PUD_INDEX_SIZE 9
#define PGD_INDEX_SIZE 9
#ifndef __ASSEMBLY__
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
index 90533dd..be4e287 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-64k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
@@ -7,7 +7,7 @@
#define PTE_INDEX_SIZE 12
#define PMD_INDEX_SIZE 12
#define PUD_INDEX_SIZE 0
-#define PGD_INDEX_SIZE 4
+#define PGD_INDEX_SIZE 6
#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 8e2d037..426ed13 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -100,8 +100,8 @@ extern struct task_struct *last_task_used_spe;
#endif
#ifdef CONFIG_PPC64
-/* 64-bit user address space is 44-bits (16TB user VM) */
-#define TASK_SIZE_USER64 (0x0000100000000000UL)
+/* 64-bit user address space is 46-bits (64TB user VM) */
+#define TASK_SIZE_USER64 (0x0000400000000000UL)
/*
* 32-bit user address space is 4GB - 1 page
diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h
index 0c5fa31..f6fc0ee 100644
--- a/arch/powerpc/include/asm/sparsemem.h
+++ b/arch/powerpc/include/asm/sparsemem.h
@@ -10,8 +10,8 @@
*/
#define SECTION_SIZE_BITS 24
-#define MAX_PHYSADDR_BITS 44
-#define MAX_PHYSMEM_BITS 44
+#define MAX_PHYSADDR_BITS 46
+#define MAX_PHYSMEM_BITS 46
#endif /* CONFIG_SPARSEMEM */
--
1.7.10
^ permalink raw reply related
* [PATCH -V1 8/9] arch/powerpc: Use 32bit array for slb cache
From: Aneesh Kumar K.V @ 2012-06-29 14:17 UTC (permalink / raw)
To: benh, paulus, michael, anton; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1340979457-26018-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
With larger vsid we need to track more bits of ESID in slb cache
for slb invalidate.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/paca.h | 2 +-
arch/powerpc/mm/slb_low.S | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index daf813f..3e7abba 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -100,7 +100,7 @@ struct paca_struct {
/* SLB related definitions */
u16 vmalloc_sllp;
u16 slb_cache_ptr;
- u16 slb_cache[SLB_CACHE_ENTRIES];
+ u32 slb_cache[SLB_CACHE_ENTRIES];
#endif /* CONFIG_PPC_STD_MMU_64 */
#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index c1fc81c..d522679 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -269,10 +269,10 @@ _GLOBAL(slb_compare_rr_to_size)
bge 1f
/* still room in the slb cache */
- sldi r11,r3,1 /* r11 = offset * sizeof(u16) */
- rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
- add r11,r11,r13 /* r11 = (u16 *)paca + offset */
- sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
+ sldi r11,r3,2 /* r11 = offset * sizeof(u32) */
+ rldicl r10,r10,36,28 /* get the 36 bits of the ESID */
+ add r11,r11,r13 /* r11 = (u32 *)paca + offset */
+ stw r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
addi r3,r3,1 /* offset++ */
b 2f
1: /* offset >= SLB_CACHE_ENTRIES */
--
1.7.10
^ permalink raw reply related
* [PATCH -V1 7/9] arch/powerpc: Use 50 bits of VSID in slbmte
From: Aneesh Kumar K.V @ 2012-06-29 14:17 UTC (permalink / raw)
To: benh, paulus, michael, anton; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1340979457-26018-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Increase the number of valid VSID bits in slbmte instruction.
We will use the new bits when we increase valid VSID bits.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/slb_low.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index c355af6..c1fc81c 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -226,7 +226,7 @@ _GLOBAL(slb_allocate_user)
*/
slb_finish_load:
ASM_VSID_SCRAMBLE(r10,r9,256M)
- rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */
+ rldimi r11,r10,SLB_VSID_SHIFT,2 /* combine VSID and flags */
/* r3 = EA, r11 = VSID data */
/*
@@ -290,7 +290,7 @@ _GLOBAL(slb_compare_rr_to_size)
slb_finish_load_1T:
srdi r10,r10,40-28 /* get 1T ESID */
ASM_VSID_SCRAMBLE(r10,r9,1T)
- rldimi r11,r10,SLB_VSID_SHIFT_1T,16 /* combine VSID and flags */
+ rldimi r11,r10,SLB_VSID_SHIFT_1T,2 /* combine VSID and flags */
li r10,MMU_SEGSIZE_1T
rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
--
1.7.10
^ permalink raw reply related
* [PATCH -V1 6/9] arch/powerpc: Increase the slice range to 64TB
From: Aneesh Kumar K.V @ 2012-06-29 14:17 UTC (permalink / raw)
To: benh, paulus, michael, anton; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1340979457-26018-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
This patch makes the high psizes mask as an unsigned char array
so that we can have more than 16TB. Currently we support upto
64TB
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 7 ++-
arch/powerpc/include/asm/page_64.h | 7 ++-
arch/powerpc/mm/hash_utils_64.c | 15 +++---
arch/powerpc/mm/slb_low.S | 35 ++++++++----
arch/powerpc/mm/slice.c | 95 +++++++++++++++++++++------------
5 files changed, 109 insertions(+), 50 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index e48c66b..47ddfa1 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -456,7 +456,12 @@ typedef struct {
#ifdef CONFIG_PPC_MM_SLICES
u64 low_slices_psize; /* SLB page size encodings */
- u64 high_slices_psize; /* 4 bits per slice for now */
+ /*
+ * FIXME!! it should be derived from PGTABLE_RANGE
+ * Right now we support 64TB and 4 bits for each
+ * 1TB slice we need 32 bytes for 64TB.
+ */
+ unsigned char high_slices_psize[32]; /* 4 bits per slice for now */
#else
u16 sllp; /* SLB page size encoding */
#endif
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index fed85e6..8806e87 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -82,7 +82,12 @@ extern u64 ppc64_pft_size;
struct slice_mask {
u16 low_slices;
- u16 high_slices;
+ /*
+ * FIXME!!
+ * This should be derived out of PGTABLE_RANGE. For the current
+ * max 64TB, u64 should be ok.
+ */
+ u64 high_slices;
};
struct mm_struct;
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 8b5d3c2..beace0b 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -804,16 +804,19 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
#ifdef CONFIG_PPC_MM_SLICES
unsigned int get_paca_psize(unsigned long addr)
{
- unsigned long index, slices;
+ u64 lpsizes;
+ unsigned char *hpsizes;
+ unsigned long index, mask_index;
if (addr < SLICE_LOW_TOP) {
- slices = get_paca()->context.low_slices_psize;
+ lpsizes = get_paca()->context.low_slices_psize;
index = GET_LOW_SLICE_INDEX(addr);
- } else {
- slices = get_paca()->context.high_slices_psize;
- index = GET_HIGH_SLICE_INDEX(addr);
+ return (lpsizes >> (index * 4)) & 0xF;
}
- return (slices >> (index * 4)) & 0xF;
+ hpsizes = get_paca()->context.high_slices_psize;
+ index = GET_HIGH_SLICE_INDEX(addr) >> 1;
+ mask_index = GET_HIGH_SLICE_INDEX(addr) - (index << 1);
+ return (hpsizes[index] >> (mask_index * 4)) & 0xF;
}
#else
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index b9ee79ce..c355af6 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -108,17 +108,34 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
* between 4k and 64k standard page size
*/
#ifdef CONFIG_PPC_MM_SLICES
+ /* r10 have esid */
cmpldi r10,16
-
- /* Get the slice index * 4 in r11 and matching slice size mask in r9 */
- ld r9,PACALOWSLICESPSIZE(r13)
- sldi r11,r10,2
+ /* below SLICE_LOW_TOP */
blt 5f
- ld r9,PACAHIGHSLICEPSIZE(r13)
- srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT - 2)
- andi. r11,r11,0x3c
-
-5: /* Extract the psize and multiply to get an array offset */
+ /*
+ * Handle hpsizes,
+ * r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
+ * We use r10 here, later we restore it to esid.
+ * Can we use other register instead of r10 ?
+ */
+ srdi r10,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT) /* index */
+ srdi r11,r10,1 /* r11 is array index */
+ addi r9,r11,PACAHIGHSLICEPSIZE
+ lbzx r9,r9,r13 /* r9 is hpsizes[r11] */
+ sldi r11,r11,1
+ subf r11,r11,r10 /* mask_index = index - (array_index << 1) */
+ srdi r10,r3,28 /* restore r10 with esid */
+ b 6f
+5:
+ /*
+ * Handle lpsizes
+ * r9 is get_paca()->context.low_slices_psize, r11 is index
+ */
+ ld r9,PACALOWSLICESPSIZE(r13)
+ mr r11,r10
+6:
+ sldi r11,r11,2 /* index * 4 */
+ /* Extract the psize and multiply to get an array offset */
srd r9,r9,r11
andi. r9,r9,0xf
mulli r9,r9,MMUPSIZEDEFSIZE
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 73709f7..302a481 100644
--- a/arch/powerpc/mm/slice.c
+++ b/arch/powerpc/mm/slice.c
@@ -42,7 +42,7 @@ int _slice_debug = 1;
static void slice_print_mask(const char *label, struct slice_mask mask)
{
- char *p, buf[16 + 3 + 16 + 1];
+ char *p, buf[16 + 3 + 64 + 1];
int i;
if (!_slice_debug)
@@ -142,19 +142,24 @@ static struct slice_mask slice_mask_for_free(struct mm_struct *mm)
static struct slice_mask slice_mask_for_size(struct mm_struct *mm, int psize)
{
+ unsigned char *hpsizes;
+ int index, mask_index;
struct slice_mask ret = { 0, 0 };
unsigned long i;
- u64 psizes;
+ u64 lpsizes;
- psizes = mm->context.low_slices_psize;
+ lpsizes = mm->context.low_slices_psize;
for (i = 0; i < SLICE_NUM_LOW; i++)
- if (((psizes >> (i * 4)) & 0xf) == psize)
+ if (((lpsizes >> (i * 4)) & 0xf) == psize)
ret.low_slices |= 1u << i;
- psizes = mm->context.high_slices_psize;
- for (i = 0; i < SLICE_NUM_HIGH; i++)
- if (((psizes >> (i * 4)) & 0xf) == psize)
+ hpsizes = mm->context.high_slices_psize;
+ for (i = 0; i < SLICE_NUM_HIGH; i++) {
+ index = i >> 1;
+ mask_index = i - (index << 1);
+ if (((hpsizes[index] >> (mask_index * 4)) & 0xf) == psize)
ret.high_slices |= 1u << i;
+ }
return ret;
}
@@ -183,8 +188,10 @@ static void slice_flush_segments(void *parm)
static void slice_convert(struct mm_struct *mm, struct slice_mask mask, int psize)
{
+ int index, mask_index;
/* Write the new slice psize bits */
- u64 lpsizes, hpsizes;
+ unsigned char *hpsizes;
+ u64 lpsizes;
unsigned long i, flags;
slice_dbg("slice_convert(mm=%p, psize=%d)\n", mm, psize);
@@ -201,14 +208,18 @@ static void slice_convert(struct mm_struct *mm, struct slice_mask mask, int psiz
lpsizes = (lpsizes & ~(0xful << (i * 4))) |
(((unsigned long)psize) << (i * 4));
+ /* Assign the value back */
+ mm->context.low_slices_psize = lpsizes;
+
hpsizes = mm->context.high_slices_psize;
- for (i = 0; i < SLICE_NUM_HIGH; i++)
+ for (i = 0; i < SLICE_NUM_HIGH; i++) {
+ index = i >> 1;
+ mask_index = i - (index << 1);
if (mask.high_slices & (1u << i))
- hpsizes = (hpsizes & ~(0xful << (i * 4))) |
- (((unsigned long)psize) << (i * 4));
-
- mm->context.low_slices_psize = lpsizes;
- mm->context.high_slices_psize = hpsizes;
+ hpsizes[index] = (hpsizes[index] &
+ ~(0xf << (mask_index * 4))) |
+ (((unsigned long)psize) << (mask_index * 4));
+ }
slice_dbg(" lsps=%lx, hsps=%lx\n",
mm->context.low_slices_psize,
@@ -587,18 +598,19 @@ unsigned long arch_get_unmapped_area_topdown(struct file *filp,
unsigned int get_slice_psize(struct mm_struct *mm, unsigned long addr)
{
- u64 psizes;
- int index;
+ unsigned char *hpsizes;
+ int index, mask_index;
if (addr < SLICE_LOW_TOP) {
- psizes = mm->context.low_slices_psize;
+ u64 lpsizes;
+ lpsizes = mm->context.low_slices_psize;
index = GET_LOW_SLICE_INDEX(addr);
- } else {
- psizes = mm->context.high_slices_psize;
- index = GET_HIGH_SLICE_INDEX(addr);
+ return (lpsizes >> (index * 4)) & 0xf;
}
-
- return (psizes >> (index * 4)) & 0xf;
+ hpsizes = mm->context.high_slices_psize;
+ index = GET_HIGH_SLICE_INDEX(addr) >> 1;
+ mask_index = GET_HIGH_SLICE_INDEX(addr) - (index << 1);
+ return (hpsizes[index] >> (mask_index * 4)) & 0xf;
}
EXPORT_SYMBOL_GPL(get_slice_psize);
@@ -618,7 +630,9 @@ EXPORT_SYMBOL_GPL(get_slice_psize);
*/
void slice_set_user_psize(struct mm_struct *mm, unsigned int psize)
{
- unsigned long flags, lpsizes, hpsizes;
+ int index, mask_index;
+ unsigned char *hpsizes;
+ unsigned long flags, lpsizes;
unsigned int old_psize;
int i;
@@ -639,15 +653,21 @@ void slice_set_user_psize(struct mm_struct *mm, unsigned int psize)
if (((lpsizes >> (i * 4)) & 0xf) == old_psize)
lpsizes = (lpsizes & ~(0xful << (i * 4))) |
(((unsigned long)psize) << (i * 4));
+ /* Assign the value back */
+ mm->context.low_slices_psize = lpsizes;
hpsizes = mm->context.high_slices_psize;
- for (i = 0; i < SLICE_NUM_HIGH; i++)
- if (((hpsizes >> (i * 4)) & 0xf) == old_psize)
- hpsizes = (hpsizes & ~(0xful << (i * 4))) |
- (((unsigned long)psize) << (i * 4));
+ for (i = 0; i < SLICE_NUM_HIGH; i++) {
+ index = i >> 1;
+ mask_index = i - (index << 1);
+ if (((hpsizes[index] >> (mask_index * 4)) & 0xf) == old_psize)
+ hpsizes[index] = (hpsizes[index] &
+ ~(0xf << (mask_index * 4))) |
+ (((unsigned long)psize) << (mask_index * 4));
+ }
+
+
- mm->context.low_slices_psize = lpsizes;
- mm->context.high_slices_psize = hpsizes;
slice_dbg(" lsps=%lx, hsps=%lx\n",
mm->context.low_slices_psize,
@@ -660,18 +680,27 @@ void slice_set_user_psize(struct mm_struct *mm, unsigned int psize)
void slice_set_psize(struct mm_struct *mm, unsigned long address,
unsigned int psize)
{
+ unsigned char *hpsizes;
unsigned long i, flags;
- u64 *p;
+ u64 *lpsizes;
spin_lock_irqsave(&slice_convert_lock, flags);
if (address < SLICE_LOW_TOP) {
i = GET_LOW_SLICE_INDEX(address);
- p = &mm->context.low_slices_psize;
+ lpsizes = &mm->context.low_slices_psize;
+ *lpsizes = (*lpsizes & ~(0xful << (i * 4))) |
+ ((unsigned long) psize << (i * 4));
} else {
+ int index, mask_index;
i = GET_HIGH_SLICE_INDEX(address);
- p = &mm->context.high_slices_psize;
+ hpsizes = mm->context.high_slices_psize;
+ index = i >> 1;
+ mask_index = i - (index << 1);
+ hpsizes[index] = (hpsizes[index] &
+ ~(0xf << (mask_index * 4))) |
+ (((unsigned long)psize) << (mask_index * 4));
}
- *p = (*p & ~(0xful << (i * 4))) | ((unsigned long) psize << (i * 4));
+
spin_unlock_irqrestore(&slice_convert_lock, flags);
#ifdef CONFIG_SPU_BASE
--
1.7.10
^ permalink raw reply related
* [PATCH -V1 3/9] arch/powerpc: Simplify hpte_decode
From: Aneesh Kumar K.V @ 2012-06-29 14:17 UTC (permalink / raw)
To: benh, paulus, michael, anton; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1340979457-26018-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
This patch simplify hpte_decode for easy switching of virtual address to
vsid and segment offset combination in the later patch
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/hash_native_64.c | 51 ++++++++++++++++++++++----------------
1 file changed, 30 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index cab3892..76c2574 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -357,9 +357,10 @@ static void native_hpte_invalidate(unsigned long slot, struct virt_addr va,
static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
int *psize, int *ssize, struct virt_addr *va)
{
+ unsigned long avpn, pteg, vpi;
unsigned long hpte_r = hpte->r;
unsigned long hpte_v = hpte->v;
- unsigned long avpn;
+ unsigned long vsid, seg_off;
int i, size, shift, penc;
if (!(hpte_v & HPTE_V_LARGE))
@@ -386,32 +387,40 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
}
/* This works for all page sizes, and for 256M and 1T segments */
+ *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
shift = mmu_psize_defs[size].shift;
- avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm) << 23;
-
- if (shift < 23) {
- unsigned long vpi, vsid, pteg;
- pteg = slot / HPTES_PER_GROUP;
- if (hpte_v & HPTE_V_SECONDARY)
- pteg = ~pteg;
- switch (hpte_v >> HPTE_V_SSIZE_SHIFT) {
- case MMU_SEGSIZE_256M:
- vpi = ((avpn >> 28) ^ pteg) & htab_hash_mask;
- break;
- case MMU_SEGSIZE_1T:
- vsid = avpn >> 40;
+ avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
+ pteg = slot / HPTES_PER_GROUP;
+ if (hpte_v & HPTE_V_SECONDARY)
+ pteg = ~pteg;
+
+ switch (*ssize) {
+ case MMU_SEGSIZE_256M:
+ /* We only have 28 - 23 bits of seg_off in avpn */
+ seg_off = (avpn & 0x1f) << 23;
+ vsid = avpn >> 5;
+ /* We can find more bits from the pteg value */
+ if (shift < 23) {
+ vpi = (vsid ^ pteg) & htab_hash_mask;
+ seg_off |= vpi << shift;
+ }
+ va->addr = vsid << 28 | seg_off;
+ case MMU_SEGSIZE_1T:
+ /* We only have 40 - 23 bits of seg_off in avpn */
+ seg_off = (avpn & 0x1ffff) << 23;
+ vsid = avpn >> 17;
+ if (shift < 23) {
vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
- break;
- default:
- avpn = vpi = size = 0;
+ seg_off |= vpi << shift;
}
- avpn |= (vpi << mmu_psize_defs[size].shift);
+ va->addr = vsid << 40 | seg_off;
+ default:
+ seg_off = 0;
+ vsid = 0;
+ va->addr = 0;
}
-
- va->addr = avpn;
*psize = size;
- *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
}
/*
--
1.7.10
^ permalink raw reply related
* [PATCH -V1 5/9] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE
From: Aneesh Kumar K.V @ 2012-06-29 14:17 UTC (permalink / raw)
To: benh, paulus, michael, anton; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1340979457-26018-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
As we keep increasing PGTABLE_RANGE we need not increase the virual
map area for kernel.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/pgtable-ppc64.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index c420561..8af1cf2 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -41,7 +41,7 @@
#else
#define KERN_VIRT_START ASM_CONST(0xD000000000000000)
#endif
-#define KERN_VIRT_SIZE PGTABLE_RANGE
+#define KERN_VIRT_SIZE ASM_CONST(0x0000100000000000)
/*
* The vmalloc space starts at the beginning of that region, and
--
1.7.10
^ permalink raw reply related
* [PATCH -V1 4/9] arch/powerpc: Use vsid and segment offset to represent virtual address
From: Aneesh Kumar K.V @ 2012-06-29 14:17 UTC (permalink / raw)
To: benh, paulus, michael, anton; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1340979457-26018-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
This patch enables us to have 78 bit virtual address.
With 1TB segments we use 40 bits of virtual adress as segment offset and
the remaining 24 bits (of the current 64 bit virtual address) are used
to index the virtual segment. Out of the 24 bits we currently use 19 bits
for user context and that leave us with only 4 bits for effective segment
ID. In-order to support more than 16TB of memory we would require more than
4 ESID bits. This patch splits the virtual address to two unsigned long
components, vsid and segment offset thereby allowing us to support 78 bit
virtual address.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 62 ++++++++---
arch/powerpc/mm/hash_low_64.S | 191 ++++++++++++++++++---------------
arch/powerpc/mm/hash_native_64.c | 36 ++++---
arch/powerpc/mm/hash_utils_64.c | 6 +-
arch/powerpc/platforms/ps3/htab.c | 13 +--
arch/powerpc/platforms/pseries/lpar.c | 29 ++---
6 files changed, 192 insertions(+), 145 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 5ff936b..e48c66b 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -143,8 +143,10 @@ struct mmu_psize_def
unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
};
+/* 78 bit power virtual address */
struct virt_addr {
- unsigned long addr;
+ unsigned long vsid;
+ unsigned long seg_off;
};
#endif /* __ASSEMBLY__ */
@@ -161,6 +163,13 @@ struct virt_addr {
#ifndef __ASSEMBLY__
+static inline int segment_shift(int ssize)
+{
+ if (ssize == MMU_SEGSIZE_256M)
+ return SID_SHIFT;
+ return SID_SHIFT_1T;
+}
+
/*
* The current system page and segment sizes
*/
@@ -184,6 +193,32 @@ extern unsigned long tce_alloc_start, tce_alloc_end;
extern int mmu_ci_restrictions;
/*
+ * This computes the AVPN and B fields of the first dword of a HPTE,
+ * for use when we want to match an existing PTE. The bottom 7 bits
+ * of the returned value are zero.
+ */
+static inline unsigned long hpte_encode_avpn(struct virt_addr va, int psize,
+ int ssize)
+{
+ unsigned long v;
+
+ /*
+ * The AVA field omits the low-order 23 bits of the 78 bits VA.
+ * These bits are not needed in the PTE, because the
+ * low-order b of these bits are part of the byte offset
+ * into the virtual page and, if b < 23, the high-order
+ * 23-b of these bits are always used in selecting the
+ * PTEGs to be searched
+ */
+ v = va.seg_off >> 23;
+ v |= va.vsid << (segment_shift(ssize) - 23);
+ v &= ~(mmu_psize_defs[psize].avpnm);
+ v <<= HPTE_V_AVPN_SHIFT;
+ v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
+ return v;
+}
+
+/*
* This function sets the AVPN and L fields of the HPTE appropriately
* for the page size
*/
@@ -191,11 +226,9 @@ static inline unsigned long hpte_encode_v(struct virt_addr va, int psize,
int ssize)
{
unsigned long v;
- v = (va.addr >> 23) & ~(mmu_psize_defs[psize].avpnm);
- v <<= HPTE_V_AVPN_SHIFT;
+ v = hpte_encode_avpn(va, psize, ssize);
if (psize != MMU_PAGE_4K)
v |= HPTE_V_LARGE;
- v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
return v;
}
@@ -222,30 +255,31 @@ static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
/*
* Build a VA given VSID, EA and segment size
*/
-static inline struct virt_addr hpt_va(unsigned long ea, unsigned long vsid,
- int ssize)
+static inline struct virt_addr hpt_va(unsigned long ea, unsigned long vsid, int ssize)
{
struct virt_addr va;
+
+ va.vsid = vsid;
if (ssize == MMU_SEGSIZE_256M)
- va.addr = (vsid << 28) | (ea & 0xfffffffUL);
- va.addr = (vsid << 40) | (ea & 0xffffffffffUL);
+ va.seg_off = ea & 0xfffffffUL;
+ else
+ va.seg_off = ea & 0xffffffffffUL;
return va;
}
/*
* This hashes a virtual address
*/
-
-static inline unsigned long hpt_hash(struct virt_addr va, unsigned int shift,
- int ssize)
+/* Verify */
+static inline unsigned long hpt_hash(struct virt_addr va, unsigned int shift, int ssize)
{
unsigned long hash, vsid;
if (ssize == MMU_SEGSIZE_256M) {
- hash = (va.addr >> 28) ^ ((va.addr & 0x0fffffffUL) >> shift);
+ hash = (va.vsid & 0x0000007fffffffff) ^ (va.seg_off >> shift);
} else {
- vsid = va.addr >> 40;
- hash = vsid ^ (vsid << 25) ^ ((va.addr & 0xffffffffffUL) >> shift);
+ vsid = va.vsid;
+ hash = vsid ^ (vsid << 25) ^ (va.seg_off >> shift);
}
return hash & 0x7fffffffffUL;
}
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index a242b5d..cf66a0a 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -71,10 +71,12 @@ _GLOBAL(__hash_page_4K)
/* Save non-volatile registers.
* r31 will hold "old PTE"
* r30 is "new PTE"
- * r29 is "va"
+ * r29 is vsid
* r28 is a hash value
* r27 is hashtab mask (maybe dynamic patched instead ?)
+ * r26 is seg_off
*/
+ std r26,STK_REG(r26)(r1)
std r27,STK_REG(r27)(r1)
std r28,STK_REG(r28)(r1)
std r29,STK_REG(r29)(r1)
@@ -119,10 +121,9 @@ BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- /* Calc va and put it in r29 */
- rldicr r29,r5,28,63-28
- rldicl r3,r3,0,36
- or r29,r3,r29
+ /* r29 is virtual address and r26 is seg_off */
+ mr r29,r5 /* vsid */
+ rldicl r26,r3,0,36 /* ea & 0x000000000fffffffUL */
/* Calculate hash value for primary slot and store it in r28 */
rldicl r5,r5,0,25 /* vsid & 0x0000007fffffffff */
@@ -130,14 +131,17 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
xor r28,r5,r0
b 4f
-3: /* Calc VA and hash in r29 and r28 for 1T segment */
- sldi r29,r5,40 /* vsid << 40 */
- clrldi r3,r3,24 /* ea & 0xffffffffff */
+3: /* r29 is virtual address and r26 is seg_off */
+ mr r29,r5 /* vsid */
+ rldicl r26,r3,0,24 /* ea & 0xffffffffff */
+ /*
+ * calculate hash value for primary slot and
+ * store it in r28 for 1T segment
+ */
rldic r28,r5,25,25 /* (vsid << 25) & 0x7fffffffff */
clrldi r5,r5,40 /* vsid & 0xffffff */
rldicl r0,r3,64-12,36 /* (ea >> 12) & 0xfffffff */
xor r28,r28,r5
- or r29,r3,r29 /* VA */
xor r28,r28,r0 /* hash */
/* Convert linux PTE bits into HW equivalents */
@@ -183,20 +187,21 @@ htab_insert_pte:
andc r30,r30,r0
ori r30,r30,_PAGE_HASHPTE
- /* physical address r5 */
- rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
- sldi r5,r5,PAGE_SHIFT
+ /* physical address r6 */
+ rldicl r6,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
+ sldi r6,r6,PAGE_SHIFT
/* Calculate primary group hash */
and r0,r28,r27
rldicr r3,r0,3,63-3 /* r3 = (hash & mask) << 3 */
/* Call ppc_md.hpte_insert */
- ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
- li r7,0 /* !bolted, !secondary */
- li r8,MMU_PAGE_4K /* page size */
- ld r9,STK_PARM(r9)(r1) /* segment size */
+ ld r7,STK_PARM(r4)(r1) /* Retrieve new pp bits */
+ mr r4,r29 /* Retrieve vsid */
+ mr r5,r26 /* seg_off */
+ li r8,0 /* !bolted, !secondary */
+ li r9,MMU_PAGE_4K /* page size */
+ ld r10,STK_PARM(r9)(r1) /* segment size */
_GLOBAL(htab_call_hpte_insert1)
bl . /* Patched by htab_finish_init() */
cmpdi 0,r3,0
@@ -206,20 +211,21 @@ _GLOBAL(htab_call_hpte_insert1)
/* Now try secondary slot */
- /* physical address r5 */
- rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
- sldi r5,r5,PAGE_SHIFT
+ /* physical address r6 */
+ rldicl r6,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
+ sldi r6,r6,PAGE_SHIFT
/* Calculate secondary group hash */
andc r0,r27,r28
rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */
/* Call ppc_md.hpte_insert */
- ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
- li r7,HPTE_V_SECONDARY /* !bolted, secondary */
- li r8,MMU_PAGE_4K /* page size */
- ld r9,STK_PARM(r9)(r1) /* segment size */
+ ld r7,STK_PARM(r4)(r1) /* Retrieve new pp bits */
+ mr r4,r29 /* Retrieve vsid */
+ mr r5,r26 /* seg_off */
+ li r8,HPTE_V_SECONDARY /* !bolted, secondary */
+ li r9,MMU_PAGE_4K /* page size */
+ ld r10,STK_PARM(r9)(r1) /* segment size */
_GLOBAL(htab_call_hpte_insert2)
bl . /* Patched by htab_finish_init() */
cmpdi 0,r3,0
@@ -286,13 +292,13 @@ htab_modify_pte:
add r3,r0,r3 /* add slot idx */
/* Call ppc_md.hpte_updatepp */
- mr r5,r29 /* va */
- li r6,MMU_PAGE_4K /* page size */
- ld r7,STK_PARM(r9)(r1) /* segment size */
- ld r8,STK_PARM(r8)(r1) /* get "local" param */
+ mr r5,r29 /* vsid */
+ mr r6,r26 /* seg off */
+ li r7,MMU_PAGE_4K /* page size */
+ ld r8,STK_PARM(r9)(r1) /* segment size */
+ ld r9,STK_PARM(r8)(r1) /* get "local" param */
_GLOBAL(htab_call_hpte_updatepp)
bl . /* Patched by htab_finish_init() */
-
/* if we failed because typically the HPTE wasn't really here
* we try an insertion.
*/
@@ -347,12 +353,14 @@ _GLOBAL(__hash_page_4K)
/* Save non-volatile registers.
* r31 will hold "old PTE"
* r30 is "new PTE"
- * r29 is "va"
+ * r29 is vsid
* r28 is a hash value
* r27 is hashtab mask (maybe dynamic patched instead ?)
* r26 is the hidx mask
* r25 is the index in combo page
+ * r24 is seg_off
*/
+ std r24,STK_REG(r24)(r1)
std r25,STK_REG(r25)(r1)
std r26,STK_REG(r26)(r1)
std r27,STK_REG(r27)(r1)
@@ -402,10 +410,9 @@ BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- /* Calc va and put it in r29 */
- rldicr r29,r5,28,63-28 /* r29 = (vsid << 28) */
- rldicl r3,r3,0,36 /* r3 = (ea & 0x0fffffff) */
- or r29,r3,r29 /* r29 = va */
+ /* r29 is virtual address and r24 is seg_off */
+ mr r29,r5 /* vsid */
+ rldicl r24,r3,0,36 /* ea & 0x000000000fffffffUL */
/* Calculate hash value for primary slot and store it in r28 */
rldicl r5,r5,0,25 /* vsid & 0x0000007fffffffff */
@@ -413,14 +420,17 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
xor r28,r5,r0
b 4f
-3: /* Calc VA and hash in r29 and r28 for 1T segment */
- sldi r29,r5,40 /* vsid << 40 */
- clrldi r3,r3,24 /* ea & 0xffffffffff */
+3: /* r29 is virtual address and r24 is seg_off */
+ mr r29,r5 /* vsid */
+ rldicl r24,r3,0,24 /* ea & 0xffffffffff */
+ /*
+ * Calculate hash value for primary slot and
+ * store it in r28 for 1T segment
+ */
rldic r28,r5,25,25 /* (vsid << 25) & 0x7fffffffff */
clrldi r5,r5,40 /* vsid & 0xffffff */
rldicl r0,r3,64-12,36 /* (ea >> 12) & 0xfffffff */
xor r28,r28,r5
- or r29,r3,r29 /* VA */
xor r28,r28,r0 /* hash */
/* Convert linux PTE bits into HW equivalents */
@@ -481,25 +491,26 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
bne htab_modify_pte
htab_insert_pte:
- /* real page number in r5, PTE RPN value + index */
+ /* real page number in r6, PTE RPN value + index */
andis. r0,r31,_PAGE_4K_PFN@h
srdi r5,r31,PTE_RPN_SHIFT
bne- htab_special_pfn
sldi r5,r5,PAGE_SHIFT-HW_PAGE_SHIFT
add r5,r5,r25
htab_special_pfn:
- sldi r5,r5,HW_PAGE_SHIFT
+ sldi r6,r5,HW_PAGE_SHIFT
/* Calculate primary group hash */
and r0,r28,r27
rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
/* Call ppc_md.hpte_insert */
- ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
- li r7,0 /* !bolted, !secondary */
- li r8,MMU_PAGE_4K /* page size */
- ld r9,STK_PARM(r9)(r1) /* segment size */
+ ld r7,STK_PARM(r4)(r1) /* Retrieve new pp bits */
+ mr r4,r29 /* Retrieve vsid */
+ mr r5,r24 /* seg off */
+ li r8,0 /* !bolted, !secondary */
+ li r9,MMU_PAGE_4K /* page size */
+ ld r10,STK_PARM(r9)(r1) /* segment size */
_GLOBAL(htab_call_hpte_insert1)
bl . /* patched by htab_finish_init() */
cmpdi 0,r3,0
@@ -515,18 +526,19 @@ _GLOBAL(htab_call_hpte_insert1)
bne- 3f
sldi r5,r5,PAGE_SHIFT-HW_PAGE_SHIFT
add r5,r5,r25
-3: sldi r5,r5,HW_PAGE_SHIFT
+3: sldi r6,r5,HW_PAGE_SHIFT
/* Calculate secondary group hash */
andc r0,r27,r28
rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */
/* Call ppc_md.hpte_insert */
- ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
- li r7,HPTE_V_SECONDARY /* !bolted, secondary */
- li r8,MMU_PAGE_4K /* page size */
- ld r9,STK_PARM(r9)(r1) /* segment size */
+ ld r7,STK_PARM(r4)(r1) /* Retrieve new pp bits */
+ mr r4,r29 /* Retrieve vsid */
+ mr r5,r24 /* seg off */
+ li r8,HPTE_V_SECONDARY /* !bolted, secondary */
+ li r9,MMU_PAGE_4K /* page size */
+ ld r10,STK_PARM(r9)(r1) /* segment size */
_GLOBAL(htab_call_hpte_insert2)
bl . /* patched by htab_finish_init() */
cmpdi 0,r3,0
@@ -628,13 +640,13 @@ htab_modify_pte:
add r3,r0,r3 /* add slot idx */
/* Call ppc_md.hpte_updatepp */
- mr r5,r29 /* va */
- li r6,MMU_PAGE_4K /* page size */
- ld r7,STK_PARM(r9)(r1) /* segment size */
- ld r8,STK_PARM(r8)(r1) /* get "local" param */
+ mr r5,r29 /* vsid */
+ mr r6,r24 /* seg off */
+ li r7,MMU_PAGE_4K /* page size */
+ ld r8,STK_PARM(r9)(r1) /* segment size */
+ ld r9,STK_PARM(r8)(r1) /* get "local" param */
_GLOBAL(htab_call_hpte_updatepp)
bl . /* patched by htab_finish_init() */
-
/* if we failed because typically the HPTE wasn't really here
* we try an insertion.
*/
@@ -684,10 +696,12 @@ _GLOBAL(__hash_page_64K)
/* Save non-volatile registers.
* r31 will hold "old PTE"
* r30 is "new PTE"
- * r29 is "va"
+ * r29 is vsid
* r28 is a hash value
* r27 is hashtab mask (maybe dynamic patched instead ?)
+ * r26 is seg off
*/
+ std r26,STK_REG(r26)(r1)
std r27,STK_REG(r27)(r1)
std r28,STK_REG(r28)(r1)
std r29,STK_REG(r29)(r1)
@@ -737,10 +751,9 @@ BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- /* Calc va and put it in r29 */
- rldicr r29,r5,28,63-28
- rldicl r3,r3,0,36
- or r29,r3,r29
+ /* r29 is virtual address and r26 is seg_off */
+ mr r29,r5 /* vsid */
+ rldicl r26,r3,0,36 /* ea & 0x000000000fffffffUL */
/* Calculate hash value for primary slot and store it in r28 */
rldicl r5,r5,0,25 /* vsid & 0x0000007fffffffff */
@@ -748,14 +761,17 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
xor r28,r5,r0
b 4f
-3: /* Calc VA and hash in r29 and r28 for 1T segment */
- sldi r29,r5,40 /* vsid << 40 */
- clrldi r3,r3,24 /* ea & 0xffffffffff */
+3: /* r29 is virtual address and r26 is seg_off */
+ mr r29,r5 /* vsid */
+ rldicl r26,r3,0,24 /* ea & 0xffffffffff */
+ /*
+ * calculate hash value for primary slot and
+ * store it in r28 for 1T segment
+ */
rldic r28,r5,25,25 /* (vsid << 25) & 0x7fffffffff */
clrldi r5,r5,40 /* vsid & 0xffffff */
rldicl r0,r3,64-16,40 /* (ea >> 16) & 0xffffff */
xor r28,r28,r5
- or r29,r3,r29 /* VA */
xor r28,r28,r0 /* hash */
/* Convert linux PTE bits into HW equivalents */
@@ -804,20 +820,21 @@ ht64_insert_pte:
#else
ori r30,r30,_PAGE_HASHPTE
#endif
- /* Phyical address in r5 */
- rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
- sldi r5,r5,PAGE_SHIFT
+ /* Phyical address in r6 */
+ rldicl r6,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
+ sldi r6,r6,PAGE_SHIFT
/* Calculate primary group hash */
and r0,r28,r27
rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
/* Call ppc_md.hpte_insert */
- ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
- li r7,0 /* !bolted, !secondary */
- li r8,MMU_PAGE_64K
- ld r9,STK_PARM(r9)(r1) /* segment size */
+ ld r7,STK_PARM(r4)(r1) /* Retrieve new pp bits */
+ mr r4,r29 /* Retrieve vsid */
+ mr r5,r26 /* seg_off */
+ li r8,0 /* !bolted, !secondary */
+ li r9,MMU_PAGE_64K
+ ld r10,STK_PARM(r9)(r1) /* segment size */
_GLOBAL(ht64_call_hpte_insert1)
bl . /* patched by htab_finish_init() */
cmpdi 0,r3,0
@@ -827,20 +844,21 @@ _GLOBAL(ht64_call_hpte_insert1)
/* Now try secondary slot */
- /* Phyical address in r5 */
- rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
- sldi r5,r5,PAGE_SHIFT
+ /* Phyical address in r6 */
+ rldicl r6,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
+ sldi r6,r6,PAGE_SHIFT
/* Calculate secondary group hash */
andc r0,r27,r28
rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */
/* Call ppc_md.hpte_insert */
- ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
- li r7,HPTE_V_SECONDARY /* !bolted, secondary */
- li r8,MMU_PAGE_64K
- ld r9,STK_PARM(r9)(r1) /* segment size */
+ ld r7,STK_PARM(r4)(r1) /* Retrieve new pp bits */
+ mr r4,r29 /* Retrieve vsid */
+ mr r5,r26 /* seg_off */
+ li r8,HPTE_V_SECONDARY /* !bolted, secondary */
+ li r9,MMU_PAGE_64K
+ ld r10,STK_PARM(r9)(r1) /* segment size */
_GLOBAL(ht64_call_hpte_insert2)
bl . /* patched by htab_finish_init() */
cmpdi 0,r3,0
@@ -907,10 +925,11 @@ ht64_modify_pte:
add r3,r0,r3 /* add slot idx */
/* Call ppc_md.hpte_updatepp */
- mr r5,r29 /* va */
- li r6,MMU_PAGE_64K
- ld r7,STK_PARM(r9)(r1) /* segment size */
- ld r8,STK_PARM(r8)(r1) /* get "local" param */
+ mr r5,r29 /* vsid */
+ mr r6,r26 /* seg off */
+ li r7,MMU_PAGE_64K
+ ld r8,STK_PARM(r9)(r1) /* segment size */
+ ld r9,STK_PARM(r8)(r1) /* get "local" param */
_GLOBAL(ht64_call_hpte_updatepp)
bl . /* patched by htab_finish_init() */
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 76c2574..d65b63c 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -42,10 +42,12 @@ DEFINE_RAW_SPINLOCK(native_tlbie_lock);
/* Verify docs says 14 .. 14+i bits */
static inline void __tlbie(struct virt_addr va, int psize, int ssize)
{
- unsigned long vaddr = va.addr;
+ unsigned long vaddr;
unsigned int penc;
- vaddr &= ~(0xffffULL << 48);
+ /* We need only lower 48 bit of va, non SLS segment */
+ vaddr = va.vsid << segment_shift(ssize);
+ vaddr |= va.seg_off;
/* clear top 16 bits, non SLS segment */
vaddr &= ~(0xffffULL << 48);
@@ -74,9 +76,13 @@ static inline void __tlbie(struct virt_addr va, int psize, int ssize)
/* Verify docs says 14 .. 14+i bits */
static inline void __tlbiel(struct virt_addr va, int psize, int ssize)
{
- unsigned long vaddr = va.addr;
+ unsigned long vaddr;
unsigned int penc;
+ /* We need only lower 48 bit of va, non SLS segment */
+ vaddr = va.vsid << segment_shift(ssize);
+ vaddr |= va.seg_off;
+
vaddr &= ~(0xffffULL << 48);
switch (psize) {
@@ -148,9 +154,9 @@ static long native_hpte_insert(unsigned long hpte_group, struct virt_addr va,
int i;
if (!(vflags & HPTE_V_BOLTED)) {
- DBG_LOW(" insert(group=%lx, va=%016lx, pa=%016lx,"
- " rflags=%lx, vflags=%lx, psize=%d)\n",
- hpte_group, va, pa, rflags, vflags, psize);
+ DBG_LOW(" insert(group=%lx, vsid=%016lx, seg_off=%016lx, pa=%016lx,"
+ " rflags=%lx, vflags=%lx, psize=%d)\n", hpte_group,
+ va.vsid, va.seg_off, pa, rflags, vflags, psize);
}
for (i = 0; i < HPTES_PER_GROUP; i++) {
@@ -239,8 +245,9 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
want_v = hpte_encode_v(va, psize, ssize);
- DBG_LOW(" update(va=%016lx, avpnv=%016lx, hash=%016lx, newpp=%x)",
- va, want_v & HPTE_V_AVPN, slot, newpp);
+ DBG_LOW(" update(vsid=%016lx, seg_off=%016lx, avpnv=%016lx, "
+ "hash=%016lx, newpp=%lx)", va.vsid, va.seg_off,
+ want_v & HPTE_V_AVPN, slot, newpp);
native_lock_hpte(hptep);
@@ -331,7 +338,7 @@ static void native_hpte_invalidate(unsigned long slot, struct virt_addr va,
local_irq_save(flags);
- DBG_LOW(" invalidate(va=%016lx, hash: %x)\n", va, slot);
+ DBG_LOW(" invalidate(va=%016lx, seg=%016lx, hash: %lx)\n", va.vsid, va.seg_off, slot);
want_v = hpte_encode_v(va, psize, ssize);
native_lock_hpte(hptep);
@@ -405,7 +412,6 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
vpi = (vsid ^ pteg) & htab_hash_mask;
seg_off |= vpi << shift;
}
- va->addr = vsid << 28 | seg_off;
case MMU_SEGSIZE_1T:
/* We only have 40 - 23 bits of seg_off in avpn */
seg_off = (avpn & 0x1ffff) << 23;
@@ -414,12 +420,12 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
seg_off |= vpi << shift;
}
- va->addr = vsid << 40 | seg_off;
default:
seg_off = 0;
vsid = 0;
- va->addr = 0;
}
+ va->vsid = vsid;
+ va->seg_off = seg_off;
*psize = size;
}
@@ -499,7 +505,7 @@ static void native_flush_hash_range(unsigned long number, int local)
va = batch->vaddr[i];
pte = batch->pte[i];
- pte_iterate_hashed_subpages(pte, psize, va.addr, index, shift) {
+ pte_iterate_hashed_subpages(pte, psize, va.seg_off, index, shift) {
hash = hpt_hash(va, shift, ssize);
hidx = __rpte_to_hidx(pte, index);
if (hidx & _PTEIDX_SECONDARY)
@@ -525,7 +531,7 @@ static void native_flush_hash_range(unsigned long number, int local)
va = batch->vaddr[i];
pte = batch->pte[i];
- pte_iterate_hashed_subpages(pte, psize, va.addr, index,
+ pte_iterate_hashed_subpages(pte, psize, va.seg_off, index,
shift) {
__tlbiel(va, psize, ssize);
} pte_iterate_hashed_end();
@@ -542,7 +548,7 @@ static void native_flush_hash_range(unsigned long number, int local)
va = batch->vaddr[i];
pte = batch->pte[i];
- pte_iterate_hashed_subpages(pte, psize, va.addr, index,
+ pte_iterate_hashed_subpages(pte, psize, va.seg_off, index,
shift) {
__tlbie(va, psize, ssize);
} pte_iterate_hashed_end();
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 2429d53..8b5d3c2 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -1158,8 +1158,10 @@ void flush_hash_page(struct virt_addr va, real_pte_t pte, int psize, int ssize,
{
unsigned long hash, index, shift, hidx, slot;
- DBG_LOW("flush_hash_page(va=%016lx)\n", va.addr);
- pte_iterate_hashed_subpages(pte, psize, va.addr, index, shift) {
+ DBG_LOW("flush_hash_page(vsid=%016lx seg_off=%016lx)\n",
+ va.vsid, va.seg_off);
+ /* since we won't cross segments, use seg_off for iteration */
+ pte_iterate_hashed_subpages(pte, psize, va.seg_off, index, shift) {
hash = hpt_hash(va, shift, ssize);
hidx = __rpte_to_hidx(pte, index);
if (hidx & _PTEIDX_SECONDARY)
diff --git a/arch/powerpc/platforms/ps3/htab.c b/arch/powerpc/platforms/ps3/htab.c
index 6e27576..4aa969d 100644
--- a/arch/powerpc/platforms/ps3/htab.c
+++ b/arch/powerpc/platforms/ps3/htab.c
@@ -75,8 +75,9 @@ static long ps3_hpte_insert(unsigned long hpte_group, struct virt_addr va,
if (result) {
/* all entries bolted !*/
- pr_info("%s:result=%d va=%lx pa=%lx ix=%lx v=%llx r=%llx\n",
- __func__, result, va, pa, hpte_group, hpte_v, hpte_r);
+ pr_info("%s:result=%d vsid=%lx seg_off=%lx pa=%lx ix=%lx "
+ "v=%llx r=%llx\n", __func__, result, va.vsid,
+ va.seg_off, pa, hpte_group, hpte_v, hpte_r);
BUG();
}
@@ -125,8 +126,8 @@ static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp,
&hpte_rs);
if (result) {
- pr_info("%s: res=%d read va=%lx slot=%lx psize=%d\n",
- __func__, result, va, slot, psize);
+ pr_info("%s: res=%d read vsid=%lx seg_off=%lx slot=%lx psize=%d\n",
+ __func__, result, va.vsid, va.seg_off, slot, psize);
BUG();
}
@@ -170,8 +171,8 @@ static void ps3_hpte_invalidate(unsigned long slot, struct virt_addr va,
result = lv1_write_htab_entry(PS3_LPAR_VAS_ID_CURRENT, slot, 0, 0);
if (result) {
- pr_info("%s: res=%d va=%lx slot=%lx psize=%d\n",
- __func__, result, va, slot, psize);
+ pr_info("%s: res=%d vsid=%lx seg_off=%lx slot=%lx psize=%d\n",
+ __func__, result, va.vsid, va.seg_off, slot, psize);
BUG();
}
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index b4e9641..4c0848f 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -118,9 +118,10 @@ static long pSeries_lpar_hpte_insert(unsigned long hpte_group,
unsigned long hpte_v, hpte_r;
if (!(vflags & HPTE_V_BOLTED))
- pr_devel("hpte_insert(group=%lx, va=%016lx, pa=%016lx, "
- "rflags=%lx, vflags=%lx, psize=%d)\n",
- hpte_group, va.addr, pa, rflags, vflags, psize);
+ pr_devel("hpte_insert(group=%lx, vsid=%016lx, segoff=%016lx, "
+ "pa=%016lx, rflags=%lx, vflags=%lx, psize=%d)\n",
+ hpte_group, va.vsid, va.seg_off,
+ pa, rflags, vflags, psize);
hpte_v = hpte_encode_v(va, psize, ssize) | vflags | HPTE_V_VALID;
hpte_r = hpte_encode_r(pa, psize) | rflags;
@@ -227,22 +228,6 @@ static void pSeries_lpar_hptab_clear(void)
}
/*
- * This computes the AVPN and B fields of the first dword of a HPTE,
- * for use when we want to match an existing PTE. The bottom 7 bits
- * of the returned value are zero.
- */
-static inline unsigned long hpte_encode_avpn(struct virt_addr va, int psize,
- int ssize)
-{
- unsigned long v;
-
- v = (va.addr >> 23) & ~(mmu_psize_defs[psize].avpnm);
- v <<= HPTE_V_AVPN_SHIFT;
- v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
- return v;
-}
-
-/*
* NOTE: for updatepp ops we are fortunate that the linux "newpp" bits and
* the low 3 bits of flags happen to line up. So no transform is needed.
* We can probably optimize here and assume the high bits of newpp are
@@ -345,8 +330,8 @@ static void pSeries_lpar_hpte_invalidate(unsigned long slot, struct virt_addr va
unsigned long lpar_rc;
unsigned long dummy1, dummy2;
- pr_devel(" inval : slot=%lx, va=%016lx, psize: %d, local: %d\n",
- slot, va.addr, psize, local);
+ pr_devel(" inval : slot=%lx, vsid=%016lx, seg_off=%016lx, psize: %d, local: %d\n",
+ slot, va.vsid, va.seg_off, psize, local);
want_v = hpte_encode_avpn(va, psize, ssize);
lpar_rc = plpar_pte_remove(H_AVPN, slot, want_v, &dummy1, &dummy2);
@@ -403,7 +388,7 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
for (i = 0; i < number; i++) {
va = batch->vaddr[i];
pte = batch->pte[i];
- pte_iterate_hashed_subpages(pte, psize, va.addr, index, shift) {
+ pte_iterate_hashed_subpages(pte, psize, va.seg_off, index, shift) {
hash = hpt_hash(va, shift, ssize);
hidx = __rpte_to_hidx(pte, index);
if (hidx & _PTEIDX_SECONDARY)
--
1.7.10
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