* Re: [PATCH 2/3] VFIO: VFIO_DEVICE_SET_ADDR_MAPPING command
From: Benjamin Herrenschmidt @ 2013-03-16 5:37 UTC (permalink / raw)
To: Gavin Shan; +Cc: aik, Alex Williamson, linuxppc-dev, kvm
In-Reply-To: <20130316013417.GA3873@shangw.(null)>
On Sat, 2013-03-16 at 09:34 +0800, Gavin Shan wrote:
> >Could you explain further how this will be used? How the device is
> >exposed to a guest is entirely a userspace construct, so why does vfio
> >need to know or care about this? I had assumed for AER that QEMU would
> >do the translation from host to guest address space.
> >
>
> The weak IOCTL function (vfio_pci_arch_ioctl) was introduced by previous
> patch. The PowerNV platform is going to override it to figure out the
> information for EEH core to use. On the other hand, QEMU will runs into
> the IOCTL command while opening (creating) one VFIO device.
>
> Though I'm not familiar with AER very much. AER is quite different from
> EEH. The EEH functionality implemented in PHB instead of in PCI device
> core. So we don't care AER stuff in EEH directly :-)
To give Alex a bit more background...
EEH is our IBM specific error handling facility which is a superset of AER.
IE. In addition to AER's error detection and logging, it adds a layer of
error detection at the host bridge level (such as iommu violations etc...)
and a mechanism for handling and recovering from errors. This is tied to
our iommu domain stuff (our PE's) and our device "freezing" capability
among others.
With VFIO + KVM, we want to implement most of the EEH support for guests in
the host kernel. The reason is multipart and we can discuss this separately
as some of it might well be debatable (mostly it's more convenient that way
because we hook into the underlying HW/FW EEH which isn't directly userspace
accessible so we don't have to add a new layer of kernel -> user API in
addition to the VFIO stuff), but there's at least one aspect of it that drives
this requirement more strongly which is performance:
When EEH is enabled, whenever any MMIO returns all 1's, the kernel will do
a firmware call to query the EEH state of the device and check whether it
has been frozen. On some devices, that can be a performance issue, and
going all the way to qemu for that would be horribly expensive.
So we want at least a way to handle that call in the kernel and for that we
need at least some way of mapping things there.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: add Book E support to 64-bit hibernation
From: Johannes Berg @ 2013-03-15 15:22 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, Wang Dongsheng
In-Reply-To: <1363279961.28440.4@snotra>
On Thu, 2013-03-14 at 11:52 -0500, Scott Wood wrote:
> > > +#ifdef CONFIG_PPC_BOOK3S_64
> > > /* can't use RESTORE_SPECIAL(MSR) */
> > > ld r0, SL_MSR(r11)
> > > mtmsrd r0, 0
> >
> > Unfortunately, I forgot the reason for this comment, and didn't put a
> > better one (almost 6 years ago!!)
> If it's because book3s needs mtmsrd instead of mtmsr, that doesn't
> apply to booke.
Indeed, looking at the code again now that seems pretty obvious.
Looking at the patch again, I'd be a little concerned about the lack of
cache flushing, seems a bit odd but I'm sure you know what you're doing
(and I don't know book3e at all, and hardly remember book3s -- or even
that name...) :-)
johannes
^ permalink raw reply
* Kernel panic on PowerMac G5 while scanning for SMU sensors
From: Phileas Fogg @ 2013-03-17 12:07 UTC (permalink / raw)
To: linuxppc-dev
I wanted to read the temperature sensors of my PowerMac G5 11,2.
For that i installed the lm-sensors package, run 'sensors-detect'
command and my Linux 3.8.2 kernel paniced in
_smu_i2c_low_completion_
with this message
'Unable to handle kernel paging request for data at address 0x00000008.'
Regards
^ permalink raw reply
* Re: Kernel panic on PowerMac G5 while scanning for SMU sensors
From: Phileas Fogg @ 2013-03-17 12:42 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <5145B20C.2090104@mail.ru>
On 03/17/2013 01:07 PM, Phileas Fogg wrote:
>
> I wanted to read the temperature sensors of my PowerMac G5 11,2.
> For that i installed the lm-sensors package, run 'sensors-detect'
> command and my Linux 3.8.2 kernel paniced in
>
> _smu_i2c_low_completion_
>
> with this message
>
> 'Unable to handle kernel paging request for data at address 0x00000008.'
>
> Regards
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
A further analysis showed that it crashes in _smu_i2c_complete_command_
which is called from _smu_i2c_low_completion_.
This line caused the panic:
list_del(&cmd->link);
regards
^ permalink raw reply
* RE: [PATCH 5/5 v9] iommu/fsl: Freescale PAMU driver and iommu implementation.
From: Sethi Varun-B16395 @ 2013-03-17 15:48 UTC (permalink / raw)
To: Kumar Gala
Cc: Wood Scott-B07421, linux-kernel@vger.kernel.org,
Yoder Stuart-B08248, iommu@lists.linux-foundation.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <0080B56D-8417-41B9-8341-665457D04DE6@kernel.crashing.org>
> -----Original Message-----
> From: iommu-bounces@lists.linux-foundation.org [mailto:iommu-
> bounces@lists.linux-foundation.org] On Behalf Of Kumar Gala
> Sent: Friday, March 15, 2013 1:50 AM
> To: Sethi Varun-B16395
> Cc: benh@kernel.crashing.org; linux-kernel@vger.kernel.org; Yoder Stuart-
> B08248; iommu@lists.linux-foundation.org; Wood Scott-B07421; linuxppc-
> dev@lists.ozlabs.org
> Subject: Re: [PATCH 5/5 v9] iommu/fsl: Freescale PAMU driver and iommu
> implementation.
>=20
>=20
> On Mar 13, 2013, at 1:49 PM, Varun Sethi wrote:
>=20
> > +/*
> > + * Table of SVRs and the corresponding PORT_ID values.
> > + *
> > + * All future CoreNet-enabled SOCs will have this erratum fixed, so
> > +this table
> > + * should never need to be updated. SVRs are guaranteed to be
> > +unique, so
> > + * there is no worry that a future SOC will inadvertently have one of
> > +these
> > + * values.
> > + */
>=20
> Maybe add to the comment about what port_id represents
>=20
[Sethi Varun-B16395] ok.
> > +static const struct {
> > + u32 svr;
> > + u32 port_id;
> > +} port_id_map[] =3D {
> > + {0x82100010, 0xFF000000}, /* P2040 1.0 */
> > + {0x82100011, 0xFF000000}, /* P2040 1.1 */
> > + {0x82100110, 0xFF000000}, /* P2041 1.0 */
> > + {0x82100111, 0xFF000000}, /* P2041 1.1 */
> > + {0x82110310, 0xFF000000}, /* P3041 1.0 */
> > + {0x82110311, 0xFF000000}, /* P3041 1.1 */
> > + {0x82010020, 0xFFF80000}, /* P4040 2.0 */
> > + {0x82000020, 0xFFF80000}, /* P4080 2.0 */
> > + {0x82210010, 0xFC000000}, /* P5010 1.0 */
> > + {0x82210020, 0xFC000000}, /* P5010 2.0 */
> > + {0x82200010, 0xFC000000}, /* P5020 1.0 */
> > + {0x82050010, 0xFF800000}, /* P5021 1.0 */
> > + {0x82040010, 0xFF800000}, /* P5040 1.0 */
> > +};
> > +
> > +#define SVR_SECURITY 0x80000 /* The Security (E) bit */
> > +
> > +static int __init fsl_pamu_probe(struct platform_device *pdev) {
> > + void __iomem *pamu_regs =3D NULL;
> > + struct ccsr_guts __iomem *guts_regs =3D NULL;
> > + u32 pamubypenr, pamu_counter;
> > + unsigned long pamu_reg_off;
> > + unsigned long pamu_reg_base;
> > + struct pamu_isr_data *data;
> > + struct device_node *guts_node;
> > + u64 size;
> > + struct page *p;
> > + int ret =3D 0;
> > + int irq;
> > + phys_addr_t ppaact_phys;
> > + phys_addr_t spaact_phys;
> > + phys_addr_t omt_phys;
> > + size_t mem_size =3D 0;
> > + unsigned int order =3D 0;
> > + u32 csd_port_id =3D 0;
> > + unsigned i;
> > + /*
> > + * enumerate all PAMUs and allocate and setup PAMU tables
> > + * for each of them,
> > + * NOTE : All PAMUs share the same LIODN tables.
> > + */
> > +
> > + pamu_regs =3D of_iomap(pdev->dev.of_node, 0);
> > + if (!pamu_regs) {
> > + dev_err(&pdev->dev, "ioremap of PAMU node failed\n");
> > + return -ENOMEM;
> > + }
> > + of_get_address(pdev->dev.of_node, 0, &size, NULL);
> > +
> > + irq =3D irq_of_parse_and_map(pdev->dev.of_node, 0);
> > + if (irq =3D=3D NO_IRQ) {
> > + dev_warn(&pdev->dev, "no interrupts listed in PAMU node\n");
> > + goto error;
> > + }
> > +
> > + data =3D kzalloc(sizeof(struct pamu_isr_data), GFP_KERNEL);
> > + if (!data) {
> > + iounmap(pamu_regs);
> > + return -ENOMEM;
> > + }
> > + data->pamu_reg_base =3D pamu_regs;
> > + data->count =3D size / PAMU_OFFSET;
> > +
> > + /* The ISR needs access to the regs, so we won't iounmap them */
> > + ret =3D request_irq(irq, pamu_av_isr, 0, "pamu", data);
> > + if (ret < 0) {
> > + dev_err(&pdev->dev, "error %i installing ISR for irq %i\n",
> > + ret, irq);
> > + goto error;
> > + }
> > +
> > + guts_node =3D of_find_compatible_node(NULL, NULL,
> > + "fsl,qoriq-device-config-1.0");
>=20
> This doesn't work for T4 or B4 device trees.
>=20
[Sethi Varun-B16395]hmm.... I need to use the dcfg space for this.
> > + if (!guts_node) {
> > + dev_err(&pdev->dev, "could not find GUTS node %s\n",
> > + pdev->dev.of_node->full_name);
> > + ret =3D -ENODEV;
> > + goto error;
> > + }
> > +
> > + guts_regs =3D of_iomap(guts_node, 0);
> > + of_node_put(guts_node);
> > + if (!guts_regs) {
> > + dev_err(&pdev->dev, "ioremap of GUTS node failed\n");
> > + ret =3D -ENODEV;
> > + goto error;
> > + }
> > +
> > + /* read in the PAMU capability registers */
> > + get_pamu_cap_values((unsigned long)pamu_regs);
> > + /*
> > + * To simplify the allocation of a coherency domain, we allocate
> the
> > + * PAACT and the OMT in the same memory buffer. Unfortunately,
> this
> > + * wastes more memory compared to allocating the buffers
> separately.
> > + */
> > + /* Determine how much memory we need */
> > + mem_size =3D (PAGE_SIZE << get_order(PAACT_SIZE)) +
> > + (PAGE_SIZE << get_order(SPAACT_SIZE)) +
> > + (PAGE_SIZE << get_order(OMT_SIZE));
> > + order =3D get_order(mem_size);
> > +
> > + p =3D alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
> > + if (!p) {
> > + dev_err(&pdev->dev, "unable to allocate PAACT/SPAACT/OMT
> block\n");
> > + ret =3D -ENOMEM;
> > + goto error;
> > + }
> > +
> > + ppaact =3D page_address(p);
> > + ppaact_phys =3D page_to_phys(p);
> > +
> > + /* Make sure the memory is naturally aligned */
> > + if (ppaact_phys & ((PAGE_SIZE << order) - 1)) {
> > + dev_err(&pdev->dev, "PAACT/OMT block is unaligned\n");
> > + ret =3D -ENOMEM;
> > + goto error;
> > + }
> > +
> > + spaact =3D (void *)ppaact + (PAGE_SIZE << get_order(PAACT_SIZE));
> > + omt =3D (void *)spaact + (PAGE_SIZE << get_order(SPAACT_SIZE));
> > +
> > + dev_dbg(&pdev->dev, "ppaact virt=3D%p phys=3D0x%llx\n", ppaact,
> > + (unsigned long long) ppaact_phys);
> > +
> > + /* Check to see if we need to implement the work-around on this SOC
> > +*/
> > +
> > + /* Determine the Port ID for our coherence subdomain */
> > + for (i =3D 0; i < ARRAY_SIZE(port_id_map); i++) {
> > + if (port_id_map[i].svr =3D=3D (mfspr(SPRN_SVR) & ~SVR_SECURITY))
> {
> > + csd_port_id =3D port_id_map[i].port_id;
> > + dev_dbg(&pdev->dev, "found matching SVR %08x\n",
> > + port_id_map[i].svr);
> > + break;
> > + }
> > + }
> > +
> > + if (csd_port_id) {
> > + dev_dbg(&pdev->dev, "creating coherency subdomain at address
> "
> > + "0x%llx, size %zu, port id 0x%08x", ppaact_phys,
> > + mem_size, csd_port_id);
> > +
> > + ret =3D create_csd(ppaact_phys, mem_size, csd_port_id);
> > + if (ret) {
> > + dev_err(&pdev->dev, "could not create coherence "
> > + "subdomain\n");
> > + return ret;
> > + }
> > + }
> > +
> > + spaact_phys =3D virt_to_phys(spaact);
> > + omt_phys =3D virt_to_phys(omt);
> > +
> > + spaace_pool =3D gen_pool_create(ilog2(sizeof(struct paace)), -1);
> > + if (!spaace_pool) {
> > + ret =3D -ENOMEM;
> > + dev_err(&pdev->dev, "PAMU : failed to allocate spaace gen
> pool\n");
> > + goto error;
> > + }
> > +
> > + ret =3D gen_pool_add(spaace_pool, (unsigned long)spaact, SPAACT_SIZE,
> -1);
> > + if (ret)
> > + goto error_genpool;
> > +
> > + pamubypenr =3D in_be32(&guts_regs->pamubypenr);
> > +
> > + for (pamu_reg_off =3D 0, pamu_counter =3D 0x80000000; pamu_reg_off <
> size;
> > + pamu_reg_off +=3D PAMU_OFFSET, pamu_counter >>=3D 1) {
> > +
> > + pamu_reg_base =3D (unsigned long) pamu_regs + pamu_reg_off;
> > + setup_one_pamu(pamu_reg_base, pamu_reg_off, ppaact_phys,
> > + spaact_phys, omt_phys);
> > + /* Disable PAMU bypass for this PAMU */
> > + pamubypenr &=3D ~pamu_counter;
> > + }
> > +
> > + setup_omt(omt);
> > +
> > + /* Enable all relevant PAMU(s) */
> > + out_be32(&guts_regs->pamubypenr, pamubypenr);
> > +
> > + iounmap(guts_regs);
> > +
> > + /* Enable DMA for the LIODNs in the device tree*/
> > +
> > + setup_liodns();
> > +
> > + return 0;
> > +
> > +error_genpool:
> > + gen_pool_destroy(spaace_pool);
> > +
> > +error:
> > + if (irq !=3D NO_IRQ)
> > + free_irq(irq, 0);
>=20
> Should be:
>=20
> free_irq(irq, data);
>=20
[Sethi Varun-B16395] Yes.
> > +
> > + if (pamu_regs)
> > + iounmap(pamu_regs);
> > +
> > + if (guts_regs)
> > + iounmap(guts_regs);
> > +
> > + if (ppaact)
> > + free_pages((unsigned long)ppaact, order);
> > +
> > + ppaact =3D NULL;
> > +
>=20
> you alloc data, shouldn't you free it ?
>=20
[Sethi Varun-B16395] Yes.
-Varun
^ permalink raw reply
* RE: [PATCH 5/5 v9] iommu/fsl: Freescale PAMU driver and iommu implementation.
From: Sethi Varun-B16395 @ 2013-03-17 15:49 UTC (permalink / raw)
To: Kumar Gala
Cc: Wood Scott-B07421, joro@8bytes.org, linux-kernel@vger.kernel.org,
Yoder Stuart-B08248, iommu@lists.linux-foundation.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <DF9A711B-63AF-411C-84E4-0C9F61A2EB21@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Friday, March 15, 2013 1:53 AM
> To: Sethi Varun-B16395
> Cc: joro@8bytes.org; linux-kernel@vger.kernel.org; Yoder Stuart-B08248;
> iommu@lists.linux-foundation.org; Wood Scott-B07421; linuxppc-
> dev@lists.ozlabs.org
> Subject: Re: [PATCH 5/5 v9] iommu/fsl: Freescale PAMU driver and iommu
> implementation.
>=20
>=20
> On Mar 14, 2013, at 3:20 PM, Kumar Gala wrote:
>=20
> >
> > On Mar 13, 2013, at 1:49 PM, Varun Sethi wrote:
> >
> >> +/*
> >> + * Table of SVRs and the corresponding PORT_ID values.
> >> + *
> >> + * All future CoreNet-enabled SOCs will have this erratum fixed, so
> >> +this table
> >> + * should never need to be updated. SVRs are guaranteed to be
> >> +unique, so
> >> + * there is no worry that a future SOC will inadvertently have one
> >> +of these
> >> + * values.
> >> + */
> >
> > Maybe add to the comment about what port_id represents
>=20
> also, add reference to the erratum #/id/name
>=20
[Sethi Varun-B16395] Ok.
-Varun
^ permalink raw reply
* RE: [PATCH 5/5 v9] iommu/fsl: Freescale PAMU driver and iommu implementation.
From: Sethi Varun-B16395 @ 2013-03-17 15:49 UTC (permalink / raw)
To: Yoder Stuart-B08248, Kumar Gala
Cc: Wood Scott-B07421, joro@8bytes.org, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <9F6FE96B71CF29479FF1CDC8046E1503586936@039-SN1MPN1-002.039d.mgd.msft.net>
> -----Original Message-----
> From: Yoder Stuart-B08248
> Sent: Friday, March 15, 2013 2:45 AM
> To: Kumar Gala; Sethi Varun-B16395
> Cc: joro@8bytes.org; iommu@lists.linux-foundation.org; linuxppc-
> dev@lists.ozlabs.org; linux-kernel@vger.kernel.org;
> benh@kernel.crashing.org; Wood Scott-B07421
> Subject: RE: [PATCH 5/5 v9] iommu/fsl: Freescale PAMU driver and iommu
> implementation.
>=20
>=20
>=20
> > -----Original Message-----
> > From: Kumar Gala [mailto:galak@kernel.crashing.org]
> > Sent: Thursday, March 14, 2013 3:20 PM
> > To: Sethi Varun-B16395
> > Cc: joro@8bytes.org; iommu@lists.linux-foundation.org;
> > linuxppc-dev@lists.ozlabs.org; linux- kernel@vger.kernel.org;
> > benh@kernel.crashing.org; Wood Scott-B07421; Yoder Stuart-B08248
> > Subject: Re: [PATCH 5/5 v9] iommu/fsl: Freescale PAMU driver and iommu
> implementation.
> >
> >
> > On Mar 13, 2013, at 1:49 PM, Varun Sethi wrote:
> >
> > > +/*
> > > + * Table of SVRs and the corresponding PORT_ID values.
> > > + *
> > > + * All future CoreNet-enabled SOCs will have this erratum fixed, so
> > > +this table
> > > + * should never need to be updated. SVRs are guaranteed to be
> > > +unique, so
> > > + * there is no worry that a future SOC will inadvertently have one
> > > +of these
> > > + * values.
> > > + */
> >
> > Maybe add to the comment about what port_id represents
>=20
> When you update the comment, I would also suggest identifying the
> specific errata here (A-004510) so that it's easy to reference back to
> the specific issue this code is fixing.
[Sethi Varun-B16395] Ok
-Varun
^ permalink raw reply
* Re: [PATCH 1/9] powerpc,kvm: fix imbalance srcu_read_[un]lock()
From: Paul Mackerras @ 2013-03-17 21:26 UTC (permalink / raw)
To: Lai Jiangshan
Cc: kvm, Gleb Natapov, Marcelo Tosatti, Alexander Graf, kvm-ppc,
linux-kernel, Andrew Morton, Paul E. McKenney, linuxppc-dev
In-Reply-To: <1363366257-4886-2-git-send-email-laijs@cn.fujitsu.com>
On Sat, Mar 16, 2013 at 12:50:49AM +0800, Lai Jiangshan wrote:
> At the point of up_out label in kvmppc_hv_setup_htab_rma(),
> srcu read lock is still held.
>
> We have to release it before return.
>
> Signed-off-by: Lai Jiangshan <laijs@cn.fujitsu.com>
> Cc: Marcelo Tosatti <mtosatti@redhat.com>
> Cc: Gleb Natapov <gleb@redhat.com>
> Cc: Alexander Graf <agraf@suse.de>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: kvm@vger.kernel.org
> Cc: kvm-ppc@vger.kernel.org
> ---
> arch/powerpc/kvm/book3s_hv.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index 80dcc53..c26740e 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -1799,7 +1799,7 @@ static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu)
>
> up_out:
> up_read(¤t->mm->mmap_sem);
> - goto out;
> + goto out_srcu;
Acked-by: Paul Mackerras <paulus@samba.org>
^ permalink raw reply
* [git pull] Please pull powerpc.git merge branch
From: Benjamin Herrenschmidt @ 2013-03-18 5:17 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev, Linux Kernel list
Hi Linus !
Here's a few powerpc fixes for 3.9, mostly regressions (though not all
from 3.9 merge window) that we've been hammering into shape over the
last couple of weeks. They fix booting on Cell and G5 among other
things (yes, we've been a bit sloppy with older machines this time
around).
Cheers,
Ben.
The following changes since commit 7c6baa304b841673d3a55ea4fcf9a5cbf7a1674b:
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (2013-03-11 07:54:29 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge
for you to fetch changes up to af81d7878c641629f2693ae3fdaf74b4af14dfca:
powerpc: Rename USER_ESID_BITS* to ESID_BITS* (2013-03-17 12:45:44 +1100)
----------------------------------------------------------------
Aneesh Kumar K.V (3):
powerpc: Make VSID_BITS* dependency explicit
powerpc: Update kernel VSID range
powerpc: Rename USER_ESID_BITS* to ESID_BITS*
Anton Blanchard (1):
powerpc: Fix -mcmodel=medium breakage in prom_init.c
Benjamin Herrenschmidt (2):
powerpc: Fix STAB initialization
powerpc: Fix cputable entry for 970MP rev 1.0
Michael Neuling (1):
powerpc/ptrace: Fix brk.len used uninitialised
Paul Bolle (1):
powerpc: Remove last traces of POWER4_ONLY
Stephen Rothwell (1):
powerpc: Make sure that we alays include CONFIG_BINFMT_ELF
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/asm/mmu-hash64.h | 128 ++++++++++++++++----------------
arch/powerpc/kernel/cputable.c | 2 +-
arch/powerpc/kernel/exceptions-64s.S | 34 ++++++---
arch/powerpc/kernel/prom_init.c | 14 ++--
arch/powerpc/kernel/ptrace.c | 1 +
arch/powerpc/kvm/book3s_64_mmu_host.c | 4 +-
arch/powerpc/mm/hash_utils_64.c | 22 ++++--
arch/powerpc/mm/mmu_context_hash64.c | 11 +--
arch/powerpc/mm/pgtable_64.c | 2 +-
arch/powerpc/mm/slb_low.S | 50 ++++++-------
arch/powerpc/mm/tlb_hash64.c | 2 +-
arch/powerpc/platforms/Kconfig.cputype | 6 +-
13 files changed, 150 insertions(+), 127 deletions(-)
^ permalink raw reply
* RE: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support
From: Leekha Shaveta-B20052 @ 2013-03-18 6:28 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <69F32D25-11C5-414D-A23A-AD25C9CCF9C6@kernel.crashing.org>
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Friday, March 15, 2013 9:28 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
> - Add support for B4 board's personalities in board file b4_qds.c, It=20
> is common for B4 personalities B4860 and B4420QDS
> - Add B4QDS support in Kconfig and Makefile
Code also references a B4220, what about it?
[SL] I have added the basic support for it in board file as it's one of the=
personality of
B4, missed it in description. But device trees for this has not been create=
d and tested.
So what do you suggest here:
Should I add it here in B4 board support or should I remove its references =
altogether?
>=20
> B4860QDS is a high-performance computing evaluation, development and=20
> test platform supporting the B4860 QorIQ Power Architecture processor,=20
> with following major features:
>=20
> - Four dual-threaded e6500 Power Architecture processors
> organized in one cluster-each core runs up to 1.8 GHz
> - Two DDR3/3L controllers for high-speed memory interface each
> runs at up to 1866.67 MHz
> - CoreNet fabric that fully supports coherency using MESI protocol
> between the e6500 cores, SC3900 FVP cores, memories and
> external interfaces.
> - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3=
and RMAN
> - Large internal cache memory with snooping and stashing capabilities
> - Sixteen 10-GHz SerDes lanes that serve:
> - Two SRIO interfaces. Each supports up to 4 lanes and
> a total of up to 8 lanes
> - Up to 8-lanes Common Public Radio Interface (CPRI) controller
> for glue-less antenna connection
> - Two 10-Gbit Ethernet controllers (10GEC)
> - Six 1G/2.5-Gbit Ethernet controllers for network communications
> - PCI Express controller
> - Debug (Aurora)
> - Various system peripherals
>=20
> B4420 is a reduced personality of B4860 with fewer core/clusters(both=20
> SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII=
interfaces and reduced target frequencies.
>=20
> Key differences between B4860 and B4420:
> B4420 has:
> - Fewer e6500 cores:
> 1 cluster with 2 e6500 cores
> - Fewer SC3900 cores/clusters:
> 1 cluster with 2 SC3900 cores per cluster
> - Single DDRC
> - 2X 4 lane serdes
> - 3 SGMII interfaces
> - no sRIO
> - no 10G
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> arch/powerpc/platforms/85xx/Kconfig | 16 +++++
> arch/powerpc/platforms/85xx/Makefile | 1 +
> arch/powerpc/platforms/85xx/b4_qds.c | 102=20
> ++++++++++++++++++++++++++++++++++
> 3 files changed, 119 insertions(+), 0 deletions(-) create mode 100644=20
> arch/powerpc/platforms/85xx/b4_qds.c
>=20
> diff --git a/arch/powerpc/platforms/85xx/Kconfig=20
> b/arch/powerpc/platforms/85xx/Kconfig
> index 31dc066..7bbd522 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -262,6 +262,22 @@ config SGY_CTS1000
>=20
> endif # PPC32
>=20
> +config B4_QDS
> + bool "Freescale B4 QDS"
> + select DEFAULT_UIMAGE
> + select E500
> + select PPC_E500MC
> + select PHYS_64BIT
> + select SWIOTLB
> + select MPC8xxx_GPIO
should be:
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
[SL] will change it.
=20
> + select HAS_RAPIDIO
> + select PPC_EPAPR_HV_PIC
> + help
> + This option enables support for the B4 QDS board
> + The B4 application development system B4 QDS is a complete
> + debugging environment intended for engineers developing
> + applications for the B4.
> +
Should be in the if PPC64 section with T4240 QDS support
[SL] ok=20
> config P5020_DS
> bool "Freescale P5020 DS"
> select DEFAULT_UIMAGE
> diff --git a/arch/powerpc/platforms/85xx/Makefile=20
> b/arch/powerpc/platforms/85xx/Makefile
> index 712e233..a12ae2d 100644
> --- a/arch/powerpc/platforms/85xx/Makefile
> +++ b/arch/powerpc/platforms/85xx/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) +=3D smp.o obj-y +=3D common.o
>=20
> obj-$(CONFIG_BSC9131_RDB) +=3D bsc913x_rdb.o
> +obj-$(CONFIG_B4_QDS) +=3D b4_qds.o corenet_ds.o
> obj-$(CONFIG_MPC8540_ADS) +=3D mpc85xx_ads.o
> obj-$(CONFIG_MPC8560_ADS) +=3D mpc85xx_ads.o
> obj-$(CONFIG_MPC85xx_CDS) +=3D mpc85xx_cds.o diff --git=20
> a/arch/powerpc/platforms/85xx/b4_qds.c=20
> b/arch/powerpc/platforms/85xx/b4_qds.c
> new file mode 100644
> index 0000000..0c6702f
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/b4_qds.c
> @@ -0,0 +1,102 @@
> +/*
> + * B4 QDS Setup
> + * Should apply for QDS platform of B4860 and it's personalities.
> + * viz B4860/B4420/B4220QDS
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or=20
> +modify it
> + * under the terms of the GNU General Public License as published=20
> +by the
> + * Free Software Foundation; either version 2 of the License, or=20
> +(at your
> + * option) any later version.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/phy.h>
> +
> +#include <asm/time.h>
> +#include <asm/machdep.h>
> +#include <asm/pci-bridge.h>
> +#include <mm/mmu_decl.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <asm/mpic.h>
> +
> +#include <linux/of_platform.h>
> +#include <sysdev/fsl_soc.h>
> +#include <sysdev/fsl_pci.h>
> +#include <asm/ehv_pic.h>
> +
> +#include "corenet_ds.h"
> +
> +/*
> + * Called very early, device-tree isn't unflattened */ static int=20
> +__init b4_qds_probe(void) {
> + unsigned long root =3D of_get_flat_dt_root(); #ifdef CONFIG_SMP
> + extern struct smp_ops_t smp_85xx_ops; #endif
> +
> + if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
> + (of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
> + (of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
> + return 1;
> +
> + /* Check if we're running under the Freescale hypervisor */
> + if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
> + (of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
> + (of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
> + ppc_md.init_IRQ =3D ehv_pic_init;
> + ppc_md.get_irq =3D ehv_pic_get_irq;
> + ppc_md.restart =3D fsl_hv_restart;
> + ppc_md.power_off =3D fsl_hv_halt;
> + ppc_md.halt =3D fsl_hv_halt;
> +#ifdef CONFIG_SMP
> + /*
> + * Disable the timebase sync operations because we can't write
> + * to the timebase registers under the hypervisor.
> + */
> + smp_85xx_ops.give_timebase =3D NULL;
> + smp_85xx_ops.take_timebase =3D NULL;
> +#endif
> + return 1;
> + }
> +
> + return 0;
> +}
> +
> +define_machine(b4_qds) {
> + .name =3D "B4 QDS",
> + .probe =3D b4_qds_probe,
> + .setup_arch =3D corenet_ds_setup_arch,
> + .init_IRQ =3D corenet_ds_pic_init,
> +#ifdef CONFIG_PCI
> + .pcibios_fixup_bus =3D fsl_pcibios_fixup_bus,
> +#endif
> +/* coreint doesn't play nice with lazy EE, use legacy mpic for now */=20
> +#ifdef CONFIG_PPC64
> + .get_irq =3D mpic_get_irq,
> +#else
> + .get_irq =3D mpic_get_coreint_irq,
> +#endif
> + .restart =3D fsl_rstcr_restart,
> + .calibrate_decr =3D generic_calibrate_decr,
> + .progress =3D udbg_progress,
> +#ifdef CONFIG_PPC64
> + .power_save =3D book3e_idle,
> +#else
> + .power_save =3D e500_idle,
> +#endif
> +};
> +
> +machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
> +
> +#ifdef CONFIG_SWIOTLB
> +machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier); #endif
> --
> 1.7.6.GIT
>=20
>=20
Regards,
Shaveta
=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* RE: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device tree
From: Leekha Shaveta-B20052 @ 2013-03-18 6:31 UTC (permalink / raw)
To: Kumar Gala
Cc: Fleming Andy-AFLEMING, Aggrwal Poonam-B10812,
linuxppc-dev@lists.ozlabs.org, Lian Minghuan-B31939,
Mehresh Ramneek-B31383
In-Reply-To: <7EB2D4A9-A5BC-4958-9AD8-51B254666356@kernel.crashing.org>
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Saturday, March 16, 2013 1:57 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming Andy-AFLEM=
ING; Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board devi=
ce tree
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/boot/dts/b4860qds.dts | 178=20
> ++++++++++++++++++++++++++++++++++++
> 1 files changed, 178 insertions(+), 0 deletions(-) create mode 100644=20
> arch/powerpc/boot/dts/b4860qds.dts
>=20
> diff --git a/arch/powerpc/boot/dts/b4860qds.dts=20
> b/arch/powerpc/boot/dts/b4860qds.dts
> new file mode 100644
> index 0000000..ae6ac05
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/b4860qds.dts
> @@ -0,0 +1,178 @@
> +/*
> + * B4860DS Device Tree Source
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions ar=
e met:
> + * * Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * * Redistributions in binary form must reproduce the above copyrig=
ht
> + * notice, this list of conditions and the following disclaimer in=
the
> + * documentation and/or other materials provided with the distribu=
tion.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote pro=
ducts
> + * derived from this software without specific prior written permi=
ssion.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of=20
> +the
> + * GNU General Public License ("GPL") as published by the Free=20
> +Software
> + * Foundation, either version 2 of that License or (at your option)=20
> +any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND=20
> +ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE=20
> +IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE=20
> +ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE=20
> +FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL=20
> +DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR=20
> +SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER=20
> +CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,=20
> +OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE=20
> +USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/include/ "fsl/b4860si-pre.dtsi"
> +
> +/ {
> + model =3D "fsl,B4860QDS";
> + compatible =3D "fsl,B4860QDS";
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + interrupt-parent =3D <&mpic>;
> +
> + ifc: localbus@ffe124000 {
> + reg =3D <0xf 0xfe124000 0 0x2000>;
> + ranges =3D <0 0 0xf 0xe8000000 0x08000000
> + 2 0 0xf 0xff800000 0x00010000
> + 3 0 0xf 0xffdf0000 0x00008000>;
> +
> + nor@0,0 {
> + #address-cells =3D <1>;
> + #size-cells =3D <1>;
> + compatible =3D "cfi-flash";
> + reg =3D <0x0 0x0 0x8000000>;
> + bank-width =3D <2>;
> + device-width =3D <1>;
> + };
> +
> + nand@2,0 {
> + #address-cells =3D <1>;
> + #size-cells =3D <1>;
> + compatible =3D "fsl,ifc-nand";
> + reg =3D <0x2 0x0 0x10000>;
> +
> + partition@0 {
> + /* This location must not be altered */
> + /* 1MB for u-boot Bootloader Image */
> + reg =3D <0x0 0x00100000>;
> + label =3D "NAND U-Boot Image";
> + read-only;
> + };
> +
> + partition@100000 {
> + /* 1MB for DTB Image */
> + reg =3D <0x00100000 0x00100000>;
> + label =3D "NAND DTB Image";
> + };
> +
> + partition@200000 {
> + /* 10MB for Linux Kernel Image */
> + reg =3D <0x00200000 0x00A00000>;
> + label =3D "NAND Linux Kernel Image";
> + };
> +
> + partition@c00000 {
> + /* 500MB for Root file System Image */
> + reg =3D <0x00c00000 0x1F400000>;
> + label =3D "NAND RFS Image";
> + };
> + };
> +
> + board-control@3,0 {
> + compatible =3D "fsl,b4860qds-fpga", "fsl,fpga-qixis";
> + reg =3D <3 0 0x300>;
> + };
> + };
> +
dscr nodes are missing and should be included
[SL] I don't have much idea about dcsr nodes structure and their respective=
testing, also couldn't find then in T4 device tree files. I have added ini=
tial device trees. Dcsr may be added later as updation. What do you say? =20
> + memory {
> + device_type =3D "memory";
> + };
> +
> + soc: soc@ffe000000 {
> + ranges =3D <0x00000000 0xf 0xfe000000 0x1000000>;
> + reg =3D <0xf 0xfe000000 0 0x00001000>;
> + spi@110000 {
> + flash@0 {
> + #address-cells =3D <1>;
> + #size-cells =3D <1>;
> + compatible =3D "sst,sst25wf040";
> + reg =3D <0>;
> + spi-max-frequency =3D <40000000>; /* input clock */
> + };
> + };
> +
> + sdhc@114000 {
> + status =3D "disabled";
> + };
> +
> + i2c@118000 {
> + eeprom@50 {
> + compatible =3D "at24,24c64";
> + reg =3D <0x50>;
> + };
> + eeprom@51 {
> + compatible =3D "at24,24c256";
> + reg =3D <0x51>;
> + };
> + eeprom@53 {
> + compatible =3D "at24,24c256";
> + reg =3D <0x53>;
> + };
> + eeprom@57 {
> + compatible =3D "at24,24c256";
> + reg =3D <0x57>;
> + };
> + rtc@68 {
> + compatible =3D "dallas,ds3232";
> + reg =3D <0x68>;
> + interrupts =3D <0x1 0x1 0 0>;
there is no IRQ for RTC on the board.
[SL] will remove it.=20
> + };
> + };
> +
> + usb@210000 {
> + dr_mode =3D "host";
> + phy_type =3D "ulpi";
> + };
> +
> + };
> +
> + pci0: pcie@ffe200000 {
> + reg =3D <0xf 0xfe200000 0 0x10000>;
> + ranges =3D <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
> + 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
> + pcie@0 {
> + ranges =3D <0x02000000 0 0xe0000000
> + 0x02000000 0 0xe0000000
> + 0 0x20000000
> +
> + 0x01000000 0 0x00000000
> + 0x01000000 0 0x00000000
> + 0 0x00010000>;
> + };
> + };
> +
> + rio: rapidio@ffe0c0000 {
> + reg =3D <0xf 0xfe0c0000 0 0x11000>;
> +
> + port1 {
> + ranges =3D <0 0 0xc 0x20000000 0 0x10000000>;
> + };
> + port2 {
> + ranges =3D <0 0 0xc 0x30000000 0 0x10000000>;
> + };
> + };
> +
> +};
> +
> +/include/ "fsl/b4860si-post.dtsi"
> --
> 1.7.6.GIT
>=20
Regards,
Shaveta
=20
^ permalink raw reply
* RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS
From: Leekha Shaveta-B20052 @ 2013-03-18 6:59 UTC (permalink / raw)
To: Kumar Gala
Cc: Li Yang-R58472, Zhao Chenhui-B35336, Mehresh Ramneek-B31383,
Lian Minghuan-B31939, Tang Yuantian-B29983, Fleming Andy-AFLEMING,
Sethi Varun-B16395, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <112ADD30-18A2-4147-B185-46841D0119BD@kernel.crashing.org>
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Saturday, March 16, 2013 2:00 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li Yang-R58472; Tan=
g Yuantian-B29983; Sethi Varun-B16395; Lian Minghuan-B31939; Mehresh Ramnee=
k-B31383; Fleming Andy-AFLEMING
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree=
files for B4860QDS
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> ---
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 184 ++++++++++++++++++++++=
+++++
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 80 ++++++++++++
> 2 files changed, 264 insertions(+), 0 deletions(-) create mode 100644=20
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
* SEC node is missing
* DCSR nodes are missing.
- k
[SL] will add sec node, same reply for dcsr.
>=20
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi=20
> b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> new file mode 100644
> index 0000000..2db68b2
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> @@ -0,0 +1,184 @@
> +/*
> + * B4860 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions ar=
e met:
> + * * Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * * Redistributions in binary form must reproduce the above copyrig=
ht
> + * notice, this list of conditions and the following disclaimer in=
the
> + * documentation and/or other materials provided with the distribu=
tion.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote pro=
ducts
> + * derived from this software without specific prior written permi=
ssion.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of=20
> +the
> + * GNU General Public License ("GPL") as published by the Free=20
> +Software
> + * Foundation, either version 2 of that License or (at your option)=20
> +any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND=20
> +ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE=20
> +IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE=20
> +ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE=20
> +FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL=20
> +DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR=20
> +SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER=20
> +CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,=20
> +OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE=20
> +USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +&ifc {
> + #address-cells =3D <2>;
> + #size-cells =3D <1>;
> + compatible =3D "fsl,ifc", "simple-bus";
> + interrupts =3D <25 2 0 0>;
> +};
> +
> +/* controller at 0x200000 */
> +&pci0 {
> + compatible =3D "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
> + device_type =3D "pci";
> + #size-cells =3D <2>;
> + #address-cells =3D <3>;
> + bus-range =3D <0x0 0xff>;
> + interrupts =3D <20 2 0 0>;
> + pcie@0 {
> + #interrupt-cells =3D <1>;
> + #size-cells =3D <2>;
> + #address-cells =3D <3>;
> + device_type =3D "pci";
> + interrupts =3D <20 2 0 0>;
> + interrupt-map-mask =3D <0xf800 0 0 7>;
> + interrupt-map =3D <
> + /* IDSEL 0x0 */
> + 0000 0 0 1 &mpic 40 1 0 0
> + 0000 0 0 2 &mpic 1 1 0 0
> + 0000 0 0 3 &mpic 2 1 0 0
> + 0000 0 0 4 &mpic 3 1 0 0
> + >;
> + };
> +};
> +
> +&rio {
> + compatible =3D "fsl,srio";
> + interrupts =3D <16 2 1 11>;
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + ranges;
> +
> + port1 {
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + cell-index =3D <1>;
> + };
> +
> + port2 {
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + cell-index =3D <2>;
> + };
> +};
> +
> +&soc {
> + #address-cells =3D <1>;
> + #size-cells =3D <1>;
> + device_type =3D "soc";
> + compatible =3D "simple-bus";
> +
> + soc-sram-error {
> + compatible =3D "fsl,soc-sram-error";
> + interrupts =3D <16 2 1 2>;
> + };
> +
> + corenet-law@0 {
> + compatible =3D "fsl,corenet-law";
> + reg =3D <0x0 0x1000>;
> + fsl,num-laws =3D <32>;
> + };
> +
> + ddr1: memory-controller@8000 {
> + compatible =3D "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-c=
ontroller";
> + reg =3D <0x8000 0x1000>;
> + interrupts =3D <16 2 1 8>;
> + };
> +
> + ddr2: memory-controller@9000 {
> + compatible =3D "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-co=
ntroller";
> + reg =3D <0x9000 0x1000>;
> + interrupts =3D <16 2 1 9>;
> + };
> +
> + cpc: l3-cache-controller@10000 {
> + compatible =3D "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-co=
ntroller", "cache";
> + reg =3D <0x10000 0x1000
> + 0x11000 0x1000>;
> + interrupts =3D <16 2 1 4
> + 16 2 1 5>;
> + };
> +
> + corenet-cf@18000 {
> + compatible =3D "fsl,corenet-cf";
> + reg =3D <0x18000 0x1000>;
> + interrupts =3D <16 2 1 0>;
> + fsl,ccf-num-csdids =3D <32>;
> + fsl,ccf-num-snoopids =3D <32>;
> + };
> +
> + iommu@20000 {
> + compatible =3D "fsl,pamu-v1.0", "fsl,pamu";
> + reg =3D <0x20000 0x4000>;
> + interrupts =3D <
> + 24 2 0 0
> + 16 2 1 1>;
> + };
> +
> +/include/ "qoriq-mpic.dtsi"
> +
> + guts: global-utilities@e0000 {
> + compatible =3D "fsl,b4860-device-config";
> + reg =3D <0xe0000 0xe00>;
> + fsl,has-rstcr;
> + fsl,liodn-bits =3D <12>;
> + };
> +
> + clockgen: global-utilities@e1000 {
> + compatible =3D "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2";
> + reg =3D <0xe1000 0x1000>;
> + };
> +
> + rcpm: global-utilities@e2000 {
> + compatible =3D "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2";
> + reg =3D <0xe2000 0x1000>;
> + };
> +
> +/include/ "qoriq-dma-0.dtsi"
> +/include/ "qoriq-dma-1.dtsi"
> +
> +/include/ "qonverge-usb2-dr-0.dtsi"
> + usb0: usb@210000 {
> + compatible =3D "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
> + };
> +
> +/include/ "qoriq-espi-0.dtsi"
> + spi@110000 {
> + fsl,espi-num-chipselects =3D <4>;
> + };
> +
> +/include/ "qoriq-esdhc-0.dtsi"
> + sdhc@114000 {
> + sdhci,auto-cmd12;
> + };
> +/include/ "qoriq-i2c-0.dtsi"
> +/include/ "qoriq-i2c-1.dtsi"
> +/include/ "qoriq-duart-0.dtsi"
> +/include/ "qoriq-duart-1.dtsi"
> +
> + L2: l2-cache-controller@c20000 {
> + next-level-cache =3D <&cpc>;
should have compatible & reg nodes
[SL] agree. Will add=20
> + };
> +};
[ snip ]
- k
Regards,
Shaveta
^ permalink raw reply
* RE: [PATCH 4/6] powerpc/fsl-booke: Add initial B4420QDS board device tree
From: Leekha Shaveta-B20052 @ 2013-03-18 7:00 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <78325CC6-01B7-4A81-A4E9-40188B7994DE@kernel.crashing.org>
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Saturday, March 16, 2013 2:02 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 4/6] powerpc/fsl-booke: Add initial B4420QDS board devi=
ce tree
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> arch/powerpc/boot/dts/b4420qds.dts | 168=20
> ++++++++++++++++++++++++++++++++++++
> 1 files changed, 168 insertions(+), 0 deletions(-) create mode 100644=20
> arch/powerpc/boot/dts/b4420qds.dts
If B4420 and B4860 qds are same board, refactor this into a b4qds.dtsi file=
for common board features like NOR, NAND, SPI, SDHC, etc.
[SL] will work on refactoring and send new set of patches soon. Thanks for =
the feedback.
Regards,
Shaveta
=20
- k
^ permalink raw reply
* KVM breaking the ppc64_defconfig UP build
From: Michael Ellerman @ 2013-03-18 7:01 UTC (permalink / raw)
To: linuxppc-dev, paulus, benh
Hi guys,
The ppc64_defconfig build with CONFIG_SMP=n (ie. UP) is broken by KVM:
arch/powerpc/kvm/book3s_hv.c:1855:2: error: implicit declaration of function 'inhibit_secondary_onlining'
arch/powerpc/kvm/book3s_hv.c:1862:2: error: implicit declaration of function 'uninhibit_secondary_onlining'
http://kisskb.ellerman.id.au/kisskb/buildresult/8400164/
The fix for that is fairly easy.
Once that's fixed there is breakage in arch/powerpc/kvm/book3s_hv_interrupts.S
caused by us calling smp_send_reschedule() to cause a self-IPI on 970.
It's not clear to me how we fix that one, any ideas?
cheers
^ permalink raw reply
* RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS
From: Leekha Shaveta-B20052 @ 2013-03-18 7:41 UTC (permalink / raw)
To: Timur Tabi, Kumar Gala
Cc: Mehresh Ramneek-B31383, Zhao Chenhui-B35336, Lian Minghuan-B31939,
Tang Yuantian-B29983, Fleming Andy-AFLEMING, Sethi Varun-B16395,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <CAOZdJXV5UgT71j5XJH8K6DnfE-SUVL2jE7yNZUhE+gstb_33tQ@mail.gmail.com>
-----Original Message-----
From: Timur Tabi [mailto:timur@tabi.org]=20
Sent: Friday, March 15, 2013 6:38 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian Minghuan-B3193=
9; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Set=
hi Varun-B16395
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree=
files for B4860QDS
On Fri, Mar 15, 2013 at 2:55 AM, Shaveta Leekha <shaveta@freescale.com> wro=
te:
> + iommu@20000 {
> + compatible =3D "fsl,pamu-v1.0", "fsl,pamu";
> + reg =3D <0x20000 0x4000>;
> + interrupts =3D <
> + 24 2 0 0
> + 16 2 1 1>;
> + };
You need to add the PAMU topology.
[SL] Thanks for reviewing the patches.
These patches are on similar lines as T4 initial support
In due course of time, we plan to add pamu topology and pamu related suppor=
t in various devices both for T4 and B4.
Kumar can you please suggest?
Regards,
Shaveta
--=20
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [patch 1/2] mm: remove free_area_cache use in powerpc architecture
From: Michel Lespinasse @ 2013-03-18 8:08 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, linuxppc-dev; +Cc: riel, akpm
In-Reply-To: <20130221230557.8BDCA5A4174@corp2gmr1-2.hot.corp.google.com>
On Thu, Feb 21, 2013 at 3:05 PM, <akpm@linux-foundation.org> wrote:
> From: Michel Lespinasse <walken@google.com>
> Subject: mm: remove free_area_cache use in powerpc architecture
>
> As all other architectures have been converted to use vm_unmapped_area(),
> we are about to retire the free_area_cache.
Ping ? I haven't seen any replies from the ppc maintainers, and
powerpc is now the only remaining user of free_area_cache. Could you
please take these two patches ?
Thanks,
--
Michel "Walken" Lespinasse
A program is never fully debugged until the last user dies.
^ permalink raw reply
* Re: [patch 1/2] mm: remove free_area_cache use in powerpc architecture
From: Benjamin Herrenschmidt @ 2013-03-18 8:19 UTC (permalink / raw)
To: Michel Lespinasse
Cc: riel, dwg, Paul Mackerras, Aneesh Kumar K.V, akpm, linuxppc-dev
In-Reply-To: <CANN689EuRDmoMaUE6E9kv2C70SY556MQAhopxCXCm6=gwuuPPg@mail.gmail.com>
On Mon, 2013-03-18 at 01:08 -0700, Michel Lespinasse wrote:
> On Thu, Feb 21, 2013 at 3:05 PM, <akpm@linux-foundation.org> wrote:
> > From: Michel Lespinasse <walken@google.com>
> > Subject: mm: remove free_area_cache use in powerpc architecture
> >
> > As all other architectures have been converted to use vm_unmapped_area(),
> > we are about to retire the free_area_cache.
>
> Ping ? I haven't seen any replies from the ppc maintainers, and
> powerpc is now the only remaining user of free_area_cache. Could you
> please take these two patches ?
Ah the ppc maintainer was totally swamped (and now on vacation) and was
hoping somebody else would review & test that ...
Aneesh, David, can you have a look ?
Thanks !
Cheers,
Ben.
^ permalink raw reply
* [PATCH] powerpc: add CONFIG(s) require for using flash controller
From: Prabhakar Kushwaha @ 2013-03-18 8:31 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Prabhakar Kushwaha
Add CONFIG(s) required for NAND and NOR flash controller usage.
It defines MTD, Jffs2 and UBIFS file system required for controllers.
It also enables IFC controller
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Based upon http://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
branch next
arch/powerpc/configs/corenet64_smp_defconfig | 35 +++++++++++++++++++++++++-
arch/powerpc/configs/mpc85xx_defconfig | 31 +++++++++++++++++++++++
arch/powerpc/configs/mpc85xx_smp_defconfig | 31 +++++++++++++++++++++++
3 files changed, 96 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 36a5c41..1c6eb66 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -26,6 +26,7 @@ CONFIG_P5040_DS=y
CONFIG_T4240_QDS=y
# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
CONFIG_BINFMT_MISC=m
+CONFIG_FSL_IFC=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCI_MSI=y
CONFIG_RAPIDIO=y
@@ -58,16 +59,33 @@ CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_M25P80=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
@@ -122,7 +140,16 @@ CONFIG_NTFS_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_HUGETLBFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
@@ -130,6 +157,12 @@ CONFIG_NFSD=m
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=m
CONFIG_CRC_T10DIF=y
+CONFIG_CRC16=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index e12146f..37812b4 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -47,6 +47,7 @@ CONFIG_HIGHMEM=y
CONFIG_BINFMT_MISC=m
CONFIG_MATH_EMULATION=y
CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_FSL_IFC=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_RAPIDIO=y
@@ -78,18 +79,33 @@ CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
CONFIG_FTL=y
CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_M25P80=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
@@ -207,6 +223,15 @@ CONFIG_NTFS_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
CONFIG_ADFS_FS=m
CONFIG_AFFS_FS=m
CONFIG_HFS_FS=m
@@ -225,6 +250,12 @@ CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_CRC_T10DIF=y
+CONFIG_CRC16=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_INFO=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 8d00ea5b..7fc3e6f 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -50,6 +50,7 @@ CONFIG_HIGHMEM=y
CONFIG_BINFMT_MISC=m
CONFIG_MATH_EMULATION=y
CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_FSL_IFC=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_RAPIDIO=y
@@ -81,18 +82,33 @@ CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
CONFIG_FTL=y
CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_M25P80=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
@@ -207,6 +223,15 @@ CONFIG_NTFS_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
CONFIG_ADFS_FS=m
CONFIG_AFFS_FS=m
CONFIG_HFS_FS=m
@@ -225,6 +250,12 @@ CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_CRC_T10DIF=y
+CONFIG_CRC16=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_INFO=y
--
1.7.9.5
^ permalink raw reply related
* Re: [GIT PULL 0/8] perf/urgent fixes
From: Ingo Molnar @ 2013-03-18 9:02 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: Feng Tang, Srikar Dronamraju, Jack Mitchell, Stephane Eranian,
Oleg Nesterov, linuxppc-dev, Paul Mackerras, Jiri Olsa,
Namhyung Kim, Andi Kleen, Irina Tirdea, Robert Richter,
Vinson Lee, Ingo Molnar, Marcin Slusarz, Arnaldo Carvalho de Melo,
Frederic Weisbecker, Ingo Molnar, Sukadev Bhattiprolu,
Peter Zijlstra, Corey Ashford, Anton Blanchard, Namhyung Kim,
Arnaldo Carvalho de Melo, linux-kernel, Pekka Enberg, David Ahern
In-Reply-To: <1363263795-31485-1-git-send-email-acme@infradead.org>
* Arnaldo Carvalho de Melo <acme@infradead.org> wrote:
> From: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
>
> Hi Ingo,
>
> Please consider pulling,
>
> - Arnaldo
>
> The following changes since commit cb16b91a449afd01b85ec4e59f30449d11c4acd7:
>
> s390: Fix a header dependencies related build error (2013-03-11 10:43:35 +0100)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux tags/perf-urgent-for-mingo
>
> for you to fetch changes up to d1398ccfec56e54010476efd6a316427d29045a6:
>
> perf tools: Fix LIBNUMA build with glibc 2.12 and older. (2013-03-14 08:06:21 -0300)
>
> ----------------------------------------------------------------
> perf/urgent fixes:
>
> . perf probe: Fix segfault due to testing the wrong pointer for NULL,
> from Ananth N Mavinakayanahalli.
>
> . libtraceevent: Remove hard coded include to /usr/local/include in
> Makefile, which causes cross builds to include host header files,
> fix from Jack Mitchell.
>
> . perf record: Use the right target interface for synthesizing
> threads when --cpu/-C option is used, fix from Jiri Olsa.
>
> . Check if -DFORTIFY_SOURCE=2 is allowed, as gcc 4.7.2 defines
> it and then the build is broken when it is redefined in perf,
> fix from Marcin Slusarz.
>
> . Fix build with NO_NEWT=1, that can happen explicitely or when
> the newt-devel package is not installed, from Michael Ellerman.
>
> . perf/POWER7: Create a sysfs format entry for Power7 events, missing
> patch from a patchseries already merged, from Sukadev Bhattiprolu.
>
> . Fix LIBNUMA build with glibc 2.12 and older, from Vinson Lee.
>
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
>
> ----------------------------------------------------------------
> Ananth N Mavinakayanahalli (1):
> perf probe: Fix segfault
>
> Jack Mitchell (1):
> libtraceevent: Remove hard coded include to /usr/local/include in Makefile
>
> Jiri Olsa (1):
> perf record: Fix -C option
>
> Marcin Slusarz (1):
> perf tools: check if -DFORTIFY_SOURCE=2 is allowed
>
> Michael Ellerman (2):
> perf annotate: Fix build with NO_NEWT=1
> perf report: Fix build with NO_NEWT=1
>
> Sukadev Bhattiprolu (1):
> perf/POWER7: Create a sysfs format entry for Power7 events
>
> Vinson Lee (1):
> perf tools: Fix LIBNUMA build with glibc 2.12 and older.
>
> arch/powerpc/perf/power7-pmu.c | 13 +++++++++++++
> tools/lib/traceevent/Makefile | 2 +-
> tools/perf/Makefile | 8 +++++++-
> tools/perf/bench/bench.h | 24 ++++++++++++++++++++++++
> tools/perf/builtin-record.c | 6 ++++--
> tools/perf/util/hist.h | 5 +++--
> tools/perf/util/strlist.c | 2 +-
> 7 files changed, 53 insertions(+), 7 deletions(-)
Pulled, thanks Arnaldo!
Ingo
^ permalink raw reply
* Re: [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale
From: Rojhalat Ibrahim @ 2013-03-18 9:22 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <677E5CC0-EC8D-4DB5-B9E3-F4E4D39EEF59@kernel.crashing.org>
On Thursday 14 March 2013 15:35:40 Kumar Gala wrote:
> On Mar 14, 2013, at 4:43 AM, Rojhalat Ibrahim wrote:
> > On Wednesday 13 March 2013 14:07:16 Kumar Gala wrote:
> >> diff --git a/arch/powerpc/sysdev/fsl_pci.c
> >> b/arch/powerpc/sysdev/fsl_pci.c
> >> index 41bbcc4..b18c377 100644
> >> --- a/arch/powerpc/sysdev/fsl_pci.c
> >> +++ b/arch/powerpc/sysdev/fsl_pci.c
> >> @@ -74,6 +74,35 @@ static int __init fsl_pcie_check_link(struct
> >> pci_controller *hose) return 0;
> >> }
> >>
> >> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int
> >> devfn, + int offset, int len, u32 *val)
> >> +{
> >> + struct pci_controller *hose = pci_bus_to_host(bus);
> >> +
> >> + /* check the link status */
> >> + if ((bus->number == hose->first_busno) && (devfn == 0)) {
> >> + if (fsl_pcie_check_link(hose))
> >> + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> >> + else
> >> + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> >> + }
> >> + return indirect_read_config(bus, devfn, offset, len, val);
> >> +}
> >> +
> >
> > This does not work because fsl_indirect_read_config calls
> > fsl_pcie_check_link which calls early_read_config_dword which eventually
> > calls fsl_indirect_read_config, so the kernel hangs in a recursion loop.
> > Below is a modified patch that does work.
> ok, that makes sense, but I guess now its making me question the following statement:
> > if ((bus->number == hose->first_busno) && (devfn == 0)) {
>
> Why do we have this conditional?
>
> - k
Right. This is not necessary anymore. I modified the patch accordingly.
Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
---
arch/powerpc/include/asm/pci-bridge.h | 6 ++++
arch/powerpc/sysdev/fsl_pci.c | 51 +++++++++++++++++++++++++++++-----
arch/powerpc/sysdev/indirect_pci.c | 10 ++----
3 files changed, 54 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index c0278f0..ffbc5fd 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -120,6 +120,12 @@ extern void setup_indirect_pci(struct pci_controller* hose,
resource_size_t cfg_addr,
resource_size_t cfg_data, u32 flags);
+extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 *val);
+
+extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 val);
+
static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
return bus->sysdata;
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 41bbcc4..9c0fcc9 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -54,12 +54,22 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
return;
}
-static int __init fsl_pcie_check_link(struct pci_controller *hose)
+static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
+ int, int, u32 *);
+
+static int fsl_pcie_check_link(struct pci_controller *hose)
{
- u32 val;
+ u32 val = 0;
if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
- early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
+ if (hose->ops->read == fsl_indirect_read_config) {
+ struct pci_bus bus;
+ bus.number = 0;
+ bus.sysdata = hose;
+ bus.ops = hose->ops;
+ indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
+ } else
+ early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
if (val < PCIE_LTSSM_L0)
return 1;
} else {
@@ -74,6 +84,33 @@ static int __init fsl_pcie_check_link(struct pci_controller *hose)
return 0;
}
+static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 *val)
+{
+ struct pci_controller *hose = pci_bus_to_host(bus);
+
+ if (fsl_pcie_check_link(hose))
+ hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+ else
+ hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+
+ return indirect_read_config(bus, devfn, offset, len, val);
+}
+
+static struct pci_ops fsl_indirect_pci_ops =
+{
+ .read = fsl_indirect_read_config,
+ .write = indirect_write_config,
+};
+
+static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
+ resource_size_t cfg_addr,
+ resource_size_t cfg_data, u32 flags)
+{
+ setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
+ hose->ops = &fsl_indirect_pci_ops;
+}
+
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
#define MAX_PHYS_ADDR_BITS 40
@@ -469,8 +506,8 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
if (!hose->private_data)
goto no_bridge;
- setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
- PPC_INDIRECT_TYPE_BIG_ENDIAN);
+ fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
+ PPC_INDIRECT_TYPE_BIG_ENDIAN);
if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
@@ -779,8 +816,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
if (ret)
goto err0;
} else {
- setup_indirect_pci(hose, rsrc_cfg.start,
- rsrc_cfg.start + 4, 0);
+ fsl_setup_indirect_pci(hose, rsrc_cfg.start,
+ rsrc_cfg.start + 4, 0);
}
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index 82fdad8..c6c8b52 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -20,9 +20,8 @@
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
-static int
-indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
- int len, u32 *val)
+int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 *val)
{
struct pci_controller *hose = pci_bus_to_host(bus);
volatile void __iomem *cfg_data;
@@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
return PCIBIOS_SUCCESSFUL;
}
-static int
-indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
- int len, u32 val)
+int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 val)
{
struct pci_controller *hose = pci_bus_to_host(bus);
volatile void __iomem *cfg_data;
^ permalink raw reply related
* RE: [PATCH 1/3] powerpc/mpic: add irq_set_wake support
From: Wang Dongsheng-B40534 @ 2013-03-18 9:28 UTC (permalink / raw)
To: Gala Kumar-B11780, benh@kernel.crashing.org
Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1362728327-21013-1-git-send-email-dongsheng.wang@freescale.com>
Hi Benjamin & Kumar,
I am not sure who can apply these patches...
Could you apply these patches?
Thanks.
[1/3] powerpc/mpic: add irq_set_wake support
http://patchwork.ozlabs.org/patch/226034/
[2/3] powerpc/mpic: add global timer support
http://patchwork.ozlabs.org/patch/226035/
[3/3] powerpc/fsl: add MPIC timer wakeup support
http://patchwork.ozlabs.org/patch/226036/
> -----Original Message-----
> From: Wang Dongsheng-B40534
> Sent: Friday, March 08, 2013 3:39 PM
> To: Wood Scott-B07421; Gala Kumar-B11780
> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
> Subject: [PATCH 1/3] powerpc/mpic: add irq_set_wake support
>=20
> Add irq_set_wake support. Just add IRQF_NO_SUSPEND to desc->action->flag.
> So the wake up interrupt will not be disable in suspend_device_irqs.
>=20
> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
> ---
> arch/powerpc/sysdev/mpic.c | 15 +++++++++++++++
> 1 files changed, 15 insertions(+), 0 deletions(-)
>=20
> diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
> index 3b2efd4..10e474e 100644
> --- a/arch/powerpc/sysdev/mpic.c
> +++ b/arch/powerpc/sysdev/mpic.c
> @@ -920,6 +920,18 @@ int mpic_set_irq_type(struct irq_data *d, unsigned
> int flow_type)
> return IRQ_SET_MASK_OK_NOCOPY;
> }
>=20
> +static int mpic_irq_set_wake(struct irq_data *d, unsigned int on) {
> + struct irq_desc *desc =3D container_of(d, struct irq_desc, irq_data);
> +
> + if (on)
> + desc->action->flags |=3D IRQF_NO_SUSPEND;
> + else
> + desc->action->flags &=3D ~IRQF_NO_SUSPEND;
> +
> + return 0;
> +}
> +
> void mpic_set_vector(unsigned int virq, unsigned int vector) {
> struct mpic *mpic =3D mpic_from_irq(virq); @@ -957,6 +969,7 @@ static
> struct irq_chip mpic_irq_chip =3D {
> .irq_unmask =3D mpic_unmask_irq,
> .irq_eoi =3D mpic_end_irq,
> .irq_set_type =3D mpic_set_irq_type,
> + .irq_set_wake =3D mpic_irq_set_wake,
> };
>=20
> #ifdef CONFIG_SMP
> @@ -971,6 +984,7 @@ static struct irq_chip mpic_tm_chip =3D {
> .irq_mask =3D mpic_mask_tm,
> .irq_unmask =3D mpic_unmask_tm,
> .irq_eoi =3D mpic_end_irq,
> + .irq_set_wake =3D mpic_irq_set_wake,
> };
>=20
> #ifdef CONFIG_MPIC_U3_HT_IRQS
> @@ -981,6 +995,7 @@ static struct irq_chip mpic_irq_ht_chip =3D {
> .irq_unmask =3D mpic_unmask_ht_irq,
> .irq_eoi =3D mpic_end_ht_irq,
> .irq_set_type =3D mpic_set_irq_type,
> + .irq_set_wake =3D mpic_irq_set_wake,
> };
> #endif /* CONFIG_MPIC_U3_HT_IRQS */
>=20
> --
> 1.7.5.1
^ permalink raw reply
* Re: [patch 2/2] mm: use vm_unmapped_area() on powerpc architecture
From: Aneesh Kumar K.V @ 2013-03-18 10:40 UTC (permalink / raw)
To: akpm, benh; +Cc: linuxppc-dev, akpm, walken, paulus
In-Reply-To: <20130221230558.C201931C1B7@corp2gmr1-1.hot.corp.google.com>
akpm@linux-foundation.org writes:
> From: Michel Lespinasse <walken@google.com>
> Subject: mm: use vm_unmapped_area() on powerpc architecture
>
> Update the powerpc slice_get_unmapped_area function to make use of
> vm_unmapped_area() instead of implementing a brute force search.
>
> Signed-off-by: Michel Lespinasse <walken@google.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
> ---
>
> arch/powerpc/mm/slice.c | 123 ++++++++++++++++++++++++--------------
> 1 file changed, 78 insertions(+), 45 deletions(-)
>
> diff -puN arch/powerpc/mm/slice.c~mm-use-vm_unmapped_area-on-powerpc-architecture arch/powerpc/mm/slice.c
> --- a/arch/powerpc/mm/slice.c~mm-use-vm_unmapped_area-on-powerpc-architecture
> +++ a/arch/powerpc/mm/slice.c
> @@ -237,36 +237,69 @@ static void slice_convert(struct mm_stru
> #endif
> }
>
> +/*
> + * Compute which slice addr is part of;
> + * set *boundary_addr to the start or end boundary of that slice
> + * (depending on 'end' parameter);
> + * return boolean indicating if the slice is marked as available in the
> + * 'available' slice_mark.
> + */
> +static bool slice_scan_available(unsigned long addr,
> + struct slice_mask available,
> + int end,
> + unsigned long *boundary_addr)
> +{
> + unsigned long slice;
> + if (addr < SLICE_LOW_TOP) {
> + slice = GET_LOW_SLICE_INDEX(addr);
> + *boundary_addr = (slice + end) << SLICE_LOW_SHIFT;
> + return !!(available.low_slices & (1u << slice));
> + } else {
> + slice = GET_HIGH_SLICE_INDEX(addr);
> + *boundary_addr = (slice + end) ?
> + ((slice + end) << SLICE_HIGH_SHIFT) : SLICE_LOW_TOP;
> + return !!(available.high_slices & (1u << slice));
> + }
> +}
Can you clarify more on when boundary_addr is set to start of the slice
in the comment ? Also may be it would be better if we can say
slice_scan_prev_available and slice_scan_next_available and get rid of
end completely ?
I have tested with both the patches applied and the resulting kernel boots fine.
-aneesh
^ permalink raw reply
* Re: [patch 2/2] mm: use vm_unmapped_area() on powerpc architecture
From: Aneesh Kumar K.V @ 2013-03-18 11:12 UTC (permalink / raw)
To: akpm, benh; +Cc: linuxppc-dev, akpm, walken, paulus
In-Reply-To: <20130221230558.C201931C1B7@corp2gmr1-1.hot.corp.google.com>
akpm@linux-foundation.org writes:
> From: Michel Lespinasse <walken@google.com>
> Subject: mm: use vm_unmapped_area() on powerpc architecture
>
> Update the powerpc slice_get_unmapped_area function to make use of
> vm_unmapped_area() instead of implementing a brute force search.
>
> Signed-off-by: Michel Lespinasse <walken@google.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
> ---
>
> arch/powerpc/mm/slice.c | 123 ++++++++++++++++++++++++--------------
> 1 file changed, 78 insertions(+), 45 deletions(-)
>
> diff -puN arch/powerpc/mm/slice.c~mm-use-vm_unmapped_area-on-powerpc-architecture arch/powerpc/mm/slice.c
> --- a/arch/powerpc/mm/slice.c~mm-use-vm_unmapped_area-on-powerpc-architecture
> +++ a/arch/powerpc/mm/slice.c
> @@ -237,36 +237,69 @@ static void slice_convert(struct mm_stru
> #endif
> }
>
> +/*
> + * Compute which slice addr is part of;
> + * set *boundary_addr to the start or end boundary of that slice
> + * (depending on 'end' parameter);
> + * return boolean indicating if the slice is marked as available in the
> + * 'available' slice_mark.
> + */
> +static bool slice_scan_available(unsigned long addr,
> + struct slice_mask available,
> + int end,
> + unsigned long *boundary_addr)
> +{
> + unsigned long slice;
> + if (addr < SLICE_LOW_TOP) {
> + slice = GET_LOW_SLICE_INDEX(addr);
> + *boundary_addr = (slice + end) << SLICE_LOW_SHIFT;
> + return !!(available.low_slices & (1u << slice));
> + } else {
> + slice = GET_HIGH_SLICE_INDEX(addr);
> + *boundary_addr = (slice + end) ?
> + ((slice + end) << SLICE_HIGH_SHIFT) : SLICE_LOW_TOP;
> + return !!(available.high_slices & (1u << slice));
> + }
> +}
> +
how about ?
static bool slice_scan_available(unsigned long addr,
struct slice_mask available,
int end,
unsigned long *boundary_addr)
{
unsigned long slice;
if (addr < SLICE_LOW_TOP) {
slice = GET_LOW_SLICE_INDEX(addr);
*boundary_addr = (slice + end) << SLICE_LOW_SHIFT;
return !!(available.low_slices & (1u << slice));
} else {
slice = GET_HIGH_SLICE_INDEX(addr);
if ((slice + end) >= SLICE_NUM_HIGH)
/* loop back in the high slice */
*boundary_addr = SLICE_LOW_TOP;
else
*boundary_addr = (slice + end) << SLICE_HIGH_SHIFT;
return !!(available.high_slices & (1u << slice));
}
}
-aneesh
^ permalink raw reply
* Re: [patch 2/2] mm: use vm_unmapped_area() on powerpc architecture
From: Michel Lespinasse @ 2013-03-18 11:23 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: akpm, paulus, linuxppc-dev
In-Reply-To: <87d2ux2c7w.fsf@linux.vnet.ibm.com>
On Mon, Mar 18, 2013 at 4:12 AM, Aneesh Kumar K.V
<aneesh.kumar@linux.vnet.ibm.com> wrote:
> how about ?
>
> static bool slice_scan_available(unsigned long addr,
> struct slice_mask available,
> int end,
> unsigned long *boundary_addr)
> {
> unsigned long slice;
> if (addr < SLICE_LOW_TOP) {
> slice = GET_LOW_SLICE_INDEX(addr);
> *boundary_addr = (slice + end) << SLICE_LOW_SHIFT;
> return !!(available.low_slices & (1u << slice));
> } else {
> slice = GET_HIGH_SLICE_INDEX(addr);
> if ((slice + end) >= SLICE_NUM_HIGH)
> /* loop back in the high slice */
> *boundary_addr = SLICE_LOW_TOP;
> else
> *boundary_addr = (slice + end) << SLICE_HIGH_SHIFT;
I don't mind having this section as an if..else rather than ?:
statement. However, the condition would need to be if (slice == 0 &&
end == 0) or if (slice + end == 0)
This is because the beginning of high slice 0 is at SLICE_LOW_TOP and not at 0,
and the end of high slice 63 is at 64TB not at SLICE_LOW_TOP.
> return !!(available.high_slices & (1u << slice));
> }
> }
--
Michel "Walken" Lespinasse
A program is never fully debugged until the last user dies.
^ permalink raw reply
* Re: [patch 2/2] mm: use vm_unmapped_area() on powerpc architecture
From: Aneesh Kumar K.V @ 2013-03-18 12:27 UTC (permalink / raw)
To: Michel Lespinasse; +Cc: akpm, paulus, linuxppc-dev
In-Reply-To: <CANN689H_Q8RBmyuF6hqOB+prZciHTUPudfhs_+y0p2peHwTdTw@mail.gmail.com>
Michel Lespinasse <walken@google.com> writes:
> On Mon, Mar 18, 2013 at 4:12 AM, Aneesh Kumar K.V
> <aneesh.kumar@linux.vnet.ibm.com> wrote:
>> how about ?
>>
>> static bool slice_scan_available(unsigned long addr,
>> struct slice_mask available,
>> int end,
>> unsigned long *boundary_addr)
>> {
>> unsigned long slice;
>> if (addr < SLICE_LOW_TOP) {
>> slice = GET_LOW_SLICE_INDEX(addr);
>> *boundary_addr = (slice + end) << SLICE_LOW_SHIFT;
>> return !!(available.low_slices & (1u << slice));
>> } else {
>> slice = GET_HIGH_SLICE_INDEX(addr);
>
>> if ((slice + end) >= SLICE_NUM_HIGH)
>> /* loop back in the high slice */
>> *boundary_addr = SLICE_LOW_TOP;
>> else
>> *boundary_addr = (slice + end) << SLICE_HIGH_SHIFT;
>
> I don't mind having this section as an if..else rather than ?:
> statement. However, the condition would need to be if (slice == 0 &&
> end == 0) or if (slice + end == 0)
>
> This is because the beginning of high slice 0 is at SLICE_LOW_TOP and not at 0,
> and the end of high slice 63 is at 64TB not at SLICE_LOW_TOP.
>
aha, I missed the fact that it was to handle slice = 0 && end == 0
case. I was looking it as looping back to start slice in high slice
range once we reached 0xffffffff. Above slice 63 in high slice, we
should have available always unset, so beyond that we can ideally
loop back to SLICE_LOW_TOP right ?
-aneesh
^ permalink raw reply
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