* [PATCH -V5 00/25] THP support for PPC64
From: Aneesh Kumar K.V @ 2013-04-04 5:57 UTC (permalink / raw)
To: benh, paulus; +Cc: linux-mm, linuxppc-dev
Hi,
This patchset adds transparent hugepage support for PPC64.
TODO:
* hash preload support in update_mmu_cache_pmd (we don't do that for hugetlb)
Some numbers:
The latency measurements code from Anton found at
http://ozlabs.org/~anton/junkcode/latency2001.c
THP disabled 64K page size
------------------------
[root@llmp24l02 ~]# ./latency2001 8G
8589934592 731.73 cycles 205.77 ns
[root@llmp24l02 ~]# ./latency2001 8G
8589934592 743.39 cycles 209.05 ns
[root@llmp24l02 ~]#
THP disabled large page via hugetlbfs
-------------------------------------
[root@llmp24l02 ~]# ./latency2001 -l 8G
8589934592 416.09 cycles 117.01 ns
[root@llmp24l02 ~]# ./latency2001 -l 8G
8589934592 415.74 cycles 116.91 ns
THP enabled 64K page size.
----------------
[root@llmp24l02 ~]# ./latency2001 8G
8589934592 405.07 cycles 113.91 ns
[root@llmp24l02 ~]# ./latency2001 8G
8589934592 411.82 cycles 115.81 ns
[root@llmp24l02 ~]#
We are close to hugetlbfs in latency and we can achieve this with zero
config/page reservation. Most of the allocations above are fault allocated.
Another test that does 50000000 random access over 1GB area goes from
2.65 seconds to 1.07 seconds with this patchset.
split_huge_page impact:
---------------------
To look at the performance impact of large page invalidate, I tried the below
experiment. The test involved, accessing a large contiguous region of memory
location as below
for (i = 0; i < size; i += PAGE_SIZE)
data[i] = i;
We wanted to access the data in sequential order so that we look at the
worst case THP performance. Accesing the data in sequential order implies
we have the Page table cached and overhead of TLB miss is as minimal as
possible. We also don't touch the entire page, because that can result in
cache evict.
After we touched the full range as above, we now call mprotect on each
of that page. A mprotect will result in a hugepage split. This should
allow us to measure the impact of hugepage split.
for (i = 0; i < size; i += PAGE_SIZE)
mprotect(&data[i], PAGE_SIZE, PROT_READ);
Split hugepage impact:
---------------------
THP enabled: 2.851561705 seconds for test completion
THP disable: 3.599146098 seconds for test completion
We are 20.7% better than non THP case even when we have all the large pages split.
Detailed output:
THP enabled:
---------------------------------------
[root@llmp24l02 ~]# cat /proc/vmstat | grep thp
thp_fault_alloc 0
thp_fault_fallback 0
thp_collapse_alloc 0
thp_collapse_alloc_failed 0
thp_split 0
thp_zero_page_alloc 0
thp_zero_page_alloc_failed 0
[root@llmp24l02 ~]# /root/thp/tools/perf/perf stat -e page-faults,dTLB-load-misses ./split-huge-page-mpro 20G
time taken to touch all the data in ns: 2763096913
Performance counter stats for './split-huge-page-mpro 20G':
1,581 page-faults
3,159 dTLB-load-misses
2.851561705 seconds time elapsed
[root@llmp24l02 ~]#
[root@llmp24l02 ~]# cat /proc/vmstat | grep thp
thp_fault_alloc 1279
thp_fault_fallback 0
thp_collapse_alloc 0
thp_collapse_alloc_failed 0
thp_split 1279
thp_zero_page_alloc 0
thp_zero_page_alloc_failed 0
[root@llmp24l02 ~]#
77.05% split-huge-page [kernel.kallsyms] [k] .clear_user_page
7.10% split-huge-page [kernel.kallsyms] [k] .perf_event_mmap_ctx
1.51% split-huge-page split-huge-page-mpro [.] 0x0000000000000a70
0.96% split-huge-page [unknown] [H] 0x000000000157e3bc
0.81% split-huge-page [kernel.kallsyms] [k] .up_write
0.76% split-huge-page [kernel.kallsyms] [k] .perf_event_mmap
0.76% split-huge-page [kernel.kallsyms] [k] .down_write
0.74% split-huge-page [kernel.kallsyms] [k] .lru_add_page_tail
0.61% split-huge-page [kernel.kallsyms] [k] .split_huge_page
0.59% split-huge-page [kernel.kallsyms] [k] .change_protection
0.51% split-huge-page [kernel.kallsyms] [k] .release_pages
0.96% split-huge-page [unknown] [H] 0x000000000157e3bc
|
|--79.44%-- reloc_start
| |
| |--86.54%-- .__pSeries_lpar_hugepage_invalidate
| | .pSeries_lpar_hugepage_invalidate
| | .hpte_need_hugepage_flush
| | .split_huge_page
| | .__split_huge_page_pmd
| | .vma_adjust
| | .vma_merge
| | .mprotect_fixup
| | .SyS_mprotect
THP disabled:
---------------
[root@llmp24l02 ~]# echo never > /sys/kernel/mm/transparent_hugepage/enabled
[root@llmp24l02 ~]# /root/thp/tools/perf/perf stat -e page-faults,dTLB-load-misses ./split-huge-page-mpro 20G
time taken to touch all the data in ns: 3513767220
Performance counter stats for './split-huge-page-mpro 20G':
3,27,726 page-faults
3,29,654 dTLB-load-misses
3.599146098 seconds time elapsed
[root@llmp24l02 ~]#
Changes from V4:
* Fix bad page error in page_table_alloc
BUG: Bad page state in process stream pfn:f1a59
page:f0000000034dc378 count:1 mapcount:0 mapping: (null) index:0x0
[c000000f322c77d0] [c00000000015e198] .bad_page+0xe8/0x140
[c000000f322c7860] [c00000000015e3c4] .free_pages_prepare+0x1d4/0x1e0
[c000000f322c7910] [c000000000160450] .free_hot_cold_page+0x50/0x230
[c000000f322c79c0] [c00000000003ad18] .page_table_alloc+0x168/0x1c0
Changes from V3:
* PowerNV boot fixes
Change from V2:
* Change patch "powerpc: Reduce PTE table memory wastage" to use much simpler approach
for PTE page sharing.
* Changes to handle huge pages in KVM code.
* Address other review comments
Changes from V1
* Address review comments
* More patch split
* Add batch hpte invalidate for hugepages.
Changes from RFC V2:
* Address review comments
* More code cleanup and patch split
Changes from RFC V1:
* HugeTLB fs now works
* Compile issues fixed
* rebased to v3.8
* Patch series reorded so that ppc64 cleanups and MM THP changes are moved
early in the series. This should help in picking those patches early.
Thanks,
-aneesh
^ permalink raw reply
* [PATCH -V5 02/25] powerpc: Save DAR and DSISR in pt_regs on MCE
From: Aneesh Kumar K.V @ 2013-04-04 5:57 UTC (permalink / raw)
To: benh, paulus; +Cc: linux-mm, linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1365055083-31956-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
We were not saving DAR and DSISR on MCE. Save then and also print the values
along with exception details in xmon.
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/kernel/exceptions-64s.S | 9 +++++++++
arch/powerpc/xmon/xmon.c | 2 +-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 0e9c48c..d02e730 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -640,9 +640,18 @@ slb_miss_user_pseries:
.align 7
.globl machine_check_common
machine_check_common:
+
+ mfspr r10,SPRN_DAR
+ std r10,PACA_EXGEN+EX_DAR(r13)
+ mfspr r10,SPRN_DSISR
+ stw r10,PACA_EXGEN+EX_DSISR(r13)
EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
FINISH_NAP
DISABLE_INTS
+ ld r3,PACA_EXGEN+EX_DAR(r13)
+ lwz r4,PACA_EXGEN+EX_DSISR(r13)
+ std r3,_DAR(r1)
+ std r4,_DSISR(r1)
bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
bl .machine_check_exception
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 1f8d2f1..a72e490 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -1423,7 +1423,7 @@ static void excprint(struct pt_regs *fp)
printf(" sp: %lx\n", fp->gpr[1]);
printf(" msr: %lx\n", fp->msr);
- if (trap == 0x300 || trap == 0x380 || trap == 0x600) {
+ if (trap == 0x300 || trap == 0x380 || trap == 0x600 || trap == 0x200) {
printf(" dar: %lx\n", fp->dar);
if (trap != 0x380)
printf(" dsisr: %lx\n", fp->dsisr);
--
1.7.10
^ permalink raw reply related
* [PATCH -V5 05/25] powerpc: Move the pte free routines from common header
From: Aneesh Kumar K.V @ 2013-04-04 5:57 UTC (permalink / raw)
To: benh, paulus; +Cc: linux-mm, linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1365055083-31956-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
This patch moves the common code to 32/64 bit headers and also duplicate
4K_PAGES and 64K_PAGES section. We will later change the 64 bit 64K_PAGES
version to support smaller PTE fragments. The patch doesn't introduce
any functional changes.
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/pgalloc-32.h | 45 ++++++++++
arch/powerpc/include/asm/pgalloc-64.h | 157 ++++++++++++++++++++++++++++++---
arch/powerpc/include/asm/pgalloc.h | 46 +---------
3 files changed, 189 insertions(+), 59 deletions(-)
diff --git a/arch/powerpc/include/asm/pgalloc-32.h b/arch/powerpc/include/asm/pgalloc-32.h
index 580cf73..27b2386 100644
--- a/arch/powerpc/include/asm/pgalloc-32.h
+++ b/arch/powerpc/include/asm/pgalloc-32.h
@@ -37,6 +37,17 @@ extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+ free_page((unsigned long)pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
+{
+ pgtable_page_dtor(ptepage);
+ __free_page(ptepage);
+}
+
static inline void pgtable_free(void *table, unsigned index_size)
{
BUG_ON(index_size); /* 32-bit doesn't use this */
@@ -45,4 +56,38 @@ static inline void pgtable_free(void *table, unsigned index_size)
#define check_pgt_cache() do { } while (0)
+#ifdef CONFIG_SMP
+static inline void pgtable_free_tlb(struct mmu_gather *tlb,
+ void *table, int shift)
+{
+ unsigned long pgf = (unsigned long)table;
+ BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+ pgf |= shift;
+ tlb_remove_table(tlb, (void *)pgf);
+}
+
+static inline void __tlb_remove_table(void *_table)
+{
+ void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
+ unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
+
+ pgtable_free(table, shift);
+}
+#else
+static inline void pgtable_free_tlb(struct mmu_gather *tlb,
+ void *table, int shift)
+{
+ pgtable_free(table, shift);
+}
+#endif
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
+ unsigned long address)
+{
+ struct page *page = page_address(table);
+
+ tlb_flush_pgtable(tlb, address);
+ pgtable_page_dtor(page);
+ pgtable_free_tlb(tlb, page, 0);
+}
#endif /* _ASM_POWERPC_PGALLOC_32_H */
diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h
index 292725c..cdbf555 100644
--- a/arch/powerpc/include/asm/pgalloc-64.h
+++ b/arch/powerpc/include/asm/pgalloc-64.h
@@ -72,8 +72,83 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte))
#define pmd_pgtable(pmd) pmd_page(pmd)
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+ unsigned long address)
+{
+ return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+ unsigned long address)
+{
+ struct page *page;
+ pte_t *pte;
+
+ pte = pte_alloc_one_kernel(mm, address);
+ if (!pte)
+ return NULL;
+ page = virt_to_page(pte);
+ pgtable_page_ctor(page);
+ return page;
+}
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+ free_page((unsigned long)pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
+{
+ pgtable_page_dtor(ptepage);
+ __free_page(ptepage);
+}
+
+static inline void pgtable_free(void *table, unsigned index_size)
+{
+ if (!index_size)
+ free_page((unsigned long)table);
+ else {
+ BUG_ON(index_size > MAX_PGTABLE_INDEX_SIZE);
+ kmem_cache_free(PGT_CACHE(index_size), table);
+ }
+}
+
+#ifdef CONFIG_SMP
+static inline void pgtable_free_tlb(struct mmu_gather *tlb,
+ void *table, int shift)
+{
+ unsigned long pgf = (unsigned long)table;
+ BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+ pgf |= shift;
+ tlb_remove_table(tlb, (void *)pgf);
+}
+
+static inline void __tlb_remove_table(void *_table)
+{
+ void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
+ unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
+
+ pgtable_free(table, shift);
+}
+#else /* !CONFIG_SMP */
+static inline void pgtable_free_tlb(struct mmu_gather *tlb,
+ void *table, int shift)
+{
+ pgtable_free(table, shift);
+}
+#endif /* CONFIG_SMP */
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
+ unsigned long address)
+{
+ struct page *page = page_address(table);
+
+ tlb_flush_pgtable(tlb, address);
+ pgtable_page_dtor(page);
+ pgtable_free_tlb(tlb, page, 0);
+}
-#else /* CONFIG_PPC_64K_PAGES */
+#else /* if CONFIG_PPC_64K_PAGES */
#define pud_populate(mm, pud, pmd) pud_set(pud, (unsigned long)pmd)
@@ -83,31 +158,25 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
pmd_set(pmd, (unsigned long)pte);
}
-#define pmd_populate(mm, pmd, pte_page) \
- pmd_populate_kernel(mm, pmd, page_address(pte_page))
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-#endif /* CONFIG_PPC_64K_PAGES */
-
-static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
+ pgtable_t pte_page)
{
- return kmem_cache_alloc(PGT_CACHE(PMD_INDEX_SIZE),
- GFP_KERNEL|__GFP_REPEAT);
+ pmd_populate_kernel(mm, pmd, page_address(pte_page));
}
-static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+static inline pgtable_t pmd_pgtable(pmd_t pmd)
{
- kmem_cache_free(PGT_CACHE(PMD_INDEX_SIZE), pmd);
+ return pmd_page(pmd);
}
static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
unsigned long address)
{
- return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
+ return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
}
static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
+ unsigned long address)
{
struct page *page;
pte_t *pte;
@@ -120,6 +189,17 @@ static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
return page;
}
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+ free_page((unsigned long)pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
+{
+ pgtable_page_dtor(ptepage);
+ __free_page(ptepage);
+}
+
static inline void pgtable_free(void *table, unsigned index_size)
{
if (!index_size)
@@ -130,6 +210,55 @@ static inline void pgtable_free(void *table, unsigned index_size)
}
}
+#ifdef CONFIG_SMP
+static inline void pgtable_free_tlb(struct mmu_gather *tlb,
+ void *table, int shift)
+{
+ unsigned long pgf = (unsigned long)table;
+ BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+ pgf |= shift;
+ tlb_remove_table(tlb, (void *)pgf);
+}
+
+static inline void __tlb_remove_table(void *_table)
+{
+ void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
+ unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
+
+ pgtable_free(table, shift);
+}
+#else /* !CONFIG_SMP */
+static inline void pgtable_free_tlb(struct mmu_gather *tlb,
+ void *table, int shift)
+{
+ pgtable_free(table, shift);
+}
+#endif /* CONFIG_SMP */
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
+ unsigned long address)
+{
+ struct page *page = page_address(table);
+
+ tlb_flush_pgtable(tlb, address);
+ pgtable_page_dtor(page);
+ pgtable_free_tlb(tlb, page, 0);
+}
+
+#endif /* CONFIG_PPC_64K_PAGES */
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+ return kmem_cache_alloc(PGT_CACHE(PMD_INDEX_SIZE),
+ GFP_KERNEL|__GFP_REPEAT);
+}
+
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+ kmem_cache_free(PGT_CACHE(PMD_INDEX_SIZE), pmd);
+}
+
+
#define __pmd_free_tlb(tlb, pmd, addr) \
pgtable_free_tlb(tlb, pmd, PMD_INDEX_SIZE)
#ifndef CONFIG_PPC_64K_PAGES
diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h
index bf301ac..e9a9f60 100644
--- a/arch/powerpc/include/asm/pgalloc.h
+++ b/arch/powerpc/include/asm/pgalloc.h
@@ -3,6 +3,7 @@
#ifdef __KERNEL__
#include <linux/mm.h>
+#include <asm-generic/tlb.h>
#ifdef CONFIG_PPC_BOOK3E
extern void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address);
@@ -13,56 +14,11 @@ static inline void tlb_flush_pgtable(struct mmu_gather *tlb,
}
#endif /* !CONFIG_PPC_BOOK3E */
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
-{
- pgtable_page_dtor(ptepage);
- __free_page(ptepage);
-}
-
#ifdef CONFIG_PPC64
#include <asm/pgalloc-64.h>
#else
#include <asm/pgalloc-32.h>
#endif
-#ifdef CONFIG_SMP
-struct mmu_gather;
-extern void tlb_remove_table(struct mmu_gather *, void *);
-
-static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift)
-{
- unsigned long pgf = (unsigned long)table;
- BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
- pgf |= shift;
- tlb_remove_table(tlb, (void *)pgf);
-}
-
-static inline void __tlb_remove_table(void *_table)
-{
- void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
- unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
-
- pgtable_free(table, shift);
-}
-#else /* CONFIG_SMP */
-static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift)
-{
- pgtable_free(table, shift);
-}
-#endif /* !CONFIG_SMP */
-
-static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage,
- unsigned long address)
-{
- tlb_flush_pgtable(tlb, address);
- pgtable_page_dtor(ptepage);
- pgtable_free_tlb(tlb, page_address(ptepage), 0);
-}
-
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PGALLOC_H */
--
1.7.10
^ permalink raw reply related
* [PATCH -V5 01/25] powerpc: Use signed formatting when printing error
From: Aneesh Kumar K.V @ 2013-04-04 5:57 UTC (permalink / raw)
To: benh, paulus; +Cc: linux-mm, linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1365055083-31956-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
PAPR defines these errors as negative values. So print them accordingly
for easy debugging.
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/platforms/pseries/lpar.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 0da39fe..a77c35b 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -155,7 +155,7 @@ static long pSeries_lpar_hpte_insert(unsigned long hpte_group,
*/
if (unlikely(lpar_rc != H_SUCCESS)) {
if (!(vflags & HPTE_V_BOLTED))
- pr_devel(" lpar err %lu\n", lpar_rc);
+ pr_devel(" lpar err %ld\n", lpar_rc);
return -2;
}
if (!(vflags & HPTE_V_BOLTED))
--
1.7.10
^ permalink raw reply related
* Re: [PATCH v2 7/11] Use stop machine to update cpu maps
From: Paul Mackerras @ 2013-04-04 4:46 UTC (permalink / raw)
To: Nathan Fontenot; +Cc: linuxppc-dev
In-Reply-To: <51509E3C.2030008@linux.vnet.ibm.com>
On Mon, Mar 25, 2013 at 01:58:04PM -0500, Nathan Fontenot wrote:
> From: Jesse Larrew <jlarrew@linux.vnet.ibm.com>
>
> The new PRRN firmware feature allows CPU and memory resources to be
> transparently reassigned across NUMA boundaries. When this happens, the
> kernel must update the node maps to reflect the new affinity
> information.
>
> Although the NUMA maps can be protected by locking primitives during the
> update itself, this is insufficient to prevent concurrent accesses to these
> structures. Since cpumask_of_node() hands out a pointer to these
> structures, they can still be modified outside of the lock. Furthermore,
> tracking down each usage of these pointers and adding locks would be quite
> invasive and difficult to maintain.
>
> Situations like these are best handled using stop_machine(). Since the NUMA
> affinity updates are exceptionally rare events, this approach has the
> benefit of not adding any overhead while accessing the NUMA maps during
> normal operation.
I notice you do one stop_machine() call for every cpu whose affinity
has changed. Couldn't we update the affinity for them all in one
stop_machine call? Given that stopping the whole machine can be quite
slow, wouldn't it be better to do one call rather than potentially
many?
Paul.
^ permalink raw reply
* Re: [PATCH v2 6/11] Update CPU Maps
From: Paul Mackerras @ 2013-04-04 4:42 UTC (permalink / raw)
To: Nathan Fontenot; +Cc: linuxppc-dev
In-Reply-To: <51509E04.9000709@linux.vnet.ibm.com>
On Mon, Mar 25, 2013 at 01:57:08PM -0500, Nathan Fontenot wrote:
> From: Jesse Larrew <jlarrew@linux.vnet.ibm.com>
>
> Platform events such as partition migration or the new PRRN firmware
> feature can cause the NUMA characteristics of a CPU to change, and these
> changes will be reflected in the device tree nodes for the affected
> CPUs.
>
> This patch registers a handler for Open Firmware device tree updates
> and reconfigures the CPU and node maps whenever the associativity
> changes. Currently, this is accomplished by marking the affected CPUs in
> the cpu_associativity_changes_mask and allowing
> arch_update_cpu_topology() to retrieve the new associativity information
> using hcall_vphn().
>
> Protecting the NUMA cpu maps from concurrent access during an update
> operation will be addressed in a subsequent patch in this series.
>
> Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
[snip]
> + if (firmware_has_feature(OV5_PRRN)) {
Shouldn't this be FW_FEATURE_PRRN? How well has this patch been
tested? :-/
Paul.
^ permalink raw reply
* Re: [PATCH v2 5/11] Update numa.c to use updated firmware_has_feature()
From: Paul Mackerras @ 2013-04-04 4:20 UTC (permalink / raw)
To: Nathan Fontenot; +Cc: linuxppc-dev
In-Reply-To: <51509DC5.3020007@linux.vnet.ibm.com>
On Mon, Mar 25, 2013 at 01:56:05PM -0500, Nathan Fontenot wrote:
> Update the numa code to use the updated firmware_has_feature() when checking
> for type 1 affinity.
>
> Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
Acked-by: Paul Mackerras <paulus@samba.org>
^ permalink raw reply
* Re: [PATCH v2 4/11] Update firmware_has_feature() to check architecture bits
From: Paul Mackerras @ 2013-04-04 4:19 UTC (permalink / raw)
To: Nathan Fontenot; +Cc: linuxppc-dev
In-Reply-To: <51509D7E.5060101@linux.vnet.ibm.com>
On Mon, Mar 25, 2013 at 01:54:54PM -0500, Nathan Fontenot wrote:
> The firmware_has_feature() function makes it easy to check for supported
> features of the hypervisor. This patch extends the capability of the
> firmware_has_feature() function to include checking for specified bits
> in vector 5 of the architecture vector as is reported in the device tree.
>
> As part of this the #defines used for the architecture vector are
> moved to prom.h and re-defined such that the vector 5 options have the vector
> index and the feature bits encoded into them. This makes for a much
> simpler design to add bits from the architecture vector to be added to
> the checking done in firmware_has_feature().
>
> Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
Acked-by: Paul Mackerras <paulus@samba.org>
The inner loop in fw_vec5_feature_init is perhaps a bit less efficient
than it could be, but I don't imagine it's going to take a noticeable
amount of time.
Paul.
^ permalink raw reply
* Re: [PATCH v2 2/11] Add PRRN Event Handler
From: Paul Mackerras @ 2013-04-04 3:34 UTC (permalink / raw)
To: Nathan Fontenot; +Cc: linuxppc-dev
In-Reply-To: <51509CF0.10200@linux.vnet.ibm.com>
On Mon, Mar 25, 2013 at 01:52:32PM -0500, Nathan Fontenot wrote:
> From: Jesse Larrew <jlarrew@linux.vnet.ibm.com>
>
> A PRRN event is signaled via the RTAS event-scan mechanism, which
> returns a Hot Plug Event message "fixed part" indicating "Platform
> Resource Reassignment". In response to the Hot Plug Event message,
> we must call ibm,update-nodes to determine which resources were
> reassigned and then ibm,update-properties to obtain the new affinity
> information about those resources.
>
> The PRRN event-scan RTAS message contains only the "fixed part" with
> the "Type" field set to the value 160 and no Extended Event Log. The
> four-byte Extended Event Log Length field is repurposed (since no
> Extended Event Log message is included) to pass the "scope" parameter
> that causes the ibm,update-nodes to return the nodes affected by the
> specific resource reassignment.
>
> This patch adds a handler in rtasd for PRRN RTAS events. The function
> pseries_devicetree_update() (from mobility.c) is used to make the
> ibm,update-nodes/ibm,update-properties RTAS calls. Updating the NUMA maps
> (handled by a subsequent patch) will require significant processing,
> so pseries_devicetree_update() is called from an asynchronous workqueue
> to allow rtasd to continue processing events. Since we flush all work
> on the queue before handling any new work there should only be one event
> in flight of being handled at a time.
^^ "of" is superfluous
In the worst case where PRRN events come close together in time, the
flush_work will block for however long it takes to do this
"significant processing", meaning that we're no better off using a
workqueue. Do we have any reason to think that these PRRN events will
normally be widely spaced in time? If so you should mention it in the
patch description.
Also, rtasd isn't actually a task, it's just a function that gets run
via schedule_delayed_work_on() and re-schedules itself each time it
runs. Is there any deadlock possibility in calling flush_work from a
work function?
Paul.
^ permalink raw reply
* Re: [PATCH v2 1/11] Expose pseries devicetree_update()
From: Paul Mackerras @ 2013-04-04 3:09 UTC (permalink / raw)
To: Nathan Fontenot; +Cc: linuxppc-dev
In-Reply-To: <51509CBA.9010101@linux.vnet.ibm.com>
On Mon, Mar 25, 2013 at 01:51:38PM -0500, Nathan Fontenot wrote:
> From: Jesse Larrew <jlarrew@linux.vnet.ibm.com>
>
> Newer firmware on Power systems can transparently reassign platform resources
> (CPU and Memory) in use. For instance, if a processor or memory unit is
> predicted to fail, the platform may transparently move the processing to an
> equivalent unused processor or the memory state to an equivalent unused
> memory unit. However, reassigning resources across NUMA boundaries may alter
> the performance of the partition. When such reassignment is necessary, the
> Platform Resource Reassignment Notification (PRRN) option provides a
> mechanism to inform the Linux kernel of changes to the NUMA affinity of
> its platform resources.
>
> When rtasd receives a PRRN event, it needs to make a series of RTAS
> calls (ibm,update-nodes and ibm,update-properties) to retrieve the
> updated device tree information. These calls are already handled in the
> pseries_devtree_update() routine used in partition migration.
>
> This patch simply exposes pseries_devicetree_update() so it can be
> called by rtasd. pseries_devicetree_update() and supporting functions
> are also modified to take a 32-bit 'scope' parameter. This parameter is
> required by the ibm,update-nodes/ibm,update-properties RTAS calls, and
> the appropriate value is contained within the RTAS event for PRRN
> notifications. In pseries_devicetree_update() it was previously
> hard-coded to 1, the scope value for partition migration.
>
> Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
Acked-by: Paul Mackerras <paulus@samba.org>
^ permalink raw reply
* RE: [PATCH 02/17] powerpc/85xx: do not sync time base at boot time
From: Zhao Chenhui-B35336 @ 2013-04-04 1:20 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <E5707E1B-20F9-495B-A83C-E115CDCEF4BE@kernel.crashing.org>
=0A=
No other reason. Just avoid doing it again at boot time in kernel.=0A=
=0A=
-Chenhui=0A=
=0A=
________________________________________=0A=
From: Kumar Gala [galak@kernel.crashing.org]=0A=
Sent: Wednesday, April 03, 2013 23:10=0A=
To: Zhao Chenhui-B35336=0A=
Cc: linuxppc-dev@lists.ozlabs.org=0A=
Subject: Re: [PATCH 02/17] powerpc/85xx: do not sync time base at boot time=
=0A=
=0A=
On Apr 3, 2013, at 8:09 AM, Zhao Chenhui wrote:=0A=
=0A=
> From: Chen-Hui Zhao <chenhui.zhao@freescale.com>=0A=
>=0A=
> The bootloader have done time base sync for all cores, so skip=0A=
> the synchronization process at boot time of kernel.=0A=
>=0A=
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>=0A=
> Signed-off-by: Li Yang <leoli@freescale.com>=0A=
> Signed-off-by: Andy Fleming <afleming@freescale.com>=0A=
> ---=0A=
> arch/powerpc/platforms/85xx/smp.c | 8 ++++++++=0A=
> 1 files changed, 8 insertions(+), 0 deletions(-)=0A=
=0A=
What harm is there in doing the sync? I'm sure there is another reason you=
want to skip the TB sync that should be conveyed in the commit message.=0A=
=0A=
- k=0A=
^ permalink raw reply
* Re: [PATCH] fsl/sata: create a sysfs entry for rx water mark
From: Jeff Garzik @ 2013-04-03 23:57 UTC (permalink / raw)
To: Qiang Liu; +Cc: linux-ide, linuxppc-dev
In-Reply-To: <1362381623-10856-1-git-send-email-qiang.liu@freescale.com>
On 03/04/2013 02:20 AM, Qiang Liu wrote:
> Support config RX WATER MARK via sysfs when running at run-time;
> A wrokaround for fix the exception happened to some WD HDD, found on
> WD3000HLFS-01G6U1, WD3000HLFS-01G6U0, some SSD disks. The read performance
> is also regression (about 30%) when use default value.
>
> According to the latest documents, 0x10 is the default value of RX WATER MARK,
> but exception/performance issue happened to some disks mentioned above.
>
> The exception log as below when testing read performance with IOZone:
> ata1.00: exception Emask 0x0 SAct 0x7 SErr 0x800000 action 0x6 frozen
> ata1: SError: { LinkSeq }
> ata1.00: failed command: READ FPDMA QUEUED
> ata1.00: cmd 60/00:00:ff:2c:14/01:00:02:00:00/40 tag 0 ncq 131072 in
> res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout)
> ata1.00: status: { DRDY }
> ata1.00: failed command: READ FPDMA QUEUED
> ata1.00: cmd 60/00:08:ff:2d:14/01:00:02:00:00/40 tag 1 ncq 131072 in
> res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout)
> ata1.00: status: { DRDY }
> ata1.00: failed command: WRITE FPDMA QUEUED
> ata1.00: cmd 61/10:10:af:08:6e/00:00:12:00:00/40 tag 2 ncq 8192 out
> res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout)
> ata1.00: status: { DRDY }
> ata1: hard resetting link
> ata1: Hardreset failed, not off-lined 0
> ata1: Signature Update detected @ 504 msecs
> ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
> ata1.00: configured for UDMA/133
> ata1.00: device reported invalid CHS sector 0
> ata1.00: device reported invalid CHS sector 0
> ata1.00: device reported invalid CHS sector 0
> ata1: EH complete
>
> The exception/performance can be resolved when RX WATER MARK value is 0x16.
>
> Signed-off-by: Qiang Liu <qiang.liu@freescale.com>
> ---
> drivers/ata/sata_fsl.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 55 insertions(+), 0 deletions(-)
applied, though it seems advisable to simply set 0x16 than all this mess
^ permalink raw reply
* Re: [RFC PATCH v3 5/6] kvm/ppc/mpic: in-kernel MPIC emulation
From: Scott Wood @ 2013-04-03 23:23 UTC (permalink / raw)
To: Scott Wood
Cc: linuxppc-dev, <paulus@samba.org>, Alexander Graf,
<kvm-ppc@vger.kernel.org>, <kvm@vger.kernel.org>
In-Reply-To: <1365026850.25627.16@snotra>
On 04/03/2013 05:07:30 PM, Scott Wood wrote:
> On 04/03/2013 04:58:56 PM, Alexander Graf wrote:
>>=20
>>=20
>> Am 03.04.2013 um 23:38 schrieb Scott Wood <scottwood@freescale.com>:
>>=20
>> > On 04/03/2013 11:19:42 AM, Alexander Graf wrote:
>> >> On 03.04.2013, at 03:57, Scott Wood wrote:
>> >> > + switch (attr->group) {
>> >> > + case KVM_DEV_MPIC_GRP_MISC:
>> >> > + switch (attr->attr) {
>> >> > + case KVM_DEV_MPIC_BASE_ADDR:
>> >> > + mutex_lock(&opp->kvm->slots_lock);
>> >> > + attr64 =3D opp->reg_base;
>> >> > + mutex_unlock(&opp->kvm->slots_lock);
>> >> > +
>> >> > + if (copy_to_user((u64 __user *)(long)attr->addr,
>> >> > + &attr64, sizeof(u64)))
>> >> u64 is tricky with put_user on 32bit hosts, so here copy_to_user =20
>> makes sense
>> >
>> > What are the issues with put_user? It looks like it's supported =20
>> with a pair of "stw" instructions.
>>=20
>> Oh? Last time I tried to use get/put_user for one_reg it failed on =20
>> ppc32. So maybe the u64 support is new?
>=20
> Not new according to git -- though I haven't tried to use it yet; =20
> maybe it's broken.
Yeah, it's broken. :-P
__get_user_size() looks OK, but __get_user_check/nocheck() goes through =20
an intermediary "unsigned long __gu_val".
There's a separate __get_user64_nocheck() that uses "long long", but no =20
"check" variant, no "put", and it's only available in 32-bit builds. =20
And it's not used anywhere (barring ungreppable token-pasting magic). =20
Sigh.
-Scott=
^ permalink raw reply
* Re: [PATCH] powerpc: add Book E support to 64-bit hibernation
From: Scott Wood @ 2013-04-03 20:15 UTC (permalink / raw)
To: Wang Dongsheng-B40534
Cc: Wood Scott-B07421, Johannes Berg, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <ABB05CD9C9F68C46A5CEDC7F15439259EDC264@039-SN2MPN1-021.039d.mgd.msft.net>
On 04/03/2013 12:36:41 AM, Wang Dongsheng-B40534 wrote:
>=20
>=20
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Wednesday, April 03, 2013 8:35 AM
> > To: Wang Dongsheng-B40534
> > Cc: Wood Scott-B07421; Johannes Berg; linuxppc-dev@lists.ozlabs.org
> > Subject: Re: [PATCH] powerpc: add Book E support to 64-bit =20
> hibernation
> >
> > On 04/02/2013 12:28:40 AM, Wang Dongsheng-B40534 wrote:
> > > Hi scott & Johannes,
> > >
> > > Thanks for reviewing.
> > >
> > > @scott, About this patch, could you please help ack this patch?
> >
> > Please investigate the issue of whether we are loading kernel module
> > code in this step, and whether cache flushing is needed as a result.
> >
> Sorry, I am not very clear what you mean.
> When the kernel boot end, modprobe some xx.ko?
Suppose, before the kernel was suspended, modules had been loaded. At =20
what point do those modules get restored, and when does the cache get =20
flushed?
-Scott=
^ permalink raw reply
* Re: [PATCH] powerpc/pci: fix 64 bit pci size issue
From: Kumar Gala @ 2013-04-03 19:08 UTC (permalink / raw)
To: Roy Zang; +Cc: scottwood, linuxppc-dev
In-Reply-To: <1364562377-7579-1-git-send-email-tie-fei.zang@freescale.com>
On Mar 29, 2013, at 8:06 AM, Roy Zang wrote:
> The size might be 64 bit, so use ilog2() instead of __ilog2() or
> __ilog2_u64().
>
> ilog2() can select 32bit or 64bit funciton automatically.
>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
> arch/powerpc/sysdev/fsl_pci.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH 5/5 v11] iommu/fsl: Freescale PAMU driver and iommu implementation.
From: Alex Williamson @ 2013-04-03 18:01 UTC (permalink / raw)
To: Joerg Roedel
Cc: stuart.yoder, linux-kernel, iommu, scottwood, Varun Sethi,
linuxppc-dev
In-Reply-To: <20130402161812.GI15687@8bytes.org>
On Tue, 2013-04-02 at 18:18 +0200, Joerg Roedel wrote:
> Cc'ing Alex Williamson
>
> Alex, can you please review the iommu-group part of this patch?
Sure, it looks pretty reasonable. AIUI, all PCI devices are below some
kind of host bridge that is either new and supports partitioning or old
and doesn't. I don't know if that's a visibility or isolation
requirement, perhaps PCI ACS-ish. In the new host bridge case, each
device gets a group. This seems not to have any quirks for
multifunction devices though. On AMD and Intel IOMMUs we test
multifunction device ACS support to determine whether all the functions
should be in the same group. Is there any reason to trust multifunction
devices on PAMU?
I also find it curious what happens to the iommu group of the host
bridge. In the partitionable case the host bridge group is removed, in
the non-partitionable case the host bridge group becomes the group for
the children, removing the host bridge. It's unique to PAMU so far that
these host bridges are even in an iommu group (x86 only adds pci
devices), but I don't see it as necessarily wrong leaving it in either
scenario. Does it solve some problem to remove them from the groups?
Thanks,
Alex
^ permalink raw reply
* RE: Clearing DBSR and DBCR0 in host handler.
From: Bhushan Bharat-R65777 @ 2013-04-03 17:33 UTC (permalink / raw)
To: Kumar Gala
Cc: linuxppc-dev@lists.ozlabs.org, Alexander Graf, Wood Scott-B07421
In-Reply-To: <C62C333B-D3CA-4AE2-B9DF-39E3CF73A3C5@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Wednesday, April 03, 2013 9:41 PM
> To: Bhushan Bharat-R65777
> Cc: linuxppc-dev@lists.ozlabs.org; Benjamin Herrenschmidt; Alexander Graf=
; Wood
> Scott-B07421
> Subject: Re: Clearing DBSR and DBCR0 in host handler.
>=20
>=20
> On Apr 3, 2013, at 10:24 AM, Bhushan Bharat-R65777 wrote:
>=20
> > Hi All,
> >
> > The kernel exception handling code for 32 bit (transfer_to_handler in
> entry_32.S) clear DBSR and load DBCR0 with 0 (global_dbcr0 variable, whic=
h is
> zero) if user space used debug (DBCR0.IDM set).
> >
> > But I do not same (clearing DBCR0 and DBSR) in 64bit exception handler.=
Is
> this an issue or I am missing something?
> >
> > Thanks
> > -Bharat
>=20
> Are you having a problem with debug w/the 64-bit kernel?
No not any issue, I was looking into code where it saves/restores of debug =
register. I observed the above said inconsistency in 32 bit and 64 bit.
> The 32-bit kernel
> supports several kernel level debug features that the 64-bit doesn't supp=
ort.
I am talking about the a user process debugging:
- A user process is under debugging using gdb. So the h/w debug register =
will have thread context.
- An interrupt/exception happens in user process.
- Now on 32 bit we clear the DBSR (pending events) and DBCR0 (so no new e=
vents get captured). But on 64bit we do not follow same, Why it is so?
Are we doing something extra on 32 bit or something is missing on 64 bi=
t?=20
Can it happen that on 64 bit some more debug events get captured and de=
bug interrupts get fired if MSR.DE is set, which is undesired.=20
Or I am missing something here ?
Thanks
-Bharat
> So if you are having an issue that might be more helpful to convey that j=
ust
> asking about exception code path.
>=20
> - k
^ permalink raw reply
* Re: [PATCH 1/5] powerpc/85xx: add SEC-5.3 device tree
From: Kumar Gala @ 2013-04-03 16:46 UTC (permalink / raw)
To: <vakul@freescale.com>; +Cc: Shaveta Leekha, linuxppc-dev
In-Reply-To: <1364886874-9580-1-git-send-email-vakul@freescale.com>
On Apr 2, 2013, at 2:14 AM, <vakul@freescale.com> <vakul@freescale.com> =
wrote:
> From: Shaveta Leekha <shaveta@freescale.com>
>=20
> Signed-off-by: Vakul Garg <vakul@freescale.com>
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi | 118 =
+++++++++++++++++++++++++
> 1 files changed, 118 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi
applied to next
- k
^ permalink raw reply
* Re: [PATCH] powerpc/fsl-msi: use a different locklcass for the cascade interrupt
From: Kumar Gala @ 2013-04-03 16:46 UTC (permalink / raw)
To: Sebastian Andrzej Siewior; +Cc: tglx, linuxppc-dev
In-Reply-To: <1364909616-59478-1-git-send-email-bigeasy@linutronix.de>
On Apr 2, 2013, at 8:33 AM, Sebastian Andrzej Siewior wrote:
> lockdep thinks that it might deadlock because it grabs a lock of the
> same class while calling the generic_irq_handler(). This annotation will
> inform lockdep that it will not.
>
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> ---
> arch/powerpc/sysdev/fsl_msi.c | 4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH 01/17] powerpc/85xx: fix a bug with the parameter of mpic_reset_core()
From: Kumar Gala @ 2013-04-03 16:46 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev
In-Reply-To: <1364994565-16010-1-git-send-email-chenhui.zhao@freescale.com>
On Apr 3, 2013, at 8:09 AM, Zhao Chenhui wrote:
> From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
>
> mpic_reset_core() need a logical cpu number instead of physical.
>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/platforms/85xx/smp.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH] sgy-cts1000: Remove __dev* attributes
From: Kumar Gala @ 2013-04-03 16:46 UTC (permalink / raw)
To: Ben Collins
Cc: linuxppc-dev@lists.ozlabs.org, Linus Torvalds,
linux-kernel@vger.kernel.org
In-Reply-To: <1A7562E2-E3F4-499C-AB2E-788D08234B02@gmail.com>
On Mar 18, 2013, at 6:19 PM, Ben Collins wrote:
> Somehow the driver snuck in with these still in it.
>
> Signed-off-by: Ben Collins <ben.c@servergy.com>
> ---
> arch/powerpc/platforms/85xx/sgy_cts1000.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH 4/5] powerpc/fsl-booke: Add B4_QDS board support
From: Kumar Gala @ 2013-04-03 16:42 UTC (permalink / raw)
To: Shaveta Leekha; +Cc: linuxppc-dev
In-Reply-To: <1364886968-9634-3-git-send-email-shaveta@freescale.com>
On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:
> - Add support for B4 board in board file b4_qds.c,
> It is common for B4860, B4420 and B4220QDS as they share same QDS =
board
> - Add B4QDS support in Kconfig and Makefile
>=20
> B4860QDS is a high-performance computing evaluation, development and
> test platform supporting the B4860 QorIQ Power Architecture processor,
> with following major features:
>=20
> - Four dual-threaded e6500 Power Architecture processors
> organized in one cluster-each core runs up to 1.8 GHz
> - Two DDR3/3L controllers for high-speed memory interface each
> runs at up to 1866.67 MHz
> - CoreNet fabric that fully supports coherency using MESI protocol
> between the e6500 cores, SC3900 FVP cores, memories and
> external interfaces.
> - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC =
5.3 and RMAN
> - Large internal cache memory with snooping and stashing =
capabilities
> - Sixteen 10-GHz SerDes lanes that serve:
> - Two SRIO interfaces. Each supports up to 4 lanes and
> a total of up to 8 lanes
> - Up to 8-lanes Common Public Radio Interface (CPRI) controller
> for glue-less antenna connection
> - Two 10-Gbit Ethernet controllers (10GEC)
> - Six 1G/2.5-Gbit Ethernet controllers for network =
communications
> - PCI Express controller
> - Debug (Aurora)
> - Various system peripherals
>=20
> B4420 and B4220 have some differences in comparison to B4860 with =
fewer core/clusters(both SC3900 and e6500),
> fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and =
reduced target frequencies.
>=20
> Key differences between B4860 and B4420:
> B4420 has:
> - Fewer e6500 cores:
> 1 cluster with 2 e6500 cores
> - Fewer SC3900 cores/clusters:
> 1 cluster with 2 SC3900 cores per cluster
> - Single DDRC @ 1.6GHz
> - 2 X 4 lane serdes
> - 3 SGMII interfaces
> - no sRIO
> - no 10G
>=20
> Key differences between B4860 and B4220:
> B4220 has:
> - Fewer e6500 cores:
> 1 cluster with 1 e6500 core
> - Fewer SC3900 cores/clusters:
> 1 cluster with 2 SC3900 cores per cluster
> - Single DDRC @ 1.33GHz
> - 2 X 2 lane serdes
> - 2 SGMII interfaces
> - no sRIO
> - no 10G
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> arch/powerpc/platforms/85xx/Kconfig | 17 ++++++
> arch/powerpc/platforms/85xx/Makefile | 1 +
> arch/powerpc/platforms/85xx/b4_qds.c | 102 =
++++++++++++++++++++++++++++++++++
> 3 files changed, 120 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/platforms/85xx/b4_qds.c
commit messages should line wrap at 75 chars.
- k=
^ permalink raw reply
* Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
From: Kumar Gala @ 2013-04-03 16:39 UTC (permalink / raw)
To: Shaveta Leekha
Cc: Zhao Chenhui, Minghuan Lian, Vakul Garg, Tang Yuantian,
Andy Fleming, Ramneek Mehresh, Varun Sethi, linuxppc-dev
In-Reply-To: <1364886968-9634-1-git-send-email-shaveta@freescale.com>
On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:
> B4860 and B4420 are similar that share some commonalities
>=20
> * common features have been added in b4si-pre.dtsi and b4si-post.dtsi
> * differences are added in respective silicon files of B4860 and B4420
What are the differences between B4860 & B4420, beyond # of cores?
>=20
> There are several things missing from the device trees of B4860 and =
B4420:
>=20
> * DPAA related nodes (Qman, Bman, Fman, Rman)
> * DSP related nodes/information
What about:
serdes, sfp [security fuse processor], thermal, gpio, maple, cpri, quad =
timers,=20
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Vakul Garg <vakul@freescale.com>
> ---
> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 94 ++++++++++
> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 49 +++++
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 138 ++++++++++++++
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 ++++++
> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 262 =
+++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/b4si-pre.dtsi | 65 +++++++
Remove b4si-pre.dtsi, there isn't enough here to warrant not just =
merging it into b4420si-pre.dtsi & b4860si-pre.dtsi
> 6 files changed, 667 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
>=20
> diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi =
b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> new file mode 100644
> index 0000000..bba0c03
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> @@ -0,0 +1,94 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + * * Redistributions of source code must retain the above =
copyright
> + * notice, this list of conditions and the following =
disclaimer.
> + * * Redistributions in binary form must reproduce the above =
copyright
> + * notice, this list of conditions and the following disclaimer =
in the
> + * documentation and/or other materials provided with the =
distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote =
products
> + * derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and =
any
> + * express or implied warranties, including, but not limited to, the =
implied
> + * warranties of merchantability and fitness for a particular purpose =
are
> + * disclaimed. In no event shall Freescale Semiconductor be liable =
for any
> + * direct, indirect, incidental, special, exemplary, or consequential =
damages
> + * (including, but not limited to, procurement of substitute goods or =
services;
> + * loss of use, data, or profits; or business interruption) however =
caused and
> + * on any theory of liability, whether in contract, strict liability, =
or tort
> + * (including negligence or otherwise) arising in any way out of the =
use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +/include/ "b4si-post.dtsi"
> +
> +/* controller at 0x200000 */
> +&pci0 {
> + compatible =3D "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
> +};
> +
> +&dcsr {
> + dcsr-epu@0 {
> + compatible =3D "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
> + };
> + dcsr-npc {
> + compatible =3D "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
> + };
> + dcsr-dpaa@9000 {
> + compatible =3D "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
> + };
> + dcsr-ocn@11000 {
> + compatible =3D "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
> + };
> + dcsr-nal@18000 {
> + compatible =3D "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
> + };
> + dcsr-rcpm@22000 {
> + compatible =3D "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
> + };
> + dcsr-snpc@30000 {
> + compatible =3D "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
> + };
> + dcsr-snpc@31000 {
> + compatible =3D "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
> + };
> + dcsr-cpu-sb-proxy@108000 {
> + compatible =3D "fsl,dcsr-e6500-sb-proxy", =
"fsl,dcsr-cpu-sb-proxy";
> + cpu-handle =3D <&cpu1>;
> + reg =3D <0x108000 0x1000 0x109000 0x1000>;
> + };
> +};
> +
> +&soc {
> + cpc: l3-cache-controller@10000 {
> + compatible =3D "fsl,b4420-l3-cache-controller", "cache";
> + };
> +
> + corenet-cf@18000 {
> + compatible =3D "fsl,b4420-corenet-cf";
> + };
> +
> + guts: global-utilities@e0000 {
> + compatible =3D "fsl,b4420-device-config", =
"fsl,qoriq-device-config-2.0";
> + };
> +
> + clockgen: global-utilities@e1000 {
> + compatible =3D "fsl,b4420-clockgen", =
"fsl,qoriq-clockgen-2";
> + };
> +
> + L2: l2-cache-controller@c20000 {
> + compatible =3D "fsl,b4420-l2-cache-controller";
> + };
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi =
b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> new file mode 100644
> index 0000000..555b0e4
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> @@ -0,0 +1,49 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (pre include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + * * Redistributions of source code must retain the above =
copyright
> + * notice, this list of conditions and the following =
disclaimer.
> + * * Redistributions in binary form must reproduce the above =
copyright
> + * notice, this list of conditions and the following disclaimer =
in the
> + * documentation and/or other materials provided with the =
distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote =
products
> + * derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and =
any
> + * express or implied warranties, including, but not limited to, the =
implied
> + * warranties of merchantability and fitness for a particular purpose =
are
> + * disclaimed. In no event shall Freescale Semiconductor be liable =
for any
> + * direct, indirect, incidental, special, exemplary, or consequential =
damages
> + * (including, but not limited to, procurement of substitute goods or =
services;
> + * loss of use, data, or profits; or business interruption) however =
caused and
> + * on any theory of liability, whether in contract, strict liability, =
or tort
> + * (including negligence or otherwise) arising in any way out of the =
use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +/dts-v1/;
> +
> +/include/ "b4si-pre.dtsi"
> +
> +/ {
> + compatible =3D "fsl,B4420";
> +
> + cpus {
> + cpu1: PowerPC,e6500@1 {
> + device_type =3D "cpu";
> + reg =3D <2 3>;
> + next-level-cache =3D <&L2>;
> + };
> + };
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi =
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> new file mode 100644
> index 0000000..f43910f
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> @@ -0,0 +1,138 @@
> +/*
> + * B4860 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + * * Redistributions of source code must retain the above =
copyright
> + * notice, this list of conditions and the following =
disclaimer.
> + * * Redistributions in binary form must reproduce the above =
copyright
> + * notice, this list of conditions and the following disclaimer =
in the
> + * documentation and/or other materials provided with the =
distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote =
products
> + * derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND =
ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE =
IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE =
ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE =
FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL =
DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR =
SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER =
CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, =
OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE =
USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/include/ "b4si-post.dtsi"
> +
> +/* controller at 0x200000 */
> +&pci0 {
> + compatible =3D "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
> +};
> +
> +&rio {
> + compatible =3D "fsl,srio";
> + interrupts =3D <16 2 1 11>;
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + fsl,iommu-parent =3D <&pamu0>;
> + ranges;
> +
> + port1 {
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + cell-index =3D <1>;
> + fsl,liodn-reg =3D <&guts 0x510>; /* RIO1LIODNR */
> + };
> +
> + port2 {
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + cell-index =3D <2>;
> + fsl,liodn-reg =3D <&guts 0x514>; /* RIO2LIODNR */
> + };
> +};
> +
> +&dcsr {
> + dcsr-epu@0 {
> + compatible =3D "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
> + };
> + dcsr-npc {
> + compatible =3D "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
> + };
> + dcsr-dpaa@9000 {
> + compatible =3D "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
> + };
> + dcsr-ocn@11000 {
> + compatible =3D "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
> + };
> + dcsr-ddr@13000 {
> + compatible =3D "fsl,dcsr-ddr";
> + dev-handle =3D <&ddr2>;
> + reg =3D <0x13000 0x1000>;
> + };
> + dcsr-nal@18000 {
> + compatible =3D "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
> + };
> + dcsr-rcpm@22000 {
> + compatible =3D "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
> + };
> + dcsr-snpc@30000 {
> + compatible =3D "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
> + };
> + dcsr-snpc@31000 {
> + compatible =3D "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
> + };
> + dcsr-cpu-sb-proxy@108000 {
> + compatible =3D "fsl,dcsr-e6500-sb-proxy", =
"fsl,dcsr-cpu-sb-proxy";
> + cpu-handle =3D <&cpu1>;
> + reg =3D <0x108000 0x1000 0x109000 0x1000>;
> + };
> + dcsr-cpu-sb-proxy@110000 {
> + compatible =3D "fsl,dcsr-e6500-sb-proxy", =
"fsl,dcsr-cpu-sb-proxy";
> + cpu-handle =3D <&cpu2>;
> + reg =3D <0x110000 0x1000 0x111000 0x1000>;
> + };
> + dcsr-cpu-sb-proxy@118000 {
> + compatible =3D "fsl,dcsr-e6500-sb-proxy", =
"fsl,dcsr-cpu-sb-proxy";
> + cpu-handle =3D <&cpu3>;
> + reg =3D <0x118000 0x1000 0x119000 0x1000>;
> + };
> +};
> +
> +&soc {
> + ddr2: memory-controller@9000 {
> + compatible =3D "fsl,qoriq-memory-controller-v4.5", =
"fsl,qoriq-memory-controller";
> + reg =3D <0x9000 0x1000>;
> + interrupts =3D <16 2 1 9>;
> + };
> +
> + cpc: l3-cache-controller@10000 {
> + compatible =3D "fsl,b4860-l3-cache-controller", "cache";
> + };
> +
> + corenet-cf@18000 {
> + compatible =3D "fsl,b4860-corenet-cf";
> + };
> +
> + guts: global-utilities@e0000 {
> + compatible =3D "fsl,b4860-device-config", =
"fsl,qoriq-device-config-2.0";
> + };
> +
> + clockgen: global-utilities@e1000 {
> + compatible =3D "fsl,b4860-clockgen", =
"fsl,qoriq-clockgen-2";
> + };
> +
> + L2: l2-cache-controller@c20000 {
> + compatible =3D "fsl,b4860-l2-cache-controller";
> + };
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi =
b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> new file mode 100644
> index 0000000..f5737a0
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> @@ -0,0 +1,59 @@
> +/*
> + * B4860 Silicon/SoC Device Tree Source (pre include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + * * Redistributions of source code must retain the above =
copyright
> + * notice, this list of conditions and the following =
disclaimer.
> + * * Redistributions in binary form must reproduce the above =
copyright
> + * notice, this list of conditions and the following disclaimer =
in the
> + * documentation and/or other materials provided with the =
distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote =
products
> + * derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND =
ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE =
IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE =
ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE =
FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL =
DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR =
SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER =
CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, =
OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE =
USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/dts-v1/;
> +
> +/include/ "b4si-pre.dtsi"
> +
> +/ {
> + compatible =3D "fsl,B4860";
> +
> + cpus {
> + cpu1: PowerPC,e6500@1 {
> + device_type =3D "cpu";
> + reg =3D <2 3>;
> + next-level-cache =3D <&L2>;
> + };
> + cpu2: PowerPC,e6500@2 {
> + device_type =3D "cpu";
> + reg =3D <4 5>;
> + next-level-cache =3D <&L2>;
> + };
> + cpu3: PowerPC,e6500@3 {
> + device_type =3D "cpu";
> + reg =3D <6 7>;
> + next-level-cache =3D <&L2>;
> + };
> + };
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi =
b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> new file mode 100644
> index 0000000..06c97a2
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> @@ -0,0 +1,262 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + * * Redistributions of source code must retain the above =
copyright
> + * notice, this list of conditions and the following =
disclaimer.
> + * * Redistributions in binary form must reproduce the above =
copyright
> + * notice, this list of conditions and the following disclaimer =
in the
> + * documentation and/or other materials provided with the =
distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote =
products
> + * derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and =
any
> + * express or implied warranties, including, but not limited to, the =
implied
> + * warranties of merchantability and fitness for a particular purpose =
are
> + * disclaimed. In no event shall Freescale Semiconductor be liable =
for any
> + * direct, indirect, incidental, special, exemplary, or consequential =
damages
> + * (including, but not limited to, procurement of substitute goods or =
services;
> + * loss of use, data, or profits; or business interruption) however =
caused and
> + * on any theory of liability, whether in contract, strict liability, =
or tort
> + * (including negligence or otherwise) arising in any way out of the =
use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +&ifc {
> + #address-cells =3D <2>;
> + #size-cells =3D <1>;
> + compatible =3D "fsl,ifc", "simple-bus";
> + interrupts =3D <25 2 0 0>;
> +};
> +
> +/* controller at 0x200000 */
> +&pci0 {
> + compatible =3D "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
> + device_type =3D "pci";
> + #size-cells =3D <2>;
> + #address-cells =3D <3>;
> + bus-range =3D <0x0 0xff>;
> + interrupts =3D <20 2 0 0>;
> + fsl,iommu-parent =3D <&pamu0>;
> + pcie@0 {
> + #interrupt-cells =3D <1>;
> + #size-cells =3D <2>;
> + #address-cells =3D <3>;
> + device_type =3D "pci";
> + interrupts =3D <20 2 0 0>;
> + interrupt-map-mask =3D <0xf800 0 0 7>;
> + interrupt-map =3D <
> + /* IDSEL 0x0 */
> + 0000 0 0 1 &mpic 40 1 0 0
> + 0000 0 0 2 &mpic 1 1 0 0
> + 0000 0 0 3 &mpic 2 1 0 0
> + 0000 0 0 4 &mpic 3 1 0 0
> + >;
> + };
> +};
> +
> +&dcsr {
> + #address-cells =3D <1>;
> + #size-cells =3D <1>;
> + compatible =3D "fsl,dcsr", "simple-bus";
> +
> + dcsr-epu@0 {
> + compatible =3D "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
> + interrupts =3D <52 2 0 0
> + 84 2 0 0
> + 85 2 0 0
> + 94 2 0 0
> + 95 2 0 0>;
> + reg =3D <0x0 0x1000>;
> + };
> + dcsr-npc {
> + compatible =3D "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
> + reg =3D <0x1000 0x1000 0x1002000 0x10000>;
> + };
> + dcsr-nxc@2000 {
> + compatible =3D "fsl,dcsr-nxc";
> + reg =3D <0x2000 0x1000>;
> + };
> + dcsr-corenet {
> + compatible =3D "fsl,dcsr-corenet";
> + reg =3D <0x8000 0x1000 0x1A000 0x1000>;
> + };
> + dcsr-dpaa@9000 {
> + compatible =3D "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
> + reg =3D <0x9000 0x1000>;
> + };
> + dcsr-ocn@11000 {
> + compatible =3D "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
> + reg =3D <0x11000 0x1000>;
> + };
> + dcsr-ddr@12000 {
> + compatible =3D "fsl,dcsr-ddr";
> + dev-handle =3D <&ddr1>;
> + reg =3D <0x12000 0x1000>;
> + };
> + dcsr-nal@18000 {
> + compatible =3D "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
> + reg =3D <0x18000 0x1000>;
> + };
> + dcsr-rcpm@22000 {
> + compatible =3D "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
> + reg =3D <0x22000 0x1000>;
> + };
> + dcsr-snpc@30000 {
> + compatible =3D "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
> + reg =3D <0x30000 0x1000 0x1022000 0x10000>;
> + };
> + dcsr-snpc@31000 {
> + compatible =3D "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
> + reg =3D <0x31000 0x1000 0x1042000 0x10000>;
> + };
> + dcsr-cpu-sb-proxy@100000 {
> + compatible =3D "fsl,dcsr-e6500-sb-proxy", =
"fsl,dcsr-cpu-sb-proxy";
> + cpu-handle =3D <&cpu0>;
> + reg =3D <0x100000 0x1000 0x101000 0x1000>;
> + };
> +};
> +
> +&soc {
> + #address-cells =3D <1>;
> + #size-cells =3D <1>;
> + device_type =3D "soc";
> + compatible =3D "simple-bus";
> +
> + soc-sram-error {
> + compatible =3D "fsl,soc-sram-error";
> + interrupts =3D <16 2 1 2>;
> + };
> +
> + corenet-law@0 {
> + compatible =3D "fsl,corenet-law";
> + reg =3D <0x0 0x1000>;
> + fsl,num-laws =3D <32>;
> + };
> +
> + ddr1: memory-controller@8000 {
> + compatible =3D "fsl,qoriq-memory-controller-v4.5", =
"fsl,qoriq-memory-controller";
> + reg =3D <0x8000 0x1000>;
> + interrupts =3D <16 2 1 8>;
> + };
> +
> + cpc: l3-cache-controller@10000 {
> + compatible =3D "fsl,b4-l3-cache-controller", "cache";
> + reg =3D <0x10000 0x1000>;
> + interrupts =3D <16 2 1 4>;
> + };
> +
> + corenet-cf@18000 {
> + compatible =3D "fsl,b4-corenet-cf";
> + reg =3D <0x18000 0x1000>;
> + interrupts =3D <16 2 1 0>;
> + fsl,ccf-num-csdids =3D <32>;
> + fsl,ccf-num-snoopids =3D <32>;
> + };
> +
> + iommu@20000 {
> + compatible =3D "fsl,pamu-v1.0", "fsl,pamu";
> + reg =3D <0x20000 0x4000>;
> + #address-cells =3D <1>;
> + #size-cells =3D <1>;
> + interrupts =3D <
> + 24 2 0 0
> + 16 2 1 1>;
> +
> +
> + /* PCIe, DMA, SRIO */
> + pamu0: pamu@0 {
> + reg =3D <0 0x1000>;
> + fsl,primary-cache-geometry =3D <8 1>;
> + fsl,secondary-cache-geometry =3D <32 2>;
> + };
> +
> + /* AXI2, Maple */
> + pamu1: pamu@1000 {
> + reg =3D <0x1000 0x1000>;
> + fsl,primary-cache-geometry =3D <32 1>;
> + fsl,secondary-cache-geometry =3D <32 2>;
> + };
> +
> + /* Q/BMan */
> + pamu2: pamu@2000 {
> + reg =3D <0x2000 0x1000>;
> + fsl,primary-cache-geometry =3D <32 1>;
> + fsl,secondary-cache-geometry =3D <32 2>;
> + };
> +
> + /* AXI1, FMAN */
> + pamu3: pamu@3000 {
> + reg =3D <0x3000 0x1000>;
> + fsl,primary-cache-geometry =3D <32 1>;
> + fsl,secondary-cache-geometry =3D <32 2>;
> + };
> + };
> +
> +/include/ "qoriq-mpic.dtsi"
> +
> + guts: global-utilities@e0000 {
> + compatible =3D "fsl,b4-device-config";
> + reg =3D <0xe0000 0xe00>;
> + fsl,has-rstcr;
> + fsl,liodn-bits =3D <12>;
> + };
> +
> + rcpm: global-utilities@e2000 {
> + compatible =3D "fsl,b4-rcpm", "fsl,qoriq-rcpm-2";
> + reg =3D <0xe2000 0x1000>;
> + };
> +
> +/include/ "qoriq-dma-0.dtsi"
> + dma@100300 {
> + fsl,iommu-parent =3D <&pamu0>;
> + fsl,liodn-reg =3D <&guts 0x580>; /* DMA1LIODNR */
> + };
> +
> +/include/ "qoriq-dma-1.dtsi"
> + dma@101300 {
> + fsl,iommu-parent =3D <&pamu0>;
> + fsl,liodn-reg =3D <&guts 0x584>; /* DMA2LIODNR */
> + };
> +
> +/include/ "qonverge-usb2-dr-0.dtsi"
> + usb0: usb@210000 {
> + compatible =3D "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
> + fsl,iommu-parent =3D <&pamu1>;
> + fsl,liodn-reg =3D <&guts 0x520>; /* USB1LIODNR */
> + };
> +
> +/include/ "qoriq-espi-0.dtsi"
> + spi@110000 {
> + fsl,espi-num-chipselects =3D <4>;
> + };
> +
> +/include/ "qoriq-esdhc-0.dtsi"
> + sdhc@114000 {
> + sdhci,auto-cmd12;
> + fsl,iommu-parent =3D <&pamu1>;
> + fsl,liodn-reg =3D <&guts 0x530>; /* eSDHCLIODNR */
> + };
> +
> +/include/ "qoriq-i2c-0.dtsi"
> +/include/ "qoriq-i2c-1.dtsi"
> +/include/ "qoriq-duart-0.dtsi"
> +/include/ "qoriq-duart-1.dtsi"
> +/include/ "qoriq-sec5.3-0.dtsi"
> +
> + L2: l2-cache-controller@c20000 {
> + compatible =3D "fsl,b4-l2-cache-controller";
> + reg =3D <0xc20000 0x1000>;
white space issue
> + next-level-cache =3D <&cpc>;
> + };
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi =
b/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
> new file mode 100644
> index 0000000..b6161c8
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
> @@ -0,0 +1,65 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (pre include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + * * Redistributions of source code must retain the above =
copyright
> + * notice, this list of conditions and the following =
disclaimer.
> + * * Redistributions in binary form must reproduce the above =
copyright
> + * notice, this list of conditions and the following disclaimer =
in the
> + * documentation and/or other materials provided with the =
distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote =
products
> + * derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and =
any
> + * express or implied warranties, including, but not limited to, the =
implied
> + * warranties of merchantability and fitness for a particular purpose =
are
> + * disclaimed. In no event shall Freescale Semiconductor be liable =
for any
> + * direct, indirect, incidental, special, exemplary, or consequential =
damages
> + * (including, but not limited to, procurement of substitute goods or =
services;
> + * loss of use, data, or profits; or business interruption) however =
caused and
> + * on any theory of liability, whether in contract, strict liability, =
or tort
> + * (including negligence or otherwise) arising in any way out of the =
use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +/ {
> + compatible =3D "fsl,B4";
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + interrupt-parent =3D <&mpic>;
> +
> + aliases {
> + ccsr =3D &soc;
> + dcsr =3D &dcsr;
> +
> + serial0 =3D &serial0;
> + serial1 =3D &serial1;
> + serial2 =3D &serial2;
> + serial3 =3D &serial3;
> + pci0 =3D &pci0;
> + dma0 =3D &dma0;
> + dma1 =3D &dma1;
> + sdhc =3D &sdhc;
> + };
> +
> + cpus {
> + #address-cells =3D <1>;
> + #size-cells =3D <0>;
> +
> + cpu0: PowerPC,e6500@0 {
> + device_type =3D "cpu";
> + reg =3D <0 1>;
> + next-level-cache =3D <&L2>;
> + };
> + };
> +};
> --=20
> 1.7.6.GIT
>=20
^ permalink raw reply
* Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
From: Scott Wood @ 2013-04-03 16:39 UTC (permalink / raw)
To: Leekha Shaveta-B20052
Cc: Wood Scott-B07421, Zhao Chenhui-B35336, Mehresh Ramneek-B31383,
Garg Vakul-B16394, Lian Minghuan-B31939, Tang Yuantian-B29983,
Fleming Andy-AFLEMING, Sethi Varun-B16395,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <E12D2F89F87F4A49B0320A4C2DE7E74915165F@039-SN2MPN1-011.039d.mgd.msft.net>
On 04/03/2013 01:42:14 AM, Leekha Shaveta-B20052 wrote:
>=20
>=20
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, April 03, 2013 12:49 AM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian =20
> Minghuan-B31939; Leekha Shaveta-B20052; Garg Vakul-B16394; Tang =20
> Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi =20
> Varun-B16395
> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon =20
> device tree files for B4860 and B4420
>=20
> On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
> > +/ {
> > + compatible =3D "fsl,B4860";
> > +
> > + cpus {
> > + cpu1: PowerPC,e6500@1 {
> > + device_type =3D "cpu";
> > + reg =3D <2 3>;
> > + next-level-cache =3D <&L2>;
> > + };
> > + cpu2: PowerPC,e6500@2 {
> > + device_type =3D "cpu";
> > + reg =3D <4 5>;
> > + next-level-cache =3D <&L2>;
> > + };
> > + cpu3: PowerPC,e6500@3 {
> > + device_type =3D "cpu";
> > + reg =3D <6 7>;
> > + next-level-cache =3D <&L2>;
> > + };
>=20
> The unit addresses need to match "reg".
> [SL] You mean "@1" should match to "reg =3D <2 3>" ?
Yes, it should be "@2" for that node.
> As each e6500 core in B4860 is dual- threaded, reg property here =20
> represents the thread's identifier in that PA core.
>=20
> So convention used in T4 and B4 is: core 0 having threads 0 and 1,
> Core 1 having <2 3> and =20
> so on....
The convention used in device trees is that the unit address matches =20
the reg.
-Scott=
^ permalink raw reply
* Re: [PATCH V3 1/2] powerpc/MPIC: Add get_version API both for internal and external use
From: Scott Wood @ 2013-04-03 16:17 UTC (permalink / raw)
To: Jia Hongtao; +Cc: hongtao.jia, B07421, linuxppc-dev
In-Reply-To: <1364954598-31914-1-git-send-email-hongtao.jia@freescale.com>
On 04/02/2013 09:03:17 PM, Jia Hongtao wrote:
> MPIC version is useful information for both mpic_alloc() and =20
> mpic_init().
> The patch provide an API to get MPIC version for reusing the code.
> Also, some other IP block may need MPIC version for their own use.
> The API for external use is also provided.
>=20
> Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> Changes for V3:
> * change the name of function from mpic_primary_get_version() to
> fsl_mpic_primary_get_version().
> * return 0 if mpic_primary is null.
>=20
> arch/powerpc/include/asm/mpic.h | 3 +++
> arch/powerpc/sysdev/mpic.c | 29 ++++++++++++++++++++++-------
> 2 files changed, 25 insertions(+), 7 deletions(-)
>=20
> diff --git a/arch/powerpc/include/asm/mpic.h =20
> b/arch/powerpc/include/asm/mpic.h
> index c0f9ef9..ea6bf72 100644
> --- a/arch/powerpc/include/asm/mpic.h
> +++ b/arch/powerpc/include/asm/mpic.h
> @@ -393,6 +393,9 @@ struct mpic
> #define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* =20
> Original MPIC */
> #define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* =20
> Tsi108/109 PIC */
>=20
> +/* Get the version of primary MPIC */
> +extern u32 fsl_mpic_primary_get_version(void);
> +
> /* Allocate the controller structure and setup the linux irq descs
> * for the range if interrupts passed in. No HW initialization is
> * actually performed.
> diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
> index d30e6a6..e793337 100644
> --- a/arch/powerpc/sysdev/mpic.c
> +++ b/arch/powerpc/sysdev/mpic.c
> @@ -1165,10 +1165,30 @@ static struct irq_domain_ops mpic_host_ops =3D {
> .xlate =3D mpic_host_xlate,
> };
>=20
> +static u32 mpic_get_version(struct mpic *mpic)
> +{
> + u32 brr1;
> +
> + brr1 =3D _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
> + MPIC_FSL_BRR1);
> +
> + return brr1 & MPIC_FSL_BRR1_VER;
> +}
This one should have "fsl" in the name as well.
-Scott=
^ permalink raw reply
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