* [PATCH v2 43/45] sh: Use get/put_online_cpus_atomic() to prevent CPU offline
From: Srivatsa S. Bhat @ 2013-06-25 20:33 UTC (permalink / raw)
To: tglx, peterz, tj, oleg, paulmck, rusty, mingo, akpm, namhyung,
walken, vincent.guittot, laijs
Cc: linux-arch, nikunj, zhong, linux-pm, fweisbec, linux-sh,
linux-kernel, rostedt, xiaoguangrong, sbw, Paul Mundt, wangyun,
Srivatsa S. Bhat, netdev, Thomas Gleixner, linuxppc-dev
In-Reply-To: <20130625202452.16593.22810.stgit@srivatsabhat.in.ibm.com>
Once stop_machine() is gone from the CPU offline path, we won't be able
to depend on disabling preemption to prevent CPUs from going offline
from under us.
Use the get/put_online_cpus_atomic() APIs to prevent CPUs from going
offline, while invoking from atomic context.
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-sh@vger.kernel.org
Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
---
arch/sh/kernel/smp.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
index 4569645..42ec182 100644
--- a/arch/sh/kernel/smp.c
+++ b/arch/sh/kernel/smp.c
@@ -357,7 +357,7 @@ static void flush_tlb_mm_ipi(void *mm)
*/
void flush_tlb_mm(struct mm_struct *mm)
{
- preempt_disable();
+ get_online_cpus_atomic();
if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
smp_call_function(flush_tlb_mm_ipi, (void *)mm, 1);
@@ -369,7 +369,7 @@ void flush_tlb_mm(struct mm_struct *mm)
}
local_flush_tlb_mm(mm);
- preempt_enable();
+ put_online_cpus_atomic();
}
struct flush_tlb_data {
@@ -390,7 +390,7 @@ void flush_tlb_range(struct vm_area_struct *vma,
{
struct mm_struct *mm = vma->vm_mm;
- preempt_disable();
+ get_online_cpus_atomic();
if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
struct flush_tlb_data fd;
@@ -405,7 +405,7 @@ void flush_tlb_range(struct vm_area_struct *vma,
cpu_context(i, mm) = 0;
}
local_flush_tlb_range(vma, start, end);
- preempt_enable();
+ put_online_cpus_atomic();
}
static void flush_tlb_kernel_range_ipi(void *info)
@@ -433,7 +433,7 @@ static void flush_tlb_page_ipi(void *info)
void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
- preempt_disable();
+ get_online_cpus_atomic();
if ((atomic_read(&vma->vm_mm->mm_users) != 1) ||
(current->mm != vma->vm_mm)) {
struct flush_tlb_data fd;
@@ -448,7 +448,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
cpu_context(i, vma->vm_mm) = 0;
}
local_flush_tlb_page(vma, page);
- preempt_enable();
+ put_online_cpus_atomic();
}
static void flush_tlb_one_ipi(void *info)
^ permalink raw reply related
* [PATCH v2 44/45] sparc: Use get/put_online_cpus_atomic() to prevent CPU offline
From: Srivatsa S. Bhat @ 2013-06-25 20:33 UTC (permalink / raw)
To: tglx, peterz, tj, oleg, paulmck, rusty, mingo, akpm, namhyung,
walken, vincent.guittot, laijs
Cc: linux-arch, nikunj, zhong, linux-pm, fweisbec, linux-kernel,
rostedt, xiaoguangrong, Sam Ravnborg, sbw, Dave Kleikamp, wangyun,
Srivatsa S. Bhat, netdev, sparclinux, Thomas Gleixner,
linuxppc-dev, David S. Miller
In-Reply-To: <20130625202452.16593.22810.stgit@srivatsabhat.in.ibm.com>
Once stop_machine() is gone from the CPU offline path, we won't be able
to depend on disabling preemption to prevent CPUs from going offline
from under us.
Use the get/put_online_cpus_atomic() APIs to prevent CPUs from going
offline, while invoking from atomic context.
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Dave Kleikamp <dave.kleikamp@oracle.com>
Cc: sparclinux@vger.kernel.org
Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
---
arch/sparc/kernel/smp_64.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/sparc/kernel/smp_64.c b/arch/sparc/kernel/smp_64.c
index 77539ed..4f71a95 100644
--- a/arch/sparc/kernel/smp_64.c
+++ b/arch/sparc/kernel/smp_64.c
@@ -792,7 +792,9 @@ static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 d
/* Send cross call to all processors except self. */
static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
{
+ get_online_cpus_atomic();
smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
+ put_online_cpus_atomic();
}
extern unsigned long xcall_sync_tick;
@@ -896,7 +898,7 @@ void smp_flush_dcache_page_impl(struct page *page, int cpu)
atomic_inc(&dcpage_flushes);
#endif
- this_cpu = get_cpu();
+ this_cpu = get_online_cpus_atomic();
if (cpu == this_cpu) {
__local_flush_dcache_page(page);
@@ -922,7 +924,7 @@ void smp_flush_dcache_page_impl(struct page *page, int cpu)
}
}
- put_cpu();
+ put_online_cpus_atomic();
}
void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
@@ -933,7 +935,7 @@ void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
if (tlb_type == hypervisor)
return;
- preempt_disable();
+ get_online_cpus_atomic();
#ifdef CONFIG_DEBUG_DCFLUSH
atomic_inc(&dcpage_flushes);
@@ -958,7 +960,7 @@ void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
}
__local_flush_dcache_page(page);
- preempt_enable();
+ put_online_cpus_atomic();
}
void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
@@ -1150,6 +1152,7 @@ void smp_capture(void)
{
int result = atomic_add_ret(1, &smp_capture_depth);
+ get_online_cpus_atomic();
if (result == 1) {
int ncpus = num_online_cpus();
@@ -1166,6 +1169,7 @@ void smp_capture(void)
printk("done\n");
#endif
}
+ put_online_cpus_atomic();
}
void smp_release(void)
^ permalink raw reply related
* [PATCH v2 45/45] tile: Use get/put_online_cpus_atomic() to prevent CPU offline
From: Srivatsa S. Bhat @ 2013-06-25 20:34 UTC (permalink / raw)
To: tglx, peterz, tj, oleg, paulmck, rusty, mingo, akpm, namhyung,
walken, vincent.guittot, laijs
Cc: linux-arch, nikunj, zhong, linux-pm, Chris Metcalf, fweisbec,
linux-kernel, rostedt, xiaoguangrong, sbw, wangyun,
Srivatsa S. Bhat, netdev, linuxppc-dev
In-Reply-To: <20130625202452.16593.22810.stgit@srivatsabhat.in.ibm.com>
Once stop_machine() is gone from the CPU offline path, we won't be able
to depend on disabling preemption to prevent CPUs from going offline
from under us.
Use the get/put_online_cpus_atomic() APIs to prevent CPUs from going
offline, while invoking from atomic context.
Cc: Chris Metcalf <cmetcalf@tilera.com>
Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
---
arch/tile/kernel/module.c | 3 +++
arch/tile/kernel/tlb.c | 15 +++++++++++++++
arch/tile/mm/homecache.c | 3 +++
3 files changed, 21 insertions(+)
diff --git a/arch/tile/kernel/module.c b/arch/tile/kernel/module.c
index 4918d91..db7d858 100644
--- a/arch/tile/kernel/module.c
+++ b/arch/tile/kernel/module.c
@@ -20,6 +20,7 @@
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/kernel.h>
+#include <linux/cpu.h>
#include <asm/pgtable.h>
#include <asm/homecache.h>
#include <arch/opcode.h>
@@ -79,8 +80,10 @@ void module_free(struct module *mod, void *module_region)
vfree(module_region);
/* Globally flush the L1 icache. */
+ get_online_cpus_atomic();
flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,
0, 0, 0, NULL, NULL, 0);
+ put_online_cpus_atomic();
/*
* FIXME: If module_region == mod->module_init, trim exception
diff --git a/arch/tile/kernel/tlb.c b/arch/tile/kernel/tlb.c
index 3fd54d5..a32b9dd 100644
--- a/arch/tile/kernel/tlb.c
+++ b/arch/tile/kernel/tlb.c
@@ -14,6 +14,7 @@
*/
#include <linux/cpumask.h>
+#include <linux/cpu.h>
#include <linux/module.h>
#include <linux/hugetlb.h>
#include <asm/tlbflush.h>
@@ -35,6 +36,8 @@ void flush_tlb_mm(struct mm_struct *mm)
{
HV_Remote_ASID asids[NR_CPUS];
int i = 0, cpu;
+
+ get_online_cpus_atomic();
for_each_cpu(cpu, mm_cpumask(mm)) {
HV_Remote_ASID *asid = &asids[i++];
asid->y = cpu / smp_topology.width;
@@ -43,6 +46,7 @@ void flush_tlb_mm(struct mm_struct *mm)
}
flush_remote(0, HV_FLUSH_EVICT_L1I, mm_cpumask(mm),
0, 0, 0, NULL, asids, i);
+ put_online_cpus_atomic();
}
void flush_tlb_current_task(void)
@@ -55,8 +59,11 @@ void flush_tlb_page_mm(struct vm_area_struct *vma, struct mm_struct *mm,
{
unsigned long size = vma_kernel_pagesize(vma);
int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
+
+ get_online_cpus_atomic();
flush_remote(0, cache, mm_cpumask(mm),
va, size, size, mm_cpumask(mm), NULL, 0);
+ put_online_cpus_atomic();
}
void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
@@ -71,13 +78,18 @@ void flush_tlb_range(struct vm_area_struct *vma,
unsigned long size = vma_kernel_pagesize(vma);
struct mm_struct *mm = vma->vm_mm;
int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
+
+ get_online_cpus_atomic();
flush_remote(0, cache, mm_cpumask(mm), start, end - start, size,
mm_cpumask(mm), NULL, 0);
+ put_online_cpus_atomic();
}
void flush_tlb_all(void)
{
int i;
+
+ get_online_cpus_atomic();
for (i = 0; ; ++i) {
HV_VirtAddrRange r = hv_inquire_virtual(i);
if (r.size == 0)
@@ -89,10 +101,13 @@ void flush_tlb_all(void)
r.start, r.size, HPAGE_SIZE, cpu_online_mask,
NULL, 0);
}
+ put_online_cpus_atomic();
}
void flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
+ get_online_cpus_atomic();
flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,
start, end - start, PAGE_SIZE, cpu_online_mask, NULL, 0);
+ put_online_cpus_atomic();
}
diff --git a/arch/tile/mm/homecache.c b/arch/tile/mm/homecache.c
index 1ae9119..7ff5bf0 100644
--- a/arch/tile/mm/homecache.c
+++ b/arch/tile/mm/homecache.c
@@ -397,9 +397,12 @@ void homecache_change_page_home(struct page *page, int order, int home)
BUG_ON(page_count(page) > 1);
BUG_ON(page_mapcount(page) != 0);
kva = (unsigned long) page_address(page);
+
+ get_online_cpus_atomic();
flush_remote(0, HV_FLUSH_EVICT_L2, &cpu_cacheable_map,
kva, pages * PAGE_SIZE, PAGE_SIZE, cpu_online_mask,
NULL, 0);
+ put_online_cpus_atomic();
for (i = 0; i < pages; ++i, kva += PAGE_SIZE) {
pte_t *ptep = virt_to_pte(NULL, kva);
^ permalink raw reply related
* Re: [PATCH v2 25/45] staging/octeon: Use get/put_online_cpus_atomic() to prevent CPU offline
From: Greg Kroah-Hartman @ 2013-06-25 20:45 UTC (permalink / raw)
To: Srivatsa S. Bhat
Cc: David Daney, peterz, fweisbec, linux-kernel, walken, mingo,
linux-arch, vincent.guittot, xiaoguangrong, wangyun, paulmck,
devel, nikunj, linux-pm, rusty, rostedt, namhyung, tglx, laijs,
zhong, netdev, oleg, sbw, tj, akpm, linuxppc-dev
In-Reply-To: <20130625203003.16593.38565.stgit@srivatsabhat.in.ibm.com>
On Wed, Jun 26, 2013 at 02:00:04AM +0530, Srivatsa S. Bhat wrote:
> Once stop_machine() is gone from the CPU offline path, we won't be able
> to depend on disabling preemption to prevent CPUs from going offline
> from under us.
>
> Use the get/put_online_cpus_atomic() APIs to prevent CPUs from going
> offline, while invoking from atomic context.
>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: devel@driverdev.osuosl.org
> Acked-by: David Daney <david.daney@cavium.com>
> Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply
* Re: mpc85xx_edac.c: Should the mpc85xx_l2_isr be shared irqs?
From: Scott Wood @ 2013-06-25 20:54 UTC (permalink / raw)
To: Xufeng Zhang; +Cc: linuxppc-dev
In-Reply-To: <CA+=dFzhEf12XKxL5=M5vhtoYin9Ct=RucNCh=v-FVQUSPrkOww@mail.gmail.com>
On Wed, Jul 18, 2012 at 05:00:29PM +0800, Xufeng Zhang wrote:
> Hi All,
>
> I detected below error when booting p1021mds after enabled EDAC feature:
> EDAC MC: Ver: 2.1.0 Jul 17 2012
> Freescale(R) MPC85xx EDAC driver, (C) 2006 Montavista Software
> EDAC MC0: Giving out device to 'MPC85xx_edac' 'mpc85xx_mc_err': DEV mpc85xx_mc_e
> rr
> IRQ 45/[EDAC] MC err: IRQF_DISABLED is not guaranteed on shared IRQs
> MPC85xx_edac acquired irq 45 for MC
> MPC85xx_edac MC err registered
> EDAC DEVICE0: Giving out device to module 'MPC85xx_edac' controller 'mpc85xx_l2_
> err': DEV 'mpc85xx_l2_err' (INTERRUPT)
> mpc85xx_l2_err_probe: Unable to requiest irq 45 for MPC85xx L2 err
>
> Then kernel hang.
>
> When request irq for l2-cache, since it share the same irq with memory
> controller,
> I think the code should be:
> printk(KERN_ERR
>
>
>
>
>
> Thanks,
> Xufeng Zhang
>
>
> --- a/drivers/edac/mpc85xx_edac.c
> +++ b/drivers/edac/mpc85xx_edac.c
> @@ -577,7 +577,7 @@ static int __devinit mpc85xx_l2_err_probe(struct
> of_device *op,
> if (edac_op_state == EDAC_OPSTATE_INT) {
> pdata->irq = irq_of_parse_and_map(op->node, 0);
> res = devm_request_irq(&op->dev, pdata->irq,
> - mpc85xx_l2_isr, IRQF_DISABLED,
> + mpc85xx_l2_isr, IRQF_DISABLED | IRQF_SHARED,
> "[EDAC] L2 err", edac_dev);
> if (res < 0) {
Sorry for the delayed response... That "IRQF_DISABLED is not guaranteed"
message was removed in v2.6.35 (along with the rest of IRQF_DISABLED
support) which was almost two years old even back when your e-mail was
sent. Even back then, as far as I can tell your patch would be
introducing, not fixing, that message.
It does look like this interrupt should be shared, though.
The deprecated IRQF_DISABLED should be removed.
-Scott
^ permalink raw reply
* Re: [PATCH v2 15/45] rcu: Use get/put_online_cpus_atomic() to prevent CPU offline
From: Paul E. McKenney @ 2013-06-25 22:00 UTC (permalink / raw)
To: Srivatsa S. Bhat
Cc: peterz, fweisbec, linux-kernel, walken, mingo, linux-arch,
vincent.guittot, xiaoguangrong, wangyun, nikunj, linux-pm, rusty,
rostedt, namhyung, tglx, laijs, zhong, netdev, oleg, sbw, tj,
akpm, linuxppc-dev
In-Reply-To: <20130625202755.16593.67819.stgit@srivatsabhat.in.ibm.com>
On Wed, Jun 26, 2013 at 01:57:55AM +0530, Srivatsa S. Bhat wrote:
> Once stop_machine() is gone from the CPU offline path, we won't be able
> to depend on disabling preemption to prevent CPUs from going offline
> from under us.
>
> In RCU code, rcu_implicit_dynticks_qs() checks if a CPU is offline,
> while being protected by a spinlock. Use the get/put_online_cpus_atomic()
> APIs to prevent CPUs from going offline, while invoking from atomic context.
I am not completely sure that this is needed. Here is a (quite possibly
flawed) argument for its not being needed:
o rcu_gp_init() holds off CPU-hotplug operations during
grace-period initialization. Therefore, RCU will avoid
looking for quiescent states from CPUs that were offline
(and thus in an extended quiescent state) at the beginning
of the grace period.
o If force_qs_rnp() is looking for a quiescent state from
a given CPU, and if it senses that CPU as being offline,
then even without synchronization we know that the CPU
was offline some time during the current grace period.
After all, it was online at the beginning of the grace
period (otherwise, we would not be looking at it at all),
and our later sampling of its state must have therefore
happened after the start of the grace period. Given that
the grace period has not yet ended, it also has to happened
before the end of the grace period.
o Therefore, we should be able to sample the offline state
without synchronization.
Possible flaws in this argument: memory ordering, oddnesses in
the sampling and updates of the cpumask recording which CPUs are
online, and so on.
Thoughts?
Thanx, Paul
> Cc: Dipankar Sarma <dipankar@in.ibm.com>
> Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
> Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
> ---
>
> kernel/rcutree.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/kernel/rcutree.c b/kernel/rcutree.c
> index cf3adc6..caeed1a 100644
> --- a/kernel/rcutree.c
> +++ b/kernel/rcutree.c
> @@ -2107,6 +2107,8 @@ static void force_qs_rnp(struct rcu_state *rsp, int (*f)(struct rcu_data *))
> rcu_initiate_boost(rnp, flags); /* releases rnp->lock */
> continue;
> }
> +
> + get_online_cpus_atomic();
> cpu = rnp->grplo;
> bit = 1;
> for (; cpu <= rnp->grphi; cpu++, bit <<= 1) {
> @@ -2114,6 +2116,8 @@ static void force_qs_rnp(struct rcu_state *rsp, int (*f)(struct rcu_data *))
> f(per_cpu_ptr(rsp->rda, cpu)))
> mask |= bit;
> }
> + put_online_cpus_atomic();
> +
> if (mask != 0) {
>
> /* rcu_report_qs_rnp() releases rnp->lock. */
>
^ permalink raw reply
* Re: [v2] Enhanced support for MPC8xx/8xxx watchdog
From: Scott Wood @ 2013-06-25 23:04 UTC (permalink / raw)
To: LEROY Christophe
Cc: Wim Van Sebroeck, linuxppc-dev, linux-kernel, linux-watchdog
In-Reply-To: <201302280852.r1S8qMYu003742@localhost.localdomain>
On Thu, Feb 28, 2013 at 09:52:22AM +0100, LEROY Christophe wrote:
> This patch modifies the behaviour of the MPC8xx/8xxx watchdog. On the MPC8xx,
> at 133Mhz, the maximum timeout of the watchdog timer is 1s, which means it must
> be pinged twice a second. This is not in line with the Linux watchdog concept
> which is based on a default watchdog timeout around 60s.
> This patch introduces an intermediate layer between the CPU and the userspace.
> The kernel pings the watchdog at the required frequency at the condition that
> userspace tools refresh it regularly.
> Existing parameter 'timeout' is renamed 'hw_time'.
> The new parameter 'timeout' allows to set up the userspace timeout.
> The driver also implements the WDIOC_SETTIMEOUT ioctl.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
>
>
> diff -ur linux-3.7.9/drivers/watchdog/mpc8xxx_wdt.c linux/drivers/watchdog/mpc8xxx_wdt.c
> --- linux-3.7.9/drivers/watchdog/mpc8xxx_wdt.c 2013-02-17 19:53:32.000000000 +0100
> +++ linux/drivers/watchdog/mpc8xxx_wdt.c 2013-02-27 16:00:07.000000000 +0100
> @@ -52,10 +52,17 @@
> static struct mpc8xxx_wdt __iomem *wd_base;
> static int mpc8xxx_wdt_init_late(void);
>
> -static u16 timeout = 0xffff;
> -module_param(timeout, ushort, 0);
> +#define WD_TIMO 10 /* Default timeout = 10 seconds */
If the default Linux watchdog timeout is normally 60 seconds, why is it 10
here?
> +static uint timeout = WD_TIMO;
> +module_param(timeout, uint, 0);
> MODULE_PARM_DESC(timeout,
> - "Watchdog timeout in ticks. (0<timeout<65536, default=65535)");
> + "Watchdog SW timeout in seconds. (0 < timeout < 65536s, default = "
> + __MODULE_STRING(WD_TIMO) "s)");
> +static u16 hw_timo = 0xffff;
> +module_param(hw_timo, ushort, 0);
> +MODULE_PARM_DESC(hw_timo,
> + "Watchdog HW timeout in ticks. (0 < hw_timo < 65536, default = 65535)");
hw_timeout would be more legibile -- this is a public interface.
> static bool reset = 1;
> module_param(reset, bool, 0);
> @@ -72,10 +79,12 @@
> * to 0
> */
> static int prescale = 1;
> -static unsigned int timeout_sec;
> +static unsigned int hw_timo_sec;
>
> +static int wdt_auto = 1;
bool, and add a comment indicating what this means.
> static unsigned long wdt_is_open;
> static DEFINE_SPINLOCK(wdt_spinlock);
> +static unsigned long wdt_last_ping;
>
> static void mpc8xxx_wdt_keepalive(void)
> {
> @@ -91,9 +100,20 @@
>
> static void mpc8xxx_wdt_timer_ping(unsigned long arg)
> {
> - mpc8xxx_wdt_keepalive();
> - /* We're pinging it twice faster than needed, just to be sure. */
> - mod_timer(&wdt_timer, jiffies + HZ * timeout_sec / 2);
> + if (wdt_auto)
> + wdt_last_ping = jiffies;
> +
> + if (jiffies - wdt_last_ping <= timeout * HZ) {
So timeout cannot be more than UINT_MAX / HZ... Might want to check for
that, just in case.
What happens if there's a race? If another CPU updates wdt_last_ping in
parallel, then you could see wdt_last_ping greater than the value you
read for jiffies. Since this is an unsigned comparison, it will fail to
call keepalive. You might get saved by pinging it twice as often as
necessary, but you shouldn't rely on that.
> + mpc8xxx_wdt_keepalive();
> + /* We're pinging it twice faster than needed, to be sure. */
> + mod_timer(&wdt_timer, jiffies + HZ * hw_timo_sec / 2);
> + }
> +}
> +
> +static void mpc8xxx_wdt_sw_keepalive(void)
> +{
> + wdt_last_ping = jiffies;
> + mpc8xxx_wdt_timer_ping(0);
> }
This isn't new with this patch, but it looks like
mpc8xxx_wdt_keepalive() can be called either from timer context, or with
interrupts enabled... yet it uses a bare spin_lock() rather than an
irq-safe version. This should be fixed.
-Scott
^ permalink raw reply
* Re: powerpc/85xx: Move ePAPR paravirt initialization earlier
From: Scott Wood @ 2013-06-25 23:14 UTC (permalink / raw)
To: Laurentiu TUDOR; +Cc: linuxppc-dev
In-Reply-To: <1362498756-395-1-git-send-email-Laurentiu.Tudor@freescale.com>
On Tue, Mar 05, 2013 at 05:52:36PM +0200, Laurentiu TUDOR wrote:
> From: Tudor Laurentiu <laurentiu.tudor@freescale.com>
>
> The ePAPR para-virtualization needs to happen very early
> otherwise the bytechannel based console will silently
> drop some of the early boot messages.
>
> Before this patch, this is how the kernel log started:
> -----------------------------------------------------
> > Brought up 2 CPUs
> > devtmpfs: initialized
> > NET: Registered protocol family 16
> [...]
> -----------------------------------------------------
>
> After the patch the early messages show up:
> -----------------------------------------------------
> > Using P5020 DS machine description
> > MMU: Supported page sizes
> > 4 KB as direct
> > 4096 KB as direct
> [...]
> -----------------------------------------------------
>
> At console init, the kernel tried to flush the log buffer.
> Since the paravirt was not yet initialized the console write
> function failed silently, thus losing the buffered messages.
[snip]
> diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
> index 6da881b..ce092ac 100644
> --- a/arch/powerpc/kernel/setup_64.c
> +++ b/arch/powerpc/kernel/setup_64.c
> @@ -66,6 +66,7 @@
> #include <asm/code-patching.h>
> #include <asm/kvm_ppc.h>
> #include <asm/hugetlb.h>
> +#include <asm/epapr_hcalls.h>
>
> #include "setup.h"
>
> @@ -599,6 +600,8 @@ void __init setup_arch(char **cmdline_p)
> /* Initialize the MMU context management stuff */
> mmu_context_init();
>
> + epapr_paravirt_init();
> +
> kvm_linear_init();
>
> /* Interrupt code needs to be 64K-aligned */
Is this early enough? There's udbg activity before this. Maybe it
should even go before udbg_early_init... This would require converting
the code to use the early device tree functions.
-Scott
^ permalink raw reply
* Re: BUG: no PCI/PCIe devices found in 85xx architecture
From: Scott Wood @ 2013-06-25 23:46 UTC (permalink / raw)
To: Stefani Seibold; +Cc: linuxppc-dev
In-Reply-To: <1372185614.4726.12.camel@wall-e>
On 06/25/2013 01:40:14 PM, Stefani Seibold wrote:
> Hi,
>=20
> there is a bug in kernel 3.9 which the new fsl_pci platform driver. =20
> The
> pcibios_init in pci_32.c will be called before the platform driver =20
> probe
> will be invoked.
>=20
> The call order for a p2020 board with linux 3.9 is currently:
>=20
> fsl_pci_init
> pcibios_init
> fsl_pci_probe
> fsl_pci_probe
> fsl_pci_probe
>=20
> Therefore the PCI/PCIe bridge will be added after the PCI/PCIe busses
> was scanned for devices. So no PCI/PCIe devices are available.
>=20
> Everything works fine by reverting the fsl_pci.[ch] to the version in
> linux 3.4, because the PCI/PCIe bridges will be added in
> the ..._setup_arch() function, before the pcibios_init function is
> called.
>=20
> Any solution for this issue?
I can't reproduce this on p3041 -- pcibios_init gets called after =20
fsl_pci_probe, and its PCIe e1000 gets detected and used.
fsl_pci_probe should be called when of_platform_bus_probe is called, =20
which is in a machine_arch_initcall. pcibios_init is a =20
subsys_initcall, which should happen later.
Which p2020 board are you using? Could you check when it is calling =20
of_platform_bus_probe?
-Scott=
^ permalink raw reply
* Re: [PATCH 1/6] powerpc/eeh: Don't collect PCI-CFG data on PHB
From: Gavin Shan @ 2013-06-25 23:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Gavin Shan
In-Reply-To: <1372161315.3944.201.camel@pasglop>
On Tue, Jun 25, 2013 at 09:55:15PM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2013-06-25 at 18:00 +0800, Gavin Shan wrote:
>> + /*
>> + * When the PHB is fenced or dead, it's pointless to collect
>> + * the data from PCI config space because it should return
>> + * 0xFF's. For ER, we still retrieve the data from the PCI
>> + * config space.
>> + */
>> + if (eeh_probe_mode_dev() &&
>> + (pe->type & EEH_PE_PHB) &&
>> + (pe->state & (EEH_PE_ISOLATED | EEH_PE_PHB_DEAD)))
>> + valid_cfg_log = false;
>> +
>
>I'm still unsure about that one. EEH_PE_ISOLATED could be the result
>of a normal ER of PE#0 (which can happen for various reasons other
>than a fence) in which case the config space is available and
>interesting.
>
It's something like the followings. For ER on PE#0, we will have
PE with type of EEH_PE_BUS marked as isolated, instead of the
one with EEH_PE_PHB.
[ EEH_PE_PHB] <---> [ EEH_PE_PHB] <---> [ EEH_PE_PHB]
|
[ EEH_PE_BUS ] PE#0
|
-------------------------
| |
[ EEH_PE_BUS ] PE#1 [ EEH_PE_BUS] PE#2
>I would either not bother and collect the FF's, or make this specific
>to fence and only fence.
>
I'd like to keep it specific to fenced PHB and it's already be that :-)
Thanks,
Gavin
^ permalink raw reply
* Re: [PATCH 1/6] powerpc/eeh: Don't collect PCI-CFG data on PHB
From: Gavin Shan @ 2013-06-25 23:50 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Gavin Shan
In-Reply-To: <1372161366.3944.202.camel@pasglop>
On Tue, Jun 25, 2013 at 09:56:06PM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2013-06-25 at 18:00 +0800, Gavin Shan wrote:
>> + pci_regs_buf[0] = 0;
>> + eeh_pe_for_each_dev(pe, edev) {
>> + loglen += eeh_gather_pci_data(edev, pci_regs_buf,
>> + EEH_PCI_REGS_LOG_LEN);
>> + }
>> + }
>
>Unless I'm mistaken, this is buggy and will overwrite the content of
>pci_regs_buf for every device (they will all write over the same
>portion of the log).
>
No, you're right. I'm going to fix it in next revision :-)
Thanks,
Gavin
^ permalink raw reply
* Re: [PATCH 2/6] powerpc/eeh: Check PCIe link after reset
From: Gavin Shan @ 2013-06-25 23:54 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Gavin Shan
In-Reply-To: <1372161520.3944.204.camel@pasglop>
On Tue, Jun 25, 2013 at 09:58:40PM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2013-06-25 at 18:00 +0800, Gavin Shan wrote:
>> After reset (e.g. complete reset) in order to bring the fenced PHB
>> back, the PCIe link might not be ready yet. The patch intends to
>> make sure the PCIe link is ready before accessing its subordinate
>> PCI devices. The patch also fixes that wrong values restored to
>> PCI_COMMAND register for PCI bridges.
>
>This should also help if we end up doing a full reset for ER cases
>right ?
>
>IE, in a setup with PHB -> device (no switch), if the device driver
>requests a fundamental reset, we should do a PERST at the PHB level (are
>we ?) and thus restore things in a similar way.
>
Yes, you're right. We will do PERST if the device driver requests
fundamental reset on the root port. Otherwise, no matter which
type of reset (fundamental or hot) the device driver requests,
the upstream bridge got hot reset. Anyway, the piece of code
(checking PCIe link) is possiblly applied to ER case.
Thanks,
Gavin
>> Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
>> ---
>> arch/powerpc/kernel/eeh_pe.c | 157 ++++++++++++++++++++++++++++++++++++++----
>> 1 files changed, 144 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
>> index 55943fc..016588a 100644
>> --- a/arch/powerpc/kernel/eeh_pe.c
>> +++ b/arch/powerpc/kernel/eeh_pe.c
>> @@ -22,6 +22,7 @@
>> * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
>> */
>>
>> +#include <linux/delay.h>
>> #include <linux/export.h>
>> #include <linux/gfp.h>
>> #include <linux/init.h>
>> @@ -567,30 +568,132 @@ void eeh_pe_state_clear(struct eeh_pe *pe, int state)
>> eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
>> }
>>
>> -/**
>> - * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
>> - * @data: EEH device
>> - * @flag: Unused
>> +/*
>> + * Some PCI bridges (e.g. PLX bridges) have primary/secondary
>> + * buses assigned explicitly by firmware, and we probably have
>> + * lost that after reset. So we have to delay the check until
>> + * the PCI-CFG registers have been restored for the parent
>> + * bridge.
>> *
>> - * Loads the PCI configuration space base address registers,
>> - * the expansion ROM base address, the latency timer, and etc.
>> - * from the saved values in the device node.
>> + * Don't use normal PCI-CFG accessors, which probably has been
>> + * blocked on normal path during the stage. So we need utilize
>> + * eeh operations, which is always permitted.
>> */
>> -static void *eeh_restore_one_device_bars(void *data, void *flag)
>> +static void eeh_bridge_check_link(struct pci_dev *pdev,
>> + struct device_node *dn)
>> +{
>> + int cap;
>> + uint32_t val;
>> + int timeout = 0;
>> +
>> + /*
>> + * We only check root port and downstream ports of
>> + * PCIe switches
>> + */
>> + if (!pci_is_pcie(pdev) ||
>> + (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
>> + pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
>> + return;
>> +
>> + pr_debug("%s: Check PCIe link for %s ...\n",
>> + __func__, pci_name(pdev));
>> +
>> + /* Check slot status */
>> + cap = pdev->pcie_cap;
>> + eeh_ops->read_config(dn, cap + PCI_EXP_SLTSTA, 2, &val);
>> + if (!(val & PCI_EXP_SLTSTA_PDS)) {
>> + pr_debug(" No card in the slot (0x%04x) !\n", val);
>> + return;
>> + }
>> +
>> + /* Check power status if we have the capability */
>> + eeh_ops->read_config(dn, cap + PCI_EXP_SLTCAP, 2, &val);
>> + if (val & PCI_EXP_SLTCAP_PCP) {
>> + eeh_ops->read_config(dn, cap + PCI_EXP_SLTCTL, 2, &val);
>> + if (val & PCI_EXP_SLTCTL_PCC) {
>> + pr_debug(" In power-off state, power it on ...\n");
>> + val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
>> + val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
>> + eeh_ops->write_config(dn, cap + PCI_EXP_SLTCTL, 2, val);
>> + msleep(2 * 1000);
>> + }
>> + }
>> +
>> + /* Enable link */
>> + eeh_ops->read_config(dn, cap + PCI_EXP_LNKCTL, 2, &val);
>> + val &= ~PCI_EXP_LNKCTL_LD;
>> + eeh_ops->write_config(dn, cap + PCI_EXP_LNKCTL, 2, val);
>> +
>> + /* Check link */
>> + eeh_ops->read_config(dn, cap + PCI_EXP_LNKCAP, 4, &val);
>> + if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
>> + pr_debug(" No link reporting capability (0x%08x) \n", val);
>> + msleep(1000);
>> + return;
>> + }
>> +
>> + /* Wait the link is up until timeout (5s) */
>> + timeout = 0;
>> + while (timeout < 5000) {
>> + msleep(20);
>> + timeout += 20;
>> +
>> + eeh_ops->read_config(dn, cap + PCI_EXP_LNKSTA, 2, &val);
>> + if (val & PCI_EXP_LNKSTA_DLLLA)
>> + break;
>> + }
>> +
>> + if (val & PCI_EXP_LNKSTA_DLLLA)
>> + pr_debug(" Link up (%s)\n",
>> + (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
>> + else
>> + pr_debug(" Link not ready (0x%04x)\n", val);
>> +}
>> +
>> +#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
>> +#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
>> +
>> +static void eeh_restore_bridge_bars(struct pci_dev *pdev,
>> + struct eeh_dev *edev,
>> + struct device_node *dn)
>> +{
>> + int i;
>> +
>> + /*
>> + * Device BARs: 0x10 - 0x18
>> + * Bus numbers and windows: 0x18 - 0x30
>> + */
>> + for (i = 4; i < 13; i++)
>> + eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
>> + /* Rom: 0x38 */
>> + eeh_ops->write_config(dn, 14*4, 4, edev->config_space[14]);
>> +
>> + /* Cache line & Latency timer: 0xC 0xD */
>> + eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
>> + SAVED_BYTE(PCI_CACHE_LINE_SIZE));
>> + eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
>> + SAVED_BYTE(PCI_LATENCY_TIMER));
>> + /* Max latency, min grant, interrupt ping and line: 0x3C */
>> + eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
>> +
>> + /* PCI Command: 0x4 */
>> + eeh_ops->write_config(dn, PCI_COMMAND, 4, edev->config_space[1]);
>> +
>> + /* Check the PCIe link is ready */
>> + eeh_bridge_check_link(pdev, dn);
>> +}
>> +
>> +static void eeh_restore_device_bars(struct eeh_dev *edev,
>> + struct device_node *dn)
>> {
>> int i;
>> u32 cmd;
>> - struct eeh_dev *edev = (struct eeh_dev *)data;
>> - struct device_node *dn = eeh_dev_to_of_node(edev);
>>
>> for (i = 4; i < 10; i++)
>> eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
>> /* 12 == Expansion ROM Address */
>> eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]);
>>
>> -#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
>> -#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
>> -
>> eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
>> SAVED_BYTE(PCI_CACHE_LINE_SIZE));
>> eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
>> @@ -613,6 +716,34 @@ static void *eeh_restore_one_device_bars(void *data, void *flag)
>> else
>> cmd &= ~PCI_COMMAND_SERR;
>> eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd);
>> +}
>> +
>> +/**
>> + * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
>> + * @data: EEH device
>> + * @flag: Unused
>> + *
>> + * Loads the PCI configuration space base address registers,
>> + * the expansion ROM base address, the latency timer, and etc.
>> + * from the saved values in the device node.
>> + */
>> +static void *eeh_restore_one_device_bars(void *data, void *flag)
>> +{
>> + struct pci_dev *pdev = NULL;
>> + struct eeh_dev *edev = (struct eeh_dev *)data;
>> + struct device_node *dn = eeh_dev_to_of_node(edev);
>> +
>> + /* Trace the PCI bridge */
>> + if (eeh_probe_mode_dev()) {
>> + pdev = eeh_dev_to_pci_dev(edev);
>> + if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
>> + pdev = NULL;
>> + }
>> +
>> + if (pdev)
>> + eeh_restore_bridge_bars(pdev, edev, dn);
>> + else
>> + eeh_restore_device_bars(edev, dn);
>>
>> return NULL;
>> }
>
>
^ permalink raw reply
* Re: [PATCH 1/6] powerpc/eeh: Don't collect PCI-CFG data on PHB
From: Benjamin Herrenschmidt @ 2013-06-25 23:57 UTC (permalink / raw)
To: Gavin Shan; +Cc: linuxppc-dev
In-Reply-To: <20130625234917.GA4556@shangw.(null)>
On Wed, 2013-06-26 at 07:49 +0800, Gavin Shan wrote:
> It's something like the followings. For ER on PE#0, we will have
> PE with type of EEH_PE_BUS marked as isolated, instead of the
> one with EEH_PE_PHB.
>
>
> [ EEH_PE_PHB] <---> [ EEH_PE_PHB] <---> [ EEH_PE_PHB]
> |
> [ EEH_PE_BUS ] PE#0
> |
So we actually have two PEs here ? One real (PE#0) and one imaginary
(PHB PE) with no PE# associated ?
> -------------------------
> | |
> [ EEH_PE_BUS ] PE#1 [ EEH_PE_BUS] PE#2
>
> >I would either not bother and collect the FF's, or make this specific
> >to fence and only fence.
> >
>
> I'd like to keep it specific to fenced PHB and it's already be
> that :-)
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 1/6] powerpc/eeh: Don't collect PCI-CFG data on PHB
From: Gavin Shan @ 2013-06-26 0:12 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Gavin Shan
In-Reply-To: <1372204646.3944.223.camel@pasglop>
On Wed, Jun 26, 2013 at 09:57:26AM +1000, Benjamin Herrenschmidt wrote:
>On Wed, 2013-06-26 at 07:49 +0800, Gavin Shan wrote:
>> It's something like the followings. For ER on PE#0, we will have
>> PE with type of EEH_PE_BUS marked as isolated, instead of the
>> one with EEH_PE_PHB.
>>
>>
>> [ EEH_PE_PHB] <---> [ EEH_PE_PHB] <---> [ EEH_PE_PHB]
>> |
>> [ EEH_PE_BUS ] PE#0
>> |
>
>So we actually have two PEs here ? One real (PE#0) and one imaginary
>(PHB PE) with no PE# associated ?
>
Yes, The (PHB PE) is actually a container to all PEs under the
PHB ;-)
>> -------------------------
>> | |
>> [ EEH_PE_BUS ] PE#1 [ EEH_PE_BUS] PE#2
>>
>> >I would either not bother and collect the FF's, or make this specific
>> >to fence and only fence.
>> >
>>
>> I'd like to keep it specific to fenced PHB and it's already be
>> that :-)
Thanks,
Gavin
^ permalink raw reply
* [PATCH v3 00/6] Follow-up fixes for EEH on PowerNV
From: Gavin Shan @ 2013-06-26 1:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
The series of patches are follow-up in order to make EEH workable for PowerNV
platform on Juno-IOC-L machine. Couple of issues have been fixed with help of
Ben:
- Check PCIe link after PHB complete reset
- Restore config space for bridges
- The EEH address cache wasn't built successfully
- Misc cleanup on output messages
- Misc cleanup on EEH flags maintained by "struct pnv_phb"
- Misc cleanup on properties of functions to avoid build warnings
The series of patches have been verified on Juno-IOC-L machine:
Trigger frozen PE:
echo 0x0000000002000000 > /sys/kernel/debug/powerpc/PCI0000/err_injct
sleep 1
echo 0x0 > /sys/kernel/debug/powerpc/PCI0000/err_injct
Trigger fenced PHB:
echo 0x8000000000000000 > /sys/kernel/debug/powerpc/PCI0000/err_injct
Changelog:
==========
v2 -> v3:
* Fix overwritten buffer while collecting data
from PCI config space.
v1 -> v2:
* Remove the mechanism to block PCI-CFG and MMIO.
* Add one patch to do cleanup on output messages.
* Add one patch to avoid build warnings.
* Split functions to restore BARs for PCI devices and bridges separately.
---
arch/powerpc/include/asm/eeh.h | 4 +-
arch/powerpc/kernel/eeh.c | 43 ++++++--
arch/powerpc/kernel/eeh_cache.c | 4 +-
arch/powerpc/kernel/eeh_pe.c | 157 ++++++++++++++++++++++++++---
arch/powerpc/platforms/powernv/eeh-ioda.c | 33 ++++---
arch/powerpc/platforms/powernv/pci-ioda.c | 1 +
arch/powerpc/platforms/powernv/pci.c | 4 +-
arch/powerpc/platforms/powernv/pci.h | 7 +-
8 files changed, 207 insertions(+), 46 deletions(-)
Thanks,
Gavin
^ permalink raw reply
* [PATCH 3/6] powerpc/powernv: Replace variables with flags
From: Gavin Shan @ 2013-06-26 1:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372210688-12214-1-git-send-email-shangw@linux.vnet.ibm.com>
We have 2 fields in "struct pnv_phb" to trace the states. The patch
replace the fields with one and introduces flags for that. The patch
doesn't impact the logic.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/eeh-ioda.c | 8 ++++----
arch/powerpc/platforms/powernv/pci.c | 4 ++--
arch/powerpc/platforms/powernv/pci.h | 7 +++++--
3 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
index 84f3036..85025d7 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -132,7 +132,7 @@ static int ioda_eeh_post_init(struct pci_controller *hose)
&ioda_eeh_dbgfs_ops);
#endif
- phb->eeh_enabled = 1;
+ phb->eeh_state |= PNV_EEH_STATE_ENABLED;
}
return 0;
@@ -815,7 +815,7 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
* removed, we needn't take care of it any more.
*/
phb = hose->private_data;
- if (phb->removed)
+ if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
continue;
rc = opal_pci_next_error(phb->opal_id,
@@ -850,7 +850,7 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
list_for_each_entry_safe(hose, tmp,
&hose_list, list_node) {
phb = hose->private_data;
- phb->removed = 1;
+ phb->eeh_state |= PNV_EEH_STATE_REMOVED;
}
WARN(1, "EEH: dead IOC detected\n");
@@ -867,7 +867,7 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
WARN(1, "EEH: dead PHB#%x detected\n",
hose->global_number);
- phb->removed = 1;
+ phb->eeh_state |= PNV_EEH_STATE_REMOVED;
ret = 3;
goto out;
} else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 6d9a506..1f31826 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -308,7 +308,7 @@ static int pnv_pci_read_config(struct pci_bus *bus,
if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED))
return PCIBIOS_SUCCESSFUL;
- if (phb->eeh_enabled) {
+ if (phb->eeh_state & PNV_EEH_STATE_ENABLED) {
if (*val == EEH_IO_ERROR_VALUE(size)) {
busdn = pci_bus_to_OF_node(bus);
for (dn = busdn->child; dn; dn = dn->sibling) {
@@ -358,7 +358,7 @@ static int pnv_pci_write_config(struct pci_bus *bus,
/* Check if the PHB got frozen due to an error (no response) */
#ifdef CONFIG_EEH
- if (!phb->eeh_enabled)
+ if (!(phb->eeh_state & PNV_EEH_STATE_ENABLED))
pnv_pci_config_check_eeh(phb, bus, bdfn);
#else
pnv_pci_config_check_eeh(phb, bus, bdfn);
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 43906e3..40bdf02 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -78,6 +78,10 @@ struct pnv_eeh_ops {
int (*configure_bridge)(struct eeh_pe *pe);
int (*next_error)(struct eeh_pe **pe);
};
+
+#define PNV_EEH_STATE_ENABLED (1 << 0) /* EEH enabled */
+#define PNV_EEH_STATE_REMOVED (1 << 1) /* PHB removed */
+
#endif /* CONFIG_EEH */
struct pnv_phb {
@@ -92,8 +96,7 @@ struct pnv_phb {
#ifdef CONFIG_EEH
struct pnv_eeh_ops *eeh_ops;
- int eeh_enabled;
- int removed;
+ int eeh_state;
#endif
#ifdef CONFIG_DEBUG_FS
--
1.7.5.4
^ permalink raw reply related
* [PATCH 5/6] powerpc/eeh: Refactor the output message
From: Gavin Shan @ 2013-06-26 1:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372210688-12214-1-git-send-email-shangw@linux.vnet.ibm.com>
We needn't the the whole backtrace other than one-line message in
the error reporting interrupt handler. For errors triggered by
access PCI config space or MMIO, we replace "WARN(1, ...)" with
pr_err() and dump_stack().
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/kernel/eeh.c | 9 +++++++--
arch/powerpc/platforms/powernv/eeh-ioda.c | 25 ++++++++++++++++---------
2 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 2dd0bd1..f7f2775 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -324,7 +324,9 @@ static int eeh_phb_check_failure(struct eeh_pe *pe)
eeh_serialize_unlock(flags);
eeh_send_failure_event(phb_pe);
- WARN(1, "EEH: PHB failure detected\n");
+ pr_err("EEH: PHB#%x failure detected\n",
+ phb_pe->phb->global_number);
+ dump_stack();
return 1;
out:
@@ -453,7 +455,10 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
* a stack trace will help the device-driver authors figure
* out what happened. So print that out.
*/
- WARN(1, "EEH: failure detected\n");
+ pr_err("EEH: Frozen PE#%x detected on PHB#%x\n",
+ pe->addr, pe->phb->global_number);
+ dump_stack();
+
return 1;
dn_unlock:
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
index 85025d7..0cd1c4a 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -853,11 +853,14 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
phb->eeh_state |= PNV_EEH_STATE_REMOVED;
}
- WARN(1, "EEH: dead IOC detected\n");
+ pr_err("EEH: dead IOC detected\n");
ret = 4;
goto out;
- } else if (severity == OPAL_EEH_SEV_INF)
+ } else if (severity == OPAL_EEH_SEV_INF) {
+ pr_info("EEH: IOC informative error "
+ "detected\n");
ioda_eeh_hub_diag(hose);
+ }
break;
case OPAL_EEH_PHB_ERROR:
@@ -865,8 +868,8 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
if (ioda_eeh_get_phb_pe(hose, pe))
break;
- WARN(1, "EEH: dead PHB#%x detected\n",
- hose->global_number);
+ pr_err("EEH: dead PHB#%x detected\n",
+ hose->global_number);
phb->eeh_state |= PNV_EEH_STATE_REMOVED;
ret = 3;
goto out;
@@ -874,20 +877,24 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
if (ioda_eeh_get_phb_pe(hose, pe))
break;
- WARN(1, "EEH: fenced PHB#%x detected\n",
- hose->global_number);
+ pr_err("EEH: fenced PHB#%x detected\n",
+ hose->global_number);
ret = 2;
goto out;
- } else if (severity == OPAL_EEH_SEV_INF)
+ } else if (severity == OPAL_EEH_SEV_INF) {
+ pr_info("EEH: PHB#%x informative error "
+ "detected\n",
+ hose->global_number);
ioda_eeh_phb_diag(hose);
+ }
break;
case OPAL_EEH_PE_ERROR:
if (ioda_eeh_get_pe(hose, frozen_pe_no, pe))
break;
- WARN(1, "EEH: Frozen PE#%x on PHB#%x detected\n",
- (*pe)->addr, (*pe)->phb->global_number);
+ pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
+ (*pe)->addr, (*pe)->phb->global_number);
ret = 1;
goto out;
}
--
1.7.5.4
^ permalink raw reply related
* [PATCH 1/6] powerpc/eeh: Don't collect PCI-CFG data on PHB
From: Gavin Shan @ 2013-06-26 1:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372210688-12214-1-git-send-email-shangw@linux.vnet.ibm.com>
When the PHB is fenced or dead, it's pointless to collect the data
from PCI config space of subordinate PCI devices since it should
return 0xFF's. The patch also fixes overwritten buffer while getting
PCI config data.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/kernel/eeh.c | 34 ++++++++++++++++++++++++----------
1 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 951a632..2dd0bd1 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -232,16 +232,30 @@ void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
{
size_t loglen = 0;
struct eeh_dev *edev;
+ bool valid_cfg_log = true;
- eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
- eeh_ops->configure_bridge(pe);
- eeh_pe_restore_bars(pe);
-
- pci_regs_buf[0] = 0;
- eeh_pe_for_each_dev(pe, edev) {
- loglen += eeh_gather_pci_data(edev, pci_regs_buf,
- EEH_PCI_REGS_LOG_LEN);
- }
+ /*
+ * When the PHB is fenced or dead, it's pointless to collect
+ * the data from PCI config space because it should return
+ * 0xFF's. For ER, we still retrieve the data from the PCI
+ * config space.
+ */
+ if (eeh_probe_mode_dev() &&
+ (pe->type & EEH_PE_PHB) &&
+ (pe->state & (EEH_PE_ISOLATED | EEH_PE_PHB_DEAD)))
+ valid_cfg_log = false;
+
+ if (valid_cfg_log) {
+ eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
+ eeh_ops->configure_bridge(pe);
+ eeh_pe_restore_bars(pe);
+
+ pci_regs_buf[0] = 0;
+ eeh_pe_for_each_dev(pe, edev) {
+ loglen += eeh_gather_pci_data(edev, pci_regs_buf + loglen,
+ EEH_PCI_REGS_LOG_LEN - loglen);
+ }
+ }
eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
}
--
1.7.5.4
^ permalink raw reply related
* [PATCH 2/6] powerpc/eeh: Check PCIe link after reset
From: Gavin Shan @ 2013-06-26 1:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372210688-12214-1-git-send-email-shangw@linux.vnet.ibm.com>
After reset (e.g. complete reset) in order to bring the fenced PHB
back, the PCIe link might not be ready yet. The patch intends to
make sure the PCIe link is ready before accessing its subordinate
PCI devices. The patch also fixes that wrong values restored to
PCI_COMMAND register for PCI bridges.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/kernel/eeh_pe.c | 157 ++++++++++++++++++++++++++++++++++++++----
1 files changed, 144 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index 55943fc..016588a 100644
--- a/arch/powerpc/kernel/eeh_pe.c
+++ b/arch/powerpc/kernel/eeh_pe.c
@@ -22,6 +22,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#include <linux/delay.h>
#include <linux/export.h>
#include <linux/gfp.h>
#include <linux/init.h>
@@ -567,30 +568,132 @@ void eeh_pe_state_clear(struct eeh_pe *pe, int state)
eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
}
-/**
- * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
- * @data: EEH device
- * @flag: Unused
+/*
+ * Some PCI bridges (e.g. PLX bridges) have primary/secondary
+ * buses assigned explicitly by firmware, and we probably have
+ * lost that after reset. So we have to delay the check until
+ * the PCI-CFG registers have been restored for the parent
+ * bridge.
*
- * Loads the PCI configuration space base address registers,
- * the expansion ROM base address, the latency timer, and etc.
- * from the saved values in the device node.
+ * Don't use normal PCI-CFG accessors, which probably has been
+ * blocked on normal path during the stage. So we need utilize
+ * eeh operations, which is always permitted.
*/
-static void *eeh_restore_one_device_bars(void *data, void *flag)
+static void eeh_bridge_check_link(struct pci_dev *pdev,
+ struct device_node *dn)
+{
+ int cap;
+ uint32_t val;
+ int timeout = 0;
+
+ /*
+ * We only check root port and downstream ports of
+ * PCIe switches
+ */
+ if (!pci_is_pcie(pdev) ||
+ (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
+ pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
+ return;
+
+ pr_debug("%s: Check PCIe link for %s ...\n",
+ __func__, pci_name(pdev));
+
+ /* Check slot status */
+ cap = pdev->pcie_cap;
+ eeh_ops->read_config(dn, cap + PCI_EXP_SLTSTA, 2, &val);
+ if (!(val & PCI_EXP_SLTSTA_PDS)) {
+ pr_debug(" No card in the slot (0x%04x) !\n", val);
+ return;
+ }
+
+ /* Check power status if we have the capability */
+ eeh_ops->read_config(dn, cap + PCI_EXP_SLTCAP, 2, &val);
+ if (val & PCI_EXP_SLTCAP_PCP) {
+ eeh_ops->read_config(dn, cap + PCI_EXP_SLTCTL, 2, &val);
+ if (val & PCI_EXP_SLTCTL_PCC) {
+ pr_debug(" In power-off state, power it on ...\n");
+ val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
+ val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
+ eeh_ops->write_config(dn, cap + PCI_EXP_SLTCTL, 2, val);
+ msleep(2 * 1000);
+ }
+ }
+
+ /* Enable link */
+ eeh_ops->read_config(dn, cap + PCI_EXP_LNKCTL, 2, &val);
+ val &= ~PCI_EXP_LNKCTL_LD;
+ eeh_ops->write_config(dn, cap + PCI_EXP_LNKCTL, 2, val);
+
+ /* Check link */
+ eeh_ops->read_config(dn, cap + PCI_EXP_LNKCAP, 4, &val);
+ if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
+ pr_debug(" No link reporting capability (0x%08x) \n", val);
+ msleep(1000);
+ return;
+ }
+
+ /* Wait the link is up until timeout (5s) */
+ timeout = 0;
+ while (timeout < 5000) {
+ msleep(20);
+ timeout += 20;
+
+ eeh_ops->read_config(dn, cap + PCI_EXP_LNKSTA, 2, &val);
+ if (val & PCI_EXP_LNKSTA_DLLLA)
+ break;
+ }
+
+ if (val & PCI_EXP_LNKSTA_DLLLA)
+ pr_debug(" Link up (%s)\n",
+ (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
+ else
+ pr_debug(" Link not ready (0x%04x)\n", val);
+}
+
+#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
+#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
+
+static void eeh_restore_bridge_bars(struct pci_dev *pdev,
+ struct eeh_dev *edev,
+ struct device_node *dn)
+{
+ int i;
+
+ /*
+ * Device BARs: 0x10 - 0x18
+ * Bus numbers and windows: 0x18 - 0x30
+ */
+ for (i = 4; i < 13; i++)
+ eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
+ /* Rom: 0x38 */
+ eeh_ops->write_config(dn, 14*4, 4, edev->config_space[14]);
+
+ /* Cache line & Latency timer: 0xC 0xD */
+ eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
+ SAVED_BYTE(PCI_CACHE_LINE_SIZE));
+ eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
+ SAVED_BYTE(PCI_LATENCY_TIMER));
+ /* Max latency, min grant, interrupt ping and line: 0x3C */
+ eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
+
+ /* PCI Command: 0x4 */
+ eeh_ops->write_config(dn, PCI_COMMAND, 4, edev->config_space[1]);
+
+ /* Check the PCIe link is ready */
+ eeh_bridge_check_link(pdev, dn);
+}
+
+static void eeh_restore_device_bars(struct eeh_dev *edev,
+ struct device_node *dn)
{
int i;
u32 cmd;
- struct eeh_dev *edev = (struct eeh_dev *)data;
- struct device_node *dn = eeh_dev_to_of_node(edev);
for (i = 4; i < 10; i++)
eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
/* 12 == Expansion ROM Address */
eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]);
-#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
-#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
-
eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
SAVED_BYTE(PCI_CACHE_LINE_SIZE));
eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
@@ -613,6 +716,34 @@ static void *eeh_restore_one_device_bars(void *data, void *flag)
else
cmd &= ~PCI_COMMAND_SERR;
eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd);
+}
+
+/**
+ * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
+ * @data: EEH device
+ * @flag: Unused
+ *
+ * Loads the PCI configuration space base address registers,
+ * the expansion ROM base address, the latency timer, and etc.
+ * from the saved values in the device node.
+ */
+static void *eeh_restore_one_device_bars(void *data, void *flag)
+{
+ struct pci_dev *pdev = NULL;
+ struct eeh_dev *edev = (struct eeh_dev *)data;
+ struct device_node *dn = eeh_dev_to_of_node(edev);
+
+ /* Trace the PCI bridge */
+ if (eeh_probe_mode_dev()) {
+ pdev = eeh_dev_to_pci_dev(edev);
+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
+ pdev = NULL;
+ }
+
+ if (pdev)
+ eeh_restore_bridge_bars(pdev, edev, dn);
+ else
+ eeh_restore_device_bars(edev, dn);
return NULL;
}
--
1.7.5.4
^ permalink raw reply related
* [PATCH 6/6] powerpc/eeh: Avoid build warnings
From: Gavin Shan @ 2013-06-26 1:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372210688-12214-1-git-send-email-shangw@linux.vnet.ibm.com>
The patch is for avoiding following build warnings:
The function .pnv_pci_ioda_fixup() references
the function __init .eeh_init().
This is often because .pnv_pci_ioda_fixup lacks a __init
The function .pnv_pci_ioda_fixup() references
the function __init .eeh_addr_cache_build().
This is often because .pnv_pci_ioda_fixup lacks a __init
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/eeh.h | 4 ++--
arch/powerpc/kernel/eeh.c | 2 +-
arch/powerpc/kernel/eeh_cache.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index dd65e31..09a8743 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -202,13 +202,13 @@ struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
void *eeh_dev_init(struct device_node *dn, void *data);
void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
-int __init eeh_init(void);
+int eeh_init(void);
int __init eeh_ops_register(struct eeh_ops *ops);
int __exit eeh_ops_unregister(const char *name);
unsigned long eeh_check_failure(const volatile void __iomem *token,
unsigned long val);
int eeh_dev_check_failure(struct eeh_dev *edev);
-void __init eeh_addr_cache_build(void);
+void eeh_addr_cache_build(void);
void eeh_add_device_tree_early(struct device_node *);
void eeh_add_device_tree_late(struct pci_bus *);
void eeh_add_sysfs_files(struct pci_bus *);
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index f7f2775..14475f6 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -751,7 +751,7 @@ int __exit eeh_ops_unregister(const char *name)
* Even if force-off is set, the EEH hardware is still enabled, so that
* newer systems can boot.
*/
-int __init eeh_init(void)
+int eeh_init(void)
{
struct pci_controller *hose, *tmp;
struct device_node *phb;
diff --git a/arch/powerpc/kernel/eeh_cache.c b/arch/powerpc/kernel/eeh_cache.c
index 858ebea..ea9a94c 100644
--- a/arch/powerpc/kernel/eeh_cache.c
+++ b/arch/powerpc/kernel/eeh_cache.c
@@ -285,7 +285,7 @@ void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
* Must be run late in boot process, after the pci controllers
* have been scanned for devices (after all device resources are known).
*/
-void __init eeh_addr_cache_build(void)
+void eeh_addr_cache_build(void)
{
struct device_node *dn;
struct eeh_dev *edev;
--
1.7.5.4
^ permalink raw reply related
* [PATCH 4/6] powerpc/eeh: Fix address catch for PowerNV
From: Gavin Shan @ 2013-06-26 1:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372210688-12214-1-git-send-email-shangw@linux.vnet.ibm.com>
On the PowerNV platform, the EEH address cache isn't built correctly
because we skipped the EEH devices without binding PE. The patch
fixes that.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/kernel/eeh_cache.c | 2 +-
arch/powerpc/platforms/powernv/pci-ioda.c | 1 +
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/eeh_cache.c b/arch/powerpc/kernel/eeh_cache.c
index 1d5d9a6..858ebea 100644
--- a/arch/powerpc/kernel/eeh_cache.c
+++ b/arch/powerpc/kernel/eeh_cache.c
@@ -194,7 +194,7 @@ static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
}
/* Skip any devices for which EEH is not enabled. */
- if (!edev->pe) {
+ if (!eeh_probe_mode_dev() && !edev->pe) {
#ifdef DEBUG
pr_info("PCI: skip building address cache for=%s - %s\n",
pci_name(dev), dn->full_name);
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 3e5c3d5..0ff9a3a 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -998,6 +998,7 @@ static void pnv_pci_ioda_fixup(void)
pnv_pci_ioda_create_dbgfs();
#ifdef CONFIG_EEH
+ eeh_probe_mode_set(EEH_PROBE_MODE_DEV);
eeh_addr_cache_build();
eeh_init();
#endif
--
1.7.5.4
^ permalink raw reply related
* Re: [PATCH 2/8] powerpc/perf: Rework disable logic in pmu_disable()
From: Michael Ellerman @ 2013-06-26 3:28 UTC (permalink / raw)
To: Anshuman Khandual; +Cc: linuxppc-dev, sukadev, Paul Mackerras
In-Reply-To: <51C97D7F.4030405@linux.vnet.ibm.com>
On Tue, Jun 25, 2013 at 04:52:39PM +0530, Anshuman Khandual wrote:
> On 06/24/2013 04:58 PM, Michael Ellerman wrote:
> > In pmu_disable() we disable the PMU by setting the FC (Freeze Counters)
> > bit in MMCR0. In order to do this we have to read/modify/write MMCR0.
> >
> > It's possible that we read a value from MMCR0 which has PMAO (PMU Alert
> > Occurred) set. When we write that value back it will cause an interrupt
> > to occur. We will then end up in the PMU interrupt handler even though
> > we are supposed to have just disabled the PMU.
> >
>
> Is that possible ? First of all MMCR0[PMAO] could not be written by SW.
> Even if you try writing it, how its going to generate PMU interrupt ?
> HW sets this bit MMCR0[PMAO] after a PMU interrupt has already occurred
> not that if we set this, a PMU interrupt would be generated.
Yes it's possible.
cheers
^ permalink raw reply
* Re: BUG: no PCI/PCIe devices found in 85xx architecture
From: Stefani Seibold @ 2013-06-26 5:21 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <1372203995.8183.26@snotra>
Am Dienstag, den 25.06.2013, 18:46 -0500 schrieb Scott Wood:
> On 06/25/2013 01:40:14 PM, Stefani Seibold wrote:
> > Hi,
> >
> > there is a bug in kernel 3.9 which the new fsl_pci platform driver.
> > The
> > pcibios_init in pci_32.c will be called before the platform driver
> > probe
> > will be invoked.
> >
> > The call order for a p2020 board with linux 3.9 is currently:
> >
> > fsl_pci_init
> > pcibios_init
> > fsl_pci_probe
> > fsl_pci_probe
> > fsl_pci_probe
> >
> > Therefore the PCI/PCIe bridge will be added after the PCI/PCIe busses
> > was scanned for devices. So no PCI/PCIe devices are available.
> >
> > Everything works fine by reverting the fsl_pci.[ch] to the version in
> > linux 3.4, because the PCI/PCIe bridges will be added in
> > the ..._setup_arch() function, before the pcibios_init function is
> > called.
> >
> > Any solution for this issue?
>
> I can't reproduce this on p3041 -- pcibios_init gets called after
> fsl_pci_probe, and its PCIe e1000 gets detected and used.
>
> fsl_pci_probe should be called when of_platform_bus_probe is called,
> which is in a machine_arch_initcall. pcibios_init is a
> subsys_initcall, which should happen later.
>
> Which p2020 board are you using? Could you check when it is calling
> of_platform_bus_probe?
>
> -Scott
Great, you are my hero. This is the solution.
In my old board support package for the kernel 3.4 there was a
machine_device_initcall(). I did not saw the tiny difference against
machine_arch_initcall() used by the other 85xx boards as i ported it to
3.9.
Thanks
- Stefani
^ permalink raw reply
* [PATCH 0/6 v5] KVM :PPC: Userspace Debug support
From: Bharat Bhushan @ 2013-06-26 5:42 UTC (permalink / raw)
To: kvm-ppc, kvm, agraf, scottwood, tiejun.chen, benh, linuxppc-dev,
linux-kernel, mikey
Cc: Bharat Bhushan
From: Bharat Bhushan <bharat.bhushan@freescale.com>
Note: These patches are based on http://github.com/agraf/linux-2.6.git queue
This patchset adds the userspace debug support for booke/bookehv.
this is tested on powerpc e500v2/e500mc devices.
We are now assuming that debug resource will not be used by kernel for
its own debugging. It will be used for only kernel user process debugging.
So the kernel debug load interface during context_to is used to load
debug conext for that selected process.
v4->v5
- Some comments reworded and other cleanup (like change of function name etc)
- Added a function for setting MSRP rather than inline
v3->v4
- 4 out of 7 patches of initial patchset were applied.
This patchset is on and above those 4 patches
- KVM local "struct kvmppc_booke_debug_reg" is replaced by
powerpc global "struct debug_reg"
- use switch_booke_debug_regs() for debug register context switch.
- Save DBSR before kernel pre-emption is enabled.
- Some more cleanup
v2->v3
- We are now assuming that debug resource will not be used by
kernel for its own debugging.
It will be used for only kernel user process debugging.
So the kernel debug load interface during context_to is
used to load debug conext for that selected process.
v1->v2
- Debug registers are save/restore in vcpu_put/vcpu_get.
Earlier the debug registers are saved/restored in guest entry/exit
Bharat Bhushan (6):
powerpc: remove unnecessary line continuations
powerpc: move debug registers in a structure
powerpc: export debug registers save function for KVM
KVM: PPC: exit to user space on "ehpriv" instruction
KVM: PPC: Using "struct debug_reg"
KVM: PPC: Add userspace debug stub support
arch/powerpc/include/asm/disassemble.h | 4 +
arch/powerpc/include/asm/kvm_host.h | 16 +--
arch/powerpc/include/asm/processor.h | 38 +++--
arch/powerpc/include/asm/reg_booke.h | 8 +-
arch/powerpc/include/asm/switch_to.h | 4 +
arch/powerpc/include/uapi/asm/kvm.h | 22 ++-
arch/powerpc/kernel/asm-offsets.c | 2 +-
arch/powerpc/kernel/process.c | 45 +++---
arch/powerpc/kernel/ptrace.c | 154 +++++++++---------
arch/powerpc/kernel/signal_32.c | 6 +-
arch/powerpc/kernel/traps.c | 35 ++--
arch/powerpc/kvm/booke.c | 273 ++++++++++++++++++++++++++++----
arch/powerpc/kvm/booke.h | 5 +
arch/powerpc/kvm/e500_emulate.c | 27 +++
14 files changed, 455 insertions(+), 184 deletions(-)
^ permalink raw reply
* [PATCH 1/6 v5] powerpc: remove unnecessary line continuations
From: Bharat Bhushan @ 2013-06-26 5:42 UTC (permalink / raw)
To: kvm-ppc, kvm, agraf, scottwood, tiejun.chen, benh, linuxppc-dev,
linux-kernel, mikey
Cc: Bharat Bhushan
In-Reply-To: <1372225346-5029-1-git-send-email-Bharat.Bhushan@freescale.com>
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
arch/powerpc/kernel/process.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index ceb4e7b..639a8de 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -325,7 +325,7 @@ static void set_debug_reg_defaults(struct thread_struct *thread)
/*
* Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
*/
- thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \
+ thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
DBCR1_IAC3US | DBCR1_IAC4US;
/*
* Force Data Address Compare User/Supervisor bits to be User-only
--
1.7.0.4
^ permalink raw reply related
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