* Re: windfarm_fcu_controls: cpu-pump-0 <HW FAULT>
From: Andreas Schwab @ 2013-08-03 8:43 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Andreas Schwab
In-Reply-To: <1375481448.15999.47.camel__48019.1930350431$1375481501$gmane$org@pasglop>
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
> Can you add some more printk's in there to check what's going on inside
> wf_fcu_get_pump_minmax() ?
All values from mpu->processor_part_num are 0xffff.
> Also is it getting faults for both pumps ?
Yes.
> Does it work with the older driver ? (both the minmax and the reading of
> the pump).
The minmax situation is the same, but otherwise appears to work (no fan
reading errors logged). Here is an example debug output:
** CPU 1 RPM: 300 Ex, 300, Pump: 1250, In, overtemp: 0
cpu 0, exhaust RPM: 300
cpu 0, temp raw: 023c, m_diode: 9982, b_diode: fffff799
temp: 52.139
cpu 0, current: 8.789, voltage: 1.286, power: 11.308 W
cpu 1, exhaust RPM: 300
cpu 1, temp raw: 021c, m_diode: a047, b_diode: fffff777
temp: 50.380
cpu 1, current: 8.666, voltage: 1.281, power: 11.108 W
power target: 55.000, error: 43.691
integral: 00f42f8d
integ_p: 10
adj_in_target: 65.011, ttarget: 74
deriv_p: -15
prop_p: -103
sum: -118
> What is the "failures" bitmask value ?
3 for both.
Andreas.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
^ permalink raw reply
* Re: [PATCH 6/6 v2] kvm: powerpc: use caching attributes as per linux pte
From: Benjamin Herrenschmidt @ 2013-08-03 4:25 UTC (permalink / raw)
To: Bhushan Bharat-R65777
Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org, agraf@suse.de,
kvm-ppc@vger.kernel.org, kvm@vger.kernel.org
In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D070F8FE9@039-SN2MPN1-012.039d.mgd.msft.net>
On Sat, 2013-08-03 at 03:11 +0000, Bhushan Bharat-R65777 wrote:
>
> >
> > Could you explain why we need to set dirty/referenced on the PTE, when we didn't
> > need to do that before? All we're getting from the PTE is wimg.
> > We have MMU notifiers to take care of the page being unmapped, and we've already
> > marked the page itself as dirty if the TLB entry is writeable.
>
> I pulled this code from book3s.
>
> Ben, can you describe why we need this on book3s ?
If you let the guest write to the page you must set the dirty bit on the PTE
(or the struct page, at least one of them), similar with accessed on any access.
If you don't, the VM might swap the page out without writing it back to disk
for example, assuming it contains no modified data.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 5/6 v2] kvm: powerpc: booke: Add linux pte lookup like booke3s
From: Benjamin Herrenschmidt @ 2013-08-03 4:24 UTC (permalink / raw)
To: Bhushan Bharat-R65777
Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org, agraf@suse.de,
kvm-ppc@vger.kernel.org, kvm@vger.kernel.org
In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D070F8FCC@039-SN2MPN1-012.039d.mgd.msft.net>
On Sat, 2013-08-03 at 02:58 +0000, Bhushan Bharat-R65777 wrote:
> One of the problem I saw was that if I put this code in
> asm/pgtable-32.h and asm/pgtable-64.h then pte_persent() and other
> friend function (on which this code depends) are defined in pgtable.h.
> And pgtable.h includes asm/pgtable-32.h and asm/pgtable-64.h before it
> defines pte_present() and friends functions.
>
> Ok I move wove this in asm/pgtable*.h, initially I fought with myself
> to take this code in pgtable* but finally end up doing here (got
> biased by book3s :)).
Is there a reason why these routines can not be completely generic
in pgtable.h ?
Ben.
^ permalink raw reply
* RE: [PATCH 6/6 v2] kvm: powerpc: use caching attributes as per linux pte
From: Bhushan Bharat-R65777 @ 2013-08-03 3:11 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org, agraf@suse.de,
kvm-ppc@vger.kernel.org, kvm@vger.kernel.org
In-Reply-To: <20130802233452.GA27636@home.buserror.net>
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Saturday, August 03, 2013 5:05 AM
> To: Bhushan Bharat-R65777
> Cc: benh@kernel.crashing.org; agraf@suse.de; kvm-ppc@vger.kernel.org;
> kvm@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Bhushan Bharat-R65777
> Subject: Re: [PATCH 6/6 v2] kvm: powerpc: use caching attributes as per l=
inux
> pte
>=20
> On Thu, Aug 01, 2013 at 04:42:38PM +0530, Bharat Bhushan wrote:
> > diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index
> > 17722d8..ebcccc2 100644
> > --- a/arch/powerpc/kvm/booke.c
> > +++ b/arch/powerpc/kvm/booke.c
> > @@ -697,7 +697,7 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run,
> > struct kvm_vcpu *vcpu) #endif
> >
> > kvmppc_fix_ee_before_entry();
> > -
> > + vcpu->arch.pgdir =3D current->mm->pgd;
> > ret =3D __kvmppc_vcpu_run(kvm_run, vcpu);
>=20
> kvmppc_fix_ee_before_entry() is supposed to be the last thing that happen=
s
> before __kvmppc_vcpu_run().
>=20
> > @@ -332,6 +324,8 @@ static inline int kvmppc_e500_shadow_map(struct
> kvmppc_vcpu_e500 *vcpu_e500,
> > unsigned long hva;
> > int pfnmap =3D 0;
> > int tsize =3D BOOK3E_PAGESZ_4K;
> > + pte_t pte;
> > + int wimg =3D 0;
> >
> > /*
> > * Translate guest physical to true physical, acquiring @@ -437,6
> > +431,8 @@ static inline int kvmppc_e500_shadow_map(struct
> > kvmppc_vcpu_e500 *vcpu_e500,
> >
> > if (likely(!pfnmap)) {
> > unsigned long tsize_pages =3D 1 << (tsize + 10 - PAGE_SHIFT);
> > + pgd_t *pgdir;
> > +
> > pfn =3D gfn_to_pfn_memslot(slot, gfn);
> > if (is_error_noslot_pfn(pfn)) {
> > printk(KERN_ERR "Couldn't get real page for gfn %lx!\n", @@
> -447,9
> > +443,18 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_=
e500
> *vcpu_e500,
> > /* Align guest and physical address to page map boundaries */
> > pfn &=3D ~(tsize_pages - 1);
> > gvaddr &=3D ~((tsize_pages << PAGE_SHIFT) - 1);
> > + pgdir =3D vcpu_e500->vcpu.arch.pgdir;
> > + pte =3D lookup_linux_pte(pgdir, hva, 1, &tsize_pages);
> > + if (pte_present(pte)) {
> > + wimg =3D (pte >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK;
> > + } else {
> > + printk(KERN_ERR "pte not present: gfn %lx, pfn %lx\n",
> > + (long)gfn, pfn);
> > + return -EINVAL;
> > + }
> > }
>=20
> How does wimg get set in the pfnmap case?
Pfnmap is not kernel managed pages, right? So should we set I+G there ?
>=20
> Could you explain why we need to set dirty/referenced on the PTE, when we=
didn't
> need to do that before? All we're getting from the PTE is wimg.
> We have MMU notifiers to take care of the page being unmapped, and we've =
already
> marked the page itself as dirty if the TLB entry is writeable.
I pulled this code from book3s.
Ben, can you describe why we need this on book3s ?
Thanks
-Bharat
>=20
> -Scott
^ permalink raw reply
* RE: [PATCH 5/6 v2] kvm: powerpc: booke: Add linux pte lookup like booke3s
From: Bhushan Bharat-R65777 @ 2013-08-03 2:58 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org, agraf@suse.de,
kvm-ppc@vger.kernel.org, kvm@vger.kernel.org
In-Reply-To: <1375485408.15999.67.camel@pasglop>
DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogQmVuamFtaW4gSGVycmVu
c2NobWlkdCBbbWFpbHRvOmJlbmhAa2VybmVsLmNyYXNoaW5nLm9yZ10NCj4gU2VudDogU2F0dXJk
YXksIEF1Z3VzdCAwMywgMjAxMyA0OjQ3IEFNDQo+IFRvOiBXb29kIFNjb3R0LUIwNzQyMQ0KPiBD
YzogQmh1c2hhbiBCaGFyYXQtUjY1Nzc3OyBhZ3JhZkBzdXNlLmRlOyBrdm0tcHBjQHZnZXIua2Vy
bmVsLm9yZzsNCj4ga3ZtQHZnZXIua2VybmVsLm9yZzsgbGludXhwcGMtZGV2QGxpc3RzLm96bGFi
cy5vcmc7IEJodXNoYW4gQmhhcmF0LVI2NTc3Nw0KPiBTdWJqZWN0OiBSZTogW1BBVENIIDUvNiB2
Ml0ga3ZtOiBwb3dlcnBjOiBib29rZTogQWRkIGxpbnV4IHB0ZSBsb29rdXAgbGlrZQ0KPiBib29r
ZTNzDQo+IA0KPiBPbiBGcmksIDIwMTMtMDgtMDIgYXQgMTc6NTggLTA1MDAsIFNjb3R0IFdvb2Qg
d3JvdGU6DQo+ID4NCj4gPiBXaGF0IGFib3V0IDY0LWJpdCBQVEVzIG9uIDMyLWJpdCBrZXJuZWxz
Pw0KPiA+DQo+ID4gSW4gYW55IGNhc2UsIHRoaXMgY29kZSBkb2VzIG5vdCBiZWxvbmcgaW4gS1ZN
LiAgSXQgc2hvdWxkIGJlIGluIHRoZQ0KPiA+IG1haW4gUFBDIG1tIGNvZGUsIGV2ZW4gaWYgS1ZN
IGlzIHRoZSBvbmx5IHVzZXIuDQo+IA0KPiBBbHNvIGRvbid0IHdlIGRvIHNpbWlsYXIgdGhpbmdz
IGluIEJvb2tTIEtWTSA/IEF0IHRoZSB2ZXJ5IGxlYXN0IHRoYXQgc3V0ZmYNCj4gc2hvdWxkIGJl
Y29tZSBjb21tb24uIEFuZCB5ZXMsIEkgYWdyZWUsIGl0IHNob3VsZCBwcm9iYWJseSBhbHNvIG1v
dmUgdG8gcGd0YWJsZSoNCg0KT25lIG9mIHRoZSBwcm9ibGVtIEkgc2F3IHdhcyB0aGF0IGlmIEkg
cHV0IHRoaXMgY29kZSBpbiBhc20vcGd0YWJsZS0zMi5oIGFuZCBhc20vcGd0YWJsZS02NC5oIHRo
ZW4gcHRlX3BlcnNlbnQoKSBhbmQgb3RoZXIgZnJpZW5kIGZ1bmN0aW9uIChvbiB3aGljaCB0aGlz
IGNvZGUgZGVwZW5kcykgYXJlIGRlZmluZWQgaW4gcGd0YWJsZS5oLiBBbmQgcGd0YWJsZS5oIGlu
Y2x1ZGVzIGFzbS9wZ3RhYmxlLTMyLmggYW5kIGFzbS9wZ3RhYmxlLTY0LmggYmVmb3JlIGl0IGRl
ZmluZXMgcHRlX3ByZXNlbnQoKSBhbmQgZnJpZW5kcyBmdW5jdGlvbnMuDQoNCk9rIEkgbW92ZSB3
b3ZlIHRoaXMgaW4gYXNtL3BndGFibGUqLmgsIGluaXRpYWxseSBJIGZvdWdodCB3aXRoIG15c2Vs
ZiB0byB0YWtlIHRoaXMgY29kZSBpbiBwZ3RhYmxlKiBidXQgZmluYWxseSBlbmQgdXAgZG9pbmcg
aGVyZSAoZ290IGJpYXNlZCBieSBib29rM3MgOikpLg0KDQpUaGFua3MNCi1CaGFyYXQNCg0KPiAN
Cj4gQ2hlZXJzLA0KPiBCZW4uDQo+IA0KPiANCg0K
^ permalink raw reply
* Re: [PATCH 5/6 v2] kvm: powerpc: booke: Add linux pte lookup like booke3s
From: Benjamin Herrenschmidt @ 2013-08-02 23:16 UTC (permalink / raw)
To: Scott Wood
Cc: kvm, agraf, kvm-ppc, Bharat Bhushan, Bharat Bhushan, linuxppc-dev
In-Reply-To: <1375484319.26902.4.camel@snotra.buserror.net>
On Fri, 2013-08-02 at 17:58 -0500, Scott Wood wrote:
>
> What about 64-bit PTEs on 32-bit kernels?
>
> In any case, this code does not belong in KVM. It should be in the
> main
> PPC mm code, even if KVM is the only user.
Also don't we do similar things in BookS KVM ? At the very least that
sutff should become common. And yes, I agree, it should probably also
move to pgtable*
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH v3 17/31] clk: mpc512x: introduce COMMON_CLK for MPC512x
From: Mike Turquette @ 2013-08-02 23:41 UTC (permalink / raw)
To: Gerhard Sittig, linuxppc-dev, Anatolij Gustschin,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
In-Reply-To: <1374495298-22019-18-git-send-email-gsi@denx.de>
Quoting Gerhard Sittig (2013-07-22 05:14:44)
> this change implements a clock driver for the MPC512x PowerPC platform
> which follows the COMMON_CLK approach and uses common clock drivers
> shared with other platforms
> =
> this driver implements the publicly announced set of clocks (which can
> get referenced by means of symbolic identifiers from the dt-bindings
> header file), as well as generates additional 'struct clk' items where
> the SoC hardware cannot easily get mapped to the common primitives of
> the clock API, or requires "intermediate" clock nodes to represent
> clocks that have both gates and dividers
> =
> the previous PPC_CLOCK implementation is kept in place and remains in
> parallel to the common clock implementation for test and comparison
> during migration, a compile time option picks one of the two
> alternatives (Kconfig switch, common clock used by default)
> =
> some of the clock items get pre-enabled in the clock driver to not have
> them automatically disabled by the underlying clock subsystem because of
> their being unused -- this approach is desirable because
> - some of the clocks are useful to have for diagnostics and information
> despite their not getting claimed by any drivers (CPU, internal and
> external RAM, internal busses, boot media)
> - some of the clocks aren't claimed by their peripheral drivers yet,
> either because of missing driver support or because device tree specs
> aren't available yet (but the workarounds will get removed as the
> drivers get adjusted and the device tree provides the clock specs)
> - some help introduce support for and migrate to the common
> infrastructure, while more appropriate support for specific hardware
> constraints isn't available yet (remaining changes are strictly
> internal to the clock driver and won't affect peripheral drivers)
> =
> clkdev registration provides "alias names" for few clock items
> - to not break those peripheral drivers which encode their component
> index into the name that is used for clock lookup (UART, SPI, USB)
> - to not break those drivers which use names for the clock lookup which
> were encoded in the previous PPC_CLOCK implementation (NFC, VIU, CAN)
> this workaround will get removed as these drivers get adjusted after
> device tree based clock lookup has become available
> =
> Signed-off-by: Gerhard Sittig <gsi@denx.de>
Hi Gerhard,
This looks OK to me. Do you want me to take it or will you keep the
series together? Note that I took "clk: wrap I/O access for improved
portability" into the clk tree already.
Regards,
Mike
> ---
> arch/powerpc/platforms/512x/Kconfig | 14 +-
> arch/powerpc/platforms/512x/Makefile | 4 +-
> arch/powerpc/platforms/512x/clock-commonclk.c | 786 +++++++++++++++++++=
++++++
> include/linux/clk-provider.h | 16 +
> 4 files changed, 818 insertions(+), 2 deletions(-)
> create mode 100644 arch/powerpc/platforms/512x/clock-commonclk.c
> =
> diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms=
/512x/Kconfig
> index fc9c1cb..c5fcdd0 100644
> --- a/arch/powerpc/platforms/512x/Kconfig
> +++ b/arch/powerpc/platforms/512x/Kconfig
> @@ -1,9 +1,21 @@
> +config MPC512x_COMMON_CLK
> + bool "MPC512x platform uses COMMON_CLK"
> + default y
> + depends on PPC_MPC512x
> + help
> + This option is only here to support tests and comparison
> + during development and migration. This option will get
> + removed after the COMMON_CLK support for MPC512x has become
> + fully operational and all drivers were adjusted to explicitly
> + acquire their required clocks.
> +
> config PPC_MPC512x
> bool "512x-based boards"
> depends on 6xx
> select FSL_SOC
> select IPIC
> - select PPC_CLOCK
> + select PPC_CLOCK if !MPC512x_COMMON_CLK
> + select COMMON_CLK if MPC512x_COMMON_CLK
> select PPC_PCI_CHOICE
> select FSL_PCI if PCI
> select ARCH_WANT_OPTIONAL_GPIOLIB
> diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platform=
s/512x/Makefile
> index 72fb934..1e05f9d 100644
> --- a/arch/powerpc/platforms/512x/Makefile
> +++ b/arch/powerpc/platforms/512x/Makefile
> @@ -1,7 +1,9 @@
> #
> # Makefile for the Freescale PowerPC 512x linux kernel.
> #
> -obj-y +=3D clock.o mpc512x_shared.o
> +obj-$(CONFIG_PPC_CLOCK) +=3D clock.o
> +obj-$(CONFIG_COMMON_CLK) +=3D clock-commonclk.o
> +obj-y +=3D mpc512x_shared.o
> obj-$(CONFIG_MPC5121_ADS) +=3D mpc5121_ads.o mpc5121_ads_cpld.o
> obj-$(CONFIG_MPC512x_GENERIC) +=3D mpc512x_generic.o
> obj-$(CONFIG_PDM360NG) +=3D pdm360ng.o
> diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc=
/platforms/512x/clock-commonclk.c
> new file mode 100644
> index 0000000..762ee85
> --- /dev/null
> +++ b/arch/powerpc/platforms/512x/clock-commonclk.c
> @@ -0,0 +1,786 @@
> +/*
> + * Copyright (C) 2013 DENX Software Engineering
> + *
> + * Gerhard Sittig, <gsi@denx.de>
> + *
> + * common clock driver support for the MPC512x platform
> + *
> + * This is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/device.h>
> +#include <linux/errno.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +
> +#include <asm/mpc5121.h>
> +#include <dt-bindings/clock/mpc512x-clock.h>
> +
> +#include "mpc512x.h" /* our public mpc5121_clk_init() API */
> +
> +/* helpers to keep the MCLK intermediates "somewhere" in our table */
> +enum {
> + MCLK_IDX_MUX0,
> + MCLK_IDX_EN0,
> + MCLK_IDX_DIV0,
> + MCLK_IDX_MUX1,
> + MCLK_MAX_IDX,
> +};
> +
> +#define NR_PSCS 12
> +#define NR_MSCANS 4
> +#define NR_SPDIFS 1
> +#define NR_MCLKS (NR_PSCS + NR_MSCANS + NR_SPDIFS)
> +
> +/* extend the public set of clocks by adding internal slots for manageme=
nt */
> +enum {
> + /* arrange for adjacent numbers after the public set */
> + MPC512x_CLK_START_PRIVATE =3D MPC512x_CLK_LAST_PUBLIC,
> + /* clocks which aren't announced to the public */
> + MPC512x_CLK_DDR,
> + MPC512x_CLK_MEM,
> + MPC512x_CLK_IIM,
> + MPC512x_CLK_SDHC_2,
> + /* intermediates in div+gate combos or fractional dividers */
> + MPC512x_CLK_DDR_UG,
> + MPC512x_CLK_SDHC_x4,
> + MPC512x_CLK_SDHC_UG,
> + MPC512x_CLK_DIU_x4,
> + MPC512x_CLK_DIU_UG,
> + MPC512x_CLK_MBX_BUS_UG,
> + MPC512x_CLK_MBX_UG,
> + MPC512x_CLK_MBX_3D_UG,
> + MPC512x_CLK_PCI_UG,
> + MPC512x_CLK_NFC_UG,
> + MPC512x_CLK_LPC_UG,
> + MPC512x_CLK_SPDIF_TX_IN,
> + /* intermediates for the mux+gate+div+mux MCLK generation */
> + MPC512x_CLK_MCLKS_FIRST,
> + MPC512x_CLK_MCLKS_LAST =3D MPC512x_CLK_MCLKS_FIRST
> + + NR_MCLKS * MCLK_MAX_IDX,
> + /* internal, symbolic spec for the number of slots */
> + MPC512x_CLK_LAST_PRIVATE,
> +};
> +
> +/* data required for the OF clock provider registration */
> +static struct clk *clks[MPC512x_CLK_LAST_PRIVATE];
> +static struct clk_onecell_data clk_data;
> +
> +/* CCM register access */
> +static struct mpc512x_ccm __iomem *clkregs;
> +static DEFINE_SPINLOCK(clklock);
> +
> +/* convenience wrappers around the common clk API */
> +static inline struct clk *mpc512x_clk_fixed(const char *name, int rate)
> +{
> + return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rat=
e);
> +}
> +
> +static inline struct clk *mpc512x_clk_factor(
> + const char *name, const char *parent_name,
> + int mul, int div)
> +{
> + int clkflags;
> +
> + clkflags =3D CLK_SET_RATE_PARENT;
> + return clk_register_fixed_factor(NULL, name, parent_name, clkflag=
s,
> + mul, div);
> +}
> +
> +static inline struct clk *mpc512x_clk_divider(
> + const char *name, const char *parent_name, u8 clkflags,
> + u32 __iomem *reg, u8 pos, u8 len, int divflags)
> +{
> + return clk_register_divider(NULL, name, parent_name, clkflags,
> + reg, pos, len, divflags, &clklock);
> +}
> +
> +static inline struct clk *mpc512x_clk_divtable(
> + const char *name, const char *parent_name,
> + u32 __iomem *reg, u8 pos, u8 len,
> + const struct clk_div_table *divtab)
> +{
> + u8 divflags;
> +
> + divflags =3D 0;
> + return clk_register_divider_table(NULL, name, parent_name, 0,
> + reg, pos, len, divflags,
> + divtab, &clklock);
> +}
> +
> +static inline struct clk *mpc512x_clk_gated(
> + const char *name, const char *parent_name,
> + u32 __iomem *reg, u8 pos)
> +{
> + int clkflags;
> +
> + clkflags =3D CLK_SET_RATE_PARENT;
> + return clk_register_gate(NULL, name, parent_name, clkflags,
> + reg, pos, 0, &clklock);
> +}
> +
> +static inline struct clk *mpc512x_clk_muxed(const char *name,
> + const char **parent_names, int parent_count,
> + u32 __iomem *reg, u8 pos, u8 len)
> +{
> + int clkflags;
> + u8 muxflags;
> +
> + clkflags =3D CLK_SET_RATE_PARENT;
> + muxflags =3D 0;
> + return clk_register_mux(NULL, name,
> + parent_names, parent_count, clkflags,
> + reg, pos, len, muxflags, &clklock);
> +}
> +
> +/* helper to isolate a bit field from a register */
> +static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint=
8_t len)
> +{
> + uint32_t val;
> +
> + val =3D in_be32(reg);
> + val >>=3D pos;
> + val &=3D (1 << len) - 1;
> + return val;
> +}
> +
> +/* get the SPMF and translate it into the "sys pll" multiplier */
> +static int get_spmf_mult(void)
> +{
> + static int spmf_to_mult[] =3D {
> + 68, 1, 12, 16, 20, 24, 28, 32,
> + 36, 40, 44, 48, 52, 56, 60, 64,
> + };
> + int spmf;
> +
> + spmf =3D get_bit_field(&clkregs->spmr, 24, 4);
> + return spmf_to_mult[spmf];
> +}
> +
> +/*
> + * get the SYS_DIV value and translate it into a divide factor
> + *
> + * values returned from here are a multiple of the real factor since the
> + * divide ratio is fractional
> + */
> +static int get_sys_div_x2(void)
> +{
> + static int sysdiv_code_to_x2[] =3D {
> + 4, 5, 6, 7, 8, 9, 10, 14,
> + 12, 16, 18, 22, 20, 24, 26, 30,
> + 28, 32, 34, 38, 36, 40, 42, 46,
> + 44, 48, 50, 54, 52, 56, 58, 62,
> + 60, 64, 66,
> + };
> + int divcode;
> +
> + divcode =3D get_bit_field(&clkregs->scfr2, 26, 6);
> + return sysdiv_code_to_x2[divcode];
> +}
> +
> +/*
> + * get the CPMF value and translate it into a multiplier factor
> + *
> + * values returned from here are a multiple of the real factor since the
> + * multiplier ratio is fractional
> + */
> +static int get_cpmf_mult_x2(void)
> +{
> + static int cpmf_to_mult[] =3D {
> + 72, 2, 2, 3, 4, 5, 6, 7,
> + };
> + int cpmf;
> +
> + cpmf =3D get_bit_field(&clkregs->spmr, 16, 4);
> + return cpmf_to_mult[cpmf];
> +}
> +
> +/*
> + * some of the clock dividers do scale in a linear way, yet not all of
> + * their bit combinations are legal; use a divider table to get a
> + * resulting set of applicable divider values
> + */
> +
> +/* applies to the IPS_DIV, and PCI_DIV values */
> +static struct clk_div_table divtab_2346[] =3D {
> + { .val =3D 2, .div =3D 2, },
> + { .val =3D 3, .div =3D 3, },
> + { .val =3D 4, .div =3D 4, },
> + { .val =3D 6, .div =3D 6, },
> + { .div =3D 0, },
> +};
> +
> +/* applies to the MBX_DIV, LPC_DIV, and NFC_DIV values */
> +static struct clk_div_table divtab_1234[] =3D {
> + { .val =3D 1, .div =3D 1, },
> + { .val =3D 2, .div =3D 2, },
> + { .val =3D 3, .div =3D 3, },
> + { .val =3D 4, .div =3D 4, },
> + { .div =3D 0, },
> +};
> +
> +static int get_freq_from_dt(char *propname)
> +{
> + struct device_node *np;
> + const unsigned int *prop;
> + int val;
> +
> + val =3D 0;
> + np =3D of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
> + if (np) {
> + prop =3D of_get_property(np, propname, NULL);
> + if (prop)
> + val =3D *prop;
> + of_node_put(np);
> + }
> + return val;
> +}
> +
> +static void mpc512x_clk_preset_data(void)
> +{
> + size_t i;
> +
> + for (i =3D 0; i < ARRAY_SIZE(clks); i++)
> + clks[i] =3D ERR_PTR(-ENODEV);
> +}
> +
> +/*
> + * - receives the "bus frequency" from the caller (that's the IPS clock
> + * rate, the historical source of clock information)
> + * - fetches the system PLL multiplier and divider values as well as the
> + * IPS divider value from hardware
> + * - determines the REF clock rate either from the XTAL/OSC spec (if
> + * there is a device tree node describing the oscillator) or from the
> + * IPS bus clock (supported for backwards compatibility, such that
> + * setups without XTAL/OSC specs keep working)
> + * - creates the "ref" clock item in the clock tree, such that
> + * subsequent code can create the remainder of the hierarchy (REF ->
> + * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
> + * values
> + */
> +static void mpc512x_clk_setup_ref_clock(int bus_freq,
> + int *sys_mul, int *sys_div, int *ips_div)
> +{
> + struct clk *osc_clk;
> + int calc_freq;
> +
> + /* fetch mul/div factors from the hardware */
> + *sys_mul =3D get_spmf_mult();
> + *sys_mul *=3D 2; /* compensate for the fractional divide=
r */
> + *sys_div =3D get_sys_div_x2();
> + *ips_div =3D get_bit_field(&clkregs->scfr1, 23, 3);
> +
> + /* lookup the oscillator node */
> + osc_clk =3D clk_get(NULL, "osc");
> + if (osc_clk) {
> + /* descend REF directly from OSC, verify the IPS rate */
> + clks[MPC512x_CLK_REF] =3D mpc512x_clk_factor("ref", "osc"=
, 1, 1);
> + calc_freq =3D clk_get_rate(clks[MPC512x_CLK_REF]);
> + calc_freq *=3D *sys_mul;
> + calc_freq /=3D *sys_div;
> + calc_freq /=3D 2;
> + calc_freq /=3D *ips_div;
> + if (bus_freq && calc_freq !=3D bus_freq)
> + pr_warn("calc rate %d !=3D OF spec %d\n",
> + calc_freq, bus_freq);
> + } else {
> + /* calculate OSC rate and create REF from the freq value =
*/
> + calc_freq =3D bus_freq; /* start with IPS */
> + calc_freq *=3D *ips_div; /* IPS -> CSB */
> + calc_freq *=3D 2; /* CSB -> SYS */
> + calc_freq *=3D *sys_div; /* SYS -> PLL out */
> + calc_freq /=3D *sys_mul; /* PLL out -> REF =3D=3D OSC */
> + clks[MPC512x_CLK_REF] =3D mpc512x_clk_fixed("ref", calc_f=
req);
> + }
> +}
> +
> +/*
> + * helper code for the MCLK subtree setup
> + *
> + * the overview in section 5.2.4 of the MPC5121e Reference Manual rev4
> + * suggests that all instances of the "PSC clock generation" are equal,
> + * and that one might re-use the PSC setup for MSCAN clock generation
> + * (section 5.2.5) as well, at least the logic if not the data for
> + * description
> + *
> + * the details (starting at page 5-20) show differences in the specific
> + * inputs of the first mux stage ("can clk in", "spdif tx"), and the
> + * factual non-availability of the second mux stage (it's present yet
> + * only one input is valid)
> + *
> + * the MSCAN clock related registers (starting at page 5-35) all
> + * reference "spdif clk" at the first mux stage and don't mention any
> + * "can clk" at all, which somehow is unexpected
> + *
> + * TODO re-check the document, and clarify whether the RM is correct in
> + * the overview or in the details, and whether the difference is a
> + * clipboard induced error or results from chip revisions
> + *
> + * it turns out that the RM rev4 as of 2012-06 talks about "can" for the
> + * PSCs while RM rev3 as of 2008-10 talks about "spdif", so I guess that
> + * first a doc update is required which better reflects reality in the
> + * SoC before the implementation should follow while no questions remain
> + */
> +
> +/*
> + * note that this declaration raises a checkpatch warning, but
> + * it's the very data type which <linux/clk-provider.h> expects,
> + * making this declaration pass checkpatch will break compilation
> + */
> +static const char *parent_names_mux0[] =3D {
> + "sys", "ref", "psc-mclk-in", "spdif-tx",
> +};
> +
> +enum mclk_type {
> + MCLK_TYPE_PSC,
> + MCLK_TYPE_MSCAN,
> + MCLK_TYPE_SPDIF,
> +};
> +
> +struct mclk_setup_data {
> + enum mclk_type type;
> + int comp_idx;
> + bool has_mclk1;
> + int bit_sccr1, bit_sccr2;
> + const char *name_mux0;
> + const char *name_en0;
> + const char *name_div0;
> + const char *parent_names_mux1[2];
> + const char *name_mux1;
> + const char *name_mclk;
> +};
> +
> +#define MCLK_SETUP_DATA_PSC(id) { \
> + MCLK_TYPE_PSC, id, \
> + 0, 27 - id, -1, \
> + "psc" #id "-mux0", \
> + "psc" #id "-en0", \
> + "psc" #id "_mclk_div", \
> + { "psc" #id "_mclk_div", "dummy", }, \
> + "psc" #id "_mclk_out", \
> + "psc" #id "_mclk", \
> +}
> +
> +#define MCLK_SETUP_DATA_MSCAN(id) { \
> + MCLK_TYPE_MSCAN, id, \
> + 0, -1, 25, \
> + "mscan" #id "-mux0", \
> + "mscan" #id "-en0", \
> + "mscan" #id "_mclk_div", \
> + { "mscan" #id "_mclk_div", "dummy", }, \
> + "mscan" #id "_mclk_out", \
> + "mscan" #id "_mclk", \
> +}
> +
> +#define MCLK_SETUP_DATA_SPDIF { \
> + MCLK_TYPE_SPDIF, 0, \
> + 1, -1, 23, \
> + "spdif-mux0", \
> + "spdif-en0", \
> + "spdif_mclk_div", \
> + { "spdif_mclk_div", "spdif-rx", }, \
> + "spdif_mclk_out", \
> + "spdif_mclk", \
> +}
> +
> +static struct mclk_setup_data mclk_psc_data[] =3D {
> + MCLK_SETUP_DATA_PSC(0),
> + MCLK_SETUP_DATA_PSC(1),
> + MCLK_SETUP_DATA_PSC(2),
> + MCLK_SETUP_DATA_PSC(3),
> + MCLK_SETUP_DATA_PSC(4),
> + MCLK_SETUP_DATA_PSC(5),
> + MCLK_SETUP_DATA_PSC(6),
> + MCLK_SETUP_DATA_PSC(7),
> + MCLK_SETUP_DATA_PSC(8),
> + MCLK_SETUP_DATA_PSC(9),
> + MCLK_SETUP_DATA_PSC(10),
> + MCLK_SETUP_DATA_PSC(11),
> +};
> +
> +static struct mclk_setup_data mclk_mscan_data[] =3D {
> + MCLK_SETUP_DATA_MSCAN(0),
> + MCLK_SETUP_DATA_MSCAN(1),
> + MCLK_SETUP_DATA_MSCAN(2),
> + MCLK_SETUP_DATA_MSCAN(3),
> +};
> +
> +static struct mclk_setup_data mclk_spdif_data[] =3D {
> + MCLK_SETUP_DATA_SPDIF,
> +};
> +
> +/* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
> +static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
> +{
> + size_t clks_idx_pub, clks_idx_int;
> + u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */
> + u32 __iomem *sccr_reg; /* system clock control register (enable)=
*/
> + int sccr_bit;
> + int div;
> +
> + /* derive a few parameters from the component type and index */
> + switch (entry->type) {
> + case MCLK_TYPE_PSC:
> + clks_idx_pub =3D MPC512x_CLK_PSC0_MCLK + entry->comp_idx;
> + clks_idx_int =3D MPC512x_CLK_MCLKS_FIRST
> + + (entry->comp_idx) * MCLK_MAX_IDX;
> + mccr_reg =3D &clkregs->psc_ccr[entry->comp_idx];
> + break;
> + case MCLK_TYPE_MSCAN:
> + clks_idx_pub =3D MPC512x_CLK_MSCAN0_MCLK + entry->comp_id=
x;
> + clks_idx_int =3D MPC512x_CLK_MCLKS_FIRST
> + + (NR_PSCS + entry->comp_idx) * MCLK_MAX_IDX;
> + mccr_reg =3D &clkregs->mscan_ccr[entry->comp_idx];
> + break;
> + case MCLK_TYPE_SPDIF:
> + clks_idx_pub =3D MPC512x_CLK_SPDIF_MCLK;
> + clks_idx_int =3D MPC512x_CLK_MCLKS_FIRST
> + + (NR_PSCS + NR_MSCANS) * MCLK_MAX_IDX;
> + mccr_reg =3D &clkregs->spccr;
> + break;
> + default:
> + return;
> + }
> + if (entry->bit_sccr1 >=3D 0) {
> + sccr_reg =3D &clkregs->sccr1;
> + sccr_bit =3D entry->bit_sccr1;
> + } else if (entry->bit_sccr2 >=3D 0) {
> + sccr_reg =3D &clkregs->sccr2;
> + sccr_bit =3D entry->bit_sccr2;
> + } else {
> + sccr_reg =3D NULL;
> + }
> +
> + /*
> + * this was grabbed from the PPC_CLOCK implementation, which
> + * enforced a specific MCLK divider while the clock was gated
> + * during setup (that's a documented hardware requirement)
> + *
> + * the PPC_CLOCK implementation might even have violated the
> + * "MCLK <=3D IPS" constraint, the fixed divider value of 1
> + * results in a divider of 2 and thus MCLK =3D SYS/2 which equals
> + * CSB which is greater than IPS; the serial port setup may have
> + * adjusted the divider which the clock setup might have left in
> + * an undesirable state
> + *
> + * initial setup is:
> + * - MCLK 0 from SYS
> + * - MCLK DIV such to not exceed the IPS clock
> + * - MCLK 0 enabled
> + * - MCLK 1 from MCLK DIV
> + */
> + div =3D clk_get_rate(clks[MPC512x_CLK_SYS]);
> + div /=3D clk_get_rate(clks[MPC512x_CLK_IPS]);
> + out_be32(mccr_reg, (0 << 16));
> + out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17));
> + out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17));
> +
> + /*
> + * create the 'struct clk' items of the MCLK's clock subtree
> + *
> + * note that by design we always create all nodes and won't take
> + * shortcuts here, because
> + * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are
> + * selectable inputs to the CFM while those who "actually use"
> + * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
> + * for their bitrate
> + * - in the absence of "aliases" for clocks we need to create
> + * individial 'struct clk' items for whatever might get
> + * referenced or looked up, even if several of those items are
> + * identical from the logical POV (their rate value)
> + * - for easier future maintenance and for better reflection of
> + * the SoC's documentation, it appears appropriate to generate
> + * clock items even for those muxers which actually are NOPs
> + * (those with two inputs of which one is reserved)
> + */
> + clks[clks_idx_int + MCLK_IDX_MUX0] =3D mpc512x_clk_muxed(
> + entry->name_mux0,
> + &parent_names_mux0[0], ARRAY_SIZE(parent_names_mu=
x0),
> + mccr_reg, 14, 2);
> + clks[clks_idx_int + MCLK_IDX_EN0] =3D mpc512x_clk_gated(
> + entry->name_en0, entry->name_mux0,
> + mccr_reg, 16);
> + clks[clks_idx_int + MCLK_IDX_DIV0] =3D mpc512x_clk_divider(
> + entry->name_div0,
> + entry->name_en0, CLK_SET_RATE_GATE,
> + mccr_reg, 17, 15, 0);
> + if (entry->has_mclk1) {
> + clks[clks_idx_int + MCLK_IDX_MUX1] =3D mpc512x_clk_muxed(
> + entry->name_mux1,
> + &entry->parent_names_mux1[0],
> + ARRAY_SIZE(entry->parent_names_mux1),
> + mccr_reg, 7, 1);
> + } else {
> + clks[clks_idx_int + MCLK_IDX_MUX1] =3D mpc512x_clk_factor(
> + entry->name_mux1, entry->parent_names_mux=
1[0],
> + 1, 1);
> + }
> + if (sccr_reg) {
> + clks[clks_idx_pub] =3D mpc512x_clk_gated(
> + entry->name_mclk,
> + entry->name_mux1, sccr_reg, sccr_bit);
> + } else {
> + clks[clks_idx_pub] =3D mpc512x_clk_factor(
> + entry->name_mclk,
> + entry->name_mux1, 1, 1);
> + }
> +
> + /*
> + * without this "clock device" registration, "simple" lookups in
> + * the SPI master initialization and serial port setup will fail
> + *
> + * those drivers need to get adjusted to lookup their required
> + * clocks from device tree specs, and device tree nodes need to
> + * provide the clock specs, before this clkdev registration
> + * becomes obsolete
> + */
> + clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
> +}
> +
> +static void mpc512x_clk_setup_mclks(struct mclk_setup_data *table, size_=
t count)
> +{
> + while (count-- > 0)
> + mpc512x_clk_setup_mclk(table++);
> +}
> +
> +static void mpc512x_clk_setup_clock_tree(int busfreq)
> +{
> + int sys_mul, sys_div, ips_div;
> + int mul, div;
> + int freq;
> +
> + /*
> + * TODO
> + * - consider whether to handle clocks which have both gates and
> + * dividers via intermediates or by means of composites
> + * - fractional dividers appear to not map well to composites
> + * since they can be seen as a fixed multiplier and an
> + * adjustable divider, while composites can only combine at
> + * most one of a mux, div, and gate each into one 'struct clk'
> + * item
> + * - PSC/MSCAN/SPDIF clock generation OTOH already is very
> + * specific and cannot get mapped to componsites (at least not
> + * a single one, maybe two of them, but see the comment about
> + * "intermediates are referenced from elsewhere, too")
> + * - trim the list of auto-enabled clocks after drivers acquire
> + * them correctly as needed
> + */
> +
> + /* regardless of whether XTAL/OSC exists, have REF created */
> + mpc512x_clk_setup_ref_clock(busfreq, &sys_mul, &sys_div, &ips_div=
);
> +
> + /* now setup the REF -> SYS -> CSB -> IPS hierarchy */
> + clks[MPC512x_CLK_SYS] =3D mpc512x_clk_factor("sys", "ref",
> + sys_mul, sys_div);
> + clks[MPC512x_CLK_CSB] =3D mpc512x_clk_factor("csb", "sys", 1, 2);
> + clks[MPC512x_CLK_IPS] =3D mpc512x_clk_divtable("ips", "csb",
> + &clkregs->scfr1, 23,=
3,
> + divtab_2346);
> +
> + /* now setup anything below SYS and CSB and IPS */
> + clks[MPC512x_CLK_DDR_UG] =3D mpc512x_clk_factor("ddr-ug", "sys", =
1, 2);
> + clks[MPC512x_CLK_SDHC_x4] =3D mpc512x_clk_factor("sdhc-x4", "csb"=
, 4, 1);
> + clks[MPC512x_CLK_SDHC_UG] =3D mpc512x_clk_divider("sdhc-ug", "sdh=
c-x4", 0,
> + &clkregs->scfr2, =
0, 8,
> + CLK_DIVIDER_ONE_B=
ASED);
> + clks[MPC512x_CLK_DIU_x4] =3D mpc512x_clk_factor("diu-x4", "csb", =
4, 1);
> + clks[MPC512x_CLK_DIU_UG] =3D mpc512x_clk_divider("diu-ug", "diu-x=
4", 0,
> + &clkregs->scfr1, 0=
, 8,
> + CLK_DIVIDER_ONE_BA=
SED);
> +
> + /*
> + * the "power architecture PLL" was setup from data which was
> + * sampled from the reset config word, at this point in time the
> + * configuration can be considered fixed and read only (i.e. no
> + * longer adjustable, or no longer in need of adjustment), which
> + * is why we don't register a PLL here but assume fixed factors
> + */
> + mul =3D get_cpmf_mult_x2();
> + div =3D 2; /* compensate for the fractional factor */
> + clks[MPC512x_CLK_E300] =3D mpc512x_clk_factor("e300", "csb", mul,=
div);
> +
> + clks[MPC512x_CLK_MBX_BUS_UG] =3D mpc512x_clk_factor("mbx-bus-ug",=
"csb",
> + 1, 2);
> + clks[MPC512x_CLK_MBX_UG] =3D mpc512x_clk_divtable("mbx-ug", "mbx-=
bus-ug",
> + &clkregs->scfr1, =
14, 3,
> + divtab_1234);
> + clks[MPC512x_CLK_MBX_3D_UG] =3D mpc512x_clk_factor("mbx-3d-ug", "=
mbx-ug",
> + 1, 1);
> + clks[MPC512x_CLK_PCI_UG] =3D mpc512x_clk_divtable("pci-ug", "csb",
> + &clkregs->scfr1, =
20, 3,
> + divtab_2346);
> + clks[MPC512x_CLK_NFC_UG] =3D mpc512x_clk_divtable("nfc-ug", "ips",
> + &clkregs->scfr1, =
8, 3,
> + divtab_1234);
> + clks[MPC512x_CLK_LPC_UG] =3D mpc512x_clk_divtable("lpc-ug", "ips",
> + &clkregs->scfr1, =
11, 3,
> + divtab_1234);
> +
> + clks[MPC512x_CLK_LPC] =3D mpc512x_clk_gated("lpc", "lpc-ug",
> + &clkregs->sccr1, 30);
> + clks[MPC512x_CLK_NFC] =3D mpc512x_clk_gated("nfc", "nfc-ug",
> + &clkregs->sccr1, 29);
> + clks[MPC512x_CLK_PATA] =3D mpc512x_clk_gated("pata", "ips",
> + &clkregs->sccr1, 28);
> + mpc512x_clk_setup_mclks(mclk_psc_data, ARRAY_SIZE(mclk_psc_data));
> + clks[MPC512x_CLK_PSC_FIFO] =3D mpc512x_clk_gated("psc-fifo", "ips=
",
> + &clkregs->sccr1, 1=
5);
> + clks[MPC512x_CLK_SATA] =3D mpc512x_clk_gated("sata", "ips",
> + &clkregs->sccr1, 14);
> + clks[MPC512x_CLK_FEC] =3D mpc512x_clk_gated("fec", "ips",
> + &clkregs->sccr1, 13);
> + clks[MPC512x_CLK_PCI] =3D mpc512x_clk_gated("pci", "pci-ug",
> + &clkregs->sccr1, 11);
> + clks[MPC512x_CLK_DDR] =3D mpc512x_clk_gated("ddr", "ddr-ug",
> + &clkregs->sccr1, 10);
> +
> + clks[MPC512x_CLK_DIU] =3D mpc512x_clk_gated("diu", "diu-ug",
> + &clkregs->sccr2, 31);
> + clks[MPC512x_CLK_AXE] =3D mpc512x_clk_gated("axe", "csb",
> + &clkregs->sccr2, 30);
> + clks[MPC512x_CLK_MEM] =3D mpc512x_clk_gated("mem", "ips",
> + &clkregs->sccr2, 29);
> + clks[MPC512x_CLK_USB1] =3D mpc512x_clk_gated("usb1", "csb",
> + &clkregs->sccr2, 28);
> + clks[MPC512x_CLK_USB2] =3D mpc512x_clk_gated("usb2", "csb",
> + &clkregs->sccr2, 27);
> + clks[MPC512x_CLK_I2C] =3D mpc512x_clk_gated("i2c", "ips",
> + &clkregs->sccr2, 26);
> + mpc512x_clk_setup_mclks(mclk_mscan_data, ARRAY_SIZE(mclk_mscan_da=
ta));
> + clks[MPC512x_CLK_SDHC] =3D mpc512x_clk_gated("sdhc", "sdhc-ug",
> + &clkregs->sccr2, 24);
> + mpc512x_clk_setup_mclks(mclk_spdif_data, ARRAY_SIZE(mclk_spdif_da=
ta));
> + clks[MPC512x_CLK_MBX_BUS] =3D mpc512x_clk_gated("mbx-bus", "mbx-b=
us-ug",
> + &clkregs->sccr2, 22=
);
> + clks[MPC512x_CLK_MBX] =3D mpc512x_clk_gated("mbx", "mbx-ug",
> + &clkregs->sccr2, 21);
> + clks[MPC512x_CLK_MBX_3D] =3D mpc512x_clk_gated("mbx-3d", "mbx-3d-=
ug",
> + &clkregs->sccr2, 20);
> + clks[MPC512x_CLK_IIM] =3D mpc512x_clk_gated("iim", "csb",
> + &clkregs->sccr2, 19);
> + clks[MPC512x_CLK_VIU] =3D mpc512x_clk_gated("viu", "csb",
> + &clkregs->sccr2, 18);
> + clks[MPC512x_CLK_SDHC_2] =3D mpc512x_clk_gated("sdhc-2", "sdhc-ug=
",
> + &clkregs->sccr2, 17);
> +
> + /*
> + * externally provided clocks (when implemented in hardware,
> + * device tree may specify values which otherwise were unknown)
> + */
> + freq =3D get_freq_from_dt("psc_mclk_in");
> + if (!freq)
> + freq =3D 25000000;
> + clks[MPC512x_CLK_PSC_MCLK_IN] =3D mpc512x_clk_fixed("psc_mclk_in"=
, freq);
> + freq =3D get_freq_from_dt("spdif_tx_in");
> + clks[MPC512x_CLK_SPDIF_TX_IN] =3D mpc512x_clk_fixed("spdif_tx_in"=
, freq);
> + freq =3D get_freq_from_dt("spdif_rx_in");
> + clks[MPC512x_CLK_SPDIF_TX_IN] =3D mpc512x_clk_fixed("spdif_rx_in"=
, freq);
> +
> + /* fixed frequency for AC97, always 24.567MHz */
> + clks[MPC512x_CLK_AC97] =3D mpc512x_clk_fixed("ac97", 24567000);
> +
> + /* clkdev registration for compatibility reasons */
> + clk_register_clkdev(clks[MPC512x_CLK_REF], "ref_clk", NULL);
> + clk_register_clkdev(clks[MPC512x_CLK_SYS], "sys_clk", NULL);
> + clk_register_clkdev(clks[MPC512x_CLK_VIU], "viu_clk", NULL);
> + clk_register_clkdev(clks[MPC512x_CLK_NFC], "nfc_clk", NULL);
> + clk_register_clkdev(clks[MPC512x_CLK_USB1], "usb1_clk", NULL);
> + clk_register_clkdev(clks[MPC512x_CLK_USB2], "usb2_clk", NULL);
> +
> + pr_debug("clock tree setup complete\n");
> + freq =3D clk_get_rate(clks[MPC512x_CLK_E300]);
> + pr_debug("derived PPC freq [%d]\n", freq);
> + freq =3D clk_get_rate(clks[MPC512x_CLK_IPS]);
> + pr_debug("derived IPS freq [%d]\n", freq);
> + freq =3D clk_get_rate(clks[MPC512x_CLK_LPC]);
> + pr_debug("derived LPC freq [%d]\n", freq);
> +
> + /* enable some of the clocks here unconditionally because ... */
> + pr_debug("automatically enabling some clocks\n");
> + /* some are essential yet never get claimed by any driver */
> + clk_prepare_enable(clks[MPC512x_CLK_DUMMY]);
> + clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */
> + clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */
> + clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
> + clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
> + clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
> + /* some are required yet no dependencies were declared */
> + clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
> + /* some are not yet acquired by their respective drivers */
> + clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console=
*/
> + clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
> + clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
> + clk_prepare_enable(clks[MPC512x_CLK_I2C]);
> + /*
> + * some have their individual clock subtree with separate clock
> + * items and their individual enable counters, yet share a
> + * common gate (refer to the same register location) while the
> + * common clock driver code is not aware of the fact and the
> + * platform's code doesn't provide specific support either
> + *
> + * what might happen is that e.g. enabling two MSCAN clock items
> + * and disabling one of them will disable the common gate and
> + * thus break the other MSCAN clock as well
> + */
> + clk_prepare_enable(clks[MPC512x_CLK_MSCAN0_MCLK]);
> + clk_prepare_enable(clks[MPC512x_CLK_MSCAN1_MCLK]);
> + clk_prepare_enable(clks[MPC512x_CLK_MSCAN2_MCLK]);
> + clk_prepare_enable(clks[MPC512x_CLK_MSCAN3_MCLK]);
> +}
> +
> +/*
> + * registers the set of public clocks (those listed in the dt-bindings/
> + * header file) for OF lookups, keeps the intermediates private to us
> + */
> +static void mpc5121_clk_register_of_provider(struct device_node *np)
> +{
> + clk_data.clks =3D clks;
> + clk_data.clk_num =3D MPC512x_CLK_LAST_PUBLIC + 1; /* _not_ ARRAY_=
SIZE() */
> + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +}
> +
> +int __init mpc5121_clk_init(void)
> +{
> + struct device_node *clk_np;
> + int busfreq;
> +
> + /* map the clock control registers */
> + clk_np =3D of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock=
");
> + if (!clk_np)
> + return -ENODEV;
> + clkregs =3D of_iomap(clk_np, 0);
> + WARN_ON(!clkregs);
> +
> + /* invalidate all not yet registered clock slots */
> + mpc512x_clk_preset_data();
> +
> + /*
> + * have the device tree scanned for "fixed-clock" nodes (which
> + * includes the oscillator node if the board's DT provides one)
> + */
> + of_clk_init(NULL);
> +
> + /*
> + * add a dummy clock for those situations where a clock spec is
> + * required yet no real clock is involved
> + */
> + clks[MPC512x_CLK_DUMMY] =3D mpc512x_clk_fixed("dummy", 0);
> +
> + /*
> + * have all the real nodes in the clock tree populated from REF
> + * down to all leaves, either starting from the OSC node or from
> + * a REF root that was created from the IPS bus clock input
> + */
> + busfreq =3D get_freq_from_dt("bus-frequency");
> + mpc512x_clk_setup_clock_tree(busfreq);
> +
> + /* register as an OF clock provider */
> + mpc5121_clk_register_of_provider(clk_np);
> +
> + return 0;
> +}
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index c4f7799..7f8fc64 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -497,6 +497,20 @@ static inline const char *of_clk_get_parent_name(str=
uct device_node *np,
> * for improved portability across platforms
> */
> =
> +#if IS_ENABLED(CONFIG_PPC)
> +
> +static inline u32 clk_readl(u32 __iomem *reg)
> +{
> + return ioread32be(reg);
> +}
> +
> +static inline void clk_writel(u32 val, u32 __iomem *reg)
> +{
> + iowrite32be(val, reg);
> +}
> +
> +#else /* platform dependent I/O accessors */
> +
> static inline u32 clk_readl(u32 __iomem *reg)
> {
> return readl(reg);
> @@ -507,5 +521,7 @@ static inline void clk_writel(u32 val, u32 __iomem *r=
eg)
> writel(val, reg);
> }
> =
> +#endif /* platform dependent I/O accessors */
> +
> #endif /* CONFIG_COMMON_CLK */
> #endif /* CLK_PROVIDER_H */
> -- =
> 1.7.10.4
^ permalink raw reply
* Re: [PATCH v3 18/31] dts: mpc512x: add clock specs for client lookups
From: Mike Turquette @ 2013-08-02 23:41 UTC (permalink / raw)
To: Gerhard Sittig, linuxppc-dev, Anatolij Gustschin,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
In-Reply-To: <1374495298-22019-19-git-send-email-gsi@denx.de>
Quoting Gerhard Sittig (2013-07-22 05:14:45)
> this addresses the client side of device tree based clock lookups
> =
> add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu, viu,
> mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the shared
> mpc5121.dtsi include
> =
> these specs map 'clock-names' encoded in drivers to their respective
> 'struct clk' items in the platform's clock driver
> =
> Signed-off-by: Gerhard Sittig <gsi@denx.de>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
> ---
> arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++=
++++++
> 1 file changed, 79 insertions(+)
> =
> diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/m=
pc5121.dtsi
> index 8f4cba0..3657ae6 100644
> --- a/arch/powerpc/boot/dts/mpc5121.dtsi
> +++ b/arch/powerpc/boot/dts/mpc5121.dtsi
> @@ -51,6 +51,10 @@
> compatible =3D "fsl,mpc5121-mbx";
> reg =3D <0x20000000 0x4000>;
> interrupts =3D <66 0x8>;
> + clocks =3D <&clks MPC512x_CLK_MBX_BUS>,
> + <&clks MPC512x_CLK_MBX_3D>,
> + <&clks MPC512x_CLK_MBX>;
> + clock-names =3D "mbx-bus", "mbx-3d", "mbx";
> };
> =
> sram@30000000 {
> @@ -64,6 +68,8 @@
> interrupts =3D <6 8>;
> #address-cells =3D <1>;
> #size-cells =3D <1>;
> + clocks =3D <&clks MPC512x_CLK_NFC>;
> + clock-names =3D "per";
> };
> =
> localbus@80000020 {
> @@ -153,12 +159,22 @@
> compatible =3D "fsl,mpc5121-mscan";
> reg =3D <0x1300 0x80>;
> interrupts =3D <12 0x8>;
> + clocks =3D <&clks MPC512x_CLK_IPS>,
> + <&clks MPC512x_CLK_SYS>,
> + <&clks MPC512x_CLK_REF>,
> + <&clks MPC512x_CLK_MSCAN0_MCLK>;
> + clock-names =3D "ips", "sys", "ref", "mclk";
> };
> =
> can@1380 {
> compatible =3D "fsl,mpc5121-mscan";
> reg =3D <0x1380 0x80>;
> interrupts =3D <13 0x8>;
> + clocks =3D <&clks MPC512x_CLK_IPS>,
> + <&clks MPC512x_CLK_SYS>,
> + <&clks MPC512x_CLK_REF>,
> + <&clks MPC512x_CLK_MSCAN1_MCLK>;
> + clock-names =3D "ips", "sys", "ref", "mclk";
> };
> =
> sdhc@1500 {
> @@ -167,6 +183,9 @@
> interrupts =3D <8 0x8>;
> dmas =3D <&dma0 30>;
> dma-names =3D "rx-tx";
> + clocks =3D <&clks MPC512x_CLK_IPS>,
> + <&clks MPC512x_CLK_SDHC>;
> + clock-names =3D "ipg", "per";
> };
> =
> i2c@1700 {
> @@ -175,6 +194,8 @@
> compatible =3D "fsl,mpc5121-i2c", "fsl-i2c";
> reg =3D <0x1700 0x20>;
> interrupts =3D <9 0x8>;
> + clocks =3D <&clks MPC512x_CLK_I2C>;
> + clock-names =3D "per";
> };
> =
> i2c@1720 {
> @@ -183,6 +204,8 @@
> compatible =3D "fsl,mpc5121-i2c", "fsl-i2c";
> reg =3D <0x1720 0x20>;
> interrupts =3D <10 0x8>;
> + clocks =3D <&clks MPC512x_CLK_I2C>;
> + clock-names =3D "per";
> };
> =
> i2c@1740 {
> @@ -191,6 +214,8 @@
> compatible =3D "fsl,mpc5121-i2c", "fsl-i2c";
> reg =3D <0x1740 0x20>;
> interrupts =3D <11 0x8>;
> + clocks =3D <&clks MPC512x_CLK_I2C>;
> + clock-names =3D "per";
> };
> =
> i2ccontrol@1760 {
> @@ -202,30 +227,46 @@
> compatible =3D "fsl,mpc5121-axe";
> reg =3D <0x2000 0x100>;
> interrupts =3D <42 0x8>;
> + clocks =3D <&clks MPC512x_CLK_AXE>;
> + clock-names =3D "per";
> };
> =
> display@2100 {
> compatible =3D "fsl,mpc5121-diu";
> reg =3D <0x2100 0x100>;
> interrupts =3D <64 0x8>;
> + clocks =3D <&clks MPC512x_CLK_DIU>;
> + clock-names =3D "per";
> };
> =
> can@2300 {
> compatible =3D "fsl,mpc5121-mscan";
> reg =3D <0x2300 0x80>;
> interrupts =3D <90 0x8>;
> + clocks =3D <&clks MPC512x_CLK_IPS>,
> + <&clks MPC512x_CLK_SYS>,
> + <&clks MPC512x_CLK_REF>,
> + <&clks MPC512x_CLK_MSCAN2_MCLK>;
> + clock-names =3D "ips", "sys", "ref", "mclk";
> };
> =
> can@2380 {
> compatible =3D "fsl,mpc5121-mscan";
> reg =3D <0x2380 0x80>;
> interrupts =3D <91 0x8>;
> + clocks =3D <&clks MPC512x_CLK_IPS>,
> + <&clks MPC512x_CLK_SYS>,
> + <&clks MPC512x_CLK_REF>,
> + <&clks MPC512x_CLK_MSCAN3_MCLK>;
> + clock-names =3D "ips", "sys", "ref", "mclk";
> };
> =
> viu@2400 {
> compatible =3D "fsl,mpc5121-viu";
> reg =3D <0x2400 0x400>;
> interrupts =3D <67 0x8>;
> + clocks =3D <&clks MPC512x_CLK_VIU>;
> + clock-names =3D "per";
> };
> =
> mdio@2800 {
> @@ -233,6 +274,8 @@
> reg =3D <0x2800 0x800>;
> #address-cells =3D <1>;
> #size-cells =3D <0>;
> + clocks =3D <&clks MPC512x_CLK_FEC>;
> + clock-names =3D "per";
> };
> =
> eth0: ethernet@2800 {
> @@ -241,6 +284,8 @@
> reg =3D <0x2800 0x800>;
> local-mac-address =3D [ 00 00 00 00 00 00 ];
> interrupts =3D <4 0x8>;
> + clocks =3D <&clks MPC512x_CLK_FEC>;
> + clock-names =3D "per";
> };
> =
> /* USB1 using external ULPI PHY */
> @@ -252,6 +297,8 @@
> interrupts =3D <43 0x8>;
> dr_mode =3D "otg";
> phy_type =3D "ulpi";
> + clocks =3D <&clks MPC512x_CLK_USB1>;
> + clock-names =3D "per";
> };
> =
> /* USB0 using internal UTMI PHY */
> @@ -263,6 +310,8 @@
> interrupts =3D <44 0x8>;
> dr_mode =3D "otg";
> phy_type =3D "utmi_wide";
> + clocks =3D <&clks MPC512x_CLK_USB2>;
> + clock-names =3D "per";
> };
> =
> /* IO control */
> @@ -281,6 +330,8 @@
> compatible =3D "fsl,mpc5121-pata";
> reg =3D <0x10200 0x100>;
> interrupts =3D <5 0x8>;
> + clocks =3D <&clks MPC512x_CLK_PATA>;
> + clock-names =3D "per";
> };
> =
> /* 512x PSCs are not 52xx PSC compatible */
> @@ -292,6 +343,8 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC0_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> /* PSC1 */
> @@ -301,6 +354,8 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC1_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> /* PSC2 */
> @@ -310,6 +365,8 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC2_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> /* PSC3 */
> @@ -319,6 +376,8 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC3_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> /* PSC4 */
> @@ -328,6 +387,8 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC4_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> /* PSC5 */
> @@ -337,6 +398,8 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC5_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> /* PSC6 */
> @@ -346,6 +409,8 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC6_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> /* PSC7 */
> @@ -355,6 +420,8 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC7_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> /* PSC8 */
> @@ -364,6 +431,8 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC8_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> /* PSC9 */
> @@ -373,6 +442,8 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC9_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> /* PSC10 */
> @@ -382,6 +453,8 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC10_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> /* PSC11 */
> @@ -391,12 +464,16 @@
> interrupts =3D <40 0x8>;
> fsl,rx-fifo-size =3D <16>;
> fsl,tx-fifo-size =3D <16>;
> + clocks =3D <&clks MPC512x_CLK_PSC11_MCLK>;
> + clock-names =3D "mclk";
> };
> =
> pscfifo@11f00 {
> compatible =3D "fsl,mpc5121-psc-fifo";
> reg =3D <0x11f00 0x100>;
> interrupts =3D <40 0x8>;
> + clocks =3D <&clks MPC512x_CLK_PSC_FIFO>;
> + clock-names =3D "per";
> };
> =
> dma0: dma@14000 {
> @@ -414,6 +491,8 @@
> #address-cells =3D <3>;
> #size-cells =3D <2>;
> #interrupt-cells =3D <1>;
> + clocks =3D <&clks MPC512x_CLK_PCI>;
> + clock-names =3D "per";
> =
> reg =3D <0x80008500 0x100 /* internal registers */
> 0x80008300 0x8>; /* config space access registers =
*/
> -- =
> 1.7.10.4
^ permalink raw reply
* Re: [PATCH 6/6 v2] kvm: powerpc: use caching attributes as per linux pte
From: Scott Wood @ 2013-08-02 23:34 UTC (permalink / raw)
To: Bharat Bhushan; +Cc: kvm, agraf, kvm-ppc, Bharat Bhushan, linuxppc-dev
In-Reply-To: <1375355558-19187-7-git-send-email-Bharat.Bhushan@freescale.com>
On Thu, Aug 01, 2013 at 04:42:38PM +0530, Bharat Bhushan wrote:
> diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> index 17722d8..ebcccc2 100644
> --- a/arch/powerpc/kvm/booke.c
> +++ b/arch/powerpc/kvm/booke.c
> @@ -697,7 +697,7 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
> #endif
>
> kvmppc_fix_ee_before_entry();
> -
> + vcpu->arch.pgdir = current->mm->pgd;
> ret = __kvmppc_vcpu_run(kvm_run, vcpu);
kvmppc_fix_ee_before_entry() is supposed to be the last thing that
happens before __kvmppc_vcpu_run().
> @@ -332,6 +324,8 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
> unsigned long hva;
> int pfnmap = 0;
> int tsize = BOOK3E_PAGESZ_4K;
> + pte_t pte;
> + int wimg = 0;
>
> /*
> * Translate guest physical to true physical, acquiring
> @@ -437,6 +431,8 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
>
> if (likely(!pfnmap)) {
> unsigned long tsize_pages = 1 << (tsize + 10 - PAGE_SHIFT);
> + pgd_t *pgdir;
> +
> pfn = gfn_to_pfn_memslot(slot, gfn);
> if (is_error_noslot_pfn(pfn)) {
> printk(KERN_ERR "Couldn't get real page for gfn %lx!\n",
> @@ -447,9 +443,18 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
> /* Align guest and physical address to page map boundaries */
> pfn &= ~(tsize_pages - 1);
> gvaddr &= ~((tsize_pages << PAGE_SHIFT) - 1);
> + pgdir = vcpu_e500->vcpu.arch.pgdir;
> + pte = lookup_linux_pte(pgdir, hva, 1, &tsize_pages);
> + if (pte_present(pte)) {
> + wimg = (pte >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK;
> + } else {
> + printk(KERN_ERR "pte not present: gfn %lx, pfn %lx\n",
> + (long)gfn, pfn);
> + return -EINVAL;
> + }
> }
How does wimg get set in the pfnmap case?
Could you explain why we need to set dirty/referenced on the PTE, when we
didn't need to do that before? All we're getting from the PTE is wimg.
We have MMU notifiers to take care of the page being unmapped, and we've
already marked the page itself as dirty if the TLB entry is writeable.
-Scott
^ permalink raw reply
* Re: [PATCH v3 17/31] clk: mpc512x: introduce COMMON_CLK for MPC512x
From: Mike Turquette @ 2013-08-02 23:30 UTC (permalink / raw)
To: Gerhard Sittig, linuxppc-dev, Anatolij Gustschin,
linux-arm-kernel, devicetree
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
In-Reply-To: <20130723131406.GI19071@book.gsilab.sittig.org>
Quoting Gerhard Sittig (2013-07-23 06:14:06)
> [ summary: "shared gate" support desirable? approach acceptable? ]
> =
> On Mon, Jul 22, 2013 at 14:14 +0200, Gerhard Sittig wrote:
> > =
> > this change implements a clock driver for the MPC512x PowerPC platform
> > which follows the COMMON_CLK approach and uses common clock drivers
> > shared with other platforms
> > =
> > [ ... ]
> > =
> > some of the clock items get pre-enabled in the clock driver to not have
> > them automatically disabled by the underlying clock subsystem because of
> > their being unused -- this approach is desirable because
> > [ ... ]
> > - some help introduce support for and migrate to the common
> > infrastructure, while more appropriate support for specific hardware
> > constraints isn't available yet (remaining changes are strictly
> > internal to the clock driver and won't affect peripheral drivers)
> =
> This remark was related to the CAN clocks of the MPC512x SoC.
Gerhard,
Thanks for the patch (way far down below here). I'll check into it to
see if that implementation looks OK. It would be helpful if another
platform with shared gates could weigh in on whether the implementation
works for them.
Still, a shared gate solution is not a prerequisite for this series,
correct?
Regards,
Mike
> =
> The clock subtrees which are involved in generating CAN bitrates
> include one path from the XTAL to an internal MCLK (this is part
> of the CCF support for the platform), and another path from the
> MCLK or yet another IP bus clock to the actual bitrate on the
> wire (this is taken care of within the mscan(4) driver).
> =
> The MCLK generation for CAN is documented in the MPC5121e
> Reference Manual, chapter 5, section 5.2.5 "MSCAN Clock
> Generation". SYS, REF (both internal), PSC_MCLK_IN, and SPDIF_TX
> (both external) are muxed, gated, and divided. The result is
> muxed with IP. The result is fed into the MSCAN component and
> gets muxed with IP again (can't tell why, maybe for backwards
> compatibility).
> =
> In parallel to this MCLK block there is SCCR2[25], the "BDLC and
> MSCAN clock enable", documented in section 5.3.1.3 "System Clock
> Control Register 2". So there is a gate that "somehow needs to
> get setup" yet isn't part of the visible MCLK chain.
> =
> The series up to and including v3 approaches the problem by
> - adding a gate after the second MCLK mux, which gets exported
> for client lookups and is the MCLK input for the mscan(4)
> driver
> - creating that gate for each of the four MSCAN clocks of the
> SoC, all of them referencing the single "enable" bit in the
> SCCR2 register
> - pre-enabling the MSCAN clocks from within the clock driver, and
> thus avoid having the clock disabled from the common
> infrastructure, because disabling one of these clocks had
> closed the shared gate and thus had broken all other clock uses
> =
> > clkdev registration provides "alias names" for few clock items
> > [ ... ]
> > =
> [ ... ]
> > +
> > +/* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
> > +static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
> > +{
> > + size_t clks_idx_pub, clks_idx_int;
> > + u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */
> > + u32 __iomem *sccr_reg; /* system clock control register (enable)=
*/
> > + int sccr_bit;
> > + int div;
> > +
> > + /* derive a few parameters from the component type and index */
> > + switch (entry->type) {
> > + case MCLK_TYPE_PSC:
> > + clks_idx_pub =3D MPC512x_CLK_PSC0_MCLK + entry->comp_idx;
> > + clks_idx_int =3D MPC512x_CLK_MCLKS_FIRST
> > + + (entry->comp_idx) * MCLK_MAX_IDX;
> > + mccr_reg =3D &clkregs->psc_ccr[entry->comp_idx];
> > + break;
> > + case MCLK_TYPE_MSCAN:
> > + clks_idx_pub =3D MPC512x_CLK_MSCAN0_MCLK + entry->comp_id=
x;
> > + clks_idx_int =3D MPC512x_CLK_MCLKS_FIRST
> > + + (NR_PSCS + entry->comp_idx) * MCLK_MAX_IDX;
> > + mccr_reg =3D &clkregs->mscan_ccr[entry->comp_idx];
> > + break;
> > + case MCLK_TYPE_SPDIF:
> > + clks_idx_pub =3D MPC512x_CLK_SPDIF_MCLK;
> > + clks_idx_int =3D MPC512x_CLK_MCLKS_FIRST
> > + + (NR_PSCS + NR_MSCANS) * MCLK_MAX_IDX;
> > + mccr_reg =3D &clkregs->spccr;
> > + break;
> > + default:
> > + return;
> > + }
> > + if (entry->bit_sccr1 >=3D 0) {
> > + sccr_reg =3D &clkregs->sccr1;
> > + sccr_bit =3D entry->bit_sccr1;
> > + } else if (entry->bit_sccr2 >=3D 0) {
> > + sccr_reg =3D &clkregs->sccr2;
> > + sccr_bit =3D entry->bit_sccr2;
> > + } else {
> > + sccr_reg =3D NULL;
> > + }
> > +
> > + /*
> > + * this was grabbed from the PPC_CLOCK implementation, which
> > + * enforced a specific MCLK divider while the clock was gated
> > + * during setup (that's a documented hardware requirement)
> > + *
> > + * the PPC_CLOCK implementation might even have violated the
> > + * "MCLK <=3D IPS" constraint, the fixed divider value of 1
> > + * results in a divider of 2 and thus MCLK =3D SYS/2 which equals
> > + * CSB which is greater than IPS; the serial port setup may have
> > + * adjusted the divider which the clock setup might have left in
> > + * an undesirable state
> > + *
> > + * initial setup is:
> > + * - MCLK 0 from SYS
> > + * - MCLK DIV such to not exceed the IPS clock
> > + * - MCLK 0 enabled
> > + * - MCLK 1 from MCLK DIV
> > + */
> > + div =3D clk_get_rate(clks[MPC512x_CLK_SYS]);
> > + div /=3D clk_get_rate(clks[MPC512x_CLK_IPS]);
> > + out_be32(mccr_reg, (0 << 16));
> > + out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17));
> > + out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17));
> > +
> > + /*
> > + * create the 'struct clk' items of the MCLK's clock subtree
> > + *
> > + * note that by design we always create all nodes and won't take
> > + * shortcuts here, because
> > + * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are
> > + * selectable inputs to the CFM while those who "actually use"
> > + * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
> > + * for their bitrate
> > + * - in the absence of "aliases" for clocks we need to create
> > + * individial 'struct clk' items for whatever might get
> > + * referenced or looked up, even if several of those items are
> > + * identical from the logical POV (their rate value)
> > + * - for easier future maintenance and for better reflection of
> > + * the SoC's documentation, it appears appropriate to generate
> > + * clock items even for those muxers which actually are NOPs
> > + * (those with two inputs of which one is reserved)
> > + */
> > + clks[clks_idx_int + MCLK_IDX_MUX0] =3D mpc512x_clk_muxed(
> > + entry->name_mux0,
> > + &parent_names_mux0[0], ARRAY_SIZE(parent_names_mu=
x0),
> > + mccr_reg, 14, 2);
> > + clks[clks_idx_int + MCLK_IDX_EN0] =3D mpc512x_clk_gated(
> > + entry->name_en0, entry->name_mux0,
> > + mccr_reg, 16);
> > + clks[clks_idx_int + MCLK_IDX_DIV0] =3D mpc512x_clk_divider(
> > + entry->name_div0,
> > + entry->name_en0, CLK_SET_RATE_GATE,
> > + mccr_reg, 17, 15, 0);
> > + if (entry->has_mclk1) {
> > + clks[clks_idx_int + MCLK_IDX_MUX1] =3D mpc512x_clk_muxed(
> > + entry->name_mux1,
> > + &entry->parent_names_mux1[0],
> > + ARRAY_SIZE(entry->parent_names_mux1),
> > + mccr_reg, 7, 1);
> > + } else {
> > + clks[clks_idx_int + MCLK_IDX_MUX1] =3D mpc512x_clk_factor(
> > + entry->name_mux1, entry->parent_names_mux=
1[0],
> > + 1, 1);
> > + }
> > + if (sccr_reg) {
> > + clks[clks_idx_pub] =3D mpc512x_clk_gated(
> > + entry->name_mclk,
> > + entry->name_mux1, sccr_reg, sccr_bit);
> > + } else {
> > + clks[clks_idx_pub] =3D mpc512x_clk_factor(
> > + entry->name_mclk,
> > + entry->name_mux1, 1, 1);
> > + }
> > +
> > + /*
> > + * without this "clock device" registration, "simple" lookups in
> > + * the SPI master initialization and serial port setup will fail
> > + *
> > + * those drivers need to get adjusted to lookup their required
> > + * clocks from device tree specs, and device tree nodes need to
> > + * provide the clock specs, before this clkdev registration
> > + * becomes obsolete
> > + */
> > + clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
> > +}
> > [ ... ]
> =
> This was the routine which sets up _one_ MCLK block, note the
> assignment at the routine's end to the "published" clock item
> that's the gate's output after the second mux stage.
> =
> > [ ... ]
> > + clks[MPC512x_CLK_I2C] =3D mpc512x_clk_gated("i2c", "ips",
> > + &clkregs->sccr2, 26);
> > + mpc512x_clk_setup_mclks(mclk_mscan_data, ARRAY_SIZE(mclk_mscan_da=
ta));
> > + clks[MPC512x_CLK_SDHC] =3D mpc512x_clk_gated("sdhc", "sdhc-ug",
> > + &clkregs->sccr2, 24);
> > + mpc512x_clk_setup_mclks(mclk_spdif_data, ARRAY_SIZE(mclk_spdif_da=
ta));
> > [ ... ]
> =
> This is the invocation of the routine which sets up four MCLK
> blocks for the MSCAN components, while all of them refer to bit
> 25 of SCCR2.
> =
> > [ ... ]
> > +
> > + /* enable some of the clocks here unconditionally because ... */
> > + pr_debug("automatically enabling some clocks\n");
> > + /* some are essential yet never get claimed by any driver */
> > + clk_prepare_enable(clks[MPC512x_CLK_DUMMY]);
> > + clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */
> > + clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */
> > + clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
> > + clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
> > + clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
> > + /* some are required yet no dependencies were declared */
> > + clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
> > + /* some are not yet acquired by their respective drivers */
> > + clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console=
*/
> > + clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
> > + clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
> > + clk_prepare_enable(clks[MPC512x_CLK_I2C]);
> > + /*
> > + * some have their individual clock subtree with separate clock
> > + * items and their individual enable counters, yet share a
> > + * common gate (refer to the same register location) while the
> > + * common clock driver code is not aware of the fact and the
> > + * platform's code doesn't provide specific support either
> > + *
> > + * what might happen is that e.g. enabling two MSCAN clock items
> > + * and disabling one of them will disable the common gate and
> > + * thus break the other MSCAN clock as well
> > + */
> > + clk_prepare_enable(clks[MPC512x_CLK_MSCAN0_MCLK]);
> > + clk_prepare_enable(clks[MPC512x_CLK_MSCAN1_MCLK]);
> > + clk_prepare_enable(clks[MPC512x_CLK_MSCAN2_MCLK]);
> > + clk_prepare_enable(clks[MPC512x_CLK_MSCAN3_MCLK]);
> > +}
> =
> This is the pre-enable workaround for the MSCAN0 to MSCAN3 clock
> items.
> =
> The above approach does work in that it introduces complete
> support for common clock on the MPC512x platform, with the CAN
> component being operational, and the clock driver using shared
> logic across platforms.
> =
> The remaining issue is that regardless of whether CAN is used,
> the (chip internal) clock is enabled. This may not be a problem
> when bitrates aren't generated and the wire isn't driven.
> =
> =
> The question now is how to correctly support the situation where
> a gate is shared between subtrees yet isn't really part of any
> path within the subtrees. I really cannot find a single spot
> where to introduce the gate such that it's not duplicated.
> =
> The appropriate solution would not be to pre-enable those clocks,
> but to either introduce another gate clock type which supports a
> shared reference, or to add support for the shared reference to
> the existing gate code.
> =
> =
> I'd rather not duplicate most or all of the code of clk-gate.c,
> instead I looked into how to add "shared gate" support to the
> existing driver.
> =
> My question is whether the approach is acceptable. It adds
> minimal overhead and shall be OK for the enable/disable path from
> a technical POV. And it doesn't feel like too much of a stretch.
> But there may be non-technical reasons to reject the approach.
> I'd like to learn whether to follow that path before preparing
> another version of the patch series.
> =
> The diffs were taken with the '-w -b' options to demonstrate
> their essence and not drown it in whitespace changes. The
> implementation assumes that the caller which registers the gate
> (the platform's clock driver) provides both the counter cell and
> the lock. And that all gates with a "shared use counter" use the
> same lock (which is satisfied as they all get registered from the
> same spot in the platform's clock driver).
> =
> The CLK_IGNORE_UNUSED flag addresses a different problem. The
> SoC has four MSCAN components, while two of them are enabled in
> the device tree (the other two are present but disabled). So
> during probe two of the clocks get enabled. After probe all
> unused clocks automatically get disabled (that's another two).
> So the "shared use counter" drops to zero although components are
> in use, because "disable, it's unused" isn't told from "disable
> after enable, regular use". The flag would become obsolete if
> the common gate logic would implement a separate disable_unused()
> routine, but I guess this isn't necessary and the use of the flag
> is appropriate.
> =
> That the example use creates a field for just one counter is to
> better demonstrate the use and potential extension as need
> arises. Reducing this to a mere integer variable would be a
> micro optimization.
> =
> =
> The extension of the existing clk_gate implementation:
> =
> --- a/drivers/clk/clk-gate.c
> +++ b/drivers/clk/clk-gate.c
> @@ -46,6 +46,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e=
nable)
> struct clk_gate *gate =3D to_clk_gate(hw);
> int set =3D gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
> unsigned long flags =3D 0;
> + int need_reg_access;
> u32 reg;
> =
> set ^=3D enable;
> @@ -53,6 +54,20 @@ static void clk_gate_endisable(struct clk_hw *hw, int =
enable)
> if (gate->lock)
> spin_lock_irqsave(gate->lock, flags);
> =
> + /*
> + * if a "shared use counter" was specified, keep track of enable
> + * and disable calls and only access hardware registers upon the
> + * very first enable or very last disable call
> + */
> + if (!gate->share_count) {
> + need_reg_access =3D 1;
> + } else if (enable) {
> + need_reg_access =3D (*gate->share_count)++ =3D=3D 0;
> + } else {
> + need_reg_access =3D --(*gate->share_count) =3D=3D 0;
> + }
> +
> + if (need_reg_access) {
> if (gate->flags & CLK_GATE_HIWORD_MASK) {
> reg =3D BIT(gate->bit_idx + 16);
> if (set)
> @@ -67,6 +82,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e=
nable)
> }
> =
> clk_writel(reg, gate->reg);
> + }
> =
> if (gate->lock)
> spin_unlock_irqrestore(gate->lock, flags);
> @@ -118,10 +134,11 @@ EXPORT_SYMBOL_GPL(clk_gate_ops);
> * @clk_gate_flags: gate-specific flags for this clock
> * @lock: shared register lock for this clock
> */
> -struct clk *clk_register_gate(struct device *dev, const char *name,
> +struct clk *clk_register_gate_shared(struct device *dev, const char *nam=
e,
> const char *parent_name, unsigned long flags,
> void __iomem *reg, u8 bit_idx,
> - u8 clk_gate_flags, spinlock_t *lock)
> + u8 clk_gate_flags, spinlock_t *lock,
> + int *share_count)
> {
> struct clk_gate *gate;
> struct clk *clk;
> @@ -152,6 +169,7 @@ struct clk *clk_register_gate(struct device *dev, con=
st char *name,
> gate->bit_idx =3D bit_idx;
> gate->flags =3D clk_gate_flags;
> gate->lock =3D lock;
> + gate->share_count =3D share_count;
> gate->hw.init =3D &init;
> =
> clk =3D clk_register(dev, &gate->hw);
> @@ -161,3 +179,14 @@ struct clk *clk_register_gate(struct device *dev, co=
nst char *name,
> =
> return clk;
> }
> +
> +struct clk *clk_register_gate(struct device *dev, const char *name,
> + const char *parent_name, unsigned long flags,
> + void __iomem *reg, u8 bit_idx,
> + u8 clk_gate_flags, spinlock_t *lock)
> +{
> +
> + return clk_register_gate_shared(dev, name, parent_name, flags,
> + reg, bit_idx, clk_gate_flags,
> + lock, NULL);
> +}
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -222,6 +222,7 @@ struct clk_gate {
> u8 bit_idx;
> u8 flags;
> spinlock_t *lock;
> + int *share_count;
> };
> =
> #define CLK_GATE_SET_TO_DISABLE BIT(0)
> @@ -232,6 +233,11 @@ struct clk *clk_register_gate(struct device *dev, co=
nst char *name,
> const char *parent_name, unsigned long flags,
> void __iomem *reg, u8 bit_idx,
> u8 clk_gate_flags, spinlock_t *lock);
> +struct clk *clk_register_gate_shared(struct device *dev, const char *nam=
e,
> + const char *parent_name, unsigned long flags,
> + void __iomem *reg, u8 bit_idx,
> + u8 clk_gate_flags, spinlock_t *lock,
> + int *share_count);
> =
> struct clk_div_table {
> unsigned int val;
> =
> =
> How to use these shared gates:
> =
> --- a/arch/powerpc/platforms/512x/clock-commonclk.c
> +++ b/arch/powerpc/platforms/512x/clock-commonclk.c
> @@ -123,6 +123,39 @@ static inline struct clk *mpc512x_clk_gated(
> reg, pos, 0, &clklock);
> }
> =
> +enum mpc512x_clk_shared_gate_id_t {
> + MPC512x_CLK_SHARED_GATE_MSCAN,
> + MPC512x_CLK_SHARED_GATE_MAX,
> +};
> +
> +static int mpc512x_clk_gate_counters[MPC512x_CLK_SHARED_GATE_MAX];
> +
> +/*
> + * implementor's note: since clk_gate items don't implement a separate
> + * .disable_unused() callback, their .disable() routine gets called and
> + * "disable the clock as we can't see it's in use" cannot be told from
> + * "regular disable, count these events please"
> + *
> + * passing the CLK_IGNORE_UNUSED flag upon clock creation will suppress
> + * the "disable, unused" call, so use counts won't get unbalanced, the
> + * clock either never got enabled and thus need not get disabled, or
> + * part of the hardware got enabled while disabling the other part isn't
> + * wanted
> + */
> +static inline struct clk *mpc512x_clk_gated_shared(
> + const char *name, const char *parent_name,
> + u32 __iomem *reg, u8 pos,
> + enum mpc512x_clk_shared_gate_id_t share_id)
> +{
> + int clkflags;
> +
> + clkflags =3D CLK_SET_RATE_PARENT;
> + clkflags |=3D CLK_IGNORE_UNUSED;
> + return clk_register_gate_shared(NULL, name, parent_name, clkflags,
> + reg, pos, 0, &clklock,
> + &mpc512x_clk_gate_counters[share_=
id]);
> +}
> +
> static inline struct clk *mpc512x_clk_muxed(const char *name,
> const char **parent_names, int parent_count,
> u32 __iomem *reg, u8 pos, u8 len)
> @@ -520,9 +553,16 @@ static void mpc512x_clk_setup_mclk(struct mclk_setup=
_data *entry)
> 1, 1);
> }
> if (sccr_reg) {
> + if (entry->type =3D=3D MCLK_TYPE_MSCAN) {
> + clks[clks_idx_pub] =3D mpc512x_clk_gated_shared(
> + entry->name_mclk,
> + entry->name_mux1, sccr_reg, sccr_=
bit,
> + MPC512x_CLK_SHARED_GATE_MSCAN);
> + } else {
> clks[clks_idx_pub] =3D mpc512x_clk_gated(
> entry->name_mclk,
> entry->name_mux1, sccr_reg, sccr_=
bit);
> + }
> } else {
> clks[clks_idx_pub] =3D mpc512x_clk_factor(
> entry->name_mclk,
> =
> Local tests have shown that the extension solves the problem of
> how to satisfy the SoC's constraints on the MPC512x platform.
> The MSCAN clocks no longer need to get pre-enabled, instead they
> get setup and enabled only as the mscan(4) driver probes devices
> according to how it was instructed (device tree nodes).
> =
> What do you think? Is the "shared gate" support in the common
> logic appropriate? I'd rather not duplicate all of this code
> just to introduce the specific gate I need, while most of the
> logic is identical to the existing gate implementation. The
> desire isn't to override the gate's operations, but to wrap them
> and to consult a counter in addition, while the register access
> still applies.
> =
> =
> =
> virtually yours
> Gerhard Sittig
> -- =
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de
^ permalink raw reply
* Re: [PATCH 5/6 v2] kvm: powerpc: booke: Add linux pte lookup like booke3s
From: Scott Wood @ 2013-08-02 22:58 UTC (permalink / raw)
To: Bharat Bhushan; +Cc: kvm, agraf, kvm-ppc, Bharat Bhushan, linuxppc-dev
In-Reply-To: <1375355558-19187-6-git-send-email-Bharat.Bhushan@freescale.com>
On Thu, 2013-08-01 at 16:42 +0530, Bharat Bhushan wrote:
> KVM need to lookup linux pte for getting TLB attributes (WIMGE).
> This is similar to how book3s does.
> This will be used in follow-up patches.
>
> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
> ---
> v1->v2
> - This is a new change in this version
>
> arch/powerpc/include/asm/kvm_booke.h | 73 ++++++++++++++++++++++++++++++++++
> 1 files changed, 73 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/kvm_booke.h b/arch/powerpc/include/asm/kvm_booke.h
> index d3c1eb3..903624d 100644
> --- a/arch/powerpc/include/asm/kvm_booke.h
> +++ b/arch/powerpc/include/asm/kvm_booke.h
> @@ -102,4 +102,77 @@ static inline ulong kvmppc_get_msr(struct kvm_vcpu *vcpu)
> {
> return vcpu->arch.shared->msr;
> }
> +
> +/*
> + * Lock and read a linux PTE. If it's present and writable, atomically
> + * set dirty and referenced bits and return the PTE, otherwise return 0.
> + */
> +static inline pte_t kvmppc_read_update_linux_pte(pte_t *p, int writing)
> +{
> + pte_t pte;
> +
> +#ifdef PTE_ATOMIC_UPDATES
> + pte_t tmp;
> + /* wait until _PAGE_BUSY is clear then set it atomically */
_PAGE_BUSY is 0 on book3e.
> +#ifdef CONFIG_PPC64
> + __asm__ __volatile__ (
> + "1: ldarx %0,0,%3\n"
> + " andi. %1,%0,%4\n"
> + " bne- 1b\n"
> + " ori %1,%0,%4\n"
> + " stdcx. %1,0,%3\n"
> + " bne- 1b"
> + : "=&r" (pte), "=&r" (tmp), "=m" (*p)
> + : "r" (p), "i" (_PAGE_BUSY)
> + : "cc");
> +#else
> + __asm__ __volatile__ (
> + "1: lwarx %0,0,%3\n"
> + " andi. %1,%0,%4\n"
> + " bne- 1b\n"
> + " ori %1,%0,%4\n"
> + " stwcx. %1,0,%3\n"
> + " bne- 1b"
> + : "=&r" (pte), "=&r" (tmp), "=m" (*p)
> + : "r" (p), "i" (_PAGE_BUSY)
> + : "cc");
> +#endif
What about 64-bit PTEs on 32-bit kernels?
In any case, this code does not belong in KVM. It should be in the main
PPC mm code, even if KVM is the only user.
-Scott
^ permalink raw reply
* Re: [PATCH v3 16/31] dts: mpc512x: add clock related device tree specs
From: Mike Turquette @ 2013-08-02 22:46 UTC (permalink / raw)
To: Gerhard Sittig, linuxppc-dev, Anatolij Gustschin,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
In-Reply-To: <1374495298-22019-17-git-send-email-gsi@denx.de>
Quoting Gerhard Sittig (2013-07-22 05:14:43)
> this addresses the clock driver aka provider's side of clocks
> - prepare for future '<&clks ID>' phandle references for device tree
> based clock lookup in client drivers
> - introduce a 'clocks' subtree with an 'osc' node for the crystal
> or oscillator SoC input (fixed frequency)
> - provide default values with 33MHz oscillator frequency in the
> common include (the 66MHz IPS bus already was there), add
> override values for the ifm AC14xx board which deviates from
> the reference design (25MHz xtal, 80MHz IPS bus)
> =
> Signed-off-by: Gerhard Sittig <gsi@denx.de>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
> ---
> arch/powerpc/boot/dts/ac14xx.dts | 7 +++++++
> arch/powerpc/boot/dts/mpc5121.dtsi | 15 ++++++++++++++-
> 2 files changed, 21 insertions(+), 1 deletion(-)
> =
> diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac1=
4xx.dts
> index a543c40..a1b8837 100644
> --- a/arch/powerpc/boot/dts/ac14xx.dts
> +++ b/arch/powerpc/boot/dts/ac14xx.dts
> @@ -139,7 +139,14 @@
> };
> };
> =
> + clocks {
> + osc {
> + clock-frequency =3D <25000000>;
> + };
> + };
> +
> soc@80000000 {
> + bus-frequency =3D <80000000>; /* 80 MHz ips bus */
> =
> clock@f00 {
> compatible =3D "fsl,mpc5121rev2-clock", "fsl,mpc5=
121-clock";
> diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/m=
pc5121.dtsi
> index bd14c00..8f4cba0 100644
> --- a/arch/powerpc/boot/dts/mpc5121.dtsi
> +++ b/arch/powerpc/boot/dts/mpc5121.dtsi
> @@ -9,6 +9,8 @@
> * option) any later version.
> */
> =
> +#include <dt-bindings/clock/mpc512x-clock.h>
> +
> /dts-v1/;
> =
> / {
> @@ -73,6 +75,16 @@
> ranges =3D <0x0 0x0 0xfc000000 0x04000000>;
> };
> =
> + clocks {
> + #address-cells =3D <1>;
> + #size-cells =3D <0>;
> +
> + osc {
> + compatible =3D "fsl,mpc512x-osc", "fixed-clock";
> + clock-frequency =3D <33000000>;
> + };
> + };
> +
> soc@80000000 {
> compatible =3D "fsl,mpc5121-immr";
> #address-cells =3D <1>;
> @@ -118,9 +130,10 @@
> };
> =
> /* Clock control */
> - clock@f00 {
> + clks: clock@f00 {
> compatible =3D "fsl,mpc5121-clock";
> reg =3D <0xf00 0x100>;
> + #clock-cells =3D <1>;
> };
> =
> /* Power Management Controller */
> -- =
> 1.7.10.4
^ permalink raw reply
* Re: [PATCH v3 15/31] dts: mpc512x: introduce dt-bindings/clock/ header
From: Mike Turquette @ 2013-08-02 22:43 UTC (permalink / raw)
To: Gerhard Sittig, linuxppc-dev, Anatolij Gustschin,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
In-Reply-To: <1374495298-22019-16-git-send-email-gsi@denx.de>
Quoting Gerhard Sittig (2013-07-22 05:14:42)
> introduce a dt-bindings/ header file for MPC512x clocks,
> providing symbolic identifiers for those SoC clocks which
> clients will reference from their device tree nodes
> =
> Signed-off-by: Gerhard Sittig <gsi@denx.de>
> ---
> include/dt-bindings/clock/mpc512x-clock.h | 59 +++++++++++++++++++++++=
++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 include/dt-bindings/clock/mpc512x-clock.h
> =
> diff --git a/include/dt-bindings/clock/mpc512x-clock.h b/include/dt-bindi=
ngs/clock/mpc512x-clock.h
> new file mode 100644
> index 0000000..46c560e
> --- /dev/null
> +++ b/include/dt-bindings/clock/mpc512x-clock.h
> @@ -0,0 +1,59 @@
> +/*
> + * This header provides constants for MPC512x clock specs in DT bindings.
> + *
> + * Unfortunately the clock number declaration cannot be an enum but
> + * needs to be a list of #define directives since when referenced from
> + * within DTS files they need to get resolved "at compile time".
Above comment is not really necessary. Otherwise,
Reviewed-by: Mike Turquette <mturquette@linaro.org>
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
> +#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
> +
> +#define MPC512x_CLK_DUMMY 0
> +#define MPC512x_CLK_REF 1
> +#define MPC512x_CLK_SYS 2
> +#define MPC512x_CLK_DIU 3
> +#define MPC512x_CLK_VIU 4
> +#define MPC512x_CLK_CSB 5
> +#define MPC512x_CLK_E300 6
> +#define MPC512x_CLK_IPS 7
> +#define MPC512x_CLK_FEC 8
> +#define MPC512x_CLK_SATA 9
> +#define MPC512x_CLK_PATA 10
> +#define MPC512x_CLK_NFC 11
> +#define MPC512x_CLK_LPC 12
> +#define MPC512x_CLK_MBX_BUS 13
> +#define MPC512x_CLK_MBX 14
> +#define MPC512x_CLK_MBX_3D 15
> +#define MPC512x_CLK_AXE 16
> +#define MPC512x_CLK_USB1 17
> +#define MPC512x_CLK_USB2 18
> +#define MPC512x_CLK_I2C 19
> +#define MPC512x_CLK_MSCAN0_MCLK 20
> +#define MPC512x_CLK_MSCAN1_MCLK 21
> +#define MPC512x_CLK_MSCAN2_MCLK 22
> +#define MPC512x_CLK_MSCAN3_MCLK 23
> +#define MPC512x_CLK_SDHC 24
> +#define MPC512x_CLK_PCI 25
> +#define MPC512x_CLK_PSC_MCLK_IN 26
> +#define MPC512x_CLK_SPDIF_TX 27
> +#define MPC512x_CLK_SPDIF_RX 28
> +#define MPC512x_CLK_SPDIF_MCLK 29
> +#define MPC512x_CLK_AC97 30
> +#define MPC512x_CLK_PSC0_MCLK 31
> +#define MPC512x_CLK_PSC1_MCLK 32
> +#define MPC512x_CLK_PSC2_MCLK 33
> +#define MPC512x_CLK_PSC3_MCLK 34
> +#define MPC512x_CLK_PSC4_MCLK 35
> +#define MPC512x_CLK_PSC5_MCLK 36
> +#define MPC512x_CLK_PSC6_MCLK 37
> +#define MPC512x_CLK_PSC7_MCLK 38
> +#define MPC512x_CLK_PSC8_MCLK 39
> +#define MPC512x_CLK_PSC9_MCLK 40
> +#define MPC512x_CLK_PSC10_MCLK 41
> +#define MPC512x_CLK_PSC11_MCLK 42
> +#define MPC512x_CLK_PSC_FIFO 43
> +
> +#define MPC512x_CLK_LAST_PUBLIC 43
> +
> +#endif
> -- =
> 1.7.10.4
^ permalink raw reply
* Re: [PATCH v3 13/31] clk: wrap I/O access for improved portability
From: Mike Turquette @ 2013-08-02 22:30 UTC (permalink / raw)
To: Gerhard Sittig, linuxppc-dev, Anatolij Gustschin,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
In-Reply-To: <1374495298-22019-14-git-send-email-gsi@denx.de>
Quoting Gerhard Sittig (2013-07-22 05:14:40)
> the common clock drivers were motivated/initiated by ARM development
> and apparently assume little endian peripherals
> =
> wrap register/peripherals access in the common code (div, gate, mux)
> in preparation of adding COMMON_CLK support for other platforms
> =
> Signed-off-by: Gerhard Sittig <gsi@denx.de>
I've taken this into clk-next for testing. regmap deserves investigation
but I don't think your series should be blocked on that. We can always
overhaul the basic clock primitives with regmap support later on if that
makes sense.
Regards,
Mike
> ---
> drivers/clk/clk-divider.c | 6 +++---
> drivers/clk/clk-gate.c | 6 +++---
> drivers/clk/clk-mux.c | 6 +++---
> include/linux/clk-provider.h | 17 +++++++++++++++++
> 4 files changed, 26 insertions(+), 9 deletions(-)
> =
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 6d55eb2..2c07061 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct c=
lk_hw *hw,
> struct clk_divider *divider =3D to_clk_divider(hw);
> unsigned int div, val;
> =
> - val =3D readl(divider->reg) >> divider->shift;
> + val =3D clk_readl(divider->reg) >> divider->shift;
> val &=3D div_mask(divider);
> =
> div =3D _get_div(divider, val);
> @@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, =
unsigned long rate,
> if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
> val =3D div_mask(divider) << (divider->shift + 16);
> } else {
> - val =3D readl(divider->reg);
> + val =3D clk_readl(divider->reg);
> val &=3D ~(div_mask(divider) << divider->shift);
> }
> val |=3D value << divider->shift;
> - writel(val, divider->reg);
> + clk_writel(val, divider->reg);
> =
> if (divider->lock)
> spin_unlock_irqrestore(divider->lock, flags);
> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> index 790306e..b7fbd96 100644
> --- a/drivers/clk/clk-gate.c
> +++ b/drivers/clk/clk-gate.c
> @@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e=
nable)
> if (set)
> reg |=3D BIT(gate->bit_idx);
> } else {
> - reg =3D readl(gate->reg);
> + reg =3D clk_readl(gate->reg);
> =
> if (set)
> reg |=3D BIT(gate->bit_idx);
> @@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e=
nable)
> reg &=3D ~BIT(gate->bit_idx);
> }
> =
> - writel(reg, gate->reg);
> + clk_writel(reg, gate->reg);
> =
> if (gate->lock)
> spin_unlock_irqrestore(gate->lock, flags);
> @@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
> u32 reg;
> struct clk_gate *gate =3D to_clk_gate(hw);
> =
> - reg =3D readl(gate->reg);
> + reg =3D clk_readl(gate->reg);
> =
> /* if a set bit disables this clk, flip it before masking */
> if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index 614444c..02ef506 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
> * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock,=
so
> * val =3D 0x4 really means "bit 2, index starts at bit 0"
> */
> - val =3D readl(mux->reg) >> mux->shift;
> + val =3D clk_readl(mux->reg) >> mux->shift;
> val &=3D mux->mask;
> =
> if (mux->table) {
> @@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 i=
ndex)
> if (mux->flags & CLK_MUX_HIWORD_MASK) {
> val =3D mux->mask << (mux->shift + 16);
> } else {
> - val =3D readl(mux->reg);
> + val =3D clk_readl(mux->reg);
> val &=3D ~(mux->mask << mux->shift);
> }
> val |=3D index << mux->shift;
> - writel(val, mux->reg);
> + clk_writel(val, mux->reg);
> =
> if (mux->lock)
> spin_unlock_irqrestore(mux->lock, flags);
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 1ec14a7..c4f7799 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -12,6 +12,7 @@
> #define __LINUX_CLK_PROVIDER_H
> =
> #include <linux/clk.h>
> +#include <linux/io.h>
> =
> #ifdef CONFIG_COMMON_CLK
> =
> @@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(str=
uct device_node *np,
> #define of_clk_init(matches) \
> { while (0); }
> #endif /* CONFIG_OF */
> +
> +/*
> + * wrap access to peripherals in accessor routines
> + * for improved portability across platforms
> + */
> +
> +static inline u32 clk_readl(u32 __iomem *reg)
> +{
> + return readl(reg);
> +}
> +
> +static inline void clk_writel(u32 val, u32 __iomem *reg)
> +{
> + writel(val, reg);
> +}
> +
> #endif /* CONFIG_COMMON_CLK */
> #endif /* CLK_PROVIDER_H */
> -- =
> 1.7.10.4
^ permalink raw reply
* [git pull] Please pull powerpc.git merge branch
From: Benjamin Herrenschmidt @ 2013-08-02 22:28 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev, Linux Kernel list
[ resent in case you missed it ]
Hi Linus !
Here is not quite a handful of powerpc fixes for rc3. The windfarm fix is
a regression fix (though not a new one), the PMU interrupt rename is not
a fix per-se but has been submitted a long time ago and I kept forgetting
to put it in (it puts us back in sync with x86), the other perf bit is
just about putting an API/ABI bit definition in the right place for
userspace to consume, and finally, we have a fix for the VPHN (Virtual
Partition Home Node) feature (notification that the hypervisor is moving
nodes around) which could cause lockups so we may as well fix it now.
Thanks !
Cheers,
Ben.
The following changes since commit ff3d79dc12c2ed38483f6c1e0f26fde430f27c9d:
powerpc/perf: BHRB filter configuration should follow the task (2013-07-24 14:42:34 +1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge
for you to fetch changes up to fe956a1d4081ce1a959f87df397a15e252201f10:
powerpc/windfarm: Fix noisy slots-fan on Xserve (rm31) (2013-08-01 13:11:47 +1000)
----------------------------------------------------------------
Aaro Koskinen (1):
powerpc/windfarm: Fix noisy slots-fan on Xserve (rm31)
Michael Ellerman (2):
powerpc: Rename PMU interrupts from CNT to PMI
powerpc/perf: Export PERF_EVENT_CONFIG_EBB_SHIFT to userspace
Robert Jennings (1):
powerpc: VPHN topology change updates all siblings
arch/powerpc/include/asm/perf_event_server.h | 6 +--
arch/powerpc/include/asm/smp.h | 4 ++
arch/powerpc/include/uapi/asm/Kbuild | 1 +
arch/powerpc/include/uapi/asm/perf_event.h | 18 +++++++++
arch/powerpc/kernel/irq.c | 2 +-
arch/powerpc/mm/numa.c | 59 +++++++++++++++++++++-------
arch/powerpc/perf/core-book3s.c | 2 +-
arch/powerpc/perf/power8-pmu.c | 6 +--
drivers/macintosh/windfarm_rm31.c | 18 ++++-----
9 files changed, 82 insertions(+), 34 deletions(-)
create mode 100644 arch/powerpc/include/uapi/asm/perf_event.h
^ permalink raw reply
* Re: [PATCH] drivers/crypto/nx: saves chaining value from co-processor
From: Fionnuala Gunter @ 2013-08-02 22:16 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1375480754.15999.42.camel@pasglop>
On Sat, 2013-08-03 at 07:59 +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2013-08-02 at 16:55 -0500, Fionnuala Gunter wrote:
> > Sorry, I thought linuxppc-dev was the right tree since the patch is
> > for
> > a ppc driver and you've carried previous nx driver submissions
> > upstream.
> >
> > I want to submit to the proper place, so what is your preference?
>
> Well, that's the right place if you want me to merge it, which seems to
> be what Marcelo is also expecting...
Please merge this patch, it fixes a hot bug.
> However I do wonder why is that expectation there in the first place and
> why aren't those handled by the crypto maintainer...
In the future I can submit patches to the crypto maintainer.
-Fin
^ permalink raw reply
* Re: [PATCH 00/11] Add compression support to pstore
From: Tony Luck @ 2013-08-02 22:12 UTC (permalink / raw)
To: Aruna Balakrishnaiah, linuxppc-dev@ozlabs.org, paulus@samba.org,
linux-kernel@vger.kernel.org, benh@kernel.crashing.org,
keescook@chromium.org
In-Reply-To: <CA+8MBbLuhVDCb26ag3AH0vXrP4MXHLxS5aVn8pTi4=qL1NdR5w@mail.gmail.com>
A quick experiment to use your patchset - but with compression
disabled by tweaking this line in pstore_dump():
zipped_len = -1; //zip_data(dst, hsize + len);
turned out well. This kernel dumps uncompressed dmesg blobs into pstore
and gets them back out again. So it seems likely that the problems are
someplace in the compression/decompression code.
-Tony
^ permalink raw reply
* Re: windfarm_fcu_controls: cpu-pump-0 <HW FAULT>
From: Benjamin Herrenschmidt @ 2013-08-02 22:10 UTC (permalink / raw)
To: Andreas Schwab; +Cc: linuxppc-dev
In-Reply-To: <87r4eb52s6.fsf@igel.home>
On Fri, 2013-08-02 at 21:08 +0200, Andreas Schwab wrote:
> wf_fcu_fan_get_rpm is returning EFAULT when reading the values for the
> cpu pump controls on the PowerMac7,3. Also, wf_fcu_get_pump_minmax is
> unable to get the real limits and falls back to using the defaults.
>
> Here is the output when DEBUG is defined:
Can you add some more printk's in there to check what's going on inside
wf_fcu_get_pump_minmax() ?
Also is it getting faults for both pumps ?
Does it work with the older driver ? (both the minmax and the reading of
the pump). What is the "failures" bitmask value ?
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH v1 05/24] clk: wrap I/O access for improved portability
From: Mike Turquette @ 2013-08-02 22:09 UTC (permalink / raw)
To: Nicolas Pitre, Russell King - ARM Linux
Cc: Detlev Zundel, Wolfram Sang, devicetree-discuss,
Greg Kroah-Hartman, Gerhard Sittig, linuxppc-dev, Rob Herring,
Mark Brown, Marc Kleine-Budde, Wolfgang Grandegger,
David Woodhouse, Sascha Hauer, linux-arm-kernel,
Mauro Carvalho Chehab
In-Reply-To: <alpine.LFD.2.03.1307181330520.14924@syhkavp.arg>
Quoting Nicolas Pitre (2013-07-18 10:47:22)
> On Thu, 18 Jul 2013, Russell King - ARM Linux wrote:
> =
> > 1. clk_get() and clk_put() are NOT part of the common clock API.
> > They're separate - they're part of the clk API, and the infrastructu=
re
> > behind that is clkdev, which is a separately owned thing (by me.)
> > =
> > 2. The "contract" of the clk API is defined by the clk API, not by some
> > random implementation like the common clock API. The clk API is
> > maintained by myself, and is described in include/linux/clk.h
> > =
> > 3. clk_prepare() and clk_unprepare() are functions MUST only be called
> > from contexts where sleeping is permitted. These functions MAY sleep
> > for whatever reason they require to, and as long as they require to.
> > (This is the whole reason these two functions were created in the
> > first place.)
> > =
> > 4. clk_enable() and clk_disable() MAY be called from any context, but
> > MUST never sleep. If you need to talk over a non-atomic bus for the=
se,
> > then these functions should be no-ops, and the code which does that
> > must be executed from the clk_prepare()/clk_unprepare() operations.
> =
> Could the above be included in some form in Documentation/clk.txt (this =
> is likely one of the first location people look for information) and =
> elsewhere if appropriate please?
> =
> A *lot* of people are confused by the prepare-enable-disable-unprepare =
> sequence and when I try to find some rational for the prepare/enable =
> split I can only direct them to mail archive posts since this is nowhere =
> to be found in the kernel.
> =
> The comments in include/linux/clk.h, while correct, are very terse and =
> don't provide any insight to the reason why there is a split in the API.
> =
> The content of Documentation/clk.txt does refer to prepare and enable =
> (and their counterparts) but again doesn't provide any clue about the =
> reason for their existence.
> =
> Since there've been several good posts with usage example now buried =
> into list archives, I think this would go a long way helping people get =
> it right if those were part of the kernel documentation as well.
I'll update Documentation/clk.txt with more verbosity. The document was
originally intended as a "porting guide" to help migrate from legacy
frameworks to the common struct clk implementation. However the scope of
the document should probably be generalized a bit more.
Regards,
Mike
> =
> =
> Nicolas
^ permalink raw reply
* Re: [PATCH] drivers/crypto/nx: saves chaining value from co-processor
From: Benjamin Herrenschmidt @ 2013-08-02 21:59 UTC (permalink / raw)
To: Fionnuala Gunter; +Cc: linuxppc-dev
In-Reply-To: <1375480550.32477.19.camel@what-is-leg>
On Fri, 2013-08-02 at 16:55 -0500, Fionnuala Gunter wrote:
> Sorry, I thought linuxppc-dev was the right tree since the patch is
> for
> a ppc driver and you've carried previous nx driver submissions
> upstream.
>
> I want to submit to the proper place, so what is your preference?
Well, that's the right place if you want me to merge it, which seems to
be what Marcelo is also expecting...
However I do wonder why is that expectation there in the first place and
why aren't those handled by the crypto maintainer...
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] drivers/crypto/nx: saves chaining value from co-processor
From: Fionnuala Gunter @ 2013-08-02 21:55 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1375477741.15999.23.camel@pasglop>
On Sat, 2013-08-03 at 07:09 +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2013-08-02 at 15:58 -0500, Fionnuala Gunter wrote:
> > The chaining value from co-processor was not being saved. This value is
> > needed because it is used as the IV, for example by cts i.e.
> > cts(cbc(aes)).
> >
> > Signed-off-by: Fionnuala Gunter <fin@linux.vnet.ibm.com>
> > Signed-off-by: Marcelo Cerri <mhcerri@linux.vnet.ibm.com>
>
> So now you guys are sending the patch to linuxppc-dev and not the crypto
> list ..
>
> I need to understand things better here. Any reason why those drivers
> aren't handled by the crypto maintainer ?
>
> Ben.
Sorry, I thought linuxppc-dev was the right tree since the patch is for
a ppc driver and you've carried previous nx driver submissions
upstream.
I want to submit to the proper place, so what is your preference?
-Fin
^ permalink raw reply
* Re: [PATCH 00/11] Add compression support to pstore
From: Tony Luck @ 2013-08-02 21:39 UTC (permalink / raw)
To: Aruna Balakrishnaiah, linuxppc-dev@ozlabs.org, paulus@samba.org,
linux-kernel@vger.kernel.org, benh@kernel.crashing.org,
keescook@chromium.org
Cc: jkenisto@linux.vnet.ibm.com, mahesh@linux.vnet.ibm.com,
ccross@android.com, anton@samba.org, cbouatmailru@gmail.com
In-Reply-To: <3908561D78D1C84285E8C5FCA982C28F31CAA167@ORSMSX106.amr.corp.intel.com>
[-- Attachment #1: Type: text/plain, Size: 1598 bytes --]
On Thu, Aug 1, 2013 at 4:42 PM, Luck, Tony <tony.luck@intel.com> wrote:
> when I rebuilt a plain 3.11-rc3 it didn't log anything via pstore either :-(
Well this turned out to be operator error on my part. 3.11-rc3 does in fact
log errors to pstore and allows them to be retrieved and cleared.
So then I start testing with your 11 patches in place.
First boot was fine - ERST had no records, and pstore mounted OK
(and showed no files).
Then I panic'd the machine and rebooted. The boot hung when some
rc script printed"
Mounting other filesystems:
I guess something went wrong when pstore found a non-empty ERST.
I added some debug traces and booted again. This time the boot succeeded
but I saw a GP fault reported from pstore_mkfile(). Possibly in this code:
spin_lock_irqsave(&allpstore_lock, flags);
list_for_each_entry(pos, &allpstore, list) {
if (pos->type == type &&
pos->id == id &&
pos->psi == psi) {
rc = -EEXIST;
break;
}
}
spin_unlock_irqrestore(&allpstore_lock, flags);
My other tracing showed that we'd already found two compressed entries in
ERST and were working on a third when this error happened (implying that
my hang had been a panic that failed to print anything to console)
I've attached one of the compressed files that v3.11-rc3 shows in pstore
now. The "openssl zlib -d" trick you mentioned back in June mostly works
to decode ... but it seems to dump some trailing garbage at the end of
the file.
-Tony
[-- Attachment #2: unknown-erst-5907623178007478273 --]
[-- Type: application/octet-stream, Size: 4375 bytes --]
^ permalink raw reply
* Re: therm_pm72 units, interface
From: Ben Hutchings @ 2013-08-02 20:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Michel Dänzer, linuxppc-dev, Jan Engelhardt
In-Reply-To: <1375476455.15999.13.camel@pasglop>
[-- Attachment #1: Type: text/plain, Size: 1714 bytes --]
On Sat, 2013-08-03 at 06:47 +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2013-08-02 at 16:47 +0200, Michel Dänzer wrote:
> > On Fre, 2013-08-02 at 22:51 +1000, Benjamin Herrenschmidt wrote:
> > > On Fri, 2013-08-02 at 12:03 +0200, Michel Dänzer wrote:
> > > > Could a similar change fix the same problem on desktop G5s? The same
> > > > values for slots_param in windfarm_pm112.c don't help, unfortunately.
> > >
> > > You have a 11,2 and a noisy fan ? Odd, mine(s) don't.... I can dbl check
> > > the values vs. what Darwin uses tomorrow...
> >
> > Yes, see /proc/cpuinfo below.
> >
> > With older kernels (currently still using Debian's 3.2.0-4-powerpc64
> > because of this problem), the fans go basically silent as soon as the
> > windfarm modules are loaded. With current kernels, the fans stay at the
> > level OF sets them to, until after a while they go into 'airplane mode'.
> >
> > One thing I notice now is that the lines like
> >
> > [ 9.539173] windfarm: CPUs control loops started.
> > [ 16.209962] windfarm: Backside control loop started.
> > [ 16.262274] windfarm: Slots control loop started.
> > [ 16.371642] windfarm: Drive bay control loop started.
> >
> > no longer appear in dmesg with current kernels. Should they?
>
> Yes. Do you have all the windfarm modules loaded ? What about
> i2c-powermac ? (It's typical that the latter is missed, I think it
> doesn't auto-load, which we never fixed, we used to request distros to
> just built it in)
We built it as a module in 3.2 and we still do. The regression
apparently occurred between 3.8 and 3.9.
Ben.
--
Ben Hutchings
This sentence contradicts itself - no actually it doesn't.
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 828 bytes --]
^ permalink raw reply
* Re: [PATCH] drivers/crypto/nx: saves chaining value from co-processor
From: Benjamin Herrenschmidt @ 2013-08-02 21:09 UTC (permalink / raw)
To: Fionnuala Gunter; +Cc: linuxppc-dev
In-Reply-To: <1375477090.32477.10.camel@what-is-leg>
On Fri, 2013-08-02 at 15:58 -0500, Fionnuala Gunter wrote:
> The chaining value from co-processor was not being saved. This value is
> needed because it is used as the IV, for example by cts i.e.
> cts(cbc(aes)).
>
> Signed-off-by: Fionnuala Gunter <fin@linux.vnet.ibm.com>
> Signed-off-by: Marcelo Cerri <mhcerri@linux.vnet.ibm.com>
So now you guys are sending the patch to linuxppc-dev and not the crypto
list ..
I need to understand things better here. Any reason why those drivers
aren't handled by the crypto maintainer ?
Ben.
> ---
> drivers/crypto/nx/nx-aes-cbc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/crypto/nx/nx-aes-cbc.c
> b/drivers/crypto/nx/nx-aes-cbc.c
> index 35d483f..a2f99a9 100644
> --- a/drivers/crypto/nx/nx-aes-cbc.c
> +++ b/drivers/crypto/nx/nx-aes-cbc.c
> @@ -95,6 +95,7 @@ static int cbc_aes_nx_crypt(struct blkcipher_desc
> *desc,
> if (rc)
> goto out;
>
> + memcpy(desc->info, csbcpb->cpb.aes_cbc.cv, AES_BLOCK_SIZE);
> atomic_inc(&(nx_ctx->stats->aes_ops));
> atomic64_add(csbcpb->csb.processed_byte_count,
> &(nx_ctx->stats->aes_bytes));
^ permalink raw reply
* Re: therm_pm72 units, interface
From: Benjamin Herrenschmidt @ 2013-08-02 21:04 UTC (permalink / raw)
To: Ben Hutchings; +Cc: Michel Dänzer, linuxppc-dev, Jan Engelhardt
In-Reply-To: <1375477013.32254.22.camel@deadeye.wl.decadent.org.uk>
On Fri, 2013-08-02 at 22:56 +0200, Ben Hutchings wrote:
> > Yes. Do you have all the windfarm modules loaded ? What about
> > i2c-powermac ? (It's typical that the latter is missed, I think it
> > doesn't auto-load, which we never fixed, we used to request distros
> to
> > just built it in)
>
> We built it as a module in 3.2 and we still do. The regression
> apparently occurred between 3.8 and 3.9.
Interesting. Maybe the old MODULE_ALIAS statement in there no longer
work....
Ben.
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox