* [RFC PATCH 3/4] powerpc: refactor of_get_cpu_node to support other architectures
From: Sudeep KarkadaNagesha @ 2013-08-15 17:09 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-pm, devicetree,
microblaze-uclinux, linux, linuxppc-dev
Cc: Jonas Bonn, Michal Simek, Sudeep KarkadaNagesha, Rob Herring,
Rafael J. Wysocki, Grant Likely
In-Reply-To: <1376586580-5409-1-git-send-email-Sudeep.KarkadaNagesha@arm.com>
From: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Currently different drivers requiring to access cpu device node are
parsing the device tree themselves. Since the ordering in the DT need
not match the logical cpu ordering, the parsing logic needs to consider
that. However, this has resulted in lots of code duplication and in some
cases even incorrect logic.
It's better to consolidate them by adding support for getting cpu
device node for a given logical cpu index in DT core library. However
logical to physical index mapping can be architecture specific.
PowerPC has it's own implementation to get the cpu node for a given
logical index.
This patch refactors the current implementation of of_get_cpu_node.
This in preparation to move the implementation to DT core library.
It separates out the logical to physical mapping so that a default
matching of the physical id to the logical cpu index can be added
when moved to common code. Architecture specific code can override it.
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
---
arch/powerpc/kernel/prom.c | 70 ++++++++++++++++++++++++++++--------------=
----
1 file changed, 43 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index eb23ac9..594c9f9 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -865,45 +865,61 @@ static int __init prom_reconfig_setup(void)
__initcall(prom_reconfig_setup);
#endif
=20
+bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
+{
+=09return (int)phys_id =3D=3D get_hard_smp_processor_id(cpu);
+}
+
+static bool __of_find_n_match_cpu_property(struct device_node *cpun,
+=09=09=09const char *prop_name, int cpu, unsigned int *thread)
+{
+=09const __be32 *cell;
+=09int ac, prop_len, tid;
+=09u64 hwid;
+
+=09ac =3D of_n_addr_cells(cpun);
+=09cell =3D of_get_property(cpun, prop_name, &prop_len);
+=09if (!cell)
+=09=09return false;
+=09prop_len /=3D sizeof(*cell);
+=09for (tid =3D 0; tid < prop_len; tid++) {
+=09=09hwid =3D of_read_number(cell, ac);
+=09=09if (arch_match_cpu_phys_id(cpu, hwid)) {
+=09=09=09if (thread)
+=09=09=09=09*thread =3D tid;
+=09=09=09return true;
+=09=09}
+=09}
+=09return false;
+}
+
/* Find the device node for a given logical cpu number, also returns the c=
pu
* local thread number (index in ibm,interrupt-server#s) if relevant and
* asked for (non NULL)
*/
struct device_node *of_get_cpu_node(int cpu, unsigned int *thread)
{
-=09int hardid;
-=09struct device_node *np;
+=09struct device_node *cpun, *cpus;
=20
-=09hardid =3D get_hard_smp_processor_id(cpu);
+=09cpus =3D of_find_node_by_path("/cpus");
+=09if (!cpus) {
+=09=09pr_warn("Missing cpus node, bailing out\n");
+=09=09return NULL;
+=09}
=20
-=09for_each_node_by_type(np, "cpu") {
-=09=09const u32 *intserv;
-=09=09unsigned int plen, t;
+=09for_each_child_of_node(cpus, cpun) {
+=09=09if (of_node_cmp(cpun->type, "cpu"))
+=09=09=09continue;
=20
=09=09/* Check for ibm,ppc-interrupt-server#s. If it doesn't exist
=09=09 * fallback to "reg" property and assume no threads
=09=09 */
-=09=09intserv =3D of_get_property(np, "ibm,ppc-interrupt-server#s",
-=09=09=09=09&plen);
-=09=09if (intserv =3D=3D NULL) {
-=09=09=09const u32 *reg =3D of_get_property(np, "reg", NULL);
-=09=09=09if (reg =3D=3D NULL)
-=09=09=09=09continue;
-=09=09=09if (*reg =3D=3D hardid) {
-=09=09=09=09if (thread)
-=09=09=09=09=09*thread =3D 0;
-=09=09=09=09return np;
-=09=09=09}
-=09=09} else {
-=09=09=09plen /=3D sizeof(u32);
-=09=09=09for (t =3D 0; t < plen; t++) {
-=09=09=09=09if (hardid =3D=3D intserv[t]) {
-=09=09=09=09=09if (thread)
-=09=09=09=09=09=09*thread =3D t;
-=09=09=09=09=09return np;
-=09=09=09=09}
-=09=09=09}
-=09=09}
+=09=09if (__of_find_n_match_cpu_property(cpun,
+=09=09=09=09"ibm,ppc-interrupt-server#s", cpu, thread))
+=09=09=09return cpun;
+
+=09=09if (__of_find_n_match_cpu_property(cpun, "reg", cpu, thread))
+=09=09=09return cpun;
=09}
=09return NULL;
}
--=20
1.8.1.2
^ permalink raw reply related
* [RFC PATCH 4/4] of: move of_get_cpu_node implementation to DT core library
From: Sudeep KarkadaNagesha @ 2013-08-15 17:09 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-pm, devicetree,
microblaze-uclinux, linux, linuxppc-dev
Cc: Jonas Bonn, Michal Simek, Sudeep KarkadaNagesha, Rob Herring,
Rafael J. Wysocki, Grant Likely
In-Reply-To: <1376586580-5409-1-git-send-email-Sudeep.KarkadaNagesha@arm.com>
From: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
This patch moves the generalized implementation of of_get_cpu_node from
PowerPC to DT core library, thereby adding support for retrieving cpu
node for a given logical cpu index on any architecture.
The CPU subsystem can now use this function to assign of_node in the
cpu device while registering CPUs.
It is recommended to use these helper function only in pre-SMP/early
initialisation stages to retrieve CPU device node pointers in logical
ordering. Once the cpu devices are registered, it can be retrieved easily
from cpu device of_node which avoids unnecessary parsing and matching.
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
---
arch/powerpc/include/asm/prom.h | 3 --
arch/powerpc/kernel/prom.c | 55 ------------------------
drivers/of/base.c | 94 +++++++++++++++++++++++++++++++++++++=
++++
include/linux/cpu.h | 1 +
include/linux/of.h | 7 +++
5 files changed, 102 insertions(+), 58 deletions(-)
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/pro=
m.h
index bc2da15..ac204e0 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -43,9 +43,6 @@ void of_parse_dma_window(struct device_node *dn, const vo=
id *dma_window_prop,
=20
extern void kdump_move_device_tree(void);
=20
-/* CPU OF node matching */
-struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
-
/* cache lookup */
struct device_node *of_find_next_cache_node(struct device_node *np);
=20
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 594c9f9..1c14cd4 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -870,61 +870,6 @@ bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
=09return (int)phys_id =3D=3D get_hard_smp_processor_id(cpu);
}
=20
-static bool __of_find_n_match_cpu_property(struct device_node *cpun,
-=09=09=09const char *prop_name, int cpu, unsigned int *thread)
-{
-=09const __be32 *cell;
-=09int ac, prop_len, tid;
-=09u64 hwid;
-
-=09ac =3D of_n_addr_cells(cpun);
-=09cell =3D of_get_property(cpun, prop_name, &prop_len);
-=09if (!cell)
-=09=09return false;
-=09prop_len /=3D sizeof(*cell);
-=09for (tid =3D 0; tid < prop_len; tid++) {
-=09=09hwid =3D of_read_number(cell, ac);
-=09=09if (arch_match_cpu_phys_id(cpu, hwid)) {
-=09=09=09if (thread)
-=09=09=09=09*thread =3D tid;
-=09=09=09return true;
-=09=09}
-=09}
-=09return false;
-}
-
-/* Find the device node for a given logical cpu number, also returns the c=
pu
- * local thread number (index in ibm,interrupt-server#s) if relevant and
- * asked for (non NULL)
- */
-struct device_node *of_get_cpu_node(int cpu, unsigned int *thread)
-{
-=09struct device_node *cpun, *cpus;
-
-=09cpus =3D of_find_node_by_path("/cpus");
-=09if (!cpus) {
-=09=09pr_warn("Missing cpus node, bailing out\n");
-=09=09return NULL;
-=09}
-
-=09for_each_child_of_node(cpus, cpun) {
-=09=09if (of_node_cmp(cpun->type, "cpu"))
-=09=09=09continue;
-
-=09=09/* Check for ibm,ppc-interrupt-server#s. If it doesn't exist
-=09=09 * fallback to "reg" property and assume no threads
-=09=09 */
-=09=09if (__of_find_n_match_cpu_property(cpun,
-=09=09=09=09"ibm,ppc-interrupt-server#s", cpu, thread))
-=09=09=09return cpun;
-
-=09=09if (__of_find_n_match_cpu_property(cpun, "reg", cpu, thread))
-=09=09=09return cpun;
-=09}
-=09return NULL;
-}
-EXPORT_SYMBOL(of_get_cpu_node);
-
#if defined(CONFIG_DEBUG_FS) && defined(DEBUG)
static struct debugfs_blob_wrapper flat_dt_blob;
=20
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 5c54279..d088e45 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -18,6 +18,7 @@
* 2 of the License, or (at your option) any later version.
*/
#include <linux/ctype.h>
+#include <linux/cpu.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/spinlock.h>
@@ -230,6 +231,99 @@ const void *of_get_property(const struct device_node *=
np, const char *name,
}
EXPORT_SYMBOL(of_get_property);
=20
+/*
+ * arch_match_cpu_phys_id - Match the given logical CPU and physical id
+ *
+ * @cpu: logical index of a cpu
+ * @phys_id: physical identifier of a cpu
+ *
+ * CPU logical to physical index mapping is architecture specific.
+ * However this __weak function provides a default match of physical
+ * id to logical cpu index.
+ *
+ * Returns true if the physical identifier and the logical index correspon=
d
+ * to the same cpu, false otherwise.
+ */
+bool __weak arch_match_cpu_phys_id(int cpu, u64 phys_id)
+{
+=09return (u32)phys_id =3D=3D cpu;
+}
+
+/**
+ * Checks if the given "prop_name" property holds the physical id of the
+ * core/thread corresponding to the logical cpu 'cpu'. If 'thread' is not
+ * NULL, local thread number within the core is returned in it.
+ */
+static bool __of_find_n_match_cpu_property(struct device_node *cpun,
+=09=09=09const char *prop_name, int cpu, unsigned int *thread)
+{
+=09const __be32 *cell;
+=09int ac, prop_len, tid;
+=09u64 hwid;
+
+=09ac =3D of_n_addr_cells(cpun);
+=09cell =3D of_get_property(cpun, prop_name, &prop_len);
+=09if (!cell)
+=09=09return false;
+=09prop_len /=3D sizeof(*cell);
+=09for (tid =3D 0; tid < prop_len; tid++) {
+=09=09hwid =3D of_read_number(cell, ac);
+=09=09if (arch_match_cpu_phys_id(cpu, hwid)) {
+=09=09=09if (thread)
+=09=09=09=09*thread =3D tid;
+=09=09=09return true;
+=09=09}
+=09}
+=09return false;
+}
+
+/**
+ * of_get_cpu_node - Get device node associated with the given logical CPU
+ *
+ * @cpu: CPU number(logical index) for which device node is required
+ * @thread: if not NULL, local thread number within the physical core is
+ * returned
+ *
+ * The main purpose of this function is to retrieve the device node for th=
e
+ * given logical CPU index. It should be used to initialize the of_node in
+ * cpu device. Once of_node in cpu device is populated, all the further
+ * references can use that instead.
+ *
+ * CPU logical to physical index mapping is architecture specific and is b=
uilt
+ * before booting secondary cores. This function uses arch_match_cpu_phys_=
id
+ * which can be overridden by architecture specific implementation.
+ *
+ * Returns a node pointer for the logical cpu if found, else NULL.
+ */
+struct device_node *of_get_cpu_node(int cpu, unsigned int *thread)
+{
+=09struct device_node *cpun, *cpus;
+
+=09cpus =3D of_find_node_by_path("/cpus");
+=09if (!cpus) {
+=09=09pr_warn("Missing cpus node, bailing out\n");
+=09=09return NULL;
+=09}
+
+=09for_each_child_of_node(cpus, cpun) {
+=09=09if (of_node_cmp(cpun->type, "cpu"))
+=09=09=09continue;
+#ifdef CONFIG_PPC
+=09=09/* Check for historical "ibm,ppc-interrupt-server#s" property
+=09=09 * for thread ids on PowerPC. If it doesn't exist fallback to
+=09=09 * standard "reg" property.
+=09=09 */
+=09=09if (__of_find_n_match_cpu_property(cpun,
+=09=09=09=09"ibm,ppc-interrupt-server#s", cpu, thread))
+=09=09=09return cpun;
+#endif
+=09=09if (__of_find_n_match_cpu_property(cpun, "reg", cpu, thread))
+=09=09=09return cpun;
+=09}
+=09return NULL;
+}
+EXPORT_SYMBOL(of_get_cpu_node);
+
/** Checks if the given "compat" string matches one of the strings in
* the device's "compatible" property
*/
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index ab0eade..3dfed2b 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -28,6 +28,7 @@ struct cpu {
extern int register_cpu(struct cpu *cpu, int num);
extern struct device *get_cpu_device(unsigned cpu);
extern bool cpu_is_hotpluggable(unsigned cpu);
+extern bool arch_match_cpu_phys_id(int cpu, u64 phys_id);
=20
extern int cpu_add_dev_attr(struct device_attribute *attr);
extern void cpu_remove_dev_attr(struct device_attribute *attr);
diff --git a/include/linux/of.h b/include/linux/of.h
index 1fd08ca..c0bb2f1 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -266,6 +266,7 @@ extern int of_device_is_available(const struct device_n=
ode *device);
extern const void *of_get_property(const struct device_node *node,
=09=09=09=09const char *name,
=09=09=09=09int *lenp);
+extern struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
#define for_each_property_of_node(dn, pp) \
=09for (pp =3D dn->properties; pp !=3D NULL; pp =3D pp->next)
=20
@@ -459,6 +460,12 @@ static inline const void *of_get_property(const struct=
device_node *node,
=09return NULL;
}
=20
+static inline struct device_node *of_get_cpu_node(int cpu,
+=09=09=09=09=09unsigned int *thread)
+{
+=09return NULL;
+}
+
static inline int of_property_read_u64(const struct device_node *np,
=09=09=09=09 const char *propname, u64 *out_value)
{
--=20
1.8.1.2
^ permalink raw reply related
* [RFC PATCH 1/4] microblaze: remove undefined of_get_cpu_node declaration
From: Sudeep KarkadaNagesha @ 2013-08-15 17:09 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-pm, devicetree,
microblaze-uclinux, linux, linuxppc-dev
Cc: Jonas Bonn, Michal Simek, Sudeep KarkadaNagesha, Rob Herring,
Rafael J. Wysocki, Grant Likely
In-Reply-To: <1376586580-5409-1-git-send-email-Sudeep.KarkadaNagesha@arm.com>
From: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
This patch removes the declaration of the function 'of_get_cpu_node'
which is not defined for microblaze. This is in preparation to move
it's definition from PPC to DT common code.
Michal Simek says: "it was just there because Microblaze
was based on powerpc code"
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Cc: Michal Simek <monstr@monstr.eu>
---
arch/microblaze/include/asm/prom.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/a=
sm/prom.h
index 20c5e8e..9977816 100644
--- a/arch/microblaze/include/asm/prom.h
+++ b/arch/microblaze/include/asm/prom.h
@@ -50,9 +50,6 @@ void of_parse_dma_window(struct device_node *dn, const vo=
id *dma_window_prop,
=20
extern void kdump_move_device_tree(void);
=20
-/* CPU OF node matching */
-struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
-
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
=20
--=20
1.8.1.2
^ permalink raw reply related
* [RFC PATCH 2/4] openrisc: remove undefined of_get_cpu_node declaration
From: Sudeep KarkadaNagesha @ 2013-08-15 17:09 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-pm, devicetree,
microblaze-uclinux, linux, linuxppc-dev
Cc: Jonas Bonn, Michal Simek, Sudeep KarkadaNagesha, Rob Herring,
Rafael J. Wysocki, Grant Likely
In-Reply-To: <1376586580-5409-1-git-send-email-Sudeep.KarkadaNagesha@arm.com>
From: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
This patch removes the declaration of the function 'of_get_cpu_node'
which is not defined for openrisc. This is in preparation to move
it's definition from PPC to DT common code.
Again it could be there as it was originally copied from powerpc.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Cc: Jonas Bonn <jonas@southpole.se>
---
arch/openrisc/include/asm/prom.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/openrisc/include/asm/prom.h b/arch/openrisc/include/asm/p=
rom.h
index bbb34e5..eb59bfe 100644
--- a/arch/openrisc/include/asm/prom.h
+++ b/arch/openrisc/include/asm/prom.h
@@ -44,9 +44,6 @@ void of_parse_dma_window(struct device_node *dn, const vo=
id *dma_window_prop,
=20
extern void kdump_move_device_tree(void);
=20
-/* CPU OF node matching */
-struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
-
/* Get the MAC address */
extern const void *of_get_mac_address(struct device_node *np);
=20
--=20
1.8.1.2
^ permalink raw reply related
* [RFC PATCH 0/4] DT: move of_get_cpu_node from PPC to DT core
From: Sudeep KarkadaNagesha @ 2013-08-15 17:09 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-pm, devicetree,
microblaze-uclinux, linux, linuxppc-dev
Cc: Jonas Bonn, Michal Simek, Sudeep KarkadaNagesha, Rob Herring,
Rafael J. Wysocki, Grant Likely
In-Reply-To: <1374492747-13879-1-git-send-email-Sudeep.KarkadaNagesha@arm.com>
From: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Hi,
This series needs to be prepended with the original series[1][2][3]
Except the first patch in the original series(which is merged into this
as last patch), there is no other change(apart from function signature)
I am posting only this part for feedback separately for review as the
original series is already reviewed. Once this part is review and aknowledg=
ed
I will combine the complete series and post it.
Hi Rob,
Since the compatible 'ibm,ppc-interrupt-server#s' is one-off and for
historical reasons, if future architectures are adhering to ePAPR,
IMO having a weak definition of arch_of_cpu_get_node as you suggested
could lead to it's misuse in future. So I didn't take that approach.
Regards,
Sudeep
Sudeep KarkadaNagesha (4):
microblaze: remove undefined of_get_cpu_node declaration
openrisc: remove undefined of_get_cpu_node declaration
powerpc: refactor of_get_cpu_node to support other architectures
of: move of_get_cpu_node implementation to DT core library
arch/microblaze/include/asm/prom.h | 3 --
arch/openrisc/include/asm/prom.h | 3 --
arch/powerpc/include/asm/prom.h | 3 --
arch/powerpc/kernel/prom.c | 43 +----------------
drivers/of/base.c | 94 ++++++++++++++++++++++++++++++++++=
++++
include/linux/cpu.h | 1 +
include/linux/of.h | 7 +++
7 files changed, 104 insertions(+), 50 deletions(-)
--=20
1.8.1.2
[1] https://lkml.org/lkml/2013/7/15/128
[2] https://lkml.org/lkml/2013/7/17/341
[3] https://lkml.org/lkml/2013/7/22/219
^ permalink raw reply
* [PATCH v2 02/10] ppc/cell: use get_unused_fd_flags(0) instead of get_unused_fd()
From: Yann Droneaud @ 2013-08-15 13:10 UTC (permalink / raw)
To: Jeremy Kerr, Arnd Bergmann, Benjamin Herrenschmidt,
Paul Mackerras
Cc: Yann Droneaud, cbe-oss-dev, linuxppc-dev, linux-kernel
In-Reply-To: <cover.1376327678.git.ydroneaud@opteya.com>
Macro get_unused_fd() is used to allocate a file descriptor with
default flags. Those default flags (0) can be "unsafe":
O_CLOEXEC must be used by default to not leak file descriptor
across exec().
Instead of macro get_unused_fd(), functions anon_inode_getfd()
or get_unused_fd_flags() should be used with flags given by userspace.
If not possible, flags should be set to O_CLOEXEC to provide userspace
with a default safe behavor.
In a further patch, get_unused_fd() will be removed so that
new code start using anon_inode_getfd() or get_unused_fd_flags()
with correct flags.
This patch replaces calls to get_unused_fd() with equivalent call to
get_unused_fd_flags(0) to preserve current behavor for existing code.
The hard coded flag value (0) should be reviewed on a per-subsystem basis,
and, if possible, set to O_CLOEXEC.
Signed-off-by: Yann Droneaud <ydroneaud@opteya.com>
Link: http://lkml.kernel.org/r/cover.1376327678.git.ydroneaud@opteya.com
---
arch/powerpc/platforms/cell/spufs/inode.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index f390042..88df441 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -301,7 +301,7 @@ static int spufs_context_open(struct path *path)
int ret;
struct file *filp;
- ret = get_unused_fd();
+ ret = get_unused_fd_flags(0);
if (ret < 0)
return ret;
@@ -518,7 +518,7 @@ static int spufs_gang_open(struct path *path)
int ret;
struct file *filp;
- ret = get_unused_fd();
+ ret = get_unused_fd_flags(0);
if (ret < 0)
return ret;
--
1.8.3.1
^ permalink raw reply related
* [PATCH v2 00/10] Getting rid of get_unused_fd_flags()
From: Yann Droneaud @ 2013-08-15 13:10 UTC (permalink / raw)
To: Tony Luck, Fenghua Yu, Al Viro, linux-ia64, Jeremy Kerr,
Arnd Bergmann, Benjamin Herrenschmidt, Paul Mackerras,
linuxppc-dev, cbe-oss-dev, Greg Kroah-Hartman, John Stultz,
Erik Gilling, devel, Alex Williamson, kvm, linux-fsdevel,
Eric Paris, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo
Cc: Yann Droneaud, linux-kernel
Hi,
Macro get_unused_fd() is a shortcut to call function get_unused_fd_flags(),
to allocate a file descriptor.
The macro use 0 as flags, so the file descriptor is created
without O_CLOEXEC flag.
This can be seen as an unsafe default eg. in most case O_CLOEXEC
must be used to not leak file descriptor across exec().
Newer kernel code should use anon_inode_getfd() or get_unused_fd_flags()
with flags provided by userspace. If flags cannot be given by userspace,
O_CLOEXEC must be the default flag.
Using O_CLOEXEC by default allows userspace to choose, without race,
if the file descriptor is going to be inherited across exec().
They are two ways to achieve this:
- makes get_unused_fd() use O_CLOEXEC by default
It's difficult to get it right: every code using of get_unused_fd()
must take this change into account and be fixed as soon as
macro get_unused_fd() do the switch. Non updated code will have
unexpected behavor and it's likely going to break API contract.
- remove get_unused_fd()
It's going to break some out of tree, not yet upstream kernel code,
but it's easy to notice and fix. Anyway, newer code should use
anon_inode_getfd() or get_unused_fd_flags().
The latter option was choosen to ensure no unexpected behavor
for out of tree, not yet upstream code. Removing the macro is the safest
choice: it's better to break build than trying to make get_unused_fd()
use O_CLOEXEC by default and get all user of get_unused_fd() update.
Additionnaly, removing the macro is not going to break modules ABI.
In linux-next tag 20130815, they're currently:
- 19 calls to get_unused_fd_flags() (+4)
not counting get_unused_fd() and anon_inode_getfd()
- 10 calls to get_unused_fd() (-4)
- 11 calls to anon_inode_getfd() (0)
The following patchset try to convert all calls to get_unused_fd()
to get_unused_fd_flags(0) before removing get_unused_fd() macro.
Without get_unused_fd() macro, more subsystems are likely to use
anon_inode_getfd() and be teached to provide an API that let userspace
choose the opening flags of the file descriptor.
Changes from v1 <http://lkml.kernel.org/r/cover.1372777600.git.ydroneaud@opteya.com>:
- explicitly added subsystem maintainers as mail recepients.
- infiniband: use get_unused_fd_flags(0) instead of get_unused_fd()
DROPPED: subsystem maintainer applied another patch using
get_unused_fd_flags(O_CLOEXEC) as suggested.
- android/sw_sync: use get_unused_fd_flags(0) instead of get_unused_fd()
MODIFIED: use get_unused_fd_flags(O_CLOEXEC) as suggested by
<http://lkml.kernel.org/r/CACSP8SjXGMk2_kX_+RgzqqQwqKernvF1Wt3K5tw991W5dfAnCA@mail.gmail.com>
- android/sync: use get_unused_fd_flags(0) instead of get_unused_fd()
MODIFIED: use get_unused_fd_flags(O_CLOEXEC) as suggested by
<http://lkml.kernel.org/r/CACSP8SjZcpcpEtQHzcGYhf-MP7QGo0XpN7-uN7rmD=vNtopG=w@mail.gmail.com>
- xfs: use get_unused_fd_flags(0) instead of get_unused_fd()
DROPPED: applied asis by subsystem maintainer.
- sctp: use get_unused_fd_flags(0) instead of get_unused_fd()
DROPPED: applied asis by subsystem maintainer.
Yann Droneaud (10):
ia64: use get_unused_fd_flags(0) instead of get_unused_fd()
ppc/cell: use get_unused_fd_flags(0) instead of get_unused_fd()
android/sw_sync: use get_unused_fd_flags(O_CLOEXEC) instead of
get_unused_fd()
android/sync: use get_unused_fd_flags(O_CLOEXEC) instead of
get_unused_fd()
vfio: use get_unused_fd_flags(0) instead of get_unused_fd()
binfmt_misc: use get_unused_fd_flags(0) instead of get_unused_fd()
file: use get_unused_fd_flags(0) instead of get_unused_fd()
fanotify: use get_unused_fd_flags(0) instead of get_unused_fd()
events: use get_unused_fd_flags(0) instead of get_unused_fd()
file: remove get_unused_fd()
arch/ia64/kernel/perfmon.c | 2 +-
arch/powerpc/platforms/cell/spufs/inode.c | 4 ++--
drivers/staging/android/sw_sync.c | 2 +-
drivers/staging/android/sync.c | 2 +-
drivers/vfio/vfio.c | 2 +-
fs/binfmt_misc.c | 2 +-
fs/file.c | 2 +-
fs/notify/fanotify/fanotify_user.c | 2 +-
include/linux/file.h | 1 -
kernel/events/core.c | 2 +-
10 files changed, 10 insertions(+), 11 deletions(-)
--
1.8.3.1
^ permalink raw reply
* [PATCH v3 2/7] net: ucc_geth: use platform_{get,set}_drvdata()
From: Libo Chen @ 2013-08-15 13:01 UTC (permalink / raw)
To: David Miller, leoli; +Cc: netdev, Li Zefan, linuxppc-dev, Sergei Shtylyov
Use the wrapper functions for getting and setting the driver data using
platform_device instead of using dev_{get,set}_drvdata() with &ofdev->dev,
so we can directly pass a struct platform_device.
Signed-off-by: Libo Chen <libo.chen@huawei.com>
---
drivers/net/ethernet/freescale/ucc_geth.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/freescale/ucc_geth.c b/drivers/net/ethernet/freescale/ucc_geth.c
index 3c43dac..533885c 100644
--- a/drivers/net/ethernet/freescale/ucc_geth.c
+++ b/drivers/net/ethernet/freescale/ucc_geth.c
@@ -3911,8 +3911,7 @@ static int ucc_geth_probe(struct platform_device* ofdev)
static int ucc_geth_remove(struct platform_device* ofdev)
{
- struct device *device = &ofdev->dev;
- struct net_device *dev = dev_get_drvdata(device);
+ struct net_device *dev = platform_get_drvdata(ofdev);
struct ucc_geth_private *ugeth = netdev_priv(dev);
unregister_netdev(dev);
--
1.7.1
^ permalink raw reply related
* [PATCH v3 0/7] net: use platform_{get,set}_drvdata()
From: Libo Chen @ 2013-08-15 13:01 UTC (permalink / raw)
To: David Miller
Cc: Sergei Shtylyov, Greg KH, netdev, jg1.han, Li Zefan, vbordug,
linuxppc-dev
Use the wrapper functions for getting and setting the driver data using
platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev,
so we can directly pass a struct platform_device.
changelog v3:
remove modify about dev_set_drvdata()
changelog v2:
this version add modify record about dev_set_drvdata().
Libo Chen (7):
net: fsl_pq_mdio: use platform_{get,set}_drvdata()
net: ucc_geth: use platform_{get,set}_drvdata()
net: fec_mpc52xx_phy: use platform_{get,set}_drvdata()
net: sunbmac: use platform_{get,set}_drvdata()
net: sunhme: use platform_{get,set}_drvdata()
net: xilinx_emaclite: use platform_{get,set}_drvdata()
net: davinci_mdio: use platform_{get,set}_drvdata()
drivers/net/ethernet/freescale/fec_mpc52xx_phy.c | 3 +--
drivers/net/ethernet/freescale/fsl_pq_mdio.c | 2 +-
drivers/net/ethernet/freescale/ucc_geth.c | 3 +--
drivers/net/ethernet/sun/sunbmac.c | 2 +-
drivers/net/ethernet/sun/sunhme.c | 6 +++---
drivers/net/ethernet/ti/davinci_mdio.c | 3 +--
drivers/net/ethernet/xilinx/xilinx_emaclite.c | 3 +--
7 files changed, 9 insertions(+), 13 deletions(-)
^ permalink raw reply
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
From: Tomasz Figa @ 2013-08-15 12:18 UTC (permalink / raw)
To: Nicolin Chen, ian.campbell, pawel.moll, galak
Cc: mark.rutland, devicetree, alsa-devel, lars, swarren, festevam,
s.hauer, timur, rob.herring, broonie, p.zabel, shawn.guo,
linuxppc-dev
In-Reply-To: <4eb991fafc171305ebc71847fecb7bdae0ede927.1376565456.git.b42378@freescale.com>
[-- Attachment #1: Type: text/plain, Size: 56452 bytes --]
Hi Nicolin,
[Ccing DT bindings maintainers]
On Thursday 15 of August 2013 19:26:39 Nicolin Chen wrote:
> This patch add S/PDIF controller driver for Freescale SoC.
>
> Signed-off-by: Nicolin Chen <b42378@freescale.com>
> ---
> .../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
> sound/soc/fsl/Kconfig | 3 +
> sound/soc/fsl/Makefile | 2 +
> sound/soc/fsl/fsl_spdif.c | 1336
> ++++++++++++++++++++ sound/soc/fsl/fsl_spdif.h
> | 224 ++++ 5 files changed, 1641 insertions(+), 0 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/sound/fsl,spdif.txt create mode
> 100644 sound/soc/fsl/fsl_spdif.c
> create mode 100644 sound/soc/fsl/fsl_spdif.h
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> b/Documentation/devicetree/bindings/sound/fsl,spdif.txt new file mode
> 100644
> index 0000000..301b827
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> @@ -0,0 +1,76 @@
> +Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
> +
> +The Freescale S/PDIF audio block is a stereo transceiver that allows
> the +processor to receive and transmit digital audio via an coaxial
> cable or +a fibre cable.
> +
> +Required properties:
> +
> + - compatible : Compatible list, contains "fsl,<chip>-spdif".
> +
> + - reg : Offset and length of the register set for the device.
> +
> + - interrupts : Contains spdif interrupt.
> +
> + - dmas : Generic dma devicetree binding as described in
> + Documentation/devicetree/bindings/dma/dma.txt.
> +
> + - dma-names : Two dmas have to be defined, "tx" and "rx".
> +
> + - clocks : Contains an entry for each entry in clock-names.
> +
> + - clock-names : Includes the following entries:
> + name type comments
> + "core" Required The core clock of spdif controller
> +
> + "rx" Optional Rx clock source for spdif record.
> + If absent, will use core clock.
> +
> + "tx" Optional Tx clock source for spdif playback.
> + If absent, will use core clock.
> +
> + "tx-32000" Optional Tx clock source for 32000Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "tx-44100" Optional Tx clock source for 44100Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "tx-48000" Optional Tx clock source for 48000Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "src<0-7>" Optional Clock source list for tx and rx clock
> + to look up their clock source indexes.
> + This clock list should be identical to
> + the list of TxClk_Source bit value of
> + register SPDIF_STC. If absent or failed
> + to look up, tx and rx clock would then
> + ignore the "rx", "tx" "tx-32000",
> + "tx-44100", "tx-48000" clock phandles
> + and select the core clock as default
> + tx and rx clock.
I suspect a little abuse of clocks property here. From the description of
"core" and "src<0-7>" clocks I assume that the IP can have up to 9 clock
inputs - core clock and up to 8 extra source clocks. Is it correct?
If yes, this makes the "tx", "rx" and "tx-*" clocks describe
configuration, not hardware. IMHO it should be up to the driver which
source clocks to use for tx and rx channels and for each sampling rate.
> +Optional properties:
> +
> + - rx-clksrc-lock: This is a boolean property. If present, ClkSrc_Sel
> bit + of SPDIF_SRPC would be set a clock source that cares DPLL locked
> condition. +
This again looks like software configuration, not hardware description.
Could you elaborate a bit more on meaning of this property?
> +Example:
> +
> +spdif: spdif@02004000 {
> + compatible = "fsl,imx6q-spdif",
> + "fsl,imx35-spdif";
> + reg = <0x02004000 0x4000>;
> + interrupts = <0 52 0x04>;
> + dmas = <&sdma 14 18 0>,
> + <&sdma 15 18 0>;
> + dma-names = "rx", "tx";
> +
> + clocks = <&clks 197>, <&clks 3>, <&clks 197>,
> + <&clks 107>, <&clks 118>, <&clks 62>,
> + <&clks 139>;
> + clock-names = "core", "src0", "src1", "src2",
> + "src4", "src5", "src6";
> + rx-clksrc-lock;
> +
> + status = "okay";
> +};
> diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
> index e15f771..2c518db 100644
> --- a/sound/soc/fsl/Kconfig
> +++ b/sound/soc/fsl/Kconfig
> @@ -1,6 +1,9 @@
> config SND_SOC_FSL_SSI
> tristate
>
> +config SND_SOC_FSL_SPDIF
> + tristate
> +
> config SND_SOC_FSL_UTILS
> tristate
>
> diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
> index d4b4aa8..4b5970e 100644
> --- a/sound/soc/fsl/Makefile
> +++ b/sound/soc/fsl/Makefile
> @@ -12,9 +12,11 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) +=
> snd-soc-p1022-rdk.o
>
> # Freescale PowerPC SSI/DMA Platform Support
> snd-soc-fsl-ssi-objs := fsl_ssi.o
> +snd-soc-fsl-spdif-objs := fsl_spdif.o
> snd-soc-fsl-utils-objs := fsl_utils.o
> snd-soc-fsl-dma-objs := fsl_dma.o
> obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
> +obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
> obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
> obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
>
> diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
> new file mode 100644
> index 0000000..173d699
> --- /dev/null
> +++ b/sound/soc/fsl/fsl_spdif.c
> @@ -0,0 +1,1336 @@
> +/*
> + * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * Based on stmp3xxx_spdif_dai.c
> + * Vladimir Barinov <vbarinov@embeddedalley.com>
> + * Copyright 2008 SigmaTel, Inc
> + * Copyright 2008 Embedded Alley Solutions, Inc
> + *
> + * This file is licensed under the terms of the GNU General Public
> License + * version 2. This program is licensed "as is" without any
> warranty of any + * kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/clk-private.h>
> +#include <linux/regmap.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +
> +#include <sound/asoundef.h>
> +#include <sound/soc.h>
> +#include <sound/dmaengine_pcm.h>
> +
> +#include "fsl_spdif.h"
> +#include "imx-pcm.h"
> +
> +#define FSL_SPDIF_TXFIFO_WML 0x8
> +#define FSL_SPDIF_RXFIFO_WML 0x8
> +
> +#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
> +#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |
> INT_URX_OV|\ + INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
> + INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
> +
> +/* Index list for the values that has if (DPLL Locked) in ClkSrc_Sel
> bit of SRPC */ +static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3,
> 0x4, 0xa, 0xb, }; +#define SRPC_NODPLL_START1 0x5
> +#define SRPC_NODPLL_START2 0xc
> +
> +/*
> + * SPDIF control structure
> + * Defines channel status, subcode and Q sub
> + */
> +struct spdif_mixer_control {
> + /* spinlock to access control data */
> + spinlock_t ctl_lock;
> +
> + /* IEC958 channel tx status bit */
> + unsigned char ch_status[4];
> +
> + /* User bits */
> + unsigned char subcode[2 * SPDIF_UBITS_SIZE];
> +
> + /* Q subcode part of user bits */
> + unsigned char qsub[2 * SPDIF_QSUB_SIZE];
> +
> + /* buffer ptrs for writer */
> + u32 upos;
> + u32 qpos;
> +
> + /* ready buffer index of the two buffers */
> + u32 ready_buf;
> +};
> +
> +struct fsl_spdif_priv {
> + struct spdif_mixer_control fsl_spdif_control;
> + struct snd_soc_dai_driver cpu_dai_drv;
> + struct platform_device *pdev;
> + struct regmap *regmap;
> + atomic_t dpll_locked;
> + u32 irq;
> + s8 rxclk_src;
> + s8 txclk_src[SPDIF_TXRATE_MAX];
> + u8 txclk_div[SPDIF_TXRATE_MAX];
> + struct clk *txclk[SPDIF_TXRATE_MAX];
> + struct clk *txclk_main;
> + struct clk *rxclk;
> + struct clk *coreclk;
> + struct snd_dmaengine_dai_dma_data dma_params_tx;
> + struct snd_dmaengine_dai_dma_data dma_params_rx;
> +
> + /* The name space will be allocated dynamically */
> + char name[0];
> +};
> +
> +
> +#ifdef DEBUG
> +static void dumpregs(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 val, i;
> + int ret;
> +
> + /* Valid address set of SPDIF is {[0x0-0x38], 0x44, 0x50} */
> + for (i = 0 ; i <= REG_SPDIF_STC; i += 4) {
> + ret = regmap_read(regmap, REG_SPDIF_SCR + i, &val);
> + if (!ret)
> + dev_dbg(&pdev->dev, "REG 0x%02x = 0x%06x\n", i, val);
> + }
> +}
> +#else
> +static void dumpregs(struct fsl_spdif_priv *spdif_priv) {}
> +#endif
> +
> +
> +/* DPLL locked and lock loss interrupt handler */
> +static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 locked;
> +
> + regmap_read(regmap, REG_SPDIF_SRPC, &locked);
> + locked &= SRPC_DPLL_LOCKED;
> +
> + dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
> + locked ? "locked" : "loss lock");
> +
> + atomic_set(&spdif_priv->dpll_locked, locked ? 1 : 0);
> +}
> +
> +/* Receiver found illegal symbol interrupt handler */
> +static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> +
> + dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
> +
> + if (!atomic_read(&spdif_priv->dpll_locked)) {
> + /* dpll unlocked seems no audio stream */
> + regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
> + }
> +}
> +
> +/* U/Q Channel receive register full */
> +static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char
> name) +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 *pos, size, val, reg;
> +
> + switch (name) {
> + case 'U':
> + pos = &ctrl->upos;
> + size = SPDIF_UBITS_SIZE;
> + reg = REG_SPDIF_SRU;
> + break;
> + case 'Q':
> + pos = &ctrl->qpos;
> + size = SPDIF_QSUB_SIZE;
> + reg = REG_SPDIF_SRQ;
> + break;
> + default:
> + return;
> + }
> +
> + dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
> +
> + if (*pos >= size * 2) {
> + *pos = 0;
> + } else if (unlikely((*pos % size) + 3 > size)) {
> + dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
> + return;
> + }
> +
> + regmap_read(regmap, reg, &val);
> + ctrl->subcode[*pos++] = val >> 16;
> + ctrl->subcode[*pos++] = val >> 8;
> + ctrl->subcode[*pos++] = val;
> +}
> +
> +/* U/Q Channel sync found */
> +static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct platform_device *pdev = spdif_priv->pdev;
> +
> + dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
> +
> + /* U/Q buffer reset */
> + if (ctrl->qpos == 0)
> + return;
> +
> + /* set ready to this buffer */
> + ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
> +}
> +
> +/* U/Q Channel framing error */
> +static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 val;
> +
> + dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
> +
> + /* read U/Q data and do buffer reset */
> + regmap_read(regmap, REG_SPDIF_SRU, &val);
> + regmap_read(regmap, REG_SPDIF_SRQ, &val);
> +
> + /* drop this U/Q buffer */
> + ctrl->ready_buf = 0;
> + ctrl->upos = 0;
> + ctrl->qpos = 0;
> +}
> +
> +/* Get spdif interrupt status and clear the interrupt */
> +static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val, val2;
> +
> + regmap_read(regmap, REG_SPDIF_SIS, &val);
> + regmap_read(regmap, REG_SPDIF_SIE, &val2);
> +
> + regmap_write(regmap, REG_SPDIF_SIC, val & val2);
> +
> + return val;
> +}
> +
> +static irqreturn_t spdif_isr(int irq, void *devid)
> +{
> + struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 sis;
> +
> + sis = spdif_intr_status_clear(spdif_priv);
> +
> + if (sis & INT_DPLL_LOCKED)
> + spdif_irq_dpll_lock(spdif_priv);
> +
> + if (sis & INT_TXFIFO_UNOV)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
> +
> + if (sis & INT_TXFIFO_RESYNC)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
> +
> + if (sis & INT_CNEW)
> + dev_dbg(&pdev->dev, "isr: cstatus new\n");
> +
> + if (sis & INT_VAL_NOGOOD)
> + dev_dbg(&pdev->dev, "isr: validity flag no good\n");
> +
> + if (sis & INT_SYM_ERR)
> + spdif_irq_sym_error(spdif_priv);
> +
> + if (sis & INT_BIT_ERR)
> + dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
> +
> + if (sis & INT_URX_FUL)
> + spdif_irq_uqrx_full(spdif_priv, 'U');
> +
> + if (sis & INT_URX_OV)
> + dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
> +
> + if (sis & INT_QRX_FUL)
> + spdif_irq_uqrx_full(spdif_priv, 'Q');
> +
> + if (sis & INT_QRX_OV)
> + dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
> +
> + if (sis & INT_UQ_SYNC)
> + spdif_irq_uq_sync(spdif_priv);
> +
> + if (sis & INT_UQ_ERR)
> + spdif_irq_uq_err(spdif_priv);
> +
> + if (sis & INT_RXFIFO_UNOV)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
> +
> + if (sis & INT_RXFIFO_RESYNC)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
> +
> + if (sis & INT_LOSS_LOCK)
> + spdif_irq_dpll_lock(spdif_priv);
> +
> + /* FIXME: Write Tx FIFO to clear TxEm */
> + if (sis & INT_TX_EM)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
> +
> + /* FIXME: Read Rx FIFO to clear RxFIFOFul */
> + if (sis & INT_RXFIFO_FUL)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void spdif_softreset(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val, cycle = 1000;
> +
> + regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
> + regcache_sync(regmap);
> +
> + /* RESET bit would be cleared after finishing its reset procedure */
> + do {
> + regmap_read(regmap, REG_SPDIF_SCR, &val);
> + } while ((val & SCR_SOFT_RESET) && cycle--);
> +}
> +
> +static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
> + u8 mask, u8 cstatus)
> +{
> + ctrl->ch_status[3] &= ~mask;
> + ctrl->ch_status[3] |= cstatus & mask;
> +}
> +
> +static u8 reverse_bits(u8 input)
> +{
> + u8 tmp = input;
> +
> + tmp = ((tmp & 0b10101010) >> 1) | ((tmp << 1) & 0b10101010);
> + tmp = ((tmp & 0b11001100) >> 2) | ((tmp << 2) & 0b11001100);
> + tmp = ((tmp & 0b11110000) >> 4) | ((tmp << 4) & 0b11110000);
> +
> + return tmp;
> +}
> +
> +static void spdif_write_channel_status(struct fsl_spdif_priv
> *spdif_priv) +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 ch_status;
> +
> + ch_status = (reverse_bits(ctrl->ch_status[0]) << 16) |
> + (reverse_bits(ctrl->ch_status[1]) << 8) |
> + reverse_bits(ctrl->ch_status[2]);
> + regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
> +
> + dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
> +
> + ch_status = reverse_bits(ctrl->ch_status[3]) << 16;
> + regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
> +
> + dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
> +}
> +
> +/* Set SPDIF PhaseConfig register for rx clock */
> +static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
> + enum spdif_gainsel gainsel, int dpll_locked)
> +{
> + enum spdif_rxclk_src clksrc = spdif_priv->rxclk_src;
> + struct regmap *regmap = spdif_priv->regmap;
> +
> + if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
> + return -EINVAL;
> +
> + regmap_update_bits(regmap, REG_SPDIF_SRPC,
> + SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
> + SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
> +
> + return 0;
> +}
> +
> +static int spdif_clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> + unsigned long rate_actual;
> +
> + rate_actual = clk_round_rate(clk, rate);
> + clk_set_rate(clk, rate_actual);
> +
> + return 0;
> +}
> +
> +static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
> + int sample_rate)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct spdif_mixer_control
> *ctrl = &spdif_priv->fsl_spdif_control; + struct regmap *regmap =
> spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + unsigned long clk = -1, div = 1, csfs = 0;
> + u32 stc, mask, rate;
> +
> + switch (sample_rate) {
> + case 32000:
> + rate = SPDIF_TXRATE_32000;
> + csfs = IEC958_AES3_CON_FS_32000;
> + break;
> + case 44100:
> + rate = SPDIF_TXRATE_44100;
> + csfs = IEC958_AES3_CON_FS_44100;
> + break;
> + case 48000:
> + rate = SPDIF_TXRATE_48000;
> + csfs = IEC958_AES3_CON_FS_48000;
> + break;
> + default:
> + dev_err(&pdev->dev, "unsupported samplerate %d\n", sample_rate);
> + return -EINVAL;
> + }
> +
> + clk = spdif_priv->txclk_src[rate];
> + if (clk < 0) {
> + dev_err(&pdev->dev, "no defined %d clk src\n", sample_rate);
> + return -EINVAL;
> + }
> +
> + div = spdif_priv->txclk_div[rate];
> + if (div == 0) {
> + dev_err(&pdev->dev, "tx clock source is dividing by zero\n");
> + return -EINVAL;
> + }
> + /*
> + * The S/PDIF block needs a clock of 64 * fs * div. The S/PDIF block
> + * will divide by (div). So request 64 * fs * (div+1) which will
> + * get rounded.
> + */
> + spdif_clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (div +
> 1)); +
> + dev_dbg(&pdev->dev, "expected clock rate = %d\n",
> + (int)(64 * sample_rate * div));
> + dev_dbg(&pdev->dev, "acutal clock rate = %d\n",
> + (int)clk_get_rate(spdif_priv->txclk[rate]));
> +
> + /* set fs field in consumer channel status */
> + spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
> +
> + /* select clock source and divisor */
> + stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DIV(div);
> + mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
> STC_TXCLK_DIV_MASK; + regmap_update_bits(regmap, REG_SPDIF_STC, mask,
> stc);
> +
> + dev_dbg(&pdev->dev, "set sample rate to %d\n", sample_rate);
> +
> + return 0;
> +}
> +
> +int fsl_spdif_startup(struct snd_pcm_substream *substream,
> + struct snd_soc_dai *cpu_dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + u32 scr, mask, i;
> +
> + /* Reset module and interrupts only for first initialization */
> + if (!cpu_dai->active) {
> + spdif_softreset(spdif_priv);
> +
> + /* disable all the interrupts */
> + regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
> + }
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
> + SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
> + SCR_TXFIFO_FSEL_IF8;
> + mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
> + SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
> + SCR_TXFIFO_FSEL_MASK;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_enable(spdif_priv->txclk[i]);
> + } else {
> + scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
> + mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
> + SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
> + clk_enable(spdif_priv->rxclk);
> + }
> + regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
> +
> + /* Power up SPDIF module */
> + regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
> +
> + return 0;
> +}
> +
> +static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
> + struct snd_soc_dai *cpu_dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + u32 scr, mask, i;
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + scr = 0;
> + mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
> + SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
> + SCR_TXFIFO_FSEL_MASK;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_disable(spdif_priv->txclk[i]);
> + } else {
> + scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
> + mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
> + SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
> + clk_disable(spdif_priv->rxclk);
> + }
> + regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
> +
> + /* Power down SPDIF module only if tx&rx are both inactive */
> + if (!cpu_dai->active) {
> + spdif_intr_status_clear(spdif_priv);
> + regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER,
> SCR_LOW_POWER); + }
> +}
> +
> +static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
> + struct snd_pcm_hw_params *params,
> + struct snd_soc_dai *dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct spdif_mixer_control
> *ctrl = &spdif_priv->fsl_spdif_control; + struct platform_device *pdev
> = spdif_priv->pdev;
> + u32 sample_rate = params_rate(params);
> + int ret = 0;
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + ret = spdif_set_sample_rate(substream, sample_rate);
> + if (ret) {
> + dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
> + __func__, sample_rate);
> + return ret;
> + }
> + spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
> + IEC958_AES3_CON_CLOCK_1000PPM);
> + spdif_write_channel_status(spdif_priv);
> + } else {
> + /* setup rx clock source */
> + ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
> + }
> +
> + return ret;
> +}
> +
> +static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
> + int cmd, struct snd_soc_dai *dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + int is_playack = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
> + u32 intr = is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE;
> + u32 dmaen = is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;;
> +
> + switch (cmd) {
> + case SNDRV_PCM_TRIGGER_START:
> + case SNDRV_PCM_TRIGGER_RESUME:
> + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
> + regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
> + regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
> + dumpregs(spdif_priv);
> + break;
> + case SNDRV_PCM_TRIGGER_STOP:
> + case SNDRV_PCM_TRIGGER_SUSPEND:
> + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
> + regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
> + regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +struct snd_soc_dai_ops fsl_spdif_dai_ops = {
> + .startup = fsl_spdif_startup,
> + .hw_params = fsl_spdif_hw_params,
> + .trigger = fsl_spdif_trigger,
> + .shutdown = fsl_spdif_shutdown,
> +};
> +
> +
> +/*
> + * ============================================
> + * FSL SPDIF IEC958 controller(mixer) functions
> + *
> + * Channel status get/put control
> + * User bit value get/put control
> + * Valid bit value get control
> + * DPLL lock status get control
> + * User bit sync mode selection control
> + * ============================================
> + */
> +
> +static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
> + uinfo->count = 1;
> +
> + return 0;
> +}
> +
> +static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *uvalue)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> +
> + uvalue->value.iec958.status[0] = ctrl->ch_status[0];
> + uvalue->value.iec958.status[1] = ctrl->ch_status[1];
> + uvalue->value.iec958.status[2] = ctrl->ch_status[2];
> + uvalue->value.iec958.status[3] = ctrl->ch_status[3];
> +
> + return 0;
> +}
> +
> +static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *uvalue)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> +
> + ctrl->ch_status[0] = uvalue->value.iec958.status[0];
> + ctrl->ch_status[1] = uvalue->value.iec958.status[1];
> + ctrl->ch_status[2] = uvalue->value.iec958.status[2];
> + ctrl->ch_status[3] = uvalue->value.iec958.status[3];
> +
> + spdif_write_channel_status(spdif_priv);
> +
> + return 0;
> +}
> +
> +/* Get channel status from SPDIF_RX_CCHAN register */
> +static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 cstatus, val;
> +
> + regmap_read(regmap, REG_SPDIF_SIS, &val);
> + if (!(val & INT_CNEW)) {
> + return -EAGAIN;
> + }
> +
> + regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
> + ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
> + ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
> + ucontrol->value.iec958.status[2] = cstatus & 0xFF;
> +
> + regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
> + ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
> + ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
> + ucontrol->value.iec958.status[5] = cstatus & 0xFF;
> +
> + /* clear intr */
> + regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
> +
> + return 0;
> +}
> +
> +/*
> + * Get User bits (subcode) from chip value which readed out
> + * in UChannel register.
> + */
> +static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&ctrl->ctl_lock, flags);
> + if (ctrl->ready_buf) {
> + int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
> + memcpy(&ucontrol->value.iec958.subcode[0],
> + &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
> + } else {
> + ret = -EAGAIN;
> + }
> + spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
> +
> + return ret;
> +}
> +
> +/* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
> +static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
> + uinfo->count = SPDIF_QSUB_SIZE;
> +
> + return 0;
> +}
> +
> +/* Get Q subcode from chip value which readed out in QChannel register
> */ +static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&ctrl->ctl_lock, flags);
> + if (ctrl->ready_buf) {
> + int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
> + memcpy(&ucontrol->value.bytes.data[0],
> + &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
> + } else {
> + ret = -EAGAIN;
> + }
> + spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
> +
> + return ret;
> +}
> +
> +/* Valid bit infomation */
> +static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 0;
> + uinfo->value.integer.max = 1;
> +
> + return 0;
> +}
> +
> +/* Get valid good bit from interrupt status register */
> +static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val;
> +
> + val = regmap_read(regmap, REG_SPDIF_SIS, &val);
> + ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
> + regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
> +
> + return 0;
> +}
> +
> +/* DPLL lock infomation */
> +static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 16000;
> + uinfo->value.integer.max = 96000;
> +
> + return 0;
> +}
> +
> +static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
> + 24, 16, 12, 8, 6, 4, 3,
> +};
> +
> +/* Get RX data clock rate given the SPDIF bus_clk */
> +static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
> + enum spdif_gainsel gainsel)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u64 tmpval64, busclk_freq = 0;
> + u32 freqmeas, phaseconf;
> + enum spdif_rxclk_src clksrc;
> +
> + regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
> + regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
> +
> + clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
> + if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) {
> + /* get bus clock from system */
> + busclk_freq = clk_get_rate(spdif_priv->rxclk);
> + }
> +
> + /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
> + tmpval64 = (u64) busclk_freq * freqmeas;
> + do_div(tmpval64, gainsel_multi[gainsel] * 1024);
> + do_div(tmpval64, 128 * 1024);
> +
> + dev_dbg(&pdev->dev, "FreqMeas: %d\n", (int)freqmeas);
> + dev_dbg(&pdev->dev, "BusclkFreq: %d\n", (int)busclk_freq);
> + dev_dbg(&pdev->dev, "RxRate: %d\n", (int)tmpval64);
> +
> + return (int)tmpval64;
> +}
> +
> +/*
> + * Get DPLL lock or not info from stable interrupt status register.
> + * User application must use this control to get locked,
> + * then can do next PCM operation
> + */
> +static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + int rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
> +
> + if (atomic_read(&spdif_priv->dpll_locked))
> + ucontrol->value.integer.value[0] = rate;
> + else
> + ucontrol->value.integer.value[0] = 0;
> +
> + return 0;
> +}
> +
> +/* User bit sync mode info */
> +static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 0;
> + uinfo->value.integer.max = 1;
> +
> + return 0;
> +}
> +
> +/*
> + * User bit sync mode:
> + * 1 CD User channel subcode
> + * 0 Non-CD data
> + */
> +static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val;
> +
> + regmap_read(regmap, REG_SPDIF_SRCD, &val);
> + ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
> +
> + return 0;
> +}
> +
> +/*
> + * User bit sync mode:
> + * 1 CD User channel subcode
> + * 0 Non-CD data
> + */
> +static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
> +
> + regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
> +
> + return 0;
> +}
> +
> +/* FSL SPDIF IEC958 controller defines */
> +static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
> + /* status cchanel controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
> + .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_WRITE |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_pb_get,
> + .put = fsl_spdif_pb_put,
> + },
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_capture_get,
> + },
> + /* user bits controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 Subcode Capture Default",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_subcode_get,
> + },
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 Q-subcode Capture Default",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_qinfo,
> + .get = fsl_spdif_qget,
> + },
> + /* valid bit error controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 V-Bit Errors",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_vbit_info,
> + .get = fsl_spdif_vbit_get,
> + },
> + /* DPLL lock info get controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "RX Sample Rate",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_rxrate_info,
> + .get = fsl_spdif_rxrate_get,
> + },
> + /* User bit sync mode set/get controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 USyncMode CDText",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_WRITE |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_usync_info,
> + .get = fsl_spdif_usync_get,
> + .put = fsl_spdif_usync_put,
> + },
> +};
> +
> +static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
> +{
> + struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
> +
> + dai->playback_dma_data = &spdif_private->dma_params_tx;
> + dai->capture_dma_data = &spdif_private->dma_params_rx;
> +
> + snd_soc_add_dai_controls(dai, fsl_spdif_ctrls,
> ARRAY_SIZE(fsl_spdif_ctrls)); +
> + return 0;
> +}
> +
> +struct snd_soc_dai_driver fsl_spdif_dai = {
> + .probe = &fsl_spdif_dai_probe,
> + .playback = {
> + .channels_min = 2,
> + .channels_max = 2,
> + .rates = FSL_SPDIF_RATES_PLAYBACK,
> + .formats = FSL_SPDIF_FORMATS_PLAYBACK,
> + },
> + .capture = {
> + .channels_min = 2,
> + .channels_max = 2,
> + .rates = FSL_SPDIF_RATES_CAPTURE,
> + .formats = FSL_SPDIF_FORMATS_CAPTURE,
> + },
> + .ops = &fsl_spdif_dai_ops,
> +};
> +
> +static const struct snd_soc_component_driver fsl_spdif_component = {
> + .name = "fsl-spdif",
> +};
> +
> +/*
> + * ================
> + * FSL SPDIF REGMAP
> + * ================
> + */
> +
> +static bool fsl_spdif_readable_reg(struct device *dev, unsigned int
> reg) +{
> + switch (reg) {
> + case REG_SPDIF_SCR:
> + case REG_SPDIF_SRCD:
> + case REG_SPDIF_SRPC:
> + case REG_SPDIF_SIE:
> + case REG_SPDIF_SIS:
> + case REG_SPDIF_SRL:
> + case REG_SPDIF_SRR:
> + case REG_SPDIF_SRCSH:
> + case REG_SPDIF_SRCSL:
> + case REG_SPDIF_SRU:
> + case REG_SPDIF_SRQ:
> + case REG_SPDIF_STCSCH:
> + case REG_SPDIF_STCSCL:
> + case REG_SPDIF_SRFM:
> + case REG_SPDIF_STC:
> + return true;
> + default:
> + return false;
> + };
> +}
> +
> +static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int
> reg) +{
> + switch (reg) {
> + case REG_SPDIF_SCR:
> + case REG_SPDIF_SRCD:
> + case REG_SPDIF_SRPC:
> + case REG_SPDIF_SIE:
> + case REG_SPDIF_SIC:
> + case REG_SPDIF_STL:
> + case REG_SPDIF_STR:
> + case REG_SPDIF_STCSCH:
> + case REG_SPDIF_STCSCL:
> + case REG_SPDIF_STC:
> + return true;
> + default:
> + return false;
> + };
> +}
> +
> +static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int
> reg) +{
> + /* Sync all registers after reset */
> + return true;
> +}
> +
> +static const struct regmap_config fsl_spdif_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> +
> + .max_register = REG_SPDIF_STC,
> + .readable_reg = fsl_spdif_readable_reg,
> + .writeable_reg = fsl_spdif_writeable_reg,
> + .volatile_reg = fsl_spdif_volatile_reg,
> + .cache_type = REGCACHE_RBTREE,
> +};
> +
> +static void spdif_clksrc_index_lookup(struct fsl_spdif_priv
> *spdif_priv) +{
> + const char *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
> + struct platform_device *pdev = spdif_priv->pdev;
> + struct device_node *np = pdev->dev.of_node;
> + struct clk *tmpclk;
> + char tmp[16];
> + int i, j;
> +
> + /* Start to decide tx/rxclk_src index */
> + spdif_priv->rxclk_src = -1;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + spdif_priv->txclk_src[i] = -1;
> +
> + /* Look up the clock source list to find the clock source index */
> + for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> + sprintf(tmp, "src%d", i);
> + tmpclk = devm_clk_get(&pdev->dev, tmp);
> + if (IS_ERR(tmpclk))
> + continue;
> +
> + /* Catch the clksrc identical to configured rxclk */
> + if (tmpclk == spdif_priv->rxclk)
> + spdif_priv->rxclk_src = i;
> +
> + for (j = 0; j < SPDIF_TXRATE_MAX; j++) {
> + /* Catch the clksrc identical to configured txclk */
> + if (tmpclk == spdif_priv->txclk[j])
> + spdif_priv->txclk_src[j] = i;
> + }
> + }
> +
> + /* Plan B when failed to find the index for rx clock source */
> + if (spdif_priv->rxclk_src == -1) {
> + dev_warn(&pdev->dev, "force to use core clock as rx clock.\n");
> + spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
> + spdif_priv->rxclk = spdif_priv->coreclk;
> + }
> +
> + /* Plan B when failed to find the index for tx clock source */
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
> + if (spdif_priv->txclk_src[i] != -1)
> + continue;
> + dev_warn(&pdev->dev, "force to use core clock as %s clock.\n",
> rate[i]); + spdif_priv->txclk_src[i] = DEFAULT_TXCLK_SRC;
> + spdif_priv->txclk[i] = spdif_priv->coreclk;
> + }
> +
> + if (i > SRPC_NODPLL_START1) {
> + /* Drop src5 for rxclk src */
> + spdif_priv->rxclk_src -= 1;
> +
> + /* Restore the offset to higher rxclk src */
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
> + }
> +
> + /* Use the un-conditioned conf for rx clock if no rx-clksrc-lock */
> + if (!of_property_read_bool(np, "rx-clksrc-lock")) {
> + if (i < SRPC_NODPLL_START1)
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
> + else if (i < SRPC_NODPLL_START2)
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET2;
> + }
> +}
> +
> +static void spdif_clk_cal_txdiv(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct platform_device *pdev = spdif_priv->pdev;
> + struct clk **clk = spdif_priv->txclk;
> + u64 rate_ideal, rate_actual, sub, savesub;
> + u32 i, div, arate, rate[] = { 32000, 44100, 48000, };
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++, savesub = 100000) {
> + for (div = 1; div <= 128; div++) {
> + rate_ideal = rate[i] * (div + 1) * 64;
> + rate_actual = clk_round_rate(clk[i], rate_ideal);
> +
> + arate = rate_actual / 64;
> + arate /= div;
> + if (arate == rate[i]) {
> + savesub = 0;
> + spdif_priv->txclk_div[i] = div;
> + break;
> + } else if (arate / rate[i] == 1) {
> + sub = (arate - rate[i]) * 100000;
> + do_div(sub, rate[i]);
> + if (sub < savesub) {
> + savesub = sub;
> + spdif_priv->txclk_div[i] = div;
> + }
> + } else if (rate[i] / arate == 1) {
> + sub = (rate[i] - arate) * 100000;
> + do_div(sub, rate[i]);
> + if (sub < savesub) {
> + savesub = sub;
> + spdif_priv->txclk_div[i] = div;
> + }
> + }
> + }
> + dev_dbg(&pdev->dev, "calculated %dHz div: %d\n",
> + rate[i], spdif_priv->txclk_div[i]);
> + }
> +}
> +
> +static int fsl_spdif_probe(struct platform_device *pdev)
> +{
> + const char *p, *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
> + struct fsl_spdif_priv *spdif_priv;
> + struct spdif_mixer_control *ctrl;
> + struct device_node *np = pdev->dev.of_node;
> + struct resource res;
> + void __iomem *regs;
> + int ret = 0, i;
> +
> + if (!of_device_is_available(np))
> + return -ENODEV;
I'm not sure your probe function will be ever called if the device is
unavailable. A simple check for !np would be enough.
> + /* The DAI name is the last part of the full name of the node. */
This has not been mentioned in binding documentation and I'm not sure this
is correct.
> + p = strrchr(np->full_name, '/') + 1;
You should be able to use np->name directly.
> + spdif_priv = devm_kzalloc(&pdev->dev,
> + sizeof(struct fsl_spdif_priv) + strlen(p) + 1, GFP_KERNEL);
> + if (!spdif_priv) {
> + dev_err(&pdev->dev, "could not allocate DAI object\n");
> + return -ENOMEM;
> + }
> +
> + strcpy(spdif_priv->name, p);
> +
> + spdif_priv->pdev = pdev;
> +
> + /* Initialize this copy of the CPU DAI driver structure */
> + memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai,
> sizeof(fsl_spdif_dai)); + spdif_priv->cpu_dai_drv.name =
> spdif_priv->name;
> +
> + /* Get the addresses and IRQ */
> + ret = of_address_to_resource(np, 0, &res);
This has been already done for you by platform driver core. You can just
use platform_get_resource() to retrieve the already parsed resource.
> + if (ret) {
> + dev_err(&pdev->dev, "could not determine device resources\n");
> + return ret;
> + }
> +
> + regs = of_iomap(np, 0);
devm_ioremap_resource() would be better here.
> + if (IS_ERR(regs)) {
> + dev_err(&pdev->dev, "could not map device resources\n");
> + return PTR_ERR(regs);
> + }
> +
> + spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
> + "core", regs, &fsl_spdif_regmap_config);
> + if (IS_ERR(spdif_priv->regmap)) {
> + dev_err(&pdev->dev, "regmap init failed\n");
> + ret = PTR_ERR(spdif_priv->regmap);
> + return ret;
> + }
> +
> + spdif_priv->irq = irq_of_parse_and_map(np, 0);
platform_get_resource()
> + if (spdif_priv->irq == NO_IRQ) {
> + dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
> + ret = -ENXIO;
> + goto error_iomap;
> + }
> +
> + /* The 'name' should not have any slashes in it. */
> + ret = request_irq(spdif_priv->irq, spdif_isr, 0,
> + spdif_priv->name, spdif_priv);
> + if (ret) {
> + dev_err(&pdev->dev, "could not claim irq %u\n", spdif_priv->irq);
> + goto error_irqmap;
> + }
> +
> + spdif_priv->coreclk = devm_clk_get(&pdev->dev, NULL);
I'm not sure this is correct. You have not specified the order of clocks
in your DT bindings, so it is not guaranteed that "core" clock will be
always first.
IMHO it won't hurt to simply call devm_clk_get() with "core" as clock
name and will be much safer.
Best regards,
Tomasz
> + if (IS_ERR(spdif_priv->coreclk)) {
> + dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
> + ret = PTR_ERR(spdif_priv->coreclk);
> + goto error_irqreq;
> + }
> +
> + spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rx");
> + if (IS_ERR(spdif_priv->rxclk)) {
> + dev_warn(&pdev->dev, "using core clock as rx clk\n");
> + spdif_priv->rxclk = spdif_priv->coreclk;
> + }
> +
> + spdif_priv->txclk_main = devm_clk_get(&pdev->dev, "tx");
> + if (IS_ERR(spdif_priv->txclk_main)) {
> + dev_warn(&pdev->dev, "using core clock as tx clk\n");
> + spdif_priv->txclk_main = spdif_priv->coreclk;
> + }
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
> + spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, rate[i]);
> + if (IS_ERR(spdif_priv->txclk[i])) {
> + dev_warn(&pdev->dev, "using tx clock as %s clk\n", rate[i]);
> + spdif_priv->txclk[i] = spdif_priv->txclk_main;
> + }
> + }
> +
> + spdif_clksrc_index_lookup(spdif_priv);
> +
> + /* We use regmap to control core clk, so no need to prepare it */
> + clk_prepare(spdif_priv->rxclk);
> + clk_prepare(spdif_priv->txclk_main);
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_prepare(spdif_priv->txclk[i]);
> +
> + spdif_clk_cal_txdiv(spdif_priv);
> +
> + /* initial spinlock for control data */
> + ctrl = &spdif_priv->fsl_spdif_control;
> + spin_lock_init(&ctrl->ctl_lock);
> +
> + /* init tx channel status default value */
> + ctrl->ch_status[0] =
> + IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015;
> + ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
> + ctrl->ch_status[2] = 0x00;
> + ctrl->ch_status[3] =
> + IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
> +
> + atomic_set(&spdif_priv->dpll_locked, 0);
> +
> + spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
> + spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
> + spdif_priv->dma_params_tx.addr = res.start + REG_SPDIF_STL;
> + spdif_priv->dma_params_rx.addr = res.start + REG_SPDIF_SRL;
> +
> + /* Register with ASoC */
> + dev_set_drvdata(&pdev->dev, spdif_priv);
> +
> + ret = snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
> + &spdif_priv->cpu_dai_drv, 1);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
> + goto error_dev;
> + }
> +
> + ret = imx_pcm_dma_init(pdev);
> + if (ret) {
> + dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
> + goto error_component;
> + }
> +
> + return ret;
> +
> +error_component:
> + snd_soc_unregister_component(&pdev->dev);
> +error_dev:
> + dev_set_drvdata(&pdev->dev, NULL);
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_unprepare(spdif_priv->txclk[i]);
> + clk_unprepare(spdif_priv->txclk_main);
> + clk_unprepare(spdif_priv->rxclk);
> +error_irqreq:
> + free_irq(spdif_priv->irq, spdif_priv);
> +error_irqmap:
> + irq_dispose_mapping(spdif_priv->irq);
> +error_iomap:
> + iounmap(regs);
> +
> + return ret;
> +}
> +
> +static int fsl_spdif_remove(struct platform_device *pdev)
> +{
> + struct fsl_spdif_priv *spdif_priv = platform_get_drvdata(pdev);
> + int i;
> +
> + imx_pcm_dma_exit(pdev);
> + snd_soc_unregister_component(&pdev->dev);
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_unprepare(spdif_priv->txclk[i]);
> + clk_unprepare(spdif_priv->txclk_main);
> + clk_unprepare(spdif_priv->rxclk);
> +
> + free_irq(spdif_priv->irq, spdif_priv);
> + irq_dispose_mapping(spdif_priv->irq);
> +
> + dev_set_drvdata(&pdev->dev, NULL);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id fsl_spdif_dt_ids[] = {
> + { .compatible = "fsl,imx35-spdif", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
> +
> +static struct platform_driver fsl_spdif_driver = {
> + .driver = {
> + .name = "fsl-spdif-dai",
> + .owner = THIS_MODULE,
> + .of_match_table = fsl_spdif_dt_ids,
> + },
> + .probe = fsl_spdif_probe,
> + .remove = fsl_spdif_remove,
> +};
> +
> +module_platform_driver(fsl_spdif_driver);
> +
> +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
> +MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:fsl-spdif-dai");
> diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h
> new file mode 100644
> index 0000000..df183fb
> --- /dev/null
> +++ b/sound/soc/fsl/fsl_spdif.h
> @@ -0,0 +1,224 @@
> +/*
> + * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * Author: Nicolin Chen <b42378@freescale.com>
> + *
> + * Based on fsl_ssi.h
> + * Author: Timur Tabi <timur@freescale.com>
> + * Copyright 2007-2008 Freescale Semiconductor, Inc.
> + *
> + * This file is licensed under the terms of the GNU General Public
> License + * version 2. This program is licensed "as is" without any
> warranty of any + * kind, whether express or implied.
> + */
> +
> +#ifndef _FSL_SPDIF_DAI_H
> +#define _FSL_SPDIF_DAI_H
> +
> +/* S/PDIF Register Map */
> +#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
> +#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
> +#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
> +#define REG_SPDIF_SIE 0xc /* InterruptEn Register */
> +#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
> +#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
> +#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
> +#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
> +#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
> +#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
> +#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
> +#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
> +#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
> +#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
> +#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
> +#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
> +#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
> +#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
> +
> +
> +/* SPDIF Configuration register */
> +#define SCR_RXFIFO_CTL_OFFSET 23
> +#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
> +#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
> +#define SCR_RXFIFO_OFF_OFFSET 22
> +#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
> +#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
> +#define SCR_RXFIFO_RST_OFFSET 21
> +#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
> +#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
> +#define SCR_RXFIFO_FSEL_OFFSET 19
> +#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_AUTOSYNC_OFFSET 18
> +#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_AUTOSYNC_OFFSET 17
> +#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_FSEL_OFFSET 15
> +#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_LOW_POWER (1 << 13)
> +#define SCR_SOFT_RESET (1 << 12)
> +#define SCR_TXFIFO_CTRL_OFFSET 10
> +#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_DMA_RX_EN_OFFSET 9
> +#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
> +#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
> +#define SCR_DMA_TX_EN_OFFSET 8
> +#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
> +#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
> +#define SCR_VAL_OFFSET 5
> +#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
> +#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
> +#define SCR_TXSEL_OFFSET 2
> +#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
> +#define SCR_USRC_SEL_OFFSET 0x0
> +#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
> +
> +/* SPDIF CDText control */
> +#define SRCD_CD_USER_OFFSET 1
> +#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
> +
> +/* SPDIF Phase Configuration register */
> +#define SRPC_DPLL_LOCKED (1 << 6)
> +#define SRPC_CLKSRC_SEL_OFFSET 7
> +#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
> +#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) &
> SRPC_CLKSRC_SEL_MASK) +#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
> +#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
> +#define SRPC_GAINSEL_OFFSET 3
> +#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
> +#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) &
> SRPC_GAINSEL_MASK) +
> +/* SPDIF rx clock source */
> +enum spdif_rxclk_src {
> + SRPC_CLKSRC_0 = 0,
> + SRPC_CLKSRC_1,
> + SRPC_CLKSRC_2,
> + SRPC_CLKSRC_3,
> + SRPC_CLKSRC_4,
> + SRPC_CLKSRC_5,
> + SRPC_CLKSRC_6,
> + SRPC_CLKSRC_7,
> + SRPC_CLKSRC_8,
> + SRPC_CLKSRC_9,
> + SRPC_CLKSRC_10,
> + SRPC_CLKSRC_11,
> + SRPC_CLKSRC_12,
> + SRPC_CLKSRC_13,
> + SRPC_CLKSRC_14,
> + SRPC_CLKSRC_15,
> +};
> +#define SRPC_CLKSRC_MAX (SRPC_CLKSRC_15 + 1)
> +#define DEFAULT_RXCLK_SRC SRPC_CLKSRC_0
> +
> +enum spdif_gainsel {
> + GAINSEL_MULTI_24 = 0,
> + GAINSEL_MULTI_16,
> + GAINSEL_MULTI_12,
> + GAINSEL_MULTI_8,
> + GAINSEL_MULTI_6,
> + GAINSEL_MULTI_4,
> + GAINSEL_MULTI_3,
> +};
> +#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
> +#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
> +
> +/* SPDIF interrupt mask define */
> +#define INT_DPLL_LOCKED (1 << 20)
> +#define INT_TXFIFO_UNOV (1 << 19)
> +#define INT_TXFIFO_RESYNC (1 << 18)
> +#define INT_CNEW (1 << 17)
> +#define INT_VAL_NOGOOD (1 << 16)
> +#define INT_SYM_ERR (1 << 15)
> +#define INT_BIT_ERR (1 << 14)
> +#define INT_URX_FUL (1 << 10)
> +#define INT_URX_OV (1 << 9)
> +#define INT_QRX_FUL (1 << 8)
> +#define INT_QRX_OV (1 << 7)
> +#define INT_UQ_SYNC (1 << 6)
> +#define INT_UQ_ERR (1 << 5)
> +#define INT_RXFIFO_UNOV (1 << 4)
> +#define INT_RXFIFO_RESYNC (1 << 3)
> +#define INT_LOSS_LOCK (1 << 2)
> +#define INT_TX_EM (1 << 1)
> +#define INT_RXFIFO_FUL (1 << 0)
> +
> +/* SPDIF Clock register */
> +#define STC_SYSCLK_DIV_OFFSET 11
> +#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
> +#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) &
> STC_SYSCLK_DIV_MASK) +#define STC_TXCLK_SRC_OFFSET 8
> +#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
> +#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) &
> STC_TXCLK_SRC_MASK) +#define STC_TXCLK_ALL_EN_OFFSET 7
> +#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
> +#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
> +#define STC_TXCLK_DIV_OFFSET 0
> +#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
> +#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) &
> STC_TXCLK_DIV_MASK) +
> +/* SPDIF tx clksrc */
> +enum spdif_txclk_src {
> + STC_TXCLK_SRC_0 = 0,
> + STC_TXCLK_SRC_1,
> + STC_TXCLK_SRC_2,
> + STC_TXCLK_SRC_3,
> + STC_TXCLK_SRC_4,
> + STC_TXCLK_SRC_5,
> + STC_TXCLK_SRC_6,
> + STC_TXCLK_SRC_7,
> +};
> +#define STC_TXCLK_SRC_MAX (STC_TXCLK_SRC_7 + 1)
> +#define DEFAULT_TXCLK_SRC STC_TXCLK_SRC_1
> +
> +/* SPDIF tx rate */
> +enum spdif_txrate {
> + SPDIF_TXRATE_32000 = 0,
> + SPDIF_TXRATE_44100,
> + SPDIF_TXRATE_48000,
> +};
> +#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
> +
> +
> +#define SPDIF_CSTATUS_BYTE 6
> +#define SPDIF_UBITS_SIZE 96
> +#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
> +
> +
> +#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
> + SNDRV_PCM_RATE_44100 | \
> + SNDRV_PCM_RATE_48000)
> +
> +#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
> + SNDRV_PCM_RATE_32000 | \
> + SNDRV_PCM_RATE_44100 | \
> + SNDRV_PCM_RATE_48000 | \
> + SNDRV_PCM_RATE_64000 | \
> + SNDRV_PCM_RATE_96000)
> +
> +#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
> + SNDRV_PCM_FMTBIT_S20_3LE | \
> + SNDRV_PCM_FMTBIT_S24_LE)
> +
> +#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
> +
> +#endif /* _FSL_SPDIF_DAI_H */
[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* [PATCH] powerpc: add the missing required isync for the coherent icache flush
From: Kevin Hao @ 2013-08-15 11:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc
Even we don't need to flush the dcache and invalidate the icache
on the CPU which has coherent icache. But we do need an isync to
discard the prefetched instructions in this case.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
arch/powerpc/kernel/misc_32.S | 2 ++
arch/powerpc/kernel/misc_64.S | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 777d999..0b84c8d 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -433,6 +433,7 @@ _GLOBAL(invalidate_dcache_range)
*/
_GLOBAL(__flush_dcache_icache)
BEGIN_FTR_SECTION
+ isync
blr
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
@@ -474,6 +475,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
*/
_GLOBAL(__flush_dcache_icache_phys)
BEGIN_FTR_SECTION
+ isync
blr /* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
mfmsr r10
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 992a78e..d74fefb 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -69,6 +69,7 @@ PPC64_CACHES:
_KPROBE(flush_icache_range)
BEGIN_FTR_SECTION
+ isync
blr
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
/*
--
1.8.3.1
^ permalink raw reply related
* [PATCH v2 3/3] powerpc: check CPU_FTR_COHERENT_ICACHE in __flush_dcache_icache for 64bit kernel
From: Kevin Hao @ 2013-08-15 11:45 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc
In-Reply-To: <20130807060950.GC26904@pek-khao-d1.corp.ad.wrs.com>
We don't need to flush the dcache and invalidate the icache on the
CPU which has CPU_FTR_COHERENT_ICACHE set. Also add the missing
required isync in this case.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
v2: Add the isync.
arch/powerpc/kernel/misc_64.S | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 971d7e7..992a78e 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -207,6 +207,10 @@ _GLOBAL(flush_inval_dcache_range)
* void __flush_dcache_icache(void *page)
*/
_GLOBAL(__flush_dcache_icache)
+BEGIN_FTR_SECTION
+ isync
+ blr
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
/*
* Flush the data cache to memory
*
--
1.8.3.1
^ permalink raw reply related
* [PATCH v5 2/2] ASoC: fsl: Add S/PDIF machine driver
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: devicetree, alsa-devel, festevam, timur, rob.herring, shawn.guo,
linuxppc-dev
In-Reply-To: <cover.1376565456.git.b42378@freescale.com>
Add S/PDIF machine driver for Freescale i.MX series SoC.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
---
.../devicetree/bindings/sound/imx-audio-spdif.txt | 29 +++++
sound/soc/fsl/Kconfig | 11 ++
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/imx-spdif.c | 134 ++++++++++++++++++++
4 files changed, 176 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
create mode 100644 sound/soc/fsl/imx-spdif.c
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
new file mode 100644
index 0000000..9a3fa26
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
@@ -0,0 +1,29 @@
+Freescale i.MX audio complex with S/PDIF transceiver
+
+Required properties:
+
+ - compatible : "fsl,imx-audio-spdif"
+
+ - model : The user-visible name of this sound complex
+
+ - spdif-controller : The phandle of the i.MX S/PDIF controller
+
+
+Optional properties:
+
+ - spdif-transmitter : The phandle of the spdif-transmitter dummy codec
+
+ - spdif-receiver : The phandle of the spdif-receiver dummy codec
+
+* Note: At least one of these two properties should be set in the DT binding.
+
+
+Example:
+
+sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-transmitter = <&spdif_tx_codec>;
+ spdif-receiver = <&spdif_rx_codec>;
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 2c518db..4cc118c 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -195,6 +195,17 @@ config SND_SOC_IMX_SGTL5000
Say Y if you want to add support for SoC audio on an i.MX board with
a sgtl5000 codec.
+config SND_SOC_IMX_SPDIF
+ tristate "SoC Audio support for i.MX boards with S/PDIF"
+ select SND_SOC_IMX_PCM_DMA
+ select SND_SOC_FSL_SPDIF
+ select SND_SOC_FSL_UTILS
+ select SND_SOC_SPDIF
+ help
+ SoC Audio support for i.MX boards with S/PDIF
+ Say Y if you want to add support for SoC audio on an i.MX board with
+ a S/DPDIF.
+
config SND_SOC_IMX_MC13783
tristate "SoC Audio support for I.MX boards with mc13783"
depends on MFD_MC13783 && ARM
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 4b5970e..e2aaff7 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -45,6 +45,7 @@ snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
snd-soc-wm1133-ev1-objs := wm1133-ev1.o
snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
snd-soc-imx-wm8962-objs := imx-wm8962.o
+snd-soc-imx-spdif-objs :=imx-spdif.o
snd-soc-imx-mc13783-objs := imx-mc13783.o
obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
@@ -53,4 +54,5 @@ obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
obj-$(CONFIG_SND_SOC_IMX_WM8962) += snd-soc-imx-wm8962.o
+obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o
obj-$(CONFIG_SND_SOC_IMX_MC13783) += snd-soc-imx-mc13783.o
diff --git a/sound/soc/fsl/imx-spdif.c b/sound/soc/fsl/imx-spdif.c
new file mode 100644
index 0000000..893f3d1
--- /dev/null
+++ b/sound/soc/fsl/imx-spdif.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <sound/soc.h>
+
+struct imx_spdif_data {
+ struct snd_soc_dai_link dai[2];
+ struct snd_soc_card card;
+};
+
+static int imx_spdif_audio_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *spdif_np, *codec_tx_np, *codec_rx_np;
+ struct platform_device *spdif_pdev;
+ struct imx_spdif_data *data;
+ int ret = 0, num_links = 0;
+
+ spdif_np = of_parse_phandle(np, "spdif-controller", 0);
+ if (!spdif_np) {
+ dev_err(&pdev->dev, "failed to find spdif-controller\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ spdif_pdev = of_find_device_by_node(spdif_np);
+ if (!spdif_pdev) {
+ dev_err(&pdev->dev, "failed to find S/PDIF device\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data) {
+ dev_err(&pdev->dev, "failed to allocate memory\n");
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ codec_tx_np = of_parse_phandle(np, "spdif-transmitter", 0);
+ if (codec_tx_np) {
+ data->dai[num_links].name = "S/PDIF TX";
+ data->dai[num_links].stream_name = "S/PDIF PCM Playback";
+ data->dai[num_links].codec_dai_name = "dit-hifi";
+ data->dai[num_links].codec_of_node = codec_tx_np;
+ data->dai[num_links].cpu_of_node = spdif_np;
+ data->dai[num_links].platform_of_node = spdif_np;
+ num_links++;
+ }
+
+ codec_rx_np = of_parse_phandle(np, "spdif-receiver", 0);
+ if (codec_rx_np) {
+ data->dai[num_links].name = "S/PDIF RX";
+ data->dai[num_links].stream_name = "S/PDIF PCM Capture";
+ data->dai[num_links].codec_dai_name = "dir-hifi";
+ data->dai[num_links].codec_of_node = codec_rx_np;
+ data->dai[num_links].cpu_of_node = spdif_np;
+ data->dai[num_links].platform_of_node = spdif_np;
+ num_links++;
+ }
+
+ if (!num_links) {
+ dev_err(&pdev->dev, "no enabled S/PDIF DAI link\n");
+ goto fail;
+ }
+
+ data->card.dev = &pdev->dev;
+ data->card.num_links = num_links;
+ data->card.dai_link = data->dai;
+
+ ret = snd_soc_of_parse_card_name(&data->card, "model");
+ if (ret)
+ goto fail;
+
+ ret = snd_soc_register_card(&data->card);
+ if (ret) {
+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+ goto fail;
+ }
+
+ platform_set_drvdata(pdev, data);
+
+fail:
+ if (codec_tx_np)
+ of_node_put(codec_tx_np);
+ if (codec_rx_np)
+ of_node_put(codec_rx_np);
+ if (spdif_np)
+ of_node_put(spdif_np);
+
+ return ret;
+}
+
+static int imx_spdif_audio_remove(struct platform_device *pdev)
+{
+ struct imx_spdif_data *data = platform_get_drvdata(pdev);
+
+ snd_soc_unregister_card(&data->card);
+
+ return 0;
+}
+
+static const struct of_device_id imx_spdif_dt_ids[] = {
+ { .compatible = "fsl,imx-audio-spdif", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_spdif_dt_ids);
+
+static struct platform_driver imx_spdif_driver = {
+ .driver = {
+ .name = "imx-spdif",
+ .owner = THIS_MODULE,
+ .of_match_table = imx_spdif_dt_ids,
+ },
+ .probe = imx_spdif_audio_probe,
+ .remove = imx_spdif_audio_remove,
+};
+
+module_platform_driver(imx_spdif_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Freescale i.MX S/PDIF machine driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx-spdif");
--
1.7.1
^ permalink raw reply related
* [PATCH v5 0/2] Add freescale S/PDIF CPU DAI and machine drivers
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: devicetree, alsa-devel, festevam, timur, rob.herring, shawn.guo,
linuxppc-dev
Changelog:
v4->v5:
* Dropped rx/tx-clksrc-names DT bindings.
* Use standard clock binding instead to pass the clock source list.
* Update the compatible list by using "imx35", the first SoC that has spdif.
v3->v4:
* Use regmap for CPU DAI driver.
* Use individual clock source for 32KHz, 44KHz, 48KHz playback.
* Determine clock source configuration from 'clocks' entry.
* Added imx53 to compatible list, merged imx6q and imx6dl in the list.
* Improve the algorism of reverse_bits().
* Dropped the unneeded clk_put().
v2->v3:
* Removed a wrong tag from the commit of patch-1.
v1->v2:
* Dropped one applied patch for spdif dummy codec drivers.
* Use generic DMA DT binding.
* Let spdif controller driver calculate the clock div.
* Added one optional clock source for spdif tx.
* Reivsed documentation accordingly.
Nicolin Chen (2):
ASoC: fsl: Add S/PDIF CPU DAI driver
ASoC: fsl: Add S/PDIF machine driver
.../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
.../devicetree/bindings/sound/imx-audio-spdif.txt | 29 +
sound/soc/fsl/Kconfig | 14 +
sound/soc/fsl/Makefile | 4 +
sound/soc/fsl/fsl_spdif.c | 1336 ++++++++++++++++++++
sound/soc/fsl/fsl_spdif.h | 224 ++++
sound/soc/fsl/imx-spdif.c | 134 ++
7 files changed, 1817 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,spdif.txt
create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
create mode 100644 sound/soc/fsl/fsl_spdif.c
create mode 100644 sound/soc/fsl/fsl_spdif.h
create mode 100644 sound/soc/fsl/imx-spdif.c
^ permalink raw reply
* [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: devicetree, alsa-devel, festevam, timur, rob.herring, shawn.guo,
linuxppc-dev
In-Reply-To: <cover.1376565456.git.b42378@freescale.com>
This patch add S/PDIF controller driver for Freescale SoC.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
---
.../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
sound/soc/fsl/Kconfig | 3 +
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/fsl_spdif.c | 1336 ++++++++++++++++++++
sound/soc/fsl/fsl_spdif.h | 224 ++++
5 files changed, 1641 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,spdif.txt
create mode 100644 sound/soc/fsl/fsl_spdif.c
create mode 100644 sound/soc/fsl/fsl_spdif.h
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
new file mode 100644
index 0000000..301b827
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
@@ -0,0 +1,76 @@
+Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
+
+The Freescale S/PDIF audio block is a stereo transceiver that allows the
+processor to receive and transmit digital audio via an coaxial cable or
+a fibre cable.
+
+Required properties:
+
+ - compatible : Compatible list, contains "fsl,<chip>-spdif".
+
+ - reg : Offset and length of the register set for the device.
+
+ - interrupts : Contains spdif interrupt.
+
+ - dmas : Generic dma devicetree binding as described in
+ Documentation/devicetree/bindings/dma/dma.txt.
+
+ - dma-names : Two dmas have to be defined, "tx" and "rx".
+
+ - clocks : Contains an entry for each entry in clock-names.
+
+ - clock-names : Includes the following entries:
+ name type comments
+ "core" Required The core clock of spdif controller
+
+ "rx" Optional Rx clock source for spdif record.
+ If absent, will use core clock.
+
+ "tx" Optional Tx clock source for spdif playback.
+ If absent, will use core clock.
+
+ "tx-32000" Optional Tx clock source for 32000Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "tx-44100" Optional Tx clock source for 44100Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "tx-48000" Optional Tx clock source for 48000Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "src<0-7>" Optional Clock source list for tx and rx clock
+ to look up their clock source indexes.
+ This clock list should be identical to
+ the list of TxClk_Source bit value of
+ register SPDIF_STC. If absent or failed
+ to look up, tx and rx clock would then
+ ignore the "rx", "tx" "tx-32000",
+ "tx-44100", "tx-48000" clock phandles
+ and select the core clock as default
+ tx and rx clock.
+
+Optional properties:
+
+ - rx-clksrc-lock: This is a boolean property. If present, ClkSrc_Sel bit
+ of SPDIF_SRPC would be set a clock source that cares DPLL locked condition.
+
+Example:
+
+spdif: spdif@02004000 {
+ compatible = "fsl,imx6q-spdif",
+ "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+ interrupts = <0 52 0x04>;
+ dmas = <&sdma 14 18 0>,
+ <&sdma 15 18 0>;
+ dma-names = "rx", "tx";
+
+ clocks = <&clks 197>, <&clks 3>, <&clks 197>,
+ <&clks 107>, <&clks 118>, <&clks 62>,
+ <&clks 139>;
+ clock-names = "core", "src0", "src1", "src2",
+ "src4", "src5", "src6";
+ rx-clksrc-lock;
+
+ status = "okay";
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index e15f771..2c518db 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,6 +1,9 @@
config SND_SOC_FSL_SSI
tristate
+config SND_SOC_FSL_SPDIF
+ tristate
+
config SND_SOC_FSL_UTILS
tristate
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index d4b4aa8..4b5970e 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -12,9 +12,11 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) += snd-soc-p1022-rdk.o
# Freescale PowerPC SSI/DMA Platform Support
snd-soc-fsl-ssi-objs := fsl_ssi.o
+snd-soc-fsl-spdif-objs := fsl_spdif.o
snd-soc-fsl-utils-objs := fsl_utils.o
snd-soc-fsl-dma-objs := fsl_dma.o
obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
new file mode 100644
index 0000000..173d699
--- /dev/null
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -0,0 +1,1336 @@
+/*
+ * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Based on stmp3xxx_spdif_dai.c
+ * Vladimir Barinov <vbarinov@embeddedalley.com>
+ * Copyright 2008 SigmaTel, Inc
+ * Copyright 2008 Embedded Alley Solutions, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/regmap.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+
+#include <sound/asoundef.h>
+#include <sound/soc.h>
+#include <sound/dmaengine_pcm.h>
+
+#include "fsl_spdif.h"
+#include "imx-pcm.h"
+
+#define FSL_SPDIF_TXFIFO_WML 0x8
+#define FSL_SPDIF_RXFIFO_WML 0x8
+
+#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
+#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL | INT_URX_OV|\
+ INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
+ INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
+
+/* Index list for the values that has if (DPLL Locked) in ClkSrc_Sel bit of SRPC */
+static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb, };
+#define SRPC_NODPLL_START1 0x5
+#define SRPC_NODPLL_START2 0xc
+
+/*
+ * SPDIF control structure
+ * Defines channel status, subcode and Q sub
+ */
+struct spdif_mixer_control {
+ /* spinlock to access control data */
+ spinlock_t ctl_lock;
+
+ /* IEC958 channel tx status bit */
+ unsigned char ch_status[4];
+
+ /* User bits */
+ unsigned char subcode[2 * SPDIF_UBITS_SIZE];
+
+ /* Q subcode part of user bits */
+ unsigned char qsub[2 * SPDIF_QSUB_SIZE];
+
+ /* buffer ptrs for writer */
+ u32 upos;
+ u32 qpos;
+
+ /* ready buffer index of the two buffers */
+ u32 ready_buf;
+};
+
+struct fsl_spdif_priv {
+ struct spdif_mixer_control fsl_spdif_control;
+ struct snd_soc_dai_driver cpu_dai_drv;
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ atomic_t dpll_locked;
+ u32 irq;
+ s8 rxclk_src;
+ s8 txclk_src[SPDIF_TXRATE_MAX];
+ u8 txclk_div[SPDIF_TXRATE_MAX];
+ struct clk *txclk[SPDIF_TXRATE_MAX];
+ struct clk *txclk_main;
+ struct clk *rxclk;
+ struct clk *coreclk;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
+
+ /* The name space will be allocated dynamically */
+ char name[0];
+};
+
+
+#ifdef DEBUG
+static void dumpregs(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 val, i;
+ int ret;
+
+ /* Valid address set of SPDIF is {[0x0-0x38], 0x44, 0x50} */
+ for (i = 0 ; i <= REG_SPDIF_STC; i += 4) {
+ ret = regmap_read(regmap, REG_SPDIF_SCR + i, &val);
+ if (!ret)
+ dev_dbg(&pdev->dev, "REG 0x%02x = 0x%06x\n", i, val);
+ }
+}
+#else
+static void dumpregs(struct fsl_spdif_priv *spdif_priv) {}
+#endif
+
+
+/* DPLL locked and lock loss interrupt handler */
+static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 locked;
+
+ regmap_read(regmap, REG_SPDIF_SRPC, &locked);
+ locked &= SRPC_DPLL_LOCKED;
+
+ dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
+ locked ? "locked" : "loss lock");
+
+ atomic_set(&spdif_priv->dpll_locked, locked ? 1 : 0);
+}
+
+/* Receiver found illegal symbol interrupt handler */
+static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+
+ dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
+
+ if (!atomic_read(&spdif_priv->dpll_locked)) {
+ /* dpll unlocked seems no audio stream */
+ regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
+ }
+}
+
+/* U/Q Channel receive register full */
+static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 *pos, size, val, reg;
+
+ switch (name) {
+ case 'U':
+ pos = &ctrl->upos;
+ size = SPDIF_UBITS_SIZE;
+ reg = REG_SPDIF_SRU;
+ break;
+ case 'Q':
+ pos = &ctrl->qpos;
+ size = SPDIF_QSUB_SIZE;
+ reg = REG_SPDIF_SRQ;
+ break;
+ default:
+ return;
+ }
+
+ dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
+
+ if (*pos >= size * 2) {
+ *pos = 0;
+ } else if (unlikely((*pos % size) + 3 > size)) {
+ dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
+ return;
+ }
+
+ regmap_read(regmap, reg, &val);
+ ctrl->subcode[*pos++] = val >> 16;
+ ctrl->subcode[*pos++] = val >> 8;
+ ctrl->subcode[*pos++] = val;
+}
+
+/* U/Q Channel sync found */
+static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct platform_device *pdev = spdif_priv->pdev;
+
+ dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
+
+ /* U/Q buffer reset */
+ if (ctrl->qpos == 0)
+ return;
+
+ /* set ready to this buffer */
+ ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
+}
+
+/* U/Q Channel framing error */
+static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 val;
+
+ dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
+
+ /* read U/Q data and do buffer reset */
+ regmap_read(regmap, REG_SPDIF_SRU, &val);
+ regmap_read(regmap, REG_SPDIF_SRQ, &val);
+
+ /* drop this U/Q buffer */
+ ctrl->ready_buf = 0;
+ ctrl->upos = 0;
+ ctrl->qpos = 0;
+}
+
+/* Get spdif interrupt status and clear the interrupt */
+static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val, val2;
+
+ regmap_read(regmap, REG_SPDIF_SIS, &val);
+ regmap_read(regmap, REG_SPDIF_SIE, &val2);
+
+ regmap_write(regmap, REG_SPDIF_SIC, val & val2);
+
+ return val;
+}
+
+static irqreturn_t spdif_isr(int irq, void *devid)
+{
+ struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 sis;
+
+ sis = spdif_intr_status_clear(spdif_priv);
+
+ if (sis & INT_DPLL_LOCKED)
+ spdif_irq_dpll_lock(spdif_priv);
+
+ if (sis & INT_TXFIFO_UNOV)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
+
+ if (sis & INT_TXFIFO_RESYNC)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
+
+ if (sis & INT_CNEW)
+ dev_dbg(&pdev->dev, "isr: cstatus new\n");
+
+ if (sis & INT_VAL_NOGOOD)
+ dev_dbg(&pdev->dev, "isr: validity flag no good\n");
+
+ if (sis & INT_SYM_ERR)
+ spdif_irq_sym_error(spdif_priv);
+
+ if (sis & INT_BIT_ERR)
+ dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
+
+ if (sis & INT_URX_FUL)
+ spdif_irq_uqrx_full(spdif_priv, 'U');
+
+ if (sis & INT_URX_OV)
+ dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
+
+ if (sis & INT_QRX_FUL)
+ spdif_irq_uqrx_full(spdif_priv, 'Q');
+
+ if (sis & INT_QRX_OV)
+ dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
+
+ if (sis & INT_UQ_SYNC)
+ spdif_irq_uq_sync(spdif_priv);
+
+ if (sis & INT_UQ_ERR)
+ spdif_irq_uq_err(spdif_priv);
+
+ if (sis & INT_RXFIFO_UNOV)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
+
+ if (sis & INT_RXFIFO_RESYNC)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
+
+ if (sis & INT_LOSS_LOCK)
+ spdif_irq_dpll_lock(spdif_priv);
+
+ /* FIXME: Write Tx FIFO to clear TxEm */
+ if (sis & INT_TX_EM)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
+
+ /* FIXME: Read Rx FIFO to clear RxFIFOFul */
+ if (sis & INT_RXFIFO_FUL)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
+
+ return IRQ_HANDLED;
+}
+
+static void spdif_softreset(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val, cycle = 1000;
+
+ regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
+ regcache_sync(regmap);
+
+ /* RESET bit would be cleared after finishing its reset procedure */
+ do {
+ regmap_read(regmap, REG_SPDIF_SCR, &val);
+ } while ((val & SCR_SOFT_RESET) && cycle--);
+}
+
+static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
+ u8 mask, u8 cstatus)
+{
+ ctrl->ch_status[3] &= ~mask;
+ ctrl->ch_status[3] |= cstatus & mask;
+}
+
+static u8 reverse_bits(u8 input)
+{
+ u8 tmp = input;
+
+ tmp = ((tmp & 0b10101010) >> 1) | ((tmp << 1) & 0b10101010);
+ tmp = ((tmp & 0b11001100) >> 2) | ((tmp << 2) & 0b11001100);
+ tmp = ((tmp & 0b11110000) >> 4) | ((tmp << 4) & 0b11110000);
+
+ return tmp;
+}
+
+static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 ch_status;
+
+ ch_status = (reverse_bits(ctrl->ch_status[0]) << 16) |
+ (reverse_bits(ctrl->ch_status[1]) << 8) |
+ reverse_bits(ctrl->ch_status[2]);
+ regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
+
+ dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
+
+ ch_status = reverse_bits(ctrl->ch_status[3]) << 16;
+ regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
+
+ dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
+}
+
+/* Set SPDIF PhaseConfig register for rx clock */
+static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
+ enum spdif_gainsel gainsel, int dpll_locked)
+{
+ enum spdif_rxclk_src clksrc = spdif_priv->rxclk_src;
+ struct regmap *regmap = spdif_priv->regmap;
+
+ if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
+ return -EINVAL;
+
+ regmap_update_bits(regmap, REG_SPDIF_SRPC,
+ SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
+ SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
+
+ return 0;
+}
+
+static int spdif_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long rate_actual;
+
+ rate_actual = clk_round_rate(clk, rate);
+ clk_set_rate(clk, rate_actual);
+
+ return 0;
+}
+
+static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
+ int sample_rate)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ unsigned long clk = -1, div = 1, csfs = 0;
+ u32 stc, mask, rate;
+
+ switch (sample_rate) {
+ case 32000:
+ rate = SPDIF_TXRATE_32000;
+ csfs = IEC958_AES3_CON_FS_32000;
+ break;
+ case 44100:
+ rate = SPDIF_TXRATE_44100;
+ csfs = IEC958_AES3_CON_FS_44100;
+ break;
+ case 48000:
+ rate = SPDIF_TXRATE_48000;
+ csfs = IEC958_AES3_CON_FS_48000;
+ break;
+ default:
+ dev_err(&pdev->dev, "unsupported samplerate %d\n", sample_rate);
+ return -EINVAL;
+ }
+
+ clk = spdif_priv->txclk_src[rate];
+ if (clk < 0) {
+ dev_err(&pdev->dev, "no defined %d clk src\n", sample_rate);
+ return -EINVAL;
+ }
+
+ div = spdif_priv->txclk_div[rate];
+ if (div == 0) {
+ dev_err(&pdev->dev, "tx clock source is dividing by zero\n");
+ return -EINVAL;
+ }
+ /*
+ * The S/PDIF block needs a clock of 64 * fs * div. The S/PDIF block
+ * will divide by (div). So request 64 * fs * (div+1) which will
+ * get rounded.
+ */
+ spdif_clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (div + 1));
+
+ dev_dbg(&pdev->dev, "expected clock rate = %d\n",
+ (int)(64 * sample_rate * div));
+ dev_dbg(&pdev->dev, "acutal clock rate = %d\n",
+ (int)clk_get_rate(spdif_priv->txclk[rate]));
+
+ /* set fs field in consumer channel status */
+ spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
+
+ /* select clock source and divisor */
+ stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DIV(div);
+ mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | STC_TXCLK_DIV_MASK;
+ regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
+
+ dev_dbg(&pdev->dev, "set sample rate to %d\n", sample_rate);
+
+ return 0;
+}
+
+int fsl_spdif_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 scr, mask, i;
+
+ /* Reset module and interrupts only for first initialization */
+ if (!cpu_dai->active) {
+ spdif_softreset(spdif_priv);
+
+ /* disable all the interrupts */
+ regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
+ }
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
+ SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
+ SCR_TXFIFO_FSEL_IF8;
+ mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
+ SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
+ SCR_TXFIFO_FSEL_MASK;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_enable(spdif_priv->txclk[i]);
+ } else {
+ scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
+ mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
+ SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
+ clk_enable(spdif_priv->rxclk);
+ }
+ regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
+
+ /* Power up SPDIF module */
+ regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
+
+ return 0;
+}
+
+static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 scr, mask, i;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ scr = 0;
+ mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
+ SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
+ SCR_TXFIFO_FSEL_MASK;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_disable(spdif_priv->txclk[i]);
+ } else {
+ scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
+ mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
+ SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
+ clk_disable(spdif_priv->rxclk);
+ }
+ regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
+
+ /* Power down SPDIF module only if tx&rx are both inactive */
+ if (!cpu_dai->active) {
+ spdif_intr_status_clear(spdif_priv);
+ regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, SCR_LOW_POWER);
+ }
+}
+
+static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 sample_rate = params_rate(params);
+ int ret = 0;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ ret = spdif_set_sample_rate(substream, sample_rate);
+ if (ret) {
+ dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
+ __func__, sample_rate);
+ return ret;
+ }
+ spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
+ IEC958_AES3_CON_CLOCK_1000PPM);
+ spdif_write_channel_status(spdif_priv);
+ } else {
+ /* setup rx clock source */
+ ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
+ }
+
+ return ret;
+}
+
+static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ int is_playack = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
+ u32 intr = is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE;
+ u32 dmaen = is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
+ regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
+ dumpregs(spdif_priv);
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
+ regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+struct snd_soc_dai_ops fsl_spdif_dai_ops = {
+ .startup = fsl_spdif_startup,
+ .hw_params = fsl_spdif_hw_params,
+ .trigger = fsl_spdif_trigger,
+ .shutdown = fsl_spdif_shutdown,
+};
+
+
+/*
+ * ============================================
+ * FSL SPDIF IEC958 controller(mixer) functions
+ *
+ * Channel status get/put control
+ * User bit value get/put control
+ * Valid bit value get control
+ * DPLL lock status get control
+ * User bit sync mode selection control
+ * ============================================
+ */
+
+static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
+ uinfo->count = 1;
+
+ return 0;
+}
+
+static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uvalue)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+
+ uvalue->value.iec958.status[0] = ctrl->ch_status[0];
+ uvalue->value.iec958.status[1] = ctrl->ch_status[1];
+ uvalue->value.iec958.status[2] = ctrl->ch_status[2];
+ uvalue->value.iec958.status[3] = ctrl->ch_status[3];
+
+ return 0;
+}
+
+static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uvalue)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+
+ ctrl->ch_status[0] = uvalue->value.iec958.status[0];
+ ctrl->ch_status[1] = uvalue->value.iec958.status[1];
+ ctrl->ch_status[2] = uvalue->value.iec958.status[2];
+ ctrl->ch_status[3] = uvalue->value.iec958.status[3];
+
+ spdif_write_channel_status(spdif_priv);
+
+ return 0;
+}
+
+/* Get channel status from SPDIF_RX_CCHAN register */
+static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 cstatus, val;
+
+ regmap_read(regmap, REG_SPDIF_SIS, &val);
+ if (!(val & INT_CNEW)) {
+ return -EAGAIN;
+ }
+
+ regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
+ ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
+ ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
+ ucontrol->value.iec958.status[2] = cstatus & 0xFF;
+
+ regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
+ ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
+ ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
+ ucontrol->value.iec958.status[5] = cstatus & 0xFF;
+
+ /* clear intr */
+ regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
+
+ return 0;
+}
+
+/*
+ * Get User bits (subcode) from chip value which readed out
+ * in UChannel register.
+ */
+static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&ctrl->ctl_lock, flags);
+ if (ctrl->ready_buf) {
+ int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
+ memcpy(&ucontrol->value.iec958.subcode[0],
+ &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
+ } else {
+ ret = -EAGAIN;
+ }
+ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+ return ret;
+}
+
+/* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
+static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
+ uinfo->count = SPDIF_QSUB_SIZE;
+
+ return 0;
+}
+
+/* Get Q subcode from chip value which readed out in QChannel register */
+static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&ctrl->ctl_lock, flags);
+ if (ctrl->ready_buf) {
+ int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
+ memcpy(&ucontrol->value.bytes.data[0],
+ &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
+ } else {
+ ret = -EAGAIN;
+ }
+ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+ return ret;
+}
+
+/* Valid bit infomation */
+static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+
+ return 0;
+}
+
+/* Get valid good bit from interrupt status register */
+static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val;
+
+ val = regmap_read(regmap, REG_SPDIF_SIS, &val);
+ ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
+ regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
+
+ return 0;
+}
+
+/* DPLL lock infomation */
+static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 16000;
+ uinfo->value.integer.max = 96000;
+
+ return 0;
+}
+
+static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
+ 24, 16, 12, 8, 6, 4, 3,
+};
+
+/* Get RX data clock rate given the SPDIF bus_clk */
+static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
+ enum spdif_gainsel gainsel)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u64 tmpval64, busclk_freq = 0;
+ u32 freqmeas, phaseconf;
+ enum spdif_rxclk_src clksrc;
+
+ regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
+ regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
+
+ clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
+ if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) {
+ /* get bus clock from system */
+ busclk_freq = clk_get_rate(spdif_priv->rxclk);
+ }
+
+ /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
+ tmpval64 = (u64) busclk_freq * freqmeas;
+ do_div(tmpval64, gainsel_multi[gainsel] * 1024);
+ do_div(tmpval64, 128 * 1024);
+
+ dev_dbg(&pdev->dev, "FreqMeas: %d\n", (int)freqmeas);
+ dev_dbg(&pdev->dev, "BusclkFreq: %d\n", (int)busclk_freq);
+ dev_dbg(&pdev->dev, "RxRate: %d\n", (int)tmpval64);
+
+ return (int)tmpval64;
+}
+
+/*
+ * Get DPLL lock or not info from stable interrupt status register.
+ * User application must use this control to get locked,
+ * then can do next PCM operation
+ */
+static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ int rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
+
+ if (atomic_read(&spdif_priv->dpll_locked))
+ ucontrol->value.integer.value[0] = rate;
+ else
+ ucontrol->value.integer.value[0] = 0;
+
+ return 0;
+}
+
+/* User bit sync mode info */
+static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+
+ return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val;
+
+ regmap_read(regmap, REG_SPDIF_SRCD, &val);
+ ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
+
+ return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
+
+ regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
+
+ return 0;
+}
+
+/* FSL SPDIF IEC958 controller defines */
+static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
+ /* status cchanel controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_WRITE |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_pb_get,
+ .put = fsl_spdif_pb_put,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_capture_get,
+ },
+ /* user bits controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 Subcode Capture Default",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_subcode_get,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 Q-subcode Capture Default",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_qinfo,
+ .get = fsl_spdif_qget,
+ },
+ /* valid bit error controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 V-Bit Errors",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_vbit_info,
+ .get = fsl_spdif_vbit_get,
+ },
+ /* DPLL lock info get controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "RX Sample Rate",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_rxrate_info,
+ .get = fsl_spdif_rxrate_get,
+ },
+ /* User bit sync mode set/get controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 USyncMode CDText",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_WRITE |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_usync_info,
+ .get = fsl_spdif_usync_get,
+ .put = fsl_spdif_usync_put,
+ },
+};
+
+static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
+{
+ struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
+
+ dai->playback_dma_data = &spdif_private->dma_params_tx;
+ dai->capture_dma_data = &spdif_private->dma_params_rx;
+
+ snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
+
+ return 0;
+}
+
+struct snd_soc_dai_driver fsl_spdif_dai = {
+ .probe = &fsl_spdif_dai_probe,
+ .playback = {
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = FSL_SPDIF_RATES_PLAYBACK,
+ .formats = FSL_SPDIF_FORMATS_PLAYBACK,
+ },
+ .capture = {
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = FSL_SPDIF_RATES_CAPTURE,
+ .formats = FSL_SPDIF_FORMATS_CAPTURE,
+ },
+ .ops = &fsl_spdif_dai_ops,
+};
+
+static const struct snd_soc_component_driver fsl_spdif_component = {
+ .name = "fsl-spdif",
+};
+
+/*
+ * ================
+ * FSL SPDIF REGMAP
+ * ================
+ */
+
+static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case REG_SPDIF_SCR:
+ case REG_SPDIF_SRCD:
+ case REG_SPDIF_SRPC:
+ case REG_SPDIF_SIE:
+ case REG_SPDIF_SIS:
+ case REG_SPDIF_SRL:
+ case REG_SPDIF_SRR:
+ case REG_SPDIF_SRCSH:
+ case REG_SPDIF_SRCSL:
+ case REG_SPDIF_SRU:
+ case REG_SPDIF_SRQ:
+ case REG_SPDIF_STCSCH:
+ case REG_SPDIF_STCSCL:
+ case REG_SPDIF_SRFM:
+ case REG_SPDIF_STC:
+ return true;
+ default:
+ return false;
+ };
+}
+
+static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case REG_SPDIF_SCR:
+ case REG_SPDIF_SRCD:
+ case REG_SPDIF_SRPC:
+ case REG_SPDIF_SIE:
+ case REG_SPDIF_SIC:
+ case REG_SPDIF_STL:
+ case REG_SPDIF_STR:
+ case REG_SPDIF_STCSCH:
+ case REG_SPDIF_STCSCL:
+ case REG_SPDIF_STC:
+ return true;
+ default:
+ return false;
+ };
+}
+
+static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
+{
+ /* Sync all registers after reset */
+ return true;
+}
+
+static const struct regmap_config fsl_spdif_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+
+ .max_register = REG_SPDIF_STC,
+ .readable_reg = fsl_spdif_readable_reg,
+ .writeable_reg = fsl_spdif_writeable_reg,
+ .volatile_reg = fsl_spdif_volatile_reg,
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static void spdif_clksrc_index_lookup(struct fsl_spdif_priv *spdif_priv)
+{
+ const char *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
+ struct platform_device *pdev = spdif_priv->pdev;
+ struct device_node *np = pdev->dev.of_node;
+ struct clk *tmpclk;
+ char tmp[16];
+ int i, j;
+
+ /* Start to decide tx/rxclk_src index */
+ spdif_priv->rxclk_src = -1;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ spdif_priv->txclk_src[i] = -1;
+
+ /* Look up the clock source list to find the clock source index */
+ for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
+ sprintf(tmp, "src%d", i);
+ tmpclk = devm_clk_get(&pdev->dev, tmp);
+ if (IS_ERR(tmpclk))
+ continue;
+
+ /* Catch the clksrc identical to configured rxclk */
+ if (tmpclk == spdif_priv->rxclk)
+ spdif_priv->rxclk_src = i;
+
+ for (j = 0; j < SPDIF_TXRATE_MAX; j++) {
+ /* Catch the clksrc identical to configured txclk */
+ if (tmpclk == spdif_priv->txclk[j])
+ spdif_priv->txclk_src[j] = i;
+ }
+ }
+
+ /* Plan B when failed to find the index for rx clock source */
+ if (spdif_priv->rxclk_src == -1) {
+ dev_warn(&pdev->dev, "force to use core clock as rx clock.\n");
+ spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
+ spdif_priv->rxclk = spdif_priv->coreclk;
+ }
+
+ /* Plan B when failed to find the index for tx clock source */
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
+ if (spdif_priv->txclk_src[i] != -1)
+ continue;
+ dev_warn(&pdev->dev, "force to use core clock as %s clock.\n", rate[i]);
+ spdif_priv->txclk_src[i] = DEFAULT_TXCLK_SRC;
+ spdif_priv->txclk[i] = spdif_priv->coreclk;
+ }
+
+ if (i > SRPC_NODPLL_START1) {
+ /* Drop src5 for rxclk src */
+ spdif_priv->rxclk_src -= 1;
+
+ /* Restore the offset to higher rxclk src */
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
+ }
+
+ /* Use the un-conditioned conf for rx clock if no rx-clksrc-lock */
+ if (!of_property_read_bool(np, "rx-clksrc-lock")) {
+ if (i < SRPC_NODPLL_START1)
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
+ else if (i < SRPC_NODPLL_START2)
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET2;
+ }
+}
+
+static void spdif_clk_cal_txdiv(struct fsl_spdif_priv *spdif_priv)
+{
+ struct platform_device *pdev = spdif_priv->pdev;
+ struct clk **clk = spdif_priv->txclk;
+ u64 rate_ideal, rate_actual, sub, savesub;
+ u32 i, div, arate, rate[] = { 32000, 44100, 48000, };
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++, savesub = 100000) {
+ for (div = 1; div <= 128; div++) {
+ rate_ideal = rate[i] * (div + 1) * 64;
+ rate_actual = clk_round_rate(clk[i], rate_ideal);
+
+ arate = rate_actual / 64;
+ arate /= div;
+ if (arate == rate[i]) {
+ savesub = 0;
+ spdif_priv->txclk_div[i] = div;
+ break;
+ } else if (arate / rate[i] == 1) {
+ sub = (arate - rate[i]) * 100000;
+ do_div(sub, rate[i]);
+ if (sub < savesub) {
+ savesub = sub;
+ spdif_priv->txclk_div[i] = div;
+ }
+ } else if (rate[i] / arate == 1) {
+ sub = (rate[i] - arate) * 100000;
+ do_div(sub, rate[i]);
+ if (sub < savesub) {
+ savesub = sub;
+ spdif_priv->txclk_div[i] = div;
+ }
+ }
+ }
+ dev_dbg(&pdev->dev, "calculated %dHz div: %d\n",
+ rate[i], spdif_priv->txclk_div[i]);
+ }
+}
+
+static int fsl_spdif_probe(struct platform_device *pdev)
+{
+ const char *p, *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
+ struct fsl_spdif_priv *spdif_priv;
+ struct spdif_mixer_control *ctrl;
+ struct device_node *np = pdev->dev.of_node;
+ struct resource res;
+ void __iomem *regs;
+ int ret = 0, i;
+
+ if (!of_device_is_available(np))
+ return -ENODEV;
+
+ /* The DAI name is the last part of the full name of the node. */
+ p = strrchr(np->full_name, '/') + 1;
+ spdif_priv = devm_kzalloc(&pdev->dev,
+ sizeof(struct fsl_spdif_priv) + strlen(p) + 1, GFP_KERNEL);
+ if (!spdif_priv) {
+ dev_err(&pdev->dev, "could not allocate DAI object\n");
+ return -ENOMEM;
+ }
+
+ strcpy(spdif_priv->name, p);
+
+ spdif_priv->pdev = pdev;
+
+ /* Initialize this copy of the CPU DAI driver structure */
+ memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
+ spdif_priv->cpu_dai_drv.name = spdif_priv->name;
+
+ /* Get the addresses and IRQ */
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret) {
+ dev_err(&pdev->dev, "could not determine device resources\n");
+ return ret;
+ }
+
+ regs = of_iomap(np, 0);
+ if (IS_ERR(regs)) {
+ dev_err(&pdev->dev, "could not map device resources\n");
+ return PTR_ERR(regs);
+ }
+
+ spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
+ "core", regs, &fsl_spdif_regmap_config);
+ if (IS_ERR(spdif_priv->regmap)) {
+ dev_err(&pdev->dev, "regmap init failed\n");
+ ret = PTR_ERR(spdif_priv->regmap);
+ return ret;
+ }
+
+ spdif_priv->irq = irq_of_parse_and_map(np, 0);
+ if (spdif_priv->irq == NO_IRQ) {
+ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
+ ret = -ENXIO;
+ goto error_iomap;
+ }
+
+ /* The 'name' should not have any slashes in it. */
+ ret = request_irq(spdif_priv->irq, spdif_isr, 0,
+ spdif_priv->name, spdif_priv);
+ if (ret) {
+ dev_err(&pdev->dev, "could not claim irq %u\n", spdif_priv->irq);
+ goto error_irqmap;
+ }
+
+ spdif_priv->coreclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(spdif_priv->coreclk)) {
+ dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
+ ret = PTR_ERR(spdif_priv->coreclk);
+ goto error_irqreq;
+ }
+
+ spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rx");
+ if (IS_ERR(spdif_priv->rxclk)) {
+ dev_warn(&pdev->dev, "using core clock as rx clk\n");
+ spdif_priv->rxclk = spdif_priv->coreclk;
+ }
+
+ spdif_priv->txclk_main = devm_clk_get(&pdev->dev, "tx");
+ if (IS_ERR(spdif_priv->txclk_main)) {
+ dev_warn(&pdev->dev, "using core clock as tx clk\n");
+ spdif_priv->txclk_main = spdif_priv->coreclk;
+ }
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
+ spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, rate[i]);
+ if (IS_ERR(spdif_priv->txclk[i])) {
+ dev_warn(&pdev->dev, "using tx clock as %s clk\n", rate[i]);
+ spdif_priv->txclk[i] = spdif_priv->txclk_main;
+ }
+ }
+
+ spdif_clksrc_index_lookup(spdif_priv);
+
+ /* We use regmap to control core clk, so no need to prepare it */
+ clk_prepare(spdif_priv->rxclk);
+ clk_prepare(spdif_priv->txclk_main);
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_prepare(spdif_priv->txclk[i]);
+
+ spdif_clk_cal_txdiv(spdif_priv);
+
+ /* initial spinlock for control data */
+ ctrl = &spdif_priv->fsl_spdif_control;
+ spin_lock_init(&ctrl->ctl_lock);
+
+ /* init tx channel status default value */
+ ctrl->ch_status[0] =
+ IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015;
+ ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
+ ctrl->ch_status[2] = 0x00;
+ ctrl->ch_status[3] =
+ IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
+
+ atomic_set(&spdif_priv->dpll_locked, 0);
+
+ spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
+ spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
+ spdif_priv->dma_params_tx.addr = res.start + REG_SPDIF_STL;
+ spdif_priv->dma_params_rx.addr = res.start + REG_SPDIF_SRL;
+
+ /* Register with ASoC */
+ dev_set_drvdata(&pdev->dev, spdif_priv);
+
+ ret = snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
+ &spdif_priv->cpu_dai_drv, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
+ goto error_dev;
+ }
+
+ ret = imx_pcm_dma_init(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
+ goto error_component;
+ }
+
+ return ret;
+
+error_component:
+ snd_soc_unregister_component(&pdev->dev);
+error_dev:
+ dev_set_drvdata(&pdev->dev, NULL);
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_unprepare(spdif_priv->txclk[i]);
+ clk_unprepare(spdif_priv->txclk_main);
+ clk_unprepare(spdif_priv->rxclk);
+error_irqreq:
+ free_irq(spdif_priv->irq, spdif_priv);
+error_irqmap:
+ irq_dispose_mapping(spdif_priv->irq);
+error_iomap:
+ iounmap(regs);
+
+ return ret;
+}
+
+static int fsl_spdif_remove(struct platform_device *pdev)
+{
+ struct fsl_spdif_priv *spdif_priv = platform_get_drvdata(pdev);
+ int i;
+
+ imx_pcm_dma_exit(pdev);
+ snd_soc_unregister_component(&pdev->dev);
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_unprepare(spdif_priv->txclk[i]);
+ clk_unprepare(spdif_priv->txclk_main);
+ clk_unprepare(spdif_priv->rxclk);
+
+ free_irq(spdif_priv->irq, spdif_priv);
+ irq_dispose_mapping(spdif_priv->irq);
+
+ dev_set_drvdata(&pdev->dev, NULL);
+
+ return 0;
+}
+
+static const struct of_device_id fsl_spdif_dt_ids[] = {
+ { .compatible = "fsl,imx35-spdif", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
+
+static struct platform_driver fsl_spdif_driver = {
+ .driver = {
+ .name = "fsl-spdif-dai",
+ .owner = THIS_MODULE,
+ .of_match_table = fsl_spdif_dt_ids,
+ },
+ .probe = fsl_spdif_probe,
+ .remove = fsl_spdif_remove,
+};
+
+module_platform_driver(fsl_spdif_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:fsl-spdif-dai");
diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h
new file mode 100644
index 0000000..df183fb
--- /dev/null
+++ b/sound/soc/fsl/fsl_spdif.h
@@ -0,0 +1,224 @@
+/*
+ * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Nicolin Chen <b42378@freescale.com>
+ *
+ * Based on fsl_ssi.h
+ * Author: Timur Tabi <timur@freescale.com>
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef _FSL_SPDIF_DAI_H
+#define _FSL_SPDIF_DAI_H
+
+/* S/PDIF Register Map */
+#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
+#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
+#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
+#define REG_SPDIF_SIE 0xc /* InterruptEn Register */
+#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
+#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
+#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
+#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
+#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
+#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
+#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
+#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
+#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
+#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
+#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
+#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
+#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
+#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
+
+
+/* SPDIF Configuration register */
+#define SCR_RXFIFO_CTL_OFFSET 23
+#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
+#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
+#define SCR_RXFIFO_OFF_OFFSET 22
+#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
+#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
+#define SCR_RXFIFO_RST_OFFSET 21
+#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
+#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
+#define SCR_RXFIFO_FSEL_OFFSET 19
+#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_AUTOSYNC_OFFSET 18
+#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
+#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_AUTOSYNC_OFFSET 17
+#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_FSEL_OFFSET 15
+#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_LOW_POWER (1 << 13)
+#define SCR_SOFT_RESET (1 << 12)
+#define SCR_TXFIFO_CTRL_OFFSET 10
+#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_DMA_RX_EN_OFFSET 9
+#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
+#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
+#define SCR_DMA_TX_EN_OFFSET 8
+#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
+#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
+#define SCR_VAL_OFFSET 5
+#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
+#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
+#define SCR_TXSEL_OFFSET 2
+#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
+#define SCR_USRC_SEL_OFFSET 0x0
+#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
+
+/* SPDIF CDText control */
+#define SRCD_CD_USER_OFFSET 1
+#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
+
+/* SPDIF Phase Configuration register */
+#define SRPC_DPLL_LOCKED (1 << 6)
+#define SRPC_CLKSRC_SEL_OFFSET 7
+#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
+#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) & SRPC_CLKSRC_SEL_MASK)
+#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
+#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
+#define SRPC_GAINSEL_OFFSET 3
+#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
+#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) & SRPC_GAINSEL_MASK)
+
+/* SPDIF rx clock source */
+enum spdif_rxclk_src {
+ SRPC_CLKSRC_0 = 0,
+ SRPC_CLKSRC_1,
+ SRPC_CLKSRC_2,
+ SRPC_CLKSRC_3,
+ SRPC_CLKSRC_4,
+ SRPC_CLKSRC_5,
+ SRPC_CLKSRC_6,
+ SRPC_CLKSRC_7,
+ SRPC_CLKSRC_8,
+ SRPC_CLKSRC_9,
+ SRPC_CLKSRC_10,
+ SRPC_CLKSRC_11,
+ SRPC_CLKSRC_12,
+ SRPC_CLKSRC_13,
+ SRPC_CLKSRC_14,
+ SRPC_CLKSRC_15,
+};
+#define SRPC_CLKSRC_MAX (SRPC_CLKSRC_15 + 1)
+#define DEFAULT_RXCLK_SRC SRPC_CLKSRC_0
+
+enum spdif_gainsel {
+ GAINSEL_MULTI_24 = 0,
+ GAINSEL_MULTI_16,
+ GAINSEL_MULTI_12,
+ GAINSEL_MULTI_8,
+ GAINSEL_MULTI_6,
+ GAINSEL_MULTI_4,
+ GAINSEL_MULTI_3,
+};
+#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
+#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
+
+/* SPDIF interrupt mask define */
+#define INT_DPLL_LOCKED (1 << 20)
+#define INT_TXFIFO_UNOV (1 << 19)
+#define INT_TXFIFO_RESYNC (1 << 18)
+#define INT_CNEW (1 << 17)
+#define INT_VAL_NOGOOD (1 << 16)
+#define INT_SYM_ERR (1 << 15)
+#define INT_BIT_ERR (1 << 14)
+#define INT_URX_FUL (1 << 10)
+#define INT_URX_OV (1 << 9)
+#define INT_QRX_FUL (1 << 8)
+#define INT_QRX_OV (1 << 7)
+#define INT_UQ_SYNC (1 << 6)
+#define INT_UQ_ERR (1 << 5)
+#define INT_RXFIFO_UNOV (1 << 4)
+#define INT_RXFIFO_RESYNC (1 << 3)
+#define INT_LOSS_LOCK (1 << 2)
+#define INT_TX_EM (1 << 1)
+#define INT_RXFIFO_FUL (1 << 0)
+
+/* SPDIF Clock register */
+#define STC_SYSCLK_DIV_OFFSET 11
+#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
+#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK)
+#define STC_TXCLK_SRC_OFFSET 8
+#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
+#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)
+#define STC_TXCLK_ALL_EN_OFFSET 7
+#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
+#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
+#define STC_TXCLK_DIV_OFFSET 0
+#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
+#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_TXCLK_DIV_MASK)
+
+/* SPDIF tx clksrc */
+enum spdif_txclk_src {
+ STC_TXCLK_SRC_0 = 0,
+ STC_TXCLK_SRC_1,
+ STC_TXCLK_SRC_2,
+ STC_TXCLK_SRC_3,
+ STC_TXCLK_SRC_4,
+ STC_TXCLK_SRC_5,
+ STC_TXCLK_SRC_6,
+ STC_TXCLK_SRC_7,
+};
+#define STC_TXCLK_SRC_MAX (STC_TXCLK_SRC_7 + 1)
+#define DEFAULT_TXCLK_SRC STC_TXCLK_SRC_1
+
+/* SPDIF tx rate */
+enum spdif_txrate {
+ SPDIF_TXRATE_32000 = 0,
+ SPDIF_TXRATE_44100,
+ SPDIF_TXRATE_48000,
+};
+#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
+
+
+#define SPDIF_CSTATUS_BYTE 6
+#define SPDIF_UBITS_SIZE 96
+#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
+
+
+#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_44100 | \
+ SNDRV_PCM_RATE_48000)
+
+#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
+ SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_44100 | \
+ SNDRV_PCM_RATE_48000 | \
+ SNDRV_PCM_RATE_64000 | \
+ SNDRV_PCM_RATE_96000)
+
+#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S20_3LE | \
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
+
+#endif /* _FSL_SPDIF_DAI_H */
--
1.7.1
^ permalink raw reply related
* Re: [alsa-devel] [PATCH v4 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
From: Shawn Guo @ 2013-08-15 9:24 UTC (permalink / raw)
To: Nicolin Chen
Cc: devicetree, alsa-devel, lars, Stephen Warren, linuxppc-dev, timur,
rob.herring, broonie, p.zabel, Fabio Estevam
In-Reply-To: <20130815021823.GA1846@MrMyself>
On Thu, Aug 15, 2013 at 10:18:23AM +0800, Nicolin Chen wrote:
> Hi Stephen,
>
> On Wed, Aug 14, 2013 at 09:47:19AM -0600, Stephen Warren wrote:
> > If the clock source name list is different, then it needs a different
> > compatible value, so that each compatible value can specify which clock
> > names are required.
> >
> > Also, the compatible value itself should always include the exact HW
> > that's present (most specific HW version), as well as any other HW it's
> > compatible with.
>
> Thank you for the comments. Yes, I did so in v1-v3, but after rethinking
> about the situation (Actually both the HW version and the clock mux itself
> are same, just the clock sources connecting to the mux might be different),
> so I decided to do this by abstracting the driver from those source info
> and letting DT binding to pass such information. Because I think putting
> the clock sources into the driver differed by compatible value would make
> the driver more like SoC-specified, not the ideal way -- SoC-independent,
> since the clock sources are based on SoC design, not on itself.
+1
It's pretty much the differences at SoC integration level not the IP
itself, and it just happens to be handled in a register of the IP.
Shawn
^ permalink raw reply
* Re: [PATCH] Revert "cxgb3: Check and handle the dma mapping errors"
From: David Miller @ 2013-08-15 8:24 UTC (permalink / raw)
To: divy; +Cc: santosh, fenlason, aik, netdev, linuxppc-dev, linux-kernel,
torvalds
In-Reply-To: <520BA8E4.3010406@chelsio.com>
From: Divy Le ray <divy@chelsio.com>
Date: Wed, 14 Aug 2013 08:57:24 -0700
> On 08/14/2013 02:19 AM, Alexey Kardashevskiy wrote:
>> This reverts commit f83331bab149e29fa2c49cf102c0cd8c3f1ce9f9.
>>
>> As the tests PPC64 (powernv platform) show, IOMMU pages are leaking
>> when transferring big amount of small packets (<=64 bytes),
>> "ping -f" and waiting for 15 seconds is the simplest way to confirm
>> the bug.
>>
>> Cc: Linus Torvalds<torvalds@linux-foundation.org>
>> Cc: Santosh Rastapur<santosh@chelsio.com>
>> Cc: Jay Fenlason<fenlason@redhat.com>
>> Cc: David S. Miller<davem@davemloft.net>
>> Cc: Divy Le ray<divy@chelsio.com>
>> Signed-off-by: Alexey Kardashevskiy<aik@ozlabs.ru>
>
> Acked-by: Divy Le Ray <divy@chelsio.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH 03/10] KVM: PPC: reserve a capability and ioctl numbers for realmode VFIO
From: Alexander Graf @ 2013-08-15 7:56 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: kvm, linux-doc, linux-kernel, kvm-ppc, Paul Mackerras,
linuxppc-dev
In-Reply-To: <520C8947.4020906@ozlabs.ru>
On 15.08.2013, at 09:54, Alexey Kardashevskiy wrote:
> On 08/15/2013 05:43 PM, Alexander Graf wrote:
>>=20
>> On 15.08.2013, at 09:42, Alexey Kardashevskiy wrote:
>>=20
>>> On 08/15/2013 05:25 PM, Alexander Graf wrote:
>>>>=20
>>>> On 15.08.2013, at 09:24, Alexander Graf wrote:
>>>>=20
>>>>>=20
>>>>> On 15.08.2013, at 09:22, Alexey Kardashevskiy wrote:
>>>>>=20
>>>>>> On 08/15/2013 05:16 PM, Alexander Graf wrote:
>>>>>>>=20
>>>>>>> On 01.08.2013, at 06:44, Alexey Kardashevskiy wrote:
>>>>>>>=20
>>>>>>>> This is to reserve a capablity number for upcoming support
>>>>>>>> of VFIO-IOMMU DMA operations in real mode.
>>>>>>>>=20
>>>>>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>>>>>>=20
>>>>>>>> ---
>>>>>>>> Changes:
>>>>>>>> 2013/07/16:
>>>>>>>> * changed the number
>>>>>>>>=20
>>>>>>>> 2013/07/11:
>>>>>>>> * changed order in a file, added comment about a gap in ioctl =
number
>>>>>>>>=20
>>>>>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>>>>>> ---
>>>>>>>> include/uapi/linux/kvm.h | 4 ++++
>>>>>>>> 1 file changed, 4 insertions(+)
>>>>>>>>=20
>>>>>>>> diff --git a/include/uapi/linux/kvm.h =
b/include/uapi/linux/kvm.h
>>>>>>>> index 99c2533..53c3f1f 100644
>>>>>>>> --- a/include/uapi/linux/kvm.h
>>>>>>>> +++ b/include/uapi/linux/kvm.h
>>>>>>>> @@ -668,6 +668,7 @@ struct kvm_ppc_smmu_info {
>>>>>>>> #define KVM_CAP_IRQ_XICS 92
>>>>>>>> #define KVM_CAP_ARM_EL1_32BIT 93
>>>>>>>> #define KVM_CAP_SPAPR_MULTITCE 94
>>>>>>>> +#define KVM_CAP_SPAPR_TCE_IOMMU 95
>>>>>>>>=20
>>>>>>>> #ifdef KVM_CAP_IRQ_ROUTING
>>>>>>>>=20
>>>>>>>> @@ -933,6 +934,9 @@ struct kvm_s390_ucas_mapping {
>>>>>>>> #define KVM_ARM_SET_DEVICE_ADDR _IOW(KVMIO, 0xab, =
struct kvm_arm_device_addr)
>>>>>>>> /* Available with KVM_CAP_PPC_RTAS */
>>>>>>>> #define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct =
kvm_rtas_token_args)
>>>>>>>> +/* 0xad and 0xaf are already taken */
>>>>>>>=20
>>>>>>> so 0xad and 0xaf are already taken? where?
>>>>>>=20
>>>>>> Mistype :( s/af/ae/
>>>>>>=20
>>>>>> They are taken in this file:
>>>>>>=20
>>>>>> 1016 /* VM is being stopped by host */
>>>>>> 1017 #define KVM_KVMCLOCK_CTRL _IO(KVMIO, 0xad)
>>>>>> 1018 #define KVM_ARM_VCPU_INIT _IOW(KVMIO, 0xae, struct =
kvm_vcpu_init)
>>>>>=20
>>>>> Could you please make sure that whoever reads the comment in a =
year still knows where to look? :)
>>>>=20
>>>> Something like
>>>>=20
>>>> /* 0xad is taken by KVM_KVMCLOCK_CTRL */
>>>> /* 0xaf is taken by KVM_ARM_VCPU_INIT */
>>>=20
>>>=20
>>> Missed this mail and reposted without this comment but updated =
commit
>>> message saying where they are used. Repost again?
>>=20
>> The commit message doesn't really help, since you don't see that one =
when you read the header file later. So yes, please.
>=20
>=20
> Ok. Reposted as "[PATCH v8] KVM: PPC: reserve a capability and ioctl
> numbers for realmode VFIO". Thank you. Sorry for my disturbing =
ignorance.
In this case it's just sloppyness which disturbs be a lot less, as I'm =
sloppy myself :).
Alex
^ permalink raw reply
* Re: [PATCH 03/10] KVM: PPC: reserve a capability and ioctl numbers for realmode VFIO
From: Alexey Kardashevskiy @ 2013-08-15 7:54 UTC (permalink / raw)
To: Alexander Graf
Cc: kvm, linux-doc, linux-kernel, kvm-ppc, Paul Mackerras,
linuxppc-dev
In-Reply-To: <162759CE-0031-4571-A4A3-3BFE16445066@suse.de>
On 08/15/2013 05:43 PM, Alexander Graf wrote:
>
> On 15.08.2013, at 09:42, Alexey Kardashevskiy wrote:
>
>> On 08/15/2013 05:25 PM, Alexander Graf wrote:
>>>
>>> On 15.08.2013, at 09:24, Alexander Graf wrote:
>>>
>>>>
>>>> On 15.08.2013, at 09:22, Alexey Kardashevskiy wrote:
>>>>
>>>>> On 08/15/2013 05:16 PM, Alexander Graf wrote:
>>>>>>
>>>>>> On 01.08.2013, at 06:44, Alexey Kardashevskiy wrote:
>>>>>>
>>>>>>> This is to reserve a capablity number for upcoming support
>>>>>>> of VFIO-IOMMU DMA operations in real mode.
>>>>>>>
>>>>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>>>>>
>>>>>>> ---
>>>>>>> Changes:
>>>>>>> 2013/07/16:
>>>>>>> * changed the number
>>>>>>>
>>>>>>> 2013/07/11:
>>>>>>> * changed order in a file, added comment about a gap in ioctl number
>>>>>>>
>>>>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>>>>> ---
>>>>>>> include/uapi/linux/kvm.h | 4 ++++
>>>>>>> 1 file changed, 4 insertions(+)
>>>>>>>
>>>>>>> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
>>>>>>> index 99c2533..53c3f1f 100644
>>>>>>> --- a/include/uapi/linux/kvm.h
>>>>>>> +++ b/include/uapi/linux/kvm.h
>>>>>>> @@ -668,6 +668,7 @@ struct kvm_ppc_smmu_info {
>>>>>>> #define KVM_CAP_IRQ_XICS 92
>>>>>>> #define KVM_CAP_ARM_EL1_32BIT 93
>>>>>>> #define KVM_CAP_SPAPR_MULTITCE 94
>>>>>>> +#define KVM_CAP_SPAPR_TCE_IOMMU 95
>>>>>>>
>>>>>>> #ifdef KVM_CAP_IRQ_ROUTING
>>>>>>>
>>>>>>> @@ -933,6 +934,9 @@ struct kvm_s390_ucas_mapping {
>>>>>>> #define KVM_ARM_SET_DEVICE_ADDR _IOW(KVMIO, 0xab, struct kvm_arm_device_addr)
>>>>>>> /* Available with KVM_CAP_PPC_RTAS */
>>>>>>> #define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct kvm_rtas_token_args)
>>>>>>> +/* 0xad and 0xaf are already taken */
>>>>>>
>>>>>> so 0xad and 0xaf are already taken? where?
>>>>>
>>>>> Mistype :( s/af/ae/
>>>>>
>>>>> They are taken in this file:
>>>>>
>>>>> 1016 /* VM is being stopped by host */
>>>>> 1017 #define KVM_KVMCLOCK_CTRL _IO(KVMIO, 0xad)
>>>>> 1018 #define KVM_ARM_VCPU_INIT _IOW(KVMIO, 0xae, struct kvm_vcpu_init)
>>>>
>>>> Could you please make sure that whoever reads the comment in a year still knows where to look? :)
>>>
>>> Something like
>>>
>>> /* 0xad is taken by KVM_KVMCLOCK_CTRL */
>>> /* 0xaf is taken by KVM_ARM_VCPU_INIT */
>>
>>
>> Missed this mail and reposted without this comment but updated commit
>> message saying where they are used. Repost again?
>
> The commit message doesn't really help, since you don't see that one when you read the header file later. So yes, please.
Ok. Reposted as "[PATCH v8] KVM: PPC: reserve a capability and ioctl
numbers for realmode VFIO". Thank you. Sorry for my disturbing ignorance.
--
Alexey
^ permalink raw reply
* [PATCH v8] KVM: PPC: reserve a capability and ioctl numbers for realmode VFIO
From: Alexey Kardashevskiy @ 2013-08-15 7:49 UTC (permalink / raw)
To: linuxppc-dev
Cc: Gleb Natapov, kvm, Alexey Kardashevskiy, Alexander Graf,
linux-kernel, Paul Mackerras, David Gibson
This is to reserve a capablity number for upcoming support
of VFIO-IOMMU DMA operations in real mode.
The last ioctl in the group which KVM_CREATE_SPAPR_TCE_IOMMU is added to
is 0xac, the next two numbers are taken - 0xad for KVM_KVMCLOCK_CTRL and
0xae for KVM_ARM_VCPU_INIT. So the KVM_CREATE_SPAPR_TCE_IOMMU ioclt gets
0xaf.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
2013/08/15 v8:
* fixed comment again
2013/08/15:
* fixed mistype in comments
* fixed commit message which says what uses ioctls 0xad and 0xae
2013/07/16:
* changed the number
2013/07/11:
* changed order in a file, added comment about a gap in ioctl number
---
include/uapi/linux/kvm.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 99c2533..bd94127 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -668,6 +668,7 @@ struct kvm_ppc_smmu_info {
#define KVM_CAP_IRQ_XICS 92
#define KVM_CAP_ARM_EL1_32BIT 93
#define KVM_CAP_SPAPR_MULTITCE 94
+#define KVM_CAP_SPAPR_TCE_IOMMU 95
#ifdef KVM_CAP_IRQ_ROUTING
@@ -933,6 +934,11 @@ struct kvm_s390_ucas_mapping {
#define KVM_ARM_SET_DEVICE_ADDR _IOW(KVMIO, 0xab, struct kvm_arm_device_addr)
/* Available with KVM_CAP_PPC_RTAS */
#define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct kvm_rtas_token_args)
+/* 0xad is taken by KVM_KVMCLOCK_CTRL */
+/* 0xae is taken by KVM_ARM_VCPU_INIT */
+/* Available with KVM_CAP_SPAPR_TCE_IOMMU */
+#define KVM_CREATE_SPAPR_TCE_IOMMU _IOW(KVMIO, 0xaf, \
+ struct kvm_create_spapr_tce_iommu)
/* ioctl for vm fd */
#define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device)
--
1.8.3.2
^ permalink raw reply related
* Re: [PATCH 03/10] KVM: PPC: reserve a capability and ioctl numbers for realmode VFIO
From: Alexander Graf @ 2013-08-15 7:43 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: kvm, linux-doc, linux-kernel, kvm-ppc, Paul Mackerras,
linuxppc-dev
In-Reply-To: <520C8661.2000406@ozlabs.ru>
On 15.08.2013, at 09:42, Alexey Kardashevskiy wrote:
> On 08/15/2013 05:25 PM, Alexander Graf wrote:
>>=20
>> On 15.08.2013, at 09:24, Alexander Graf wrote:
>>=20
>>>=20
>>> On 15.08.2013, at 09:22, Alexey Kardashevskiy wrote:
>>>=20
>>>> On 08/15/2013 05:16 PM, Alexander Graf wrote:
>>>>>=20
>>>>> On 01.08.2013, at 06:44, Alexey Kardashevskiy wrote:
>>>>>=20
>>>>>> This is to reserve a capablity number for upcoming support
>>>>>> of VFIO-IOMMU DMA operations in real mode.
>>>>>>=20
>>>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>>>>=20
>>>>>> ---
>>>>>> Changes:
>>>>>> 2013/07/16:
>>>>>> * changed the number
>>>>>>=20
>>>>>> 2013/07/11:
>>>>>> * changed order in a file, added comment about a gap in ioctl =
number
>>>>>>=20
>>>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>>>> ---
>>>>>> include/uapi/linux/kvm.h | 4 ++++
>>>>>> 1 file changed, 4 insertions(+)
>>>>>>=20
>>>>>> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
>>>>>> index 99c2533..53c3f1f 100644
>>>>>> --- a/include/uapi/linux/kvm.h
>>>>>> +++ b/include/uapi/linux/kvm.h
>>>>>> @@ -668,6 +668,7 @@ struct kvm_ppc_smmu_info {
>>>>>> #define KVM_CAP_IRQ_XICS 92
>>>>>> #define KVM_CAP_ARM_EL1_32BIT 93
>>>>>> #define KVM_CAP_SPAPR_MULTITCE 94
>>>>>> +#define KVM_CAP_SPAPR_TCE_IOMMU 95
>>>>>>=20
>>>>>> #ifdef KVM_CAP_IRQ_ROUTING
>>>>>>=20
>>>>>> @@ -933,6 +934,9 @@ struct kvm_s390_ucas_mapping {
>>>>>> #define KVM_ARM_SET_DEVICE_ADDR _IOW(KVMIO, 0xab, struct =
kvm_arm_device_addr)
>>>>>> /* Available with KVM_CAP_PPC_RTAS */
>>>>>> #define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct =
kvm_rtas_token_args)
>>>>>> +/* 0xad and 0xaf are already taken */
>>>>>=20
>>>>> so 0xad and 0xaf are already taken? where?
>>>>=20
>>>> Mistype :( s/af/ae/
>>>>=20
>>>> They are taken in this file:
>>>>=20
>>>> 1016 /* VM is being stopped by host */
>>>> 1017 #define KVM_KVMCLOCK_CTRL _IO(KVMIO, 0xad)
>>>> 1018 #define KVM_ARM_VCPU_INIT _IOW(KVMIO, 0xae, struct =
kvm_vcpu_init)
>>>=20
>>> Could you please make sure that whoever reads the comment in a year =
still knows where to look? :)
>>=20
>> Something like
>>=20
>> /* 0xad is taken by KVM_KVMCLOCK_CTRL */
>> /* 0xaf is taken by KVM_ARM_VCPU_INIT */
>=20
>=20
> Missed this mail and reposted without this comment but updated commit
> message saying where they are used. Repost again?
The commit message doesn't really help, since you don't see that one =
when you read the header file later. So yes, please.
Alex
^ permalink raw reply
* Re: [PATCH 03/10] KVM: PPC: reserve a capability and ioctl numbers for realmode VFIO
From: Alexey Kardashevskiy @ 2013-08-15 7:42 UTC (permalink / raw)
To: Alexander Graf
Cc: kvm, linux-doc, linux-kernel, kvm-ppc, Paul Mackerras,
linuxppc-dev
In-Reply-To: <836F3C3A-0031-4A16-B0CE-E6C1BA4925E4@suse.de>
On 08/15/2013 05:25 PM, Alexander Graf wrote:
>
> On 15.08.2013, at 09:24, Alexander Graf wrote:
>
>>
>> On 15.08.2013, at 09:22, Alexey Kardashevskiy wrote:
>>
>>> On 08/15/2013 05:16 PM, Alexander Graf wrote:
>>>>
>>>> On 01.08.2013, at 06:44, Alexey Kardashevskiy wrote:
>>>>
>>>>> This is to reserve a capablity number for upcoming support
>>>>> of VFIO-IOMMU DMA operations in real mode.
>>>>>
>>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>>>
>>>>> ---
>>>>> Changes:
>>>>> 2013/07/16:
>>>>> * changed the number
>>>>>
>>>>> 2013/07/11:
>>>>> * changed order in a file, added comment about a gap in ioctl number
>>>>>
>>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>>> ---
>>>>> include/uapi/linux/kvm.h | 4 ++++
>>>>> 1 file changed, 4 insertions(+)
>>>>>
>>>>> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
>>>>> index 99c2533..53c3f1f 100644
>>>>> --- a/include/uapi/linux/kvm.h
>>>>> +++ b/include/uapi/linux/kvm.h
>>>>> @@ -668,6 +668,7 @@ struct kvm_ppc_smmu_info {
>>>>> #define KVM_CAP_IRQ_XICS 92
>>>>> #define KVM_CAP_ARM_EL1_32BIT 93
>>>>> #define KVM_CAP_SPAPR_MULTITCE 94
>>>>> +#define KVM_CAP_SPAPR_TCE_IOMMU 95
>>>>>
>>>>> #ifdef KVM_CAP_IRQ_ROUTING
>>>>>
>>>>> @@ -933,6 +934,9 @@ struct kvm_s390_ucas_mapping {
>>>>> #define KVM_ARM_SET_DEVICE_ADDR _IOW(KVMIO, 0xab, struct kvm_arm_device_addr)
>>>>> /* Available with KVM_CAP_PPC_RTAS */
>>>>> #define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct kvm_rtas_token_args)
>>>>> +/* 0xad and 0xaf are already taken */
>>>>
>>>> so 0xad and 0xaf are already taken? where?
>>>
>>> Mistype :( s/af/ae/
>>>
>>> They are taken in this file:
>>>
>>> 1016 /* VM is being stopped by host */
>>> 1017 #define KVM_KVMCLOCK_CTRL _IO(KVMIO, 0xad)
>>> 1018 #define KVM_ARM_VCPU_INIT _IOW(KVMIO, 0xae, struct kvm_vcpu_init)
>>
>> Could you please make sure that whoever reads the comment in a year still knows where to look? :)
>
> Something like
>
> /* 0xad is taken by KVM_KVMCLOCK_CTRL */
> /* 0xaf is taken by KVM_ARM_VCPU_INIT */
Missed this mail and reposted without this comment but updated commit
message saying where they are used. Repost again?
--
Alexey
^ permalink raw reply
* Re: [PATCH 03/10] KVM: PPC: reserve a capability and ioctl numbers for realmode VFIO
From: Alexander Graf @ 2013-08-15 7:25 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: kvm, linux-doc, linux-kernel, kvm-ppc, Paul Mackerras,
linuxppc-dev
In-Reply-To: <552A034A-CD3F-4737-B08A-E892E6420B83@suse.de>
On 15.08.2013, at 09:24, Alexander Graf wrote:
>=20
> On 15.08.2013, at 09:22, Alexey Kardashevskiy wrote:
>=20
>> On 08/15/2013 05:16 PM, Alexander Graf wrote:
>>>=20
>>> On 01.08.2013, at 06:44, Alexey Kardashevskiy wrote:
>>>=20
>>>> This is to reserve a capablity number for upcoming support
>>>> of VFIO-IOMMU DMA operations in real mode.
>>>>=20
>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>>=20
>>>> ---
>>>> Changes:
>>>> 2013/07/16:
>>>> * changed the number
>>>>=20
>>>> 2013/07/11:
>>>> * changed order in a file, added comment about a gap in ioctl =
number
>>>>=20
>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>> ---
>>>> include/uapi/linux/kvm.h | 4 ++++
>>>> 1 file changed, 4 insertions(+)
>>>>=20
>>>> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
>>>> index 99c2533..53c3f1f 100644
>>>> --- a/include/uapi/linux/kvm.h
>>>> +++ b/include/uapi/linux/kvm.h
>>>> @@ -668,6 +668,7 @@ struct kvm_ppc_smmu_info {
>>>> #define KVM_CAP_IRQ_XICS 92
>>>> #define KVM_CAP_ARM_EL1_32BIT 93
>>>> #define KVM_CAP_SPAPR_MULTITCE 94
>>>> +#define KVM_CAP_SPAPR_TCE_IOMMU 95
>>>>=20
>>>> #ifdef KVM_CAP_IRQ_ROUTING
>>>>=20
>>>> @@ -933,6 +934,9 @@ struct kvm_s390_ucas_mapping {
>>>> #define KVM_ARM_SET_DEVICE_ADDR _IOW(KVMIO, 0xab, struct =
kvm_arm_device_addr)
>>>> /* Available with KVM_CAP_PPC_RTAS */
>>>> #define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct =
kvm_rtas_token_args)
>>>> +/* 0xad and 0xaf are already taken */
>>>=20
>>> so 0xad and 0xaf are already taken? where?
>>=20
>> Mistype :( s/af/ae/
>>=20
>> They are taken in this file:
>>=20
>> 1016 /* VM is being stopped by host */
>> 1017 #define KVM_KVMCLOCK_CTRL _IO(KVMIO, 0xad)
>> 1018 #define KVM_ARM_VCPU_INIT _IOW(KVMIO, 0xae, struct =
kvm_vcpu_init)
>=20
> Could you please make sure that whoever reads the comment in a year =
still knows where to look? :)
Something like
/* 0xad is taken by KVM_KVMCLOCK_CTRL */
/* 0xaf is taken by KVM_ARM_VCPU_INIT */
Alex
^ permalink raw reply
* Re: [PATCH 03/10] KVM: PPC: reserve a capability and ioctl numbers for realmode VFIO
From: Alexander Graf @ 2013-08-15 7:24 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: kvm, linux-doc, linux-kernel, kvm-ppc, Paul Mackerras,
linuxppc-dev
In-Reply-To: <520C81BE.70002@ozlabs.ru>
On 15.08.2013, at 09:22, Alexey Kardashevskiy wrote:
> On 08/15/2013 05:16 PM, Alexander Graf wrote:
>>=20
>> On 01.08.2013, at 06:44, Alexey Kardashevskiy wrote:
>>=20
>>> This is to reserve a capablity number for upcoming support
>>> of VFIO-IOMMU DMA operations in real mode.
>>>=20
>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>=20
>>> ---
>>> Changes:
>>> 2013/07/16:
>>> * changed the number
>>>=20
>>> 2013/07/11:
>>> * changed order in a file, added comment about a gap in ioctl number
>>>=20
>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>> ---
>>> include/uapi/linux/kvm.h | 4 ++++
>>> 1 file changed, 4 insertions(+)
>>>=20
>>> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
>>> index 99c2533..53c3f1f 100644
>>> --- a/include/uapi/linux/kvm.h
>>> +++ b/include/uapi/linux/kvm.h
>>> @@ -668,6 +668,7 @@ struct kvm_ppc_smmu_info {
>>> #define KVM_CAP_IRQ_XICS 92
>>> #define KVM_CAP_ARM_EL1_32BIT 93
>>> #define KVM_CAP_SPAPR_MULTITCE 94
>>> +#define KVM_CAP_SPAPR_TCE_IOMMU 95
>>>=20
>>> #ifdef KVM_CAP_IRQ_ROUTING
>>>=20
>>> @@ -933,6 +934,9 @@ struct kvm_s390_ucas_mapping {
>>> #define KVM_ARM_SET_DEVICE_ADDR _IOW(KVMIO, 0xab, struct =
kvm_arm_device_addr)
>>> /* Available with KVM_CAP_PPC_RTAS */
>>> #define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct =
kvm_rtas_token_args)
>>> +/* 0xad and 0xaf are already taken */
>>=20
>> so 0xad and 0xaf are already taken? where?
>=20
> Mistype :( s/af/ae/
>=20
> They are taken in this file:
>=20
> 1016 /* VM is being stopped by host */
> 1017 #define KVM_KVMCLOCK_CTRL _IO(KVMIO, 0xad)
> 1018 #define KVM_ARM_VCPU_INIT _IOW(KVMIO, 0xae, struct =
kvm_vcpu_init)
Could you please make sure that whoever reads the comment in a year =
still knows where to look? :)
>=20
>>=20
>>> +/* Available with KVM_CAP_SPAPR_TCE_IOMMU */
>>> +#define KVM_CREATE_SPAPR_TCE_IOMMU _IOW(KVMIO, 0xaf, struct =
kvm_create_spapr_tce_iommu)
>>=20
>> and why is this one 0xaf then?
>=20
> Sorry, mistype. My bad. Sorry again.
No worries - just repost this single patch with the fixed comment.
Alex
^ permalink raw reply
* Re: [PATCH 03/10] KVM: PPC: reserve a capability and ioctl numbers for realmode VFIO
From: Alexey Kardashevskiy @ 2013-08-15 7:22 UTC (permalink / raw)
To: Alexander Graf
Cc: kvm, linux-doc, linux-kernel, kvm-ppc, Paul Mackerras,
linuxppc-dev
In-Reply-To: <ED8250FB-B0A8-4C32-A960-20ADB5742D2B@suse.de>
On 08/15/2013 05:16 PM, Alexander Graf wrote:
>
> On 01.08.2013, at 06:44, Alexey Kardashevskiy wrote:
>
>> This is to reserve a capablity number for upcoming support
>> of VFIO-IOMMU DMA operations in real mode.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>
>> ---
>> Changes:
>> 2013/07/16:
>> * changed the number
>>
>> 2013/07/11:
>> * changed order in a file, added comment about a gap in ioctl number
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> include/uapi/linux/kvm.h | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
>> index 99c2533..53c3f1f 100644
>> --- a/include/uapi/linux/kvm.h
>> +++ b/include/uapi/linux/kvm.h
>> @@ -668,6 +668,7 @@ struct kvm_ppc_smmu_info {
>> #define KVM_CAP_IRQ_XICS 92
>> #define KVM_CAP_ARM_EL1_32BIT 93
>> #define KVM_CAP_SPAPR_MULTITCE 94
>> +#define KVM_CAP_SPAPR_TCE_IOMMU 95
>>
>> #ifdef KVM_CAP_IRQ_ROUTING
>>
>> @@ -933,6 +934,9 @@ struct kvm_s390_ucas_mapping {
>> #define KVM_ARM_SET_DEVICE_ADDR _IOW(KVMIO, 0xab, struct kvm_arm_device_addr)
>> /* Available with KVM_CAP_PPC_RTAS */
>> #define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct kvm_rtas_token_args)
>> +/* 0xad and 0xaf are already taken */
>
> so 0xad and 0xaf are already taken? where?
Mistype :( s/af/ae/
They are taken in this file:
1016 /* VM is being stopped by host */
1017 #define KVM_KVMCLOCK_CTRL _IO(KVMIO, 0xad)
1018 #define KVM_ARM_VCPU_INIT _IOW(KVMIO, 0xae, struct kvm_vcpu_init)
>
>> +/* Available with KVM_CAP_SPAPR_TCE_IOMMU */
>> +#define KVM_CREATE_SPAPR_TCE_IOMMU _IOW(KVMIO, 0xaf, struct kvm_create_spapr_tce_iommu)
>
> and why is this one 0xaf then?
Sorry, mistype. My bad. Sorry again.
>
> Alex
>
>>
>> /* ioctl for vm fd */
>> #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device)
>> --
>> 1.8.3.2
>>
>
--
Alexey
^ permalink raw reply
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