* Re: [PATCH 1/2] powerpc/85xx: introduce cornet_generic machine
From: Scott Wood @ 2013-09-12 18:44 UTC (permalink / raw)
To: Kevin Hao; +Cc: linuxppc
In-Reply-To: <1378969993-14991-2-git-send-email-haokexin@gmail.com>
On Thu, 2013-09-12 at 15:13 +0800, Kevin Hao wrote:
> In the current kernel, the board files for p2041rdb, p3041ds, p4080ds,
> p5020ds, p5040ds, t4240qds and b4qds are almost the same except the
> machine name. So this introduces a cornet_generic machine to support
> all these boards to avoid the code duplication.
>
> Signed-off-by: Kevin Hao <haokexin@gmail.com>
> ---
> This patch is based on http://patchwork.ozlabs.org/patch/274390/
>
> arch/powerpc/platforms/85xx/Kconfig | 10 ++++
> arch/powerpc/platforms/85xx/Makefile | 8 +--
> arch/powerpc/platforms/85xx/b4_qds.c | 97 --------------------------------
> arch/powerpc/platforms/85xx/corenet_ds.c | 86 ++++++++++++++++++++++++++++
> arch/powerpc/platforms/85xx/p2041_rdb.c | 87 ----------------------------
> arch/powerpc/platforms/85xx/p3041_ds.c | 89 -----------------------------
> arch/powerpc/platforms/85xx/p4080_ds.c | 87 ----------------------------
> arch/powerpc/platforms/85xx/p5020_ds.c | 93 ------------------------------
> arch/powerpc/platforms/85xx/p5040_ds.c | 84 ---------------------------
> arch/powerpc/platforms/85xx/t4240_qds.c | 93 ------------------------------
> 10 files changed, 97 insertions(+), 637 deletions(-)
> delete mode 100644 arch/powerpc/platforms/85xx/b4_qds.c
> delete mode 100644 arch/powerpc/platforms/85xx/p2041_rdb.c
> delete mode 100644 arch/powerpc/platforms/85xx/p3041_ds.c
> delete mode 100644 arch/powerpc/platforms/85xx/p4080_ds.c
> delete mode 100644 arch/powerpc/platforms/85xx/p5020_ds.c
> delete mode 100644 arch/powerpc/platforms/85xx/p5040_ds.c
> delete mode 100644 arch/powerpc/platforms/85xx/t4240_qds.c
Why not merge patch 2/2 with this?
Did you use -M -C with git format-patch?
> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
> index de2eb93..3bee943 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -228,6 +228,7 @@ config P2041_RDB
> select GPIO_MPC8XXX
> select HAS_RAPIDIO
> select PPC_EPAPR_HV_PIC
> + select CORENET_GENERIC
> help
> This option enables support for the P2041 RDB board
>
> @@ -241,6 +242,7 @@ config P3041_DS
> select GPIO_MPC8XXX
> select HAS_RAPIDIO
> select PPC_EPAPR_HV_PIC
> + select CORENET_GENERIC
> help
> This option enables support for the P3041 DS board
>
> @@ -254,6 +256,7 @@ config P4080_DS
> select GPIO_MPC8XXX
> select HAS_RAPIDIO
> select PPC_EPAPR_HV_PIC
> + select CORENET_GENERIC
> help
> This option enables support for the P4080 DS board
>
> @@ -278,6 +281,7 @@ config P5020_DS
> select GPIO_MPC8XXX
> select HAS_RAPIDIO
> select PPC_EPAPR_HV_PIC
> + select CORENET_GENERIC
> help
> This option enables support for the P5020 DS board
>
> @@ -292,6 +296,7 @@ config P5040_DS
> select GPIO_MPC8XXX
> select HAS_RAPIDIO
> select PPC_EPAPR_HV_PIC
> + select CORENET_GENERIC
> help
> This option enables support for the P5040 DS board
>
> @@ -323,6 +328,7 @@ config T4240_QDS
> select GPIO_MPC8XXX
> select HAS_RAPIDIO
> select PPC_EPAPR_HV_PIC
> + select CORENET_GENERIC
> help
> This option enables support for the T4240 QDS board
>
> @@ -337,6 +343,7 @@ config B4_QDS
> select ARCH_REQUIRE_GPIOLIB
> select HAS_RAPIDIO
> select PPC_EPAPR_HV_PIC
> + select CORENET_GENERIC
> help
> This option enables support for the B4 QDS board
> The B4 application development system B4 QDS is a complete
> @@ -348,3 +355,6 @@ endif # FSL_SOC_BOOKE
>
> config TQM85xx
> bool
> +
> +config CORENET_GENERIC
> + bool
Why do we need separate kconfig symbols for each board, if they all
select the same code?
> +define_machine(corenet_generic) {
> + .name = "CORENET GENERIC",
No allcaps please.
-Scott
^ permalink raw reply
* Re: [PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB
From: Scott Wood @ 2013-09-12 18:44 UTC (permalink / raw)
To: Christophe Leroy; +Cc: linuxppc-dev, Paul Mackerras, linux-kernel
In-Reply-To: <201309121825.r8CIPrkI005690@localhost.localdomain>
On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote:
> This is a reorganisation of the setup of the TLB at kernel startup, in order
> to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 of MPC866
> and MPC885 reference manuals.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
>
> diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S linux-3.11/arch/powerpc/kernel/head_8xx.S
> --- linux-3.11.org/arch/powerpc/kernel/head_8xx.S 2013-09-02 22:46:10.000000000 +0200
> +++ linux-3.11/arch/powerpc/kernel/head_8xx.S 2013-09-09 11:28:54.000000000 +0200
> @@ -785,27 +785,24 @@
> * these mappings is mapped by page tables.
> */
> initial_mmu:
> - tlbia /* Invalidate all TLB entries */
> -/* Always pin the first 8 MB ITLB to prevent ITLB
> - misses while mucking around with SRR0/SRR1 in asm
> -*/
> - lis r8, MI_RSV4I@h
> - ori r8, r8, 0x1c00
> -
> + lis r8, MI_RESETVAL@h
> mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
>
> -#ifdef CONFIG_PIN_TLB
> - lis r10, (MD_RSV4I | MD_RESETVAL)@h
> - ori r10, r10, 0x1c00
> - mr r8, r10
> -#else
> lis r10, MD_RESETVAL@h
> -#endif
> #ifndef CONFIG_8xx_COPYBACK
> oris r10, r10, MD_WTDEF@h
> #endif
> mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
>
> + tlbia /* Invalidate all TLB entries */
Is this change to make sure we invalidate everything even if the
bootloader set RSV4I?
> + ori r8, r8, 0x1c00
> + mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
> +#ifdef CONFIG_PIN_TLB
> + ori r10, r10, 0x1c00
> + mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
> +#endif
Still 0x1c00?
> /* Now map the lower 8 Meg into the TLBs. For this quick hack,
> * we can load the instruction and data TLB registers with the
> * same values.
> @@ -825,6 +822,12 @@
> mtspr SPRN_MI_AP, r8
> mtspr SPRN_MD_AP, r8
>
> + /* Always pin the first 8 MB ITLB to prevent ITLB
> + * misses while mucking around with SRR0/SRR1 in asm
> + */
> + lis r8, (MI_RSV4I | MI_RESETVAL)@h
> + mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
Entry 0 is not pinnable.
-Scott
^ permalink raw reply
* [PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB
From: Christophe Leroy @ 2013-09-12 18:25 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, scottwood
Cc: linuxppc-dev, linux-kernel
This is a reorganisation of the setup of the TLB at kernel startup, in order
to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 of MPC866
and MPC885 reference manuals.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S linux-3.11/arch/powerpc/kernel/head_8xx.S
--- linux-3.11.org/arch/powerpc/kernel/head_8xx.S 2013-09-02 22:46:10.000000000 +0200
+++ linux-3.11/arch/powerpc/kernel/head_8xx.S 2013-09-09 11:28:54.000000000 +0200
@@ -785,27 +785,24 @@
* these mappings is mapped by page tables.
*/
initial_mmu:
- tlbia /* Invalidate all TLB entries */
-/* Always pin the first 8 MB ITLB to prevent ITLB
- misses while mucking around with SRR0/SRR1 in asm
-*/
- lis r8, MI_RSV4I@h
- ori r8, r8, 0x1c00
-
+ lis r8, MI_RESETVAL@h
mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
-#ifdef CONFIG_PIN_TLB
- lis r10, (MD_RSV4I | MD_RESETVAL)@h
- ori r10, r10, 0x1c00
- mr r8, r10
-#else
lis r10, MD_RESETVAL@h
-#endif
#ifndef CONFIG_8xx_COPYBACK
oris r10, r10, MD_WTDEF@h
#endif
mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
+ tlbia /* Invalidate all TLB entries */
+
+ ori r8, r8, 0x1c00
+ mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
+#ifdef CONFIG_PIN_TLB
+ ori r10, r10, 0x1c00
+ mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
+#endif
+
/* Now map the lower 8 Meg into the TLBs. For this quick hack,
* we can load the instruction and data TLB registers with the
* same values.
@@ -825,6 +822,12 @@
mtspr SPRN_MI_AP, r8
mtspr SPRN_MD_AP, r8
+ /* Always pin the first 8 MB ITLB to prevent ITLB
+ * misses while mucking around with SRR0/SRR1 in asm
+ */
+ lis r8, (MI_RSV4I | MI_RESETVAL)@h
+ mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
+
/* Map another 8 MByte at the IMMR to get the processor
* internal registers (among other things).
*/
@@ -870,7 +873,15 @@
mtspr SPRN_MD_TWC, r9
addis r11, r11, 0x0080 /* Add 8M */
mtspr SPRN_MD_RPN, r11
+
+ lis r10, (MD_RSV4I | MD_RESETVAL)@h
+#else
+ lis r10, MD_RESETVAL@h
#endif
+#ifndef CONFIG_8xx_COPYBACK
+ oris r10, r10, MD_WTDEF@h
+#endif
+ mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
/* Since the cache is enabled according to the information we
* just loaded into the TLB, invalidate and enable the caches here.
^ permalink raw reply
* Re: [PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle
From: Scott Wood @ 2013-09-12 18:06 UTC (permalink / raw)
To: Wang Dongsheng-B40534; +Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <ABB05CD9C9F68C46A5CEDC7F15439259010652F1@039-SN2MPN1-023.039d.mgd.msft.net>
On Wed, 2013-09-11 at 22:48 -0500, Wang Dongsheng-B40534 wrote:
>
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Thursday, September 12, 2013 7:04 AM
> > To: Wang Dongsheng-B40534
> > Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org
> > Subject: Re: [PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state and
> > altivec idle
> >
> > On Wed, 2013-09-11 at 13:56 +0800, Dongsheng Wang wrote:
> > > From: Wang Dongsheng <dongsheng.wang@freescale.com>
> > >
> > > Add a sys interface to enable/diable pw20 state or altivec idle, and
> > > control the wait entry time.
> > >
> > > Enable/Disable interface:
> > > 0, disable. 1, enable.
> > > /sys/devices/system/cpu/cpuX/pw20_state
> > > /sys/devices/system/cpu/cpuX/altivec_idle
> > >
> > > Set wait entry bit interface:
> > > bit value range 0~63, 0 bit is Mintime, 63 bit is Maxtime.
> > > /sys/devices/system/cpu/cpuX/pw20_wait_entry_bit
> > > /sys/devices/system/cpu/cpuX/altivec_idle_wait_entry_bit
> >
> > I'm no fan of the way powerpc does bit numbering, but don't flip it
> > around here -- you'll just cause confusion.
> >
> OK. 0 bit is maxtime, 63 bit is mintime.
>
> > Better yet, this interface should take real time units rather than a
> > timebase bit.
> >
> I think the real time is not suitable, because timebase bit does not correspond with
> real time.
It's a bit sloppy due to how the hardware works, but you could convert
it like you did in earlier patches. Semantically it should probably be
the minimum time to wait before entering the low power state.
> > Also, you disable the power saving mode if the maximum interval is
> > selected,
> It's not disable the pw20 state or altivec idle, just max-delay entry time.
No, the code checks for zero to set or clear the enabling bit (e.g.
PW20_WAIT).
> >but the documentation doesn't say that -- and the documentation
> > should be in the code (or other easily findable place), not just in the
> > commit message.
> >
> Also add a comment in the 85xx/common.c ?
Yes.
> > > +_GLOBAL(has_pw20_altivec_idle)
> > > + /* 0 false, 1 true */
> > > + li r3, 0
> > > +
> > > + /* PW20 & AltiVec idle feature only exists for E6500 */
> > > + mfspr r0, SPRN_PVR
> > > + rlwinm r4, r0, 16, 16, 31
> > > + lis r12, 0
> > > + ori r12, r12, PVR_VER_E6500@l
> > > + cmpw r4, r12
> > > + bne 2f
> > > + li r3, 1
> > > +2:
> > > + blr
> >
> > Why is this in asm? And shouldn't this go in the cputable somehow?
> >
> Not a special reason for this, just asm...
Asm shouldn't be used without a good reason.
-Scott
^ permalink raw reply
* RE: [PATCH v2] pstore: Adjust buffer size for compression for smaller registered buffers
From: Luck, Tony @ 2013-09-12 17:43 UTC (permalink / raw)
To: Aruna Balakrishnaiah, linuxppc-dev@ozlabs.org,
seiji.aguchi@hds.com, linux-kernel@vger.kernel.org,
keescook@chromium.org
Cc: jkenisto@linux.vnet.ibm.com, mahesh@linux.vnet.ibm.com,
ccross@android.com, cbouatmailru@gmail.com
In-Reply-To: <20130912064832.15340.52422.stgit@aruna-ThinkPad-T420>
KwlkZWZhdWx0Og0KKwkJY21wciA9IDYwOw0KKwkJYnJlYWs7DQorCX0NCiANCklzIHRoaXMgdGhl
IHJpZ2h0ICJkZWZhdWx0Ij8gIEl0IG1heSBiZSBhIGdvb2QgY2hvaWNlIGZvciBhIGJhY2tlbmQg
d2l0aCBhIHJlYWxseQ0KdGlueSBidWZmZXIgKDEgLi4uIDk5OSkuICBCdXQgbGVzcyBnb29kIGZv
ciBhICh0aGVvcmV0aWNhbCkgYmFja2VuZCB3aXRoIGEgbGFyZ2VyDQpidWZmZXIgKDEwMDAxIC4u
LiBpbmZpbml0eSBhbmQgYmV5b25kKS4gIFdoaWNoIGFyZSB5b3UgdHJ5aW5nIHRvIGNhdGNoIGhl
cmU/DQoNCi1Ub255DQoNCg==
^ permalink raw reply
* Re: [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes
From: Mark Rutland @ 2013-09-12 17:15 UTC (permalink / raw)
To: Hongbo Zhang
Cc: devicetree@vger.kernel.org, ian.campbell@citrix.com, Pawel Moll,
swarren@wwwdotorg.org, vinod.koul@intel.com,
linux-kernel@vger.kernel.org, rob.herring@calxeda.com,
djbw@fb.com, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <5225A57E.4030003@freescale.com>
On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote:
> On 09/02/2013 11:58 PM, Mark Rutland wrote:
> > Hi,
> >
> > On Fri, Aug 30, 2013 at 12:26:19PM +0100, hongbo.zhang@freescale.com wrote:
> >> From: Hongbo Zhang <hongbo.zhang@freescale.com>
> >>
> >> Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds
> >> the device tree nodes for them.
> >>
> >> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
> >> ---
> >> .../devicetree/bindings/powerpc/fsl/dma.txt | 67 ++++++++++++++++
> >> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 4 +-
> >> arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 82 ++++++++++++++++++++
> >> arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 82 ++++++++++++++++++++
> >> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 4 +-
> >> 5 files changed, 235 insertions(+), 4 deletions(-)
> >> create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
> >> create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi
> >>
> >> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
> >> index ddf17af..332ac77 100644
> >> --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
> >> +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
> >> @@ -126,6 +126,73 @@ Example:
> >> };
> >> };
> >>
> >> +** Freescale Elo3 DMA Controller
> >> + This is EloPlus controller with 8 channels, used in Freescale Txxx and Bxxx
> > I was under the impression EloPlus was the previous revision. Should
> > that say Elo3, or is Elo3 considered to be an EloPlus implementation?
> In this patch 1/3 I revise the doc to make it clear we have Elo and
> EloPlus, and I'm adding another new Elo3. Yes the only difference
> between Elo3 and EloPlus is channel numbers(8 channels vs 4 channels),
> so we can call "Elo3 is an 8-channel EloPlus"
Ok.
> >> + series chips, such as t1040, t4240, b4860.
> >> +
> >> +Required properties:
> >> +
> >> +- compatible : must include "fsl,elo3-dma"
> >> +- reg : <registers specifier for DMA general status reg>
> > The example has two reg entries. What both are should be specified. From
> > what you described last time, it sounds like each is a status register
> > for four channels.
> >
> > Presumably the first covers the channels at 0x0,0x80,0x100,0x180, and
> > the second covers the channels at 0x300,0x380,0x400,0x480? If the
> > registers have specific names in a datasheet, it would be worth
> > mentioning them.
> Yes, each is a status register for four channels, you got it -- this
> means my statement works.
> Is it necessary to specify all the register names?
> I can describe my two registers, but in other cases the reg entryies can
> cover tens even hundreds of registers, just a summary is OK I think.
I think there should at least be a description of which channels each
reg entry corresponds to. I see this hasn't been done so far for the
older Elo DMAs, but they only had 4 channels max, and one status reg.
> > If the specification of the DMA controller allows for more channels, it
> > may be worth describing that case now.
> This DMA controller doesn't allows for more channels. (Even if it does,
> it should be another new controller)
Ok.
> >> +- ranges : describes the mapping between the address space of the
> >> + DMA channels and the address space of the DMA controller
> > This looks odd as a required property, and I'm slightly confused. Is
> > this used to map the reg values of the DMA channels, or is it used when
> > mapping the DMA address space (for which dma-ranges exists in ePAPR and
> > other bindings).
> It is used to map the reg values of DMA channels.
Ok, I guess that makes sense.
> >> +
> >> +- DMA channel nodes:
> >> + - compatible : must include "fsl,eloplus-dma-channel"
> >> + - reg : <registers specifier for channel>
> > What does this represent? What are valid values?
> >
> > In the example below it looks like these are offsets of control
> > registers within the dma controller.
> Yes, they are offsets of control registers within dma controller, but
> the contents in these registers are for dma channels.
> Physically we have dma controller registers and dma channel registers,
> they are in one continuous physical address space, we divide all these
> registers into two controller/channel parts, according to contents in
> these registers, common status registers for all channels are called dma
> controller registers, otherwise channel specific registers are called
> dma channel registers.
I see, so this reg represents a channels channel specific registers
(which are distinct from the shared status registers). I was confused
initially as to what address space they were in, but that makes sense
with your description of ranges above.
> > If the reg property may have any value, how do they get mapped to bits
> > in the status register(s)?
> In fact, each channel has its own status register(and also other
> registers), the dma controller status register is just aggregation of
> all channel status register. (that seems duplicated somehow, maybe this
> is due to hardware compatibility with legacy one, and the device tree
> just describes the physical hardware without lie)
My question here was stupid, thanks for the explanation :)
> > May some channels be unusable for some reason, or will all eight
> > channels be wired on any given Elo3 DMA?
> Sorry, not get your point clearly, maybe you are clear now because of my
> previous explanations.
I assume that on any El03 DMA, there won't be a case where you can't
describe the channel at 0x80, for instance. It will always be present
(but it might not be wired up to anything any therefore be useful)?
This was related to my concerns about the status register description --
if the channels at 0x0,0x80,0x100,0x180 weren't wired, what would get
described in the dt? I guess that would never actually happen because
all 8 channels must always be present in the Elo3 IP block.
Thanks,
Mark.
^ permalink raw reply
* Re: [PATCH] powerpc/p1010rdb:remove interrupts of ethernet-phy in device tree
From: Kumar Gala @ 2013-09-12 16:41 UTC (permalink / raw)
To: Liu Shengzhou-B36685; +Cc: Zhao Qiang-B45475, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <3F453DDFF675A64A89321A1F35281021ABA9F8@039-SN1MPN1-004.039d.mgd.msft.net>
On Sep 12, 2013, at 1:54 AM, Liu Shengzhou-B36685 wrote:
>=20
>=20
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>> Sent: Wednesday, September 11, 2013 11:13 PM
>> To: Zhao Qiang-B45475
>> Cc: linuxppc-dev@lists.ozlabs.org; Liu Shengzhou-B36685
>> Subject: Re: [PATCH] powerpc/p1010rdb:remove interrupts of =
ethernet-phy in
>> device tree
>>=20
>>=20
>> On Sep 10, 2013, at 10:49 PM, Zhao Qiang wrote:
>>=20
>>> Since P1010RDB-PA and P1010RDB-PB boards use different external PHY
>>> interrupt signals.
>>> And actually the PHY interrupt is not used effectively with
>>> corresponding interrupt handler.
>>> So we can remove the interrupts node without side-effect to comply
>>> with both P1010RDB-PA and P1010RDB-PB.
>>>=20
>>> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
>>> Signed-off-by: Zhao Qiang <B45475@freescale.com>
>>> ---
>>> arch/powerpc/boot/dts/p1010rdb.dtsi | 3 ---
>>> 1 file changed, 3 deletions(-)
>>>=20
>>=20
>> NAK. The device tree should represent the HW not what drivers decide =
to do with
>> it.
>>=20
>> If different board revs have different interrupt signals than create =
dts's to
>> handle the 2 board revs.
>>=20
>> - k
>>=20
> You mean we need to create p1010rdb-pa.dtsi and p1010rdb-pb.dtsi =
replacing current p1010rdb.dtsi just because of the unused phy =
interrupt?
> and phy interrupt is not present in those dts of P3/P4/P5 platforms.
> Actually currently many hardware are not present in dts, such as a lot =
of i2c devices, temperature monitor, etc.
>=20
> -Shengzhou
>=20
I'm saying of the board revs are different w/regards to how the PHY =
interrupt is wired, than create two .dts one for each of the board revs.
If the p3/p4/p5 platforms are missing the phy interrupt in the .dts than =
its an error.
Other devices like i2c, temp mon, etc should be added. There is a =
difference between something not existing because people haven't gotten =
around to it / there isn't a binding vs a using the lack of information =
as a configuration mechanism.
- k
^ permalink raw reply
* RE: [PATCH v2] pstore: Adjust buffer size for compression for smaller registered buffers
From: Seiji Aguchi @ 2013-09-12 16:22 UTC (permalink / raw)
To: Aruna Balakrishnaiah, linuxppc-dev@ozlabs.org,
tony.luck@intel.com, linux-kernel@vger.kernel.org,
keescook@chromium.org
Cc: jkenisto@linux.vnet.ibm.com, mahesh@linux.vnet.ibm.com,
ccross@android.com, cbouatmailru@gmail.com
In-Reply-To: <20130912064832.15340.52422.stgit@aruna-ThinkPad-T420>
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VkVMKSwNCg0K
^ permalink raw reply
* Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree nodes
From: Scott Wood @ 2013-09-12 14:44 UTC (permalink / raw)
To: Tang Yuantian-B29983
Cc: Wood Scott-B07421, Li Yang-Leo-R58472,
linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org
In-Reply-To: <D07C73A334FF604B95B3CBD2A545D07B150748AA@039-SN2MPN1-013.039d.mgd.msft.net>
On Wed, 2013-09-11 at 20:31 -0500, Tang Yuantian-B29983 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: 2013=E5=B9=B49=E6=9C=8812=E6=97=A5 =E6=98=9F=E6=9C=9F=E5=9B=9B =
9:10
> > To: Tang Yuantian-B29983
> > Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> > devicetree@vger.kernel.org; Li Yang-Leo-R58472
> > Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree
> > nodes
> >=20
> > This description of "reg" is overly specific (assumes how the parent
> > node's ranges are set up), incomplete (there's a size as well as the
> > offset), and does not apply to the clockgen node itself (you probably
> > shouldn't lump them together like this).
> >=20
> Do you mean I should explain the REG of clockgen and its child node res=
pectively?
>=20
> > > +- clocks : shall be the input parent clock phandle for the clock.
> >=20
> > Not required on the clockgen node
> >=20
> Required by child node of clockgen.
My point is that you're lumping several different types of nodes
together with one binding, when some parts of the binding are not
applicable to the clockgen node.
-Scott
^ permalink raw reply
* Re: [PATCH 0/2] powerpc: allow kvm to use kerel debug framework
From: Alexander Graf @ 2013-09-12 14:29 UTC (permalink / raw)
To: Michael Neuling
Cc: linux-kernel, Bharat Bhushan, Bharat Bhushan, scottwood,
linuxppc-dev
In-Reply-To: <21895.1373441122@ale.ozlabs.ibm.com>
On 10.07.2013, at 02:25, Michael Neuling wrote:
> Alexander Graf <agraf@suse.de> wrote:
>=20
>>=20
>> On 09.07.2013, at 06:24, Michael Neuling wrote:
>>=20
>>> Alexander Graf <agraf@suse.de> wrote:
>>>=20
>>>>=20
>>>> On 04.07.2013, at 08:15, Bharat Bhushan wrote:
>>>>=20
>>>>> From: Bharat Bhushan <bharat.bhushan@freescale.com>
>>>>>=20
>>>>> This patchset moves the debug registers in a structure, which =
allows
>>>>> kvm to use same structure for debug emulation.
>>>>>=20
>>>>> Note: Earilier a patchset =
"https://lists.ozlabs.org/pipermail/linuxppc-dev/2013-June/108132.html"
>>>>> was sent which is a bunch of six patches. That patchset is divided =
into two parts:
>>>>> 1) powerpc specific changes (These 2 patches are actually have =
those changes)
>>>>> 2) KVM specific changes (will send separate patch on agraf =
repository)
>>>>=20
>>>> Mikey, if you like those could you please apply the into a topic
>>>> branch and get that one merged with Ben? I'd also pull it into my =
tree
>>>> then.
>>>=20
>>> benh would pull these directly. =20
>>>=20
>>> I'll have a chat with him to see if he wants my ACK before he does =
that.
>>=20
>> I have a bunch of patches that I need to apply on top, so I need a =
topic branch.
>=20
> I've acked the PPC specific bits of the v6 version of these patches.
>=20
> benh said he'll open a topic branch for you sometime next week and =
he'll
> stick them in there. =20
Did anything happen here?
Alex
^ permalink raw reply
* Re: [RFC PATCH v2 15/25] smp, ppc: kill SMP single function call interrupt
From: Jiang Liu @ 2013-09-12 14:04 UTC (permalink / raw)
To: Srivatsa S. Bhat
Cc: linux-arch, Deepthi Dharwar, Paul E. McKenney, Jiri Kosina,
Peter Zijlstra, linuxppc-dev, Wang YanQing, Steven Rostedt,
linux-kernel, Paul Mackerras, Preeti U Murthy, Andrew Morton,
Shaohua Li, Ingo Molnar, Jiang Liu
In-Reply-To: <5230CC84.1010503@linux.vnet.ibm.com>
On 09/12/2013 04:03 AM, Srivatsa S. Bhat wrote:
> On 09/11/2013 09:37 PM, Jiang Liu wrote:
>> From: Jiang Liu <jiang.liu@huawei.com>
>>
>> Commit 9a46ad6d6df3b54 "smp: make smp_call_function_many() use logic
>> similar to smp_call_function_single()" has unified the way to handle
>> single and multiple cross-CPU function calls. Now only one interrupt
>> is needed for architecture specific code to support generic SMP function
>> call interfaces, so kill the redundant single function call interrupt.
>>
>> Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
>> Cc: Jiang Liu <liuj97@gmail.com>
>> ---
>
> It turns out that freeing up the IPI slot in powerpc is very useful, since
> we actually wanted a slot for some other use-case (and there are only 4 slots
> available on powerpc).
>
> Here are the patches which achieve that:
> http://marc.info/?l=linuxppc-embedded&m=137886807502898&w=2
> http://marc.info/?l=linuxppc-embedded&m=137886811502909&w=2
Hi Srivatsa,
That's great and I will drop this patch from my series.
Could you please to kill call_function_single_action() instead of
call_function_action()? Please refer to
http://lkml.org/lkml/2013/9/11/579
Regards!
Gerry
>
> So, can you kindly consider dropping the powerpc patch from your series,
> if that is OK with you? Thanks!
>
> BTW, after doing the powerpc cleanup, even I had thought about killing one
> of the smp-function variants in various architectures, but never got around
> to do it. But now that you have posted the series which does that, I'll try
> to review them.
>
> Thank you!
>
> Regards,
> Srivatsa S. Bhat
>
>> arch/powerpc/include/asm/smp.h | 3 +--
>> arch/powerpc/kernel/smp.c | 12 +-----------
>> 2 files changed, 2 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
>> index 48cfc85..53faa03 100644
>> --- a/arch/powerpc/include/asm/smp.h
>> +++ b/arch/powerpc/include/asm/smp.h
>> @@ -119,8 +119,7 @@ extern int cpu_to_core_id(int cpu);
>> * in /proc/interrupts will be wrong!!! --Troy */
>> #define PPC_MSG_CALL_FUNCTION 0
>> #define PPC_MSG_RESCHEDULE 1
>> -#define PPC_MSG_CALL_FUNC_SINGLE 2
>> -#define PPC_MSG_DEBUGGER_BREAK 3
>> +#define PPC_MSG_DEBUGGER_BREAK 2
>>
>> /* for irq controllers that have dedicated ipis per message (4) */
>> extern int smp_request_message_ipi(int virq, int message);
>> diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
>> index 38b0ba6..0c53b10 100644
>> --- a/arch/powerpc/kernel/smp.c
>> +++ b/arch/powerpc/kernel/smp.c
>> @@ -123,12 +123,6 @@ static irqreturn_t reschedule_action(int irq, void *data)
>> return IRQ_HANDLED;
>> }
>>
>> -static irqreturn_t call_function_single_action(int irq, void *data)
>> -{
>> - generic_smp_call_function_single_interrupt();
>> - return IRQ_HANDLED;
>> -}
>> -
>> static irqreturn_t debug_ipi_action(int irq, void *data)
>> {
>> if (crash_ipi_function_ptr) {
>> @@ -146,14 +140,12 @@ static irqreturn_t debug_ipi_action(int irq, void *data)
>> static irq_handler_t smp_ipi_action[] = {
>> [PPC_MSG_CALL_FUNCTION] = call_function_action,
>> [PPC_MSG_RESCHEDULE] = reschedule_action,
>> - [PPC_MSG_CALL_FUNC_SINGLE] = call_function_single_action,
>> [PPC_MSG_DEBUGGER_BREAK] = debug_ipi_action,
>> };
>>
>> const char *smp_ipi_name[] = {
>> [PPC_MSG_CALL_FUNCTION] = "ipi call function",
>> [PPC_MSG_RESCHEDULE] = "ipi reschedule",
>> - [PPC_MSG_CALL_FUNC_SINGLE] = "ipi call function single",
>> [PPC_MSG_DEBUGGER_BREAK] = "ipi debugger",
>> };
>>
>> @@ -225,8 +217,6 @@ irqreturn_t smp_ipi_demux(void)
>> generic_smp_call_function_interrupt();
>> if (all & (1 << (24 - 8 * PPC_MSG_RESCHEDULE)))
>> scheduler_ipi();
>> - if (all & (1 << (24 - 8 * PPC_MSG_CALL_FUNC_SINGLE)))
>> - generic_smp_call_function_single_interrupt();
>> if (all & (1 << (24 - 8 * PPC_MSG_DEBUGGER_BREAK)))
>> debug_ipi_action(0, NULL);
>> #else
>> @@ -257,7 +247,7 @@ EXPORT_SYMBOL_GPL(smp_send_reschedule);
>>
>> void arch_send_call_function_single_ipi(int cpu)
>> {
>> - do_message_pass(cpu, PPC_MSG_CALL_FUNC_SINGLE);
>> + do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
>> }
>>
>> void arch_send_call_function_ipi_mask(const struct cpumask *mask)
>>
>
^ permalink raw reply
* [PATCH] pci: fix interrupt-map for bridges
From: Alexey Kardashevskiy @ 2013-09-12 12:25 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Alexey Kardashevskiy, Nikunj A Dadhania
The previous scheme always put 0 as a parent slot#. However it is
not always the case and QEMU's PCI bridge does not support putting
device at slot#0 as it claims SHPC support for hotplug.
This modifies the interrups map to let the linux guest resolve XICS
global interrupt number correctly.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
This is the example of working system:
[root@erif_root pci@1]# lspci
0001:00:01.0 PCI bridge: Red Hat, Inc. Device 0001
0001:01:02.0 PCI bridge: Red Hat, Inc. Device 0001
0001:01:03.0 PCI bridge: Red Hat, Inc. Device 0001
0001:02:01.0 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06)
0001:02:02.0 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06)
0001:03:01.0 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06)
0001:03:02.0 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06)
[root@erif_root pci@1]# pwd
/proc/device-tree/pci@80000002000000f/pci@1
[root@erif_root pci@1]# hexdump -e '9/4 "%08x "' -e '"\n"' i*map
00001000 00000000 00000000 00000001 3e57f7e0 00000800 00000000 00000000 00000003
00001000 00000000 00000000 00000002 3e57f7e0 00000800 00000000 00000000 00000000
00001000 00000000 00000000 00000003 3e57f7e0 00000800 00000000 00000000 00000001
00001000 00000000 00000000 00000004 3e57f7e0 00000800 00000000 00000000 00000002
00001800 00000000 00000000 00000001 3e57f7e0 00000800 00000000 00000000 00000000
00001800 00000000 00000000 00000002 3e57f7e0 00000800 00000000 00000000 00000001
00001800 00000000 00000000 00000003 3e57f7e0 00000800 00000000 00000000 00000002
00001800 00000000 00000000 00000004 3e57f7e0 00000800 00000000 00000000 00000003
[root@erif_root pci@1]# cd pci@2/
[root@erif_root pci@2]# hexdump -e '9/4 "%08x "' -e '"\n"' i*map
00000800 00000000 00000000 00000001 3e5a86f0 00001000 00000000 00000000 00000002
00000800 00000000 00000000 00000002 3e5a86f0 00001000 00000000 00000000 00000003
00000800 00000000 00000000 00000003 3e5a86f0 00001000 00000000 00000000 00000000
00000800 00000000 00000000 00000004 3e5a86f0 00001000 00000000 00000000 00000001
00001000 00000000 00000000 00000001 3e5a86f0 00001000 00000000 00000000 00000003
00001000 00000000 00000000 00000002 3e5a86f0 00001000 00000000 00000000 00000000
00001000 00000000 00000000 00000003 3e5a86f0 00001000 00000000 00000000 00000001
00001000 00000000 00000000 00000004 3e5a86f0 00001000 00000000 00000000 00000002
[root@erif_root pci@2]# cd ethernet@
ethernet@1/ ethernet@2/
[root@erif_root pci@2]# cd ethernet@1/
[root@erif_root ethernet@1]# lsprop reg
reg 00020800 00000000 00000000 00000000 00000000
02020810 00000000 00000000 00000000 00020000
02020814 00000000 00000000 00000000 00020000
01020818 00000000 00000000 00000000 00000020
02020830 00000000 00000000 00000000 00020000
[root@erif_root ethernet@1]# lsprop interrupts
interrupts 00000002
---
board-qemu/slof/pci-interrupts.fs | 31 ++++++++++++++++++++-----------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/board-qemu/slof/pci-interrupts.fs b/board-qemu/slof/pci-interrupts.fs
index a12d7bb..62785a7 100644
--- a/board-qemu/slof/pci-interrupts.fs
+++ b/board-qemu/slof/pci-interrupts.fs
@@ -1,17 +1,26 @@
: pci-gen-irq-map-one ( prop-addr prop-len slot pin -- prop-addr prop-len )
- 2dup + 4 mod ( prop-addr prop-len slot pin parentpin )
+ 2dup + 4 mod ( prop-addr prop-len slot pin parentpin )
+ >r >r >r ( prop-addr prop-len R: swizzledpin pin slot )
+
+ \ Child slot#
+ r> B lshift encode-int+ ( prop-addr prop-len R: swizzledpin pin )
+ \ Child 64bit BAR (not really used)
+ 0 encode-64+
+ \ Chile pin#
+ r> encode-int+ ( prop-addr prop-len R: swizzledpin )
+
+ \ Parent phandle
+ get-parent encode-int+
+
+ \ Parent slot#
get-node >space
- pci-addr2dev + 1- 4 mod 1+ \ do swizzling ( prop-addr prop-len slot pin swizzledpin )
- >r >r >r ( prop-addr prop-len R: swizzledpin pin slot )
-
- r> B lshift encode-int+
- 0 encode-64+ \ device slot ( prop-addr prop-len R: swizzledpin pin )
- r> encode-int+ \ device pin ( prop-addr prop-len R: swizzledpin )
-
- get-parent encode-int+ \ parent phandle
- 0 encode-int+ 0 encode-64+ \ parent slot
- r> encode-int+ \ parent swizzled pin ( prop-addr prop-len R: )
+ pci-addr2dev B lshift ( prop-addr prop-len parent-slot R: swizzledpin )
+ encode-int+
+ \ Parent 64bit BAR (not really used)
+ 0 encode-64+
+ \ Parent pin
+ r> encode-int+ ( prop-addr prop-len R: )
;
: pci-gen-irq-entry ( prop-addr prop-len config-addr -- prop-addr prop-len )
--
1.8.4.rc4
^ permalink raw reply related
* [PATCH 2/2][RFC][v3] pci: fsl: rework PCI driver compatible with Layerscape
From: Minghuan Lian @ 2013-09-12 10:07 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Minghuan Lian, Zang Roy-R61911
In-Reply-To: <1378980438-29888-1-git-send-email-Minghuan.Lian@freescale.com>
The Freescale's Layerscape series processors will use the same PCI
controller but change cores from PowerPC to ARM. This patch is to
rework FSL PCI driver to support PowerPC and ARM simultaneously.
PowerPC uses structure pci_controller to describe PCI controller,
but arm uses structure hw_pci and pci_sys_data. They also have
different architecture implementation and initialization flow.
The architecture-dependent driver will bridge the gap, get the
settings from the common driver and initialize the corresponding
structure and call the related interface to register PCI controller.
The common driver pci-fsl.c removes all the architecture-specific
code and provides structure fsl_pci to store all the controller
settings and the common functionalities that include reading/writing
PCI configuration space, parsing dts node and getting the MEM/IO and
bus number ranges, setting ATMU and check link status.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
Based on upstream master
The function has been tested on MPC8315ERDB MPC8572DS P5020DS P3041DS
and T4240QDS boards
Change log:
v3:
1. use 'fsl_arch' as function name prefix of all the
architecture-specific hooks.
2. Move PCI compatible definitions from arch/powerpc/sysdev/fsl_pci.c
to driver/pci/host/pci-fsl.c
v2:
1. Use 'pci' instead of 'pcie' in new file name and file contents.
2. Use iowrite32be()/iowrite32() instead of out_be32/le32()
3. Fix ppc_md.dma_set_mask setting
4. Synchronizes host->first_busno and pci->first_busno.
5. Fix PCI IO space settings
6. Some small changes according to Scott's comments.
arch/powerpc/Kconfig | 1 +
arch/powerpc/sysdev/fsl_pci.c | 150 +++++++++-
drivers/edac/mpc85xx_edac.c | 9 -
drivers/pci/host/Kconfig | 4 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pci-fsl.c | 656 +++++++++++++++++++++++++++---------------
include/linux/fsl/pci.h | 69 +++++
7 files changed, 648 insertions(+), 242 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 6b7530f..657d90f 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -691,6 +691,7 @@ config FSL_SOC
config FSL_PCI
bool
+ select PCI_FSL if FSL_SOC_BOOKE || PPC_86xx
select PPC_INDIRECT_PCI
select PCI_QUIRKS
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index a189ff0..4cb12e8 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -62,7 +62,11 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
#define MAX_PHYS_ADDR_BITS 40
-static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
+
+u64 fsl_arch_pci64_dma_offset(void)
+{
+ return 1ull << MAX_PHYS_ADDR_BITS;
+}
static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
{
@@ -77,17 +81,43 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
if ((dev->bus == &pci_bus_type) &&
dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
set_dma_ops(dev, &dma_direct_ops);
- set_dma_offset(dev, pci64_dma_offset);
+ set_dma_offset(dev, fsl_arch_pci64_dma_offset());
}
*dev->dma_mask = dma_mask;
return 0;
}
+struct fsl_pci *fsl_arch_sys_to_pci(void *sys)
+{
+ struct pci_controller *hose = sys;
+ struct fsl_pci *pci = hose->private_data;
+
+ /* Update the first bus number */
+ if (pci->first_busno != hose->first_busno)
+ pci->first_busno = hose->first_busno;
+
+ return pci;
+}
+
+struct pci_bus *fsl_arch_fake_pci_bus(struct fsl_pci *pci, int busnr)
+{
+ static struct pci_bus bus;
+ static struct pci_controller hose;
+
+ bus.number = busnr;
+ bus.sysdata = &hose;
+ hose.private_data = pci;
+ bus.ops = pci->ops;
+
+ return &bus;
+}
+
void fsl_pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_controller *hose = pci_bus_to_host(bus);
- int i, is_pcie = 0, no_link;
+ int i, is_pcie, no_link;
+ struct fsl_pci *pci = fsl_arch_sys_to_pci(hose);
/* The root complex bridge comes up with bogus resources,
* we copy the PHB ones in.
@@ -97,9 +127,8 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
* tricky.
*/
- if (fsl_pcie_bus_fixup)
- is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
- no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
+ is_pcie = pci->is_pcie;
+ no_link = fsl_pci_check_link(pci);
if (bus->parent == hose->bus && (is_pcie || no_link)) {
for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
@@ -121,6 +150,94 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
}
}
+int fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn)
+{
+ struct pci_controller *hose = pci->sys;
+
+ if (!hose)
+ return PCIBIOS_SUCCESSFUL;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(hose, bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int fsl_arch_pci_sys_register(struct fsl_pci *pci)
+{
+ struct pci_controller *hose;
+
+ pci_add_flags(PCI_REASSIGN_ALL_BUS);
+ hose = pcibios_alloc_controller(pci->dn);
+ if (!hose)
+ return -ENOMEM;
+
+ /* set platform device as the parent */
+ hose->private_data = pci;
+ hose->parent = pci->dev;
+ hose->first_busno = pci->first_busno;
+ hose->last_busno = pci->last_busno;
+ hose->ops = pci->ops;
+
+#ifdef CONFIG_PPC32
+ /* On 32 bits, limit I/O space to 16MB */
+ if (pci->pci_io_size > 0x01000000)
+ pci->pci_io_size = 0x01000000;
+
+ /* 32 bits needs to map IOs here */
+ hose->io_base_virt = ioremap(pci->io_base_phys + pci->io_resource.start,
+ pci->pci_io_size);
+
+ /* Expect trouble if pci_addr is not 0 */
+ if (fsl_pci_primary == pci->dn)
+ isa_io_base = (unsigned long)hose->io_base_virt;
+#endif /* CONFIG_PPC32 */
+
+ hose->pci_io_size = pci->io_resource.start + pci->pci_io_size;
+ hose->io_base_phys = pci->io_base_phys;
+ hose->io_resource = pci->io_resource;
+
+ memcpy(hose->mem_offset, pci->mem_offset, sizeof(hose->mem_offset));
+ memcpy(hose->mem_resources, pci->mem_resources,
+ sizeof(hose->mem_resources));
+ hose->dma_window_base_cur = pci->dma_window_base_cur;
+ hose->dma_window_size = pci->dma_window_size;
+
+ pci->sys = hose;
+
+ /*
+ * Install our own dma_set_mask handler to fixup dma_ops
+ * and dma_offset when memory is more than dma window size
+ */
+ if (pci->is_pcie && memblock_end_of_DRAM() > hose->dma_window_size)
+ ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
+
+#ifdef CONFIG_SWIOTLB
+ /*
+ * if we couldn't map all of DRAM via the dma windows
+ * we need SWIOTLB to handle buffers located outside of
+ * dma capable memory region
+ */
+ if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur +
+ hose->dma_window_size)
+ ppc_swiotlb_enable = 1;
+#endif
+
+ mpc85xx_pci_err_probe(to_platform_device(pci->dev));
+ return 0;
+}
+
+void fsl_arch_pci_sys_remove(struct fsl_pci *pci)
+{
+ struct pci_controller *hose = pci->sys;
+
+ if (!hose)
+ return;
+
+ pcibios_free_controller(hose);
+}
+
#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
@@ -260,6 +377,19 @@ static struct pci_ops mpc83xx_pcie_ops = {
.write = mpc83xx_pcie_write_config,
};
+static int mpc83xx_pcie_check_link(struct pci_controller *hose)
+{
+ u32 val = 0;
+
+#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
+#define PCIE_LTSSM_L0 0x16 /* L0 state */
+
+ early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
+ if (val < PCIE_LTSSM_L0)
+ return 1;
+ return 0;
+}
+
static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
struct resource *reg)
{
@@ -294,7 +424,7 @@ static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
- if (fsl_pcie_check_link(hose))
+ if (mpc83xx_pcie_check_link(hose))
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
return 0;
@@ -592,6 +722,7 @@ int fsl_pci_mcheck_exception(struct pt_regs *regs)
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
struct device_node *fsl_pci_primary;
+extern const struct of_device_id fsl_pci_ids[];
void fsl_pci_assign_primary(void)
{
@@ -607,7 +738,8 @@ void fsl_pci_assign_primary(void)
of_node_put(np);
np = fsl_pci_primary;
- if (of_match_node(pci_ids, np) && of_device_is_available(np))
+ if (of_match_node(fsl_pci_ids, np) &&
+ of_device_is_available(np))
return;
}
@@ -616,7 +748,7 @@ void fsl_pci_assign_primary(void)
* designate one as primary. This can go away once
* various bugs with primary-less systems are fixed.
*/
- for_each_matching_node(np, pci_ids) {
+ for_each_matching_node(np, fsl_pci_ids) {
if (of_device_is_available(np)) {
fsl_pci_primary = np;
of_node_put(np);
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index 3eb32f6..93203e3 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -239,7 +239,6 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
pdata = pci->pvt_info;
pdata->name = "mpc85xx_pci_err";
pdata->irq = NO_IRQ;
- dev_set_drvdata(&op->dev, pci);
pci->dev = &op->dev;
pci->mod_name = EDAC_MOD_STR;
pci->ctl_name = pdata->name;
@@ -260,14 +259,6 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
/* we only need the error registers */
r.start += 0xe00;
- if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
- pdata->name)) {
- printk(KERN_ERR "%s: Error while requesting mem region\n",
- __func__);
- res = -EBUSY;
- goto err;
- }
-
pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
if (!pdata->pci_vbase) {
printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 3d95048..37d25ae 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -19,4 +19,8 @@ config PCI_TEGRA
bool "NVIDIA Tegra PCIe controller"
depends on ARCH_TEGRA
+config PCI_FSL
+ bool "Freescale PCI/PCIe controller"
+ depends on FSL_SOC_BOOKE || PPC_86xx
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index c9a997b..3447a27 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
+obj-$(CONFIG_PCI_FSL) += pci-fsl.o
diff --git a/drivers/pci/host/pci-fsl.c b/drivers/pci/host/pci-fsl.c
index 69d338b..07d553a 100644
--- a/drivers/pci/host/pci-fsl.c
+++ b/drivers/pci/host/pci-fsl.c
@@ -22,38 +22,159 @@
#include <linux/bootmem.h>
#include <linux/memblock.h>
#include <linux/log2.h>
-#include <linux/slab.h>
-#include <linux/uaccess.h>
-
-#include <asm/io.h>
-#include <asm/prom.h>
-#include <asm/pci-bridge.h>
-#include <asm/ppc-pci.h>
-#include <asm/machdep.h>
-#include <asm/disassemble.h>
-#include <asm/ppc-opcode.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pci.h>
-
-static int fsl_pcie_check_link(struct pci_controller *hose)
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/pci_regs.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/types.h>
+#include <linux/memblock.h>
+#include <linux/fsl/pci.h>
+
+/* Indirect type */
+#define INDIRECT_TYPE_EXT_REG 0x00000002
+#define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
+#define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
+#define INDIRECT_TYPE_BIG_ENDIAN 0x00000010
+#define INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
+
+u64 __weak fsl_arch_pci64_dma_offset(void)
+{
+ return 0;
+}
+
+struct fsl_pci * __weak fsl_arch_sys_to_pci(void *sys)
+{
+ return NULL;
+}
+
+struct pci_bus * __weak fsl_arch_fake_pci_bus(struct fsl_pci *pci, int busnr)
+{
+ return NULL;
+}
+
+int __weak fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int fsl_pci_read_config(struct fsl_pci *pci, int bus, int devfn,
+ int offset, int len, u32 *val)
+{
+ u32 bus_no, reg, data;
+
+ if (pci->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
+ if (bus != pci->first_busno)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (devfn != 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ if (fsl_arch_pci_exclude_device(pci, bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ bus_no = (bus == pci->first_busno) ? pci->self_busno : bus;
+
+ if (pci->indirect_type & INDIRECT_TYPE_EXT_REG)
+ reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
+ else
+ reg = offset & 0xfc;
+
+ if (pci->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
+ iowrite32be(0x80000000 | (bus_no << 16) | (devfn << 8) | reg,
+ &pci->regs->config_addr);
+ else
+ iowrite32(0x80000000 | (bus_no << 16) | (devfn << 8) | reg,
+ &pci->regs->config_addr);
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ data = ioread32(&pci->regs->config_data);
+ switch (len) {
+ case 1:
+ *val = (data >> (8 * (offset & 3))) & 0xff;
+ break;
+ case 2:
+ *val = (data >> (8 * (offset & 3))) & 0xffff;
+ break;
+ default:
+ *val = data;
+ break;
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int fsl_pci_write_config(struct fsl_pci *pci, int bus, int devfn,
+ int offset, int len, u32 val)
+{
+ void __iomem *cfg_data;
+ u32 bus_no, reg;
+
+ if (pci->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
+ if (bus != pci->first_busno)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (devfn != 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ if (fsl_arch_pci_exclude_device(pci, bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ bus_no = (bus == pci->first_busno) ?
+ pci->self_busno : bus;
+
+ if (pci->indirect_type & INDIRECT_TYPE_EXT_REG)
+ reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
+ else
+ reg = offset & 0xfc;
+
+ if (pci->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
+ iowrite32be(0x80000000 | (bus_no << 16) | (devfn << 8) | reg,
+ &pci->regs->config_addr);
+ else
+ iowrite32(0x80000000 | (bus_no << 16) | (devfn << 8) | reg,
+ &pci->regs->config_addr);
+
+ /* suppress setting of PCI_PRIMARY_BUS */
+ if (pci->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
+ if ((offset == PCI_PRIMARY_BUS) &&
+ (bus == pci->first_busno))
+ val &= 0xffffff00;
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ cfg_data = ((void *) &(pci->regs->config_data)) + (offset & 3);
+ switch (len) {
+ case 1:
+ iowrite8(val, cfg_data);
+ break;
+ case 2:
+ iowrite16(val, cfg_data);
+ break;
+ default:
+ iowrite32(val, cfg_data);
+ break;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int fsl_pci_check_link(struct fsl_pci *pci)
{
u32 val = 0;
- if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
- if (hose->ops->read == fsl_indirect_read_config) {
- struct pci_bus bus;
- bus.number = hose->first_busno;
- bus.sysdata = hose;
- bus.ops = hose->ops;
- indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
- } else
- early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
+ if (pci->indirect_type & INDIRECT_TYPE_FSL_CFG_REG_LINK) {
+ fsl_pci_read_config(pci, 0, 0, PCIE_LTSSM, 4, &val);
if (val < PCIE_LTSSM_L0)
return 1;
} else {
- struct ccsr_pci __iomem *pci = hose->private_data;
/* for PCIe IP rev 3.0 or greater use CSR0 for link state */
- val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
+ val = (in_be32(&pci->regs->pex_csr0) & PEX_CSR0_LTSSM_MASK)
>> PEX_CSR0_LTSSM_SHIFT;
if (val != PEX_CSR0_LTSSM_L0)
return 1;
@@ -65,27 +186,65 @@ static int fsl_pcie_check_link(struct pci_controller *hose)
static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
int offset, int len, u32 *val)
{
- struct pci_controller *hose = pci_bus_to_host(bus);
+ struct fsl_pci *pci = fsl_arch_sys_to_pci(bus->sysdata);
+
+ if (!pci)
+ return PCIBIOS_DEVICE_NOT_FOUND;
- if (fsl_pcie_check_link(hose))
- hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+ if (fsl_pci_check_link(pci))
+ pci->indirect_type |= INDIRECT_TYPE_NO_PCIE_LINK;
else
- hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+ pci->indirect_type &= ~INDIRECT_TYPE_NO_PCIE_LINK;
- return indirect_read_config(bus, devfn, offset, len, val);
+ return fsl_pci_read_config(pci, bus->number, devfn, offset, len, val);
}
-#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
-
-static struct pci_ops fsl_indirect_pcie_ops =
+static int fsl_indirect_write_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 val)
{
+ struct fsl_pci *pci = fsl_arch_sys_to_pci(bus->sysdata);
+
+ if (!pci)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return fsl_pci_write_config(pci, bus->number, devfn,
+ offset, len, val);
+}
+
+static struct pci_ops fsl_indirect_pci_ops = {
.read = fsl_indirect_read_config,
- .write = indirect_write_config,
+ .write = fsl_indirect_write_config,
};
+#define EARLY_FSL_PCI_OP(rw, size, type) \
+int early_fsl_##rw##_config_##size(struct fsl_pci *pci, int bus, \
+ int devfn, int offset, type value) \
+{ \
+ return pci_bus_##rw##_config_##size(fsl_arch_fake_pci_bus(pci, bus),\
+ devfn, offset, value); \
+}
+
+EARLY_FSL_PCI_OP(read, byte, u8 *)
+EARLY_FSL_PCI_OP(read, word, u16 *)
+EARLY_FSL_PCI_OP(read, dword, u32 *)
+EARLY_FSL_PCI_OP(write, byte, u8)
+EARLY_FSL_PCI_OP(write, word, u16)
+EARLY_FSL_PCI_OP(write, dword, u32)
+
+static int early_fsl_find_capability(struct fsl_pci *pci,
+ int busnr, int devfn, int cap)
+{
+ struct pci_bus *bus = fsl_arch_fake_pci_bus(pci, busnr);
+
+ if (!bus)
+ return 0;
+
+ return pci_bus_find_capability(bus, devfn, cap);
+}
+
static int setup_one_atmu(struct ccsr_pci __iomem *pci,
- unsigned int index, const struct resource *res,
- resource_size_t offset)
+ unsigned int index, const struct resource *res,
+ resource_size_t offset)
{
resource_size_t pci_addr = res->start - offset;
resource_size_t phys_addr = res->start;
@@ -106,10 +265,10 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
if (index + i >= 5)
return -1;
- out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
- out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
- out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
- out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
+ iowrite32be(pci_addr >> 12, &pci->pow[index + i].potar);
+ iowrite32be((u64)pci_addr >> 44, &pci->pow[index + i].potear);
+ iowrite32be(phys_addr >> 12, &pci->pow[index + i].powbar);
+ iowrite32be(flags | (bits - 1), &pci->pow[index + i].powar);
pci_addr += (resource_size_t)1U << bits;
phys_addr += (resource_size_t)1U << bits;
@@ -120,21 +279,19 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
}
/* atmu setup for fsl pci/pcie controller */
-static void setup_pci_atmu(struct pci_controller *hose)
+static void setup_pci_atmu(struct fsl_pci *pci)
{
- struct ccsr_pci __iomem *pci = hose->private_data;
int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
u64 mem, sz, paddr_hi = 0;
u64 offset = 0, paddr_lo = ULLONG_MAX;
u32 pcicsrbar = 0, pcicsrbar_sz;
u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
- const char *name = hose->dn->full_name;
const u64 *reg;
int len;
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
+ if (pci->is_pcie) {
+ if (in_be32(&pci->regs->block_rev1) >= PCIE_IP_REV_2_2) {
win_idx = 2;
start_idx = 0;
end_idx = 3;
@@ -142,47 +299,54 @@ static void setup_pci_atmu(struct pci_controller *hose)
}
/* Disable all windows (except powar0 since it's ignored) */
- for(i = 1; i < 5; i++)
- out_be32(&pci->pow[i].powar, 0);
+ for (i = 1; i < 5; i++)
+ iowrite32be(0, &pci->regs->pow[i].powar);
for (i = start_idx; i < end_idx; i++)
- out_be32(&pci->piw[i].piwar, 0);
+ iowrite32be(0, &pci->regs->piw[i].piwar);
/* Setup outbound MEM window */
- for(i = 0, j = 1; i < 3; i++) {
- if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
+ for (i = 0, j = 1; i < 3; i++) {
+ if (!(pci->mem_resources[i].flags & IORESOURCE_MEM))
continue;
- paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
- paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
+ paddr_lo = min_t(u64, paddr_lo, pci->mem_resources[i].start);
+ paddr_hi = max_t(u64, paddr_hi, pci->mem_resources[i].end);
/* We assume all memory resources have the same offset */
- offset = hose->mem_offset[i];
- n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
+ offset = pci->mem_offset[i];
+ n = setup_one_atmu(pci->regs, j, &pci->mem_resources[i],
+ offset);
if (n < 0 || j >= 5) {
- pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
- hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
+ dev_err(pci->dev,
+ "Ran out of outbound PCI ATMUs for resource %d!\n",
+ i);
+ pci->mem_resources[i].flags |= IORESOURCE_DISABLED;
} else
j += n;
}
/* Setup outbound IO window */
- if (hose->io_resource.flags & IORESOURCE_IO) {
- if (j >= 5) {
- pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
- } else {
- pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
- "phy base 0x%016llx.\n",
- (u64)hose->io_resource.start,
- (u64)resource_size(&hose->io_resource),
- (u64)hose->io_base_phys);
- out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
- out_be32(&pci->pow[j].potear, 0);
- out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
+ if (pci->io_resource.flags & IORESOURCE_IO) {
+ if (j >= 5)
+ dev_err(pci->dev,
+ "Ran out of outbound PCI ATMUs for IO resource\n");
+ else {
+ dev_dbg(pci->dev,
+ "PCI IO resource start 0x%016llx,"
+ "size 0x%016llx, phy base 0x%016llx.\n",
+ (u64)pci->io_resource.start,
+ (u64)resource_size(&pci->io_resource),
+ (u64)pci->io_base_phys);
+ iowrite32be(pci->io_resource.start >> 12,
+ &pci->regs->pow[j].potar);
+ iowrite32be(0, &pci->regs->pow[j].potear);
+ iowrite32be(pci->io_base_phys >> 12,
+ &pci->regs->pow[j].powbar);
/* Enable, IO R/W */
- out_be32(&pci->pow[j].powar, 0x80088000
- | (ilog2(hose->io_resource.end
- - hose->io_resource.start + 1) - 1));
+ iowrite32be(0x80088000 |
+ (ilog2(resource_size(&pci->io_resource)) - 1),
+ &pci->regs->pow[j].powar);
}
}
@@ -191,18 +355,20 @@ static void setup_pci_atmu(struct pci_controller *hose)
paddr_lo -= offset;
if (paddr_hi == paddr_lo) {
- pr_err("%s: No outbound window space\n", name);
+ dev_err(pci->dev, "No outbound window space\n");
return;
}
if (paddr_lo == 0) {
- pr_err("%s: No space for inbound window\n", name);
+ dev_err(pci->dev, "No space for inbound window\n");
return;
}
/* setup PCSRBAR/PEXCSRBAR */
- early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
- early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
+ early_fsl_write_config_dword(pci, 0, 0, PCI_BASE_ADDRESS_0,
+ 0xffffffff);
+ early_fsl_read_config_dword(pci, 0, 0, PCI_BASE_ADDRESS_0,
+ &pcicsrbar_sz);
pcicsrbar_sz = ~pcicsrbar_sz + 1;
if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
@@ -210,11 +376,12 @@ static void setup_pci_atmu(struct pci_controller *hose)
pcicsrbar = 0x100000000ull - pcicsrbar_sz;
else
pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
- early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
+ early_fsl_write_config_dword(pci, 0, 0, PCI_BASE_ADDRESS_0,
+ pcicsrbar);
- paddr_lo = min(paddr_lo, (u64)pcicsrbar);
+ paddr_lo = min_t(u64, paddr_lo, pcicsrbar);
- pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
+ dev_info(pci->dev, "PCICSRBAR @ 0x%x\n", pcicsrbar);
/* Setup inbound mem window */
mem = memblock_end_of_DRAM();
@@ -231,17 +398,19 @@ static void setup_pci_atmu(struct pci_controller *hose)
* can avoid allocating a new ATMU by extending the DDR ATMU by one
* page.
*/
- reg = of_get_property(hose->dn, "msi-address-64", &len);
+ reg = of_get_property(pci->dn, "msi-address-64", &len);
if (reg && (len == sizeof(u64))) {
u64 address = be64_to_cpup(reg);
if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
- pr_info("%s: extending DDR ATMU to cover MSIIR", name);
+ dev_info(pci->dev,
+ "extending DDR ATMU to cover MSIIR\n");
mem += PAGE_SIZE;
} else {
/* TODO: Create a new ATMU for MSIIR */
- pr_warn("%s: msi-address-64 address of %llx is "
- "unsupported\n", name, address);
+ dev_warn(pci->dev,
+ "msi-address-64 address of %llx is "
+ "unsupported\n", address);
}
}
@@ -249,25 +418,26 @@ static void setup_pci_atmu(struct pci_controller *hose)
mem_log = ilog2(sz);
/* PCIe can overmap inbound & outbound since RX & TX are separated */
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
+ if (pci->is_pcie) {
/* Size window to exact size if power-of-two or one size up */
if ((1ull << mem_log) != mem) {
mem_log++;
if ((1ull << mem_log) > mem)
- pr_info("%s: Setting PCI inbound window "
- "greater than memory size\n", name);
+ dev_info(pci->dev,
+ "Setting PCI inbound window "
+ "greater than memory size\n");
}
piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
/* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwar, piwar);
+ iowrite32be(0, &pci->regs->piw[win_idx].pitar);
+ iowrite32be(0, &pci->regs->piw[win_idx].piwbar);
+ iowrite32be(piwar, &pci->regs->piw[win_idx].piwar);
win_idx--;
- hose->dma_window_base_cur = 0x00000000;
- hose->dma_window_size = (resource_size_t)sz;
+ pci->dma_window_base_cur = 0x00000000;
+ pci->dma_window_size = (resource_size_t)sz;
/*
* if we have >4G of memory setup second PCI inbound window to
@@ -284,28 +454,22 @@ static void setup_pci_atmu(struct pci_controller *hose)
piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
/* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwbear,
- pci64_dma_offset >> 44);
- out_be32(&pci->piw[win_idx].piwbar,
- pci64_dma_offset >> 12);
- out_be32(&pci->piw[win_idx].piwar, piwar);
-
- /*
- * install our own dma_set_mask handler to fixup dma_ops
- * and dma_offset
- */
- ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
-
- pr_info("%s: Setup 64-bit PCI DMA window\n", name);
+ iowrite32be(0, &pci->regs->piw[win_idx].pitar);
+ iowrite32be(fsl_arch_pci64_dma_offset() >> 44,
+ &pci->regs->piw[win_idx].piwbear);
+ iowrite32be(fsl_arch_pci64_dma_offset() >> 12,
+ &pci->regs->piw[win_idx].piwbar);
+ iowrite32be(piwar,
+ &pci->regs->piw[win_idx].piwar);
}
} else {
u64 paddr = 0;
/* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
+ iowrite32be(paddr >> 12, &pci->regs->piw[win_idx].pitar);
+ iowrite32be(paddr >> 12, &pci->regs->piw[win_idx].piwbar);
+ iowrite32be((piwar | (mem_log - 1)),
+ &pci->regs->piw[win_idx].piwar);
win_idx--;
paddr += 1ull << mem_log;
@@ -315,167 +479,182 @@ static void setup_pci_atmu(struct pci_controller *hose)
mem_log = ilog2(sz);
piwar |= (mem_log - 1);
- out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwar, piwar);
+ iowrite32be(paddr >> 12,
+ &pci->regs->piw[win_idx].pitar);
+ iowrite32be(paddr >> 12,
+ &pci->regs->piw[win_idx].piwbar);
+ iowrite32be(piwar,
+ &pci->regs->piw[win_idx].piwar);
win_idx--;
paddr += 1ull << mem_log;
}
- hose->dma_window_base_cur = 0x00000000;
- hose->dma_window_size = (resource_size_t)paddr;
+ pci->dma_window_base_cur = 0x00000000;
+ pci->dma_window_size = (resource_size_t)paddr;
}
- if (hose->dma_window_size < mem) {
-#ifdef CONFIG_SWIOTLB
- ppc_swiotlb_enable = 1;
-#else
- pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
- "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
- name);
+ if (pci->dma_window_size < mem) {
+#ifndef CONFIG_SWIOTLB
+ dev_err(pci->dev,
+ "Memory size exceeds PCI ATMU ability to "
+ "map - enable CONFIG_SWIOTLB to avoid dma errors.\n");
#endif
/* adjusting outbound windows could reclaim space in mem map */
if (paddr_hi < 0xffffffffull)
- pr_warning("%s: WARNING: Outbound window cfg leaves "
+ dev_warn(pci->dev,
+ "Outbound window cfg leaves "
"gaps in memory map. Adjusting the memory map "
- "could reduce unnecessary bounce buffering.\n",
- name);
+ "could reduce unnecessary bounce buffering.\n");
- pr_info("%s: DMA window size is 0x%llx\n", name,
- (u64)hose->dma_window_size);
+ dev_info(pci->dev, "DMA window size is 0x%llx\n",
+ (u64)pci->dma_window_size);
}
}
-static void __init setup_pci_cmd(struct pci_controller *hose)
+static void __init setup_pci_cmd(struct fsl_pci *pci)
{
u16 cmd;
int cap_x;
- early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
+ early_fsl_read_config_word(pci, 0, 0, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
| PCI_COMMAND_IO;
- early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
+ early_fsl_write_config_word(pci, 0, 0, PCI_COMMAND, cmd);
- cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
+ cap_x = early_fsl_find_capability(pci, 0, 0, PCI_CAP_ID_PCIX);
if (cap_x) {
int pci_x_cmd = cap_x + PCI_X_CMD;
cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
- } else {
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
- }
+ early_fsl_write_config_word(pci, 0, 0, pci_x_cmd, cmd);
+ } else
+ early_fsl_write_config_byte(pci, 0, 0, PCI_LATENCY_TIMER,
+ 0x80);
}
-int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
+static int __init
+fsl_pci_setup(struct platform_device *pdev, struct fsl_pci *pci)
{
- int len;
- struct pci_controller *hose;
- struct resource rsrc;
- const int *bus_range;
+ struct resource *rsrc;
u8 hdr_type, progif;
- struct device_node *dev;
- struct ccsr_pci __iomem *pci;
+ struct device_node *dn;
+ struct of_pci_range range;
+ struct of_pci_range_parser parser;
+ int mem = 0;
- dev = pdev->dev.of_node;
+ dn = pdev->dev.of_node;
+ pci->dn = dn;
+ pci->dev = &pdev->dev;
- if (!of_device_is_available(dev)) {
- pr_warning("%s: disabled\n", dev->full_name);
- return -ENODEV;
- }
-
- pr_debug("Adding PCI host bridge %s\n", dev->full_name);
+ dev_info(&pdev->dev, "Find controller %s\n", dn->full_name);
/* Fetch host bridge registers address */
- if (of_address_to_resource(dev, 0, &rsrc)) {
- printk(KERN_WARNING "Can't get pci register base!");
- return -ENOMEM;
+ rsrc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!rsrc) {
+ dev_err(&pdev->dev, "Can't get pci register base!");
+ return -EINVAL;
}
+ dev_info(&pdev->dev, "REG 0x%016llx..0x%016llx\n",
+ (u64)rsrc->start, (u64)rsrc->end);
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int))
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
-
- pci_add_flags(PCI_REASSIGN_ALL_BUS);
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
+ /* Parse pci range resources from device tree */
+ if (of_pci_range_parser_init(&parser, dn)) {
+ dev_err(&pdev->dev, "missing ranges property\n");
+ return -EINVAL;
+ }
- /* set platform device as the parent */
- hose->parent = &pdev->dev;
- hose->first_busno = bus_range ? bus_range[0] : 0x0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
+ /* Get the I/O and memory ranges from device tree */
+ for_each_of_pci_range(&parser, &range) {
+ unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
+ if (restype == IORESOURCE_IO) {
+ of_pci_range_to_resource(&range, dn,
+ &pci->io_resource);
+ pci->io_resource.name = "I/O";
+ pci->io_resource.start = range.pci_addr;
+ pci->io_resource.end = range.pci_addr + range.size - 1;
+ pci->pci_io_size = range.size;
+ pci->io_base_phys = range.cpu_addr - range.pci_addr;
+ dev_info(&pdev->dev,
+ " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
+ range.cpu_addr,
+ range.cpu_addr + range.size - 1,
+ range.pci_addr);
+ }
+ if (restype == IORESOURCE_MEM) {
+ if (mem >= 3)
+ continue;
+ of_pci_range_to_resource(&range, dn,
+ &pci->mem_resources[mem]);
+ pci->mem_resources[mem].name = "MEM";
+ pci->mem_offset[mem] = range.cpu_addr - range.pci_addr;
+ dev_info(&pdev->dev,
+ "MEM 0x%016llx..0x%016llx -> 0x%016llx\n",
+ (u64)pci->mem_resources[mem].start,
+ (u64)pci->mem_resources[mem].end,
+ range.pci_addr);
+ }
+ }
- pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
- (u64)rsrc.start, (u64)resource_size(&rsrc));
+ /* Get bus range */
+ if (of_pci_parse_bus_range(dn, &pci->busn)) {
+ dev_err(&pdev->dev, "failed to parse bus-range property\n");
+ pci->first_busno = 0x0;
+ pci->last_busno = 0xff;
+ } else {
+ pci->first_busno = pci->busn.start;
+ pci->last_busno = pci->busn.end;
+ }
+ dev_info(&pdev->dev, "Firmware bus number %d->%d\n",
+ pci->first_busno, pci->last_busno);
- pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
- if (!hose->private_data)
- goto no_bridge;
+ pci->regs = devm_ioremap_resource(&pdev->dev, rsrc);
+ if (IS_ERR(pci->regs))
+ return PTR_ERR(pci->regs);
- setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
- PPC_INDIRECT_TYPE_BIG_ENDIAN);
+ pci->ops = &fsl_indirect_pci_ops;
+ pci->indirect_type = INDIRECT_TYPE_BIG_ENDIAN;
- if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
- hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
+ if (in_be32(&pci->regs->block_rev1) < PCIE_IP_REV_3_0)
+ pci->indirect_type |= INDIRECT_TYPE_FSL_CFG_REG_LINK;
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- /* use fsl_indirect_read_config for PCIe */
- hose->ops = &fsl_indirect_pcie_ops;
- /* For PCIE read HEADER_TYPE to identify controler mode */
- early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
- if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
+ pci->is_pcie = early_fsl_find_capability(pci, 0, 0, PCI_CAP_ID_EXP);
+ if (pci->is_pcie) {
+ /* For PCIE read HEADER_TYPE to identify controller mode */
+ early_fsl_read_config_byte(pci, 0, 0, PCI_HEADER_TYPE,
+ &hdr_type);
+ if ((hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL)
goto no_bridge;
-
} else {
/* For PCI read PROG to identify controller mode */
- early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
+ early_fsl_read_config_byte(pci, 0, 0, PCI_CLASS_PROG, &progif);
if ((progif & 1) == 1)
goto no_bridge;
}
- setup_pci_cmd(hose);
+ setup_pci_cmd(pci);
/* check PCI express link status */
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
- PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
- if (fsl_pcie_check_link(hose))
- hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+ if (pci->is_pcie) {
+ pci->indirect_type |= INDIRECT_TYPE_EXT_REG |
+ INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
+ if (fsl_pci_check_link(pci))
+ pci->indirect_type |= INDIRECT_TYPE_NO_PCIE_LINK;
}
- printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long long)rsrc.start, hose->first_busno,
- hose->last_busno);
-
- pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, is_primary);
-
/* Setup PEX window registers */
- setup_pci_atmu(hose);
+ setup_pci_atmu(pci);
+
+ platform_set_drvdata(pdev, pci);
return 0;
no_bridge:
- iounmap(hose->private_data);
- /* unmap cfg_data & cfg_addr separately if not on same page */
- if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
- ((unsigned long)hose->cfg_addr & PAGE_MASK))
- iounmap(hose->cfg_data);
- iounmap(hose->cfg_addr);
- pcibios_free_controller(hose);
- return -ENODEV;
+ dev_info(&pdev->dev, "It works as EP mode\n");
+ return -EPERM;
}
-static const struct of_device_id pci_ids[] = {
+const struct of_device_id fsl_pci_ids[] = {
{ .compatible = "fsl,mpc8540-pci", },
{ .compatible = "fsl,mpc8548-pcie", },
{ .compatible = "fsl,mpc8610-pci", },
@@ -496,35 +675,63 @@ static const struct of_device_id pci_ids[] = {
{},
};
-static int fsl_pci_probe(struct platform_device *pdev)
+static int __init fsl_pci_probe(struct platform_device *pdev)
{
int ret;
- struct device_node *node;
+ struct fsl_pci *pci;
+
+ if (!of_device_is_available(pdev->dev.of_node)) {
+ dev_warn(&pdev->dev, "disabled\n");
+ return -ENODEV;
+ }
+
+ if (!fsl_arch_pci_sys_register) {
+ dev_err(&pdev->dev,
+ "no fsl_arch_pci_sys_register implementation\n");
+ return -EPERM;
+ }
+
+ pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci) {
+ dev_err(&pdev->dev, "no memory for fsl_pci\n");
+ return -ENOMEM;
+ }
- node = pdev->dev.of_node;
- ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
+ ret = fsl_pci_setup(pdev, pci);
+ if (ret)
+ return ret;
- mpc85xx_pci_err_probe(pdev);
+ ret = fsl_arch_pci_sys_register(pci);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register pcie to Arch\n");
+ return ret;
+ }
return 0;
}
-#ifdef CONFIG_PM
-static int fsl_pci_resume(struct device *dev)
+static int __exit fsl_pci_remove(struct platform_device *pdev)
{
- struct pci_controller *hose;
- struct resource pci_rsrc;
+ struct fsl_pci *pci = platform_get_drvdata(pdev);
- hose = pci_find_hose_for_OF_device(dev->of_node);
- if (!hose)
+ if (!pci)
return -ENODEV;
- if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
- dev_err(dev, "Get pci register base failed.");
+ if (fsl_arch_pci_sys_remove)
+ fsl_arch_pci_sys_remove(pci);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int fsl_pci_resume(struct device *dev)
+{
+ struct fsl_pci *pci = dev_get_drvdata(dev);
+
+ if (!pci)
return -ENODEV;
- }
- setup_pci_atmu(hose);
+ setup_pci_atmu(pci);
return 0;
}
@@ -545,9 +752,10 @@ static struct platform_driver fsl_pci_driver = {
.driver = {
.name = "fsl-pci",
.pm = PCI_PM_OPS,
- .of_match_table = pci_ids,
+ .of_match_table = fsl_pci_ids,
},
.probe = fsl_pci_probe,
+ .remove = fsl_pci_remove,
};
static int __init fsl_pci_init(void)
diff --git a/include/linux/fsl/pci.h b/include/linux/fsl/pci.h
index bfc241d..401d840 100644
--- a/include/linux/fsl/pci.h
+++ b/include/linux/fsl/pci.h
@@ -102,5 +102,74 @@ struct ccsr_pci {
};
+/*
+ * Structure of a PCI controller (host bridge)
+ */
+struct fsl_pci {
+ struct list_head node;
+ int is_pcie;
+ struct device_node *dn;
+ struct device *dev;
+
+ int first_busno;
+ int last_busno;
+ int self_busno;
+ struct resource busn;
+
+ struct pci_ops *ops;
+ struct ccsr_pci __iomem *regs;
+
+ u32 indirect_type;
+
+ struct resource io_resource;
+ resource_size_t io_base_phys;
+ resource_size_t pci_io_size;
+
+ struct resource mem_resources[3];
+ resource_size_t mem_offset[3];
+
+ int global_number; /* PCI domain number */
+
+ resource_size_t dma_window_base_cur;
+ resource_size_t dma_window_size;
+
+ void *sys;
+};
+
+/* Return link status 0-> link, 1-> no link */
+int fsl_pci_check_link(struct fsl_pci *pci);
+
+/*
+ * The fsl_arch_* functions are arch hooks. Those functions are
+ * implemented as weak symbols so that they can be overridden by
+ * architecture specific code if needed.
+ */
+
+/* Return PCI64 DMA offset */
+u64 fsl_arch_pci64_dma_offset(void);
+
+/*
+ * Convert architecture specific pci controller structure to fsl_pci
+ * PowerPC uses structure pci_controller and ARM uses structure pci_sys_data
+ * to describe pci controller.
+ */
+struct fsl_pci *fsl_arch_sys_to_pci(void *sys);
+
+/*
+ * To fake a PCI bus
+ * it is called by early_fsl_*(), at that time the architecture-dependent
+ * pci controller and pci bus have not been created.
+ */
+struct pci_bus *fsl_arch_fake_pci_bus(struct fsl_pci *pci, int busnr);
+
+/* To avoid touching specified devices */
+int fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn);
+
+/* Register PCI/PCIe controller to architecture system */
+int __weak fsl_arch_pci_sys_register(struct fsl_pci *pci);
+
+/* Remove PCI/PCIe controller from architecture system */
+void __weak fsl_arch_pci_sys_remove(struct fsl_pci *pci);
+
#endif /* __PCI_H */
#endif /* __KERNEL__ */
--
1.8.1.2
^ permalink raw reply related
* [PATCH 1/2][RFC][v3] pci: fsl: derive the common PCI driver to drivers/pci/host
From: Minghuan Lian @ 2013-09-12 10:07 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Minghuan Lian, Zang Roy-R61911
The Freescale's Layerscape series processors will use ARM cores.
The LS1's PCIe controllers is the same as T4240's. So it's better
the PCIe controller driver can support PowerPC and ARM
simultaneously. This patch is for this purpose. It derives
the common functions from arch/powerpc/sysdev/fsl_pci.c to
drivers/pci/host/pci-fsl.c and leaves the architecture-specific
functions which should be implemented in arch related files.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
Based on upstream master
Change log:
v3:
1. Add the new patch that only contains the code movement.
V2:
NULL
arch/powerpc/sysdev/fsl_pci.c | 521 +-----------------
arch/powerpc/sysdev/fsl_pci.h | 89 ----
.../sysdev/fsl_pci.c => drivers/pci/host/pci-fsl.c | 591 +--------------------
.../sysdev/fsl_pci.h => include/linux/fsl/pci.h | 40 +-
4 files changed, 7 insertions(+), 1234 deletions(-)
copy arch/powerpc/sysdev/fsl_pci.c => drivers/pci/host/pci-fsl.c (54%)
copy arch/powerpc/sysdev/fsl_pci.h => include/linux/fsl/pci.h (81%)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index ccfb50d..a189ff0 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -27,6 +27,7 @@
#include <linux/log2.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
+#include <linux/fsl/pci.h>
#include <asm/io.h>
#include <asm/prom.h>
@@ -58,57 +59,8 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
return;
}
-static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
- int, int, u32 *);
-
-static int fsl_pcie_check_link(struct pci_controller *hose)
-{
- u32 val = 0;
-
- if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
- if (hose->ops->read == fsl_indirect_read_config) {
- struct pci_bus bus;
- bus.number = hose->first_busno;
- bus.sysdata = hose;
- bus.ops = hose->ops;
- indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
- } else
- early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
- if (val < PCIE_LTSSM_L0)
- return 1;
- } else {
- struct ccsr_pci __iomem *pci = hose->private_data;
- /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
- val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
- >> PEX_CSR0_LTSSM_SHIFT;
- if (val != PEX_CSR0_LTSSM_L0)
- return 1;
- }
-
- return 0;
-}
-
-static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
- int offset, int len, u32 *val)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
-
- if (fsl_pcie_check_link(hose))
- hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
- else
- hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
-
- return indirect_read_config(bus, devfn, offset, len, val);
-}
-
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
-static struct pci_ops fsl_indirect_pcie_ops =
-{
- .read = fsl_indirect_read_config,
- .write = indirect_write_config,
-};
-
#define MAX_PHYS_ADDR_BITS 40
static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
@@ -132,291 +84,6 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
return 0;
}
-static int setup_one_atmu(struct ccsr_pci __iomem *pci,
- unsigned int index, const struct resource *res,
- resource_size_t offset)
-{
- resource_size_t pci_addr = res->start - offset;
- resource_size_t phys_addr = res->start;
- resource_size_t size = resource_size(res);
- u32 flags = 0x80044000; /* enable & mem R/W */
- unsigned int i;
-
- pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
- (u64)res->start, (u64)size);
-
- if (res->flags & IORESOURCE_PREFETCH)
- flags |= 0x10000000; /* enable relaxed ordering */
-
- for (i = 0; size > 0; i++) {
- unsigned int bits = min(ilog2(size),
- __ffs(pci_addr | phys_addr));
-
- if (index + i >= 5)
- return -1;
-
- out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
- out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
- out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
- out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
-
- pci_addr += (resource_size_t)1U << bits;
- phys_addr += (resource_size_t)1U << bits;
- size -= (resource_size_t)1U << bits;
- }
-
- return i;
-}
-
-/* atmu setup for fsl pci/pcie controller */
-static void setup_pci_atmu(struct pci_controller *hose)
-{
- struct ccsr_pci __iomem *pci = hose->private_data;
- int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
- u64 mem, sz, paddr_hi = 0;
- u64 offset = 0, paddr_lo = ULLONG_MAX;
- u32 pcicsrbar = 0, pcicsrbar_sz;
- u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
- const char *name = hose->dn->full_name;
- const u64 *reg;
- int len;
-
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
- win_idx = 2;
- start_idx = 0;
- end_idx = 3;
- }
- }
-
- /* Disable all windows (except powar0 since it's ignored) */
- for(i = 1; i < 5; i++)
- out_be32(&pci->pow[i].powar, 0);
- for (i = start_idx; i < end_idx; i++)
- out_be32(&pci->piw[i].piwar, 0);
-
- /* Setup outbound MEM window */
- for(i = 0, j = 1; i < 3; i++) {
- if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
- continue;
-
- paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
- paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
-
- /* We assume all memory resources have the same offset */
- offset = hose->mem_offset[i];
- n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
-
- if (n < 0 || j >= 5) {
- pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
- hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
- } else
- j += n;
- }
-
- /* Setup outbound IO window */
- if (hose->io_resource.flags & IORESOURCE_IO) {
- if (j >= 5) {
- pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
- } else {
- pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
- "phy base 0x%016llx.\n",
- (u64)hose->io_resource.start,
- (u64)resource_size(&hose->io_resource),
- (u64)hose->io_base_phys);
- out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
- out_be32(&pci->pow[j].potear, 0);
- out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
- /* Enable, IO R/W */
- out_be32(&pci->pow[j].powar, 0x80088000
- | (ilog2(hose->io_resource.end
- - hose->io_resource.start + 1) - 1));
- }
- }
-
- /* convert to pci address space */
- paddr_hi -= offset;
- paddr_lo -= offset;
-
- if (paddr_hi == paddr_lo) {
- pr_err("%s: No outbound window space\n", name);
- return;
- }
-
- if (paddr_lo == 0) {
- pr_err("%s: No space for inbound window\n", name);
- return;
- }
-
- /* setup PCSRBAR/PEXCSRBAR */
- early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
- early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
- pcicsrbar_sz = ~pcicsrbar_sz + 1;
-
- if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
- (paddr_lo > 0x100000000ull))
- pcicsrbar = 0x100000000ull - pcicsrbar_sz;
- else
- pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
- early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
-
- paddr_lo = min(paddr_lo, (u64)pcicsrbar);
-
- pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
-
- /* Setup inbound mem window */
- mem = memblock_end_of_DRAM();
-
- /*
- * The msi-address-64 property, if it exists, indicates the physical
- * address of the MSIIR register. Normally, this register is located
- * inside CCSR, so the ATMU that covers all of CCSR is used. But if
- * this property exists, then we normally need to create a new ATMU
- * for it. For now, however, we cheat. The only entity that creates
- * this property is the Freescale hypervisor, and the address is
- * specified in the partition configuration. Typically, the address
- * is located in the page immediately after the end of DDR. If so, we
- * can avoid allocating a new ATMU by extending the DDR ATMU by one
- * page.
- */
- reg = of_get_property(hose->dn, "msi-address-64", &len);
- if (reg && (len == sizeof(u64))) {
- u64 address = be64_to_cpup(reg);
-
- if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
- pr_info("%s: extending DDR ATMU to cover MSIIR", name);
- mem += PAGE_SIZE;
- } else {
- /* TODO: Create a new ATMU for MSIIR */
- pr_warn("%s: msi-address-64 address of %llx is "
- "unsupported\n", name, address);
- }
- }
-
- sz = min(mem, paddr_lo);
- mem_log = ilog2(sz);
-
- /* PCIe can overmap inbound & outbound since RX & TX are separated */
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- /* Size window to exact size if power-of-two or one size up */
- if ((1ull << mem_log) != mem) {
- mem_log++;
- if ((1ull << mem_log) > mem)
- pr_info("%s: Setting PCI inbound window "
- "greater than memory size\n", name);
- }
-
- piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
-
- /* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwar, piwar);
- win_idx--;
-
- hose->dma_window_base_cur = 0x00000000;
- hose->dma_window_size = (resource_size_t)sz;
-
- /*
- * if we have >4G of memory setup second PCI inbound window to
- * let devices that are 64-bit address capable to work w/o
- * SWIOTLB and access the full range of memory
- */
- if (sz != mem) {
- mem_log = ilog2(mem);
-
- /* Size window up if we dont fit in exact power-of-2 */
- if ((1ull << mem_log) != mem)
- mem_log++;
-
- piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
-
- /* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwbear,
- pci64_dma_offset >> 44);
- out_be32(&pci->piw[win_idx].piwbar,
- pci64_dma_offset >> 12);
- out_be32(&pci->piw[win_idx].piwar, piwar);
-
- /*
- * install our own dma_set_mask handler to fixup dma_ops
- * and dma_offset
- */
- ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
-
- pr_info("%s: Setup 64-bit PCI DMA window\n", name);
- }
- } else {
- u64 paddr = 0;
-
- /* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
- win_idx--;
-
- paddr += 1ull << mem_log;
- sz -= 1ull << mem_log;
-
- if (sz) {
- mem_log = ilog2(sz);
- piwar |= (mem_log - 1);
-
- out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwar, piwar);
- win_idx--;
-
- paddr += 1ull << mem_log;
- }
-
- hose->dma_window_base_cur = 0x00000000;
- hose->dma_window_size = (resource_size_t)paddr;
- }
-
- if (hose->dma_window_size < mem) {
-#ifdef CONFIG_SWIOTLB
- ppc_swiotlb_enable = 1;
-#else
- pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
- "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
- name);
-#endif
- /* adjusting outbound windows could reclaim space in mem map */
- if (paddr_hi < 0xffffffffull)
- pr_warning("%s: WARNING: Outbound window cfg leaves "
- "gaps in memory map. Adjusting the memory map "
- "could reduce unnecessary bounce buffering.\n",
- name);
-
- pr_info("%s: DMA window size is 0x%llx\n", name,
- (u64)hose->dma_window_size);
- }
-}
-
-static void __init setup_pci_cmd(struct pci_controller *hose)
-{
- u16 cmd;
- int cap_x;
-
- early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
- | PCI_COMMAND_IO;
- early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
-
- cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
- if (cap_x) {
- int pci_x_cmd = cap_x + PCI_X_CMD;
- cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
- | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
- } else {
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
- }
-}
-
void fsl_pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_controller *hose = pci_bus_to_host(bus);
@@ -454,112 +121,6 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
}
}
-int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
-{
- int len;
- struct pci_controller *hose;
- struct resource rsrc;
- const int *bus_range;
- u8 hdr_type, progif;
- struct device_node *dev;
- struct ccsr_pci __iomem *pci;
-
- dev = pdev->dev.of_node;
-
- if (!of_device_is_available(dev)) {
- pr_warning("%s: disabled\n", dev->full_name);
- return -ENODEV;
- }
-
- pr_debug("Adding PCI host bridge %s\n", dev->full_name);
-
- /* Fetch host bridge registers address */
- if (of_address_to_resource(dev, 0, &rsrc)) {
- printk(KERN_WARNING "Can't get pci register base!");
- return -ENOMEM;
- }
-
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int))
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
-
- pci_add_flags(PCI_REASSIGN_ALL_BUS);
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
-
- /* set platform device as the parent */
- hose->parent = &pdev->dev;
- hose->first_busno = bus_range ? bus_range[0] : 0x0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
-
- pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
- (u64)rsrc.start, (u64)resource_size(&rsrc));
-
- pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
- if (!hose->private_data)
- goto no_bridge;
-
- setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
- PPC_INDIRECT_TYPE_BIG_ENDIAN);
-
- if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
- hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
-
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- /* use fsl_indirect_read_config for PCIe */
- hose->ops = &fsl_indirect_pcie_ops;
- /* For PCIE read HEADER_TYPE to identify controler mode */
- early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
- if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
- goto no_bridge;
-
- } else {
- /* For PCI read PROG to identify controller mode */
- early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
- if ((progif & 1) == 1)
- goto no_bridge;
- }
-
- setup_pci_cmd(hose);
-
- /* check PCI express link status */
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
- PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
- if (fsl_pcie_check_link(hose))
- hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
- }
-
- printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long long)rsrc.start, hose->first_busno,
- hose->last_busno);
-
- pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, is_primary);
-
- /* Setup PEX window registers */
- setup_pci_atmu(hose);
-
- return 0;
-
-no_bridge:
- iounmap(hose->private_data);
- /* unmap cfg_data & cfg_addr separately if not on same page */
- if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
- ((unsigned long)hose->cfg_addr & PAGE_MASK))
- iounmap(hose->cfg_data);
- iounmap(hose->cfg_addr);
- pcibios_free_controller(hose);
- return -ENODEV;
-}
#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
@@ -1029,26 +590,6 @@ int fsl_pci_mcheck_exception(struct pt_regs *regs)
#endif
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
-static const struct of_device_id pci_ids[] = {
- { .compatible = "fsl,mpc8540-pci", },
- { .compatible = "fsl,mpc8548-pcie", },
- { .compatible = "fsl,mpc8610-pci", },
- { .compatible = "fsl,mpc8641-pcie", },
- { .compatible = "fsl,qoriq-pcie-v2.1", },
- { .compatible = "fsl,qoriq-pcie-v2.2", },
- { .compatible = "fsl,qoriq-pcie-v2.3", },
- { .compatible = "fsl,qoriq-pcie-v2.4", },
- { .compatible = "fsl,qoriq-pcie-v3.0", },
-
- /*
- * The following entries are for compatibility with older device
- * trees.
- */
- { .compatible = "fsl,p1022-pcie", },
- { .compatible = "fsl,p4080-pcie", },
-
- {},
-};
struct device_node *fsl_pci_primary;
@@ -1083,64 +624,4 @@ void fsl_pci_assign_primary(void)
}
}
}
-
-static int fsl_pci_probe(struct platform_device *pdev)
-{
- int ret;
- struct device_node *node;
-
- node = pdev->dev.of_node;
- ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
-
- mpc85xx_pci_err_probe(pdev);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int fsl_pci_resume(struct device *dev)
-{
- struct pci_controller *hose;
- struct resource pci_rsrc;
-
- hose = pci_find_hose_for_OF_device(dev->of_node);
- if (!hose)
- return -ENODEV;
-
- if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
- dev_err(dev, "Get pci register base failed.");
- return -ENODEV;
- }
-
- setup_pci_atmu(hose);
-
- return 0;
-}
-
-static const struct dev_pm_ops pci_pm_ops = {
- .resume = fsl_pci_resume,
-};
-
-#define PCI_PM_OPS (&pci_pm_ops)
-
-#else
-
-#define PCI_PM_OPS NULL
-
-#endif
-
-static struct platform_driver fsl_pci_driver = {
- .driver = {
- .name = "fsl-pci",
- .pm = PCI_PM_OPS,
- .of_match_table = pci_ids,
- },
- .probe = fsl_pci_probe,
-};
-
-static int __init fsl_pci_init(void)
-{
- return platform_driver_register(&fsl_pci_driver);
-}
-arch_initcall(fsl_pci_init);
#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index defc422..bbef8ec 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -16,95 +16,6 @@
struct platform_device;
-#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
-#define PCIE_LTSSM_L0 0x16 /* L0 state */
-#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
-#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
-#define PIWAR_EN 0x80000000 /* Enable */
-#define PIWAR_PF 0x20000000 /* prefetch */
-#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
-#define PIWAR_READ_SNOOP 0x00050000
-#define PIWAR_WRITE_SNOOP 0x00005000
-#define PIWAR_SZ_MASK 0x0000003f
-
-/* PCI/PCI Express outbound window reg */
-struct pci_outbound_window_regs {
- __be32 potar; /* 0x.0 - Outbound translation address register */
- __be32 potear; /* 0x.4 - Outbound translation extended address register */
- __be32 powbar; /* 0x.8 - Outbound window base address register */
- u8 res1[4];
- __be32 powar; /* 0x.10 - Outbound window attributes register */
- u8 res2[12];
-};
-
-/* PCI/PCI Express inbound window reg */
-struct pci_inbound_window_regs {
- __be32 pitar; /* 0x.0 - Inbound translation address register */
- u8 res1[4];
- __be32 piwbar; /* 0x.8 - Inbound window base address register */
- __be32 piwbear; /* 0x.c - Inbound window base extended address register */
- __be32 piwar; /* 0x.10 - Inbound window attributes register */
- u8 res2[12];
-};
-
-/* PCI/PCI Express IO block registers for 85xx/86xx */
-struct ccsr_pci {
- __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
- __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
- __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
- __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
- __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
- __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
- __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
- u8 res2[4];
- __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
- __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
- __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
- __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
- u8 res3[3016];
- __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
- __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
-
-/* PCI/PCI Express outbound window 0-4
- * Window 0 is the default window and is the only window enabled upon reset.
- * The default outbound register set is used when a transaction misses
- * in all of the other outbound windows.
- */
- struct pci_outbound_window_regs pow[5];
- u8 res14[96];
- struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
- u8 res6[96];
-/* PCI/PCI Express inbound window 3-0
- * inbound window 1 supports only a 32-bit base address and does not
- * define an inbound window base extended address register.
- */
- struct pci_inbound_window_regs piw[4];
-
- __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
- u8 res21[4];
- __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
- u8 res22[4];
- __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
- u8 res23[12];
- __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
- u8 res24[4];
- __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
- __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
- __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
- __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
- u8 res_e38[200];
- __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
- u8 res_f04[16];
- __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
-#define PEX_CSR0_LTSSM_MASK 0xFC
-#define PEX_CSR0_LTSSM_SHIFT 2
-#define PEX_CSR0_LTSSM_L0 0x11
- __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
- u8 res_f1c[228];
-
-};
-
-extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
u64 fsl_pci_immrbar_base(struct pci_controller *hose);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/drivers/pci/host/pci-fsl.c
similarity index 54%
copy from arch/powerpc/sysdev/fsl_pci.c
copy to drivers/pci/host/pci-fsl.c
index ccfb50d..69d338b 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/drivers/pci/host/pci-fsl.c
@@ -1,5 +1,5 @@
/*
- * MPC83xx/85xx/86xx PCI/PCIE support routing.
+ * 85xx/86xx/LS PCI/PCIE support routing.
*
* Copyright 2007-2012 Freescale Semiconductor, Inc.
* Copyright 2008-2009 MontaVista Software, Inc.
@@ -8,9 +8,6 @@
* Recode: ZHANG WEI <wei.zhang@freescale.com>
* Rewrite the routing for Frescale PCI and PCI Express
* Roy Zang <tie-fei.zang@freescale.com>
- * MPC83xx PCI-Express support:
- * Tony Li <tony.li@freescale.com>
- * Anton Vorontsov <avorontsov@ru.mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -38,29 +35,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
-static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
-
-static void quirk_fsl_pcie_header(struct pci_dev *dev)
-{
- u8 hdr_type;
-
- /* if we aren't a PCIe don't bother */
- if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
- return;
-
- /* if we aren't in host mode don't bother */
- pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
- if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
- return;
-
- dev->class = PCI_CLASS_BRIDGE_PCI << 8;
- fsl_pcie_bus_fixup = 1;
- return;
-}
-
-static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
- int, int, u32 *);
-
static int fsl_pcie_check_link(struct pci_controller *hose)
{
u32 val = 0;
@@ -109,29 +83,6 @@ static struct pci_ops fsl_indirect_pcie_ops =
.write = indirect_write_config,
};
-#define MAX_PHYS_ADDR_BITS 40
-static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
-
-static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
-{
- if (!dev->dma_mask || !dma_supported(dev, dma_mask))
- return -EIO;
-
- /*
- * Fixup PCI devices that are able to DMA to above the physical
- * address width of the SoC such that we can address any internal
- * SoC address from across PCI if needed
- */
- if ((dev->bus == &pci_bus_type) &&
- dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
- set_dma_ops(dev, &dma_direct_ops);
- set_dma_offset(dev, pci64_dma_offset);
- }
-
- *dev->dma_mask = dma_mask;
- return 0;
-}
-
static int setup_one_atmu(struct ccsr_pci __iomem *pci,
unsigned int index, const struct resource *res,
resource_size_t offset)
@@ -417,43 +368,6 @@ static void __init setup_pci_cmd(struct pci_controller *hose)
}
}
-void fsl_pcibios_fixup_bus(struct pci_bus *bus)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
- int i, is_pcie = 0, no_link;
-
- /* The root complex bridge comes up with bogus resources,
- * we copy the PHB ones in.
- *
- * With the current generic PCI code, the PHB bus no longer
- * has bus->resource[0..4] set, so things are a bit more
- * tricky.
- */
-
- if (fsl_pcie_bus_fixup)
- is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
- no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
-
- if (bus->parent == hose->bus && (is_pcie || no_link)) {
- for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
- struct resource *res = bus->resource[i];
- struct resource *par;
-
- if (!res)
- continue;
- if (i == 0)
- par = &hose->io_resource;
- else if (i < 4)
- par = &hose->mem_resources[i-1];
- else par = NULL;
-
- res->start = par ? par->start : 0;
- res->end = par ? par->end : 0;
- res->flags = par ? par->flags : 0;
- }
- }
-}
-
int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
{
int len;
@@ -560,475 +474,7 @@ no_bridge:
pcibios_free_controller(hose);
return -ENODEV;
}
-#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
-
-#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
-struct mpc83xx_pcie_priv {
- void __iomem *cfg_type0;
- void __iomem *cfg_type1;
- u32 dev_base;
-};
-
-struct pex_inbound_window {
- u32 ar;
- u32 tar;
- u32 barl;
- u32 barh;
-};
-
-/*
- * With the convention of u-boot, the PCIE outbound window 0 serves
- * as configuration transactions outbound.
- */
-#define PEX_OUTWIN0_BAR 0xCA4
-#define PEX_OUTWIN0_TAL 0xCA8
-#define PEX_OUTWIN0_TAH 0xCAC
-#define PEX_RC_INWIN_BASE 0xE60
-#define PEX_RCIWARn_EN 0x1
-
-static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
-
- if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
- return PCIBIOS_DEVICE_NOT_FOUND;
- /*
- * Workaround for the HW bug: for Type 0 configure transactions the
- * PCI-E controller does not check the device number bits and just
- * assumes that the device number bits are 0.
- */
- if (bus->number == hose->first_busno ||
- bus->primary == hose->first_busno) {
- if (devfn & 0xf8)
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- if (ppc_md.pci_exclude_device) {
- if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
- unsigned int devfn, int offset)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
- struct mpc83xx_pcie_priv *pcie = hose->dn->data;
- u32 dev_base = bus->number << 24 | devfn << 16;
- int ret;
-
- ret = mpc83xx_pcie_exclude_device(bus, devfn);
- if (ret)
- return NULL;
-
- offset &= 0xfff;
-
- /* Type 0 */
- if (bus->number == hose->first_busno)
- return pcie->cfg_type0 + offset;
-
- if (pcie->dev_base == dev_base)
- goto mapped;
-
- out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
-
- pcie->dev_base = dev_base;
-mapped:
- return pcie->cfg_type1 + offset;
-}
-
-static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
- int offset, int len, u32 *val)
-{
- void __iomem *cfg_addr;
-
- cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
- if (!cfg_addr)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- switch (len) {
- case 1:
- *val = in_8(cfg_addr);
- break;
- case 2:
- *val = in_le16(cfg_addr);
- break;
- default:
- *val = in_le32(cfg_addr);
- break;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
- int offset, int len, u32 val)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
- void __iomem *cfg_addr;
-
- cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
- if (!cfg_addr)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
- if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
- val &= 0xffffff00;
-
- switch (len) {
- case 1:
- out_8(cfg_addr, val);
- break;
- case 2:
- out_le16(cfg_addr, val);
- break;
- default:
- out_le32(cfg_addr, val);
- break;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops mpc83xx_pcie_ops = {
- .read = mpc83xx_pcie_read_config,
- .write = mpc83xx_pcie_write_config,
-};
-
-static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
- struct resource *reg)
-{
- struct mpc83xx_pcie_priv *pcie;
- u32 cfg_bar;
- int ret = -ENOMEM;
-
- pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
- if (!pcie)
- return ret;
-
- pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
- if (!pcie->cfg_type0)
- goto err0;
-
- cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
- if (!cfg_bar) {
- /* PCI-E isn't configured. */
- ret = -ENODEV;
- goto err1;
- }
-
- pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
- if (!pcie->cfg_type1)
- goto err1;
-
- WARN_ON(hose->dn->data);
- hose->dn->data = pcie;
- hose->ops = &mpc83xx_pcie_ops;
- hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
-
- out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
- out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
-
- if (fsl_pcie_check_link(hose))
- hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
-
- return 0;
-err1:
- iounmap(pcie->cfg_type0);
-err0:
- kfree(pcie);
- return ret;
-
-}
-
-int __init mpc83xx_add_bridge(struct device_node *dev)
-{
- int ret;
- int len;
- struct pci_controller *hose;
- struct resource rsrc_reg;
- struct resource rsrc_cfg;
- const int *bus_range;
- int primary;
-
- is_mpc83xx_pci = 1;
-
- if (!of_device_is_available(dev)) {
- pr_warning("%s: disabled by the firmware.\n",
- dev->full_name);
- return -ENODEV;
- }
- pr_debug("Adding PCI host bridge %s\n", dev->full_name);
-
- /* Fetch host bridge registers address */
- if (of_address_to_resource(dev, 0, &rsrc_reg)) {
- printk(KERN_WARNING "Can't get pci register base!\n");
- return -ENOMEM;
- }
-
- memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
-
- if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
- printk(KERN_WARNING
- "No pci config register base in dev tree, "
- "using default\n");
- /*
- * MPC83xx supports up to two host controllers
- * one at 0x8500 has config space registers at 0x8300
- * one at 0x8600 has config space registers at 0x8380
- */
- if ((rsrc_reg.start & 0xfffff) == 0x8500)
- rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
- else if ((rsrc_reg.start & 0xfffff) == 0x8600)
- rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
- }
- /*
- * Controller at offset 0x8500 is primary
- */
- if ((rsrc_reg.start & 0xfffff) == 0x8500)
- primary = 1;
- else
- primary = 0;
-
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int)) {
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
- }
-
- pci_add_flags(PCI_REASSIGN_ALL_BUS);
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
-
- hose->first_busno = bus_range ? bus_range[0] : 0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
-
- if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
- ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
- if (ret)
- goto err0;
- } else {
- setup_indirect_pci(hose, rsrc_cfg.start,
- rsrc_cfg.start + 4, 0);
- }
-
- printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long long)rsrc_reg.start, hose->first_busno,
- hose->last_busno);
-
- pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, primary);
-
- return 0;
-err0:
- pcibios_free_controller(hose);
- return ret;
-}
-#endif /* CONFIG_PPC_83xx */
-
-u64 fsl_pci_immrbar_base(struct pci_controller *hose)
-{
-#ifdef CONFIG_PPC_83xx
- if (is_mpc83xx_pci) {
- struct mpc83xx_pcie_priv *pcie = hose->dn->data;
- struct pex_inbound_window *in;
- int i;
-
- /* Walk the Root Complex Inbound windows to match IMMR base */
- in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
- for (i = 0; i < 4; i++) {
- /* not enabled, skip */
- if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
- continue;
-
- if (get_immrbase() == in_le32(&in[i].tar))
- return (u64)in_le32(&in[i].barh) << 32 |
- in_le32(&in[i].barl);
- }
-
- printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
- }
-#endif
-
-#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
- if (!is_mpc83xx_pci) {
- u32 base;
-
- pci_bus_read_config_dword(hose->bus,
- PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
- return base;
- }
-#endif
-
- return 0;
-}
-#ifdef CONFIG_E500
-static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
-{
- unsigned int rd, ra, rb, d;
-
- rd = get_rt(inst);
- ra = get_ra(inst);
- rb = get_rb(inst);
- d = get_d(inst);
-
- switch (get_op(inst)) {
- case 31:
- switch (get_xop(inst)) {
- case OP_31_XOP_LWZX:
- case OP_31_XOP_LWBRX:
- regs->gpr[rd] = 0xffffffff;
- break;
-
- case OP_31_XOP_LWZUX:
- regs->gpr[rd] = 0xffffffff;
- regs->gpr[ra] += regs->gpr[rb];
- break;
-
- case OP_31_XOP_LBZX:
- regs->gpr[rd] = 0xff;
- break;
-
- case OP_31_XOP_LBZUX:
- regs->gpr[rd] = 0xff;
- regs->gpr[ra] += regs->gpr[rb];
- break;
-
- case OP_31_XOP_LHZX:
- case OP_31_XOP_LHBRX:
- regs->gpr[rd] = 0xffff;
- break;
-
- case OP_31_XOP_LHZUX:
- regs->gpr[rd] = 0xffff;
- regs->gpr[ra] += regs->gpr[rb];
- break;
-
- case OP_31_XOP_LHAX:
- regs->gpr[rd] = ~0UL;
- break;
-
- case OP_31_XOP_LHAUX:
- regs->gpr[rd] = ~0UL;
- regs->gpr[ra] += regs->gpr[rb];
- break;
-
- default:
- return 0;
- }
- break;
-
- case OP_LWZ:
- regs->gpr[rd] = 0xffffffff;
- break;
-
- case OP_LWZU:
- regs->gpr[rd] = 0xffffffff;
- regs->gpr[ra] += (s16)d;
- break;
-
- case OP_LBZ:
- regs->gpr[rd] = 0xff;
- break;
-
- case OP_LBZU:
- regs->gpr[rd] = 0xff;
- regs->gpr[ra] += (s16)d;
- break;
-
- case OP_LHZ:
- regs->gpr[rd] = 0xffff;
- break;
-
- case OP_LHZU:
- regs->gpr[rd] = 0xffff;
- regs->gpr[ra] += (s16)d;
- break;
-
- case OP_LHA:
- regs->gpr[rd] = ~0UL;
- break;
-
- case OP_LHAU:
- regs->gpr[rd] = ~0UL;
- regs->gpr[ra] += (s16)d;
- break;
-
- default:
- return 0;
- }
-
- return 1;
-}
-
-static int is_in_pci_mem_space(phys_addr_t addr)
-{
- struct pci_controller *hose;
- struct resource *res;
- int i;
-
- list_for_each_entry(hose, &hose_list, list_node) {
- if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
- continue;
-
- for (i = 0; i < 3; i++) {
- res = &hose->mem_resources[i];
- if ((res->flags & IORESOURCE_MEM) &&
- addr >= res->start && addr <= res->end)
- return 1;
- }
- }
- return 0;
-}
-
-int fsl_pci_mcheck_exception(struct pt_regs *regs)
-{
- u32 inst;
- int ret;
- phys_addr_t addr = 0;
-
- /* Let KVM/QEMU deal with the exception */
- if (regs->msr & MSR_GS)
- return 0;
-
-#ifdef CONFIG_PHYS_64BIT
- addr = mfspr(SPRN_MCARU);
- addr <<= 32;
-#endif
- addr += mfspr(SPRN_MCAR);
-
- if (is_in_pci_mem_space(addr)) {
- if (user_mode(regs)) {
- pagefault_disable();
- ret = get_user(regs->nip, &inst);
- pagefault_enable();
- } else {
- ret = probe_kernel_address(regs->nip, inst);
- }
-
- if (mcheck_handle_load(regs, inst)) {
- regs->nip += 4;
- return 1;
- }
- }
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
static const struct of_device_id pci_ids[] = {
{ .compatible = "fsl,mpc8540-pci", },
{ .compatible = "fsl,mpc8548-pcie", },
@@ -1050,40 +496,6 @@ static const struct of_device_id pci_ids[] = {
{},
};
-struct device_node *fsl_pci_primary;
-
-void fsl_pci_assign_primary(void)
-{
- struct device_node *np;
-
- /* Callers can specify the primary bus using other means. */
- if (fsl_pci_primary)
- return;
-
- /* If a PCI host bridge contains an ISA node, it's primary. */
- np = of_find_node_by_type(NULL, "isa");
- while ((fsl_pci_primary = of_get_parent(np))) {
- of_node_put(np);
- np = fsl_pci_primary;
-
- if (of_match_node(pci_ids, np) && of_device_is_available(np))
- return;
- }
-
- /*
- * If there's no PCI host bridge with ISA, arbitrarily
- * designate one as primary. This can go away once
- * various bugs with primary-less systems are fixed.
- */
- for_each_matching_node(np, pci_ids) {
- if (of_device_is_available(np)) {
- fsl_pci_primary = np;
- of_node_put(np);
- return;
- }
- }
-}
-
static int fsl_pci_probe(struct platform_device *pdev)
{
int ret;
@@ -1143,4 +555,3 @@ static int __init fsl_pci_init(void)
return platform_driver_register(&fsl_pci_driver);
}
arch_initcall(fsl_pci_init);
-#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/include/linux/fsl/pci.h
similarity index 81%
copy from arch/powerpc/sysdev/fsl_pci.h
copy to include/linux/fsl/pci.h
index defc422..bfc241d 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/include/linux/fsl/pci.h
@@ -1,5 +1,5 @@
/*
- * MPC85xx/86xx PCI Express structure define
+ * MPC85xx/86xx/LS PCI Express structure define
*
* Copyright 2007,2011 Freescale Semiconductor, Inc
*
@@ -11,10 +11,8 @@
*/
#ifdef __KERNEL__
-#ifndef __POWERPC_FSL_PCI_H
-#define __POWERPC_FSL_PCI_H
-
-struct platform_device;
+#ifndef __PCI_H
+#define __PCI_H
#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
#define PCIE_LTSSM_L0 0x16 /* L0 state */
@@ -47,7 +45,7 @@ struct pci_inbound_window_regs {
u8 res2[12];
};
-/* PCI/PCI Express IO block registers for 85xx/86xx */
+/* PCI/PCI Express IO block registers for 85xx/86xx/LS */
struct ccsr_pci {
__be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
__be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
@@ -104,33 +102,5 @@ struct ccsr_pci {
};
-extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
-extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
-extern int mpc83xx_add_bridge(struct device_node *dev);
-u64 fsl_pci_immrbar_base(struct pci_controller *hose);
-
-extern struct device_node *fsl_pci_primary;
-
-#ifdef CONFIG_PCI
-void fsl_pci_assign_primary(void);
-#else
-static inline void fsl_pci_assign_primary(void) {}
-#endif
-
-#ifdef CONFIG_EDAC_MPC85XX
-int mpc85xx_pci_err_probe(struct platform_device *op);
-#else
-static inline int mpc85xx_pci_err_probe(struct platform_device *op)
-{
- return -ENOTSUPP;
-}
-#endif
-
-#ifdef CONFIG_FSL_PCI
-extern int fsl_pci_mcheck_exception(struct pt_regs *);
-#else
-static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
-#endif
-
-#endif /* __POWERPC_FSL_PCI_H */
+#endif /* __PCI_H */
#endif /* __KERNEL__ */
--
1.8.1.2
^ permalink raw reply related
* Re: [PATCH] powerpc 8xx: Reverting commit e0908085fc2391c85b85fb814ae1df377c8e0dcb which has become useless
From: Joakim Tjernlund @ 2013-09-12 8:13 UTC (permalink / raw)
To: Christophe Leroy; +Cc: linuxppc-dev, linux-kernel, Paul Mackerras
In-Reply-To: <201309111550.r8BFoS4G015798@localhost.localdomain>
Christophe Leroy <christophe.leroy@c-s.fr> wrote on 2013/09/11 17:50:28:
> From: Christophe Leroy <christophe.leroy@c-s.fr>
> To: Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras
<paulus@samba.org>,
> Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Joakim
Tjernlund <joakim.tjernlund@transmode.se>
> Date: 2013/09/11 18:43
> Subject: [PATCH] powerpc 8xx: Reverting commit
e0908085fc2391c85b85fb814ae1df377c8e0dcb which has become useless
>
> The commit e0908085fc2391c85b85fb814ae1df377c8e0dcb is not needed
anymore.
> The issue was because dcbst wrongly sets the store bit when causing a
DTLB
> error, but this is now fixed by commit
0a2ab51ffb8dfdf51402dcfb446629648c96bc78
> which handles the buggy dcbx instructions on data page faults on the
8xx.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Jocke
^ permalink raw reply
* [PATCH 2/2] powerpc/85xx: remove the unneeded corenet_ds.h
From: Kevin Hao @ 2013-09-12 7:13 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc
In-Reply-To: <1378969993-14991-1-git-send-email-haokexin@gmail.com>
With the patch (powerpc/85xx: introduce cornet_generic machine) this
file becomes useless. Just delete it.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
arch/powerpc/platforms/85xx/corenet_ds.h | 19 -------------------
1 file changed, 19 deletions(-)
delete mode 100644 arch/powerpc/platforms/85xx/corenet_ds.h
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.h b/arch/powerpc/platforms/85xx/corenet_ds.h
deleted file mode 100644
index ddd700b..0000000
--- a/arch/powerpc/platforms/85xx/corenet_ds.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Corenet based SoC DS Setup
- *
- * Copyright 2009 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef CORENET_DS_H
-#define CORENET_DS_H
-
-extern void __init corenet_ds_pic_init(void);
-extern void __init corenet_ds_setup_arch(void);
-extern int __init corenet_ds_publish_devices(void);
-
-#endif
--
1.8.3.1
^ permalink raw reply related
* [PATCH 1/2] powerpc/85xx: introduce cornet_generic machine
From: Kevin Hao @ 2013-09-12 7:13 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc
In-Reply-To: <1378969993-14991-1-git-send-email-haokexin@gmail.com>
In the current kernel, the board files for p2041rdb, p3041ds, p4080ds,
p5020ds, p5040ds, t4240qds and b4qds are almost the same except the
machine name. So this introduces a cornet_generic machine to support
all these boards to avoid the code duplication.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
This patch is based on http://patchwork.ozlabs.org/patch/274390/
arch/powerpc/platforms/85xx/Kconfig | 10 ++++
arch/powerpc/platforms/85xx/Makefile | 8 +--
arch/powerpc/platforms/85xx/b4_qds.c | 97 --------------------------------
arch/powerpc/platforms/85xx/corenet_ds.c | 86 ++++++++++++++++++++++++++++
arch/powerpc/platforms/85xx/p2041_rdb.c | 87 ----------------------------
arch/powerpc/platforms/85xx/p3041_ds.c | 89 -----------------------------
arch/powerpc/platforms/85xx/p4080_ds.c | 87 ----------------------------
arch/powerpc/platforms/85xx/p5020_ds.c | 93 ------------------------------
arch/powerpc/platforms/85xx/p5040_ds.c | 84 ---------------------------
arch/powerpc/platforms/85xx/t4240_qds.c | 93 ------------------------------
10 files changed, 97 insertions(+), 637 deletions(-)
delete mode 100644 arch/powerpc/platforms/85xx/b4_qds.c
delete mode 100644 arch/powerpc/platforms/85xx/p2041_rdb.c
delete mode 100644 arch/powerpc/platforms/85xx/p3041_ds.c
delete mode 100644 arch/powerpc/platforms/85xx/p4080_ds.c
delete mode 100644 arch/powerpc/platforms/85xx/p5020_ds.c
delete mode 100644 arch/powerpc/platforms/85xx/p5040_ds.c
delete mode 100644 arch/powerpc/platforms/85xx/t4240_qds.c
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index de2eb93..3bee943 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -228,6 +228,7 @@ config P2041_RDB
select GPIO_MPC8XXX
select HAS_RAPIDIO
select PPC_EPAPR_HV_PIC
+ select CORENET_GENERIC
help
This option enables support for the P2041 RDB board
@@ -241,6 +242,7 @@ config P3041_DS
select GPIO_MPC8XXX
select HAS_RAPIDIO
select PPC_EPAPR_HV_PIC
+ select CORENET_GENERIC
help
This option enables support for the P3041 DS board
@@ -254,6 +256,7 @@ config P4080_DS
select GPIO_MPC8XXX
select HAS_RAPIDIO
select PPC_EPAPR_HV_PIC
+ select CORENET_GENERIC
help
This option enables support for the P4080 DS board
@@ -278,6 +281,7 @@ config P5020_DS
select GPIO_MPC8XXX
select HAS_RAPIDIO
select PPC_EPAPR_HV_PIC
+ select CORENET_GENERIC
help
This option enables support for the P5020 DS board
@@ -292,6 +296,7 @@ config P5040_DS
select GPIO_MPC8XXX
select HAS_RAPIDIO
select PPC_EPAPR_HV_PIC
+ select CORENET_GENERIC
help
This option enables support for the P5040 DS board
@@ -323,6 +328,7 @@ config T4240_QDS
select GPIO_MPC8XXX
select HAS_RAPIDIO
select PPC_EPAPR_HV_PIC
+ select CORENET_GENERIC
help
This option enables support for the T4240 QDS board
@@ -337,6 +343,7 @@ config B4_QDS
select ARCH_REQUIRE_GPIOLIB
select HAS_RAPIDIO
select PPC_EPAPR_HV_PIC
+ select CORENET_GENERIC
help
This option enables support for the B4 QDS board
The B4 application development system B4 QDS is a complete
@@ -348,3 +355,6 @@ endif # FSL_SOC_BOOKE
config TQM85xx
bool
+
+config CORENET_GENERIC
+ bool
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 53c9f75..a6c281d 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -18,13 +18,7 @@ obj-$(CONFIG_P1010_RDB) += p1010rdb.o
obj-$(CONFIG_P1022_DS) += p1022_ds.o
obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
obj-$(CONFIG_P1023_RDS) += p1023_rds.o
-obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
-obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
-obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
-obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
-obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
-obj-$(CONFIG_T4240_QDS) += t4240_qds.o corenet_ds.o
-obj-$(CONFIG_B4_QDS) += b4_qds.o corenet_ds.o
+obj-$(CONFIG_CORENET_GENERIC) += corenet_ds.o
obj-$(CONFIG_STX_GP3) += stx_gp3.o
obj-$(CONFIG_TQM85xx) += tqm85xx.o
obj-$(CONFIG_SBC8548) += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/b4_qds.c b/arch/powerpc/platforms/85xx/b4_qds.c
deleted file mode 100644
index 0f18663..0000000
--- a/arch/powerpc/platforms/85xx/b4_qds.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * B4 QDS Setup
- * Should apply for QDS platform of B4860 and it's personalities.
- * viz B4860/B4420/B4220QDS
- *
- * Copyright 2012 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/phy.h>
-
-#include <asm/time.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <mm/mmu_decl.h>
-#include <asm/prom.h>
-#include <asm/udbg.h>
-#include <asm/mpic.h>
-
-#include <linux/of_platform.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pci.h>
-#include <asm/ehv_pic.h>
-
-#include "corenet_ds.h"
-
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init b4_qds_probe(void)
-{
- unsigned long root = of_get_flat_dt_root();
-#ifdef CONFIG_SMP
- extern struct smp_ops_t smp_85xx_ops;
-#endif
-
- if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
- (of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
- (of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
- return 1;
-
- /* Check if we're running under the Freescale hypervisor */
- if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
- (of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
- (of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
- ppc_md.init_IRQ = ehv_pic_init;
- ppc_md.get_irq = ehv_pic_get_irq;
- ppc_md.restart = fsl_hv_restart;
- ppc_md.power_off = fsl_hv_halt;
- ppc_md.halt = fsl_hv_halt;
-#ifdef CONFIG_SMP
- /*
- * Disable the timebase sync operations because we can't write
- * to the timebase registers under the hypervisor.
- */
- smp_85xx_ops.give_timebase = NULL;
- smp_85xx_ops.take_timebase = NULL;
-#endif
- return 1;
- }
-
- return 0;
-}
-
-define_machine(b4_qds) {
- .name = "B4 QDS",
- .probe = b4_qds_probe,
- .setup_arch = corenet_ds_setup_arch,
- .init_IRQ = corenet_ds_pic_init,
-#ifdef CONFIG_PCI
- .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
-#endif
- .get_irq = mpic_get_coreint_irq,
- .restart = fsl_rstcr_restart,
- .calibrate_decr = generic_calibrate_decr,
- .progress = udbg_progress,
-#ifdef CONFIG_PPC64
- .power_save = book3e_idle,
-#else
- .power_save = e500_idle,
-#endif
-};
-
-machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
-
-#ifdef CONFIG_SWIOTLB
-machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
-#endif
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index aa3690b..842d516c 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -25,6 +25,7 @@
#include <asm/prom.h>
#include <asm/udbg.h>
#include <asm/mpic.h>
+#include <asm/ehv_pic.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
@@ -94,3 +95,88 @@ int __init corenet_ds_publish_devices(void)
{
return of_platform_bus_probe(NULL, of_device_ids, NULL);
}
+
+static const char * const boards[] __initconst = {
+ "fsl,P2041RDB",
+ "fsl,P3041DS",
+ "fsl,P4080DS",
+ "fsl,P5020DS",
+ "fsl,P5040DS",
+ "fsl,T4240QDS",
+ "fsl,B4860QDS",
+ "fsl,B4420QDS",
+ "fsl,B4220QDS",
+ NULL
+};
+
+static const char * const hv_boards[] __initconst = {
+ "fsl,P2041RDB-hv",
+ "fsl,P3041DS-hv",
+ "fsl,P4080DS-hv",
+ "fsl,P5020DS-hv",
+ "fsl,P5040DS-hv",
+ "fsl,T4240QDS-hv",
+ "fsl,B4860QDS-hv",
+ "fsl,B4420QDS-hv",
+ "fsl,B4220QDS-hv",
+ NULL
+};
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init corenet_generic_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_SMP
+ extern struct smp_ops_t smp_85xx_ops;
+#endif
+
+ if (of_flat_dt_match(root, boards))
+ return 1;
+
+ /* Check if we're running under the Freescale hypervisor */
+ if (of_flat_dt_match(root, hv_boards)) {
+ ppc_md.init_IRQ = ehv_pic_init;
+ ppc_md.get_irq = ehv_pic_get_irq;
+ ppc_md.restart = fsl_hv_restart;
+ ppc_md.power_off = fsl_hv_halt;
+ ppc_md.halt = fsl_hv_halt;
+#ifdef CONFIG_SMP
+ /*
+ * Disable the timebase sync operations because we can't write
+ * to the timebase registers under the hypervisor.
+ */
+ smp_85xx_ops.give_timebase = NULL;
+ smp_85xx_ops.take_timebase = NULL;
+#endif
+ return 1;
+ }
+
+ return 0;
+}
+
+define_machine(corenet_generic) {
+ .name = "CORENET GENERIC",
+ .probe = corenet_generic_probe,
+ .setup_arch = corenet_ds_setup_arch,
+ .init_IRQ = corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq = mpic_get_coreint_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+#ifdef CONFIG_PPC64
+ .power_save = book3e_idle,
+#else
+ .power_save = e500_idle,
+#endif
+};
+
+machine_arch_initcall(corenet_generic, corenet_ds_publish_devices);
+
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(corenet_generic, swiotlb_setup_bus_notifier);
+#endif
diff --git a/arch/powerpc/platforms/85xx/p2041_rdb.c b/arch/powerpc/platforms/85xx/p2041_rdb.c
deleted file mode 100644
index 000c089..0000000
--- a/arch/powerpc/platforms/85xx/p2041_rdb.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * P2041 RDB Setup
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/phy.h>
-
-#include <asm/time.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <mm/mmu_decl.h>
-#include <asm/prom.h>
-#include <asm/udbg.h>
-#include <asm/mpic.h>
-
-#include <linux/of_platform.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pci.h>
-#include <asm/ehv_pic.h>
-
-#include "corenet_ds.h"
-
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init p2041_rdb_probe(void)
-{
- unsigned long root = of_get_flat_dt_root();
-#ifdef CONFIG_SMP
- extern struct smp_ops_t smp_85xx_ops;
-#endif
-
- if (of_flat_dt_is_compatible(root, "fsl,P2041RDB"))
- return 1;
-
- /* Check if we're running under the Freescale hypervisor */
- if (of_flat_dt_is_compatible(root, "fsl,P2041RDB-hv")) {
- ppc_md.init_IRQ = ehv_pic_init;
- ppc_md.get_irq = ehv_pic_get_irq;
- ppc_md.restart = fsl_hv_restart;
- ppc_md.power_off = fsl_hv_halt;
- ppc_md.halt = fsl_hv_halt;
-#ifdef CONFIG_SMP
- /*
- * Disable the timebase sync operations because we can't write
- * to the timebase registers under the hypervisor.
- */
- smp_85xx_ops.give_timebase = NULL;
- smp_85xx_ops.take_timebase = NULL;
-#endif
- return 1;
- }
-
- return 0;
-}
-
-define_machine(p2041_rdb) {
- .name = "P2041 RDB",
- .probe = p2041_rdb_probe,
- .setup_arch = corenet_ds_setup_arch,
- .init_IRQ = corenet_ds_pic_init,
-#ifdef CONFIG_PCI
- .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
-#endif
- .get_irq = mpic_get_coreint_irq,
- .restart = fsl_rstcr_restart,
- .calibrate_decr = generic_calibrate_decr,
- .progress = udbg_progress,
- .power_save = e500_idle,
-};
-
-machine_arch_initcall(p2041_rdb, corenet_ds_publish_devices);
-
-#ifdef CONFIG_SWIOTLB
-machine_arch_initcall(p2041_rdb, swiotlb_setup_bus_notifier);
-#endif
diff --git a/arch/powerpc/platforms/85xx/p3041_ds.c b/arch/powerpc/platforms/85xx/p3041_ds.c
deleted file mode 100644
index b3edc20..0000000
--- a/arch/powerpc/platforms/85xx/p3041_ds.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * P3041 DS Setup
- *
- * Maintained by Kumar Gala (see MAINTAINERS for contact information)
- *
- * Copyright 2009-2010 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/phy.h>
-
-#include <asm/time.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <mm/mmu_decl.h>
-#include <asm/prom.h>
-#include <asm/udbg.h>
-#include <asm/mpic.h>
-
-#include <linux/of_platform.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pci.h>
-#include <asm/ehv_pic.h>
-
-#include "corenet_ds.h"
-
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init p3041_ds_probe(void)
-{
- unsigned long root = of_get_flat_dt_root();
-#ifdef CONFIG_SMP
- extern struct smp_ops_t smp_85xx_ops;
-#endif
-
- if (of_flat_dt_is_compatible(root, "fsl,P3041DS"))
- return 1;
-
- /* Check if we're running under the Freescale hypervisor */
- if (of_flat_dt_is_compatible(root, "fsl,P3041DS-hv")) {
- ppc_md.init_IRQ = ehv_pic_init;
- ppc_md.get_irq = ehv_pic_get_irq;
- ppc_md.restart = fsl_hv_restart;
- ppc_md.power_off = fsl_hv_halt;
- ppc_md.halt = fsl_hv_halt;
-#ifdef CONFIG_SMP
- /*
- * Disable the timebase sync operations because we can't write
- * to the timebase registers under the hypervisor.
- */
- smp_85xx_ops.give_timebase = NULL;
- smp_85xx_ops.take_timebase = NULL;
-#endif
- return 1;
- }
-
- return 0;
-}
-
-define_machine(p3041_ds) {
- .name = "P3041 DS",
- .probe = p3041_ds_probe,
- .setup_arch = corenet_ds_setup_arch,
- .init_IRQ = corenet_ds_pic_init,
-#ifdef CONFIG_PCI
- .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
-#endif
- .get_irq = mpic_get_coreint_irq,
- .restart = fsl_rstcr_restart,
- .calibrate_decr = generic_calibrate_decr,
- .progress = udbg_progress,
- .power_save = e500_idle,
-};
-
-machine_arch_initcall(p3041_ds, corenet_ds_publish_devices);
-
-#ifdef CONFIG_SWIOTLB
-machine_arch_initcall(p3041_ds, swiotlb_setup_bus_notifier);
-#endif
diff --git a/arch/powerpc/platforms/85xx/p4080_ds.c b/arch/powerpc/platforms/85xx/p4080_ds.c
deleted file mode 100644
index 54df106..0000000
--- a/arch/powerpc/platforms/85xx/p4080_ds.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * P4080 DS Setup
- *
- * Maintained by Kumar Gala (see MAINTAINERS for contact information)
- *
- * Copyright 2009 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-
-#include <asm/time.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <mm/mmu_decl.h>
-#include <asm/prom.h>
-#include <asm/udbg.h>
-#include <asm/mpic.h>
-
-#include <linux/of_platform.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pci.h>
-#include <asm/ehv_pic.h>
-
-#include "corenet_ds.h"
-
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init p4080_ds_probe(void)
-{
- unsigned long root = of_get_flat_dt_root();
-#ifdef CONFIG_SMP
- extern struct smp_ops_t smp_85xx_ops;
-#endif
-
- if (of_flat_dt_is_compatible(root, "fsl,P4080DS"))
- return 1;
-
- /* Check if we're running under the Freescale hypervisor */
- if (of_flat_dt_is_compatible(root, "fsl,P4080DS-hv")) {
- ppc_md.init_IRQ = ehv_pic_init;
- ppc_md.get_irq = ehv_pic_get_irq;
- ppc_md.restart = fsl_hv_restart;
- ppc_md.power_off = fsl_hv_halt;
- ppc_md.halt = fsl_hv_halt;
-#ifdef CONFIG_SMP
- /*
- * Disable the timebase sync operations because we can't write
- * to the timebase registers under the hypervisor.
- */
- smp_85xx_ops.give_timebase = NULL;
- smp_85xx_ops.take_timebase = NULL;
-#endif
- return 1;
- }
-
- return 0;
-}
-
-define_machine(p4080_ds) {
- .name = "P4080 DS",
- .probe = p4080_ds_probe,
- .setup_arch = corenet_ds_setup_arch,
- .init_IRQ = corenet_ds_pic_init,
-#ifdef CONFIG_PCI
- .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
-#endif
- .get_irq = mpic_get_coreint_irq,
- .restart = fsl_rstcr_restart,
- .calibrate_decr = generic_calibrate_decr,
- .progress = udbg_progress,
- .power_save = e500_idle,
-};
-
-machine_arch_initcall(p4080_ds, corenet_ds_publish_devices);
-#ifdef CONFIG_SWIOTLB
-machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier);
-#endif
diff --git a/arch/powerpc/platforms/85xx/p5020_ds.c b/arch/powerpc/platforms/85xx/p5020_ds.c
deleted file mode 100644
index 39cfa40..0000000
--- a/arch/powerpc/platforms/85xx/p5020_ds.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * P5020 DS Setup
- *
- * Maintained by Kumar Gala (see MAINTAINERS for contact information)
- *
- * Copyright 2009-2010 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/phy.h>
-
-#include <asm/time.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <mm/mmu_decl.h>
-#include <asm/prom.h>
-#include <asm/udbg.h>
-#include <asm/mpic.h>
-
-#include <linux/of_platform.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pci.h>
-#include <asm/ehv_pic.h>
-
-#include "corenet_ds.h"
-
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init p5020_ds_probe(void)
-{
- unsigned long root = of_get_flat_dt_root();
-#ifdef CONFIG_SMP
- extern struct smp_ops_t smp_85xx_ops;
-#endif
-
- if (of_flat_dt_is_compatible(root, "fsl,P5020DS"))
- return 1;
-
- /* Check if we're running under the Freescale hypervisor */
- if (of_flat_dt_is_compatible(root, "fsl,P5020DS-hv")) {
- ppc_md.init_IRQ = ehv_pic_init;
- ppc_md.get_irq = ehv_pic_get_irq;
- ppc_md.restart = fsl_hv_restart;
- ppc_md.power_off = fsl_hv_halt;
- ppc_md.halt = fsl_hv_halt;
-#ifdef CONFIG_SMP
- /*
- * Disable the timebase sync operations because we can't write
- * to the timebase registers under the hypervisor.
- */
- smp_85xx_ops.give_timebase = NULL;
- smp_85xx_ops.take_timebase = NULL;
-#endif
- return 1;
- }
-
- return 0;
-}
-
-define_machine(p5020_ds) {
- .name = "P5020 DS",
- .probe = p5020_ds_probe,
- .setup_arch = corenet_ds_setup_arch,
- .init_IRQ = corenet_ds_pic_init,
-#ifdef CONFIG_PCI
- .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
-#endif
- .get_irq = mpic_get_coreint_irq,
- .restart = fsl_rstcr_restart,
- .calibrate_decr = generic_calibrate_decr,
- .progress = udbg_progress,
-#ifdef CONFIG_PPC64
- .power_save = book3e_idle,
-#else
- .power_save = e500_idle,
-#endif
-};
-
-machine_arch_initcall(p5020_ds, corenet_ds_publish_devices);
-
-#ifdef CONFIG_SWIOTLB
-machine_arch_initcall(p5020_ds, swiotlb_setup_bus_notifier);
-#endif
diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c
deleted file mode 100644
index f70e74c..0000000
--- a/arch/powerpc/platforms/85xx/p5040_ds.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * P5040 DS Setup
- *
- * Copyright 2009-2010 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-
-#include <asm/machdep.h>
-#include <asm/udbg.h>
-#include <asm/mpic.h>
-
-#include <linux/of_fdt.h>
-
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pci.h>
-#include <asm/ehv_pic.h>
-
-#include "corenet_ds.h"
-
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init p5040_ds_probe(void)
-{
- unsigned long root = of_get_flat_dt_root();
-#ifdef CONFIG_SMP
- extern struct smp_ops_t smp_85xx_ops;
-#endif
-
- if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
- return 1;
-
- /* Check if we're running under the Freescale hypervisor */
- if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
- ppc_md.init_IRQ = ehv_pic_init;
- ppc_md.get_irq = ehv_pic_get_irq;
- ppc_md.restart = fsl_hv_restart;
- ppc_md.power_off = fsl_hv_halt;
- ppc_md.halt = fsl_hv_halt;
-#ifdef CONFIG_SMP
- /*
- * Disable the timebase sync operations because we can't write
- * to the timebase registers under the hypervisor.
- */
- smp_85xx_ops.give_timebase = NULL;
- smp_85xx_ops.take_timebase = NULL;
-#endif
- return 1;
- }
-
- return 0;
-}
-
-define_machine(p5040_ds) {
- .name = "P5040 DS",
- .probe = p5040_ds_probe,
- .setup_arch = corenet_ds_setup_arch,
- .init_IRQ = corenet_ds_pic_init,
-#ifdef CONFIG_PCI
- .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
-#endif
- .get_irq = mpic_get_coreint_irq,
- .restart = fsl_rstcr_restart,
- .calibrate_decr = generic_calibrate_decr,
- .progress = udbg_progress,
-#ifdef CONFIG_PPC64
- .power_save = book3e_idle,
-#else
- .power_save = e500_idle,
-#endif
-};
-
-machine_arch_initcall(p5040_ds, corenet_ds_publish_devices);
-
-#ifdef CONFIG_SWIOTLB
-machine_arch_initcall(p5040_ds, swiotlb_setup_bus_notifier);
-#endif
diff --git a/arch/powerpc/platforms/85xx/t4240_qds.c b/arch/powerpc/platforms/85xx/t4240_qds.c
deleted file mode 100644
index 91ead6b..0000000
--- a/arch/powerpc/platforms/85xx/t4240_qds.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * T4240 QDS Setup
- *
- * Maintained by Kumar Gala (see MAINTAINERS for contact information)
- *
- * Copyright 2012 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/phy.h>
-
-#include <asm/time.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <mm/mmu_decl.h>
-#include <asm/prom.h>
-#include <asm/udbg.h>
-#include <asm/mpic.h>
-
-#include <linux/of_platform.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pci.h>
-#include <asm/ehv_pic.h>
-
-#include "corenet_ds.h"
-
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init t4240_qds_probe(void)
-{
- unsigned long root = of_get_flat_dt_root();
-#ifdef CONFIG_SMP
- extern struct smp_ops_t smp_85xx_ops;
-#endif
-
- if (of_flat_dt_is_compatible(root, "fsl,T4240QDS"))
- return 1;
-
- /* Check if we're running under the Freescale hypervisor */
- if (of_flat_dt_is_compatible(root, "fsl,T4240QDS-hv")) {
- ppc_md.init_IRQ = ehv_pic_init;
- ppc_md.get_irq = ehv_pic_get_irq;
- ppc_md.restart = fsl_hv_restart;
- ppc_md.power_off = fsl_hv_halt;
- ppc_md.halt = fsl_hv_halt;
-#ifdef CONFIG_SMP
- /*
- * Disable the timebase sync operations because we can't write
- * to the timebase registers under the hypervisor.
- */
- smp_85xx_ops.give_timebase = NULL;
- smp_85xx_ops.take_timebase = NULL;
-#endif
- return 1;
- }
-
- return 0;
-}
-
-define_machine(t4240_qds) {
- .name = "T4240 QDS",
- .probe = t4240_qds_probe,
- .setup_arch = corenet_ds_setup_arch,
- .init_IRQ = corenet_ds_pic_init,
-#ifdef CONFIG_PCI
- .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
-#endif
- .get_irq = mpic_get_coreint_irq,
- .restart = fsl_rstcr_restart,
- .calibrate_decr = generic_calibrate_decr,
- .progress = udbg_progress,
-#ifdef CONFIG_PPC64
- .power_save = book3e_idle,
-#else
- .power_save = e500_idle,
-#endif
-};
-
-machine_arch_initcall(t4240_qds, corenet_ds_publish_devices);
-
-#ifdef CONFIG_SWIOTLB
-machine_arch_initcall(t4240_qds, swiotlb_setup_bus_notifier);
-#endif
--
1.8.3.1
^ permalink raw reply related
* [PATCH 0/2] powerpc/85xx: introduce cornet_generic machine
From: Kevin Hao @ 2013-09-12 7:13 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc
This patch series introduces a common machine to support p2041rdb, p3041ds,
p4080ds, p5020ds, p5040ds, t4240qds and b4qds to avoid the code duplication.
Boot test on p5020ds and p4080ds.
Kevin Hao (2):
powerpc/85xx: introduce cornet_generic machine
powerpc/85xx: remove the unneeded corenet_ds.h
arch/powerpc/platforms/85xx/Kconfig | 10 ++++
arch/powerpc/platforms/85xx/Makefile | 8 +--
arch/powerpc/platforms/85xx/b4_qds.c | 97 --------------------------------
arch/powerpc/platforms/85xx/corenet_ds.c | 86 ++++++++++++++++++++++++++++
arch/powerpc/platforms/85xx/corenet_ds.h | 19 -------
arch/powerpc/platforms/85xx/p2041_rdb.c | 87 ----------------------------
arch/powerpc/platforms/85xx/p3041_ds.c | 89 -----------------------------
arch/powerpc/platforms/85xx/p4080_ds.c | 87 ----------------------------
arch/powerpc/platforms/85xx/p5020_ds.c | 93 ------------------------------
arch/powerpc/platforms/85xx/p5040_ds.c | 84 ---------------------------
arch/powerpc/platforms/85xx/t4240_qds.c | 93 ------------------------------
11 files changed, 97 insertions(+), 656 deletions(-)
delete mode 100644 arch/powerpc/platforms/85xx/b4_qds.c
delete mode 100644 arch/powerpc/platforms/85xx/corenet_ds.h
delete mode 100644 arch/powerpc/platforms/85xx/p2041_rdb.c
delete mode 100644 arch/powerpc/platforms/85xx/p3041_ds.c
delete mode 100644 arch/powerpc/platforms/85xx/p4080_ds.c
delete mode 100644 arch/powerpc/platforms/85xx/p5020_ds.c
delete mode 100644 arch/powerpc/platforms/85xx/p5040_ds.c
delete mode 100644 arch/powerpc/platforms/85xx/t4240_qds.c
--
1.8.3.1
^ permalink raw reply
* RE: [PATCH] powerpc/p1010rdb:remove interrupts of ethernet-phy in device tree
From: Liu Shengzhou-B36685 @ 2013-09-12 6:54 UTC (permalink / raw)
To: Kumar Gala, Zhao Qiang-B45475; +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <CE821871-A927-4A65-AA69-05F63AF2C6A1@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Wednesday, September 11, 2013 11:13 PM
> To: Zhao Qiang-B45475
> Cc: linuxppc-dev@lists.ozlabs.org; Liu Shengzhou-B36685
> Subject: Re: [PATCH] powerpc/p1010rdb:remove interrupts of ethernet-phy i=
n
> device tree
>=20
>=20
> On Sep 10, 2013, at 10:49 PM, Zhao Qiang wrote:
>=20
> > Since P1010RDB-PA and P1010RDB-PB boards use different external PHY
> > interrupt signals.
> > And actually the PHY interrupt is not used effectively with
> > corresponding interrupt handler.
> > So we can remove the interrupts node without side-effect to comply
> > with both P1010RDB-PA and P1010RDB-PB.
> >
> > Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> > Signed-off-by: Zhao Qiang <B45475@freescale.com>
> > ---
> > arch/powerpc/boot/dts/p1010rdb.dtsi | 3 ---
> > 1 file changed, 3 deletions(-)
> >
>=20
> NAK. The device tree should represent the HW not what drivers decide to =
do with
> it.
>=20
> If different board revs have different interrupt signals than create dts'=
s to
> handle the 2 board revs.
>=20
> - k
>=20
You mean we need to create p1010rdb-pa.dtsi and p1010rdb-pb.dtsi replacing =
current p1010rdb.dtsi just because of the unused phy interrupt?
and phy interrupt is not present in those dts of P3/P4/P5 platforms.
Actually currently many hardware are not present in dts, such as a lot of i=
2c devices, temperature monitor, etc.
-Shengzhou
^ permalink raw reply
* [PATCH v2] pstore: Adjust buffer size for compression for smaller registered buffers
From: Aruna Balakrishnaiah @ 2013-09-12 6:50 UTC (permalink / raw)
To: linuxppc-dev, tony.luck, seiji.aguchi, linux-kernel, keescook
Cc: jkenisto, mahesh, ccross, cbouatmailru
When backends (ex: efivars) have smaller registered buffers, the big_oops_buf
is quite too big for them as number of repeated occurences in the text captured
will be less. Patch takes care of adjusting the buffer size based on the
registered buffer size. cmpr values has been arrived after doing experiments with
plain text for buffers of size 1k - 4k (Smaller the buffer size repeated occurence
will be less) and with sample crash log for buffers ranging from 4k - 10k.
Reported-by: Seiji Aguchi <seiji.aguchi@hds.com>
Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com>
---
Changes from v1:
Retain the cmpr = 45 for buffers ranging of size 4k - 10k. 45 seems to work.
I added an additional headroom of 3%. Revert it back to 45.
fs/pstore/platform.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/fs/pstore/platform.c b/fs/pstore/platform.c
index 4ffb7ab..57b4219 100644
--- a/fs/pstore/platform.c
+++ b/fs/pstore/platform.c
@@ -195,8 +195,29 @@ error:
static void allocate_buf_for_compression(void)
{
size_t size;
+ size_t cmpr;
+
+ switch (psinfo->bufsize) {
+ /* buffer range for efivars */
+ case 1000 ... 2000:
+ cmpr = 56;
+ break;
+ case 2001 ... 3000:
+ cmpr = 54;
+ break;
+ case 3001 ... 3999:
+ cmpr = 52;
+ break;
+ /* buffer range for nvram, erst */
+ case 4000 ... 10000:
+ cmpr = 45;
+ break;
+ default:
+ cmpr = 60;
+ break;
+ }
- big_oops_buf_sz = (psinfo->bufsize * 100) / 45;
+ big_oops_buf_sz = (psinfo->bufsize * 100) / cmpr;
big_oops_buf = kmalloc(big_oops_buf_sz, GFP_KERNEL);
if (big_oops_buf) {
size = max(zlib_deflate_workspacesize(WINDOW_BITS, MEM_LEVEL),
^ permalink raw reply related
* Re: [PATCH] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB
From: leroy christophe @ 2013-09-12 5:57 UTC (permalink / raw)
To: Scott Wood; +Cc: Paul Mackerras, linuxppc-dev, linux-kernel
In-Reply-To: <1378944911.4066.12.camel@pasglop>
Le 12/09/2013 02:15, Benjamin Herrenschmidt a écrit :
> On Wed, 2013-09-11 at 17:36 -0500, Scott Wood wrote:
>> I wonder why we don't start from entry 31 so we can actually make use of
>> that autodecrement. What will happen when we load the first normal TLB
>> entry later on? I don't see any setting of SPRN_MD_CTR after this code,
>> so won't it overwrite entry 30 (the middle 8M) in the CONFIG_PIN_TLB
>> case?
>>
>> Ben, would patches like this be considered bugfixes as far as merging
>> goes, or would they be for next given that it's something that's never
>> really worked right and hasn't been touched in years?
> Since they don't affect anything outside of 8xx, I'm happy to take them
> until around -rc2 or 3. But it's your call really.
>
>
Scott, you're right, I didn't see that other consequence.
I'll come with a more complete patch this afternoon.
Thanks
^ permalink raw reply
* RE: [PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle
From: Wang Dongsheng-B40534 @ 2013-09-12 3:48 UTC (permalink / raw)
To: Wood Scott-B07421; +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1378940642.12204.427.camel@snotra.buserror.net>
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^ permalink raw reply
* Re: [PATCH] ppc: bpf_jit: support MOD operation
From: Vladimir Murzin @ 2013-09-12 2:56 UTC (permalink / raw)
To: Matt Evans; +Cc: dborkman, linuxppc-dev, davem, paulus
In-Reply-To: <C1FCF580-0B28-43FA-913B-9790BB76AAB7@ozlabs.org>
On Thu, Sep 12, 2013 at 02:18:37AM +0100, Matt Evans wrote:
> Hi Ben, Vladimir,
>
>
> *dusts off very thick PPC cobwebs* Sorry for the delay as I'm travelling, didn't get to this until now.
>
> On 02/09/2013, at 9:45 PM, Benjamin Herrenschmidt wrote:
>
> > On Mon, 2013-09-02 at 19:48 +0200, Vladimir Murzin wrote:
> >> Ping
> >>
> >> On Wed, Aug 28, 2013 at 02:49:52AM +0400, Vladimir Murzin wrote:
> >>> commit b6069a9570 (filter: add MOD operation) added generic
> >>> support for modulus operation in BPF.
> >>>
> > Sorry, nobody got a chance to review that yet. Unfortunately Matt
> > doesn't work for us anymore and none of us has experience with the
> > BPF code, so somebody (possibly me) will need to spend a bit of time
> > figuring it out before verifying that is correct.
> >
> > Do you have a test case/suite by any chance ?
> >
> > Ben.
> >
> >>> This patch brings JIT support for PPC64
> >>>
> >>> Signed-off-by: Vladimir Murzin <murzin.v@gmail.com>
> >>> ---
> >>> arch/powerpc/net/bpf_jit_comp.c | 22 ++++++++++++++++++++++
> >>> 1 file changed, 22 insertions(+)
> >>>
> >>> diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
> >>> index bf56e33..96f24dc 100644
> >>> --- a/arch/powerpc/net/bpf_jit_comp.c
> >>> +++ b/arch/powerpc/net/bpf_jit_comp.c
> >>> @@ -193,6 +193,28 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
> >>> PPC_MUL(r_A, r_A, r_scratch1);
> >>> }
> >>> break;
> >>> + case BPF_S_ALU_MOD_X: /* A %= X; */
> >>> + ctx->seen |= SEEN_XREG;
> >>> + PPC_CMPWI(r_X, 0);
> >>> + if (ctx->pc_ret0 != -1) {
> >>> + PPC_BCC(COND_EQ, addrs[ctx->pc_ret0]);
> >>> + } else {
> >>> + PPC_BCC_SHORT(COND_NE, (ctx->idx*4)+12);
> >>> + PPC_LI(r_ret, 0);
> >>> + PPC_JMP(exit_addr);
> >>> + }
> >>> + PPC_DIVWU(r_scratch1, r_A, r_X);
> >>> + PPC_MUL(r_scratch1, r_X, r_scratch1);
> >>> + PPC_SUB(r_A, r_A, r_scratch1);
> >>> + break;
>
> Without having compiled & tested this, it looks fine to me (especially with the corrected DIVWU opcode in the other patch, oops...).
>
> >>> + case BPF_S_ALU_MOD_K: /* A %= K; */
> >>> +#define r_scratch2 (r_scratch1 + 1)
> >>> + PPC_LI32(r_scratch2, K);
> >>> + PPC_DIVWU(r_scratch1, r_A, r_scratch2);
> >>> + PPC_MUL(r_scratch1, r_scratch2, r_scratch1);
> >>> + PPC_SUB(r_A, r_A, r_scratch1);
> >>> +#undef r_scratch2
> >>> + break;
>
> If you need another scratch register, it should really be defined in bpf_jit.h instead.
>
> Once you define r_scratch2 in there,
>
> Acked-by: Matt Evans <matt@ozlabs.org>
>
>
> Thanks!
>
>
> Matt
>
Thanks!
Vladimir
>
>
>
> >>> case BPF_S_ALU_DIV_X: /* A /= X; */
> >>> ctx->seen |= SEEN_XREG;
> >>> PPC_CMPWI(r_X, 0);
> >>> --
> >>> 1.8.1.5
> >>>
> >
>
^ permalink raw reply
* Re: [PATCH] powerpc: net: filter: fix DIVWU instruction opcode
From: Vladimir Murzin @ 2013-09-12 2:52 UTC (permalink / raw)
To: Matt Evans
Cc: Michael Neuling, linuxppc-dev@lists.ozlabs.org, paulus@samba.org
In-Reply-To: <79BD1567-A588-4977-BF11-C03045B55884@ozlabs.org>
On Thu, Sep 12, 2013 at 10:28:03AM +0930, Matt Evans wrote:
> On 12 Sep 2013, at 10:02, Michael Neuling <mikey@neuling.org> wrote:
>
> > Vladimir Murzin <murzin.v@gmail.com> wrote:
> >
> >> Currently DIVWU stands for *signed* divw opcode:
> >>
> >> 7d 2a 4b 96 divwu r9,r10,r9
> >> 7d 2a 4b d6 divw r9,r10,r9
> >>
> >> Use the *unsigned* divw opcode for DIVWU.
> >
> > This looks like it's in only used in the BPF JIT code.
> >
> > Matt, any chance you an ACK/NACK this?
>
> Sure, that looks sensible, thanks Vladimir.
>
> Acked-by: Matt Evans <matt@ozlabs.org>
>
Thanks!
Vladimir
> >
> > Mikey
> >
> >>
> >> Signed-off-by: Vladimir Murzin <murzin.v@gmail.com>
> >> ---
> >> arch/powerpc/include/asm/ppc-opcode.h | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
> >> index d7fe9f5..c91842c 100644
> >> --- a/arch/powerpc/include/asm/ppc-opcode.h
> >> +++ b/arch/powerpc/include/asm/ppc-opcode.h
> >> @@ -218,7 +218,7 @@
> >> #define PPC_INST_MULLW 0x7c0001d6
> >> #define PPC_INST_MULHWU 0x7c000016
> >> #define PPC_INST_MULLI 0x1c000000
> >> -#define PPC_INST_DIVWU 0x7c0003d6
> >> +#define PPC_INST_DIVWU 0x7c000396
> >> #define PPC_INST_RLWINM 0x54000000
> >> #define PPC_INST_RLDICR 0x78000004
> >> #define PPC_INST_SLW 0x7c000030
> >> --
> >> 1.7.10.4
> >>
^ permalink raw reply
* RE: [PATCH v3 2/4] powerpc/85xx: add hardware automatically enter altivec idle state
From: Wang Dongsheng-B40534 @ 2013-09-12 2:27 UTC (permalink / raw)
To: Wood Scott-B07421; +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1378939377.12204.412.camel@snotra.buserror.net>
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