* [PATCH 1/2] powerpc/p1010rdb:add P1010RDB-PB platform support
From: Zhao Qiang @ 2013-10-14 6:46 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Zhao Qiang, R61911
The P1010RDB-PB is similar to P1010RDB(P1010RDB-PA).
So, P1010RDB-PB use the same platform file as P1010RDB.
Then Add support for P1010RDB-PB platform.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
---
arch/powerpc/platforms/85xx/p1010rdb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
index 0252961..d6a3dd3 100644
--- a/arch/powerpc/platforms/85xx/p1010rdb.c
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -66,6 +66,8 @@ static int __init p1010_rdb_probe(void)
if (of_flat_dt_is_compatible(root, "fsl,P1010RDB"))
return 1;
+ if (of_flat_dt_is_compatible(root, "fsl,P1010RDB-PB"))
+ return 1;
return 0;
}
--
1.8.0
^ permalink raw reply related
* Re: [PATCH] powerpc, perf: Configure BHRB filter before enabling PMU interrupts
From: Michael Ellerman @ 2013-10-14 6:19 UTC (permalink / raw)
To: Anshuman Khandual; +Cc: linuxppc-dev, mikey
In-Reply-To: <52577F5C.6000704@linux.vnet.ibm.com>
On Fri, Oct 11, 2013 at 10:02:28AM +0530, Anshuman Khandual wrote:
> On 10/11/2013 07:41 AM, Michael Ellerman wrote:
> > On Thu, Oct 10, 2013 at 02:20:22PM +0530, Anshuman Khandual wrote:
> >
> >> Even I think this is not right. Instruction sampling should have been
> >> enabled before we enable PMU interrupts. Else there is a small window
> >> of time where we could have the PMU enabled with events (which requires
> >> sampling) without the sampling itself being enabled in MMCRA.
> >
> > Yes I agree. That's a separate bug, which we'll need to test on all the book3s
> > platforms we have perf support for.
>
> Okay, I guess any platform which supports sampling will definitely want to have
> it enabled before we can set the events to count on PMU. Can you think of any
> problem which can arise if we move it before the enabling the PMU back ? Else
> we can fix this easily.
In theory it should be a trivial change. But hardware can behave in
strange ways, it's possible on some old chip we need to do it the
current way for some reason.
So although I don't think it will be a problem, it could be, so we
will need to test it thoroughly.
cheers
^ permalink raw reply
* Re: "powerpc/83xx: gianfar_ptp: select 1588 clock source through dts file" was added twice
From: Aida Mynzhasova @ 2013-10-14 5:52 UTC (permalink / raw)
To: David Miller; +Cc: devicetree, linuxppc-dev, greg
In-Reply-To: <20131012.171110.246440214474931440.davem@davemloft.net>
On 13.10.2013 01:11, David Miller wrote:
> From: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
> Date: Sat, 12 Oct 2013 18:54:42 +0400
>
>> Hi,
>>
>> recently I looked through commits in kernel/git/torvalds/linux.git and
>> I noticed that my patch (old and new version) was added twice (by
>> David S. Miller):
>>
>> e58f6f4fb4eada7867014bfaec898f03afbce5c2
>> 894116bd0e9b7749a0c4b6c62dec13c2a0ccef68
>>
>> I think this is not good, and only
>> e58f6f4fb4eada7867014bfaec898f03afbce5c2 should be added.
>
> Read the code history properly.
>
> First 894116bd0e9b7749a0c4b6c62dec13c2a0ccef68 got applied, as you say
> accidently. Then I reverted it, see commit
> 3f3f0960aff951c5df6e42ce292d1593a2520646.
>
> Then I applied the correct version which is commit
> e58f6f4fb4eada7867014bfaec898f03afbce5c2.
>
> I didn't respond at all the first time you pointed this out hoping
> you would figure it out on your own.
>
Oh...right...
Please accept my apology.
^ permalink raw reply
* [PATCH] arch/powerpc/platforms/83xx: Remove obsolete cleanup for clientdata
From: Wolfram Sang @ 2013-10-13 16:05 UTC (permalink / raw)
To: linux-i2c; +Cc: linuxppc-dev, Paul Mackerras, Wolfram Sang
A few new i2c-drivers came into the kernel which clear the clientdata-pointer
on exit or error. This is obsolete meanwhile, the core will do it.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
---
arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
index 7bc3158..fd71cfd 100644
--- a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
+++ b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
@@ -204,7 +204,6 @@ static int mcu_remove(struct i2c_client *client)
ret = mcu_gpiochip_remove(mcu);
if (ret)
return ret;
- i2c_set_clientdata(client, NULL);
kfree(mcu);
return 0;
}
--
1.8.4.rc3
^ permalink raw reply related
* Re: "powerpc/83xx: gianfar_ptp: select 1588 clock source through dts file" was added twice
From: David Miller @ 2013-10-12 21:11 UTC (permalink / raw)
To: aida.mynzhasova; +Cc: devicetree, linuxppc-dev, greg
In-Reply-To: <525962B2.8010100@skitlab.ru>
From: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
Date: Sat, 12 Oct 2013 18:54:42 +0400
> Hi,
>
> recently I looked through commits in kernel/git/torvalds/linux.git and
> I noticed that my patch (old and new version) was added twice (by
> David S. Miller):
>
> e58f6f4fb4eada7867014bfaec898f03afbce5c2
> 894116bd0e9b7749a0c4b6c62dec13c2a0ccef68
>
> I think this is not good, and only
> e58f6f4fb4eada7867014bfaec898f03afbce5c2 should be added.
Read the code history properly.
First 894116bd0e9b7749a0c4b6c62dec13c2a0ccef68 got applied, as you say
accidently. Then I reverted it, see commit
3f3f0960aff951c5df6e42ce292d1593a2520646.
Then I applied the correct version which is commit
e58f6f4fb4eada7867014bfaec898f03afbce5c2.
I didn't respond at all the first time you pointed this out hoping
you would figure it out on your own.
^ permalink raw reply
* [PATCH 3/3] Add maintainers entry for the Freescale PAMU driver.
From: Varun Sethi @ 2013-10-12 20:32 UTC (permalink / raw)
To: joro, iommu, linuxppc-dev, linux-kernel, stuart.yoder, scottwood,
alex.williamson, r65777
Cc: Varun Sethi
In-Reply-To: <1381609954-15283-1-git-send-email-Varun.Sethi@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8a0cbf3..5b6ea5c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3511,6 +3511,13 @@ S: Maintained
F: drivers/net/ethernet/freescale/fs_enet/
F: include/linux/fs_enet_pd.h
+FREESCALE PAMU DRIVER
+M: Varun Sethi <varun.sethi@freescale.com>
+L: linuxppc-dev@lists.ozlabs.org
+L: iommu@lists.linux-foundation.org
+S: Maintained
+F: drivers/iommu/fsl_pamu*
+
FREESCALE QUICC ENGINE LIBRARY
L: linuxppc-dev@lists.ozlabs.org
S: Orphan
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/3] iommu/fsl: Enable default DMA window for PCIe devices once detached
From: Varun Sethi @ 2013-10-12 20:32 UTC (permalink / raw)
To: joro, iommu, linuxppc-dev, linux-kernel, stuart.yoder, scottwood,
alex.williamson, r65777
Cc: Varun Sethi
In-Reply-To: <1381609954-15283-1-git-send-email-Varun.Sethi@freescale.com>
from domain.
Once the PCIe device assigned to a guest VM (via VFIO) gets detached from the iommu domain
(when guest terminates), its PAMU table entry is disabled. So, this would prevent the device
from being used once it's assigned back to the host.
This patch allows for creation of a default DMA window corresponding to the device
and subsequently enabling the PAMU table entry. Before we enable the entry, we ensure that
the device's bus master capability is disabled (device quiesced).
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
---
drivers/iommu/fsl_pamu.c | 43 +++++++++++++++++++++++++++++++--------
drivers/iommu/fsl_pamu.h | 1 +
drivers/iommu/fsl_pamu_domain.c | 35 +++++++++++++++++++++++++++++++
3 files changed, 70 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/fsl_pamu.c b/drivers/iommu/fsl_pamu.c
index cba0498..fb4a031 100644
--- a/drivers/iommu/fsl_pamu.c
+++ b/drivers/iommu/fsl_pamu.c
@@ -225,6 +225,21 @@ static struct paace *pamu_get_spaace(struct paace *paace, u32 wnum)
return spaace;
}
+/*
+ * Defaul PPAACE settings for an LIODN.
+ */
+static void setup_default_ppaace(struct paace *ppaace)
+{
+ pamu_init_ppaace(ppaace);
+ /* window size is 2^(WSE+1) bytes */
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE, 35);
+ ppaace->wbah = 0;
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL, 0);
+ set_bf(ppaace->impl_attr, PAACE_IA_ATM,
+ PAACE_ATM_NO_XLATE);
+ set_bf(ppaace->addr_bitfields, PAACE_AF_AP,
+ PAACE_AP_PERMS_ALL);
+}
/**
* pamu_get_fspi_and_allocate() - Allocates fspi index and reserves subwindows
* required for primary PAACE in the secondary
@@ -253,6 +268,24 @@ static unsigned long pamu_get_fspi_and_allocate(u32 subwin_cnt)
return (spaace_addr - (unsigned long)spaact) / (sizeof(struct paace));
}
+/* Reset the PAACE entry to the default state */
+void enable_default_dma_window(int liodn)
+{
+ struct paace *ppaace;
+
+ ppaace = pamu_get_ppaace(liodn);
+ if (!ppaace) {
+ pr_debug("Invalid liodn entry\n");
+ return;
+ }
+
+ memset(ppaace, 0, sizeof(struct paace));
+
+ setup_default_ppaace(ppaace);
+ mb();
+ pamu_enable_liodn(liodn);
+}
+
/* Release the subwindows reserved for a particular LIODN */
void pamu_free_subwins(int liodn)
{
@@ -752,15 +785,7 @@ static void __init setup_liodns(void)
continue;
}
ppaace = pamu_get_ppaace(liodn);
- pamu_init_ppaace(ppaace);
- /* window size is 2^(WSE+1) bytes */
- set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE, 35);
- ppaace->wbah = 0;
- set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL, 0);
- set_bf(ppaace->impl_attr, PAACE_IA_ATM,
- PAACE_ATM_NO_XLATE);
- set_bf(ppaace->addr_bitfields, PAACE_AF_AP,
- PAACE_AP_PERMS_ALL);
+ setup_default_ppaace(ppaace);
if (of_device_is_compatible(node, "fsl,qman-portal"))
setup_qbman_paace(ppaace, QMAN_PORTAL_PAACE);
if (of_device_is_compatible(node, "fsl,qman"))
diff --git a/drivers/iommu/fsl_pamu.h b/drivers/iommu/fsl_pamu.h
index 8fc1a12..0edcbbbb 100644
--- a/drivers/iommu/fsl_pamu.h
+++ b/drivers/iommu/fsl_pamu.h
@@ -406,5 +406,6 @@ void get_ome_index(u32 *omi_index, struct device *dev);
int pamu_update_paace_stash(int liodn, u32 subwin, u32 value);
int pamu_disable_spaace(int liodn, u32 subwin);
u32 pamu_get_max_subwin_cnt(void);
+void enable_default_dma_window(int liodn);
#endif /* __FSL_PAMU_H */
diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c
index e02e1de..553ef3c 100644
--- a/drivers/iommu/fsl_pamu_domain.c
+++ b/drivers/iommu/fsl_pamu_domain.c
@@ -340,6 +340,40 @@ static inline struct device_domain_info *find_domain(struct device *dev)
return dev->archdata.iommu_domain;
}
+/* Disable device DMA capability and enable default DMA window */
+static void disable_device_dma(struct device_domain_info *info)
+{
+ struct device_domain_info *tmp;
+ int enable_dma_window = 1;
+
+#ifdef CONFIG_PCI
+ if (info->dev->bus == &pci_bus_type) {
+ struct pci_dev *pdev = NULL;
+ pdev = to_pci_dev(info->dev);
+ if (pci_is_enabled(pdev))
+ pci_disable_device(pdev);
+ }
+#endif
+ /*
+ * Sanity check, to ensure that this is not a
+ * shared LIODN. In case of a PCIe controller
+ * it's possible that all PCIe devices share
+ * the same LIODN. We can't enable the default
+ * DMA window till all the devices have been
+ * quiesced (for PCIe devices, we explicitly
+ * disable the bus master capability).
+ */
+ list_for_each_entry(tmp, &info->domain->devices, link) {
+ if (info->dev->iommu_group == tmp->dev->iommu_group) {
+ enable_dma_window = 0;
+ break;
+ }
+ }
+
+ if (enable_dma_window)
+ enable_default_dma_window(info->liodn);
+}
+
static void remove_device_ref(struct device_domain_info *info, u32 win_cnt)
{
unsigned long flags;
@@ -351,6 +385,7 @@ static void remove_device_ref(struct device_domain_info *info, u32 win_cnt)
pamu_disable_liodn(info->liodn);
spin_unlock_irqrestore(&iommu_lock, flags);
spin_lock_irqsave(&device_domain_lock, flags);
+ disable_device_dma(info);
info->dev->archdata.iommu_domain = NULL;
kmem_cache_free(iommu_devinfo_cache, info);
spin_unlock_irqrestore(&device_domain_lock, flags);
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/3] iommu/fsl: Factor out PCI specific code.
From: Varun Sethi @ 2013-10-12 20:32 UTC (permalink / raw)
To: joro, iommu, linuxppc-dev, linux-kernel, stuart.yoder, scottwood,
alex.williamson, r65777
Cc: Varun Sethi
In-Reply-To: <1381609954-15283-1-git-send-email-Varun.Sethi@freescale.com>
Factor out PCI specific code in the PAMU driver.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
---
drivers/iommu/fsl_pamu_domain.c | 81 +++++++++++++++++++--------------------
1 file changed, 40 insertions(+), 41 deletions(-)
diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c
index c857c30..e02e1de 100644
--- a/drivers/iommu/fsl_pamu_domain.c
+++ b/drivers/iommu/fsl_pamu_domain.c
@@ -677,13 +677,9 @@ static int handle_attach_device(struct fsl_dma_domain *dma_domain,
return ret;
}
-static int fsl_pamu_attach_device(struct iommu_domain *domain,
- struct device *dev)
+static void check_for_pci_dma_device(struct device **dev)
{
- struct fsl_dma_domain *dma_domain = domain->priv;
- const u32 *liodn;
- u32 liodn_cnt;
- int len, ret = 0;
+#ifdef CONFIG_PCI
struct pci_dev *pdev = NULL;
struct pci_controller *pci_ctl;
@@ -691,25 +687,38 @@ static int fsl_pamu_attach_device(struct iommu_domain *domain,
* Use LIODN of the PCI controller while attaching a
* PCI device.
*/
- if (dev->bus == &pci_bus_type) {
- pdev = to_pci_dev(dev);
+ if ((*dev)->bus == &pci_bus_type) {
+ pdev = to_pci_dev(*dev);
pci_ctl = pci_bus_to_host(pdev->bus);
/*
* make dev point to pci controller device
* so we can get the LIODN programmed by
* u-boot.
*/
- dev = pci_ctl->parent;
+ *dev = pci_ctl->parent;
}
+#endif
+}
- liodn = of_get_property(dev->of_node, "fsl,liodn", &len);
+static int fsl_pamu_attach_device(struct iommu_domain *domain,
+ struct device *dev)
+{
+ struct fsl_dma_domain *dma_domain = domain->priv;
+ struct device *dma_dev = dev;
+ const u32 *liodn;
+ u32 liodn_cnt;
+ int len, ret = 0;
+
+ check_for_pci_dma_device(&dma_dev);
+
+ liodn = of_get_property(dma_dev->of_node, "fsl,liodn", &len);
if (liodn) {
liodn_cnt = len / sizeof(u32);
ret = handle_attach_device(dma_domain, dev,
liodn, liodn_cnt);
} else {
pr_debug("missing fsl,liodn property at %s\n",
- dev->of_node->full_name);
+ dma_dev->of_node->full_name);
ret = -EINVAL;
}
@@ -720,32 +729,18 @@ static void fsl_pamu_detach_device(struct iommu_domain *domain,
struct device *dev)
{
struct fsl_dma_domain *dma_domain = domain->priv;
+ struct device *dma_dev = dev;
const u32 *prop;
int len;
- struct pci_dev *pdev = NULL;
- struct pci_controller *pci_ctl;
- /*
- * Use LIODN of the PCI controller while detaching a
- * PCI device.
- */
- if (dev->bus == &pci_bus_type) {
- pdev = to_pci_dev(dev);
- pci_ctl = pci_bus_to_host(pdev->bus);
- /*
- * make dev point to pci controller device
- * so we can get the LIODN programmed by
- * u-boot.
- */
- dev = pci_ctl->parent;
- }
+ check_for_pci_dma_device(&dma_dev);
- prop = of_get_property(dev->of_node, "fsl,liodn", &len);
+ prop = of_get_property(dma_dev->of_node, "fsl,liodn", &len);
if (prop)
detach_device(dev, dma_domain);
else
pr_debug("missing fsl,liodn property at %s\n",
- dev->of_node->full_name);
+ dma_dev->of_node->full_name);
}
static int configure_domain_geometry(struct iommu_domain *domain, void *data)
@@ -905,6 +900,7 @@ static struct iommu_group *get_device_iommu_group(struct device *dev)
return group;
}
+#ifdef CONFIG_PCI
static bool check_pci_ctl_endpt_part(struct pci_controller *pci_ctl)
{
u32 version;
@@ -945,13 +941,18 @@ static struct iommu_group *get_shared_pci_device_group(struct pci_dev *pdev)
return NULL;
}
-static struct iommu_group *get_pci_device_group(struct pci_dev *pdev)
+static struct iommu_group *get_pci_device_group(struct device *dev)
{
struct pci_controller *pci_ctl;
bool pci_endpt_partioning;
struct iommu_group *group = NULL;
- struct pci_dev *bridge, *dma_pdev = NULL;
+ struct pci_dev *bridge, *pdev;
+ struct pci_dev *dma_pdev = NULL;
+ pdev = to_pci_dev(dev);
+ /* Don't create device groups for virtual PCI bridges */
+ if (pdev->subordinate)
+ return NULL;
pci_ctl = pci_bus_to_host(pdev->bus);
pci_endpt_partioning = check_pci_ctl_endpt_part(pci_ctl);
/* We can partition PCIe devices so assign device group to the device */
@@ -1044,11 +1045,11 @@ root_bus:
return group;
}
+#endif
static int fsl_pamu_add_device(struct device *dev)
{
struct iommu_group *group = NULL;
- struct pci_dev *pdev;
const u32 *prop;
int ret, len;
@@ -1056,19 +1057,15 @@ static int fsl_pamu_add_device(struct device *dev)
* For platform devices we allocate a separate group for
* each of the devices.
*/
- if (dev->bus == &pci_bus_type) {
- pdev = to_pci_dev(dev);
- /* Don't create device groups for virtual PCI bridges */
- if (pdev->subordinate)
- return 0;
-
- group = get_pci_device_group(pdev);
-
- } else {
+ if (dev->bus == &platform_bus_type) {
prop = of_get_property(dev->of_node, "fsl,liodn", &len);
if (prop)
group = get_device_iommu_group(dev);
}
+#ifdef CONFIG_PCI
+ else
+ group = get_pci_device_group(dev);
+#endif
if (!group || IS_ERR(group))
return PTR_ERR(group);
@@ -1166,7 +1163,9 @@ int pamu_domain_init()
return ret;
bus_set_iommu(&platform_bus_type, &fsl_pamu_ops);
+#ifdef CONFIG_PCI
bus_set_iommu(&pci_bus_type, &fsl_pamu_ops);
+#endif
return ret;
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/3] iommu/fsl: PAMU driver fixes.
From: Varun Sethi @ 2013-10-12 20:32 UTC (permalink / raw)
To: joro, iommu, linuxppc-dev, linux-kernel, stuart.yoder, scottwood,
alex.williamson, r65777
Cc: Varun Sethi
The first patch fixes a build failure, when we try to build for a Freescale
platform without PCI support.
The second patch enables a default DMA window for the device, once it's
detached from a domain. In case of vfio, once device is detached from a
guest it can be again used by the host.
The last patch adds the maintainer entry for the Freescale PAMU driver.
Varun Sethi (3):
iommu/fsl: Factor out PCI specific code.
iommu/fsl: Enable default DMA window for PCIe devices once detached
Add maintainers entry for the Freescale PAMU driver.
MAINTAINERS | 7 +++
drivers/iommu/fsl_pamu.c | 43 ++++++++++++---
drivers/iommu/fsl_pamu.h | 1 +
drivers/iommu/fsl_pamu_domain.c | 116 +++++++++++++++++++++++++--------------
4 files changed, 117 insertions(+), 50 deletions(-)
--
1.7.9.5
^ permalink raw reply
* "powerpc/83xx: gianfar_ptp: select 1588 clock source through dts file" was added twice
From: Aida Mynzhasova @ 2013-10-12 14:54 UTC (permalink / raw)
To: linuxppc-dev; +Cc: devicetree, davem, Greg KH
Hi,
recently I looked through commits in kernel/git/torvalds/linux.git and I
noticed that my patch (old and new version) was added twice (by David S.
Miller):
e58f6f4fb4eada7867014bfaec898f03afbce5c2
894116bd0e9b7749a0c4b6c62dec13c2a0ccef68
I think this is not good, and only
e58f6f4fb4eada7867014bfaec898f03afbce5c2 should be added.
Thanks!
--
Regards,
Aida
^ permalink raw reply
* RE: [PATCH 1/2] iommu/fsl: Factor out PCI specific code.
From: Sethi Varun-B16395 @ 2013-10-12 7:20 UTC (permalink / raw)
To: joro@8bytes.org, iommu@lists.linux-foundation.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Yoder Stuart-B08248, alex.williamson@redhat.com
In-Reply-To: <1381343194-24059-1-git-send-email-Varun.Sethi@freescale.com>
Hi Joerg,
Please consider these patches for 3.12.
Regards
Varun
> -----Original Message-----
> From: Sethi Varun-B16395
> Sent: Wednesday, October 09, 2013 11:57 PM
> To: joro@8bytes.org; iommu@lists.linux-foundation.org; linuxppc-
> dev@lists.ozabs.org; linux-kernel@vger.kernel.org; Yoder Stuart-B08248;
> alex.williamson@redhat.com
> Cc: Sethi Varun-B16395
> Subject: [PATCH 1/2] iommu/fsl: Factor out PCI specific code.
>=20
> Factor out PCI specific code in the PAMU driver.
>=20
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> ---
> drivers/iommu/fsl_pamu_domain.c | 81 +++++++++++++++++++--------------
> ------
> 1 file changed, 40 insertions(+), 41 deletions(-)
>=20
> diff --git a/drivers/iommu/fsl_pamu_domain.c
> b/drivers/iommu/fsl_pamu_domain.c index c857c30..e02e1de 100644
> --- a/drivers/iommu/fsl_pamu_domain.c
> +++ b/drivers/iommu/fsl_pamu_domain.c
> @@ -677,13 +677,9 @@ static int handle_attach_device(struct
> fsl_dma_domain *dma_domain,
> return ret;
> }
>=20
> -static int fsl_pamu_attach_device(struct iommu_domain *domain,
> - struct device *dev)
> +static void check_for_pci_dma_device(struct device **dev)
> {
> - struct fsl_dma_domain *dma_domain =3D domain->priv;
> - const u32 *liodn;
> - u32 liodn_cnt;
> - int len, ret =3D 0;
> +#ifdef CONFIG_PCI
> struct pci_dev *pdev =3D NULL;
> struct pci_controller *pci_ctl;
>=20
> @@ -691,25 +687,38 @@ static int fsl_pamu_attach_device(struct
> iommu_domain *domain,
> * Use LIODN of the PCI controller while attaching a
> * PCI device.
> */
> - if (dev->bus =3D=3D &pci_bus_type) {
> - pdev =3D to_pci_dev(dev);
> + if ((*dev)->bus =3D=3D &pci_bus_type) {
> + pdev =3D to_pci_dev(*dev);
> pci_ctl =3D pci_bus_to_host(pdev->bus);
> /*
> * make dev point to pci controller device
> * so we can get the LIODN programmed by
> * u-boot.
> */
> - dev =3D pci_ctl->parent;
> + *dev =3D pci_ctl->parent;
> }
> +#endif
> +}
>=20
> - liodn =3D of_get_property(dev->of_node, "fsl,liodn", &len);
> +static int fsl_pamu_attach_device(struct iommu_domain *domain,
> + struct device *dev)
> +{
> + struct fsl_dma_domain *dma_domain =3D domain->priv;
> + struct device *dma_dev =3D dev;
> + const u32 *liodn;
> + u32 liodn_cnt;
> + int len, ret =3D 0;
> +
> + check_for_pci_dma_device(&dma_dev);
> +
> + liodn =3D of_get_property(dma_dev->of_node, "fsl,liodn", &len);
> if (liodn) {
> liodn_cnt =3D len / sizeof(u32);
> ret =3D handle_attach_device(dma_domain, dev,
> liodn, liodn_cnt);
> } else {
> pr_debug("missing fsl,liodn property at %s\n",
> - dev->of_node->full_name);
> + dma_dev->of_node->full_name);
> ret =3D -EINVAL;
> }
>=20
> @@ -720,32 +729,18 @@ static void fsl_pamu_detach_device(struct
> iommu_domain *domain,
> struct device *dev)
> {
> struct fsl_dma_domain *dma_domain =3D domain->priv;
> + struct device *dma_dev =3D dev;
> const u32 *prop;
> int len;
> - struct pci_dev *pdev =3D NULL;
> - struct pci_controller *pci_ctl;
>=20
> - /*
> - * Use LIODN of the PCI controller while detaching a
> - * PCI device.
> - */
> - if (dev->bus =3D=3D &pci_bus_type) {
> - pdev =3D to_pci_dev(dev);
> - pci_ctl =3D pci_bus_to_host(pdev->bus);
> - /*
> - * make dev point to pci controller device
> - * so we can get the LIODN programmed by
> - * u-boot.
> - */
> - dev =3D pci_ctl->parent;
> - }
> + check_for_pci_dma_device(&dma_dev);
>=20
> - prop =3D of_get_property(dev->of_node, "fsl,liodn", &len);
> + prop =3D of_get_property(dma_dev->of_node, "fsl,liodn", &len);
> if (prop)
> detach_device(dev, dma_domain);
> else
> pr_debug("missing fsl,liodn property at %s\n",
> - dev->of_node->full_name);
> + dma_dev->of_node->full_name);
> }
>=20
> static int configure_domain_geometry(struct iommu_domain *domain, void
> *data) @@ -905,6 +900,7 @@ static struct iommu_group
> *get_device_iommu_group(struct device *dev)
> return group;
> }
>=20
> +#ifdef CONFIG_PCI
> static bool check_pci_ctl_endpt_part(struct pci_controller *pci_ctl) {
> u32 version;
> @@ -945,13 +941,18 @@ static struct iommu_group
> *get_shared_pci_device_group(struct pci_dev *pdev)
> return NULL;
> }
>=20
> -static struct iommu_group *get_pci_device_group(struct pci_dev *pdev)
> +static struct iommu_group *get_pci_device_group(struct device *dev)
> {
> struct pci_controller *pci_ctl;
> bool pci_endpt_partioning;
> struct iommu_group *group =3D NULL;
> - struct pci_dev *bridge, *dma_pdev =3D NULL;
> + struct pci_dev *bridge, *pdev;
> + struct pci_dev *dma_pdev =3D NULL;
>=20
> + pdev =3D to_pci_dev(dev);
> + /* Don't create device groups for virtual PCI bridges */
> + if (pdev->subordinate)
> + return NULL;
> pci_ctl =3D pci_bus_to_host(pdev->bus);
> pci_endpt_partioning =3D check_pci_ctl_endpt_part(pci_ctl);
> /* We can partition PCIe devices so assign device group to the
> device */ @@ -1044,11 +1045,11 @@ root_bus:
>=20
> return group;
> }
> +#endif
>=20
> static int fsl_pamu_add_device(struct device *dev) {
> struct iommu_group *group =3D NULL;
> - struct pci_dev *pdev;
> const u32 *prop;
> int ret, len;
>=20
> @@ -1056,19 +1057,15 @@ static int fsl_pamu_add_device(struct device
> *dev)
> * For platform devices we allocate a separate group for
> * each of the devices.
> */
> - if (dev->bus =3D=3D &pci_bus_type) {
> - pdev =3D to_pci_dev(dev);
> - /* Don't create device groups for virtual PCI bridges */
> - if (pdev->subordinate)
> - return 0;
> -
> - group =3D get_pci_device_group(pdev);
> -
> - } else {
> + if (dev->bus =3D=3D &platform_bus_type) {
> prop =3D of_get_property(dev->of_node, "fsl,liodn", &len);
> if (prop)
> group =3D get_device_iommu_group(dev);
> }
> +#ifdef CONFIG_PCI
> + else
> + group =3D get_pci_device_group(dev);
> +#endif
>=20
> if (!group || IS_ERR(group))
> return PTR_ERR(group);
> @@ -1166,7 +1163,9 @@ int pamu_domain_init()
> return ret;
>=20
> bus_set_iommu(&platform_bus_type, &fsl_pamu_ops);
> +#ifdef CONFIG_PCI
> bus_set_iommu(&pci_bus_type, &fsl_pamu_ops);
> +#endif
>=20
> return ret;
> }
> --
> 1.7.9.5
^ permalink raw reply
* [PATCH] ppc-6xx: add missing iounmap() on error in hlwd_pic_init()
From: Wei Yongjun @ 2013-10-12 7:13 UTC (permalink / raw)
To: benh, paulus, grant.likely, rob.herring; +Cc: yongjun_wei, linuxppc-dev
From: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Add the missing iounmap() before return from hlwd_pic_init()
in the error handling case.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
---
arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
index 7cab21d..6c03034 100644
--- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
@@ -183,6 +183,7 @@ struct irq_domain *hlwd_pic_init(struct device_node *np)
&hlwd_irq_domain_ops, io_base);
if (!irq_domain) {
pr_err("failed to allocate irq_domain\n");
+ iounmap(io_base);
return NULL;
}
^ permalink raw reply related
* RE: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree
From: Tang Yuantian-B29983 @ 2013-10-12 3:40 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
Li Yang-Leo-R58472
In-Reply-To: <20131011092526.GE3910@e106331-lin.cambridge.arm.com>
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^ permalink raw reply
* RE: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree
From: Tang Yuantian-B29983 @ 2013-10-12 2:53 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1381518492.7979.537.camel@snotra.buserror.net>
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^ permalink raw reply
* RE: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree
From: Tang Yuantian-B29983 @ 2013-10-12 2:52 UTC (permalink / raw)
To: Wood Scott-B07421, Mark Rutland
Cc: devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
Li Yang-Leo-R58472
In-Reply-To: <1381518433.7979.536.camel@snotra.buserror.net>
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^ permalink raw reply
* [PATCH v3 3/3] powerpc/fsl-book3e-64: Use paca for hugetlb TLB1 entry selection
From: Scott Wood @ 2013-10-12 0:22 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Scott Wood, linuxppc-dev
In-Reply-To: <1381537359-22863-1-git-send-email-scottwood@freescale.com>
This keeps usage coordinated for hugetlb and indirect entries, which
should make entry selection more predictable and probably improve overall
performance when mixing the two.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v3: no changes
v2: new patch
---
arch/powerpc/mm/hugetlbpage-book3e.c | 51 +++++++++++++++++++++++++++++-------
1 file changed, 41 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/mm/hugetlbpage-book3e.c b/arch/powerpc/mm/hugetlbpage-book3e.c
index 3bc7006..ee57ac2 100644
--- a/arch/powerpc/mm/hugetlbpage-book3e.c
+++ b/arch/powerpc/mm/hugetlbpage-book3e.c
@@ -8,6 +8,44 @@
#include <linux/mm.h>
#include <linux/hugetlb.h>
+#ifdef CONFIG_PPC_FSL_BOOK3E
+#ifdef CONFIG_PPC64
+static inline int tlb1_next(void)
+{
+ struct paca_struct *paca = get_paca();
+ struct tlb_core_data *tcd;
+ int this, next;
+
+ tcd = paca->tcd_ptr;
+ this = tcd->esel_next;
+
+ next = this + 1;
+ if (next >= tcd->esel_max)
+ next = tcd->esel_first;
+
+ tcd->esel_next = next;
+ return this;
+}
+#else
+static inline int tlb1_next(void)
+{
+ int index, ncams;
+
+ ncams = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
+
+ index = __get_cpu_var(next_tlbcam_idx);
+
+ /* Just round-robin the entries and wrap when we hit the end */
+ if (unlikely(index == ncams - 1))
+ __get_cpu_var(next_tlbcam_idx) = tlbcam_index;
+ else
+ __get_cpu_var(next_tlbcam_idx)++;
+
+ return index;
+}
+#endif /* !PPC64 */
+#endif /* FSL */
+
static inline int mmu_get_tsize(int psize)
{
return mmu_psize_defs[psize].enc;
@@ -47,7 +85,7 @@ void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
struct mm_struct *mm;
#ifdef CONFIG_PPC_FSL_BOOK3E
- int index, ncams;
+ int index;
#endif
if (unlikely(is_kernel_addr(ea)))
@@ -77,18 +115,11 @@ void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
}
#ifdef CONFIG_PPC_FSL_BOOK3E
- ncams = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
-
/* We have to use the CAM(TLB1) on FSL parts for hugepages */
- index = __get_cpu_var(next_tlbcam_idx);
+ index = tlb1_next();
mtspr(SPRN_MAS0, MAS0_ESEL(index) | MAS0_TLBSEL(1));
-
- /* Just round-robin the entries and wrap when we hit the end */
- if (unlikely(index == ncams - 1))
- __get_cpu_var(next_tlbcam_idx) = tlbcam_index;
- else
- __get_cpu_var(next_tlbcam_idx)++;
#endif
+
mas1 = MAS1_VALID | MAS1_TID(mm->context.id) | MAS1_TSIZE(tsize);
mas2 = ea & ~((1UL << shift) - 1);
mas2 |= (pte_val(pte) >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK;
--
1.8.1.2
^ permalink raw reply related
* [PATCH v3 1/3] powerpc: add barrier after writing kernel PTE
From: Scott Wood @ 2013-10-12 0:22 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Scott Wood, linuxppc-dev
There is no barrier between something like ioremap() writing to
a PTE, and returning the value to a caller that may then store the
pointer in a place that is visible to other CPUs. Such callers
generally don't perform barriers of their own.
Even if callers of ioremap() and similar things did use barriers,
the most logical choise would be smp_wmb(), which is not
architecturally sufficient when BookE hardware tablewalk is used. A
full sync is specified by the architecture.
For userspace mappings, OTOH, we generally already have an lwsync due
to locking, and if we occasionally take a spurious fault due to not
having a full sync with hardware tablewalk, it will not be fatal
because we will retry rather than oops.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v3: Only add a sync for kernel mappings, and add lwsync to kernel
mappings even on targets that can't have BookE hardware tablewalk.
---
arch/powerpc/mm/pgtable_32.c | 1 +
arch/powerpc/mm/pgtable_64.c | 12 ++++++++++++
2 files changed, 13 insertions(+)
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 6c856fb..bc4806c 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -296,6 +296,7 @@ int map_page(unsigned long va, phys_addr_t pa, int flags)
set_pte_at(&init_mm, va, pg, pfn_pte(pa >> PAGE_SHIFT,
__pgprot(flags)));
}
+ smp_wmb();
return err;
}
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 536eec72..de83a39 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -153,6 +153,18 @@ int map_kernel_page(unsigned long ea, unsigned long pa, int flags)
}
#endif /* !CONFIG_PPC_MMU_NOHASH */
}
+
+#ifdef CONFIG_PPC_BOOK3E_64
+ /*
+ * With hardware tablewalk, a sync is needed to ensure that
+ * subsequent accesses see the PTE we just wrote. Unlike userspace
+ * mappings, we can't tolerate spurious faults, so make sure
+ * the new PTE will be seen the first time.
+ */
+ mb();
+#else
+ smp_wmb();
+#endif
return 0;
}
--
1.8.1.2
^ permalink raw reply related
* [PATCH v3 2/3] powerpc/e6500: TLB miss handler with hardware tablewalk support
From: Scott Wood @ 2013-10-12 0:22 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Scott Wood, Mihai Caraman, linuxppc-dev
In-Reply-To: <1381537359-22863-1-git-send-email-scottwood@freescale.com>
There are a few things that make the existing hw tablewalk handlers
unsuitable for e6500:
- Indirect entries go in TLB1 (though the resulting direct entries go in
TLB0).
- It has threads, but no "tlbsrx." -- so we need a spinlock and
a normal "tlbsx". Because we need this lock, hardware tablewalk
is mandatory on e6500 unless we want to add spinlock+tlbsx to
the normal bolted TLB miss handler.
- TLB1 has no HES (nor next-victim hint) so we need software round robin
(TODO: integrate this round robin data with hugetlb/KVM)
- The existing tablewalk handlers map half of a page table at a time,
because IBM hardware has a fixed 1MiB indirect page size. e6500
has variable size indirect entries, with a minimum of 2MiB.
So we can't do the half-page indirect mapping, and even if we
could it would be less efficient than mapping the full page.
- Like on e5500, the linear mapping is bolted, so we don't need the
overhead of supporting nested tlb misses.
Note that hardware tablewalk does not work in rev1 of e6500.
We do not expect to support e6500 rev1 in mainline Linux.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Mihai Caraman <mihai.caraman@freescale.com>
--
v3: no changes
v2: Changes mostly requested by Ben:
- Renamed book3e_tlb_per_core to tlb_core_data.
- Moved the tlb_core data struct later in the paca. I had thought that
keeping it in the same cache line as other stuff used in the TLB
miss handler would be beneficial, but it actually benchmarks as
slightly slower for some reason that I haven't been able to figure
out (even compared to leaving padding in place so that the layout
of that part of the paca doesn't change).
I did not remove it from the paca altogether, though, because
per-cpu data isn't working that early, and failing that, this is the
simplest way to get something on every CPU, with no wasted space for
avoiding cache line sharing, etc. Note that we do need one of these
structs on every thread (not core) until we've booted far enough to
figure out the thread topology.
- Moved the callsite of setup_tlb_core_data() to setup_system().
- Added BUILD_BUG_ON(MMU_PAGE_COUNT > 16).
- Stopped using implicit boolean conversion of book3e_htw_mode.
---
arch/powerpc/include/asm/mmu-book3e.h | 13 +++
arch/powerpc/include/asm/mmu.h | 21 +++--
arch/powerpc/include/asm/paca.h | 6 ++
arch/powerpc/kernel/asm-offsets.c | 9 ++
arch/powerpc/kernel/paca.c | 5 +
arch/powerpc/kernel/setup_64.c | 31 +++++++
arch/powerpc/mm/fsl_booke_mmu.c | 7 ++
arch/powerpc/mm/mem.c | 6 ++
arch/powerpc/mm/tlb_low_64e.S | 167 ++++++++++++++++++++++++++++++++++
arch/powerpc/mm/tlb_nohash.c | 93 +++++++++++++------
10 files changed, 322 insertions(+), 36 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 936db36..89b785d 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -286,8 +286,21 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
extern int mmu_linear_psize;
extern int mmu_vmemmap_psize;
+struct tlb_core_data {
+ /* For software way selection, as on Freescale TLB1 */
+ u8 esel_next, esel_max, esel_first;
+
+ /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */
+ u8 lock;
+};
+
#ifdef CONFIG_PPC64
extern unsigned long linear_map_top;
+extern int book3e_htw_mode;
+
+#define PPC_HTW_NONE 0
+#define PPC_HTW_IBM 1
+#define PPC_HTW_E6500 2
/*
* 64-bit booke platforms don't load the tlb in the tlb miss handler code.
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 691fd8a..f8d1d6d 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -180,16 +180,17 @@ static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
#define MMU_PAGE_256K 4
#define MMU_PAGE_1M 5
-#define MMU_PAGE_4M 6
-#define MMU_PAGE_8M 7
-#define MMU_PAGE_16M 8
-#define MMU_PAGE_64M 9
-#define MMU_PAGE_256M 10
-#define MMU_PAGE_1G 11
-#define MMU_PAGE_16G 12
-#define MMU_PAGE_64G 13
-
-#define MMU_PAGE_COUNT 14
+#define MMU_PAGE_2M 6
+#define MMU_PAGE_4M 7
+#define MMU_PAGE_8M 8
+#define MMU_PAGE_16M 9
+#define MMU_PAGE_64M 10
+#define MMU_PAGE_256M 11
+#define MMU_PAGE_1G 12
+#define MMU_PAGE_16G 13
+#define MMU_PAGE_64G 14
+
+#define MMU_PAGE_COUNT 15
#if defined(CONFIG_PPC_STD_MMU_64)
/* 64-bit classic hash table MMU */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index a5954ce..bea5872 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -113,6 +113,10 @@ struct paca_struct {
/* Keep pgd in the same cacheline as the start of extlb */
pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
pgd_t *kernel_pgd; /* Kernel PGD */
+
+ /* Shared by all threads of a core -- points to tcd of first thread */
+ struct tlb_core_data *tcd_ptr;
+
/* We can have up to 3 levels of reentrancy in the TLB miss handler */
u64 extlb[3][EX_TLB_SIZE / sizeof(u64)];
u64 exmc[8]; /* used for machine checks */
@@ -123,6 +127,8 @@ struct paca_struct {
void *mc_kstack;
void *crit_kstack;
void *dbg_kstack;
+
+ struct tlb_core_data tcd;
#endif /* CONFIG_PPC_BOOK3E */
mm_context_t context;
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index d8958be..f12673c 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -209,6 +209,15 @@ int main(void)
DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
+ DEFINE(PACA_TCD_PTR, offsetof(struct paca_struct, tcd_ptr));
+
+ DEFINE(TCD_ESEL_NEXT,
+ offsetof(struct tlb_core_data, esel_next));
+ DEFINE(TCD_ESEL_MAX,
+ offsetof(struct tlb_core_data, esel_max));
+ DEFINE(TCD_ESEL_FIRST,
+ offsetof(struct tlb_core_data, esel_first));
+ DEFINE(TCD_LOCK, offsetof(struct tlb_core_data, lock));
#endif /* CONFIG_PPC_BOOK3E */
#ifdef CONFIG_PPC_STD_MMU_64
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index 3fc16e3..6f98e8b 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -144,6 +144,11 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
#ifdef CONFIG_PPC_STD_MMU_64
new_paca->slb_shadow_ptr = &slb_shadow[cpu];
#endif /* CONFIG_PPC_STD_MMU_64 */
+
+#ifdef CONFIG_PPC_BOOK3E
+ /* For now -- if we have threads this will be adjusted later */
+ new_paca->tcd_ptr = &new_paca->tcd;
+#endif
}
/* Put the paca pointer into r13 and SPRG_PACA */
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 278ca93..6548003 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -99,6 +99,36 @@ int dcache_bsize;
int icache_bsize;
int ucache_bsize;
+#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
+static void setup_tlb_core_data(void)
+{
+ int cpu;
+
+ for_each_possible_cpu(cpu) {
+ int first = cpu_first_thread_sibling(cpu);
+
+ paca[cpu].tcd_ptr = &paca[first].tcd;
+
+ /*
+ * If we have threads, we need either tlbsrx.
+ * or e6500 tablewalk mode, or else TLB handlers
+ * will be racy and could produce duplicate entries.
+ */
+ if (smt_enabled_at_boot >= 2 &&
+ !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
+ book3e_htw_mode != PPC_HTW_E6500) {
+ /* Should we panic instead? */
+ WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
+ __func__);
+ }
+ }
+}
+#else
+static void setup_tlb_core_data(void)
+{
+}
+#endif
+
#ifdef CONFIG_SMP
static char *smt_enabled_cmdline;
@@ -447,6 +477,7 @@ void __init setup_system(void)
smp_setup_cpu_maps();
check_smt_enabled();
+ setup_tlb_core_data();
#ifdef CONFIG_SMP
/* Release secondary cpus out of their spinloops at 0x60 now that
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 07ba45b..b2f096e 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -52,6 +52,7 @@
#include <asm/smp.h>
#include <asm/machdep.h>
#include <asm/setup.h>
+#include <asm/paca.h>
#include "mmu_decl.h"
@@ -192,6 +193,12 @@ unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
}
tlbcam_index = i;
+#ifdef CONFIG_PPC64
+ get_paca()->tcd.esel_next = i;
+ get_paca()->tcd.esel_max = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
+ get_paca()->tcd.esel_first = i;
+#endif
+
return amount_mapped;
}
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 1cf9c5b..9e11edc 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -299,6 +299,12 @@ void __init paging_init(void)
void __init mem_init(void)
{
+ /*
+ * book3s is limited to 16 page sizes due to encoding this in
+ * a 4-bit field for slices.
+ */
+ BUILD_BUG_ON(MMU_PAGE_COUNT > 16);
+
#ifdef CONFIG_SWIOTLB
swiotlb_init(0);
#endif
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index b4113bf..f11ec58 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -239,6 +239,173 @@ itlb_miss_fault_bolted:
beq tlb_miss_common_bolted
b itlb_miss_kernel_bolted
+/*
+ * TLB miss handling for e6500 and derivatives, using hardware tablewalk.
+ *
+ * Linear mapping is bolted: no virtual page table or nested TLB misses
+ * Indirect entries in TLB1, hardware loads resulting direct entries
+ * into TLB0
+ * No HES or NV hint on TLB1, so we need to do software round-robin
+ * No tlbsrx. so we need a spinlock, and we have to deal
+ * with MAS-damage caused by tlbsx
+ * 4K pages only
+ */
+
+ START_EXCEPTION(instruction_tlb_miss_e6500)
+ tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
+
+ ld r11,PACA_TCD_PTR(r13)
+ srdi. r15,r16,60 /* get region */
+ ori r16,r16,1
+
+ TLB_MISS_STATS_SAVE_INFO_BOLTED
+ bne tlb_miss_kernel_e6500 /* user/kernel test */
+
+ b tlb_miss_common_e6500
+
+ START_EXCEPTION(data_tlb_miss_e6500)
+ tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
+
+ ld r11,PACA_TCD_PTR(r13)
+ srdi. r15,r16,60 /* get region */
+ rldicr r16,r16,0,62
+
+ TLB_MISS_STATS_SAVE_INFO_BOLTED
+ bne tlb_miss_kernel_e6500 /* user vs kernel check */
+
+/*
+ * This is the guts of the TLB miss handler for e6500 and derivatives.
+ * We are entered with:
+ *
+ * r16 = page of faulting address (low bit 0 if data, 1 if instruction)
+ * r15 = crap (free to use)
+ * r14 = page table base
+ * r13 = PACA
+ * r11 = tlb_per_core ptr
+ * r10 = crap (free to use)
+ */
+tlb_miss_common_e6500:
+ /*
+ * Search if we already have an indirect entry for that virtual
+ * address, and if we do, bail out.
+ *
+ * MAS6:IND should be already set based on MAS4
+ */
+ addi r10,r11,TCD_LOCK
+1: lbarx r15,0,r10
+ cmpdi r15,0
+ bne 2f
+ li r15,1
+ stbcx. r15,0,r10
+ bne 1b
+ .subsection 1
+2: lbz r15,0(r10)
+ cmpdi r15,0
+ bne 2b
+ b 1b
+ .previous
+
+ mfspr r15,SPRN_MAS2
+
+ tlbsx 0,r16
+ mfspr r10,SPRN_MAS1
+ andis. r10,r10,MAS1_VALID@h
+ bne tlb_miss_done_e6500
+
+ /* Undo MAS-damage from the tlbsx */
+ mfspr r10,SPRN_MAS1
+ oris r10,r10,MAS1_VALID@h
+ mtspr SPRN_MAS1,r10
+ mtspr SPRN_MAS2,r15
+
+ /* Now, we need to walk the page tables. First check if we are in
+ * range.
+ */
+ rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
+ bne- tlb_miss_fault_e6500
+
+ rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
+ cmpldi cr0,r14,0
+ clrrdi r15,r15,3
+ beq- tlb_miss_fault_e6500 /* No PGDIR, bail */
+ ldx r14,r14,r15 /* grab pgd entry */
+
+ rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
+ clrrdi r15,r15,3
+ cmpdi cr0,r14,0
+ bge tlb_miss_fault_e6500 /* Bad pgd entry or hugepage; bail */
+ ldx r14,r14,r15 /* grab pud entry */
+
+ rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
+ clrrdi r15,r15,3
+ cmpdi cr0,r14,0
+ bge tlb_miss_fault_e6500
+ ldx r14,r14,r15 /* Grab pmd entry */
+
+ mfspr r10,SPRN_MAS0
+ cmpdi cr0,r14,0
+ bge tlb_miss_fault_e6500
+
+ /* Now we build the MAS for a 2M indirect page:
+ *
+ * MAS 0 : ESEL needs to be filled by software round-robin
+ * MAS 1 : Almost fully setup
+ * - PID already updated by caller if necessary
+ * - TSIZE for now is base ind page size always
+ * MAS 2 : Use defaults
+ * MAS 3+7 : Needs to be done
+ */
+
+ ori r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
+ mtspr SPRN_MAS7_MAS3,r14
+
+ lbz r15,TCD_ESEL_NEXT(r11)
+ lbz r16,TCD_ESEL_MAX(r11)
+ lbz r14,TCD_ESEL_FIRST(r11)
+ rlwimi r10,r15,16,0x00ff0000 /* insert esel_next into MAS0 */
+ addi r15,r15,1 /* increment esel_next */
+ mtspr SPRN_MAS0,r10
+ cmpw r15,r16
+ iseleq r15,r14,r15 /* if next == last use first */
+ stb r15,TCD_ESEL_NEXT(r11)
+
+ tlbwe
+
+tlb_miss_done_e6500:
+ .macro tlb_unlock_e6500
+ li r15,0
+ isync
+ stb r15,TCD_LOCK(r11)
+ .endm
+
+ tlb_unlock_e6500
+ TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
+ tlb_epilog_bolted
+ rfi
+
+tlb_miss_kernel_e6500:
+ mfspr r10,SPRN_MAS1
+ ld r14,PACA_KERNELPGD(r13)
+ cmpldi cr0,r15,8 /* Check for vmalloc region */
+ rlwinm r10,r10,0,16,1 /* Clear TID */
+ mtspr SPRN_MAS1,r10
+ beq+ tlb_miss_common_e6500
+
+tlb_miss_fault_e6500:
+ tlb_unlock_e6500
+ /* We need to check if it was an instruction miss */
+ andi. r16,r16,1
+ bne itlb_miss_fault_e6500
+dtlb_miss_fault_e6500:
+ TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
+ tlb_epilog_bolted
+ b exc_data_storage_book3e
+itlb_miss_fault_e6500:
+ TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
+ tlb_epilog_bolted
+ b exc_instruction_storage_book3e
+
+
/**********************************************************************
* *
* TLB miss handling for Book3E with TLB reservation and HES support *
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 41cd68d..f763e57 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -43,6 +43,7 @@
#include <asm/tlb.h>
#include <asm/code-patching.h>
#include <asm/hugetlb.h>
+#include <asm/paca.h>
#include "mmu_decl.h"
@@ -58,6 +59,10 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
.shift = 12,
.enc = BOOK3E_PAGESZ_4K,
},
+ [MMU_PAGE_2M] = {
+ .shift = 21,
+ .enc = BOOK3E_PAGESZ_2M,
+ },
[MMU_PAGE_4M] = {
.shift = 22,
.enc = BOOK3E_PAGESZ_4M,
@@ -136,7 +141,7 @@ static inline int mmu_get_tsize(int psize)
int mmu_linear_psize; /* Page size used for the linear mapping */
int mmu_pte_psize; /* Page size used for PTE pages */
int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
-int book3e_htw_enabled; /* Is HW tablewalk enabled ? */
+int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
unsigned long linear_map_top; /* Top of linear mapping */
#endif /* CONFIG_PPC64 */
@@ -377,7 +382,7 @@ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
{
int tsize = mmu_psize_defs[mmu_pte_psize].enc;
- if (book3e_htw_enabled) {
+ if (book3e_htw_mode != PPC_HTW_NONE) {
unsigned long start = address & PMD_MASK;
unsigned long end = address + PMD_SIZE;
unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
@@ -430,7 +435,7 @@ static void setup_page_sizes(void)
def = &mmu_psize_defs[psize];
shift = def->shift;
- if (shift == 0)
+ if (shift == 0 || shift & 1)
continue;
/* adjust to be in terms of 4^shift Kb */
@@ -440,21 +445,40 @@ static void setup_page_sizes(void)
def->flags |= MMU_PAGE_SIZE_DIRECT;
}
- goto no_indirect;
+ goto out;
}
if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
- u32 tlb1ps = mfspr(SPRN_TLB1PS);
+ u32 tlb1cfg, tlb1ps;
+
+ tlb0cfg = mfspr(SPRN_TLB0CFG);
+ tlb1cfg = mfspr(SPRN_TLB1CFG);
+ tlb1ps = mfspr(SPRN_TLB1PS);
+ eptcfg = mfspr(SPRN_EPTCFG);
+
+ if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT))
+ book3e_htw_mode = PPC_HTW_E6500;
+
+ /*
+ * We expect 4K subpage size and unrestricted indirect size.
+ * The lack of a restriction on indirect size is a Freescale
+ * extension, indicated by PSn = 0 but SPSn != 0.
+ */
+ if (eptcfg != 2)
+ book3e_htw_mode = PPC_HTW_NONE;
for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
struct mmu_psize_def *def = &mmu_psize_defs[psize];
if (tlb1ps & (1U << (def->shift - 10))) {
def->flags |= MMU_PAGE_SIZE_DIRECT;
+
+ if (book3e_htw_mode && psize == MMU_PAGE_2M)
+ def->flags |= MMU_PAGE_SIZE_INDIRECT;
}
}
- goto no_indirect;
+ goto out;
}
#endif
@@ -471,8 +495,11 @@ static void setup_page_sizes(void)
}
/* Indirect page sizes supported ? */
- if ((tlb0cfg & TLBnCFG_IND) == 0)
- goto no_indirect;
+ if ((tlb0cfg & TLBnCFG_IND) == 0 ||
+ (tlb0cfg & TLBnCFG_PT) == 0)
+ goto out;
+
+ book3e_htw_mode = PPC_HTW_IBM;
/* Now, we only deal with one IND page size for each
* direct size. Hopefully all implementations today are
@@ -497,8 +524,8 @@ static void setup_page_sizes(void)
def->ind = ps + 10;
}
}
- no_indirect:
+out:
/* Cleanup array and print summary */
pr_info("MMU: Supported page sizes\n");
for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
@@ -539,23 +566,23 @@ static void __patch_exception(int exc, unsigned long addr)
static void setup_mmu_htw(void)
{
- /* Check if HW tablewalk is present, and if yes, enable it by:
- *
- * - patching the TLB miss handlers to branch to the
- * one dedicates to it
- *
- * - setting the global book3e_htw_enabled
- */
- unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
+ /*
+ * If we want to use HW tablewalk, enable it by patching the TLB miss
+ * handlers to branch to the one dedicated to it.
+ */
- if ((tlb0cfg & TLBnCFG_IND) &&
- (tlb0cfg & TLBnCFG_PT)) {
+ switch (book3e_htw_mode) {
+ case PPC_HTW_IBM:
patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
- book3e_htw_enabled = 1;
+ break;
+ case PPC_HTW_E6500:
+ patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
+ patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
+ break;
}
pr_info("MMU: Book3E HW tablewalk %s\n",
- book3e_htw_enabled ? "enabled" : "not supported");
+ book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");
}
/*
@@ -595,8 +622,16 @@ static void __early_init_mmu(int boot_cpu)
/* Set MAS4 based on page table setting */
mas4 = 0x4 << MAS4_WIMGED_SHIFT;
- if (book3e_htw_enabled) {
- mas4 |= mas4 | MAS4_INDD;
+ switch (book3e_htw_mode) {
+ case PPC_HTW_E6500:
+ mas4 |= MAS4_INDD;
+ mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT;
+ mas4 |= MAS4_TLBSELD(1);
+ mmu_pte_psize = MMU_PAGE_2M;
+ break;
+
+ case PPC_HTW_IBM:
+ mas4 |= MAS4_INDD;
#ifdef CONFIG_PPC_64K_PAGES
mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
mmu_pte_psize = MMU_PAGE_256M;
@@ -604,13 +639,16 @@ static void __early_init_mmu(int boot_cpu)
mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
mmu_pte_psize = MMU_PAGE_1M;
#endif
- } else {
+ break;
+
+ case PPC_HTW_NONE:
#ifdef CONFIG_PPC_64K_PAGES
mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
#else
mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
#endif
mmu_pte_psize = mmu_virtual_psize;
+ break;
}
mtspr(SPRN_MAS4, mas4);
@@ -630,8 +668,11 @@ static void __early_init_mmu(int boot_cpu)
/* limit memory so we dont have linear faults */
memblock_enforce_memory_limit(linear_map_top);
- patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
- patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e);
+ if (book3e_htw_mode == PPC_HTW_NONE) {
+ patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
+ patch_exception(0x1e0,
+ exc_instruction_tlb_miss_bolted_book3e);
+ }
}
#endif
--
1.8.1.2
^ permalink raw reply related
* Re: [PATCH v2 1/3] powerpc/booke64: add sync after writing PTE
From: Benjamin Herrenschmidt @ 2013-10-11 22:34 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <1381529267.7979.582.camel@snotra.buserror.net>
On Fri, 2013-10-11 at 17:07 -0500, Scott Wood wrote:
> On Fri, 2013-10-11 at 10:51 +1100, Benjamin Herrenschmidt wrote:
> > On Thu, 2013-10-10 at 18:25 -0500, Scott Wood wrote:
> >
> > > Looking at some of the code in mm/, I suspect that the normal callers of
> > > set_pte_at() already have an unlock (and thus a sync)
> >
> > Unlock is lwsync actually...
>
> Oops, I was seeing the conditional sync from SYNC_IO in the disassembly.
> BTW, it's a bug that we don't do SYNC_IO on e500mc -- the assumption
> that lwsync is 64-bit-only is no longer true.
Patch welcome :)
> > > already, so we may
> > > not even be relying on those retries. Certainly some of them do; it
> > > would take some effort to verify all of them.
> > >
> > > Also, without such a sync in map_kernel_page(), even with software
> > > tablewalk, couldn't we theoretically have a situation where a store to
> > > pointer X that exposes a new mapping gets reordered before the PTE store
> > > as seen by another CPU? The other CPU could see non-NULL X and
> > > dereference it, but get the stale PTE. Callers of ioremap() generally
> > > don't do a barrier of their own prior to exposing the result.
> >
> > Hrm, we transition to the new PTE either restricts the access permission
> > in which case it flushes the TLB (and synchronizes with other CPUs) or
> > extends access (adds dirty, set pte from 0 -> populated, ...) in which
> > case the worst case is we see the old one and take a spurrious fault.
>
> Yes, and the lwsync is good enough for software reading the PTE. So it
> becomes a question of how much spurious faults with hardware tablewalk
> hurt performance, and at least for the lmbench fork test, the sync is
> worse (or maybe lwsync happens to be good enough for hw tablewalk on
> e6500?).
>
> > So the problem would only be with kernel mappings and in that case I
> > think we are fine. A driver doing an ioremap shouldn't then start using
> > that mapping on another CPU before having *informed* that other CPU of
> > the existence of the mapping and that should be ordered.
>
> But are callers of ioremap() expected to use a barrier before exposing
> the pointer (and what type)? I don't think that's common practice.
>
> map_kernel_page() should not be performance critical, so it shouldn't be
> a big deal to put mb() in there.
Yup, go for it.
Cheers,
Ben.
> -Scott
>
>
^ permalink raw reply
* Re: [PATCH v2 1/3] powerpc/booke64: add sync after writing PTE
From: Scott Wood @ 2013-10-11 22:07 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1381449086.5630.42.camel@pasglop>
On Fri, 2013-10-11 at 10:51 +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2013-10-10 at 18:25 -0500, Scott Wood wrote:
>
> > Looking at some of the code in mm/, I suspect that the normal callers of
> > set_pte_at() already have an unlock (and thus a sync)
>
> Unlock is lwsync actually...
Oops, I was seeing the conditional sync from SYNC_IO in the disassembly.
BTW, it's a bug that we don't do SYNC_IO on e500mc -- the assumption
that lwsync is 64-bit-only is no longer true.
> > already, so we may
> > not even be relying on those retries. Certainly some of them do; it
> > would take some effort to verify all of them.
> >
> > Also, without such a sync in map_kernel_page(), even with software
> > tablewalk, couldn't we theoretically have a situation where a store to
> > pointer X that exposes a new mapping gets reordered before the PTE store
> > as seen by another CPU? The other CPU could see non-NULL X and
> > dereference it, but get the stale PTE. Callers of ioremap() generally
> > don't do a barrier of their own prior to exposing the result.
>
> Hrm, we transition to the new PTE either restricts the access permission
> in which case it flushes the TLB (and synchronizes with other CPUs) or
> extends access (adds dirty, set pte from 0 -> populated, ...) in which
> case the worst case is we see the old one and take a spurrious fault.
Yes, and the lwsync is good enough for software reading the PTE. So it
becomes a question of how much spurious faults with hardware tablewalk
hurt performance, and at least for the lmbench fork test, the sync is
worse (or maybe lwsync happens to be good enough for hw tablewalk on
e6500?).
> So the problem would only be with kernel mappings and in that case I
> think we are fine. A driver doing an ioremap shouldn't then start using
> that mapping on another CPU before having *informed* that other CPU of
> the existence of the mapping and that should be ordered.
But are callers of ioremap() expected to use a barrier before exposing
the pointer (and what type)? I don't think that's common practice.
map_kernel_page() should not be performance critical, so it shouldn't be
a big deal to put mb() in there.
-Scott
^ permalink raw reply
* Re: PCIE device errors after linux kernel upgrade
From: Bjorn Helgaas @ 2013-10-11 22:01 UTC (permalink / raw)
To: Leon Ravich; +Cc: linux-pci@vger.kernel.org, linuxppc-dev
In-Reply-To: <CAErSpo6zGZkL7hWmBOVzd2=MWvY18v5xLO1qg7jVfSgqa8wHzw@mail.gmail.com>
On Fri, Aug 16, 2013 at 4:05 PM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> On Tue, Aug 6, 2013 at 11:41 PM, Leon Ravich <lravich@gmail.com> wrote:
>> From comparison of pci printout from the two kernel ,
>> beside the EDAC errors I noticed other strange differences:
>>
>> In 3.8.13 I got BAR 7 and BAR 8:
>> [ 39.017749] pci 0000:00:00.0: BAR 8: assigned [mem 0xc0000000-0xdfffffff]
>> [ 39.024530] pci 0000:00:00.0: BAR 7: can't assign io (size 0x10000)
>>
>> In 3.8.13 I am getting:
>> [ 38.931873] pci_bus 0000:01: busn_res: can not insert [bus 01-ff]
>> under [bus 00-01] (conflicts with (null) [bus 00-01])
>>
>>
>> On 6 August 2013 09:32, Leon Ravich <lravich@gmail.com> wrote:
>>> Thanks Bjorn.
>
> Is this still a problem, or have you found a solution in the meantime?
>
>>> 1) If I understand it right this patch only removes the "pci
>>> 0000:00:00.0: ignoring class 0x0b2000 (doesn't
>>> match header type 01)" message , don't care about it , had it before .
>
> It also affects how the PCI core handles the device. But as you said,
> if you had the message before, it's probably not the cause of the
> current problem.
>
>>> 2) regarding the comparing of printouts:
>
> Can you post the complete logs somewhere, maybe in a bugzilla or similar?
>
> Where are the "PCIE ERR_CAP_STAT" and similar messages from? My quick
> grep didn't find them.
Did this problem ever get resolved? Is there anything we need to look at?
Bjorn
^ permalink raw reply
* Re: [PATCH 1/2] tty/hvc_console: Add DTR/RTS callback to handle HUPCL control
From: Benjamin Herrenschmidt @ 2013-10-11 20:43 UTC (permalink / raw)
To: Hendrik Brueckner
Cc: linux-s390, gregkh, heiko.carstens, linuxppc-dev, linux-kernel,
brueckner, schwidefsky, jslaby
In-Reply-To: <20131011124707.GA6082@linux.vnet.ibm.com>
On Fri, 2013-10-11 at 14:47 +0200, Hendrik Brueckner wrote:
> The tiocmget/tiocmset callbacks are used to set and get modem status and
> triggered through an tty ioctl.
>
> The dtr_rts() callback is different and it is used for DTS/RTS handshaking
> between the hvc_console (or any other tty_port) and the tty layer. The tty
> port layer uses this callback to signal the hvc_console whether to raise or
> lower the DTR/RTS lines. This is different than the ioctl interface to
> controls the modem status.
Well, DTR at least is the same via both callbacks... Also normal handshaking
is normally RTS/CTS, only some HW setups "hijacks" DTR for RTS (old Macs come
to mind).
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH RFC 00/77] Re-design MSI/MSI-X interrupts enablement pattern
From: Mark Lord @ 2013-10-11 20:29 UTC (permalink / raw)
To: Alexander Gordeev
Cc: linux-mips, VMware, Inc., linux-nvme, linux-ide, H. Peter Anvin,
linux-s390, Andy King, linux-scsi, linux-rdma, x86, Ingo Molnar,
linux-pci, iss_storagedev, linux-driver, Tejun Heo, Bjorn Helgaas,
Dan Williams, Jon Mason, Solarflare linux maintainers, netdev,
linux-kernel, Ralf Baechle, e1000-devel, Martin Schwidefsky,
linux390, linuxppc-dev
In-Reply-To: <20131011084108.GA25702@dhcp-26-207.brq.redhat.com>
On 13-10-11 04:41 AM, Alexander Gordeev wrote:
> On Thu, Oct 10, 2013 at 07:17:18PM -0400, Mark Lord wrote:
>> Just to help us all understand "the loop" issue..
>>
>> Here's an example of driver code which uses the existing MSI-X interfaces,
>> for a device which can work with either 16, 8, 4, 2, or 1 MSI-X interrupt.
>> This is from a new driver I'm working on right now:
..
> Now, this is a loop-free alternative:
>
> static int xx_alloc_msix_irqs(struct xx_dev *dev, int nvec)
> {
> nvec = roundup_pow_of_two(nvec); /* assume 0 > nvec <= 16 */
>
> xx_disable_all_irqs(dev);
>
> pci_lock_msi(dev->pdev);
>
> rc = pci_get_msix_limit(dev->pdev, nvec);
> if (rc < 0)
> goto err;
>
> nvec = min(nvec, rc); /* if limit is more than requested */
> nvec = rounddown_pow_of_two(nvec); /* (a) */
>
> xx_prep_for_msix_vectors(dev, nvec);
>
> rc = pci_enable_msix(dev->pdev, dev->irqs, nvec); /* (b) */
> if (rc < 0)
> goto err;
>
> pci_unlock_msi(dev->pdev);
>
> dev->num_vectors = nvec; /* (b) */
> return 0;
>
> err:
> pci_unlock_msi(dev->pdev);
>
> kerr(dev->name, "pci_enable_msix() failed, err=%d", rc);
> dev->num_vectors = 0;
> return rc;
> }
That would still need a loop, to handle the natural race between
the calls to pci_get_msix_limit() and pci_enable_msix() -- the driver and device
can and should fall back to a smaller number of vectors when pci_enable_msix() fails.
^ permalink raw reply
* Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree
From: Scott Wood @ 2013-10-11 19:08 UTC (permalink / raw)
To: Yuantian.Tang; +Cc: devicetree, linuxppc-dev
In-Reply-To: <1381300704-4238-1-git-send-email-Yuantian.Tang@freescale.com>
On Wed, 2013-10-09 at 14:38 +0800, Yuantian.Tang@freescale.com wrote:
> From: Tang Yuantian <yuantian.tang@frovider:
> +/ {
> + clockgen: global-utilities@e1000 {
> + compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> + reg = <0xe1000 0x1000>;
> + clock-frequency = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sysclk: sysclk {
> + #clock-cells = <0>;
> + compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
> + clock-output-names = "sysclk";
> + }
> +
> + pll0: pll0@800 {
> + #clock-cells = <1>;
> + reg = <0x800 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll0", "pll0-div2";
> + };
Where is "ranges" in the global-utilities node?
-Scott
^ permalink raw reply
* Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree
From: Scott Wood @ 2013-10-11 19:07 UTC (permalink / raw)
To: Mark Rutland
Cc: Tang Yuantian-B29983, devicetree@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, Li Yang-Leo-R58472
In-Reply-To: <20131011092526.GE3910@e106331-lin.cambridge.arm.com>
On Fri, 2013-10-11 at 10:25 +0100, Mark Rutland wrote:
> On Fri, Oct 11, 2013 at 04:18:18AM +0100, Tang Yuantian-B29983 wrote:
> > Thanks for your review.
> > See my reply inline
> >
> > > -----Original Message-----
> > > From: Mark Rutland [mailto:mark.rutland@arm.com]
> > > Sent: 2013=E5=B9=B410=E6=9C=8810=E6=97=A5 =E6=98=9F=E6=9C=9F=E5=9B=9B=
18:04
> > > To: Tang Yuantian-B29983
> > > Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> > > devicetree@vger.kernel.org; Li Yang-Leo-R58472
> > > Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in =
device
> > > tree
> > >
> > > On Wed, Oct 09, 2013 at 07:38:24AM +0100, Yuantian.Tang@freescale.c=
om
> > > wrote:
> > > > From: Tang Yuantian <yuantian.tang@freescale.com>
> > > >
> > > > The following SoCs will be affected: p2041, p3041, p4080, p5020,
> > > > p5040, b4420, b4860, t4240
> > > >
> > > > Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> > > > Signed-off-by: Li Yang <leoli@freescale.com>
> > > > ---
> > > > v5:
> > > > - refine the binding document
> > > > - update the compatible string
> > > > v4:
> > > > - add binding document
> > > > - update compatible string
> > > > - update the reg property
> > > > v3:
> > > > - fix typo
> > > > v2:
> > > > - add t4240, b4420, b4860 support
> > > > - remove pll/4 clock from p2041, p3041 and p5020 board
> > > >
> > > > .../devicetree/bindings/clock/corenet-clock.txt | 111
> > > ++++++++++++++++++++
> > > > arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 35 +++++++
> > > > arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 2 +
> > > > arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 35 +++++++
> > > > arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 4 +
> > > > arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 60 +++++++=
++++
> > > > arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 4 +
> > > > arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 60 +++++++=
++++
> > > > arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi | 4 +
> > > > arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 112
> > > +++++++++++++++++++++
> > > > arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi | 8 ++
> > > > arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 42 +++++++=
+
> > > > arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | 2 +
> > > > arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 60 +++++++=
++++
> > > > arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | 4 +
> > > > arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 85
> > > ++++++++++++++++
> > > > arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 12 +++
> > > > 17 files changed, 640 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/clock/corenet-clock.txt
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/clock/corenet-cloc=
k.txt
> > > > b/Documentation/devicetree/bindings/clock/corenet-clock.txt
> > > > new file mode 100644
> > > > index 0000000..8efc62d
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt
> > > > @@ -0,0 +1,111 @@
> > > > +* Clock Block on Freescale CoreNet Platforms
> > > > +
> > > > +Freescale CoreNet chips take primary clocking input from the ext=
ernal
> > > > +SYSCLK signal. The SYSCLK input (frequency) is multiplied using
> > > > +multiple phase locked loops (PLL) to create a variety of frequen=
cies
> > > > +which can then be passed to a variety of internal logic, includi=
ng
> > > > +cores and peripheral IP blocks.
> > > > +Please refer to the Reference Manual for details.
> > > > +
> > > > +1. Clock Block Binding
> > > > +
> > > > +Required properties:
> > > > +- compatible: Should include one or more of the following:
> > > > + - "fsl,<chip>-clockgen": for chip specific clock block
> > > > + - "fsl,qoriq-clockgen-[1,2].x": for chassis 1.x and 2.x c=
lock
> > >
> > > While I can see that "fsl,<chip>-clockgen" might have a large set o=
f
> > > strings that we may never deal with in th kernel, I'd prefer that t=
he
> > > basic strings (i.e. all the "fsl,qoriq-clockgen-[1,2].x" variants) =
were
> > > listed explicitly here.
> > >
> > > Given they only seem to be "fsl,qoriq-clockgen-1.0" and "fsl,qoriq-
> > > clockgen-2.0" this shouldn't be too difficult to list and describe.
> > >
> > OK, I will list them all.
>=20
> Thanks.
>=20
> >
> > > > +- reg: Offset and length of the clock register set
> > > > +- clock-frequency: Indicates input clock frequency of clock bloc=
k.
> > > > + Will be set by u-boot
> > >
> > > Why does the fact this is set by u-boot matter to the binding?
> > >
> > OK, I will remove it.
> >
> > > > +
> > > > +Recommended properties:
> > > > +- #ddress-cells: Specifies the number of cells used to represent
> > > > + physical base addresses. Must be present if the device h=
as
> > > > + sub-nodes and set to 1 if present
> > >
> > > Typo: #address-cells
> > >
> > > In the example it looks like the address cells of child nodes are o=
ffsets
> > > within the unit, rather than absolute physical addresses. Could the=
code
> > > not treat them as absolute addresses? Then we'd only need to docume=
nt
> > > that #address-cells, #size-cells and ranges must be present and hav=
e
> > > values suitable for mapping child nodes into the address space of t=
he
> > > parent.
> > >
> > OK, thanks.
> >
> > > > +- #size-cells: Specifies the number of cells used to represent
> > > > + the size of an address. Must be present if the device has
> > > > + sub-nodes and set to 1 if present
> > >
> > > It's not really the size of an address, it's the size of a region
> > > identified by a reg entry.
> > >
> > > I think this can be simplified by my suggestion above.
> > >
> > Yes
>=20
> Aah, I see that this is already in use, so it's a bit late to change
> this...
>=20
> >
> > > > +
> > > > +2. Clock Provider/Consumer Binding
> > > > +
> > > > +Most of the binding are from the common clock binding[1].
> > > > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> > > > +
> > > > +Required properties:
> > > > +- compatible : Should include one or more of the following:
>=20
> I didn't spot this earlier, but why "one or more"? are the 2.0 variants
> backwards compatible with the 1.0 variants.
>=20
> > > > + - "fsl,qoriq-core-pll-[1,2].x": Indicates a core PLL cloc=
k
> > > device
> > > > + - "fsl,qoriq-core-mux-[1,2].x": Indicates a core multiple=
xer
> > > clock
> > > > + device; divided from the core PLL clock
> > >
> > > As above, I'd prefer a complete list of the basic strings we expect=
.
> > >
> > There is no list here, just *-mux-1.x and *-mux-2.x
> > What kind of list do you prefer?
>=20
> Something like:
>=20
> - compatible: Should include at least one of:
> * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
> * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
> * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
> * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
> The *-2.0 variants are backwards compatible with the *-1.0 variants,
> so for compatiblity a *-1.0 variant string should be in the list.
I'm not sure that they're 100% compatible. 1.0 seems to have a "KILL"
bit in the PLL register that 2.0 doesn't have (unless it's a
documentation glitch).
> > > > +- clock-output-names: From common clock binding, indicates the n=
ames
> > > of
> > > > + output clocks
> > > > +- reg: Should be the offset and length of clock block base addre=
ss.
> > > > + The length should be 4.
> > > > +
> > > > +Example for clock block and clock provider:
> > > > +/ {
> > > > + clockgen: global-utilities@e1000 {
> > > > + compatible =3D "fsl,p5020-clockgen", "fsl,qoriq-c=
lockgen-
> > > 1.0";
> > > > + reg =3D <0xe1000 0x1000>;
> > > > + clock-frequency =3D <0>;
> > >
> > > That looks odd.
> > >
> > Yes, but it has already existed here before this patch.
> > Can I move it to sysclk clock node since it is not used yet?
>=20
> I hadn't realised there were DTS with this already. Why is there a cloc=
k
> with clock-frequency =3D <0> at all? Surely that isn't useful...
The actual frequency is patched in by U-Boot -- and moving it to a
different node would break this.
> > > > + #address-cells =3D <1>;
> > > > + #size-cells =3D <1>;
> > > > +
> > > > + sysclk: sysclk {
> > > > + #clock-cells =3D <0>;
> > > > + compatible =3D "fsl,qoriq-sysclk-1.0",
> > > > + "fixed-clock";
> > >
> > > We didn't mention in the binding that "fsl,qoriq-sysclk-1.0" was
> > > compatible with "fixed-clock" and should have "fixed-clock" in the
> > > compatible list...
> > >
> > OK, will fix it.
>=20
> Cheers. Also, doesn't a fixed-clock require a clock-frequency?
Why isn't the global-utilities node, that has the clock-frequency,
acting as the fixed-clock? I thought that's what was in earlier
revisions...
If it absolutely must be a separate node for some reason, I suppose you
could remove the "fixed-clock" and have a tiny "driver" that looks up
the frequency in the parent node. This would be an instance of a
non-"fixed-clock" that doesn't have a parent clock described in the
device tree, because the information comes from some other mechanism.
> > > > + mux1: mux1@20 {
> > > > + #clock-cells =3D <0>;
> > > > + reg =3D <0x20 0x4>;
> > > > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > > > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0=
>,
> > > <&pll1 1>;
> > > > + clock-names =3D "pll0_0", "pll0_1", "pll1=
_0",
> > > "pll1_1";
>=20
> I didn't spot this last time, but the clock-names here seem to be the
> names of the outputs from the provider, rather than the input names of
> the consumer. This goes against the intended purpose of clock-names.
As far as "pll0", "pll1", etc. goes, that appears to be the input name.
It's all on one chip, so the virtual pins are documented based on what
they're connected to.
I'm not sure I understand the "_0"/"_1" part, though. Doesn't each PLL
just have one output, which the consumer may choose to divide by 2 (or
in some cases 4)? Why does that division need to be exposed in the
device tree as separate connections to the parent clock?
-Scott
^ permalink raw reply
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