* Re: [PATCH v5 1/1] powerpc/embedded6xx: Add support for Motorola/Emerson MVME5100
From: Scott Wood @ 2014-01-07 23:51 UTC (permalink / raw)
To: Stephen Chivers; +Cc: linuxppc-dev
In-Reply-To: <20140106012306.A6AB5E06BF@canberra.localdomain>
On Mon, 2014-01-06 at 12:23 +1100, Stephen Chivers wrote:
> Add support for the Motorola/Emerson MVME5100 Single Board Computer.
>
> The MVME5100 is a 6U form factor VME64 computer with:
>
> - A single MPC7410 or MPC750 CPU
> - A HAWK Processor Host Bridge (CPU to PCI) and
> MultiProcessor Interrupt Controller (MPIC)
> - Up to 500Mb of onboard memory
> - A M48T37 Real Time Clock (RTC) and Non-Volatile Memory chip
> - Two 16550 compatible UARTS
> - Two Intel E100 Fast Ethernets
> - Two PCI Mezzanine Card (PMC) Slots
> - PPCBug Firmware
>
> The HAWK PHB/MPIC is compatible with the MPC10x devices.
>
> There is no onboard disk support. This is usually provided by installing a PMC
> in first PMC slot.
>
> This patch revives the board support, it was present in early 2.6
> series kernels. The board support in those days was by Matt Porter of
> MontaVista Software.
>
> CSC Australia has around 31 of these boards in service. The kernel in use
> for the boards is based on 2.6.31. The boards are operated without disks
> from a file server.
>
> This patch is based on linux-3.13-rc2 and has been boot tested.
>
> Only boards with 512 Mb of memory are known to work.
>
> V1->V2:
> Address comments by Kumar Gala and Scott Wood.
> Minor adjustment to platforms/embedded6xx/Kconfig to ensure
> correct indentation where possible.
>
> V2->V3:
> Address comments by Scott Wood and Ben Herrenschmidt.
> Address errors reported by checkpatch.
>
> V3->V4:
> Address comment by Geert Uytterhoeven
> Add tested by Alessio Bogani.
>
> V4->V5:
> Correct horrible typo in patch history.
> Kular Gama is Kumar Gala.
The patch history should go below the --- line, as it's for reviewers
who have seen previous versions rather than for the git history.
-Scott
^ permalink raw reply
* Re: [v7] clk: corenet: Adds the clock binding
From: Scott Wood @ 2014-01-08 0:21 UTC (permalink / raw)
To: tang yuantian; +Cc: mark.rutland, devicetree, linuxppc-dev
In-Reply-To: <1384938289-24713-1-git-send-email-Yuantian.Tang@freescale.com>
On Wed, Nov 20, 2013 at 05:04:49PM +0800, tang yuantian wrote:
> +Recommended properties:
> +- ranges: Allows valid translation between child's address space and
> + parent's. Must be present if the device has sub-nodes.
> +- #address-cells: Specifies the number of cells used to represent
> + physical base addresses. Must be present if the device has
> + sub-nodes and set to 1 if present
> +- #size-cells: Specifies the number of cells used to represent
> + the size of an address. Must be present if the device has
> + sub-nodes and set to 1 if present
Why are we specifying #address-cells/#size-cells here?
> +2. Clock Provider/Consumer Binding
> +
> +Most of the bindings are from the common clock binding[1].
> + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible : Should include one of the following:
> + * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
> + * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
> + * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
> + * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
> + * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0)
> + * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0)
Some of those lines use tabs and others spaces -- I can fix when applying.
-Scott
^ permalink raw reply
* Re: [V6,2/2] powerpc/85xx: Add TWR-P1025 board support
From: Scott Wood @ 2014-01-08 1:01 UTC (permalink / raw)
To: Xie Xiaobo; +Cc: linuxppc-dev, Michael Johnston
In-Reply-To: <1383728883-25561-2-git-send-email-X.Xie@freescale.com>
On Wed, Nov 06, 2013 at 05:08:03PM +0800, Xie Xiaobo wrote:
> TWR-P1025 Overview
> -----------------
> 512Mbyte DDR3 (on board DDR)
> 64MB Nor Flash
> eTSEC1: Connected to RGMII PHY AR8035
> eTSEC3: Connected to RGMII PHY AR8035
> Two USB2.0 Type A
> One microSD Card slot
> One mini-PCIe slot
> One mini-USB TypeB dual UART
>
> Signed-off-by: Michael Johnston <michael.johnston@freescale.com>
> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
>
> ---
> Patch V6: Add a binding doc for ssd1289 device.
> Patch V5: Miscellaneous modification. e.g. move the qe ucc node into dtsi.
> Patch V4: Fix the mdio phy interrupt issue in dts
> Patch V3: fix pcie range issue in dts
> Patch V2: QE related init codes were factored out to a common file
>
> .../devicetree/bindings/video/ssd1289fb.txt | 13 +
> arch/powerpc/boot/dts/p1025twr.dts | 95 +++++++
> arch/powerpc/boot/dts/p1025twr.dtsi | 280 +++++++++++++++++++++
> arch/powerpc/platforms/85xx/Kconfig | 6 +
> arch/powerpc/platforms/85xx/Makefile | 1 +
> arch/powerpc/platforms/85xx/twr_p102x.c | 147 +++++++++++
No mpc85xx_smp_defconfig update?
-Scott
^ permalink raw reply
* Re: [v2] powerpc 8xx: defconfig: slice by 4 is more efficient than the default slice by 8 on Powerpc 8xx.
From: Scott Wood @ 2014-01-08 1:12 UTC (permalink / raw)
To: LEROY Christophe; +Cc: Paul Mackerras, linuxppc-dev, linux-kernel
In-Reply-To: <20131122172829.CC8EE1A4DE7@localhost.localdomain>
On Fri, Nov 22, 2013 at 06:28:29PM +0100, LEROY Christophe wrote:
> On PPC_8xx, CRC32_SLICEBY4 is more efficient (almost twice) than CRC32_SLICEBY8,
> as shown below:
>
> With CRC32_SLICEBY8:
> [ 1.109204] crc32: CRC_LE_BITS = 64, CRC_BE BITS = 64
> [ 1.114401] crc32: self tests passed, processed 225944 bytes in 15118910 nsec
> [ 1.130655] crc32c: CRC_LE_BITS = 64
> [ 1.134235] crc32c: self tests passed, processed 225944 bytes in 4479879 nsec
>
> With CRC32_SLICEBY4:
> [ 1.097129] crc32: CRC_LE_BITS = 32, CRC_BE BITS = 32
> [ 1.101878] crc32: self tests passed, processed 225944 bytes in 8616242 nsec
> [ 1.116298] crc32c: CRC_LE_BITS = 32
> [ 1.119607] crc32c: self tests passed, processed 225944 bytes in 3289576 nsec
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
>
>
> diff -ur a/arch/powerpc/configs/adder875_defconfig b/arch/powerpc/configs.new/adder875_defconfig
> --- a/arch/powerpc/configs/adder875_defconfig 2013-11-22 18:20:10.342968268 +0100
> +++ b/arch/powerpc/configs.new/adder875_defconfig 2013-11-22 18:17:46.499686457 +0100
> @@ -70,3 +70,4 @@
> CONFIG_DETECT_HUNG_TASK=y
> CONFIG_DEBUG_INFO=y
> # CONFIG_RCU_CPU_STALL_DETECTOR is not set
> +CONFIG_CRC32_SLICEBY4=y
When applying I got this:
error: arch/powerpc/configs.new/adder875_defconfig: does not exist in index
error: arch/powerpc/configs.new/ep88xc_defconfig: does not exist in index
error: arch/powerpc/configs.new/mpc866_ads_defconfig: does not exist in index
error: arch/powerpc/configs.new/mpc885_ads_defconfig: does not exist in index
error: arch/powerpc/configs.new/tqm8xx_defconfig: does not exist in index
I've fixed it, but please ensure that patches can be applied using "git
am". I recommend using git to generate patches, but if you don't want to
do so be sure that it's the "b" filename, not the "a" filename, that
matches the tree.
-Scott
^ permalink raw reply
* Re: [v4] powerpc/85xx: Merge 85xx/p1023_defconfig into mpc85xx_smp_defconfig and mpc85xx_defconfig
From: Scott Wood @ 2014-01-08 1:04 UTC (permalink / raw)
To: Lijun Pan; +Cc: linuxppc-dev
In-Reply-To: <1384558100-32759-1-git-send-email-Lijun.Pan@freescale.com>
On Fri, Nov 15, 2013 at 05:28:20PM -0600, Lijun Pan wrote:
> mpc85xx_smp_defconfig and mpc85xx_defconfig already have CONFIG_P1023RDS=y.
> Merge CONFIG_P1023RDB=y and other relevant configurations into mpc85xx_smp_defconfig and mpc85_defconfig.
>
> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
I'll fix it when applying, but please keep commit messages wrapped to
around 70 characters, and keep subject lines even shorter.
-Scott
^ permalink raw reply
* Re: drivers/tty: ehv_bytechan fails to build as a module
From: Scott Wood @ 2014-01-08 1:21 UTC (permalink / raw)
To: Guenter Roeck
Cc: gregkh, dvaleev, paulus, Anton Blanchard, linuxppc-dev, timur
In-Reply-To: <20140104191537.GA9051@roeck-us.net>
On Sat, 2014-01-04 at 11:15 -0800, Guenter Roeck wrote:
> On Mon, Dec 09, 2013 at 04:03:10PM +1100, Anton Blanchard wrote:
> > ehv_bytechan is marked tristate but fails to build as a module:
> >
> > drivers/tty/ehv_bytechan.c:363:1: error: type defaults to ‘int’ in declaration of ‘console_initcall’ [-Werror=implicit-int]
> >
> > It doesn't make much sense for a console driver to be built as
> > a module, so change it to a bool.
> >
> > Signed-off-by: Anton Blanchard <anton@samba.org>
> >
>
> Any comments on this patch ? The problem still causes powerpc:allmodconfig to
> fail.
It's fine with me...
Greg, are you going to take this via tty.git or do you want it to go via
PPC?
-Scott
>
> Guenter
>
> > ---
> >
> >
> > Index: b/drivers/tty/Kconfig
> > ===================================================================
> > --- a/drivers/tty/Kconfig
> > +++ b/drivers/tty/Kconfig
> > @@ -366,7 +366,7 @@ config TRACE_SINK
> > "Trace data router for MIPI P1149.7 cJTAG standard".
> >
> > config PPC_EPAPR_HV_BYTECHAN
> > - tristate "ePAPR hypervisor byte channel driver"
> > + bool "ePAPR hypervisor byte channel driver"
> > depends on PPC
> > select EPAPR_PARAVIRT
> > help
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: drivers/tty: ehv_bytechan fails to build as a module
From: Greg KH @ 2014-01-08 1:29 UTC (permalink / raw)
To: Scott Wood
Cc: dvaleev, paulus, Anton Blanchard, linuxppc-dev, timur,
Guenter Roeck
In-Reply-To: <1389144063.8284.5.camel@snotra.buserror.net>
On Tue, Jan 07, 2014 at 07:21:03PM -0600, Scott Wood wrote:
> On Sat, 2014-01-04 at 11:15 -0800, Guenter Roeck wrote:
> > On Mon, Dec 09, 2013 at 04:03:10PM +1100, Anton Blanchard wrote:
> > > ehv_bytechan is marked tristate but fails to build as a module:
> > >
> > > drivers/tty/ehv_bytechan.c:363:1: error: type defaults to ‘int’ in declaration of ‘console_initcall’ [-Werror=implicit-int]
> > >
> > > It doesn't make much sense for a console driver to be built as
> > > a module, so change it to a bool.
> > >
> > > Signed-off-by: Anton Blanchard <anton@samba.org>
> > >
> >
> > Any comments on this patch ? The problem still causes powerpc:allmodconfig to
> > fail.
>
> It's fine with me...
>
> Greg, are you going to take this via tty.git or do you want it to go via
> PPC?
Feel free to take it through PPC.
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply
* Re: [PATCH 1/2] pci: Fix root port bus->self is NULL
From: Jiang Liu @ 2014-01-08 2:33 UTC (permalink / raw)
To: Dongsheng.Wang@freescale.com, Yijing Wang, bhelgaas@google.com,
rjw@rjwysocki.net
Cc: Scott Wood, linux-pci@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, galak@codeaurora.org
In-Reply-To: <80033eb36b0f40d682aeecc8b99dbd95@BN1PR03MB188.namprd03.prod.outlook.com>
On 2014/1/7 17:51, Dongsheng.Wang@freescale.com wrote:
>>>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index
>>>> 38e403d..7f2d1ab 100644
>>>> --- a/drivers/pci/probe.c
>>>> +++ b/drivers/pci/probe.c
>>>> @@ -1472,6 +1472,9 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
>>>> if (!dev->is_added)
>>>> nr++;
>>>>
>>>> + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
>>>> + bus->self = dev;
>>>
>>> In this case, bus is the pci root bus I think, so why set bus->self = root
>> port ?
>>> "bus->self" should pointer to the pci device that bridge out this bus.
>> Yes, this patch seems wrong. If dev is root port, bus should be root bus, so we
>> shouldn't set root_bus->self = pci_dev_of_root_port.
>>
> Why the root bus->self pointer to the bridge?
> If child bus create from root bus, the child->self will get the bridge(root port) pci device.
>
>> Actually PCI core has correctly setup pci_bus->self for secondary bus of PCIe
>> root port.
> Yes, right. But the root-bus->self is NULL. I think the root bus should get root port
> pci device for itself. If there is no bridge at board how to get the root port device?
Hi Dongsheng,
PCI root bus represents PCI host bridge, which has no
corresponding PCI device.
>
> -Dongsheng
>
>>
>> Thanks!
>> Gerry
>>
>
^ permalink raw reply
* Re: [v3, 3/7] powerpc: enable the relocatable support for the fsl booke 32bit kernel
From: Kevin Hao @ 2014-01-08 2:42 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc
In-Reply-To: <1389138364.11795.205.camel@snotra.buserror.net>
[-- Attachment #1: Type: text/plain, Size: 2940 bytes --]
On Tue, Jan 07, 2014 at 05:46:04PM -0600, Scott Wood wrote:
> On Sat, 2014-01-04 at 14:34 +0800, Kevin Hao wrote:
> > Actually there still have one limitation that we have to make sure
> > that the kernel and dtb are in the 64M memory mapped by the init tlb entry.
> > I booted the kernel successfully by using the following u-boot commands:
> > setenv fdt_high 0xffffffff
> > dhcp 6000000 128.224.162.196:/vlm-boards/p5020/uImage
> > tftp 6f00000 128.224.162.196:/vlm-boards/p5020/p5020ds.dtb
> > bootm 6000000 - 6f00000
>
> OK, that was it -- I hadn't set fdt_high and thus U-Boot was relocating
> the fdt under 64M.
>
> We should probably be using ioremap_prot() (or some other mechanism) to
It is too early to use ioremap_prot() for this case.
> create a special mapping, rather than assuming the fdt is covered by the
> initial TLB entry. That doesn't need to happen as part of this
> patchset, of course, as it's not a new limitation.
In order to fix this limitation we would have to create a separate map for
the dtb if it is not covered by the init 64M tlb. I would like to give it
a try if I can get some time.
>
> > > I'm having a hard time following the logic here. What is PAGE_OFFSET -
> > > offset supposed to be? Why would we map anything belowe PAGE_OFFSET?
> >
> > No, we don't map the address below PAGE_OFFSET.
> > memstart_addr is the physical start address of RAM.
> > start is the kernel running physical address aligned with 64M.
> >
> > offset = memstart_addr - start
> >
> > So if memstart_addr < start, the offset is negative. The PAGE_OFFSET - offset
> > is the virtual start address we should use for the init 64M map. It's above
> > the PAGE_OFFSET instead of below.
>
> Oh. I think it'd be more readable to do "offset = start -
> memstart_addr" and add offset instead of subtracting it.
Yes, I agree. The reason that I use "offset = memstart_addr - start" is that
it seems "memstart_addr" is always greater than "start" when we are booting
a kdump kernel with a kernel option like "crashkernel=64M@80M". :-)
>
> Also, offset should be phys_addr_t -- even if you don't expect to
> support offsets greater than 4G on 32-bit, it's semantically the right
> type to use. Plus, "int" would break if this code were ever used with
> 64-bit.
I thought about using phy_addr_t for the "offset" originally but gave it up
for the following reasons:
* It will not be greater than 4G.
* We have to use the ugly #ifdef CONFIG_PHYS_64BIT in restore_to_as0().
* Need more registers for arguments for restore_to_as0().
Of course you can change it to phys_addr_t if you prefer.
Thanks,
Kevin
>
> If you're OK with these changes, I can fix it while applying.
>
> -Scott
>
>
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^ permalink raw reply
* [PATCH v3.6 01/19] net: freescale: remove unused compare_addr()
From: Ding Tianhong @ 2014-01-08 2:53 UTC (permalink / raw)
To: Li Yang, Netdev, linuxppc-dev, linux-kernel@vger.kernel.org
The function did not be used any more, so remove it.
Cc: Li Yang <leoli@freescale.com>
Cc: netdev@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
drivers/net/ethernet/freescale/ucc_geth.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/net/ethernet/freescale/ucc_geth.c b/drivers/net/ethernet/freescale/ucc_geth.c
index 5548b6d..72291a8 100644
--- a/drivers/net/ethernet/freescale/ucc_geth.c
+++ b/drivers/net/ethernet/freescale/ucc_geth.c
@@ -435,11 +435,6 @@ static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
QE_CR_PROTOCOL_ETHERNET, 0);
}
-static inline int compare_addr(u8 **addr1, u8 **addr2)
-{
- return memcmp(addr1, addr2, ETH_ALEN);
-}
-
#ifdef DEBUG
static void get_statistics(struct ucc_geth_private *ugeth,
struct ucc_geth_tx_firmware_statistics *
--
1.8.0
^ permalink raw reply related
* RE: [PATCH 1/2] pci: Fix root port bus->self is NULL
From: Dongsheng.Wang @ 2014-01-08 3:51 UTC (permalink / raw)
To: Jiang Liu, Yijing Wang, bhelgaas@google.com, rjw@rjwysocki.net
Cc: Scott Wood, linux-pci@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, galak@codeaurora.org
In-Reply-To: <52CCB8E9.6020501@linux.intel.com>
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ZSwgd2hpY2ggaGFzIG5vIGNvcnJlc3BvbmRpbmcgUENJDQo+IGRldmljZS4NCj4gDQpZZXMsIGFn
cmVlLiBJZiBtb3JlIHRoYW4gb25lIGJyaWRnZSBvbiB0aGUgcm9vdCBidXMsIHRoaXMgcGF0Y2gg
aXMgd3JvbmcuDQoNClRoYW5rcyBmb3IgeW91ciByZXZpZXcuIDopDQoNCi1Eb25nc2hlbmcNCg0K
PiA+DQo+ID4gLURvbmdzaGVuZw0KPiA+DQo+ID4+DQo+ID4+IFRoYW5rcyENCj4gPj4gR2VycnkN
Cj4gPj4NCj4gPg0KPiANCg0K
^ permalink raw reply
* Re: [PATCH] powerpc: Fix alignment of secondary cpu spin vars
From: Michael Ellerman @ 2014-01-08 4:09 UTC (permalink / raw)
To: Olof Johansson
Cc: linuxppc-dev, linux-kernel@vger.kernel.org, Anton Blanchard,
chzigotzky
In-Reply-To: <20140103081219.GA10233@quad.lixom.net>
On Fri, 2014-01-03 at 00:12 -0800, Olof Johansson wrote:
> On Thu, Jan 02, 2014 at 11:56:04PM -0800, Olof Johansson wrote:
>
> > This makes things interesting though. The BE/LE trampoline code
> > assumes at least 3 consecutive instructions. What was the reasoning
> > behind entering the kernel LE instead of keeping the old boot protocol
> > and just switching to LE once kernel is loaded? Is it actually used on
> > some platforms or is this just a theoretical thing?
>
> Actually, adding a little hack that zeroes out the memory once we're done
> executing it will work just fine too. I know this is sort of icky, but maybe
> it'll be good enough for now?
>
> Of course, main worry is that this is just hiding some latent NULL deref in
> the kernel now... :-/
Wow, that would have to come close to winning the grossest-hack-in-arch-powerpc
award :)
Have you tried changing the value at 8 to point to a reserved page?
Some other possibilities:
* Change the #define so FIXUP_ENDIAN is empty for PASEMI, that would mean
you'd only be able to boot pasemi_defconfig.
* Move the hack into FIXUP_ENDIAN
cheers
^ permalink raw reply
* Re: [PATCH] powerpc: add vr save/restore functions
From: Michael Ellerman @ 2014-01-08 4:18 UTC (permalink / raw)
To: Andreas Schwab; +Cc: linuxppc-dev
In-Reply-To: <87eh4uif62.fsf@igel.home>
On Mon, 2013-12-30 at 15:31 +0100, Andreas Schwab wrote:
> GCC 4.8 now generates out-of-line vr save/restore functions when
> optimizing for size. They are needed for the raid6 altivec support.
It looks like they're identical for 32 & 64-bit ? If so can't we arrange to
have a single version?
cheers
^ permalink raw reply
* Re: [PATCH] powerpc: Fix alignment of secondary cpu spin vars
From: Benjamin Herrenschmidt @ 2014-01-08 4:18 UTC (permalink / raw)
To: Michael Ellerman
Cc: Olof Johansson, linuxppc-dev, linux-kernel@vger.kernel.org,
Anton Blanchard, chzigotzky
In-Reply-To: <1389154189.2076.5.camel@concordia>
On Wed, 2014-01-08 at 15:09 +1100, Michael Ellerman wrote:
> > Of course, main worry is that this is just hiding some latent NULL
> deref in
> > the kernel now... :-/
>
> Wow, that would have to come close to winning the
> grossest-hack-in-arch-powerpc
> award :)
>
> Have you tried changing the value at 8 to point to a reserved page?
>
> Some other possibilities:
>
> * Change the #define so FIXUP_ENDIAN is empty for PASEMI, that would
> mean
> you'd only be able to boot pasemi_defconfig.
> * Move the hack into FIXUP_ENDIAN
We actually found the root cause on irc the other day, I was waiting for
Olof to send a fix :-)
Olof: Can you try this totally untested patch ?
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -1986,8 +1986,6 @@ static void __init prom_init_stdout(void)
/* Get the full OF pathname of the stdout device */
memset(path, 0, 256);
call_prom("instance-to-path", 3, 1, prom.stdout, path, 255);
- stdout_node = call_prom("instance-to-package", 1, 1, prom.stdout);
- val = cpu_to_be32(stdout_node);
prom_setprop(prom.chosen, "/chosen", "linux,stdout-package",
&val, sizeof(val));
prom_printf("OF stdout device is: %s\n", of_stdout_device);
@@ -1995,10 +1993,14 @@ static void __init prom_init_stdout(void)
path, strlen(path) + 1);
/* If it's a display, note it */
- memset(type, 0, sizeof(type));
- prom_getprop(stdout_node, "device_type", type, sizeof(type));
- if (strcmp(type, "display") == 0)
- prom_setprop(stdout_node, path, "linux,boot-display", NULL, 0);
+ stdout_node = call_prom("instance-to-package", 1, 1, prom.stdout);
+ if (stdout_node != PROM_ERROR) {
+ val = cpu_to_be32(stdout_node);
+ memset(type, 0, sizeof(type));
+ prom_getprop(stdout_node, "device_type", type, sizeof(type));
+ if (strcmp(type, "display") == 0)
+ prom_setprop(stdout_node, path, "linux,boot-display", NU
+ }
}
^ permalink raw reply
* [PATCH 02/12][v4] pci: fsl: add structure fsl_pci
From: Minghuan Lian @ 2014-01-08 5:01 UTC (permalink / raw)
To: linuxppc-dev
Cc: Minghuan Lian, linux-pci, Zang Roy-R61911, Bjorn Helgaas,
Scott Wood
In-Reply-To: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com>
PowerPC uses structure pci_controller to describe PCI controller,
but ARM uses structure pci_sys_data. In order to support PowerPC
and ARM simultaneously, the patch adds a structure fsl_pci that
contains most of the members of the pci_controller and pci_sys_data.
Meanwhile, it defines a interface fsl_arch_sys_to_pci() which should
be implemented in architecture-specific PCI controller driver to
convert pci_controller or pci_sys_data to fsl_pci.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v4:
Added indirect type macro
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
include/linux/fsl/pci-common.h | 48 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h
index 5e4f683..7ea20a1 100644
--- a/include/linux/fsl/pci-common.h
+++ b/include/linux/fsl/pci-common.h
@@ -102,5 +102,53 @@ struct ccsr_pci {
};
+/*
+ * Structure of a PCI controller (host bridge)
+ */
+struct fsl_pci {
+ struct list_head node;
+ bool is_pcie;
+ struct device_node *dn;
+ struct device *dev;
+
+ int first_busno;
+ int last_busno;
+ int self_busno;
+ struct resource busn;
+
+ struct pci_ops *ops;
+ struct ccsr_pci __iomem *regs;
+
+#define INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
+#define INDIRECT_TYPE_EXT_REG 0x00000002
+#define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
+#define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
+#define INDIRECT_TYPE_BIG_ENDIAN 0x00000010
+#define INDIRECT_TYPE_BROKEN_MRM 0x00000020
+#define INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
+ u32 indirect_type;
+
+ struct resource io_resource;
+ resource_size_t io_base_phys;
+ resource_size_t pci_io_size;
+
+ struct resource mem_resources[3];
+ resource_size_t mem_offset[3];
+
+ int global_number; /* PCI domain number */
+
+ resource_size_t dma_window_base_cur;
+ resource_size_t dma_window_size;
+
+ void *sys;
+};
+
+/*
+ * Convert architecture specific pci controller structure to fsl_pci
+ * PowerPC uses structure pci_controller and ARM uses structure pci_sys_data
+ * to describe pci controller.
+ */
+extern struct fsl_pci *fsl_arch_sys_to_pci(void *sys);
+
#endif /* __PCI_COMMON_H */
#endif /* __KERNEL__ */
--
1.8.1.2
^ permalink raw reply related
* [PATCH 03/12][v4] pci: fsl: add PCI indirect access support
From: Minghuan Lian @ 2014-01-08 5:01 UTC (permalink / raw)
To: linuxppc-dev
Cc: Minghuan Lian, linux-pci, Zang Roy-R61911, Bjorn Helgaas,
Scott Wood
In-Reply-To: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com>
The patch adds PCI indirect read/write functions. The main code
is ported from arch/powerpc/sysdev/indirect_pci.c. We use general
IO API iowrite32be/ioread32be instead of out_be32/in_be32, and
use structure fsl_Pci instead of PowerPC's pci_controller.
The patch also provides fsl_pcie_check_link() to check PCI link.
The weak function fsl_arch_pci_exclude_device() is provided to
call ppc_md.pci_exclude_device() for PowerPC architecture.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v4:
moved indirect type macro to header file
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
drivers/pci/host/pci-fsl-common.c | 163 ++++++++++++++++++++++++++++++++------
include/linux/fsl/pci-common.h | 6 ++
2 files changed, 145 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/host/pci-fsl-common.c b/drivers/pci/host/pci-fsl-common.c
index 69d338b..d1846ee 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -35,52 +35,167 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
-static int fsl_pcie_check_link(struct pci_controller *hose)
+
+int __weak fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int fsl_pci_read_config(struct fsl_pci *pci, int bus, int devfn,
+ int offset, int len, u32 *val)
+{
+ u32 bus_no, reg, data;
+
+ if (pci->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
+ if (bus != pci->first_busno)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (devfn != 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ if (fsl_arch_pci_exclude_device(pci, bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ bus_no = (bus == pci->first_busno) ? pci->self_busno : bus;
+
+ if (pci->indirect_type & INDIRECT_TYPE_EXT_REG)
+ reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
+ else
+ reg = offset & 0xfc;
+
+ if (pci->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
+ iowrite32be(0x80000000 | (bus_no << 16) | (devfn << 8) | reg,
+ &pci->regs->config_addr);
+ else
+ iowrite32(0x80000000 | (bus_no << 16) | (devfn << 8) | reg,
+ &pci->regs->config_addr);
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ data = ioread32(&pci->regs->config_data);
+ switch (len) {
+ case 1:
+ *val = (data >> (8 * (offset & 3))) & 0xff;
+ break;
+ case 2:
+ *val = (data >> (8 * (offset & 3))) & 0xffff;
+ break;
+ default:
+ *val = data;
+ break;
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int fsl_pci_write_config(struct fsl_pci *pci, int bus, int devfn,
+ int offset, int len, u32 val)
+{
+ void __iomem *cfg_data;
+ u32 bus_no, reg;
+
+ if (pci->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
+ if (bus != pci->first_busno)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (devfn != 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ if (fsl_arch_pci_exclude_device(pci, bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ bus_no = (bus == pci->first_busno) ?
+ pci->self_busno : bus;
+
+ if (pci->indirect_type & INDIRECT_TYPE_EXT_REG)
+ reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
+ else
+ reg = offset & 0xfc;
+
+ if (pci->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
+ iowrite32be(0x80000000 | (bus_no << 16) | (devfn << 8) | reg,
+ &pci->regs->config_addr);
+ else
+ iowrite32(0x80000000 | (bus_no << 16) | (devfn << 8) | reg,
+ &pci->regs->config_addr);
+
+ /* suppress setting of PCI_PRIMARY_BUS */
+ if (pci->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
+ if ((offset == PCI_PRIMARY_BUS) &&
+ (bus == pci->first_busno))
+ val &= 0xffffff00;
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ cfg_data = ((void *) &(pci->regs->config_data)) + (offset & 3);
+ switch (len) {
+ case 1:
+ iowrite8(val, cfg_data);
+ break;
+ case 2:
+ iowrite16(val, cfg_data);
+ break;
+ default:
+ iowrite32(val, cfg_data);
+ break;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+bool fsl_pci_check_link(struct fsl_pci *pci)
{
u32 val = 0;
- if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
- if (hose->ops->read == fsl_indirect_read_config) {
- struct pci_bus bus;
- bus.number = hose->first_busno;
- bus.sysdata = hose;
- bus.ops = hose->ops;
- indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
- } else
- early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
+ if (pci->indirect_type & INDIRECT_TYPE_FSL_CFG_REG_LINK) {
+ fsl_pci_read_config(pci, 0, 0, PCIE_LTSSM, 4, &val);
if (val < PCIE_LTSSM_L0)
- return 1;
+ return false;
} else {
- struct ccsr_pci __iomem *pci = hose->private_data;
/* for PCIe IP rev 3.0 or greater use CSR0 for link state */
- val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
+ val = (ioread32be(&pci->regs->pex_csr0) & PEX_CSR0_LTSSM_MASK)
>> PEX_CSR0_LTSSM_SHIFT;
if (val != PEX_CSR0_LTSSM_L0)
- return 1;
+ return false;
}
- return 0;
+ return true;
}
static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
int offset, int len, u32 *val)
{
- struct pci_controller *hose = pci_bus_to_host(bus);
+ struct fsl_pci *pci = fsl_arch_sys_to_pci(bus->sysdata);
+
+ if (!pci)
+ return PCIBIOS_DEVICE_NOT_FOUND;
- if (fsl_pcie_check_link(hose))
- hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+ if (fsl_pci_check_link(pci))
+ pci->indirect_type &= ~INDIRECT_TYPE_NO_PCIE_LINK;
else
- hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+ pci->indirect_type |= INDIRECT_TYPE_NO_PCIE_LINK;
- return indirect_read_config(bus, devfn, offset, len, val);
+ return fsl_pci_read_config(pci, bus->number, devfn, offset, len, val);
}
-#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
-
-static struct pci_ops fsl_indirect_pcie_ops =
+static int fsl_indirect_write_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 val)
{
+ struct fsl_pci *pci = fsl_arch_sys_to_pci(bus->sysdata);
+
+ if (!pci)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return fsl_pci_write_config(pci, bus->number, devfn,
+ offset, len, val);
+}
+
+static struct pci_ops fsl_indirect_pci_ops = {
.read = fsl_indirect_read_config,
- .write = indirect_write_config,
+ .write = fsl_indirect_write_config,
};
static int setup_one_atmu(struct ccsr_pci __iomem *pci,
diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h
index 7ea20a1..726f27b 100644
--- a/include/linux/fsl/pci-common.h
+++ b/include/linux/fsl/pci-common.h
@@ -150,5 +150,11 @@ struct fsl_pci {
*/
extern struct fsl_pci *fsl_arch_sys_to_pci(void *sys);
+/* Return link status true -> link, false -> no link */
+bool fsl_pci_check_link(struct fsl_pci *pci);
+
+/* To avoid touching specified devices */
+int fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn);
+
#endif /* __PCI_COMMON_H */
#endif /* __KERNEL__ */
--
1.8.1.2
^ permalink raw reply related
* [PATCH 04/12][v4] pci: fsl: add early PCI indirect access support
From: Minghuan Lian @ 2014-01-08 5:01 UTC (permalink / raw)
To: linuxppc-dev
Cc: Minghuan Lian, linux-pci, Zang Roy-R61911, Bjorn Helgaas,
Scott Wood
In-Reply-To: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com>
The driver needs to read/write PCI configuration very early, at
that time architecture-specific PCI controller structure and
PCI bus have not been created. The patch provides an interface
fsl_arch_fake_pci_bus which should be implemented in
architecture-specific PCI driver to fake a PCI controller structure
and PCI bus. Using the fake PCI controller and PCI bus, the patch
provides the early indirect read/write functions.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
drivers/pci/host/pci-fsl-common.c | 26 ++++++++++++++++++++++++++
include/linux/fsl/pci-common.h | 7 +++++++
2 files changed, 33 insertions(+)
diff --git a/drivers/pci/host/pci-fsl-common.c b/drivers/pci/host/pci-fsl-common.c
index d1846ee..a706100 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -198,6 +198,32 @@ static struct pci_ops fsl_indirect_pci_ops = {
.write = fsl_indirect_write_config,
};
+#define EARLY_FSL_PCI_OP(rw, size, type) \
+int early_fsl_##rw##_config_##size(struct fsl_pci *pci, int bus, \
+ int devfn, int offset, type value) \
+{ \
+ return pci_bus_##rw##_config_##size(fsl_arch_fake_pci_bus(pci, bus),\
+ devfn, offset, value); \
+}
+
+EARLY_FSL_PCI_OP(read, byte, u8 *)
+EARLY_FSL_PCI_OP(read, word, u16 *)
+EARLY_FSL_PCI_OP(read, dword, u32 *)
+EARLY_FSL_PCI_OP(write, byte, u8)
+EARLY_FSL_PCI_OP(write, word, u16)
+EARLY_FSL_PCI_OP(write, dword, u32)
+
+static int early_fsl_find_capability(struct fsl_pci *pci,
+ int busnr, int devfn, int cap)
+{
+ struct pci_bus *bus = fsl_arch_fake_pci_bus(pci, busnr);
+
+ if (!bus)
+ return 0;
+
+ return pci_bus_find_capability(bus, devfn, cap);
+}
+
static int setup_one_atmu(struct ccsr_pci __iomem *pci,
unsigned int index, const struct resource *res,
resource_size_t offset)
diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h
index 726f27b..fd6c497 100644
--- a/include/linux/fsl/pci-common.h
+++ b/include/linux/fsl/pci-common.h
@@ -156,5 +156,12 @@ bool fsl_pci_check_link(struct fsl_pci *pci);
/* To avoid touching specified devices */
int fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn);
+/*
+ * To fake a PCI bus
+ * it is called by early_fsl_*(), at that time the architecture-dependent
+ * pci controller and pci bus have not been created.
+ */
+extern struct pci_bus *fsl_arch_fake_pci_bus(struct fsl_pci *pci, int busnr);
+
#endif /* __PCI_COMMON_H */
#endif /* __KERNEL__ */
--
1.8.1.2
^ permalink raw reply related
* [PATCH 01/12][v4] pci: fsl: derive the common PCI driver to drivers/pci/host
From: Minghuan Lian @ 2014-01-08 5:01 UTC (permalink / raw)
To: linuxppc-dev
Cc: Minghuan Lian, linux-pci, Zang Roy-R61911, Bjorn Helgaas,
Scott Wood
The Freescale's Layerscape series processors will use ARM cores.
The LS1's PCIe controllers is the same as T4240's. So it's better
the PCIe controller driver can support PowerPC and ARM
simultaneously. This patch is for this purpose. It derives
the common functions from arch/powerpc/sysdev/fsl_pci.c to
drivers/pci/host/pci-fsl-common.c and leaves the architecture
specific functions which should be implemented in arch related files.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v2-v4:
no change
v1-v2:
1. rename pci.h to pci-common.h
2. rename pci-fsl.c to pci-fsl-common.c
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/sysdev/fsl_pci.c | 521 +-----------------
arch/powerpc/sysdev/fsl_pci.h | 89 ----
.../fsl_pci.c => drivers/pci/host/pci-fsl-common.c | 592 +--------------------
.../fsl_pci.h => include/linux/fsl/pci-common.h | 45 +-
4 files changed, 7 insertions(+), 1240 deletions(-)
copy arch/powerpc/sysdev/fsl_pci.c => drivers/pci/host/pci-fsl-common.c (54%)
copy arch/powerpc/sysdev/fsl_pci.h => include/linux/fsl/pci-common.h (79%)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4dfd61d..0764385 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -27,6 +27,7 @@
#include <linux/log2.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
+#include <linux/fsl/pci-common.h>
#include <asm/io.h>
#include <asm/prom.h>
@@ -58,57 +59,8 @@ static void quirk_fsl_pcie_early(struct pci_dev *dev)
return;
}
-static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
- int, int, u32 *);
-
-static int fsl_pcie_check_link(struct pci_controller *hose)
-{
- u32 val = 0;
-
- if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
- if (hose->ops->read == fsl_indirect_read_config) {
- struct pci_bus bus;
- bus.number = hose->first_busno;
- bus.sysdata = hose;
- bus.ops = hose->ops;
- indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
- } else
- early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
- if (val < PCIE_LTSSM_L0)
- return 1;
- } else {
- struct ccsr_pci __iomem *pci = hose->private_data;
- /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
- val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
- >> PEX_CSR0_LTSSM_SHIFT;
- if (val != PEX_CSR0_LTSSM_L0)
- return 1;
- }
-
- return 0;
-}
-
-static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
- int offset, int len, u32 *val)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
-
- if (fsl_pcie_check_link(hose))
- hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
- else
- hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
-
- return indirect_read_config(bus, devfn, offset, len, val);
-}
-
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
-static struct pci_ops fsl_indirect_pcie_ops =
-{
- .read = fsl_indirect_read_config,
- .write = indirect_write_config,
-};
-
#define MAX_PHYS_ADDR_BITS 40
static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
@@ -132,291 +84,6 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
return 0;
}
-static int setup_one_atmu(struct ccsr_pci __iomem *pci,
- unsigned int index, const struct resource *res,
- resource_size_t offset)
-{
- resource_size_t pci_addr = res->start - offset;
- resource_size_t phys_addr = res->start;
- resource_size_t size = resource_size(res);
- u32 flags = 0x80044000; /* enable & mem R/W */
- unsigned int i;
-
- pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
- (u64)res->start, (u64)size);
-
- if (res->flags & IORESOURCE_PREFETCH)
- flags |= 0x10000000; /* enable relaxed ordering */
-
- for (i = 0; size > 0; i++) {
- unsigned int bits = min(ilog2(size),
- __ffs(pci_addr | phys_addr));
-
- if (index + i >= 5)
- return -1;
-
- out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
- out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
- out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
- out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
-
- pci_addr += (resource_size_t)1U << bits;
- phys_addr += (resource_size_t)1U << bits;
- size -= (resource_size_t)1U << bits;
- }
-
- return i;
-}
-
-/* atmu setup for fsl pci/pcie controller */
-static void setup_pci_atmu(struct pci_controller *hose)
-{
- struct ccsr_pci __iomem *pci = hose->private_data;
- int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
- u64 mem, sz, paddr_hi = 0;
- u64 offset = 0, paddr_lo = ULLONG_MAX;
- u32 pcicsrbar = 0, pcicsrbar_sz;
- u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
- const char *name = hose->dn->full_name;
- const u64 *reg;
- int len;
-
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
- win_idx = 2;
- start_idx = 0;
- end_idx = 3;
- }
- }
-
- /* Disable all windows (except powar0 since it's ignored) */
- for(i = 1; i < 5; i++)
- out_be32(&pci->pow[i].powar, 0);
- for (i = start_idx; i < end_idx; i++)
- out_be32(&pci->piw[i].piwar, 0);
-
- /* Setup outbound MEM window */
- for(i = 0, j = 1; i < 3; i++) {
- if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
- continue;
-
- paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
- paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
-
- /* We assume all memory resources have the same offset */
- offset = hose->mem_offset[i];
- n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
-
- if (n < 0 || j >= 5) {
- pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
- hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
- } else
- j += n;
- }
-
- /* Setup outbound IO window */
- if (hose->io_resource.flags & IORESOURCE_IO) {
- if (j >= 5) {
- pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
- } else {
- pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
- "phy base 0x%016llx.\n",
- (u64)hose->io_resource.start,
- (u64)resource_size(&hose->io_resource),
- (u64)hose->io_base_phys);
- out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
- out_be32(&pci->pow[j].potear, 0);
- out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
- /* Enable, IO R/W */
- out_be32(&pci->pow[j].powar, 0x80088000
- | (ilog2(hose->io_resource.end
- - hose->io_resource.start + 1) - 1));
- }
- }
-
- /* convert to pci address space */
- paddr_hi -= offset;
- paddr_lo -= offset;
-
- if (paddr_hi == paddr_lo) {
- pr_err("%s: No outbound window space\n", name);
- return;
- }
-
- if (paddr_lo == 0) {
- pr_err("%s: No space for inbound window\n", name);
- return;
- }
-
- /* setup PCSRBAR/PEXCSRBAR */
- early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
- early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
- pcicsrbar_sz = ~pcicsrbar_sz + 1;
-
- if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
- (paddr_lo > 0x100000000ull))
- pcicsrbar = 0x100000000ull - pcicsrbar_sz;
- else
- pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
- early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
-
- paddr_lo = min(paddr_lo, (u64)pcicsrbar);
-
- pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
-
- /* Setup inbound mem window */
- mem = memblock_end_of_DRAM();
-
- /*
- * The msi-address-64 property, if it exists, indicates the physical
- * address of the MSIIR register. Normally, this register is located
- * inside CCSR, so the ATMU that covers all of CCSR is used. But if
- * this property exists, then we normally need to create a new ATMU
- * for it. For now, however, we cheat. The only entity that creates
- * this property is the Freescale hypervisor, and the address is
- * specified in the partition configuration. Typically, the address
- * is located in the page immediately after the end of DDR. If so, we
- * can avoid allocating a new ATMU by extending the DDR ATMU by one
- * page.
- */
- reg = of_get_property(hose->dn, "msi-address-64", &len);
- if (reg && (len == sizeof(u64))) {
- u64 address = be64_to_cpup(reg);
-
- if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
- pr_info("%s: extending DDR ATMU to cover MSIIR", name);
- mem += PAGE_SIZE;
- } else {
- /* TODO: Create a new ATMU for MSIIR */
- pr_warn("%s: msi-address-64 address of %llx is "
- "unsupported\n", name, address);
- }
- }
-
- sz = min(mem, paddr_lo);
- mem_log = ilog2(sz);
-
- /* PCIe can overmap inbound & outbound since RX & TX are separated */
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- /* Size window to exact size if power-of-two or one size up */
- if ((1ull << mem_log) != mem) {
- mem_log++;
- if ((1ull << mem_log) > mem)
- pr_info("%s: Setting PCI inbound window "
- "greater than memory size\n", name);
- }
-
- piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
-
- /* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwar, piwar);
- win_idx--;
-
- hose->dma_window_base_cur = 0x00000000;
- hose->dma_window_size = (resource_size_t)sz;
-
- /*
- * if we have >4G of memory setup second PCI inbound window to
- * let devices that are 64-bit address capable to work w/o
- * SWIOTLB and access the full range of memory
- */
- if (sz != mem) {
- mem_log = ilog2(mem);
-
- /* Size window up if we dont fit in exact power-of-2 */
- if ((1ull << mem_log) != mem)
- mem_log++;
-
- piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
-
- /* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwbear,
- pci64_dma_offset >> 44);
- out_be32(&pci->piw[win_idx].piwbar,
- pci64_dma_offset >> 12);
- out_be32(&pci->piw[win_idx].piwar, piwar);
-
- /*
- * install our own dma_set_mask handler to fixup dma_ops
- * and dma_offset
- */
- ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
-
- pr_info("%s: Setup 64-bit PCI DMA window\n", name);
- }
- } else {
- u64 paddr = 0;
-
- /* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
- win_idx--;
-
- paddr += 1ull << mem_log;
- sz -= 1ull << mem_log;
-
- if (sz) {
- mem_log = ilog2(sz);
- piwar |= (mem_log - 1);
-
- out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwar, piwar);
- win_idx--;
-
- paddr += 1ull << mem_log;
- }
-
- hose->dma_window_base_cur = 0x00000000;
- hose->dma_window_size = (resource_size_t)paddr;
- }
-
- if (hose->dma_window_size < mem) {
-#ifdef CONFIG_SWIOTLB
- ppc_swiotlb_enable = 1;
-#else
- pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
- "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
- name);
-#endif
- /* adjusting outbound windows could reclaim space in mem map */
- if (paddr_hi < 0xffffffffull)
- pr_warning("%s: WARNING: Outbound window cfg leaves "
- "gaps in memory map. Adjusting the memory map "
- "could reduce unnecessary bounce buffering.\n",
- name);
-
- pr_info("%s: DMA window size is 0x%llx\n", name,
- (u64)hose->dma_window_size);
- }
-}
-
-static void __init setup_pci_cmd(struct pci_controller *hose)
-{
- u16 cmd;
- int cap_x;
-
- early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
- | PCI_COMMAND_IO;
- early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
-
- cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
- if (cap_x) {
- int pci_x_cmd = cap_x + PCI_X_CMD;
- cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
- | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
- } else {
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
- }
-}
-
void fsl_pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_controller *hose = pci_bus_to_host(bus);
@@ -454,112 +121,6 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
}
}
-int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
-{
- int len;
- struct pci_controller *hose;
- struct resource rsrc;
- const int *bus_range;
- u8 hdr_type, progif;
- struct device_node *dev;
- struct ccsr_pci __iomem *pci;
-
- dev = pdev->dev.of_node;
-
- if (!of_device_is_available(dev)) {
- pr_warning("%s: disabled\n", dev->full_name);
- return -ENODEV;
- }
-
- pr_debug("Adding PCI host bridge %s\n", dev->full_name);
-
- /* Fetch host bridge registers address */
- if (of_address_to_resource(dev, 0, &rsrc)) {
- printk(KERN_WARNING "Can't get pci register base!");
- return -ENOMEM;
- }
-
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int))
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
-
- pci_add_flags(PCI_REASSIGN_ALL_BUS);
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
-
- /* set platform device as the parent */
- hose->parent = &pdev->dev;
- hose->first_busno = bus_range ? bus_range[0] : 0x0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
-
- pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
- (u64)rsrc.start, (u64)resource_size(&rsrc));
-
- pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
- if (!hose->private_data)
- goto no_bridge;
-
- setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
- PPC_INDIRECT_TYPE_BIG_ENDIAN);
-
- if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
- hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
-
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- /* use fsl_indirect_read_config for PCIe */
- hose->ops = &fsl_indirect_pcie_ops;
- /* For PCIE read HEADER_TYPE to identify controler mode */
- early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
- if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
- goto no_bridge;
-
- } else {
- /* For PCI read PROG to identify controller mode */
- early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
- if ((progif & 1) == 1)
- goto no_bridge;
- }
-
- setup_pci_cmd(hose);
-
- /* check PCI express link status */
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
- PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
- if (fsl_pcie_check_link(hose))
- hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
- }
-
- printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long long)rsrc.start, hose->first_busno,
- hose->last_busno);
-
- pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, is_primary);
-
- /* Setup PEX window registers */
- setup_pci_atmu(hose);
-
- return 0;
-
-no_bridge:
- iounmap(hose->private_data);
- /* unmap cfg_data & cfg_addr separately if not on same page */
- if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
- ((unsigned long)hose->cfg_addr & PAGE_MASK))
- iounmap(hose->cfg_data);
- iounmap(hose->cfg_addr);
- pcibios_free_controller(hose);
- return -ENODEV;
-}
#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
@@ -1030,26 +591,6 @@ int fsl_pci_mcheck_exception(struct pt_regs *regs)
#endif
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
-static const struct of_device_id pci_ids[] = {
- { .compatible = "fsl,mpc8540-pci", },
- { .compatible = "fsl,mpc8548-pcie", },
- { .compatible = "fsl,mpc8610-pci", },
- { .compatible = "fsl,mpc8641-pcie", },
- { .compatible = "fsl,qoriq-pcie-v2.1", },
- { .compatible = "fsl,qoriq-pcie-v2.2", },
- { .compatible = "fsl,qoriq-pcie-v2.3", },
- { .compatible = "fsl,qoriq-pcie-v2.4", },
- { .compatible = "fsl,qoriq-pcie-v3.0", },
-
- /*
- * The following entries are for compatibility with older device
- * trees.
- */
- { .compatible = "fsl,p1022-pcie", },
- { .compatible = "fsl,p4080-pcie", },
-
- {},
-};
struct device_node *fsl_pci_primary;
@@ -1084,64 +625,4 @@ void fsl_pci_assign_primary(void)
}
}
}
-
-static int fsl_pci_probe(struct platform_device *pdev)
-{
- int ret;
- struct device_node *node;
-
- node = pdev->dev.of_node;
- ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
-
- mpc85xx_pci_err_probe(pdev);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int fsl_pci_resume(struct device *dev)
-{
- struct pci_controller *hose;
- struct resource pci_rsrc;
-
- hose = pci_find_hose_for_OF_device(dev->of_node);
- if (!hose)
- return -ENODEV;
-
- if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
- dev_err(dev, "Get pci register base failed.");
- return -ENODEV;
- }
-
- setup_pci_atmu(hose);
-
- return 0;
-}
-
-static const struct dev_pm_ops pci_pm_ops = {
- .resume = fsl_pci_resume,
-};
-
-#define PCI_PM_OPS (&pci_pm_ops)
-
-#else
-
-#define PCI_PM_OPS NULL
-
-#endif
-
-static struct platform_driver fsl_pci_driver = {
- .driver = {
- .name = "fsl-pci",
- .pm = PCI_PM_OPS,
- .of_match_table = pci_ids,
- },
- .probe = fsl_pci_probe,
-};
-
-static int __init fsl_pci_init(void)
-{
- return platform_driver_register(&fsl_pci_driver);
-}
-arch_initcall(fsl_pci_init);
#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index 8d455df..ce77aad 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -21,95 +21,6 @@ struct platform_device;
#define PCI_FSL_BRR1 0xbf8
#define PCI_FSL_BRR1_VER 0xffff
-#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
-#define PCIE_LTSSM_L0 0x16 /* L0 state */
-#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
-#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
-#define PIWAR_EN 0x80000000 /* Enable */
-#define PIWAR_PF 0x20000000 /* prefetch */
-#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
-#define PIWAR_READ_SNOOP 0x00050000
-#define PIWAR_WRITE_SNOOP 0x00005000
-#define PIWAR_SZ_MASK 0x0000003f
-
-/* PCI/PCI Express outbound window reg */
-struct pci_outbound_window_regs {
- __be32 potar; /* 0x.0 - Outbound translation address register */
- __be32 potear; /* 0x.4 - Outbound translation extended address register */
- __be32 powbar; /* 0x.8 - Outbound window base address register */
- u8 res1[4];
- __be32 powar; /* 0x.10 - Outbound window attributes register */
- u8 res2[12];
-};
-
-/* PCI/PCI Express inbound window reg */
-struct pci_inbound_window_regs {
- __be32 pitar; /* 0x.0 - Inbound translation address register */
- u8 res1[4];
- __be32 piwbar; /* 0x.8 - Inbound window base address register */
- __be32 piwbear; /* 0x.c - Inbound window base extended address register */
- __be32 piwar; /* 0x.10 - Inbound window attributes register */
- u8 res2[12];
-};
-
-/* PCI/PCI Express IO block registers for 85xx/86xx */
-struct ccsr_pci {
- __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
- __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
- __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
- __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
- __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
- __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
- __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
- u8 res2[4];
- __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
- __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
- __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
- __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
- u8 res3[3016];
- __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
- __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
-
-/* PCI/PCI Express outbound window 0-4
- * Window 0 is the default window and is the only window enabled upon reset.
- * The default outbound register set is used when a transaction misses
- * in all of the other outbound windows.
- */
- struct pci_outbound_window_regs pow[5];
- u8 res14[96];
- struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
- u8 res6[96];
-/* PCI/PCI Express inbound window 3-0
- * inbound window 1 supports only a 32-bit base address and does not
- * define an inbound window base extended address register.
- */
- struct pci_inbound_window_regs piw[4];
-
- __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
- u8 res21[4];
- __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
- u8 res22[4];
- __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
- u8 res23[12];
- __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
- u8 res24[4];
- __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
- __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
- __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
- __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
- u8 res_e38[200];
- __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
- u8 res_f04[16];
- __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
-#define PEX_CSR0_LTSSM_MASK 0xFC
-#define PEX_CSR0_LTSSM_SHIFT 2
-#define PEX_CSR0_LTSSM_L0 0x11
- __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
- u8 res_f1c[228];
-
-};
-
-extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
u64 fsl_pci_immrbar_base(struct pci_controller *hose);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/drivers/pci/host/pci-fsl-common.c
similarity index 54%
copy from arch/powerpc/sysdev/fsl_pci.c
copy to drivers/pci/host/pci-fsl-common.c
index 4dfd61d..69d338b 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -1,5 +1,5 @@
/*
- * MPC83xx/85xx/86xx PCI/PCIE support routing.
+ * 85xx/86xx/LS PCI/PCIE support routing.
*
* Copyright 2007-2012 Freescale Semiconductor, Inc.
* Copyright 2008-2009 MontaVista Software, Inc.
@@ -8,9 +8,6 @@
* Recode: ZHANG WEI <wei.zhang@freescale.com>
* Rewrite the routing for Frescale PCI and PCI Express
* Roy Zang <tie-fei.zang@freescale.com>
- * MPC83xx PCI-Express support:
- * Tony Li <tony.li@freescale.com>
- * Anton Vorontsov <avorontsov@ru.mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -38,29 +35,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
-static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
-
-static void quirk_fsl_pcie_early(struct pci_dev *dev)
-{
- u8 hdr_type;
-
- /* if we aren't a PCIe don't bother */
- if (!pci_is_pcie(dev))
- return;
-
- /* if we aren't in host mode don't bother */
- pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
- if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
- return;
-
- dev->class = PCI_CLASS_BRIDGE_PCI << 8;
- fsl_pcie_bus_fixup = 1;
- return;
-}
-
-static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
- int, int, u32 *);
-
static int fsl_pcie_check_link(struct pci_controller *hose)
{
u32 val = 0;
@@ -109,29 +83,6 @@ static struct pci_ops fsl_indirect_pcie_ops =
.write = indirect_write_config,
};
-#define MAX_PHYS_ADDR_BITS 40
-static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
-
-static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
-{
- if (!dev->dma_mask || !dma_supported(dev, dma_mask))
- return -EIO;
-
- /*
- * Fixup PCI devices that are able to DMA to above the physical
- * address width of the SoC such that we can address any internal
- * SoC address from across PCI if needed
- */
- if ((dev->bus == &pci_bus_type) &&
- dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
- set_dma_ops(dev, &dma_direct_ops);
- set_dma_offset(dev, pci64_dma_offset);
- }
-
- *dev->dma_mask = dma_mask;
- return 0;
-}
-
static int setup_one_atmu(struct ccsr_pci __iomem *pci,
unsigned int index, const struct resource *res,
resource_size_t offset)
@@ -417,43 +368,6 @@ static void __init setup_pci_cmd(struct pci_controller *hose)
}
}
-void fsl_pcibios_fixup_bus(struct pci_bus *bus)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
- int i, is_pcie = 0, no_link;
-
- /* The root complex bridge comes up with bogus resources,
- * we copy the PHB ones in.
- *
- * With the current generic PCI code, the PHB bus no longer
- * has bus->resource[0..4] set, so things are a bit more
- * tricky.
- */
-
- if (fsl_pcie_bus_fixup)
- is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
- no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
-
- if (bus->parent == hose->bus && (is_pcie || no_link)) {
- for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
- struct resource *res = bus->resource[i];
- struct resource *par;
-
- if (!res)
- continue;
- if (i == 0)
- par = &hose->io_resource;
- else if (i < 4)
- par = &hose->mem_resources[i-1];
- else par = NULL;
-
- res->start = par ? par->start : 0;
- res->end = par ? par->end : 0;
- res->flags = par ? par->flags : 0;
- }
- }
-}
-
int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
{
int len;
@@ -560,476 +474,7 @@ no_bridge:
pcibios_free_controller(hose);
return -ENODEV;
}
-#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
-
-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
- quirk_fsl_pcie_early);
-
-#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
-struct mpc83xx_pcie_priv {
- void __iomem *cfg_type0;
- void __iomem *cfg_type1;
- u32 dev_base;
-};
-
-struct pex_inbound_window {
- u32 ar;
- u32 tar;
- u32 barl;
- u32 barh;
-};
-
-/*
- * With the convention of u-boot, the PCIE outbound window 0 serves
- * as configuration transactions outbound.
- */
-#define PEX_OUTWIN0_BAR 0xCA4
-#define PEX_OUTWIN0_TAL 0xCA8
-#define PEX_OUTWIN0_TAH 0xCAC
-#define PEX_RC_INWIN_BASE 0xE60
-#define PEX_RCIWARn_EN 0x1
-
-static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
-
- if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
- return PCIBIOS_DEVICE_NOT_FOUND;
- /*
- * Workaround for the HW bug: for Type 0 configure transactions the
- * PCI-E controller does not check the device number bits and just
- * assumes that the device number bits are 0.
- */
- if (bus->number == hose->first_busno ||
- bus->primary == hose->first_busno) {
- if (devfn & 0xf8)
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- if (ppc_md.pci_exclude_device) {
- if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
- unsigned int devfn, int offset)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
- struct mpc83xx_pcie_priv *pcie = hose->dn->data;
- u32 dev_base = bus->number << 24 | devfn << 16;
- int ret;
-
- ret = mpc83xx_pcie_exclude_device(bus, devfn);
- if (ret)
- return NULL;
-
- offset &= 0xfff;
-
- /* Type 0 */
- if (bus->number == hose->first_busno)
- return pcie->cfg_type0 + offset;
-
- if (pcie->dev_base == dev_base)
- goto mapped;
-
- out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
-
- pcie->dev_base = dev_base;
-mapped:
- return pcie->cfg_type1 + offset;
-}
-
-static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
- int offset, int len, u32 *val)
-{
- void __iomem *cfg_addr;
-
- cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
- if (!cfg_addr)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- switch (len) {
- case 1:
- *val = in_8(cfg_addr);
- break;
- case 2:
- *val = in_le16(cfg_addr);
- break;
- default:
- *val = in_le32(cfg_addr);
- break;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
- int offset, int len, u32 val)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
- void __iomem *cfg_addr;
-
- cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
- if (!cfg_addr)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
- if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
- val &= 0xffffff00;
-
- switch (len) {
- case 1:
- out_8(cfg_addr, val);
- break;
- case 2:
- out_le16(cfg_addr, val);
- break;
- default:
- out_le32(cfg_addr, val);
- break;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops mpc83xx_pcie_ops = {
- .read = mpc83xx_pcie_read_config,
- .write = mpc83xx_pcie_write_config,
-};
-
-static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
- struct resource *reg)
-{
- struct mpc83xx_pcie_priv *pcie;
- u32 cfg_bar;
- int ret = -ENOMEM;
-
- pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
- if (!pcie)
- return ret;
-
- pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
- if (!pcie->cfg_type0)
- goto err0;
-
- cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
- if (!cfg_bar) {
- /* PCI-E isn't configured. */
- ret = -ENODEV;
- goto err1;
- }
-
- pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
- if (!pcie->cfg_type1)
- goto err1;
-
- WARN_ON(hose->dn->data);
- hose->dn->data = pcie;
- hose->ops = &mpc83xx_pcie_ops;
- hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
-
- out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
- out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
-
- if (fsl_pcie_check_link(hose))
- hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
-
- return 0;
-err1:
- iounmap(pcie->cfg_type0);
-err0:
- kfree(pcie);
- return ret;
-
-}
-
-int __init mpc83xx_add_bridge(struct device_node *dev)
-{
- int ret;
- int len;
- struct pci_controller *hose;
- struct resource rsrc_reg;
- struct resource rsrc_cfg;
- const int *bus_range;
- int primary;
-
- is_mpc83xx_pci = 1;
-
- if (!of_device_is_available(dev)) {
- pr_warning("%s: disabled by the firmware.\n",
- dev->full_name);
- return -ENODEV;
- }
- pr_debug("Adding PCI host bridge %s\n", dev->full_name);
-
- /* Fetch host bridge registers address */
- if (of_address_to_resource(dev, 0, &rsrc_reg)) {
- printk(KERN_WARNING "Can't get pci register base!\n");
- return -ENOMEM;
- }
-
- memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
-
- if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
- printk(KERN_WARNING
- "No pci config register base in dev tree, "
- "using default\n");
- /*
- * MPC83xx supports up to two host controllers
- * one at 0x8500 has config space registers at 0x8300
- * one at 0x8600 has config space registers at 0x8380
- */
- if ((rsrc_reg.start & 0xfffff) == 0x8500)
- rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
- else if ((rsrc_reg.start & 0xfffff) == 0x8600)
- rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
- }
- /*
- * Controller at offset 0x8500 is primary
- */
- if ((rsrc_reg.start & 0xfffff) == 0x8500)
- primary = 1;
- else
- primary = 0;
-
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int)) {
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
- }
-
- pci_add_flags(PCI_REASSIGN_ALL_BUS);
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
-
- hose->first_busno = bus_range ? bus_range[0] : 0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
-
- if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
- ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
- if (ret)
- goto err0;
- } else {
- setup_indirect_pci(hose, rsrc_cfg.start,
- rsrc_cfg.start + 4, 0);
- }
-
- printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long long)rsrc_reg.start, hose->first_busno,
- hose->last_busno);
-
- pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, primary);
-
- return 0;
-err0:
- pcibios_free_controller(hose);
- return ret;
-}
-#endif /* CONFIG_PPC_83xx */
-
-u64 fsl_pci_immrbar_base(struct pci_controller *hose)
-{
-#ifdef CONFIG_PPC_83xx
- if (is_mpc83xx_pci) {
- struct mpc83xx_pcie_priv *pcie = hose->dn->data;
- struct pex_inbound_window *in;
- int i;
-
- /* Walk the Root Complex Inbound windows to match IMMR base */
- in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
- for (i = 0; i < 4; i++) {
- /* not enabled, skip */
- if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
- continue;
-
- if (get_immrbase() == in_le32(&in[i].tar))
- return (u64)in_le32(&in[i].barh) << 32 |
- in_le32(&in[i].barl);
- }
-
- printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
- }
-#endif
-
-#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
- if (!is_mpc83xx_pci) {
- u32 base;
-
- pci_bus_read_config_dword(hose->bus,
- PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
- return base;
- }
-#endif
-
- return 0;
-}
-#ifdef CONFIG_E500
-static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
-{
- unsigned int rd, ra, rb, d;
-
- rd = get_rt(inst);
- ra = get_ra(inst);
- rb = get_rb(inst);
- d = get_d(inst);
-
- switch (get_op(inst)) {
- case 31:
- switch (get_xop(inst)) {
- case OP_31_XOP_LWZX:
- case OP_31_XOP_LWBRX:
- regs->gpr[rd] = 0xffffffff;
- break;
-
- case OP_31_XOP_LWZUX:
- regs->gpr[rd] = 0xffffffff;
- regs->gpr[ra] += regs->gpr[rb];
- break;
-
- case OP_31_XOP_LBZX:
- regs->gpr[rd] = 0xff;
- break;
-
- case OP_31_XOP_LBZUX:
- regs->gpr[rd] = 0xff;
- regs->gpr[ra] += regs->gpr[rb];
- break;
-
- case OP_31_XOP_LHZX:
- case OP_31_XOP_LHBRX:
- regs->gpr[rd] = 0xffff;
- break;
-
- case OP_31_XOP_LHZUX:
- regs->gpr[rd] = 0xffff;
- regs->gpr[ra] += regs->gpr[rb];
- break;
-
- case OP_31_XOP_LHAX:
- regs->gpr[rd] = ~0UL;
- break;
-
- case OP_31_XOP_LHAUX:
- regs->gpr[rd] = ~0UL;
- regs->gpr[ra] += regs->gpr[rb];
- break;
-
- default:
- return 0;
- }
- break;
-
- case OP_LWZ:
- regs->gpr[rd] = 0xffffffff;
- break;
-
- case OP_LWZU:
- regs->gpr[rd] = 0xffffffff;
- regs->gpr[ra] += (s16)d;
- break;
-
- case OP_LBZ:
- regs->gpr[rd] = 0xff;
- break;
-
- case OP_LBZU:
- regs->gpr[rd] = 0xff;
- regs->gpr[ra] += (s16)d;
- break;
-
- case OP_LHZ:
- regs->gpr[rd] = 0xffff;
- break;
-
- case OP_LHZU:
- regs->gpr[rd] = 0xffff;
- regs->gpr[ra] += (s16)d;
- break;
-
- case OP_LHA:
- regs->gpr[rd] = ~0UL;
- break;
-
- case OP_LHAU:
- regs->gpr[rd] = ~0UL;
- regs->gpr[ra] += (s16)d;
- break;
-
- default:
- return 0;
- }
-
- return 1;
-}
-
-static int is_in_pci_mem_space(phys_addr_t addr)
-{
- struct pci_controller *hose;
- struct resource *res;
- int i;
-
- list_for_each_entry(hose, &hose_list, list_node) {
- if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
- continue;
-
- for (i = 0; i < 3; i++) {
- res = &hose->mem_resources[i];
- if ((res->flags & IORESOURCE_MEM) &&
- addr >= res->start && addr <= res->end)
- return 1;
- }
- }
- return 0;
-}
-
-int fsl_pci_mcheck_exception(struct pt_regs *regs)
-{
- u32 inst;
- int ret;
- phys_addr_t addr = 0;
-
- /* Let KVM/QEMU deal with the exception */
- if (regs->msr & MSR_GS)
- return 0;
-
-#ifdef CONFIG_PHYS_64BIT
- addr = mfspr(SPRN_MCARU);
- addr <<= 32;
-#endif
- addr += mfspr(SPRN_MCAR);
-
- if (is_in_pci_mem_space(addr)) {
- if (user_mode(regs)) {
- pagefault_disable();
- ret = get_user(regs->nip, &inst);
- pagefault_enable();
- } else {
- ret = probe_kernel_address(regs->nip, inst);
- }
-
- if (mcheck_handle_load(regs, inst)) {
- regs->nip += 4;
- return 1;
- }
- }
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
static const struct of_device_id pci_ids[] = {
{ .compatible = "fsl,mpc8540-pci", },
{ .compatible = "fsl,mpc8548-pcie", },
@@ -1051,40 +496,6 @@ static const struct of_device_id pci_ids[] = {
{},
};
-struct device_node *fsl_pci_primary;
-
-void fsl_pci_assign_primary(void)
-{
- struct device_node *np;
-
- /* Callers can specify the primary bus using other means. */
- if (fsl_pci_primary)
- return;
-
- /* If a PCI host bridge contains an ISA node, it's primary. */
- np = of_find_node_by_type(NULL, "isa");
- while ((fsl_pci_primary = of_get_parent(np))) {
- of_node_put(np);
- np = fsl_pci_primary;
-
- if (of_match_node(pci_ids, np) && of_device_is_available(np))
- return;
- }
-
- /*
- * If there's no PCI host bridge with ISA, arbitrarily
- * designate one as primary. This can go away once
- * various bugs with primary-less systems are fixed.
- */
- for_each_matching_node(np, pci_ids) {
- if (of_device_is_available(np)) {
- fsl_pci_primary = np;
- of_node_put(np);
- return;
- }
- }
-}
-
static int fsl_pci_probe(struct platform_device *pdev)
{
int ret;
@@ -1144,4 +555,3 @@ static int __init fsl_pci_init(void)
return platform_driver_register(&fsl_pci_driver);
}
arch_initcall(fsl_pci_init);
-#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/include/linux/fsl/pci-common.h
similarity index 79%
copy from arch/powerpc/sysdev/fsl_pci.h
copy to include/linux/fsl/pci-common.h
index 8d455df..5e4f683 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/include/linux/fsl/pci-common.h
@@ -1,5 +1,5 @@
/*
- * MPC85xx/86xx PCI Express structure define
+ * MPC85xx/86xx/LS PCI Express structure define
*
* Copyright 2007,2011 Freescale Semiconductor, Inc
*
@@ -11,15 +11,8 @@
*/
#ifdef __KERNEL__
-#ifndef __POWERPC_FSL_PCI_H
-#define __POWERPC_FSL_PCI_H
-
-struct platform_device;
-
-
-/* FSL PCI controller BRR1 register */
-#define PCI_FSL_BRR1 0xbf8
-#define PCI_FSL_BRR1_VER 0xffff
+#ifndef __PCI_COMMON_H
+#define __PCI_COMMON_H
#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
#define PCIE_LTSSM_L0 0x16 /* L0 state */
@@ -52,7 +45,7 @@ struct pci_inbound_window_regs {
u8 res2[12];
};
-/* PCI/PCI Express IO block registers for 85xx/86xx */
+/* PCI/PCI Express IO block registers for 85xx/86xx/LS */
struct ccsr_pci {
__be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
__be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
@@ -109,33 +102,5 @@ struct ccsr_pci {
};
-extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
-extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
-extern int mpc83xx_add_bridge(struct device_node *dev);
-u64 fsl_pci_immrbar_base(struct pci_controller *hose);
-
-extern struct device_node *fsl_pci_primary;
-
-#ifdef CONFIG_PCI
-void fsl_pci_assign_primary(void);
-#else
-static inline void fsl_pci_assign_primary(void) {}
-#endif
-
-#ifdef CONFIG_EDAC_MPC85XX
-int mpc85xx_pci_err_probe(struct platform_device *op);
-#else
-static inline int mpc85xx_pci_err_probe(struct platform_device *op)
-{
- return -ENOTSUPP;
-}
-#endif
-
-#ifdef CONFIG_FSL_PCI
-extern int fsl_pci_mcheck_exception(struct pt_regs *);
-#else
-static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
-#endif
-
-#endif /* __POWERPC_FSL_PCI_H */
+#endif /* __PCI_COMMON_H */
#endif /* __KERNEL__ */
--
1.8.1.2
^ permalink raw reply related
* [PATCH 05/12][v4] pci: fsl: port PCI ATMU related code
From: Minghuan Lian @ 2014-01-08 5:01 UTC (permalink / raw)
To: linuxppc-dev
Cc: Minghuan Lian, linux-pci, Zang Roy-R61911, Bjorn Helgaas,
Scott Wood
In-Reply-To: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com>
The patch ports PCI ATMU related code, just uses general IO API
iowrite32be/ioread32be instead of out_be32/in_be32, uses structure
fsl_pci instead of PowerPC's pci_controller and uses dev_*()
instead of pr_*() to output the information.
The patch also provides the weak function
fsl_arch_pci64_dma_offset(), the architecture-specific driver may
return different offset.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
drivers/pci/host/pci-fsl-common.c | 190 ++++++++++++++++++++------------------
include/linux/fsl/pci-common.h | 3 +
2 files changed, 103 insertions(+), 90 deletions(-)
diff --git a/drivers/pci/host/pci-fsl-common.c b/drivers/pci/host/pci-fsl-common.c
index a706100..26ee4c3 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -35,6 +35,10 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
+u64 __weak fsl_arch_pci64_dma_offset(void)
+{
+ return 0;
+}
int __weak fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn)
{
@@ -225,8 +229,8 @@ static int early_fsl_find_capability(struct fsl_pci *pci,
}
static int setup_one_atmu(struct ccsr_pci __iomem *pci,
- unsigned int index, const struct resource *res,
- resource_size_t offset)
+ unsigned int index, const struct resource *res,
+ resource_size_t offset)
{
resource_size_t pci_addr = res->start - offset;
resource_size_t phys_addr = res->start;
@@ -247,10 +251,10 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
if (index + i >= 5)
return -1;
- out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
- out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
- out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
- out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
+ iowrite32be(pci_addr >> 12, &pci->pow[index + i].potar);
+ iowrite32be((u64)pci_addr >> 44, &pci->pow[index + i].potear);
+ iowrite32be(phys_addr >> 12, &pci->pow[index + i].powbar);
+ iowrite32be(flags | (bits - 1), &pci->pow[index + i].powar);
pci_addr += (resource_size_t)1U << bits;
phys_addr += (resource_size_t)1U << bits;
@@ -261,21 +265,19 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
}
/* atmu setup for fsl pci/pcie controller */
-static void setup_pci_atmu(struct pci_controller *hose)
+static void setup_pci_atmu(struct fsl_pci *pci)
{
- struct ccsr_pci __iomem *pci = hose->private_data;
int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
u64 mem, sz, paddr_hi = 0;
u64 offset = 0, paddr_lo = ULLONG_MAX;
u32 pcicsrbar = 0, pcicsrbar_sz;
u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
- const char *name = hose->dn->full_name;
const u64 *reg;
int len;
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
+ if (pci->is_pcie) {
+ if (in_be32(&pci->regs->block_rev1) >= PCIE_IP_REV_2_2) {
win_idx = 2;
start_idx = 0;
end_idx = 3;
@@ -283,47 +285,54 @@ static void setup_pci_atmu(struct pci_controller *hose)
}
/* Disable all windows (except powar0 since it's ignored) */
- for(i = 1; i < 5; i++)
- out_be32(&pci->pow[i].powar, 0);
+ for (i = 1; i < 5; i++)
+ iowrite32be(0, &pci->regs->pow[i].powar);
for (i = start_idx; i < end_idx; i++)
- out_be32(&pci->piw[i].piwar, 0);
+ iowrite32be(0, &pci->regs->piw[i].piwar);
/* Setup outbound MEM window */
- for(i = 0, j = 1; i < 3; i++) {
- if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
+ for (i = 0, j = 1; i < 3; i++) {
+ if (!(pci->mem_resources[i].flags & IORESOURCE_MEM))
continue;
- paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
- paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
+ paddr_lo = min_t(u64, paddr_lo, pci->mem_resources[i].start);
+ paddr_hi = max_t(u64, paddr_hi, pci->mem_resources[i].end);
/* We assume all memory resources have the same offset */
- offset = hose->mem_offset[i];
- n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
+ offset = pci->mem_offset[i];
+ n = setup_one_atmu(pci->regs, j, &pci->mem_resources[i],
+ offset);
if (n < 0 || j >= 5) {
- pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
- hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
+ dev_err(pci->dev,
+ "Ran out of outbound PCI ATMUs for resource %d!\n",
+ i);
+ pci->mem_resources[i].flags |= IORESOURCE_DISABLED;
} else
j += n;
}
/* Setup outbound IO window */
- if (hose->io_resource.flags & IORESOURCE_IO) {
- if (j >= 5) {
- pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
- } else {
- pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
- "phy base 0x%016llx.\n",
- (u64)hose->io_resource.start,
- (u64)resource_size(&hose->io_resource),
- (u64)hose->io_base_phys);
- out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
- out_be32(&pci->pow[j].potear, 0);
- out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
+ if (pci->io_resource.flags & IORESOURCE_IO) {
+ if (j >= 5)
+ dev_err(pci->dev,
+ "Ran out of outbound PCI ATMUs for IO resource\n");
+ else {
+ dev_dbg(pci->dev,
+ "PCI IO resource start 0x%016llx,"
+ "size 0x%016llx, phy base 0x%016llx.\n",
+ (u64)pci->io_resource.start,
+ (u64)resource_size(&pci->io_resource),
+ (u64)pci->io_base_phys);
+ iowrite32be(pci->io_resource.start >> 12,
+ &pci->regs->pow[j].potar);
+ iowrite32be(0, &pci->regs->pow[j].potear);
+ iowrite32be(pci->io_base_phys >> 12,
+ &pci->regs->pow[j].powbar);
/* Enable, IO R/W */
- out_be32(&pci->pow[j].powar, 0x80088000
- | (ilog2(hose->io_resource.end
- - hose->io_resource.start + 1) - 1));
+ iowrite32be(0x80088000 |
+ (ilog2(resource_size(&pci->io_resource)) - 1),
+ &pci->regs->pow[j].powar);
}
}
@@ -332,18 +341,20 @@ static void setup_pci_atmu(struct pci_controller *hose)
paddr_lo -= offset;
if (paddr_hi == paddr_lo) {
- pr_err("%s: No outbound window space\n", name);
+ dev_err(pci->dev, "No outbound window space\n");
return;
}
if (paddr_lo == 0) {
- pr_err("%s: No space for inbound window\n", name);
+ dev_err(pci->dev, "No space for inbound window\n");
return;
}
/* setup PCSRBAR/PEXCSRBAR */
- early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
- early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
+ early_fsl_write_config_dword(pci, 0, 0, PCI_BASE_ADDRESS_0,
+ 0xffffffff);
+ early_fsl_read_config_dword(pci, 0, 0, PCI_BASE_ADDRESS_0,
+ &pcicsrbar_sz);
pcicsrbar_sz = ~pcicsrbar_sz + 1;
if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
@@ -351,11 +362,12 @@ static void setup_pci_atmu(struct pci_controller *hose)
pcicsrbar = 0x100000000ull - pcicsrbar_sz;
else
pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
- early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
+ early_fsl_write_config_dword(pci, 0, 0, PCI_BASE_ADDRESS_0,
+ pcicsrbar);
- paddr_lo = min(paddr_lo, (u64)pcicsrbar);
+ paddr_lo = min_t(u64, paddr_lo, pcicsrbar);
- pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
+ dev_info(pci->dev, "PCICSRBAR @ 0x%x\n", pcicsrbar);
/* Setup inbound mem window */
mem = memblock_end_of_DRAM();
@@ -372,17 +384,19 @@ static void setup_pci_atmu(struct pci_controller *hose)
* can avoid allocating a new ATMU by extending the DDR ATMU by one
* page.
*/
- reg = of_get_property(hose->dn, "msi-address-64", &len);
+ reg = of_get_property(pci->dn, "msi-address-64", &len);
if (reg && (len == sizeof(u64))) {
u64 address = be64_to_cpup(reg);
if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
- pr_info("%s: extending DDR ATMU to cover MSIIR", name);
+ dev_info(pci->dev,
+ "extending DDR ATMU to cover MSIIR\n");
mem += PAGE_SIZE;
} else {
/* TODO: Create a new ATMU for MSIIR */
- pr_warn("%s: msi-address-64 address of %llx is "
- "unsupported\n", name, address);
+ dev_warn(pci->dev,
+ "msi-address-64 address of %llx is "
+ "unsupported\n", address);
}
}
@@ -390,25 +404,26 @@ static void setup_pci_atmu(struct pci_controller *hose)
mem_log = ilog2(sz);
/* PCIe can overmap inbound & outbound since RX & TX are separated */
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
+ if (pci->is_pcie) {
/* Size window to exact size if power-of-two or one size up */
if ((1ull << mem_log) != mem) {
mem_log++;
if ((1ull << mem_log) > mem)
- pr_info("%s: Setting PCI inbound window "
- "greater than memory size\n", name);
+ dev_info(pci->dev,
+ "Setting PCI inbound window "
+ "greater than memory size\n");
}
piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
/* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwar, piwar);
+ iowrite32be(0, &pci->regs->piw[win_idx].pitar);
+ iowrite32be(0, &pci->regs->piw[win_idx].piwbar);
+ iowrite32be(piwar, &pci->regs->piw[win_idx].piwar);
win_idx--;
- hose->dma_window_base_cur = 0x00000000;
- hose->dma_window_size = (resource_size_t)sz;
+ pci->dma_window_base_cur = 0x00000000;
+ pci->dma_window_size = (resource_size_t)sz;
/*
* if we have >4G of memory setup second PCI inbound window to
@@ -425,28 +440,22 @@ static void setup_pci_atmu(struct pci_controller *hose)
piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
/* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, 0x00000000);
- out_be32(&pci->piw[win_idx].piwbear,
- pci64_dma_offset >> 44);
- out_be32(&pci->piw[win_idx].piwbar,
- pci64_dma_offset >> 12);
- out_be32(&pci->piw[win_idx].piwar, piwar);
-
- /*
- * install our own dma_set_mask handler to fixup dma_ops
- * and dma_offset
- */
- ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
-
- pr_info("%s: Setup 64-bit PCI DMA window\n", name);
+ iowrite32be(0, &pci->regs->piw[win_idx].pitar);
+ iowrite32be(fsl_arch_pci64_dma_offset() >> 44,
+ &pci->regs->piw[win_idx].piwbear);
+ iowrite32be(fsl_arch_pci64_dma_offset() >> 12,
+ &pci->regs->piw[win_idx].piwbar);
+ iowrite32be(piwar,
+ &pci->regs->piw[win_idx].piwar);
}
} else {
u64 paddr = 0;
/* Setup inbound memory window */
- out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
+ iowrite32be(paddr >> 12, &pci->regs->piw[win_idx].pitar);
+ iowrite32be(paddr >> 12, &pci->regs->piw[win_idx].piwbar);
+ iowrite32be((piwar | (mem_log - 1)),
+ &pci->regs->piw[win_idx].piwar);
win_idx--;
paddr += 1ull << mem_log;
@@ -456,35 +465,36 @@ static void setup_pci_atmu(struct pci_controller *hose)
mem_log = ilog2(sz);
piwar |= (mem_log - 1);
- out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
- out_be32(&pci->piw[win_idx].piwar, piwar);
+ iowrite32be(paddr >> 12,
+ &pci->regs->piw[win_idx].pitar);
+ iowrite32be(paddr >> 12,
+ &pci->regs->piw[win_idx].piwbar);
+ iowrite32be(piwar,
+ &pci->regs->piw[win_idx].piwar);
win_idx--;
paddr += 1ull << mem_log;
}
- hose->dma_window_base_cur = 0x00000000;
- hose->dma_window_size = (resource_size_t)paddr;
+ pci->dma_window_base_cur = 0x00000000;
+ pci->dma_window_size = (resource_size_t)paddr;
}
- if (hose->dma_window_size < mem) {
-#ifdef CONFIG_SWIOTLB
- ppc_swiotlb_enable = 1;
-#else
- pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
- "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
- name);
+ if (pci->dma_window_size < mem) {
+#ifndef CONFIG_SWIOTLB
+ dev_err(pci->dev,
+ "Memory size exceeds PCI ATMU ability to "
+ "map - enable CONFIG_SWIOTLB to avoid dma errors.\n");
#endif
/* adjusting outbound windows could reclaim space in mem map */
if (paddr_hi < 0xffffffffull)
- pr_warning("%s: WARNING: Outbound window cfg leaves "
+ dev_warn(pci->dev,
+ "Outbound window cfg leaves "
"gaps in memory map. Adjusting the memory map "
- "could reduce unnecessary bounce buffering.\n",
- name);
+ "could reduce unnecessary bounce buffering.\n");
- pr_info("%s: DMA window size is 0x%llx\n", name,
- (u64)hose->dma_window_size);
+ dev_info(pci->dev, "DMA window size is 0x%llx\n",
+ (u64)pci->dma_window_size);
}
}
diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h
index fd6c497..02bcf5b 100644
--- a/include/linux/fsl/pci-common.h
+++ b/include/linux/fsl/pci-common.h
@@ -163,5 +163,8 @@ int fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn);
*/
extern struct pci_bus *fsl_arch_fake_pci_bus(struct fsl_pci *pci, int busnr);
+/* Return PCI64 DMA offset */
+u64 fsl_arch_pci64_dma_offset(void);
+
#endif /* __PCI_COMMON_H */
#endif /* __KERNEL__ */
--
1.8.1.2
^ permalink raw reply related
* [PATCH 07/12][v4] pci: fsl: port PCI platform driver
From: Minghuan Lian @ 2014-01-08 5:01 UTC (permalink / raw)
To: linuxppc-dev
Cc: Minghuan Lian, linux-pci, Zang Roy-R61911, Bjorn Helgaas,
Scott Wood
In-Reply-To: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com>
1. The patch ports FSL PCI platform driver. probe function
initialize fsl_pci and register it to architecture PCI system,
remove function removes fsl_pci from architecture PCI system.
fsl_arch_pci_sys_register() and fsl_arch_pci_sys_remove() should
be implemented in architecture-specific driver to provide
register/remove functionality.
2. Remove architecture-specific header and unnecessary header.
3. Change Kconfig and Makefile to support FSL PCI common driver
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/Kconfig | 1 +
drivers/pci/host/Kconfig | 10 +++++++++
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pci-fsl-common.c | 43 +++++++++++++++++++++++++++++++--------
include/linux/fsl/pci-common.h | 6 ++++++
5 files changed, 52 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index b44b52c..c708d80 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -694,6 +694,7 @@ config FSL_SOC
config FSL_PCI
bool
+ select PCI_FSL_COMMON if FSL_SOC_BOOKE || PPC_86xx
select PPC_INDIRECT_PCI
select PCI_QUIRKS
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 47d46c6..290afaa 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
+config PCI_FSL_COMMON
+ bool "Common driver for Freescale PCI/PCIe controller"
+ depends on FSL_SOC_BOOKE || PPC_86xx
+ help
+ This driver provides common support for PCI/PCIE controller
+ on Freescale embedded processors 85xx/86xx/QorIQ/Layerscape.
+ Additional drivers must be enabled in order to provide some
+ architecture-dependent functions and register the controller
+ to PCI subsystem.
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..1f8de80 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+obj-$(CONFIG_PCI_FSL_COMMON) += pci-fsl-common.o
diff --git a/drivers/pci/host/pci-fsl-common.c b/drivers/pci/host/pci-fsl-common.c
index 7184ac7..d608550 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -16,16 +16,12 @@
*/
#include <linux/kernel.h>
#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/string.h>
#include <linux/init.h>
-#include <linux/bootmem.h>
#include <linux/memblock.h>
#include <linux/log2.h>
-#include <linux/slab.h>
-#include <linux/uaccess.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
+#include <linux/fsl/pci-common.h>
#include <asm/io.h>
#include <asm/prom.h>
@@ -665,12 +661,40 @@ static const struct of_device_id pci_ids[] = {
static int fsl_pci_probe(struct platform_device *pdev)
{
int ret;
- struct device_node *node;
+ struct fsl_pci *pci;
- node = pdev->dev.of_node;
- ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
+ if (!of_device_is_available(pdev->dev.of_node)) {
+ dev_dbg(&pdev->dev, "disabled\n");
+ return -ENODEV;
+ }
+
+ pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci) {
+ dev_err(&pdev->dev, "no memory for fsl_pci\n");
+ return -ENOMEM;
+ }
+
+ ret = fsl_pci_setup(pdev, pci);
+ if (ret)
+ return ret;
+
+ ret = fsl_arch_pci_sys_register(pci);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register pcie to Arch\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int fsl_pci_remove(struct platform_device *pdev)
+{
+ struct fsl_pci *pci = platform_get_drvdata(pdev);
+
+ if (!pci)
+ return -ENODEV;
- mpc85xx_pci_err_probe(pdev);
+ fsl_arch_pci_sys_remove(pci);
return 0;
}
@@ -714,6 +738,7 @@ static struct platform_driver fsl_pci_driver = {
.of_match_table = pci_ids,
},
.probe = fsl_pci_probe,
+ .remove = fsl_pci_remove,
};
static int __init fsl_pci_init(void)
diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h
index 02bcf5b..8d33354 100644
--- a/include/linux/fsl/pci-common.h
+++ b/include/linux/fsl/pci-common.h
@@ -166,5 +166,11 @@ extern struct pci_bus *fsl_arch_fake_pci_bus(struct fsl_pci *pci, int busnr);
/* Return PCI64 DMA offset */
u64 fsl_arch_pci64_dma_offset(void);
+/* Register PCI/PCIe controller to architecture system */
+extern int fsl_arch_pci_sys_register(struct fsl_pci *pci);
+
+/* Remove PCI/PCIe controller from architecture system */
+extern void fsl_arch_pci_sys_remove(struct fsl_pci *pci);
+
#endif /* __PCI_COMMON_H */
#endif /* __KERNEL__ */
--
1.8.1.2
^ permalink raw reply related
* [PATCH 06/12][v4] pci: fsl: port PCI controller setup code
From: Minghuan Lian @ 2014-01-08 5:01 UTC (permalink / raw)
To: linuxppc-dev
Cc: Minghuan Lian, linux-pci, Zang Roy-R61911, Bjorn Helgaas,
Scott Wood
In-Reply-To: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com>
PCI controller setup code will initialize structure fsl_pci
according to PCI dts node and initialize PCI command register
and ATMU. The patch uses general API of_pci_parse_bus_range
to parse PCI bus range, uses general of_address's API to parse
PCI IO/MEM ranges.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
drivers/pci/host/pci-fsl-common.c | 179 +++++++++++++++++++++-----------------
1 file changed, 97 insertions(+), 82 deletions(-)
diff --git a/drivers/pci/host/pci-fsl-common.c b/drivers/pci/host/pci-fsl-common.c
index 26ee4c3..7184ac7 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -24,6 +24,8 @@
#include <linux/log2.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
#include <asm/io.h>
#include <asm/prom.h>
@@ -498,131 +500,144 @@ static void setup_pci_atmu(struct fsl_pci *pci)
}
}
-static void __init setup_pci_cmd(struct pci_controller *hose)
+static void __init setup_pci_cmd(struct fsl_pci *pci)
{
u16 cmd;
int cap_x;
- early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
+ early_fsl_read_config_word(pci, 0, 0, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
| PCI_COMMAND_IO;
- early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
+ early_fsl_write_config_word(pci, 0, 0, PCI_COMMAND, cmd);
- cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
+ cap_x = early_fsl_find_capability(pci, 0, 0, PCI_CAP_ID_PCIX);
if (cap_x) {
int pci_x_cmd = cap_x + PCI_X_CMD;
cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
- } else {
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
- }
+ early_fsl_write_config_word(pci, 0, 0, pci_x_cmd, cmd);
+ } else
+ early_fsl_write_config_byte(pci, 0, 0, PCI_LATENCY_TIMER,
+ 0x80);
}
-int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
+static int __init
+fsl_pci_setup(struct platform_device *pdev, struct fsl_pci *pci)
{
- int len;
- struct pci_controller *hose;
- struct resource rsrc;
- const int *bus_range;
+ struct resource *rsrc;
u8 hdr_type, progif;
- struct device_node *dev;
- struct ccsr_pci __iomem *pci;
-
- dev = pdev->dev.of_node;
+ struct device_node *dn;
+ struct of_pci_range range;
+ struct of_pci_range_parser parser;
+ int mem = 0;
- if (!of_device_is_available(dev)) {
- pr_warning("%s: disabled\n", dev->full_name);
- return -ENODEV;
- }
+ dn = pdev->dev.of_node;
+ pci->dn = dn;
+ pci->dev = &pdev->dev;
- pr_debug("Adding PCI host bridge %s\n", dev->full_name);
+ dev_info(&pdev->dev, "Find controller %s\n", dn->full_name);
/* Fetch host bridge registers address */
- if (of_address_to_resource(dev, 0, &rsrc)) {
- printk(KERN_WARNING "Can't get pci register base!");
- return -ENOMEM;
+ rsrc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!rsrc) {
+ dev_err(&pdev->dev, "Can't get pci register base!");
+ return -EINVAL;
}
+ dev_info(&pdev->dev, "REG 0x%016llx..0x%016llx\n",
+ (u64)rsrc->start, (u64)rsrc->end);
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int))
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
-
- pci_add_flags(PCI_REASSIGN_ALL_BUS);
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
+ /* Parse pci range resources from device tree */
+ if (of_pci_range_parser_init(&parser, dn)) {
+ dev_err(&pdev->dev, "missing ranges property\n");
+ return -EINVAL;
+ }
- /* set platform device as the parent */
- hose->parent = &pdev->dev;
- hose->first_busno = bus_range ? bus_range[0] : 0x0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
+ /* Get the I/O and memory ranges from device tree */
+ for_each_of_pci_range(&parser, &range) {
+ unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
+ if (restype == IORESOURCE_IO) {
+ of_pci_range_to_resource(&range, dn,
+ &pci->io_resource);
+ pci->io_resource.name = "I/O";
+ pci->io_resource.start = range.pci_addr;
+ pci->io_resource.end = range.pci_addr + range.size - 1;
+ pci->pci_io_size = range.size;
+ pci->io_base_phys = range.cpu_addr - range.pci_addr;
+ dev_info(&pdev->dev,
+ " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
+ range.cpu_addr,
+ range.cpu_addr + range.size - 1,
+ range.pci_addr);
+ }
+ if (restype == IORESOURCE_MEM) {
+ if (mem >= 3)
+ continue;
+ of_pci_range_to_resource(&range, dn,
+ &pci->mem_resources[mem]);
+ pci->mem_resources[mem].name = "MEM";
+ pci->mem_offset[mem] = range.cpu_addr - range.pci_addr;
+ dev_info(&pdev->dev,
+ "MEM 0x%016llx..0x%016llx -> 0x%016llx\n",
+ (u64)pci->mem_resources[mem].start,
+ (u64)pci->mem_resources[mem].end,
+ range.pci_addr);
+ }
+ }
- pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
- (u64)rsrc.start, (u64)resource_size(&rsrc));
+ /* Get bus range */
+ if (of_pci_parse_bus_range(dn, &pci->busn)) {
+ dev_err(&pdev->dev, "failed to parse bus-range property\n");
+ pci->first_busno = 0x0;
+ pci->last_busno = 0xff;
+ } else {
+ pci->first_busno = pci->busn.start;
+ pci->last_busno = pci->busn.end;
+ }
+ dev_info(&pdev->dev, "Firmware bus number %d->%d\n",
+ pci->first_busno, pci->last_busno);
- pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
- if (!hose->private_data)
- goto no_bridge;
+ pci->regs = devm_ioremap_resource(&pdev->dev, rsrc);
+ if (IS_ERR(pci->regs))
+ return PTR_ERR(pci->regs);
- setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
- PPC_INDIRECT_TYPE_BIG_ENDIAN);
+ pci->ops = &fsl_indirect_pci_ops;
+ pci->indirect_type = INDIRECT_TYPE_BIG_ENDIAN;
- if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
- hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
+ if (in_be32(&pci->regs->block_rev1) < PCIE_IP_REV_3_0)
+ pci->indirect_type |= INDIRECT_TYPE_FSL_CFG_REG_LINK;
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- /* use fsl_indirect_read_config for PCIe */
- hose->ops = &fsl_indirect_pcie_ops;
- /* For PCIE read HEADER_TYPE to identify controler mode */
- early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
- if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
+ pci->is_pcie = !!early_fsl_find_capability(pci, 0, 0, PCI_CAP_ID_EXP);
+ if (pci->is_pcie) {
+ /* For PCIE read HEADER_TYPE to identify controller mode */
+ early_fsl_read_config_byte(pci, 0, 0, PCI_HEADER_TYPE,
+ &hdr_type);
+ if ((hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL)
goto no_bridge;
-
} else {
/* For PCI read PROG to identify controller mode */
- early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
+ early_fsl_read_config_byte(pci, 0, 0, PCI_CLASS_PROG, &progif);
if ((progif & 1) == 1)
goto no_bridge;
}
- setup_pci_cmd(hose);
+ setup_pci_cmd(pci);
/* check PCI express link status */
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
- PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
- if (fsl_pcie_check_link(hose))
- hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+ if (pci->is_pcie) {
+ pci->indirect_type |= INDIRECT_TYPE_EXT_REG |
+ INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
+ if (!fsl_pci_check_link(pci))
+ pci->indirect_type |= INDIRECT_TYPE_NO_PCIE_LINK;
}
- printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long long)rsrc.start, hose->first_busno,
- hose->last_busno);
-
- pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, is_primary);
-
/* Setup PEX window registers */
- setup_pci_atmu(hose);
+ setup_pci_atmu(pci);
+
+ platform_set_drvdata(pdev, pci);
return 0;
no_bridge:
- iounmap(hose->private_data);
- /* unmap cfg_data & cfg_addr separately if not on same page */
- if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
- ((unsigned long)hose->cfg_addr & PAGE_MASK))
- iounmap(hose->cfg_data);
- iounmap(hose->cfg_addr);
- pcibios_free_controller(hose);
return -ENODEV;
}
--
1.8.1.2
^ permalink raw reply related
* [PATCH 08/12][v4] pci: fsl: add PowerPC PCI driver
From: Minghuan Lian @ 2014-01-08 5:01 UTC (permalink / raw)
To: linuxppc-dev
Cc: Minghuan Lian, linux-pci, Zang Roy-R61911, Bjorn Helgaas,
Scott Wood
In-Reply-To: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com>
1. Implement fsl_arch_pci64_dma_offset() to return PowerPC PCI64
DMA offset
2. Implement fsl_arch_sys_to_pci() to convert pci_controller
to fsl_pci
3. Implement fsl_arch_fake_pci_bus() to fake pci_controller
and PCI bus.
4. Implement fsl_arch_pci_exclude_device() to call
ppc_md.pci_exclude_device()
5. Implement fsl_arch_pci_sys_register() to initialize pci_controller
according to fsl_pci, add register PCI controller to PowerPC PCI
subsystem.
6. Implement fsl_arch_pci_sys_remove() to remove PCI controller from
PowerPC PCI subsystem.
7. Add mpc83xx_pcie_check_link() because pci-fsl-common dose not
support mpc83xx.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/sysdev/fsl_pci.c | 142 +++++++++++++++++++++++++++++++++++++++---
1 file changed, 135 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 0764385..38e8dca 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -62,7 +62,11 @@ static void quirk_fsl_pcie_early(struct pci_dev *dev)
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
#define MAX_PHYS_ADDR_BITS 40
-static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
+
+u64 fsl_arch_pci64_dma_offset(void)
+{
+ return 1ull << MAX_PHYS_ADDR_BITS;
+}
static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
{
@@ -77,17 +81,44 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
if ((dev->bus == &pci_bus_type) &&
dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
set_dma_ops(dev, &dma_direct_ops);
- set_dma_offset(dev, pci64_dma_offset);
+ set_dma_offset(dev, fsl_arch_pci64_dma_offset());
}
*dev->dma_mask = dma_mask;
return 0;
}
+struct fsl_pci *fsl_arch_sys_to_pci(void *sys)
+{
+ struct pci_controller *hose = sys;
+ struct fsl_pci *pci = hose->private_data;
+
+ /* Update the first bus number */
+ if (pci->first_busno != hose->first_busno)
+ pci->first_busno = hose->first_busno;
+
+ return pci;
+}
+
+struct pci_bus *fsl_arch_fake_pci_bus(struct fsl_pci *pci, int busnr)
+{
+ static struct pci_bus bus;
+ static struct pci_controller hose;
+
+ bus.number = busnr;
+ bus.sysdata = &hose;
+ hose.private_data = pci;
+ bus.ops = pci->ops;
+
+ return &bus;
+}
+
void fsl_pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_controller *hose = pci_bus_to_host(bus);
- int i, is_pcie = 0, no_link;
+ bool is_pcie, no_link;
+ int i;
+ struct fsl_pci *pci = fsl_arch_sys_to_pci(hose);
/* The root complex bridge comes up with bogus resources,
* we copy the PHB ones in.
@@ -97,9 +128,8 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
* tricky.
*/
- if (fsl_pcie_bus_fixup)
- is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
- no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
+ is_pcie = pci->is_pcie;
+ no_link = !fsl_pci_check_link(pci);
if (bus->parent == hose->bus && (is_pcie || no_link)) {
for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
@@ -121,6 +151,94 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
}
}
+int fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn)
+{
+ struct pci_controller *hose = pci->sys;
+
+ if (!hose)
+ return PCIBIOS_SUCCESSFUL;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(hose, bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int fsl_arch_pci_sys_register(struct fsl_pci *pci)
+{
+ struct pci_controller *hose;
+
+ pci_add_flags(PCI_REASSIGN_ALL_BUS);
+ hose = pcibios_alloc_controller(pci->dn);
+ if (!hose)
+ return -ENOMEM;
+
+ /* set platform device as the parent */
+ hose->private_data = pci;
+ hose->parent = pci->dev;
+ hose->first_busno = pci->first_busno;
+ hose->last_busno = pci->last_busno;
+ hose->ops = pci->ops;
+
+#ifdef CONFIG_PPC32
+ /* On 32 bits, limit I/O space to 16MB */
+ if (pci->pci_io_size > 0x01000000)
+ pci->pci_io_size = 0x01000000;
+
+ /* 32 bits needs to map IOs here */
+ hose->io_base_virt = ioremap(pci->io_base_phys + pci->io_resource.start,
+ pci->pci_io_size);
+
+ /* Expect trouble if pci_addr is not 0 */
+ if (fsl_pci_primary == pci->dn)
+ isa_io_base = (unsigned long)hose->io_base_virt;
+#endif /* CONFIG_PPC32 */
+
+ hose->pci_io_size = pci->io_resource.start + pci->pci_io_size;
+ hose->io_base_phys = pci->io_base_phys;
+ hose->io_resource = pci->io_resource;
+
+ memcpy(hose->mem_offset, pci->mem_offset, sizeof(hose->mem_offset));
+ memcpy(hose->mem_resources, pci->mem_resources,
+ sizeof(hose->mem_resources));
+ hose->dma_window_base_cur = pci->dma_window_base_cur;
+ hose->dma_window_size = pci->dma_window_size;
+
+ pci->sys = hose;
+
+ /*
+ * Install our own dma_set_mask handler to fixup dma_ops
+ * and dma_offset when memory is more than dma window size
+ */
+ if (pci->is_pcie && memblock_end_of_DRAM() > hose->dma_window_size)
+ ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
+
+#ifdef CONFIG_SWIOTLB
+ /*
+ * if we couldn't map all of DRAM via the dma windows
+ * we need SWIOTLB to handle buffers located outside of
+ * dma capable memory region
+ */
+ if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur +
+ hose->dma_window_size)
+ ppc_swiotlb_enable = 1;
+#endif
+
+ mpc85xx_pci_err_probe(to_platform_device(pci->dev));
+ return 0;
+}
+
+void fsl_arch_pci_sys_remove(struct fsl_pci *pci)
+{
+ struct pci_controller *hose = pci->sys;
+
+ if (!hose)
+ return;
+
+ pcibios_free_controller(hose);
+}
+
#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
@@ -261,6 +379,16 @@ static struct pci_ops mpc83xx_pcie_ops = {
.write = mpc83xx_pcie_write_config,
};
+static int mpc83xx_pcie_check_link(struct pci_controller *hose)
+{
+ u32 val = 0;
+
+ early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
+ if (val < PCIE_LTSSM_L0)
+ return 1;
+ return 0;
+}
+
static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
struct resource *reg)
{
@@ -295,7 +423,7 @@ static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
- if (fsl_pcie_check_link(hose))
+ if (mpc83xx_pcie_check_link(hose))
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
return 0;
--
1.8.1.2
^ permalink raw reply related
* [PATCH 11/12][v4] pci: fsl: update PCI EDAC driver
From: Minghuan Lian @ 2014-01-08 5:02 UTC (permalink / raw)
To: linuxppc-dev
Cc: Minghuan Lian, linux-pci, Zang Roy-R61911, Bjorn Helgaas,
Scott Wood
In-Reply-To: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com>
1. The pci-fsl-common driver has set fsl_pci to device as drvdata,
so EDAC driver can not call dev_set_drvdata() again. fsl_pci
contains regs field to point PCI CCSR, so EDAC may directly use
the pointer and not need to call devm_ioremap().
2. Add mpc85xx_pci_err_remove() to disable PCI error interrupt
and delete PCI EDAC from EDAC subsystem.
3. AER uses the same IRQ, so change IRQ handling mode as shared
to avoid AER can not request IRQ.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v4:
Changed IRQ handling mode as shared to avoid aer can not request IRQ.
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Added mpc85xx_pci_err_remove()
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/sysdev/fsl_pci.h | 6 +++++
drivers/edac/mpc85xx_edac.c | 61 +++++++++++++++++++++++++------------------
drivers/edac/mpc85xx_edac.h | 1 +
4 files changed, 43 insertions(+), 26 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 6d9bec4..2e3455e 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -236,6 +236,7 @@ void fsl_arch_pci_sys_remove(struct fsl_pci *pci)
if (!hose)
return;
+ mpc85xx_pci_err_remove(to_platform_device(pci->dev));
pcibios_free_controller(hose);
}
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index ce77aad..ae4dbe2 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -35,11 +35,17 @@ static inline void fsl_pci_assign_primary(void) {}
#ifdef CONFIG_EDAC_MPC85XX
int mpc85xx_pci_err_probe(struct platform_device *op);
+int mpc85xx_pci_err_remove(struct platform_device *op);
#else
static inline int mpc85xx_pci_err_probe(struct platform_device *op)
{
return -ENOTSUPP;
}
+static inline int mpc85xx_pci_err_remove(struct platform_device *op)
+{
+ return -ENOTSUPP;
+}
+
#endif
#ifdef CONFIG_FSL_PCI
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index fd46b0b..ea37db9 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -21,6 +21,7 @@
#include <linux/of_platform.h>
#include <linux/of_device.h>
+#include <linux/fsl/pci-common.h>
#include "edac_module.h"
#include "edac_core.h"
#include "mpc85xx_edac.h"
@@ -214,11 +215,13 @@ static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
int mpc85xx_pci_err_probe(struct platform_device *op)
{
+ struct fsl_pci *fslpci;
struct edac_pci_ctl_info *pci;
struct mpc85xx_pci_pdata *pdata;
- struct resource r;
int res = 0;
+ fslpci = platform_get_drvdata(op);
+
if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
return -ENOMEM;
@@ -239,7 +242,6 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
pdata = pci->pvt_info;
pdata->name = "mpc85xx_pci_err";
pdata->irq = NO_IRQ;
- dev_set_drvdata(&op->dev, pci);
pci->dev = &op->dev;
pci->mod_name = EDAC_MOD_STR;
pci->ctl_name = pdata->name;
@@ -250,30 +252,8 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
pdata->edac_idx = edac_pci_idx++;
- res = of_address_to_resource(op->dev.of_node, 0, &r);
- if (res) {
- printk(KERN_ERR "%s: Unable to get resource for "
- "PCI err regs\n", __func__);
- goto err;
- }
-
/* we only need the error registers */
- r.start += 0xe00;
-
- if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
- pdata->name)) {
- printk(KERN_ERR "%s: Error while requesting mem region\n",
- __func__);
- res = -EBUSY;
- goto err;
- }
-
- pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
- if (!pdata->pci_vbase) {
- printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
- res = -ENOMEM;
- goto err;
- }
+ pdata->pci_vbase = (void *)fslpci->regs + MPC85XX_PCI_ERR_OFFSET;
orig_pci_err_cap_dr =
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
@@ -297,7 +277,8 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
if (edac_op_state == EDAC_OPSTATE_INT) {
pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
res = devm_request_irq(&op->dev, pdata->irq,
- mpc85xx_pci_isr, IRQF_DISABLED,
+ mpc85xx_pci_isr,
+ IRQF_DISABLED | IRQF_SHARED,
"[EDAC] PCI err", pci);
if (res < 0) {
printk(KERN_ERR
@@ -327,6 +308,34 @@ err:
}
EXPORT_SYMBOL(mpc85xx_pci_err_probe);
+int mpc85xx_pci_err_remove(struct platform_device *op)
+{
+ struct edac_pci_ctl_info *pci;
+ struct mpc85xx_pci_pdata *pdata;
+
+ edac_dbg(0, "\n");
+
+ pci = edac_pci_del_device(&op->dev);
+
+ if (!pci)
+ return -EINVAL;
+
+ pdata = pci->pvt_info;
+
+ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
+ orig_pci_err_cap_dr);
+
+ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
+
+ if (edac_op_state == EDAC_OPSTATE_INT)
+ irq_dispose_mapping(pdata->irq);
+
+ edac_pci_free_ctl_info(pci);
+
+ return 0;
+}
+EXPORT_SYMBOL(mpc85xx_pci_err_remove);
+
#endif /* CONFIG_PCI */
/**************************** L2 Err device ***************************/
diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/mpc85xx_edac.h
index 932016f..3ba235a 100644
--- a/drivers/edac/mpc85xx_edac.h
+++ b/drivers/edac/mpc85xx_edac.h
@@ -131,6 +131,7 @@
#define PCI_EDE_PERR_MASK (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \
PCI_EDE_ADDR_PERR)
+#define MPC85XX_PCI_ERR_OFFSET 0x0e00
#define MPC85XX_PCI_ERR_DR 0x0000
#define MPC85XX_PCI_ERR_CAP_DR 0x0004
#define MPC85XX_PCI_ERR_EN 0x0008
--
1.8.1.2
^ permalink raw reply related
* [PATCH 12/12][v4] pci: fsl: fix function check_pci_ctl_endpt_part
From: Minghuan Lian @ 2014-01-08 5:02 UTC (permalink / raw)
To: linuxppc-dev
Cc: Minghuan Lian, linux-pci, Zang Roy-R61911, Bjorn Helgaas,
Scott Wood
In-Reply-To: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com>
The new FSL PCI driver does not use cfg_addr of pci_controller,
we may directly access PCI CCSR using fsl_pci->regs.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v4:
no change
v1-v3:
The new patch to fix function check_pci_ctl_endpt_part
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/sysdev/fsl_pci.h | 5 -----
drivers/iommu/fsl_pamu_domain.c | 6 ++++--
include/linux/fsl/pci-common.h | 1 +
3 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index ae4dbe2..3176eb2 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -16,11 +16,6 @@
struct platform_device;
-
-/* FSL PCI controller BRR1 register */
-#define PCI_FSL_BRR1 0xbf8
-#define PCI_FSL_BRR1_VER 0xffff
-
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
u64 fsl_pci_immrbar_base(struct pci_controller *hose);
diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c
index c857c30..dd7bc25 100644
--- a/drivers/iommu/fsl_pamu_domain.c
+++ b/drivers/iommu/fsl_pamu_domain.c
@@ -36,6 +36,7 @@
#include <asm/pci-bridge.h>
#include <sysdev/fsl_pci.h>
+#include <linux/fsl/pci-common.h>
#include "fsl_pamu_domain.h"
#include "pci.h"
@@ -908,10 +909,11 @@ static struct iommu_group *get_device_iommu_group(struct device *dev)
static bool check_pci_ctl_endpt_part(struct pci_controller *pci_ctl)
{
u32 version;
+ struct fsl_pci *pci = fsl_arch_sys_to_pci(pci_ctl);
/* Check the PCI controller version number by readding BRR1 register */
- version = in_be32(pci_ctl->cfg_addr + (PCI_FSL_BRR1 >> 2));
- version &= PCI_FSL_BRR1_VER;
+ version = in_be32(&pci->regs->block_rev1);
+ version &= PCIE_IP_REV_MASK;
/* If PCI controller version is >= 0x204 we can partition endpoints*/
if (version >= 0x204)
return 1;
diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h
index 3247682..4e4191e 100644
--- a/include/linux/fsl/pci-common.h
+++ b/include/linux/fsl/pci-common.h
@@ -18,6 +18,7 @@
#define PCIE_LTSSM_L0 0x16 /* L0 state */
#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
+#define PCIE_IP_REV_MASK 0xffff
#define PIWAR_EN 0x80000000 /* Enable */
#define PIWAR_PF 0x20000000 /* prefetch */
#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
--
1.8.1.2
^ permalink raw reply related
* [PATCH 09/12][v4] pci: fsl: update PCI PM driver
From: Minghuan Lian @ 2014-01-08 5:02 UTC (permalink / raw)
To: linuxppc-dev
Cc: Minghuan Lian, linux-pci, Zang Roy-R61911, Bjorn Helgaas,
Scott Wood
In-Reply-To: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com>
The patch updates PCI PM driver, uses fsl_pci instead of
pci_controller.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
drivers/pci/host/pci-fsl-common.c | 13 +++----------
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/host/pci-fsl-common.c b/drivers/pci/host/pci-fsl-common.c
index d608550..e3696eb 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -702,19 +702,12 @@ static int fsl_pci_remove(struct platform_device *pdev)
#ifdef CONFIG_PM
static int fsl_pci_resume(struct device *dev)
{
- struct pci_controller *hose;
- struct resource pci_rsrc;
+ struct fsl_pci *pci = dev_get_drvdata(dev);
- hose = pci_find_hose_for_OF_device(dev->of_node);
- if (!hose)
+ if (!pci)
return -ENODEV;
- if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
- dev_err(dev, "Get pci register base failed.");
- return -ENODEV;
- }
-
- setup_pci_atmu(hose);
+ setup_pci_atmu(pci);
return 0;
}
--
1.8.1.2
^ permalink raw reply related
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