* [git pull] Please pull mpe.git for-linus branch (for powerpc)
From: Michael Ellerman @ 2014-10-20 9:15 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev list, LKML
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Hi Linus,
Here's some more updates for powerpc for 3.18.
They are a bit late I know, though must are actually bug fixes. In my defence I
nearly cut the top of my finger off last weekend in a gruesome bike maintenance
accident, so I spent a good part of the week waiting around for doctors. True
story, I can send photos if you like :)
Probably the most interesting fix is the sys_call_table one, which enables
syscall tracing for powerpc. There's a fix for HMI handling for old firmware,
more endian fixes for firmware interfaces, more EEH fixes, Anton fixed our
routine that gets the current stack pointer, and a few other misc bits.
The following changes since commit d53ba6b3bba33432cc37b7101a86f8f3392c46e7:
cxl: Fix afu_read() not doing finish_wait() on signal or non-blocking (2014-10-09 11:29:57 +1100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux.git for-linus
for you to fetch changes up to e89dafb5ca5022d3bc63602018adfc766c73bc2b:
powerpc: Only do dynamic DMA zone limits on platforms that need it (2014-10-17 09:21:44 +1100)
----------------------------------------------------------------
Anton Blanchard (5):
powerpc: Reimplement __get_SP() as a function not a define
powerpc: Rename __get_SP() to current_stack_pointer()
powerpc/pseries: Use dump_stack instead of show_stack
powerpc: Add printk levels to setup_system output
powerpc: sync pseries_le_defconfig with pseries_defconfig
Bharata B Rao (1):
powerpc/pseries: Make CPU hotplug path endian safe
Gavin Shan (7):
powerpc/eeh: Fix condition for isolated state
powerpc/eeh: Rename flag EEH_PE_RESET to EEH_PE_CFG_BLOCKED
powerpc/powernv: Drop config requests in EEH accessors
powerpc/pseries: Drop config requests in EEH accessors
powerpc/eeh: Block PCI config access upon frozen PE
powerpc/eeh: Don't collect logs on PE with blocked config space
powerpc/eeh: Block CFG upon frozen Shiner adapter
Greg Kurz (1):
powerpc/vphn: NUMA node code expects big-endian
Mahesh Salgaonkar (2):
powerpc/book3s: Don't clear MSR_RI in hmi handler.
powerpc/powernv: Fallback to old HMI handling behavior for old firmware
Michael Ellerman (3):
powerpc/msi: Fix the msi bitmap alignment tests
powerpc/msi: Use WARN_ON() in msi bitmap selftests
powerpc: Only do dynamic DMA zone limits on platforms that need it
Nishanth Aravamudan (2):
powerpc/numa: check error return from proc_create
powerpc/numa: Add ability to disable and debug topology updates
Romeo Cane (1):
powerpc: Fix sys_call_table declaration to enable syscall tracing
Documentation/kernel-parameters.txt | 6 +++
arch/powerpc/configs/pseries_le_defconfig | 7 ++-
arch/powerpc/include/asm/eeh.h | 3 +-
arch/powerpc/include/asm/perf_event.h | 2 +-
arch/powerpc/include/asm/reg.h | 3 +-
arch/powerpc/include/asm/syscall.h | 2 +-
arch/powerpc/kernel/dma.c | 8 ++++
arch/powerpc/kernel/eeh.c | 19 +++++---
arch/powerpc/kernel/eeh_driver.c | 12 ++---
arch/powerpc/kernel/eeh_pe.c | 10 ++++-
arch/powerpc/kernel/exceptions-64s.S | 5 ---
arch/powerpc/kernel/irq.c | 2 +-
arch/powerpc/kernel/misc.S | 4 ++
arch/powerpc/kernel/ppc_ksyms.c | 2 +
arch/powerpc/kernel/process.c | 2 +-
arch/powerpc/kernel/rtas_pci.c | 30 +++++--------
arch/powerpc/kernel/setup_64.c | 32 +++++++-------
arch/powerpc/kernel/stacktrace.c | 2 +-
arch/powerpc/mm/numa.c | 41 ++++++++++++++++-
arch/powerpc/platforms/powernv/eeh-ioda.c | 2 +-
arch/powerpc/platforms/powernv/eeh-powernv.c | 57 +++++++++++++++++++++++-
arch/powerpc/platforms/powernv/opal.c | 21 +++++++++
arch/powerpc/platforms/powernv/pci.c | 2 +-
arch/powerpc/platforms/pseries/dlpar.c | 22 +++++-----
arch/powerpc/platforms/pseries/hotplug-cpu.c | 4 +-
arch/powerpc/platforms/pseries/iommu.c | 11 +++--
arch/powerpc/platforms/pseries/pseries.h | 3 +-
arch/powerpc/sysdev/msi_bitmap.c | 66 +++++++++++++++-------------
28 files changed, 261 insertions(+), 119 deletions(-)
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^ permalink raw reply
* re: [POWERPC] 4xx: EP405 boards support for arch/powerpc
From: Dan Carpenter @ 2014-10-20 9:06 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
Hello Benjamin Herrenschmidt,
The patch 619740384ceb: "[POWERPC] 4xx: EP405 boards support for
arch/powerpc" from Dec 21, 2007, leads to the following static
checker warning:
arch/powerpc/boot/4xx.c:567 ibm405gp_fixup_clocks()
warn: shifting and masking to zero
arch/powerpc/boot/4xx.c
562 fbdv = (pllmr & 0x1e000000) >> 25;
563 if (fbdv == 0)
564 fbdv = 16;
565 cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
566 opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
567 ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
^^^^^^^^^^^^^^^^^^^^^^^^^
This mask and shift means that ppdv is always 1.
568 epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
569 udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
570
571 /* check for 405GPr */
572 if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
573 fwdvb = 8 - (pllmr & 0x00000007);
574 if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
575 if (psr & 0x00000020) /* New mode enable */
576 m = fwdvb * 2 * ppdv;
577 else
578 m = fwdvb * cbdv * ppdv;
regards,
dan carpenter
^ permalink raw reply
* RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms
From: Yuantian Tang @ 2014-10-20 6:10 UTC (permalink / raw)
To: Viresh Kumar
Cc: linuxppc-dev@ozlabs.org, Rafael J. Wysocki,
Linux Kernel Mailing List, linux-pm@vger.kernel.org
In-Reply-To: <CAKohpokotKSvQ13uU4MnCer+qzBUUbGVTd19y7xswCAEKk3nGQ@mail.gmail.com>
VGhhbmtzIGZvciB5b3VyIGNvbW1lbnRzLiAgWW91ciBjb21tZW50cyB3aWxsIGJlIGFkZHJlc3Nl
ZCBpbiBuZXh0IHZlcnNpb24uDQpTb21lIGV4cGxhbmF0aW9ucyBpbmxpbmUuDQoNClRoYW5rcywN
Cll1YW50aWFuDQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogVmlyZXNo
IEt1bWFyIFttYWlsdG86dmlyZXNoLmt1bWFyQGxpbmFyby5vcmddDQo+IFNlbnQ6IEZyaWRheSwg
T2N0b2JlciAxNywgMjAxNCA0OjA5IFBNDQo+IFRvOiBUYW5nIFl1YW50aWFuLUIyOTk4Mw0KPiBD
YzogUmFmYWVsIEouIFd5c29ja2k7IExpbnV4IEtlcm5lbCBNYWlsaW5nIExpc3Q7IGxpbnV4LXBt
QHZnZXIua2VybmVsLm9yZzsNCj4gbGludXhwcGMtZGV2QG96bGFicy5vcmc7IFRhbmcgWXVhbnRp
YW4tQjI5OTgzDQo+IFN1YmplY3Q6IFJlOiBbUEFUQ0hdIGNwdWZyZXE6IHFvcmlxOiBNYWtlIHRo
ZSBkcml2ZXIgdXNhYmxlIG9uIGFsbCBRb3JJUQ0KPiBwbGF0Zm9ybXMNCj4gDQo+IE9uIDE3IE9j
dG9iZXIgMjAxNCAwODo0MywgIDxCMjk5ODNAZnJlZXNjYWxlLmNvbT4gd3JvdGU6DQo+IA0KPiBI
aSBCMjk5ODMgOikNCj4gDQo+ID4gRnJvbTogVGFuZyBZdWFudGlhbiA8WXVhbnRpYW4uVGFuZ0Bm
cmVlc2NhbGUuY29tPg0KPiA+DQo+ID4gRnJlZXNjYWxlIGludHJvZHVjZWQgbmV3IEFSTSBjb3Jl
LWJhc2VkIFNvQ3Mgd2hpY2ggc3VwcG9ydCBkeW5hbWljDQo+ID4gZnJlcXVlbmN5IHN3aXRjaCBm
ZWF0dXJlLiBERlMgb24gbmV3IFNvQ3MgYXJlIGNvbXBhdGlibGUgd2l0aCBjdXJyZW50DQo+ID4g
UG93ZXJQQyBDb3JlTmV0IHBsYXRmb3Jtcy4gSW4gb3JkZXIgdG8gc3VwcG9ydCB0aG9zZSBuZXcg
cGxhdGZvcm1zLA0KPiA+IHRoaXMgZHJpdmVyIG5lZWRzIHRvIGJlIHNsaWdodGx5IGFkanVzdGVk
LiBUaGUgbWFpbiBjaGFuZ2VzIGluY2x1ZGU6DQo+ID4NCj4gPiAxLiBDaGFuZ2VkIHRoZSBuYW1l
cyBvZiBkcml2ZXIgYW5kIGZ1bmN0aW9ucyBpbiBkcml2ZXIuDQo+ID4gMi4gQWRkZWQgdHdvIG5l
dyBmdW5jdGlvbnMgZ2V0X2NwdV9waHlzaWNhbF9pZCgpIGFuZCBnZXRfYnVzX2ZyZXEoKS4NCj4g
PiAzLiBVc2VkIGEgbmV3IHdheSB0byBnZXQgYWxsIHRoZSBDUFVzIHdoaWNoIHNoYXJpbmcgY2xv
Y2sgd2lyZS4NCj4gPg0KPiA+IFNpZ25lZC1vZmYtYnk6IFRhbmcgWXVhbnRpYW4gPFl1YW50aWFu
LlRhbmdAZnJlZXNjYWxlLmNvbT4NCj4gPiAtLS0NCj4gPiAgZHJpdmVycy9jcHVmcmVxL0tjb25m
aWcuYXJtICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDggKysNCj4gPiAgZHJpdmVycy9jcHVm
cmVxL0tjb25maWcucG93ZXJwYyAgICAgICAgICAgICAgICAgICAgfCAgMTEgKy0NCj4gPiAgZHJp
dmVycy9jcHVmcmVxL01ha2VmaWxlICAgICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0N
Cj4gPiAgLi4uL3twcGMtY29yZW5ldC1jcHVmcmVxLmMgPT4gcW9yaXEtY3B1ZnJlcS5jfSAgICAg
fCAxNTANCj4gKysrKysrKysrKysrKystLS0tLS0tDQo+ID4gIDQgZmlsZXMgY2hhbmdlZCwgMTE0
IGluc2VydGlvbnMoKyksIDU3IGRlbGV0aW9ucygtKSAgcmVuYW1lDQo+ID4gZHJpdmVycy9jcHVm
cmVxL3twcGMtY29yZW5ldC1jcHVmcmVxLmMgPT4gcW9yaXEtY3B1ZnJlcS5jfSAoNzIlKQ0KPiA+
DQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvY3B1ZnJlcS9LY29uZmlnLmFybSBiL2RyaXZlcnMv
Y3B1ZnJlcS9LY29uZmlnLmFybQ0KPiA+IGluZGV4IDgzYTc1ZGMuLjE5MjVhZTk0IDEwMDY0NA0K
PiA+IC0tLSBhL2RyaXZlcnMvY3B1ZnJlcS9LY29uZmlnLmFybQ0KPiA+ICsrKyBiL2RyaXZlcnMv
Y3B1ZnJlcS9LY29uZmlnLmFybQ0KPiA+IEBAIC0yNDcsMyArMjQ3LDExIEBAIGNvbmZpZyBBUk1f
VEVHUkFfQ1BVRlJFUQ0KPiA+ICAgICAgICAgZGVmYXVsdCB5DQo+ID4gICAgICAgICBoZWxwDQo+
ID4gICAgICAgICAgIFRoaXMgYWRkcyB0aGUgQ1BVRnJlcSBkcml2ZXIgc3VwcG9ydCBmb3IgVEVH
UkEgU09Dcy4NCj4gPiArDQo+ID4gK2NvbmZpZyBRT1JJUV9DUFVGUkVRDQo+ID4gKyAgICAgICB0
cmlzdGF0ZSAiQ1BVIGZyZXF1ZW5jeSBzY2FsaW5nIGRyaXZlciBmb3IgRnJlZXNjYWxlIFFvcklR
IFNvQ3MiDQo+ID4gKyAgICAgICBkZXBlbmRzIG9uIE9GICYmIENPTU1PTl9DTEsNCj4gPiArICAg
ICAgIHNlbGVjdCBDTEtfUFBDX0NPUkVORVQNCj4gPiArICAgICAgIGhlbHANCj4gPiArICAgICAg
ICAgVGhpcyBhZGRzIHRoZSBDUFVGcmVxIGRyaXZlciBzdXBwb3J0IGZvciBGcmVlc2NhbGUgUW9y
SVEgU29Dcw0KPiA+ICsgICAgICAgICB3aGljaCBhcmUgY2FwYWJsZSBvZiBjaGFuZ2luZyB0aGUg
Q1BVJ3MgZnJlcXVlbmN5IGR5bmFtaWNhbGx5Lg0KPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2Nw
dWZyZXEvS2NvbmZpZy5wb3dlcnBjDQo+ID4gYi9kcml2ZXJzL2NwdWZyZXEvS2NvbmZpZy5wb3dl
cnBjIGluZGV4IDcyNTY0YjcuLjNhMzQyNDggMTAwNjQ0DQo+ID4gLS0tIGEvZHJpdmVycy9jcHVm
cmVxL0tjb25maWcucG93ZXJwYw0KPiA+ICsrKyBiL2RyaXZlcnMvY3B1ZnJlcS9LY29uZmlnLnBv
d2VycGMNCj4gPiBAQCAtMjMsMTQgKzIzLDEzIEBAIGNvbmZpZyBDUFVfRlJFUV9NQVBMRQ0KPiA+
ICAgICAgICAgICBUaGlzIGFkZHMgc3VwcG9ydCBmb3IgZnJlcXVlbmN5IHN3aXRjaGluZyBvbiBN
YXBsZSA5NzBGWA0KPiA+ICAgICAgICAgICBFdmFsdWF0aW9uIEJvYXJkIGFuZCBjb21wYXRpYmxl
IGJvYXJkcyAoSUJNIEpTMnggYmxhZGVzKS4NCj4gPg0KPiA+IC1jb25maWcgUFBDX0NPUkVORVRf
Q1BVRlJFUQ0KPiA+IC0gICAgICAgdHJpc3RhdGUgIkNQVSBmcmVxdWVuY3kgc2NhbGluZyBkcml2
ZXIgZm9yIEZyZWVzY2FsZSBFNTAwTUMgU29DcyINCj4gPiAtICAgICAgIGRlcGVuZHMgb24gUFBD
X0U1MDBNQyAmJiBPRiAmJiBDT01NT05fQ0xLDQo+ID4gK2NvbmZpZyBRT1JJUV9DUFVGUkVRDQo+
ID4gKyAgICAgICB0cmlzdGF0ZSAiQ1BVIGZyZXF1ZW5jeSBzY2FsaW5nIGRyaXZlciBmb3IgRnJl
ZXNjYWxlIFFvcklRIFNvQ3MiDQo+ID4gKyAgICAgICBkZXBlbmRzIG9uIE9GICYmIENPTU1PTl9D
TEsNCj4gPiAgICAgICAgIHNlbGVjdCBDTEtfUFBDX0NPUkVORVQNCj4gPiAgICAgICAgIGhlbHAN
Cj4gPiAtICAgICAgICAgVGhpcyBhZGRzIHRoZSBDUFVGcmVxIGRyaXZlciBzdXBwb3J0IGZvciBG
cmVlc2NhbGUgZTUwMG1jLA0KPiA+IC0gICAgICAgICBlNTUwMCBhbmQgZTY1MDAgc2VyaWVzIFNv
Q3Mgd2hpY2ggYXJlIGNhcGFibGUgb2YgY2hhbmdpbmcNCj4gPiAtICAgICAgICAgdGhlIENQVSdz
IGZyZXF1ZW5jeSBkeW5hbWljYWxseS4NCj4gPiArICAgICAgICAgVGhpcyBhZGRzIHRoZSBDUFVG
cmVxIGRyaXZlciBzdXBwb3J0IGZvciBGcmVlc2NhbGUgUW9ySVEgU29Dcw0KPiA+ICsgICAgICAg
ICB3aGljaCBhcmUgY2FwYWJsZSBvZiBjaGFuZ2luZyB0aGUgQ1BVJ3MgZnJlcXVlbmN5IGR5bmFt
aWNhbGx5Lg0KPiA+DQo+ID4gIGNvbmZpZyBDUFVfRlJFUV9QTUFDDQo+ID4gICAgICAgICBib29s
ICJTdXBwb3J0IGZvciBBcHBsZSBQb3dlckJvb2tzIg0KPiANCj4gRG9uJ3QgbmVlZCB0aGlzIGR1
cGxpY2F0aW9uIGF0IGFsbC4gSnVzdCBtb3ZlIHRoaXMgdG8gS2NvbmZpZyBpbnN0ZWFkIG9mIC5h
cm0gYW5kDQo+IHBwYy4NCj4gDQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvY3B1ZnJlcS9wcGMt
Y29yZW5ldC1jcHVmcmVxLmMNCj4gPiBiL2RyaXZlcnMvY3B1ZnJlcS9xb3JpcS1jcHVmcmVxLmMN
Cj4gDQo+ID4gIC8qKg0KPiA+ICAgKiBzdHJ1Y3QgY3B1X2RhdGEgLSBwZXIgQ1BVIGRhdGEgc3Ry
dWN0IEBAIC02OSw5ICs2OCw2IEBAIHN0YXRpYw0KPiA+IGNvbnN0IHUzMiAqZm1hc2s7DQo+ID4N
Cj4gPiAgc3RhdGljIERFRklORV9QRVJfQ1BVKHN0cnVjdCBjcHVfZGF0YSAqLCBjcHVfZGF0YSk7
DQo+ID4NCj4gPiAtLyogY3B1bWFzayBpbiBhIGNsdXN0ZXIgKi8NCj4gPiAtc3RhdGljIERFRklO
RV9QRVJfQ1BVKGNwdW1hc2tfdmFyX3QsIGNwdV9tYXNrKTsNCj4gPiAtDQo+ID4gICNpZm5kZWYg
Q09ORklHX1NNUA0KPiA+ICBzdGF0aWMgaW5saW5lIGNvbnN0IHN0cnVjdCBjcHVtYXNrICpjcHVf
Y29yZV9tYXNrKGludCBjcHUpICB7IEBADQo+ID4gLTc5LDYgKzc1LDc5IEBAIHN0YXRpYyBpbmxp
bmUgY29uc3Qgc3RydWN0IGNwdW1hc2sgKmNwdV9jb3JlX21hc2soaW50DQo+ID4gY3B1KSAgfSAg
I2VuZGlmDQo+ID4NCj4gPiArI2lmIGRlZmluZWQoQ09ORklHX1BQQ19FNTAwTUMpDQo+ID4gK3N0
YXRpYyBpbnQgZ2V0X2NwdV9waHlzaWNhbF9pZChpbnQgY3B1KSB7DQo+ID4gKyAgICAgICByZXR1
cm4gZ2V0X2hhcmRfc21wX3Byb2Nlc3Nvcl9pZChjcHUpOyB9ICNlbGlmDQo+ID4gK2RlZmluZWQo
Q09ORklHX0FSTSkNCj4gDQo+IFdvdWxkbid0IGEgI2Vsc2Ugd29yayBoZXJlIGFzIHRoZXJlIGFy
ZSBqdXN0IHR3byBwbGF0Zm9ybXMgd2UgYXJlIHRhbGtpbmcgYWJvdXQgPw0KPiANCj4gPiArc3Rh
dGljIGludCBnZXRfY3B1X3BoeXNpY2FsX2lkKGludCBjcHUpIHsNCj4gPiArICAgICAgIHJldHVy
biB0b3BvbG9neV9jb3JlX2lkKGNwdSk7DQo+ID4gK30NCj4gPiArI2VuZGlmDQo+ID4gKw0KPiA+
ICtzdGF0aWMgdTMyIGdldF9idXNfZnJlcSh2b2lkKQ0KPiA+ICt7DQo+ID4gKyAgICAgICBzdHJ1
Y3QgZGV2aWNlX25vZGUgKnNvYzsNCj4gPiArICAgICAgIHUzMiBzeXNmcmVxOw0KPiA+ICsNCj4g
PiArICAgICAgIHNvYyA9IG9mX2ZpbmRfbm9kZV9ieV90eXBlKE5VTEwsICJzb2MiKTsNCj4gPiAr
ICAgICAgIGlmICghc29jKQ0KPiA+ICsgICAgICAgICAgICAgICByZXR1cm4gMDsNCj4gPiArDQo+
ID4gKyAgICAgICBpZiAob2ZfcHJvcGVydHlfcmVhZF91MzIoc29jLCAiYnVzLWZyZXF1ZW5jeSIs
ICZzeXNmcmVxKSkNCj4gPiArICAgICAgICAgICAgICAgc3lzZnJlcSA9IDA7DQo+ID4gKw0KPiA+
ICsgICAgICAgb2Zfbm9kZV9wdXQoc29jKTsNCj4gPiArDQo+ID4gKyAgICAgICByZXR1cm4gc3lz
ZnJlcTsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIHN0cnVjdCBkZXZpY2Vfbm9kZSAqY3B1
X3RvX2Nsa19ub2RlKGludCBjcHUpIHsNCj4gPiArICAgICAgIHN0cnVjdCBkZXZpY2Vfbm9kZSAq
bnAsICpjbGtfbnA7DQo+ID4gKw0KPiA+ICsgICAgICAgaWYgKCFjcHVfcHJlc2VudChjcHUpKQ0K
PiA+ICsgICAgICAgICAgICAgICByZXR1cm4gTlVMTDsNCj4gPiArDQo+ID4gKyAgICAgICBucCA9
IG9mX2dldF9jcHVfbm9kZShjcHUsIE5VTEwpOw0KPiA+ICsgICAgICAgaWYgKCFucCkNCj4gPiAr
ICAgICAgICAgICAgICAgcmV0dXJuIE5VTEw7DQo+ID4gKw0KPiA+ICsgICAgICAgY2xrX25wID0g
b2ZfcGFyc2VfcGhhbmRsZShucCwgImNsb2NrcyIsIDApOw0KPiA+ICsgICAgICAgaWYgKCFjbGtf
bnApDQo+ID4gKyAgICAgICAgICAgICAgIHJldHVybiBOVUxMOw0KPiA+ICsNCj4gPiArICAgICAg
IG9mX25vZGVfcHV0KG5wKTsNCj4gPiArDQo+ID4gKyAgICAgICByZXR1cm4gY2xrX25wOw0KPiA+
ICt9DQo+ID4gKw0KPiA+ICsvKiB0cmF2ZXJzZSBjcHUgbm9kZXMgdG8gZ2V0IGNwdSBtYXNrIG9m
IHNoYXJpbmcgY2xvY2sgd2lyZSAqLyBzdGF0aWMNCj4gPiArdm9pZCBzZXRfYWZmZWN0ZWRfY3B1
cyhzdHJ1Y3QgY3B1ZnJlcV9wb2xpY3kgKnBvbGljeSkgew0KPiA+ICsgICAgICAgc3RydWN0IGRl
dmljZV9ub2RlICpucCwgKmNsa19ucDsNCj4gPiArICAgICAgIHN0cnVjdCBjcHVtYXNrICpkc3Rw
ID0gcG9saWN5LT5jcHVzOw0KPiA+ICsgICAgICAgaW50IGk7DQo+ID4gKw0KPiA+ICsgICAgICAg
bnAgPSBjcHVfdG9fY2xrX25vZGUocG9saWN5LT5jcHUpOw0KPiA+ICsgICAgICAgaWYgKCFucCkN
Cj4gPiArICAgICAgICAgICAgICAgcmV0dXJuOw0KPiA+ICsNCj4gPiArICAgICAgIGZvcl9lYWNo
X3ByZXNlbnRfY3B1KGkpIHsNCj4gPiArICAgICAgICAgICAgICAgY2xrX25wID0gY3B1X3RvX2Ns
a19ub2RlKGkpOw0KPiA+ICsgICAgICAgICAgICAgICBpZiAoIWNsa19ucCkNCj4gPiArICAgICAg
ICAgICAgICAgICAgICAgICBjb250aW51ZTsNCj4gPiArDQo+ID4gKyAgICAgICAgICAgICAgIGlm
IChjbGtfbnAgPT0gbnApDQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgY3B1bWFza19zZXRf
Y3B1KGksIGRzdHApOw0KPiANCj4gU28geW91IGFyZSBkZXBlbmRpbmcgb24gbWF0Y2hpbmcgdGhl
IGNsb2NrLW5vZGVzIGZyb20gRFQgZm9yIGdldHRpbmcgdGhpcw0KPiBpbmZvcm1hdGlvbiwgcmln
aHQgPyBUaGVyZSBpcyBub3RoaW5nIHRoYXQgdGhlIGFyY2hpdGVjdHVyZSBnaXZlcz8NCj4gDQpZ
ZXMuIEkgdXNlZCBhbiBhcmNoaXRlY3R1cmUgZGVwZW5kZW50IHdheS4NCg0KPiA+ICsNCj4gPiAr
ICAgICAgICAgICAgICAgb2Zfbm9kZV9wdXQoY2xrX25wKTsNCj4gPiArICAgICAgIH0NCj4gPiAr
ICAgICAgIG9mX25vZGVfcHV0KG5wKTsNCj4gPiArfQ0KPiA+ICsNCj4gPiAgLyogcmVkdWNlIHRo
ZSBkdXBsaWNhdGVkIGZyZXF1ZW5jaWVzIGluIGZyZXF1ZW5jeSB0YWJsZSAqLyAgc3RhdGljDQo+
ID4gdm9pZCBmcmVxX3RhYmxlX3JlZHVwKHN0cnVjdCBjcHVmcmVxX2ZyZXF1ZW5jeV90YWJsZSAq
ZnJlcV90YWJsZSwNCj4gPiAgICAgICAgICAgICAgICAgaW50IGNvdW50KQ0KPiA+IEBAIC0xMDUs
NiArMTc0LDcgQEAgc3RhdGljIHZvaWQgZnJlcV90YWJsZV9zb3J0KHN0cnVjdA0KPiBjcHVmcmVx
X2ZyZXF1ZW5jeV90YWJsZSAqZnJlcV90YWJsZSwNCj4gPiAgICAgICAgIGludCBpLCBqLCBpbmQ7
DQo+ID4gICAgICAgICB1bnNpZ25lZCBpbnQgZnJlcSwgbWF4X2ZyZXE7DQo+ID4gICAgICAgICBz
dHJ1Y3QgY3B1ZnJlcV9mcmVxdWVuY3lfdGFibGUgdGFibGU7DQo+ID4gKw0KPiA+ICAgICAgICAg
Zm9yIChpID0gMDsgaSA8IGNvdW50IC0gMTsgaSsrKSB7DQo+ID4gICAgICAgICAgICAgICAgIG1h
eF9mcmVxID0gZnJlcV90YWJsZVtpXS5mcmVxdWVuY3k7DQo+ID4gICAgICAgICAgICAgICAgIGlu
ZCA9IGk7DQo+ID4gQEAgLTEyOSw3ICsxOTksNyBAQCBzdGF0aWMgdm9pZCBmcmVxX3RhYmxlX3Nv
cnQoc3RydWN0DQo+IGNwdWZyZXFfZnJlcXVlbmN5X3RhYmxlICpmcmVxX3RhYmxlLA0KPiA+ICAg
ICAgICAgfQ0KPiA+ICB9DQo+ID4NCj4gPiAtc3RhdGljIGludCBjb3JlbmV0X2NwdWZyZXFfY3B1
X2luaXQoc3RydWN0IGNwdWZyZXFfcG9saWN5ICpwb2xpY3kpDQo+ID4gK3N0YXRpYyBpbnQgcW9y
aXFfY3B1ZnJlcV9jcHVfaW5pdChzdHJ1Y3QgY3B1ZnJlcV9wb2xpY3kgKnBvbGljeSkNCj4gPiAg
ew0KPiA+ICAgICAgICAgc3RydWN0IGRldmljZV9ub2RlICpucDsNCj4gPiAgICAgICAgIGludCBp
LCBjb3VudCwgcmV0Ow0KPiA+IEBAIC0xNDUsMTAgKzIxNSw4IEBAIHN0YXRpYyBpbnQgY29yZW5l
dF9jcHVmcmVxX2NwdV9pbml0KHN0cnVjdA0KPiBjcHVmcmVxX3BvbGljeSAqcG9saWN5KQ0KPiA+
ICAgICAgICAgICAgICAgICByZXR1cm4gLUVOT0RFVjsNCj4gPg0KPiA+ICAgICAgICAgZGF0YSA9
IGt6YWxsb2Moc2l6ZW9mKCpkYXRhKSwgR0ZQX0tFUk5FTCk7DQo+ID4gLSAgICAgICBpZiAoIWRh
dGEpIHsNCj4gPiAtICAgICAgICAgICAgICAgcHJfZXJyKCIlczogbm8gbWVtb3J5XG4iLCBfX2Z1
bmNfXyk7DQo+IA0KPiBXYXNuJ3QgdGhpcyB1c2VmdWwgPw0KPiANClRvIGdldCByaWQgb2YgY2hl
Y2twYXRjaCB3YXJuaW5nLg0KQ3VycmVudGx5LCBjaGVja3BhdGNoIHNjcmlwdCBkb2Vzbid0IGFs
bG93IHRvIG91dHB1dCBtZW1vcnkgYWxsb2NhdGlvbiBlcnJvciBpbmZvcm1hdGlvbi4NCldlIHdp
bGwgZ2V0IG1lbW9yeSBpbmZvcm1hdGlvbiBldmVudHVhbGx5IGlmIHRoZXJlIGFyZSBtZW1vcnkg
cmVsYXRlZCBlcnJvci4NCg0KUmVnYXJkcywNCll1YW50aWFuDQoNCj4gPiArICAgICAgIGlmICgh
ZGF0YSkNCj4gPiAgICAgICAgICAgICAgICAgZ290byBlcnJfbnA7DQo+ID4gLSAgICAgICB9DQo+
ID4NCj4gPiAgICAgICAgIHBvbGljeS0+Y2xrID0gb2ZfY2xrX2dldChucCwgMCk7DQo+ID4gICAg
ICAgICBpZiAoSVNfRVJSKHBvbGljeS0+Y2xrKSkgew0KPiA+IEBAIC0xNzAsNyArMjM4LDcgQEAg
c3RhdGljIGludCBjb3JlbmV0X2NwdWZyZXFfY3B1X2luaXQoc3RydWN0DQo+IGNwdWZyZXFfcG9s
aWN5ICpwb2xpY3kpDQo+ID4gICAgICAgICB9DQo+ID4NCj4gPiAgICAgICAgIGlmIChmbWFzaykN
Cj4gPiAtICAgICAgICAgICAgICAgbWFzayA9IGZtYXNrW2dldF9oYXJkX3NtcF9wcm9jZXNzb3Jf
aWQoY3B1KV07DQo+ID4gKyAgICAgICAgICAgICAgIG1hc2sgPSBmbWFza1tnZXRfY3B1X3BoeXNp
Y2FsX2lkKGNwdSldOw0KPiA+ICAgICAgICAgZWxzZQ0KPiA+ICAgICAgICAgICAgICAgICBtYXNr
ID0gMHgwOw0KPiA+DQo+ID4gQEAgLTIwMSwxMyArMjY5LDEzIEBAIHN0YXRpYyBpbnQgY29yZW5l
dF9jcHVmcmVxX2NwdV9pbml0KHN0cnVjdA0KPiBjcHVmcmVxX3BvbGljeSAqcG9saWN5KQ0KPiA+
ICAgICAgICAgZGF0YS0+dGFibGUgPSB0YWJsZTsNCj4gPg0KPiA+ICAgICAgICAgLyogdXBkYXRl
IC0+Y3B1cyBpZiB3ZSBoYXZlIGNsdXN0ZXIsIG5vIGhhcm0gaWYgbm90ICovDQo+ID4gLSAgICAg
ICBjcHVtYXNrX2NvcHkocG9saWN5LT5jcHVzLCBwZXJfY3B1KGNwdV9tYXNrLCBjcHUpKTsNCj4g
PiAtICAgICAgIGZvcl9lYWNoX2NwdShpLCBwZXJfY3B1KGNwdV9tYXNrLCBjcHUpKQ0KPiA+ICsg
ICAgICAgc2V0X2FmZmVjdGVkX2NwdXMocG9saWN5KTsNCj4gPiArICAgICAgIGZvcl9lYWNoX2Nw
dShpLCBwb2xpY3ktPmNwdXMpDQo+ID4gICAgICAgICAgICAgICAgIHBlcl9jcHUoY3B1X2RhdGEs
IGkpID0gZGF0YTsNCj4gDQo+IEdldCByaWQgb2YgdGhpcyBwZXItY3B1IGRhdGEgYW5kIHVzZSBw
b2xpY3ktPmRyaXZlcl9kYXRhIGluc3RlYWQuDQo+IA0KPiA+DQo+ID4gICAgICAgICAvKiBNaW5p
bXVtIHRyYW5zaXRpb24gbGF0ZW5jeSBpcyAxMiBwbGF0Zm9ybSBjbG9ja3MgKi8NCj4gPiAgICAg
ICAgIHU2NHRlbXAgPSAxMlVMTCAqIE5TRUNfUEVSX1NFQzsNCj4gPiAtICAgICAgIGRvX2Rpdih1
NjR0ZW1wLCBmc2xfZ2V0X3N5c19mcmVxKCkpOw0KPiA+ICsgICAgICAgZG9fZGl2KHU2NHRlbXAs
IGdldF9idXNfZnJlcSgpKTsNCj4gPiAgICAgICAgIHBvbGljeS0+Y3B1aW5mby50cmFuc2l0aW9u
X2xhdGVuY3kgPSB1NjR0ZW1wICsgMTsNCj4gPg0KPiA+ICAgICAgICAgb2Zfbm9kZV9wdXQobnAp
Ow0KPiA+IEBAIC0yMjcsNyArMjk1LDcgQEAgZXJyX25wOg0KPiA+ICAgICAgICAgcmV0dXJuIC1F
Tk9ERVY7DQo+ID4gIH0NCj4gPg0KPiA+IC1zdGF0aWMgaW50IF9fZXhpdCBjb3JlbmV0X2NwdWZy
ZXFfY3B1X2V4aXQoc3RydWN0IGNwdWZyZXFfcG9saWN5DQo+ID4gKnBvbGljeSkNCj4gPiArc3Rh
dGljIGludCBfX2V4aXQgcW9yaXFfY3B1ZnJlcV9jcHVfZXhpdChzdHJ1Y3QgY3B1ZnJlcV9wb2xp
Y3kNCj4gPiArKnBvbGljeSkNCj4gPiAgew0KPiA+ICAgICAgICAgc3RydWN0IGNwdV9kYXRhICpk
YXRhID0gcGVyX2NwdShjcHVfZGF0YSwgcG9saWN5LT5jcHUpOw0KPiA+ICAgICAgICAgdW5zaWdu
ZWQgaW50IGNwdTsNCj4gPiBAQCAtMjM2LDEzICszMDQsMTMgQEAgc3RhdGljIGludCBfX2V4aXQg
Y29yZW5ldF9jcHVmcmVxX2NwdV9leGl0KHN0cnVjdA0KPiBjcHVmcmVxX3BvbGljeSAqcG9saWN5
KQ0KPiA+ICAgICAgICAga2ZyZWUoZGF0YS0+dGFibGUpOw0KPiA+ICAgICAgICAga2ZyZWUoZGF0
YSk7DQo+ID4NCj4gPiAtICAgICAgIGZvcl9lYWNoX2NwdShjcHUsIHBlcl9jcHUoY3B1X21hc2ss
IHBvbGljeS0+Y3B1KSkNCj4gPiArICAgICAgIGZvcl9lYWNoX2NwdShjcHUsIHBvbGljeS0+Y3B1
cykNCj4gPiAgICAgICAgICAgICAgICAgcGVyX2NwdShjcHVfZGF0YSwgY3B1KSA9IE5VTEw7DQo+
ID4NCj4gPiAgICAgICAgIHJldHVybiAwOw0KPiA+ICB9DQo+ID4NCj4gPiAtc3RhdGljIGludCBj
b3JlbmV0X2NwdWZyZXFfdGFyZ2V0KHN0cnVjdCBjcHVmcmVxX3BvbGljeSAqcG9saWN5LA0KPiA+
ICtzdGF0aWMgaW50IHFvcmlxX2NwdWZyZXFfdGFyZ2V0KHN0cnVjdCBjcHVmcmVxX3BvbGljeSAq
cG9saWN5LA0KPiA+ICAgICAgICAgICAgICAgICB1bnNpZ25lZCBpbnQgaW5kZXgpDQo+ID4gIHsN
Cj4gPiAgICAgICAgIHN0cnVjdCBjbGsgKnBhcmVudDsNCj4gPiBAQCAtMjUyLDE4ICszMjAsMTgg
QEAgc3RhdGljIGludCBjb3JlbmV0X2NwdWZyZXFfdGFyZ2V0KHN0cnVjdA0KPiBjcHVmcmVxX3Bv
bGljeSAqcG9saWN5LA0KPiA+ICAgICAgICAgcmV0dXJuIGNsa19zZXRfcGFyZW50KHBvbGljeS0+
Y2xrLCBwYXJlbnQpOyAgfQ0KPiA+DQo+ID4gLXN0YXRpYyBzdHJ1Y3QgY3B1ZnJlcV9kcml2ZXIg
cHBjX2NvcmVuZXRfY3B1ZnJlcV9kcml2ZXIgPSB7DQo+ID4gLSAgICAgICAubmFtZSAgICAgICAg
ICAgPSAicHBjX2NwdWZyZXEiLA0KPiA+ICtzdGF0aWMgc3RydWN0IGNwdWZyZXFfZHJpdmVyIHFv
cmlxX2NwdWZyZXFfZHJpdmVyID0gew0KPiA+ICsgICAgICAgLm5hbWUgICAgICAgICAgID0gInFv
cmlxX2NwdWZyZXEiLA0KPiA+ICAgICAgICAgLmZsYWdzICAgICAgICAgID0gQ1BVRlJFUV9DT05T
VF9MT09QUywNCj4gPiAtICAgICAgIC5pbml0ICAgICAgICAgICA9IGNvcmVuZXRfY3B1ZnJlcV9j
cHVfaW5pdCwNCj4gPiAtICAgICAgIC5leGl0ICAgICAgICAgICA9IF9fZXhpdF9wKGNvcmVuZXRf
Y3B1ZnJlcV9jcHVfZXhpdCksDQo+ID4gKyAgICAgICAuaW5pdCAgICAgICAgICAgPSBxb3JpcV9j
cHVmcmVxX2NwdV9pbml0LA0KPiA+ICsgICAgICAgLmV4aXQgICAgICAgICAgID0gX19leGl0X3Ao
cW9yaXFfY3B1ZnJlcV9jcHVfZXhpdCksDQo+ID4gICAgICAgICAudmVyaWZ5ICAgICAgICAgPSBj
cHVmcmVxX2dlbmVyaWNfZnJlcXVlbmN5X3RhYmxlX3ZlcmlmeSwNCj4gPiAtICAgICAgIC50YXJn
ZXRfaW5kZXggICA9IGNvcmVuZXRfY3B1ZnJlcV90YXJnZXQsDQo+ID4gKyAgICAgICAudGFyZ2V0
X2luZGV4ICAgPSBxb3JpcV9jcHVmcmVxX3RhcmdldCwNCj4gPiAgICAgICAgIC5nZXQgICAgICAg
ICAgICA9IGNwdWZyZXFfZ2VuZXJpY19nZXQsDQo+ID4gICAgICAgICAuYXR0ciAgICAgICAgICAg
PSBjcHVmcmVxX2dlbmVyaWNfYXR0ciwNCj4gPiAgfTsNCj4gPg0KPiA+IC1zdGF0aWMgY29uc3Qg
c3RydWN0IG9mX2RldmljZV9pZCBub2RlX21hdGNoZXNbXSBfX2luaXRkYXRhID0gew0KPiA+ICtz
dGF0aWMgY29uc3Qgc3RydWN0IG9mX2RldmljZV9pZCBub2RlX21hdGNoZXNbXSBfX2luaXRjb25z
dCA9IHsNCj4gPiAgICAgICAgIHsgLmNvbXBhdGlibGUgPSAiZnNsLHAyMDQxLWNsb2NrZ2VuIiwg
LmRhdGEgPSAmc2RhdGFbMF0sIH0sDQo+ID4gICAgICAgICB7IC5jb21wYXRpYmxlID0gImZzbCxw
MzA0MS1jbG9ja2dlbiIsIC5kYXRhID0gJnNkYXRhWzBdLCB9LA0KPiA+ICAgICAgICAgeyAuY29t
cGF0aWJsZSA9ICJmc2wscDUwMjAtY2xvY2tnZW4iLCAuZGF0YSA9ICZzZGF0YVsxXSwgfSwgQEAN
Cj4gPiAtMjczLDYxICszNDEsNDMgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBvZl9kZXZpY2VfaWQg
bm9kZV9tYXRjaGVzW10NCj4gX19pbml0ZGF0YSA9IHsNCj4gPiAgICAgICAgIHt9DQo+ID4gIH07
DQo+ID4NCj4gPiAtc3RhdGljIGludCBfX2luaXQgcHBjX2NvcmVuZXRfY3B1ZnJlcV9pbml0KHZv
aWQpDQo+ID4gK3N0YXRpYyBpbnQgX19pbml0IHFvcmlxX2NwdWZyZXFfaW5pdCh2b2lkKQ0KPiA+
ICB7DQo+ID4gICAgICAgICBpbnQgcmV0Ow0KPiA+ICAgICAgICAgc3RydWN0IGRldmljZV9ub2Rl
ICAqbnA7DQo+ID4gICAgICAgICBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkICptYXRjaDsNCj4g
PiAgICAgICAgIGNvbnN0IHN0cnVjdCBzb2NfZGF0YSAqZGF0YTsNCj4gPiAtICAgICAgIHVuc2ln
bmVkIGludCBjcHU7DQo+ID4NCj4gPiAgICAgICAgIG5wID0gb2ZfZmluZF9tYXRjaGluZ19ub2Rl
KE5VTEwsIG5vZGVfbWF0Y2hlcyk7DQo+ID4gICAgICAgICBpZiAoIW5wKQ0KPiA+ICAgICAgICAg
ICAgICAgICByZXR1cm4gLUVOT0RFVjsNCj4gPg0KPiA+IC0gICAgICAgZm9yX2VhY2hfcG9zc2li
bGVfY3B1KGNwdSkgew0KPiA+IC0gICAgICAgICAgICAgICBpZiAoIWFsbG9jX2NwdW1hc2tfdmFy
KCZwZXJfY3B1KGNwdV9tYXNrLCBjcHUpLA0KPiBHRlBfS0VSTkVMKSkNCj4gPiAtICAgICAgICAg
ICAgICAgICAgICAgICBnb3RvIGVycl9tYXNrOw0KPiA+IC0gICAgICAgICAgICAgICBjcHVtYXNr
X2NvcHkocGVyX2NwdShjcHVfbWFzaywgY3B1KSwNCj4gY3B1X2NvcmVfbWFzayhjcHUpKTsNCj4g
PiAtICAgICAgIH0NCj4gPiAtDQo+ID4gICAgICAgICBtYXRjaCA9IG9mX21hdGNoX25vZGUobm9k
ZV9tYXRjaGVzLCBucCk7DQo+ID4gICAgICAgICBkYXRhID0gbWF0Y2gtPmRhdGE7DQo+ID4gICAg
ICAgICBpZiAoZGF0YSkgew0KPiA+ICAgICAgICAgICAgICAgICBpZiAoZGF0YS0+ZmxhZykNCj4g
PiAgICAgICAgICAgICAgICAgICAgICAgICBmbWFzayA9IGRhdGEtPmZyZXFfbWFzazsNCj4gPiAt
ICAgICAgICAgICAgICAgbWluX2NwdWZyZXEgPSBmc2xfZ2V0X3N5c19mcmVxKCk7DQo+ID4gKyAg
ICAgICAgICAgICAgIG1pbl9jcHVmcmVxID0gZ2V0X2J1c19mcmVxKCk7DQo+ID4gICAgICAgICB9
IGVsc2Ugew0KPiA+IC0gICAgICAgICAgICAgICBtaW5fY3B1ZnJlcSA9IGZzbF9nZXRfc3lzX2Zy
ZXEoKSAvIDI7DQo+ID4gKyAgICAgICAgICAgICAgIG1pbl9jcHVmcmVxID0gZ2V0X2J1c19mcmVx
KCkgLyAyOw0KPiA+ICAgICAgICAgfQ0KPiA+DQo+ID4gICAgICAgICBvZl9ub2RlX3B1dChucCk7
DQo+ID4NCj4gPiAtICAgICAgIHJldCA9IGNwdWZyZXFfcmVnaXN0ZXJfZHJpdmVyKCZwcGNfY29y
ZW5ldF9jcHVmcmVxX2RyaXZlcik7DQo+ID4gKyAgICAgICByZXQgPSBjcHVmcmVxX3JlZ2lzdGVy
X2RyaXZlcigmcW9yaXFfY3B1ZnJlcV9kcml2ZXIpOw0KPiA+ICAgICAgICAgaWYgKCFyZXQpDQo+
ID4gLSAgICAgICAgICAgICAgIHByX2luZm8oIkZyZWVzY2FsZSBQb3dlclBDIGNvcmVuZXQgQ1BV
IGZyZXF1ZW5jeSBzY2FsaW5nDQo+IGRyaXZlclxuIik7DQo+ID4gKyAgICAgICAgICAgICAgIHBy
X2luZm8oIkZyZWVzY2FsZSBRb3JJUSBDUFUgZnJlcXVlbmN5IHNjYWxpbmcNCj4gPiArIGRyaXZl
clxuIik7DQo+ID4NCj4gPiAgICAgICAgIHJldHVybiByZXQ7DQo+ID4gLQ0KPiA+IC1lcnJfbWFz
azoNCj4gPiAtICAgICAgIGZvcl9lYWNoX3Bvc3NpYmxlX2NwdShjcHUpDQo+ID4gLSAgICAgICAg
ICAgICAgIGZyZWVfY3B1bWFza192YXIocGVyX2NwdShjcHVfbWFzaywgY3B1KSk7DQo+ID4gLQ0K
PiA+IC0gICAgICAgcmV0dXJuIC1FTk9NRU07DQo+ID4gIH0NCj4gPiAtbW9kdWxlX2luaXQocHBj
X2NvcmVuZXRfY3B1ZnJlcV9pbml0KTsNCj4gPiArbW9kdWxlX2luaXQocW9yaXFfY3B1ZnJlcV9p
bml0KTsNCj4gPg0KPiA+IC1zdGF0aWMgdm9pZCBfX2V4aXQgcHBjX2NvcmVuZXRfY3B1ZnJlcV9l
eGl0KHZvaWQpDQo+ID4gK3N0YXRpYyB2b2lkIF9fZXhpdCBxb3JpcV9jcHVmcmVxX2V4aXQodm9p
ZCkNCj4gPiAgew0KPiA+IC0gICAgICAgdW5zaWduZWQgaW50IGNwdTsNCj4gPiAtDQo+ID4gLSAg
ICAgICBmb3JfZWFjaF9wb3NzaWJsZV9jcHUoY3B1KQ0KPiA+IC0gICAgICAgICAgICAgICBmcmVl
X2NwdW1hc2tfdmFyKHBlcl9jcHUoY3B1X21hc2ssIGNwdSkpOw0KPiA+IC0NCj4gPiAtICAgICAg
IGNwdWZyZXFfdW5yZWdpc3Rlcl9kcml2ZXIoJnBwY19jb3JlbmV0X2NwdWZyZXFfZHJpdmVyKTsN
Cj4gPiArICAgICAgIGNwdWZyZXFfdW5yZWdpc3Rlcl9kcml2ZXIoJnFvcmlxX2NwdWZyZXFfZHJp
dmVyKTsNCj4gPiAgfQ0KPiA+IC1tb2R1bGVfZXhpdChwcGNfY29yZW5ldF9jcHVmcmVxX2V4aXQp
Ow0KPiA+ICttb2R1bGVfZXhpdChxb3JpcV9jcHVmcmVxX2V4aXQpOw0KPiA+DQo+ID4gIE1PRFVM
RV9MSUNFTlNFKCJHUEwiKTsNCj4gPiAgTU9EVUxFX0FVVEhPUigiVGFuZyBZdWFudGlhbiA8WXVh
bnRpYW4uVGFuZ0BmcmVlc2NhbGUuY29tPiIpOw0KPiA+IC1NT0RVTEVfREVTQ1JJUFRJT04oImNw
dWZyZXEgZHJpdmVyIGZvciBGcmVlc2NhbGUgZTUwMG1jIHNlcmllcw0KPiA+IFNvQ3MiKTsNCj4g
PiArTU9EVUxFX0RFU0NSSVBUSU9OKCJjcHVmcmVxIGRyaXZlciBmb3IgRnJlZXNjYWxlIFFvcklR
IHNlcmllcyBTb0NzIik7DQo+IA0KPiArIGNvbW1lbnRzIGZyb20gS3VtYXIgR2FsYSA6KQ0K
^ permalink raw reply
* RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms
From: Yuantian Tang @ 2014-10-20 2:20 UTC (permalink / raw)
To: Kumar Gala
Cc: linuxppc-dev@ozlabs.org, viresh.kumar@linaro.org,
rjw@rjwysocki.net, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org
In-Reply-To: <8F5E4DA7-8A64-4614-91E7-BFB28D91C737@kernel.crashing.org>
Thanks for your comments. Will address them in next version.
Also some explanations inline for your comments.
Thanks,
Yuantian
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Friday, October 17, 2014 4:04 PM
> To: Tang Yuantian-B29983
> Cc: rjw@rjwysocki.net; viresh.kumar@linaro.org; linux-kernel@vger.kernel.=
org;
> linux-pm@vger.kernel.org; linuxppc-dev@ozlabs.org; Tang Yuantian-B29983
> Subject: Re: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ
> platforms
>=20
>=20
> On Oct 17, 2014, at 5:13 AM, b29983@freescale.com wrote:
>=20
> > From: Tang Yuantian <Yuantian.Tang@freescale.com>
> >
> > Freescale introduced new ARM core-based SoCs which support dynamic
> > frequency switch feature. DFS on new SoCs are compatible with current
> > PowerPC CoreNet platforms. In order to support those new platforms,
> > this driver needs to be slightly adjusted. The main changes include:
> >
> > 1. Changed the names of driver and functions in driver.
>=20
> split the name changes/renaming into a separate patch from the other chan=
ges.
>=20
> > 2. Added two new functions get_cpu_physical_id() and get_bus_freq().
> > 3. Used a new way to get all the CPUs which sharing clock wire.
> >
> > Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> > ---
> > drivers/cpufreq/Kconfig.arm | 8 ++
> > drivers/cpufreq/Kconfig.powerpc | 11 +-
> > drivers/cpufreq/Makefile | 2 +-
> > .../{ppc-corenet-cpufreq.c =3D> qoriq-cpufreq.c} | 150 ++++++++++++=
++-------
> > 4 files changed, 114 insertions(+), 57 deletions(-) rename
> > drivers/cpufreq/{ppc-corenet-cpufreq.c =3D> qoriq-cpufreq.c} (72%)
> >
> > diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> > index 83a75dc..1925ae94 100644
> > --- a/drivers/cpufreq/Kconfig.arm
> > +++ b/drivers/cpufreq/Kconfig.arm
> > @@ -247,3 +247,11 @@ config ARM_TEGRA_CPUFREQ
> > default y
> > help
> > This adds the CPUFreq driver support for TEGRA SOCs.
> > +
> > +config QORIQ_CPUFREQ
> > + tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
> > + depends on OF && COMMON_CLK
> > + select CLK_PPC_CORENET
>=20
> Why are you not also renaming 'CLK_PPC_CORENET' to 'CLK_QORIQ' or
> something like that? Seems rather odd to select a PPC CLK support on ARM=
;)
>=20
Yes, someone else is working on that.
> > + help
> > + This adds the CPUFreq driver support for Freescale QorIQ SoCs
> > + which are capable of changing the CPU's frequency dynamically.
> > diff --git a/drivers/cpufreq/Kconfig.powerpc
> > b/drivers/cpufreq/Kconfig.powerpc index 72564b7..3a34248 100644
> > --- a/drivers/cpufreq/Kconfig.powerpc
> > +++ b/drivers/cpufreq/Kconfig.powerpc
> > @@ -23,14 +23,13 @@ config CPU_FREQ_MAPLE
> > This adds support for frequency switching on Maple 970FX
> > Evaluation Board and compatible boards (IBM JS2x blades).
> >
> > -config PPC_CORENET_CPUFREQ
> > - tristate "CPU frequency scaling driver for Freescale E500MC SoCs"
> > - depends on PPC_E500MC && OF && COMMON_CLK
> > +config QORIQ_CPUFREQ
> > + tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
> > + depends on OF && COMMON_CLK
> > select CLK_PPC_CORENET
> > help
> > - This adds the CPUFreq driver support for Freescale e500mc,
> > - e5500 and e6500 series SoCs which are capable of changing
> > - the CPU's frequency dynamically.
> > + This adds the CPUFreq driver support for Freescale QorIQ SoCs
> > + which are capable of changing the CPU's frequency dynamically.
> >
> > config CPU_FREQ_PMAC
> > bool "Support for Apple PowerBooks"
> > diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index
> > 40c53dc..0020049 100644
> > --- a/drivers/cpufreq/Makefile
> > +++ b/drivers/cpufreq/Makefile
> > @@ -84,7 +84,7 @@ obj-$(CONFIG_CPU_FREQ_CBE) +=3D
> ppc-cbe-cpufreq.o
> > ppc-cbe-cpufreq-y +=3D ppc_cbe_cpufreq_pervasive.o
> ppc_cbe_cpufreq.o
> > obj-$(CONFIG_CPU_FREQ_CBE_PMI) +=3D ppc_cbe_cpufreq_pmi.o
> > obj-$(CONFIG_CPU_FREQ_MAPLE) +=3D maple-cpufreq.o
> > -obj-$(CONFIG_PPC_CORENET_CPUFREQ) +=3D ppc-corenet-cpufreq.o
> > +obj-$(CONFIG_QORIQ_CPUFREQ) +=3D qoriq-cpufreq.o
> > obj-$(CONFIG_CPU_FREQ_PMAC) +=3D pmac32-cpufreq.o
> > obj-$(CONFIG_CPU_FREQ_PMAC64) +=3D pmac64-cpufreq.o
> > obj-$(CONFIG_PPC_PASEMI_CPUFREQ) +=3D pasemi-cpufreq.o
> > diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c
> > b/drivers/cpufreq/qoriq-cpufreq.c similarity index 72% rename from
> > drivers/cpufreq/ppc-corenet-cpufreq.c
> > rename to drivers/cpufreq/qoriq-cpufreq.c index bee5df7..80def0c
> > 100644
> > --- a/drivers/cpufreq/ppc-corenet-cpufreq.c
> > +++ b/drivers/cpufreq/qoriq-cpufreq.c
> > @@ -1,7 +1,7 @@
> > /*
> > * Copyright 2013 Freescale Semiconductor, Inc.
> > *
> > - * CPU Frequency Scaling driver for Freescale PowerPC corenet SoCs.
> > + * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
> > *
> > * This program is free software; you can redistribute it and/or
> > modify
> > * it under the terms of the GNU General Public License version 2 as
> > @@ -20,7 +20,6 @@ #include <linux/of.h> #include <linux/slab.h>
> > #include <linux/smp.h> -#include <sysdev/fsl_soc.h>
> >
> > /**
> > * struct cpu_data - per CPU data struct @@ -69,9 +68,6 @@ static
> > const u32 *fmask;
> >
> > static DEFINE_PER_CPU(struct cpu_data *, cpu_data);
> >
> > -/* cpumask in a cluster */
> > -static DEFINE_PER_CPU(cpumask_var_t, cpu_mask);
> > -
> > #ifndef CONFIG_SMP
> > static inline const struct cpumask *cpu_core_mask(int cpu) { @@ -79,6
> > +75,79 @@ static inline const struct cpumask *cpu_core_mask(int cpu) }
> > #endif
> >
> > +#if defined(CONFIG_PPC_E500MC)
>=20
> Probably should just be CONFIG_PPC, but do we need this at all. Can't we=
just
> use topology_core_id() on both ARM & PPC?
>=20
I will investigate if topology_core_id() works for PPC.
Regards,
Yuantian
> > +static int get_cpu_physical_id(int cpu) {
> > + return get_hard_smp_processor_id(cpu); } #elif defined(CONFIG_ARM)
> > +static int get_cpu_physical_id(int cpu) {
> > + return topology_core_id(cpu);
> > +}
> > +#endif
> > +
> > +static u32 get_bus_freq(void)
> > +{
> > + struct device_node *soc;
> > + u32 sysfreq;
> > +
> > + soc =3D of_find_node_by_type(NULL, "soc");
> > + if (!soc)
> > + return 0;
> > +
> > + if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
> > + sysfreq =3D 0;
> > +
> > + of_node_put(soc);
> > +
> > + return sysfreq;
> > +}
> > +
> > +static struct device_node *cpu_to_clk_node(int cpu) {
> > + struct device_node *np, *clk_np;
> > +
> > + if (!cpu_present(cpu))
> > + return NULL;
> > +
> > + np =3D of_get_cpu_node(cpu, NULL);
> > + if (!np)
> > + return NULL;
> > +
> > + clk_np =3D of_parse_phandle(np, "clocks", 0);
> > + if (!clk_np)
> > + return NULL;
> > +
> > + of_node_put(np);
> > +
> > + return clk_np;
> > +}
> > +
> > +/* traverse cpu nodes to get cpu mask of sharing clock wire */ static
> > +void set_affected_cpus(struct cpufreq_policy *policy) {
> > + struct device_node *np, *clk_np;
> > + struct cpumask *dstp =3D policy->cpus;
> > + int i;
> > +
> > + np =3D cpu_to_clk_node(policy->cpu);
> > + if (!np)
> > + return;
> > +
> > + for_each_present_cpu(i) {
> > + clk_np =3D cpu_to_clk_node(i);
> > + if (!clk_np)
> > + continue;
> > +
> > + if (clk_np =3D=3D np)
> > + cpumask_set_cpu(i, dstp);
> > +
> > + of_node_put(clk_np);
> > + }
> > + of_node_put(np);
> > +}
> > +
> > /* reduce the duplicated frequencies in frequency table */ static void
> > freq_table_redup(struct cpufreq_frequency_table *freq_table,
> > int count)
> > @@ -105,6 +174,7 @@ static void freq_table_sort(struct
> cpufreq_frequency_table *freq_table,
> > int i, j, ind;
> > unsigned int freq, max_freq;
> > struct cpufreq_frequency_table table;
> > +
> > for (i =3D 0; i < count - 1; i++) {
> > max_freq =3D freq_table[i].frequency;
> > ind =3D i;
> > @@ -129,7 +199,7 @@ static void freq_table_sort(struct
> cpufreq_frequency_table *freq_table,
> > }
> > }
> >
> > -static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy)
> > +static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
> > {
> > struct device_node *np;
> > int i, count, ret;
> > @@ -145,10 +215,8 @@ static int corenet_cpufreq_cpu_init(struct
> cpufreq_policy *policy)
> > return -ENODEV;
> >
> > data =3D kzalloc(sizeof(*data), GFP_KERNEL);
> > - if (!data) {
> > - pr_err("%s: no memory\n", __func__);
> > + if (!data)
> > goto err_np;
> > - }
> >
> > policy->clk =3D of_clk_get(np, 0);
> > if (IS_ERR(policy->clk)) {
> > @@ -170,7 +238,7 @@ static int corenet_cpufreq_cpu_init(struct
> cpufreq_policy *policy)
> > }
> >
> > if (fmask)
> > - mask =3D fmask[get_hard_smp_processor_id(cpu)];
> > + mask =3D fmask[get_cpu_physical_id(cpu)];
> > else
> > mask =3D 0x0;
> >
> > @@ -201,13 +269,13 @@ static int corenet_cpufreq_cpu_init(struct
> cpufreq_policy *policy)
> > data->table =3D table;
> >
> > /* update ->cpus if we have cluster, no harm if not */
> > - cpumask_copy(policy->cpus, per_cpu(cpu_mask, cpu));
> > - for_each_cpu(i, per_cpu(cpu_mask, cpu))
> > + set_affected_cpus(policy);
> > + for_each_cpu(i, policy->cpus)
> > per_cpu(cpu_data, i) =3D data;
> >
> > /* Minimum transition latency is 12 platform clocks */
> > u64temp =3D 12ULL * NSEC_PER_SEC;
> > - do_div(u64temp, fsl_get_sys_freq());
> > + do_div(u64temp, get_bus_freq());
> > policy->cpuinfo.transition_latency =3D u64temp + 1;
> >
> > of_node_put(np);
> > @@ -227,7 +295,7 @@ err_np:
> > return -ENODEV;
> > }
> >
> > -static int __exit corenet_cpufreq_cpu_exit(struct cpufreq_policy
> > *policy)
> > +static int __exit qoriq_cpufreq_cpu_exit(struct cpufreq_policy
> > +*policy)
> > {
> > struct cpu_data *data =3D per_cpu(cpu_data, policy->cpu);
> > unsigned int cpu;
> > @@ -236,13 +304,13 @@ static int __exit corenet_cpufreq_cpu_exit(struct
> cpufreq_policy *policy)
> > kfree(data->table);
> > kfree(data);
> >
> > - for_each_cpu(cpu, per_cpu(cpu_mask, policy->cpu))
> > + for_each_cpu(cpu, policy->cpus)
> > per_cpu(cpu_data, cpu) =3D NULL;
> >
> > return 0;
> > }
> >
> > -static int corenet_cpufreq_target(struct cpufreq_policy *policy,
> > +static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
> > unsigned int index)
> > {
> > struct clk *parent;
> > @@ -252,18 +320,18 @@ static int corenet_cpufreq_target(struct
> cpufreq_policy *policy,
> > return clk_set_parent(policy->clk, parent); }
> >
> > -static struct cpufreq_driver ppc_corenet_cpufreq_driver =3D {
> > - .name =3D "ppc_cpufreq",
> > +static struct cpufreq_driver qoriq_cpufreq_driver =3D {
> > + .name =3D "qoriq_cpufreq",
> > .flags =3D CPUFREQ_CONST_LOOPS,
> > - .init =3D corenet_cpufreq_cpu_init,
> > - .exit =3D __exit_p(corenet_cpufreq_cpu_exit),
> > + .init =3D qoriq_cpufreq_cpu_init,
> > + .exit =3D __exit_p(qoriq_cpufreq_cpu_exit),
> > .verify =3D cpufreq_generic_frequency_table_verify,
> > - .target_index =3D corenet_cpufreq_target,
> > + .target_index =3D qoriq_cpufreq_target,
> > .get =3D cpufreq_generic_get,
> > .attr =3D cpufreq_generic_attr,
> > };
> >
> > -static const struct of_device_id node_matches[] __initdata =3D {
> > +static const struct of_device_id node_matches[] __initconst =3D {
> > { .compatible =3D "fsl,p2041-clockgen", .data =3D &sdata[0], },
> > { .compatible =3D "fsl,p3041-clockgen", .data =3D &sdata[0], },
> > { .compatible =3D "fsl,p5020-clockgen", .data =3D &sdata[1], }, @@
> > -273,61 +341,43 @@ static const struct of_device_id node_matches[]
> __initdata =3D {
> > {}
> > };
> >
> > -static int __init ppc_corenet_cpufreq_init(void)
> > +static int __init qoriq_cpufreq_init(void)
> > {
> > int ret;
> > struct device_node *np;
> > const struct of_device_id *match;
> > const struct soc_data *data;
> > - unsigned int cpu;
> >
> > np =3D of_find_matching_node(NULL, node_matches);
> > if (!np)
> > return -ENODEV;
> >
> > - for_each_possible_cpu(cpu) {
> > - if (!alloc_cpumask_var(&per_cpu(cpu_mask, cpu), GFP_KERNEL))
> > - goto err_mask;
> > - cpumask_copy(per_cpu(cpu_mask, cpu), cpu_core_mask(cpu));
> > - }
> > -
> > match =3D of_match_node(node_matches, np);
> > data =3D match->data;
> > if (data) {
> > if (data->flag)
> > fmask =3D data->freq_mask;
> > - min_cpufreq =3D fsl_get_sys_freq();
> > + min_cpufreq =3D get_bus_freq();
> > } else {
> > - min_cpufreq =3D fsl_get_sys_freq() / 2;
> > + min_cpufreq =3D get_bus_freq() / 2;
> > }
> >
> > of_node_put(np);
> >
> > - ret =3D cpufreq_register_driver(&ppc_corenet_cpufreq_driver);
> > + ret =3D cpufreq_register_driver(&qoriq_cpufreq_driver);
> > if (!ret)
> > - pr_info("Freescale PowerPC corenet CPU frequency scaling driver\n");
> > + pr_info("Freescale QorIQ CPU frequency scaling driver\n");
> >
> > return ret;
> > -
> > -err_mask:
> > - for_each_possible_cpu(cpu)
> > - free_cpumask_var(per_cpu(cpu_mask, cpu));
> > -
> > - return -ENOMEM;
> > }
> > -module_init(ppc_corenet_cpufreq_init);
> > +module_init(qoriq_cpufreq_init);
> >
> > -static void __exit ppc_corenet_cpufreq_exit(void)
> > +static void __exit qoriq_cpufreq_exit(void)
> > {
> > - unsigned int cpu;
> > -
> > - for_each_possible_cpu(cpu)
> > - free_cpumask_var(per_cpu(cpu_mask, cpu));
> > -
> > - cpufreq_unregister_driver(&ppc_corenet_cpufreq_driver);
> > + cpufreq_unregister_driver(&qoriq_cpufreq_driver);
> > }
> > -module_exit(ppc_corenet_cpufreq_exit);
> > +module_exit(qoriq_cpufreq_exit);
> >
> > MODULE_LICENSE("GPL");
> > MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
> > -MODULE_DESCRIPTION("cpufreq driver for Freescale e500mc series
> > SoCs");
> > +MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");
> > --
> > 2.1.0.27.g96db324
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe
> > linux-kernel" in the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
> > Please read the FAQ at http://www.tux.org/lkml/
^ permalink raw reply
* Re: [PATCH] powerpc/pseries: Quieten relocation on exceptions warning
From: Michael Neuling @ 2014-10-19 23:03 UTC (permalink / raw)
To: Anton Blanchard; +Cc: mikey, paulus, linuxppc-dev
In-Reply-To: <1413755489-28682-1-git-send-email-anton@samba.org>
> The hypervisor returns H_P2 if relocation on exceptions are
> not supported. If we get this, just print a lower priority
> informational message.
Can you add something about why this is needed? Something about
h_set_mode being available so we can enable LE but not supporting any of
the other calls like AIL?
Mikey
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
> arch/powerpc/platforms/pseries/setup.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>=20
> diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platfo=
rms/pseries/setup.c
> index 125c589..fcc9227 100644
> --- a/arch/powerpc/platforms/pseries/setup.c
> +++ b/arch/powerpc/platforms/pseries/setup.c
> @@ -499,7 +499,11 @@ static void __init pSeries_setup_arch(void)
> =20
> if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
> long rc;
> - if ((rc =3D pSeries_enable_reloc_on_exc()) !=3D H_SUCCESS) {
> +
> + rc =3D pSeries_enable_reloc_on_exc();
> + if (rc =3D=3D H_P2) {
> + pr_info("Relocation on exceptions not supported\n");
> + } else if (rc !=3D H_SUCCESS) {
> pr_warn("Unable to enable relocation on exceptions: "
> "%ld\n", rc);
> }
^ permalink raw reply
* [PATCH] powerpc/pseries: Quieten relocation on exceptions warning
From: Anton Blanchard @ 2014-10-19 21:51 UTC (permalink / raw)
To: benh, paulus, mpe, mikey; +Cc: linuxppc-dev
The hypervisor returns H_P2 if relocation on exceptions are
not supported. If we get this, just print a lower priority
informational message.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
arch/powerpc/platforms/pseries/setup.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 125c589..fcc9227 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -499,7 +499,11 @@ static void __init pSeries_setup_arch(void)
if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
long rc;
- if ((rc = pSeries_enable_reloc_on_exc()) != H_SUCCESS) {
+
+ rc = pSeries_enable_reloc_on_exc();
+ if (rc == H_P2) {
+ pr_info("Relocation on exceptions not supported\n");
+ } else if (rc != H_SUCCESS) {
pr_warn("Unable to enable relocation on exceptions: "
"%ld\n", rc);
}
--
1.9.1
^ permalink raw reply related
* [PATCH v2 3/3] clk: ppc-corenet: fix section mismatch warning
From: Kevin Hao @ 2014-10-19 6:11 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Gerhard Sittig, Mike Turquette, Jingchang Lu
In-Reply-To: <1413699099-25743-1-git-send-email-haokexin@gmail.com>
In order to fix the following section mismatch warning:
WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference from the variable ppc_corenet_clk_driver to the function .init.text:ppc_corenet_clk_probe()
The variable ppc_corenet_clk_driver references
the function __init ppc_corenet_clk_probe()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
WARNING: drivers/clk/built-in.o(.data+0x10c): Section mismatch in reference from the variable ppc_corenet_clk_driver to the variable .init.rodata:ppc_clk_ids
The variable ppc_corenet_clk_driver references
the variable __initconst ppc_clk_ids
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
We can't just add the __init annotation to ppc_corenet_clk_driver or
remove the __init from ppc_corenet_clk_probe() and ppc_clk_ids.
So choose to use CLK_OF_DECLARE to scan and init the clock devices.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
v2: Avoid to invoke of_clk_init() in a board specific file.
drivers/clk/clk-ppc-corenet.c | 43 ++++++-------------------------------------
1 file changed, 6 insertions(+), 37 deletions(-)
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
index 8b284be4efa4..bf0fe565ce4e 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-ppc-corenet.c
@@ -268,40 +268,9 @@ static void __init sysclk_init(struct device_node *node)
of_clk_add_provider(np, of_clk_src_simple_get, clk);
}
-static const struct of_device_id clk_match[] __initconst = {
- { .compatible = "fsl,qoriq-sysclk-1.0", .data = sysclk_init, },
- { .compatible = "fsl,qoriq-sysclk-2.0", .data = sysclk_init, },
- { .compatible = "fsl,qoriq-core-pll-1.0", .data = core_pll_init, },
- { .compatible = "fsl,qoriq-core-pll-2.0", .data = core_pll_init, },
- { .compatible = "fsl,qoriq-core-mux-1.0", .data = core_mux_init, },
- { .compatible = "fsl,qoriq-core-mux-2.0", .data = core_mux_init, },
- {}
-};
-
-static int __init ppc_corenet_clk_probe(struct platform_device *pdev)
-{
- of_clk_init(clk_match);
-
- return 0;
-}
-
-static const struct of_device_id ppc_clk_ids[] __initconst = {
- { .compatible = "fsl,qoriq-clockgen-1.0", },
- { .compatible = "fsl,qoriq-clockgen-2.0", },
- {}
-};
-
-static struct platform_driver ppc_corenet_clk_driver = {
- .driver = {
- .name = "ppc_corenet_clock",
- .owner = THIS_MODULE,
- .of_match_table = ppc_clk_ids,
- },
- .probe = ppc_corenet_clk_probe,
-};
-
-static int __init ppc_corenet_clk_init(void)
-{
- return platform_driver_register(&ppc_corenet_clk_driver);
-}
-subsys_initcall(ppc_corenet_clk_init);
+CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
+CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
+CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
+CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
+CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
+CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
--
1.9.3
^ permalink raw reply related
* [PATCH v2 2/3] powerpc: call of_clk_init() from time_init()
From: Kevin Hao @ 2014-10-19 6:11 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Gerhard Sittig, Mike Turquette, Jingchang Lu
In-Reply-To: <1413699099-25743-1-git-send-email-haokexin@gmail.com>
So the boards which has COMMON_CLK enabled don't have to
invoke this in its board specific file.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
A new patch in v2.
arch/powerpc/kernel/time.c | 5 +++++
arch/powerpc/platforms/512x/clock-commonclk.c | 11 +++++------
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 7505599c2593..8d3893e7564c 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -54,6 +54,7 @@
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/irq_work.h>
+#include <linux/clk-provider.h>
#include <asm/trace.h>
#include <asm/io.h>
@@ -943,6 +944,10 @@ void __init time_init(void)
init_decrementer_clockevent();
tick_setup_hrtimer_broadcast();
+
+#ifdef CONFIG_COMMON_CLK
+ of_clk_init(NULL);
+#endif
}
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 6eb614a271fb..f691bcabd710 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -1168,6 +1168,11 @@ static void mpc5121_clk_provide_backwards_compat(void)
}
}
+/*
+ * The "fixed-clock" nodes (which includes the oscillator node if the board's
+ * DT provides one) has already been scanned by the of_clk_init() in
+ * time_init().
+ */
int __init mpc5121_clk_init(void)
{
struct device_node *clk_np;
@@ -1187,12 +1192,6 @@ int __init mpc5121_clk_init(void)
mpc512x_clk_preset_data();
/*
- * have the device tree scanned for "fixed-clock" nodes (which
- * includes the oscillator node if the board's DT provides one)
- */
- of_clk_init(NULL);
-
- /*
* add a dummy clock for those situations where a clock spec is
* required yet no real clock is involved
*/
--
1.9.3
^ permalink raw reply related
* [PATCH v2 1/3] Revert "clk: ppc-corenet: Fix Section mismatch warning"
From: Kevin Hao @ 2014-10-19 6:11 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Gerhard Sittig, Mike Turquette, Jingchang Lu
In-Reply-To: <1413699099-25743-1-git-send-email-haokexin@gmail.com>
This reverts commit da788acb28386aa896224e784954bb73c99ff26c.
That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section. This is definitely wrong
because the kernel would free the memories occupied by this struct
after boot while this driver is still registered in the driver core.
The kernel would panic when accessing this driver struct.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
A new patch in v2.
drivers/clk/clk-ppc-corenet.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
index 8e58edfeeb37..8b284be4efa4 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-ppc-corenet.c
@@ -291,7 +291,7 @@ static const struct of_device_id ppc_clk_ids[] __initconst = {
{}
};
-static struct platform_driver ppc_corenet_clk_driver __initdata = {
+static struct platform_driver ppc_corenet_clk_driver = {
.driver = {
.name = "ppc_corenet_clock",
.owner = THIS_MODULE,
--
1.9.3
^ permalink raw reply related
* [PATCH v2 0/3] fix a kernel panic on fsl corenet board when CONFIG_CLK_PPC_CORENET is enabled
From: Kevin Hao @ 2014-10-19 6:11 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Gerhard Sittig, Mike Turquette, Jingchang Lu
Hi,
I have done a boot test on p2014rdb and t4240qds boards. I don't have an access
to mpc512x board, so only build test for that.
v2:
- Revert the commit da788acb2838 first.
- Invoke of_clk_init() from a common place.
v1
This tries to fix a kernel panic introduced by commit da788acb2838
("clk: ppc-corenet: Fix Section mismatch warning").
Kevin Hao (3):
Revert "clk: ppc-corenet: Fix Section mismatch warning"
powerpc: call of_clk_init() from time_init()
clk: ppc-corenet: fix section mismatch warning
arch/powerpc/kernel/time.c | 5 ++++
arch/powerpc/platforms/512x/clock-commonclk.c | 11 ++++---
drivers/clk/clk-ppc-corenet.c | 43 ++++-----------------------
3 files changed, 16 insertions(+), 43 deletions(-)
--
1.9.3
^ permalink raw reply
* Re: [PATCH 2/2] clk: ppc-corenet: don't use platform_driver to init the clock device
From: Kevin Hao @ 2014-10-19 5:52 UTC (permalink / raw)
To: Scott Wood; +Cc: Gerhard Sittig, Jingchang Lu, linuxppc-dev, Mike Turquette
In-Reply-To: <1413525535.7417.27.camel@aoeu.buserror.net>
[-- Attachment #1: Type: text/plain, Size: 800 bytes --]
On Fri, Oct 17, 2014 at 07:58:55AM +0200, Scott Wood wrote:
> On Fri, 2014-10-17 at 06:55 +0800, Kevin Hao wrote:
> > I have thought about to put it in a more common place such as time_init(),
> > but this will be in conflict with mpc512x board. How about add an
> > arch_initcall(mpc85xx_clk_init) in arch/powerpc/platforms/85xx/common.c?
>
> Gerhard, does 512x really require of_clk_init() to be called at that
> specific time, or can it be replaced by a common of_clk_init()?
I have took a look at the mpc5121_clk_init() and it seems that the
of_clk_init() is only used to scan the 'fixed-clock' in the DT. So I think
it should be safe to invoke it a bit earlier in a common place. I will create
v2 to use this method.
Gerhard, please correct me if I am wrong.
Thanks,
Kevin
[-- Attachment #2: Type: application/pgp-signature, Size: 473 bytes --]
^ permalink raw reply
* [PATCH 2/2] powerpc/numa: ensure per-cpu NUMA mappings are correct on topology update
From: Nishanth Aravamudan @ 2014-10-18 0:50 UTC (permalink / raw)
To: Michael Ellerman
Cc: Li Zhong, Paul Mackerras, Michael Wang, linuxppc-dev, jstancek
In-Reply-To: <20141018004944.GA3969@linux.vnet.ibm.com>
We received a report of warning in kernel/sched/core.c where the sched
group was NULL on an LPAR after a topology update. This seems to occur
because after the topology update has moved the CPUs, cpu_to_node is
returning the old value still, which ends up breaking the consistency of
the NUMA topology in the per-cpu maps. Ensure that we update the per-cpu
fields when we re-map CPUs.
Signed-off-by: Nishanth Aravamudan <nacc@linux.vnet.ibm.com>
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 86fdb004ad2f..048be62dc979 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -1488,11 +1488,14 @@ static int update_cpu_topology(void *data)
cpu = smp_processor_id();
for (update = data; update; update = update->next) {
+ int new_nid = update->new_nid;
if (cpu != update->cpu)
continue;
unmap_cpu_from_node(cpu);
- map_cpu_to_node(cpu, update->new_nid);
+ map_cpu_to_node(cpu, new_nid);
+ set_cpu_numa_node(cpu, new_nid);
+ set_cpu_numa_mem(cpu, local_memory_node(new_nid));
vdso_getcpu_init();
}
^ permalink raw reply related
* [PATCH 1/2] powerpc/numa: use cached value of update->cpu in update_cpu_topology
From: Nishanth Aravamudan @ 2014-10-18 0:49 UTC (permalink / raw)
To: Michael Ellerman
Cc: Li Zhong, Paul Mackerras, Michael Wang, linuxppc-dev, jstancek
There isn't any need to keep referring to update->cpu, as we've already
checked cpu == update->cpu at this point.
Signed-off-by: Nishanth Aravamudan <nacc@linux.vnet.ibm.com>
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 649666d5d1c2..86fdb004ad2f 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -1491,8 +1491,8 @@ static int update_cpu_topology(void *data)
if (cpu != update->cpu)
continue;
- unmap_cpu_from_node(update->cpu);
- map_cpu_to_node(update->cpu, update->new_nid);
+ unmap_cpu_from_node(cpu);
+ map_cpu_to_node(cpu, update->new_nid);
vdso_getcpu_init();
}
^ permalink raw reply related
* Re: [PATCH] MAINTAINERS: nx-842 driver maintainer change
From: Nathan Fontenot @ 2014-10-18 0:00 UTC (permalink / raw)
To: Dan Streetman, Michael Ellerman, benh; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <1413587999-12684-1-git-send-email-ddstreet@ieee.org>
On 10/17/2014 06:19 PM, Dan Streetman wrote:
> Change maintainer of nx-842 compression coprocessor driver
> to Dan Streetman.
>
> Signed-off-by: Dan Streetman <ddstreet@ieee.org>
> Cc: Nathan Fontenot <nfont@linux.vnet.ibm.com>
Acked-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b0f17d5..3cc3e41 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -4605,7 +4605,7 @@ S: Supported
> F: drivers/crypto/nx/
>
> IBM Power 842 compression accelerator
> -M: Nathan Fontenot <nfont@linux.vnet.ibm.com>
> +M: Dan Streetman <ddstreet@us.ibm.com>
> S: Supported
> F: drivers/crypto/nx/nx-842.c
> F: include/linux/nx842.h
>
^ permalink raw reply
* [PATCH] MAINTAINERS: nx-842 driver maintainer change
From: Dan Streetman @ 2014-10-17 23:19 UTC (permalink / raw)
To: Michael Ellerman, benh, nfont; +Cc: linuxppc-dev, linux-kernel, Dan Streetman
Change maintainer of nx-842 compression coprocessor driver
to Dan Streetman.
Signed-off-by: Dan Streetman <ddstreet@ieee.org>
Cc: Nathan Fontenot <nfont@linux.vnet.ibm.com>
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index b0f17d5..3cc3e41 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4605,7 +4605,7 @@ S: Supported
F: drivers/crypto/nx/
IBM Power 842 compression accelerator
-M: Nathan Fontenot <nfont@linux.vnet.ibm.com>
+M: Dan Streetman <ddstreet@us.ibm.com>
S: Supported
F: drivers/crypto/nx/nx-842.c
F: include/linux/nx842.h
--
1.8.3.1
^ permalink raw reply related
* Re: [PATCH] drivers/crypto/nx: prevent oops on module exit
From: Dan Streetman @ 2014-10-17 22:05 UTC (permalink / raw)
To: Benjamin Herrenschmidt, nfont
Cc: linuxppc-dev, Seth Jennings, Robert Jennings
In-Reply-To: <1413499949.4567.3.camel@pasglop>
Yep, I own the driver now, I'll send a maintainers patch.
On Thu, Oct 16, 2014 at 6:52 PM, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
> On Fri, 2014-10-17 at 09:43 +1100, Michael Ellerman wrote:
>> On Thu, 2014-10-16 at 15:30 -0400, Dan Streetman wrote:
>> > Check old_devdata->dev in nx-842 driver before accessing it, as
>> > on systems without any nx-842 hardware, the ->dev will never be
>> > set. Currently, the module will cause an oops during unload
>> > since old_devdata->dev is null.
>>
>> Hi Dan,
>>
>> Patch looks reasonable. But I can't merge it, at least not without an ACK:
>>
>> $ ./scripts/get_maintainer.pl -f drivers/crypto/nx/
>> Nathan Fontenot <nfont@linux.vnet.ibm.com> (supporter:IBM Power 842 com...)
>> Marcelo Henrique Cerri <mhcerri@linux.vnet.ibm.com> (supporter:IBM Power in-Nest...)
>> Fionnuala Gunter <fin@linux.vnet.ibm.com> (supporter:IBM Power in-Nest...)
>> Herbert Xu <herbert@gondor.apana.org.au> (maintainer:CRYPTO API)
>> "David S. Miller" <davem@davemloft.net> (maintainer:CRYPTO API)
>> linux-crypto@vger.kernel.org (open list:IBM Power in-Nest...)
>> linux-kernel@vger.kernel.org (open list)
>>
>>
>> If any of the above is out of date please send me a patch for MAINTAINERS.
>
> I think Dan now owns that driver, Dan, please confirm.
>
> Cheers,
> Ben.
>
>
^ permalink raw reply
* [PATCH] drivers: depend on instead of select BACKLIGHT_CLASS_DEVICE and ACPI_VIDEO
From: Jani Nikula @ 2014-10-17 21:13 UTC (permalink / raw)
To: linux-kernel, dri-devel, linuxppc-dev, platform-driver-x86,
linux-usb, linux-fbdev
Cc: Daniel Drake, Jens Frederich, Jani Nikula, Greg Kroah-Hartman,
Jon Nettleton, Randy Dunlap, David Airlie, Tomi Valkeinen,
Laurent Pinchart, Daniel Vetter, Darren Hart,
Jean-Christophe Plagniol-Villard
Documentation/kbuild/kconfig-language.txt warns to use select with care,
and in general use select only for non-visible symbols and for symbols
with no dependencies, because select will force a symbol to a value
without visiting the dependencies.
Select has become particularly problematic, interdependently, with the
BACKLIGHT_CLASS_DEVICE and ACPI_VIDEO configs. For example:
scripts/kconfig/conf --randconfig Kconfig
KCONFIG_SEED=0x48312B00
warning: (DRM_RADEON && DRM_NOUVEAU && DRM_I915 && DRM_GMA500 &&
DRM_SHMOBILE && DRM_TILCDC && FB_BACKLIGHT && FB_MX3 && USB_APPLEDISPLAY
&& FB_OLPC_DCON && ASUS_LAPTOP && SONY_LAPTOP && THINKPAD_ACPI &&
EEEPC_LAPTOP && ACPI_CMPC && SAMSUNG_Q10) selects BACKLIGHT_CLASS_DEVICE
which has unmet direct dependencies (HAS_IOMEM && BACKLIGHT_LCD_SUPPORT)
warning: (DRM_RADEON && DRM_NOUVEAU && DRM_I915 && DRM_GMA500 &&
DRM_SHMOBILE && DRM_TILCDC && FB_BACKLIGHT && FB_MX3 && USB_APPLEDISPLAY
&& FB_OLPC_DCON && ASUS_LAPTOP && SONY_LAPTOP && THINKPAD_ACPI &&
EEEPC_LAPTOP && ACPI_CMPC && SAMSUNG_Q10) selects BACKLIGHT_CLASS_DEVICE
which has unmet direct dependencies (HAS_IOMEM && BACKLIGHT_LCD_SUPPORT)
With tristates it's possible to end up selecting FOO=y depending on
BAR=m in the config, which gets discovered at build time, not config
time, like reported in the thread referenced below.
Do the following to fix the dependencies:
* Depend on instead of select BACKLIGHT_CLASS_DEVICE everywhere. Drop
select BACKLIGHT_LCD_SUPPORT in such cases, as it's a dependency of
BACKLIGHT_CLASS_DEVICE.
* Remove config FB_BACKLIGHT altogether, and replace it with a
dependency on BACKLIGHT_CLASS_DEVICE. All configs selecting
FB_BACKLIGHT select or depend on FB anyway, so we can simplify.
* Depend on (ACPI && ACPI_VIDEO) || ACPI=n in several places instead of
selecting ACPI_VIDEO and a number of its dependencies if ACPI is
enabled. This is tied to backlight, as ACPI_VIDEO depends on
BACKLIGHT_CLASS_DEVICE.
* Replace a couple of select INPUT/VT with depends as it seemed to be
necessary.
Reference: http://lkml.kernel.org/r/CA+r1ZhhmT4DrWtf6MbRQo5EqXwx+LxCqh15Vsu_d9WpftLhnxw@mail.gmail.com
Reported-by: Jim Davis <jim.epost@gmail.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Darren Hart <dvhart@infradead.org>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Jens Frederich <jfrederich@gmail.com>
Cc: Daniel Drake <dsd@laptop.org>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
Sorry for the huge distribution; this is really quite hard to split up
sensibly without breaking the build!
---
drivers/gpu/drm/Kconfig | 2 +-
drivers/gpu/drm/gma500/Kconfig | 4 +---
drivers/gpu/drm/i915/Kconfig | 9 ++-------
drivers/gpu/drm/nouveau/Kconfig | 10 ++--------
drivers/gpu/drm/shmobile/Kconfig | 2 +-
drivers/gpu/drm/tilcdc/Kconfig | 3 +--
drivers/macintosh/Kconfig | 2 +-
drivers/platform/x86/Kconfig | 19 ++++++++-----------
drivers/staging/olpc_dcon/Kconfig | 2 +-
drivers/usb/misc/Kconfig | 3 +--
drivers/video/fbdev/Kconfig | 29 +++++++++++------------------
drivers/video/fbdev/core/fbsysfs.c | 8 ++++----
include/linux/fb.h | 2 +-
include/uapi/linux/fb.h | 2 +-
14 files changed, 36 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index e3b4b0f02b3d..dc789d0e293c 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -99,6 +99,7 @@ config DRM_R128
config DRM_RADEON
tristate "ATI Radeon"
depends on DRM && PCI
+ depends on BACKLIGHT_CLASS_DEVICE || BACKLIGHT_CLASS_DEVICE=n
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
@@ -108,7 +109,6 @@ config DRM_RADEON
select DRM_TTM
select POWER_SUPPLY
select HWMON
- select BACKLIGHT_CLASS_DEVICE
select INTERVAL_TREE
select MMU_NOTIFIER
help
diff --git a/drivers/gpu/drm/gma500/Kconfig b/drivers/gpu/drm/gma500/Kconfig
index 17f928ec84ea..a84d0a4fcc58 100644
--- a/drivers/gpu/drm/gma500/Kconfig
+++ b/drivers/gpu/drm/gma500/Kconfig
@@ -8,9 +8,7 @@ config DRM_GMA500
select DRM_KMS_FB_HELPER
select DRM_TTM
# GMA500 depends on ACPI_VIDEO when ACPI is enabled, just like i915
- select ACPI_VIDEO if ACPI
- select BACKLIGHT_CLASS_DEVICE if ACPI
- select INPUT if ACPI
+ depends on (ACPI && ACPI_VIDEO) || ACPI=n
help
Say yes for an experimental 2D KMS framebuffer driver for the
Intel GMA500 ('Poulsbo') and other Intel IMG based graphics
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 4e39ab34eb1c..75d4c52c0971 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -3,6 +3,8 @@ config DRM_I915
depends on DRM
depends on X86 && PCI
depends on (AGP || AGP=n)
+ depends on (ACPI && ACPI_VIDEO) || ACPI=n
+ depends on BACKLIGHT_CLASS_DEVICE || BACKLIGHT_CLASS_DEVICE=n
select INTEL_GTT
select AGP_INTEL if AGP
select INTERVAL_TREE
@@ -11,13 +13,6 @@ config DRM_I915
select SHMEM
select TMPFS
select DRM_KMS_HELPER
- # i915 depends on ACPI_VIDEO when ACPI is enabled
- # but for select to work, need to select ACPI_VIDEO's dependencies, ick
- select BACKLIGHT_LCD_SUPPORT if ACPI
- select BACKLIGHT_CLASS_DEVICE if ACPI
- select INPUT if ACPI
- select ACPI_VIDEO if ACPI
- select ACPI_BUTTON if ACPI
help
Choose this option if you have a system that has "Intel Graphics
Media Accelerator" or "HD Graphics" integrated graphics,
diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig
index 40afc69a3778..40227fc4f284 100644
--- a/drivers/gpu/drm/nouveau/Kconfig
+++ b/drivers/gpu/drm/nouveau/Kconfig
@@ -1,6 +1,7 @@
config DRM_NOUVEAU
tristate "Nouveau (NVIDIA) cards"
depends on DRM && PCI
+ depends on (ACPI && ACPI_VIDEO) || ACPI=n
select FW_LOADER
select DRM_KMS_HELPER
select DRM_KMS_FB_HELPER
@@ -10,18 +11,10 @@ config DRM_NOUVEAU
select FB_CFB_IMAGEBLIT
select FB
select FRAMEBUFFER_CONSOLE if !EXPERT
- select FB_BACKLIGHT if DRM_NOUVEAU_BACKLIGHT
- select ACPI_VIDEO if ACPI && X86 && BACKLIGHT_CLASS_DEVICE && INPUT
select X86_PLATFORM_DEVICES if ACPI && X86
select ACPI_WMI if ACPI && X86
select MXM_WMI if ACPI && X86
select POWER_SUPPLY
- # Similar to i915, we need to select ACPI_VIDEO and it's dependencies
- select BACKLIGHT_LCD_SUPPORT if ACPI && X86
- select BACKLIGHT_CLASS_DEVICE if ACPI && X86
- select INPUT if ACPI && X86
- select THERMAL if ACPI && X86
- select ACPI_VIDEO if ACPI && X86
help
Choose this option for open-source NVIDIA support.
@@ -64,6 +57,7 @@ config NOUVEAU_DEBUG_DEFAULT
config DRM_NOUVEAU_BACKLIGHT
bool "Support for backlight control"
depends on DRM_NOUVEAU
+ depends on BACKLIGHT_CLASS_DEVICE
default y
help
Say Y here if you want to control the backlight of your display
diff --git a/drivers/gpu/drm/shmobile/Kconfig b/drivers/gpu/drm/shmobile/Kconfig
index a50fe0eeaa0d..71c00f3c0fbc 100644
--- a/drivers/gpu/drm/shmobile/Kconfig
+++ b/drivers/gpu/drm/shmobile/Kconfig
@@ -2,7 +2,7 @@ config DRM_SHMOBILE
tristate "DRM Support for SH Mobile"
depends on DRM && ARM
depends on ARCH_SHMOBILE || COMPILE_TEST
- select BACKLIGHT_CLASS_DEVICE
+ depends on BACKLIGHT_CLASS_DEVICE
select DRM_KMS_HELPER
select DRM_KMS_FB_HELPER
select DRM_KMS_CMA_HELPER
diff --git a/drivers/gpu/drm/tilcdc/Kconfig b/drivers/gpu/drm/tilcdc/Kconfig
index 7c3ef79fcb37..52e60feaae53 100644
--- a/drivers/gpu/drm/tilcdc/Kconfig
+++ b/drivers/gpu/drm/tilcdc/Kconfig
@@ -1,13 +1,12 @@
config DRM_TILCDC
tristate "DRM Support for TI LCDC Display Controller"
depends on DRM && OF && ARM
+ depends on BACKLIGHT_CLASS_DEVICE
select DRM_KMS_HELPER
select DRM_KMS_FB_HELPER
select DRM_KMS_CMA_HELPER
select DRM_GEM_CMA_HELPER
select VIDEOMODE_HELPERS
- select BACKLIGHT_CLASS_DEVICE
- select BACKLIGHT_LCD_SUPPORT
help
Choose this option if you have an TI SoC with LCDC display
controller, for example AM33xx in beagle-bone, DA8xx, or
diff --git a/drivers/macintosh/Kconfig b/drivers/macintosh/Kconfig
index 3067d56b11a6..50cb2c3b567e 100644
--- a/drivers/macintosh/Kconfig
+++ b/drivers/macintosh/Kconfig
@@ -135,7 +135,7 @@ config PMAC_MEDIABAY
config PMAC_BACKLIGHT
bool "Backlight control for LCD screens"
depends on ADB_PMU && FB = y && (BROKEN || !PPC64)
- select FB_BACKLIGHT
+ depends on BACKLIGHT_CLASS_DEVICE
help
Say Y here to enable Macintosh specific extensions of the generic
backlight code. With this enabled, the brightness keys on older
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index 4dcfb7116a04..63e99ce0e3f8 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -17,7 +17,7 @@ if X86_PLATFORM_DEVICES
config ACER_WMI
tristate "Acer WMI Laptop Extras"
- depends on ACPI
+ depends on ACPI && ACPI_VIDEO
select LEDS_CLASS
select NEW_LEDS
depends on BACKLIGHT_CLASS_DEVICE
@@ -26,8 +26,6 @@ config ACER_WMI
depends on RFKILL || RFKILL = n
depends on ACPI_WMI
select INPUT_SPARSEKMAP
- # Acer WMI depends on ACPI_VIDEO when ACPI is enabled
- select ACPI_VIDEO if ACPI
---help---
This is a driver for newer Acer (and Wistron) laptops. It adds
wireless radio and bluetooth control, and on some laptops,
@@ -70,7 +68,7 @@ config ASUS_LAPTOP
depends on ACPI
select LEDS_CLASS
select NEW_LEDS
- select BACKLIGHT_CLASS_DEVICE
+ depends on BACKLIGHT_CLASS_DEVICE
depends on INPUT
depends on RFKILL || RFKILL = n
select INPUT_SPARSEKMAP
@@ -294,7 +292,7 @@ config COMPAL_LAPTOP
config SONY_LAPTOP
tristate "Sony Laptop Extras"
depends on ACPI
- select BACKLIGHT_CLASS_DEVICE
+ depends on BACKLIGHT_CLASS_DEVICE
depends on INPUT
depends on RFKILL
---help---
@@ -329,8 +327,7 @@ config THINKPAD_ACPI
depends on ACPI
depends on INPUT
depends on RFKILL || RFKILL = n
- select BACKLIGHT_LCD_SUPPORT
- select BACKLIGHT_CLASS_DEVICE
+ depends on BACKLIGHT_CLASS_DEVICE
select HWMON
select NVRAM
select NEW_LEDS
@@ -499,7 +496,7 @@ config EEEPC_LAPTOP
depends on INPUT
depends on RFKILL || RFKILL = n
depends on HOTPLUG_PCI
- select BACKLIGHT_CLASS_DEVICE
+ depends on BACKLIGHT_CLASS_DEVICE
select HWMON
select LEDS_CLASS
select NEW_LEDS
@@ -675,8 +672,8 @@ config ACPI_CMPC
tristate "CMPC Laptop Extras"
depends on X86 && ACPI
depends on RFKILL || RFKILL=n
- select INPUT
- select BACKLIGHT_CLASS_DEVICE
+ depends on INPUT
+ depends on BACKLIGHT_CLASS_DEVICE
default n
help
Support for Intel Classmate PC ACPI devices, including some
@@ -805,7 +802,7 @@ config INTEL_OAKTRAIL
config SAMSUNG_Q10
tristate "Samsung Q10 Extras"
depends on ACPI
- select BACKLIGHT_CLASS_DEVICE
+ depends on BACKLIGHT_CLASS_DEVICE
---help---
This driver provides support for backlight control on Samsung Q10
and related laptops, including Dell Latitude X200.
diff --git a/drivers/staging/olpc_dcon/Kconfig b/drivers/staging/olpc_dcon/Kconfig
index d277f048789e..94acb4279704 100644
--- a/drivers/staging/olpc_dcon/Kconfig
+++ b/drivers/staging/olpc_dcon/Kconfig
@@ -3,7 +3,7 @@ config FB_OLPC_DCON
depends on OLPC && FB
depends on I2C
depends on (GPIO_CS5535 || GPIO_CS5535=n)
- select BACKLIGHT_CLASS_DEVICE
+ depends on BACKLIGHT_CLASS_DEVICE
---help---
In order to support very low power operation, the XO laptop uses a
secondary Display CONtroller, or DCON. This secondary controller
diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig
index 76d77206e011..824630b09662 100644
--- a/drivers/usb/misc/Kconfig
+++ b/drivers/usb/misc/Kconfig
@@ -150,8 +150,7 @@ config USB_FTDI_ELAN
config USB_APPLEDISPLAY
tristate "Apple Cinema Display support"
- select BACKLIGHT_LCD_SUPPORT
- select BACKLIGHT_CLASS_DEVICE
+ depends on BACKLIGHT_CLASS_DEVICE
help
Say Y here if you want to control the backlight of Apple Cinema
Displays over USB. This driver provides a sysfs interface.
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index ccbe2ae22ac5..8cae7da2c723 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -185,13 +185,6 @@ config FB_MACMODES
depends on FB
default n
-config FB_BACKLIGHT
- bool
- depends on FB
- select BACKLIGHT_LCD_SUPPORT
- select BACKLIGHT_CLASS_DEVICE
- default n
-
config FB_MODE_HELPERS
bool "Enable Video Mode Handling Helpers"
depends on FB
@@ -323,7 +316,7 @@ config FB_CLPS711X
tristate "CLPS711X LCD support"
depends on FB && (ARCH_CLPS711X || COMPILE_TEST)
select FB_CLPS711X_OLD if ARCH_CLPS711X && !ARCH_MULTIPLATFORM
- select BACKLIGHT_LCD_SUPPORT
+ depends on BACKLIGHT_LCD_SUPPORT
select FB_MODE_HELPERS
select FB_SYS_FILLRECT
select FB_SYS_COPYAREA
@@ -351,7 +344,7 @@ config FB_SA1100
config FB_IMX
tristate "Freescale i.MX1/21/25/27 LCD support"
depends on FB && ARCH_MXC
- select BACKLIGHT_LCD_SUPPORT
+ depends on BACKLIGHT_LCD_SUPPORT
select LCD_CLASS_DEVICE
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
@@ -674,7 +667,7 @@ config FB_STI
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
select STI_CONSOLE
- select VT
+ depends on VT
default y
---help---
STI refers to the HP "Standard Text Interface" which is a set of
@@ -990,7 +983,7 @@ config FB_S1D13XXX
config FB_ATMEL
tristate "AT91/AT32 LCD Controller support"
depends on FB && HAVE_FB_ATMEL
- select FB_BACKLIGHT
+ depends on BACKLIGHT_CLASS_DEVICE
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
@@ -1019,7 +1012,6 @@ config FB_ATMEL_STN
config FB_NVIDIA
tristate "nVidia Framebuffer Support"
depends on FB && PCI
- select FB_BACKLIGHT if FB_NVIDIA_BACKLIGHT
select FB_MODE_HELPERS
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
@@ -1060,6 +1052,7 @@ config FB_NVIDIA_DEBUG
config FB_NVIDIA_BACKLIGHT
bool "Support for backlight control"
depends on FB_NVIDIA
+ depends on BACKLIGHT_CLASS_DEVICE
default y
help
Say Y here if you want to control the backlight of your display.
@@ -1067,7 +1060,6 @@ config FB_NVIDIA_BACKLIGHT
config FB_RIVA
tristate "nVidia Riva support"
depends on FB && PCI
- select FB_BACKLIGHT if FB_RIVA_BACKLIGHT
select FB_MODE_HELPERS
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
@@ -1107,6 +1099,7 @@ config FB_RIVA_DEBUG
config FB_RIVA_BACKLIGHT
bool "Support for backlight control"
depends on FB_RIVA
+ depends on BACKLIGHT_CLASS_DEVICE
default y
help
Say Y here if you want to control the backlight of your display.
@@ -1345,7 +1338,6 @@ config FB_MATROX_MAVEN
config FB_RADEON
tristate "ATI Radeon display support"
depends on FB && PCI
- select FB_BACKLIGHT if FB_RADEON_BACKLIGHT
select FB_MODE_HELPERS
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
@@ -1370,6 +1362,7 @@ config FB_RADEON_I2C
config FB_RADEON_BACKLIGHT
bool "Support for backlight control"
depends on FB_RADEON
+ depends on BACKLIGHT_CLASS_DEVICE
default y
help
Say Y here if you want to control the backlight of your display.
@@ -1389,7 +1382,6 @@ config FB_ATY128
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
- select FB_BACKLIGHT if FB_ATY128_BACKLIGHT
select FB_MACMODES if PPC_PMAC
help
This driver supports graphics boards with the ATI Rage128 chips.
@@ -1402,6 +1394,7 @@ config FB_ATY128
config FB_ATY128_BACKLIGHT
bool "Support for backlight control"
depends on FB_ATY128
+ depends on BACKLIGHT_CLASS_DEVICE
default y
help
Say Y here if you want to control the backlight of your display.
@@ -1412,7 +1405,6 @@ config FB_ATY
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
- select FB_BACKLIGHT if FB_ATY_BACKLIGHT
select FB_MACMODES if PPC
help
This driver supports graphics boards with the ATI Mach64 chips.
@@ -1452,6 +1444,7 @@ config FB_ATY_GX
config FB_ATY_BACKLIGHT
bool "Support for backlight control"
depends on FB_ATY
+ depends on BACKLIGHT_CLASS_DEVICE
default y
help
Say Y here if you want to control the backlight of your display.
@@ -1997,12 +1990,12 @@ config FB_SH_MOBILE_LCDC
tristate "SuperH Mobile LCDC framebuffer support"
depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
depends on FB_SH_MOBILE_MERAM || !FB_SH_MOBILE_MERAM
+ depends on BACKLIGHT_CLASS_DEVICE
select FB_SYS_FILLRECT
select FB_SYS_COPYAREA
select FB_SYS_IMAGEBLIT
select FB_SYS_FOPS
select FB_DEFERRED_IO
- select FB_BACKLIGHT
select SH_MIPI_DSI if SH_LCD_MIPI_DSI
---help---
Frame buffer driver for the on-chip SH-Mobile LCD controller.
@@ -2356,10 +2349,10 @@ config FB_MSM
config FB_MX3
tristate "MX3 Framebuffer support"
depends on FB && MX3_IPU
+ depends on BACKLIGHT_CLASS_DEVICE
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
- select BACKLIGHT_CLASS_DEVICE
default y
help
This is a framebuffer device for the i.MX31 LCD Controller. So
diff --git a/drivers/video/fbdev/core/fbsysfs.c b/drivers/video/fbdev/core/fbsysfs.c
index 53444ac19fe0..8f766f14038e 100644
--- a/drivers/video/fbdev/core/fbsysfs.c
+++ b/drivers/video/fbdev/core/fbsysfs.c
@@ -59,7 +59,7 @@ struct fb_info *framebuffer_alloc(size_t size, struct device *dev)
info->device = dev;
-#ifdef CONFIG_FB_BACKLIGHT
+#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
mutex_init(&info->bl_curve_mutex);
#endif
@@ -428,7 +428,7 @@ static ssize_t show_fbstate(struct device *device,
return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->state);
}
-#ifdef CONFIG_FB_BACKLIGHT
+#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
static ssize_t store_bl_curve(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
@@ -517,7 +517,7 @@ static struct device_attribute device_attrs[] = {
__ATTR(stride, S_IRUGO, show_stride, NULL),
__ATTR(rotate, S_IRUGO|S_IWUSR, show_rotate, store_rotate),
__ATTR(state, S_IRUGO|S_IWUSR, show_fbstate, store_fbstate),
-#ifdef CONFIG_FB_BACKLIGHT
+#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
__ATTR(bl_curve, S_IRUGO|S_IWUSR, show_bl_curve, store_bl_curve),
#endif
};
@@ -558,7 +558,7 @@ void fb_cleanup_device(struct fb_info *fb_info)
}
}
-#ifdef CONFIG_FB_BACKLIGHT
+#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
/* This function generates a linear backlight curve
*
* 0: off
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 09bb7a18d287..47e7742fdc9e 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -461,7 +461,7 @@ struct fb_info {
struct list_head modelist; /* mode list */
struct fb_videomode *mode; /* current mode */
-#ifdef CONFIG_FB_BACKLIGHT
+#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
/* assigned backlight device */
/* set before framebuffer registration,
remove after unregister */
diff --git a/include/uapi/linux/fb.h b/include/uapi/linux/fb.h
index fb795c3b3c17..a7a4be063432 100644
--- a/include/uapi/linux/fb.h
+++ b/include/uapi/linux/fb.h
@@ -392,7 +392,7 @@ struct fb_cursor {
struct fb_image image; /* Cursor image */
};
-#ifdef CONFIG_FB_BACKLIGHT
+#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
/* Settings for the generic backlight code */
#define FB_BACKLIGHT_LEVELS 128
#define FB_BACKLIGHT_MAX 0xFF
--
2.1.1
^ permalink raw reply related
* Re: [PATCH V2 1/2] mm: Update generic gup implementation to handle hugepage directory
From: Steve Capper @ 2014-10-17 14:10 UTC (permalink / raw)
To: Aneesh Kumar K.V
Cc: Andrea Arcangeli, linux-arch, linux, will.deacon, linux-kernel,
linux-mm, catalin.marinas, akpm, linuxppc-dev
In-Reply-To: <1413520687-31729-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
On Fri, Oct 17, 2014 at 10:08:06AM +0530, Aneesh Kumar K.V wrote:
> Update generic gup implementation with powerpc specific details.
> On powerpc at pmd level we can have hugepte, normal pmd pointer
> or a pointer to the hugepage directory.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> Changes from V1:
> * Folded arm/arm64 related changes into the patch
> * Dropped pgd_huge from generic header
>
> arch/arm/include/asm/pgtable.h | 2 +
> arch/arm64/include/asm/pgtable.h | 2 +
> include/linux/mm.h | 26 +++++++++
> mm/gup.c | 113 +++++++++++++++++++--------------------
> 4 files changed, 84 insertions(+), 59 deletions(-)
>
Hi Aneesh,
Thanks for coding this up. I've tested this for arm (Arndale board) and
arm64 (Juno); it builds without any issues and passes my futex on THP
tail test.
Please add my:
Tested-by: Steve Capper <steve.capper@linaro.org>
As this patch progresses through -mm, the arm maintainer:
Russell King <linux@arm.linux.org.uk>
and arm64 maintainers:
Catalin Marinas <catalin.marinas@arm.com>
Will Deacon <will.deacon@arm.com>
should also be on CC.
Cheers,
--
Steve
> diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
> index 90aa4583b308..46f81fbaa4a5 100644
> --- a/arch/arm/include/asm/pgtable.h
> +++ b/arch/arm/include/asm/pgtable.h
> @@ -181,6 +181,8 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
> /* to find an entry in a kernel page-table-directory */
> #define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
>
> +#define pgd_huge(pgd) (0)
> +
> #define pmd_none(pmd) (!pmd_val(pmd))
> #define pmd_present(pmd) (pmd_val(pmd))
>
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index cefd3e825612..ed8f42497ac4 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -464,6 +464,8 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
> extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
> extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
>
> +#define pgd_huge(pgd) (0)
> +
> /*
> * Encode and decode a swap entry:
> * bits 0-1: present (must be zero)
> diff --git a/include/linux/mm.h b/include/linux/mm.h
> index 02d11ee7f19d..f97732412cb4 100644
> --- a/include/linux/mm.h
> +++ b/include/linux/mm.h
> @@ -1219,6 +1219,32 @@ long get_user_pages(struct task_struct *tsk, struct mm_struct *mm,
> struct vm_area_struct **vmas);
> int get_user_pages_fast(unsigned long start, int nr_pages, int write,
> struct page **pages);
> +
> +#ifdef CONFIG_HAVE_GENERIC_RCU_GUP
> +#ifndef is_hugepd
> +/*
> + * Some architectures support hugepage directory format that is
> + * required to support different hugetlbfs sizes.
> + */
> +typedef struct { unsigned long pd; } hugepd_t;
> +#define is_hugepd(hugepd) (0)
> +#define __hugepd(x) ((hugepd_t) { (x) })
> +static inline int gup_hugepd(hugepd_t hugepd, unsigned long addr,
> + unsigned pdshift, unsigned long end,
> + int write, struct page **pages, int *nr)
> +{
> + return 0;
> +}
> +#else
> +extern int gup_hugepd(hugepd_t hugepd, unsigned long addr,
> + unsigned pdshift, unsigned long end,
> + int write, struct page **pages, int *nr);
> +#endif
> +extern int gup_huge_pte(pte_t orig, pte_t *ptep, unsigned long addr,
> + unsigned long sz, unsigned long end, int write,
> + struct page **pages, int *nr);
> +#endif
> +
> struct kvec;
> int get_kernel_pages(const struct kvec *iov, int nr_pages, int write,
> struct page **pages);
> diff --git a/mm/gup.c b/mm/gup.c
> index cd62c8c90d4a..13c560ef9ddf 100644
> --- a/mm/gup.c
> +++ b/mm/gup.c
> @@ -786,65 +786,31 @@ static int gup_pte_range(pmd_t pmd, unsigned long addr, unsigned long end,
> }
> #endif /* __HAVE_ARCH_PTE_SPECIAL */
>
> -static int gup_huge_pmd(pmd_t orig, pmd_t *pmdp, unsigned long addr,
> - unsigned long end, int write, struct page **pages, int *nr)
> +int gup_huge_pte(pte_t orig, pte_t *ptep, unsigned long addr,
> + unsigned long sz, unsigned long end, int write,
> + struct page **pages, int *nr)
> {
> - struct page *head, *page, *tail;
> int refs;
> + unsigned long pte_end;
> + struct page *head, *page, *tail;
>
> - if (write && !pmd_write(orig))
> - return 0;
> -
> - refs = 0;
> - head = pmd_page(orig);
> - page = head + ((addr & ~PMD_MASK) >> PAGE_SHIFT);
> - tail = page;
> - do {
> - VM_BUG_ON_PAGE(compound_head(page) != head, page);
> - pages[*nr] = page;
> - (*nr)++;
> - page++;
> - refs++;
> - } while (addr += PAGE_SIZE, addr != end);
>
> - if (!page_cache_add_speculative(head, refs)) {
> - *nr -= refs;
> + if (write && !pte_write(orig))
> return 0;
> - }
>
> - if (unlikely(pmd_val(orig) != pmd_val(*pmdp))) {
> - *nr -= refs;
> - while (refs--)
> - put_page(head);
> + if (!pte_present(orig))
> return 0;
> - }
>
> - /*
> - * Any tail pages need their mapcount reference taken before we
> - * return. (This allows the THP code to bump their ref count when
> - * they are split into base pages).
> - */
> - while (refs--) {
> - if (PageTail(tail))
> - get_huge_page_tail(tail);
> - tail++;
> - }
> -
> - return 1;
> -}
> -
> -static int gup_huge_pud(pud_t orig, pud_t *pudp, unsigned long addr,
> - unsigned long end, int write, struct page **pages, int *nr)
> -{
> - struct page *head, *page, *tail;
> - int refs;
> + pte_end = (addr + sz) & ~(sz-1);
> + if (pte_end < end)
> + end = pte_end;
>
> - if (write && !pud_write(orig))
> - return 0;
> + /* hugepages are never "special" */
> + VM_BUG_ON(!pfn_valid(pte_pfn(orig)));
>
> refs = 0;
> - head = pud_page(orig);
> - page = head + ((addr & ~PUD_MASK) >> PAGE_SHIFT);
> + head = pte_page(orig);
> + page = head + ((addr & (sz-1)) >> PAGE_SHIFT);
> tail = page;
> do {
> VM_BUG_ON_PAGE(compound_head(page) != head, page);
> @@ -859,13 +825,18 @@ static int gup_huge_pud(pud_t orig, pud_t *pudp, unsigned long addr,
> return 0;
> }
>
> - if (unlikely(pud_val(orig) != pud_val(*pudp))) {
> + if (unlikely(pte_val(orig) != pte_val(*ptep))) {
> *nr -= refs;
> while (refs--)
> put_page(head);
> return 0;
> }
>
> + /*
> + * Any tail pages need their mapcount reference taken before we
> + * return. (This allows the THP code to bump their ref count when
> + * they are split into base pages).
> + */
> while (refs--) {
> if (PageTail(tail))
> get_huge_page_tail(tail);
> @@ -898,10 +869,19 @@ static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
> if (pmd_numa(pmd))
> return 0;
>
> - if (!gup_huge_pmd(pmd, pmdp, addr, next, write,
> - pages, nr))
> + if (!gup_huge_pte(__pte(pmd_val(pmd)), (pte_t *)pmdp,
> + addr, PMD_SIZE, next,
> + write, pages, nr))
> return 0;
>
> + } else if (unlikely(is_hugepd(__hugepd(pmd_val(pmd))))) {
> + /*
> + * architecture have different format for hugetlbfs
> + * pmd format and THP pmd format
> + */
> + if (!gup_hugepd(__hugepd(pmd_val(pmd)), addr, PMD_SHIFT,
> + next, write, pages, nr))
> + return 0;
> } else if (!gup_pte_range(pmd, addr, next, write, pages, nr))
> return 0;
> } while (pmdp++, addr = next, addr != end);
> @@ -909,22 +889,27 @@ static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
> return 1;
> }
>
> -static int gup_pud_range(pgd_t *pgdp, unsigned long addr, unsigned long end,
> +static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
> int write, struct page **pages, int *nr)
> {
> unsigned long next;
> pud_t *pudp;
>
> - pudp = pud_offset(pgdp, addr);
> + pudp = pud_offset(&pgd, addr);
> do {
> pud_t pud = ACCESS_ONCE(*pudp);
>
> next = pud_addr_end(addr, end);
> if (pud_none(pud))
> return 0;
> - if (pud_huge(pud)) {
> - if (!gup_huge_pud(pud, pudp, addr, next, write,
> - pages, nr))
> + if (unlikely(pud_huge(pud))) {
> + if (!gup_huge_pte(__pte(pud_val(pud)), (pte_t *)pudp,
> + addr, PUD_SIZE, next,
> + write, pages, nr))
> + return 0;
> + } else if (unlikely(is_hugepd(__hugepd(pud_val(pud))))) {
> + if (!gup_hugepd(__hugepd(pud_val(pud)), addr, PUD_SHIFT,
> + next, write, pages, nr))
> return 0;
> } else if (!gup_pmd_range(pud, addr, next, write, pages, nr))
> return 0;
> @@ -970,10 +955,21 @@ int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
> local_irq_save(flags);
> pgdp = pgd_offset(mm, addr);
> do {
> + pgd_t pgd = ACCESS_ONCE(*pgdp);
> +
> next = pgd_addr_end(addr, end);
> - if (pgd_none(*pgdp))
> + if (pgd_none(pgd))
> break;
> - else if (!gup_pud_range(pgdp, addr, next, write, pages, &nr))
> + if (unlikely(pgd_huge(pgd))) {
> + if (!gup_huge_pte(__pte(pgd_val(pgd)), (pte_t *)pgdp,
> + addr, PGDIR_SIZE, next,
> + write, pages, &nr))
> + break;
> + } else if (unlikely(is_hugepd(__hugepd(pgd_val(pgd))))) {
> + if (!gup_hugepd(__hugepd(pgd_val(pgd)), addr, PGDIR_SHIFT,
> + next, write, pages, &nr))
> + break;
> + } else if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
> break;
> } while (pgdp++, addr = next, addr != end);
> local_irq_restore(flags);
> @@ -1028,5 +1024,4 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
>
> return ret;
> }
> -
> #endif /* CONFIG_HAVE_GENERIC_RCU_GUP */
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH] i2c-qoriq: modified compatibility for correct prescaler
From: Valentin Longchamp @ 2014-10-17 9:27 UTC (permalink / raw)
To: Linux PowerPC Kernel, Linux device trees, Linux I2C, Scott Wood
Cc: Rainer Boschung, Valentin Longchamp, Holger Brunck
With "fsl-i2c" compatibility the i2c frequency is not set
correctly, because it sets no prescaler. According to the AN2919 from
Freescale and the QorIQ (P2041) documentation, the source clock is 1/2
the platform clock. This implies that a prescaler of 2 must be used.
This changes the compatibility of the qoriq-i2c .dtsi files to pick the
mpc8543, which uses the same driver but sets the correct prescaler.
Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
---
arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi | 4 ++--
arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
index 5f9bf7d..aa6c366 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
@@ -36,7 +36,7 @@ i2c@118000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
- compatible = "fsl-i2c";
+ compatible = "fsl,mpc8543-i2c", "fsl-i2c";
reg = <0x118000 0x100>;
interrupts = <38 2 0 0>;
dfsrr;
@@ -46,7 +46,7 @@ i2c@118100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
- compatible = "fsl-i2c";
+ compatible = "fsl,mpc8543-i2c", "fsl-i2c";
reg = <0x118100 0x100>;
interrupts = <38 2 0 0>;
dfsrr;
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
index 7989bf5..b697a3b 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
@@ -36,7 +36,7 @@ i2c@119000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
- compatible = "fsl-i2c";
+ compatible = "fsl,mpc8543-i2c", "fsl-i2c";
reg = <0x119000 0x100>;
interrupts = <39 2 0 0>;
dfsrr;
@@ -46,7 +46,7 @@ i2c@119100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <3>;
- compatible = "fsl-i2c";
+ compatible = "fsl,mpc8543-i2c", "fsl-i2c";
reg = <0x119100 0x100>;
interrupts = <39 2 0 0>;
dfsrr;
--
1.8.0.1
^ permalink raw reply related
* [RESEND PATCH v4] dmaengine: Driver support for FSL RaidEngine device.
From: xuelin.shi @ 2014-10-17 7:28 UTC (permalink / raw)
To: dan.j.williams, vinod.koul
Cc: dmaengine, Harninder Rai, Xuelin Shi, linuxppc-dev, Naveen Burmi
From: Xuelin Shi <xuelin.shi@freescale.com>
The RaidEngine is a new FSL hardware used for Raid5/6 acceration.
This patch enables the RaidEngine functionality and provides
hardware offloading capability for memcpy, xor and pq computation.
It works with async_tx.
Signed-off-by: Harninder Rai <harninder.rai@freescale.com>
Signed-off-by: Naveen Burmi <naveenburmi@freescale.com>
Signed-off-by: Xuelin Shi <xuelin.shi@freescale.com>
---
changes for v4:
- use upper/lower_32_bits(...) instead of direct shift.
- change FSL_RAID dependency !ASYNC_TX_ENABLE_CHANNEL_SWITCH in Kconfig.
changes for v3:
- fix memory allocation flag GFP_xxx usage.
- add re_jr_issue_pending call in cleanup.
- remove unnecessary dma_run_dependencies(...).
- use dma_cookie_complete(...) instead of direct updating cookie.
drivers/dma/Kconfig | 11 +
drivers/dma/Makefile | 1 +
drivers/dma/fsl_raid.c | 875 +++++++++++++++++++++++++++++++++++++++++++++++++
drivers/dma/fsl_raid.h | 307 +++++++++++++++++
4 files changed, 1194 insertions(+)
create mode 100644 drivers/dma/fsl_raid.c
create mode 100644 drivers/dma/fsl_raid.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 605b016..b85880c 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -100,6 +100,17 @@ config FSL_DMA
EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
some Txxx and Bxxx parts.
+config FSL_RAID
+ tristate "Freescale RAID engine Support"
+ depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
+ select DMA_ENGINE
+ select DMA_ENGINE_RAID
+ ---help---
+ Enable support for Freescale RAID Engine. RAID Engine is
+ available on some QorIQ SoCs (like P5020). It has
+ the capability to offload memcpy, xor and pq computation
+ for raid5/6.
+
config MPC512X_DMA
tristate "Freescale MPC512x built-in DMA engine support"
depends on PPC_MPC512x || PPC_MPC831x
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index a029d0f4..60b163b 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
obj-$(CONFIG_TI_CPPI41) += cppi41.o
obj-$(CONFIG_K3_DMA) += k3dma.o
obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
+obj-$(CONFIG_FSL_RAID) += fsl_raid.o
diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c
new file mode 100644
index 0000000..1dc5981
--- /dev/null
+++ b/drivers/dma/fsl_raid.c
@@ -0,0 +1,875 @@
+/*
+ * drivers/dma/fsl_raid.c
+ *
+ * Freescale RAID Engine device driver
+ *
+ * Author:
+ * Harninder Rai <harninder.rai@freescale.com>
+ * Naveen Burmi <naveenburmi@freescale.com>
+ *
+ * Rewrite:
+ * Xuelin Shi <xuelin.shi@freescale.com>
+ *
+ * Copyright (c) 2010-2014 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Theory of operation:
+ *
+ * General capabilities:
+ * RAID Engine (RE) block is capable of offloading XOR, memcpy and P/Q
+ * calculations required in RAID5 and RAID6 operations. RE driver
+ * registers with Linux's ASYNC layer as dma driver. RE hardware
+ * maintains strict ordering of the requests through chained
+ * command queueing.
+ *
+ * Data flow:
+ * Software RAID layer of Linux (MD layer) maintains RAID partitions,
+ * strips, stripes etc. It sends requests to the underlying AYSNC layer
+ * which further passes it to RE driver. ASYNC layer decides which request
+ * goes to which job ring of RE hardware. For every request processed by
+ * RAID Engine, driver gets an interrupt unless coalescing is set. The
+ * per job ring interrupt handler checks the status register for errors,
+ * clears the interrupt and leave the post interrupt processing to the irq
+ * thread.
+ */
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/dmaengine.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+#include "dmaengine.h"
+#include "fsl_raid.h"
+
+#define MAX_XOR_SRCS 16
+#define MAX_PQ_SRCS 16
+#define MAX_INITIAL_DESCS 256
+#define MAX_DESCS_LIMIT (4 * MAX_INITIAL_DESCS)
+#define FRAME_FORMAT 0x1
+#define MAX_DATA_LENGTH (1024*1024)
+
+#define to_fsl_re_dma_desc(tx) container_of(tx, \
+ struct fsl_re_dma_async_tx_desc, async_tx)
+
+/* Add descriptors into per jr software queue - submit_q */
+static dma_cookie_t re_jr_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+ struct fsl_re_dma_async_tx_desc *desc;
+ struct re_jr *jr;
+ dma_cookie_t cookie;
+ unsigned long flags;
+
+ desc = to_fsl_re_dma_desc(tx);
+ jr = container_of(tx->chan, struct re_jr, chan);
+
+ spin_lock_irqsave(&jr->desc_lock, flags);
+ cookie = dma_cookie_assign(tx);
+ list_add_tail(&desc->node, &jr->submit_q);
+ spin_unlock_irqrestore(&jr->desc_lock, flags);
+
+ return cookie;
+}
+
+/* Copy descriptor from per jr software queue into hardware job ring */
+static void re_jr_issue_pending(struct dma_chan *chan)
+{
+ struct re_jr *jr;
+ int avail;
+ struct fsl_re_dma_async_tx_desc *desc, *_desc;
+ unsigned long flags;
+
+ jr = container_of(chan, struct re_jr, chan);
+
+ avail = RE_JR_INB_SLOT_AVAIL(in_be32(&jr->jrregs->inbring_slot_avail));
+ if (!avail)
+ return;
+
+ spin_lock_irqsave(&jr->desc_lock, flags);
+ list_for_each_entry_safe(desc, _desc, &jr->submit_q, node) {
+ if (!avail)
+ break;
+
+ list_move_tail(&desc->node, &jr->active_q);
+
+ memcpy(&jr->inb_ring_virt_addr[jr->inb_count], &desc->hwdesc,
+ sizeof(struct jr_hw_desc));
+
+ jr->inb_count = (jr->inb_count + 1) & RING_SIZE_MASK;
+
+ /* add one job into job ring */
+ out_be32(&jr->jrregs->inbring_add_job, RE_JR_INB_JOB_ADD(1));
+ avail--;
+ }
+ spin_unlock_irqrestore(&jr->desc_lock, flags);
+}
+
+static void re_jr_desc_done(struct fsl_re_dma_async_tx_desc *desc)
+{
+ dma_async_tx_callback callback;
+ void *callback_param;
+
+ dma_cookie_complete(&desc->async_tx);
+
+ callback = desc->async_tx.callback;
+ callback_param = desc->async_tx.callback_param;
+ if (callback)
+ callback(callback_param);
+
+ dma_descriptor_unmap(&desc->async_tx);
+}
+
+static void re_jr_dequeue(struct re_jr *jr)
+{
+ struct fsl_re_dma_async_tx_desc *desc, *_desc;
+ struct jr_hw_desc *hwdesc;
+ unsigned int count;
+ int found;
+
+ count = RE_JR_OUB_SLOT_FULL(in_be32(&jr->jrregs->oubring_slot_full));
+ while (count--) {
+ found = 0;
+ hwdesc = &jr->oub_ring_virt_addr[jr->oub_count];
+ list_for_each_entry_safe(desc, _desc, &jr->active_q, node) {
+ /* compare the hw dma addr to find the completed */
+ if (desc->hwdesc.lbea32 == hwdesc->lbea32 &&
+ desc->hwdesc.addr_low == hwdesc->addr_low) {
+ found = 1;
+ break;
+ }
+ }
+
+ BUG_ON(!found);
+ re_jr_desc_done(desc);
+ list_move_tail(&desc->node, &jr->ack_q);
+
+ jr->oub_count = (jr->oub_count + 1) & RING_SIZE_MASK;
+ out_be32(&jr->jrregs->oubring_job_rmvd, RE_JR_OUB_JOB_RMVD(1));
+ }
+}
+
+static void re_jr_cleanup_descs(struct re_jr *jr)
+{
+ struct fsl_re_dma_async_tx_desc *desc, *_desc;
+ unsigned long flags;
+
+ spin_lock_irqsave(&jr->desc_lock, flags);
+ re_jr_dequeue(jr);
+ list_for_each_entry_safe(desc, _desc, &jr->ack_q, node) {
+ if (async_tx_test_ack(&desc->async_tx))
+ list_move_tail(&desc->node, &jr->free_q);
+ }
+ spin_unlock_irqrestore(&jr->desc_lock, flags);
+
+ re_jr_issue_pending(&jr->chan);
+}
+
+static irqreturn_t re_jr_isr_thread(int irq, void *data)
+{
+ struct re_jr *jr = (struct re_jr *)data;
+
+ re_jr_cleanup_descs(jr);
+
+ return IRQ_HANDLED;
+}
+
+/* Per Job Ring interrupt handler */
+static irqreturn_t re_jr_isr(int irq, void *data)
+{
+ struct re_jr *jr = (struct re_jr *)data;
+
+ u32 irqstate, status;
+ irqstate = in_be32(&jr->jrregs->jr_interrupt_status);
+ if (!irqstate)
+ return IRQ_NONE;
+
+ /*
+ * There's no way in upper layer (read MD layer) to recover from
+ * error conditions except restart everything. In long term we
+ * need to do something more than just crashing
+ */
+ if (irqstate & RE_JR_ERROR) {
+ status = in_be32(&jr->jrregs->jr_status);
+ dev_err(jr->dev, "jr error irqstate: %x, status: %x\n",
+ irqstate, status);
+ }
+
+ /* Clear interrupt */
+ out_be32(&jr->jrregs->jr_interrupt_status, RE_JR_CLEAR_INT);
+ return IRQ_WAKE_THREAD;
+}
+
+static enum dma_status re_jr_tx_status(struct dma_chan *chan,
+ dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
+ enum dma_status ret;
+ struct re_jr *jr = container_of(chan, struct re_jr, chan);
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+
+ if (ret != DMA_COMPLETE) {
+ re_jr_cleanup_descs(jr);
+ ret = dma_cookie_status(chan, cookie, txstate);
+ }
+
+ return ret;
+}
+
+void fill_cfd_frame(struct cmpnd_frame *cf, u8 index,
+ size_t length, dma_addr_t addr, bool final)
+{
+ u32 efrl = length & CF_LENGTH_MASK;
+ efrl |= final << CF_FINAL_SHIFT;
+ cf[index].efrl32 = efrl;
+ cf[index].addr_high = upper_32_bits(addr);
+ cf[index].addr_low = lower_32_bits(addr);
+}
+
+static struct fsl_re_dma_async_tx_desc *re_jr_init_desc(struct re_jr *jr,
+ struct fsl_re_dma_async_tx_desc *desc, void *cf, dma_addr_t paddr)
+{
+ desc->jr = jr;
+ desc->async_tx.tx_submit = re_jr_tx_submit;
+ dma_async_tx_descriptor_init(&desc->async_tx, &jr->chan);
+ INIT_LIST_HEAD(&desc->node);
+
+ desc->hwdesc.fmt32 = FRAME_FORMAT << HWDESC_FMT_SHIFT;
+ desc->hwdesc.lbea32 = upper_32_bits(paddr);
+ desc->hwdesc.addr_low = lower_32_bits(paddr);
+ desc->cf_addr = cf;
+ desc->cf_paddr = paddr;
+
+ desc->cdb_addr = (void *)(cf + RE_CF_DESC_SIZE);
+ desc->cdb_paddr = paddr + RE_CF_DESC_SIZE;
+
+ return desc;
+}
+
+static struct fsl_re_dma_async_tx_desc *re_jr_alloc_desc(struct re_jr *jr,
+ unsigned long flags)
+{
+ struct fsl_re_dma_async_tx_desc *desc = NULL;
+ void *cf;
+ dma_addr_t paddr;
+ unsigned long lock_flag;
+
+ re_jr_cleanup_descs(jr);
+
+ spin_lock_irqsave(&jr->desc_lock, lock_flag);
+ if (!list_empty(&jr->free_q)) {
+ /* take one desc from free_q */
+ desc = list_first_entry(&jr->free_q,
+ struct fsl_re_dma_async_tx_desc, node);
+ list_del(&desc->node);
+
+ desc->async_tx.flags = flags;
+ }
+ spin_unlock_irqrestore(&jr->desc_lock, lock_flag);
+
+ if (!desc) {
+ desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
+ cf = dma_pool_alloc(jr->re_dev->cf_desc_pool, GFP_NOWAIT,
+ &paddr);
+ if (!desc || !cf) {
+ kfree(desc);
+ return NULL;
+ }
+
+ desc = re_jr_init_desc(jr, desc, cf, paddr);
+ desc->async_tx.flags = flags;
+
+ spin_lock_irqsave(&jr->desc_lock, lock_flag);
+ jr->alloc_count++;
+ spin_unlock_irqrestore(&jr->desc_lock, lock_flag);
+ }
+
+ return desc;
+}
+
+static struct dma_async_tx_descriptor *re_jr_prep_genq(
+ struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
+ unsigned int src_cnt, const unsigned char *scf, size_t len,
+ unsigned long flags)
+{
+ struct re_jr *jr;
+ struct fsl_re_dma_async_tx_desc *desc;
+ struct xor_cdb *xor;
+ struct cmpnd_frame *cf;
+ u32 cdb;
+ unsigned int i, j;
+
+ if (len > MAX_DATA_LENGTH) {
+ pr_err("Length greater than %d not supported\n",
+ MAX_DATA_LENGTH);
+ return NULL;
+ }
+
+ jr = container_of(chan, struct re_jr, chan);
+ desc = re_jr_alloc_desc(jr, flags);
+ if (desc <= 0)
+ return NULL;
+
+ /* Filling xor CDB */
+ cdb = RE_XOR_OPCODE << RE_CDB_OPCODE_SHIFT;
+ cdb |= (src_cnt - 1) << RE_CDB_NRCS_SHIFT;
+ cdb |= RE_BLOCK_SIZE << RE_CDB_BLKSIZE_SHIFT;
+ cdb |= INTERRUPT_ON_ERROR << RE_CDB_ERROR_SHIFT;
+ cdb |= DATA_DEPENDENCY << RE_CDB_DEPEND_SHIFT;
+ xor = desc->cdb_addr;
+ xor->cdb32 = cdb;
+
+ if (scf != NULL) {
+ /* compute q = src0*coef0^src1*coef1^..., * is GF(8) mult */
+ for (i = 0; i < src_cnt; i++)
+ xor->gfm[i] = scf[i];
+ } else {
+ /* compute P, that is XOR all srcs */
+ for (i = 0; i < src_cnt; i++)
+ xor->gfm[i] = 1;
+ }
+
+ /* Filling frame 0 of compound frame descriptor with CDB */
+ cf = desc->cf_addr;
+ fill_cfd_frame(cf, 0, sizeof(struct xor_cdb), desc->cdb_paddr, 0);
+
+ /* Fill CFD's 1st frame with dest buffer */
+ fill_cfd_frame(cf, 1, len, dest, 0);
+
+ /* Fill CFD's rest of the frames with source buffers */
+ for (i = 2, j = 0; j < src_cnt; i++, j++)
+ fill_cfd_frame(cf, i, len, src[j], 0);
+
+ /* Setting the final bit in the last source buffer frame in CFD */
+ cf[i - 1].efrl32 |= 1 << CF_FINAL_SHIFT;
+
+ return &desc->async_tx;
+}
+
+/*
+ * Prep function for P parity calculation.In RAID Engine terminology,
+ * XOR calculation is called GenQ calculation done through GenQ command
+ */
+static struct dma_async_tx_descriptor *re_jr_prep_dma_xor(
+ struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
+ unsigned int src_cnt, size_t len, unsigned long flags)
+{
+ /* NULL let genq take all coef as 1 */
+ return re_jr_prep_genq(chan, dest, src, src_cnt, NULL, len, flags);
+}
+
+/*
+ * Prep function for P/Q parity calculation.In RAID Engine terminology,
+ * P/Q calculation is called GenQQ done through GenQQ command
+ */
+static struct dma_async_tx_descriptor *re_jr_prep_pq(
+ struct dma_chan *chan, dma_addr_t *dest, dma_addr_t *src,
+ unsigned int src_cnt, const unsigned char *scf, size_t len,
+ unsigned long flags)
+{
+ struct re_jr *jr;
+ struct fsl_re_dma_async_tx_desc *desc;
+ struct pq_cdb *pq;
+ struct cmpnd_frame *cf;
+ u32 cdb;
+ u8 *p;
+ int gfmq_len, i, j;
+
+ if (len > MAX_DATA_LENGTH) {
+ pr_err("Length greater than %d not supported\n",
+ MAX_DATA_LENGTH);
+ return NULL;
+ }
+
+ /*
+ * RE requires at least 2 sources, if given only one source, we pass the
+ * second source same as the first one.
+ * With only one source, generating P is meaningless, only generate Q.
+ */
+ if (src_cnt == 1) {
+ struct dma_async_tx_descriptor *tx;
+ dma_addr_t dma_src[2];
+ unsigned char coef[2];
+
+ dma_src[0] = *src;
+ coef[0] = *scf;
+ dma_src[1] = *src;
+ coef[1] = 0;
+ tx = re_jr_prep_genq(chan, dest[1], dma_src, 2, coef, len,
+ flags);
+ if (tx)
+ desc = to_fsl_re_dma_desc(tx);
+
+ return tx;
+ }
+
+ /*
+ * During RAID6 array creation, Linux's MD layer gets P and Q
+ * calculated separately in two steps. But our RAID Engine has
+ * the capability to calculate both P and Q with a single command
+ * Hence to merge well with MD layer, we need to provide a hook
+ * here and call re_jq_prep_genq() function
+ */
+
+ if (flags & DMA_PREP_PQ_DISABLE_P)
+ return re_jr_prep_genq(chan, dest[1], src, src_cnt,
+ scf, len, flags);
+
+ jr = container_of(chan, struct re_jr, chan);
+ desc = re_jr_alloc_desc(jr, flags);
+ if (desc <= 0)
+ return NULL;
+
+ /* Filling GenQQ CDB */
+ cdb = RE_PQ_OPCODE << RE_CDB_OPCODE_SHIFT;
+ cdb |= (src_cnt - 1) << RE_CDB_NRCS_SHIFT;
+ cdb |= RE_BLOCK_SIZE << RE_CDB_BLKSIZE_SHIFT;
+ cdb |= BUFFERABLE_OUTPUT << RE_CDB_BUFFER_SHIFT;
+ cdb |= DATA_DEPENDENCY << RE_CDB_DEPEND_SHIFT;
+
+ pq = desc->cdb_addr;
+ pq->cdb32 = cdb;
+
+ p = pq->gfm_q1;
+ /* Init gfm_q1[] */
+ for (i = 0; i < src_cnt; i++)
+ p[i] = 1;
+
+ /* Align gfm[] to 32bit */
+ gfmq_len = ALIGN(src_cnt, 4);
+
+ /* Init gfm_q2[] */
+ p += gfmq_len;
+ for (i = 0; i < src_cnt; i++)
+ p[i] = scf[i];
+
+ /* Filling frame 0 of compound frame descriptor with CDB */
+ cf = desc->cf_addr;
+ fill_cfd_frame(cf, 0, sizeof(struct pq_cdb), desc->cdb_paddr, 0);
+
+ /* Fill CFD's 1st & 2nd frame with dest buffers */
+ for (i = 1, j = 0; i < 3; i++, j++)
+ fill_cfd_frame(cf, i, len, dest[j], 0);
+
+ /* Fill CFD's rest of the frames with source buffers */
+ for (i = 3, j = 0; j < src_cnt; i++, j++)
+ fill_cfd_frame(cf, i, len, src[j], 0);
+
+ /* Setting the final bit in the last source buffer frame in CFD */
+ cf[i - 1].efrl32 |= 1 << CF_FINAL_SHIFT;
+
+ return &desc->async_tx;
+}
+
+/*
+ * Prep function for memcpy. In RAID Engine, memcpy is done through MOVE
+ * command. Logic of this function will need to be modified once multipage
+ * support is added in Linux's MD/ASYNC Layer
+ */
+static struct dma_async_tx_descriptor *re_jr_prep_memcpy(
+ struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+ size_t len, unsigned long flags)
+{
+ struct re_jr *jr;
+ struct fsl_re_dma_async_tx_desc *desc;
+ size_t length;
+ struct cmpnd_frame *cf;
+ struct move_cdb *move;
+ u32 cdb;
+
+ jr = container_of(chan, struct re_jr, chan);
+
+ if (len > MAX_DATA_LENGTH) {
+ pr_err("Length greater than %d not supported\n",
+ MAX_DATA_LENGTH);
+ return NULL;
+ }
+
+ desc = re_jr_alloc_desc(jr, flags);
+ if (desc <= 0)
+ return NULL;
+
+ /* Filling move CDB */
+ cdb = RE_MOVE_OPCODE << RE_CDB_OPCODE_SHIFT;
+ cdb |= RE_BLOCK_SIZE << RE_CDB_BLKSIZE_SHIFT;
+ cdb |= INTERRUPT_ON_ERROR << RE_CDB_ERROR_SHIFT;
+ cdb |= DATA_DEPENDENCY << RE_CDB_DEPEND_SHIFT;
+
+ move = desc->cdb_addr;
+ move->cdb32 = cdb;
+
+ /* Filling frame 0 of CFD with move CDB */
+ cf = desc->cf_addr;
+ fill_cfd_frame(cf, 0, sizeof(struct move_cdb), desc->cdb_paddr, 0);
+
+ length = min_t(size_t, len, MAX_DATA_LENGTH);
+
+ /* Fill CFD's 1st frame with dest buffer */
+ fill_cfd_frame(cf, 1, length, dest, 0);
+
+ /* Fill CFD's 2nd frame with src buffer */
+ fill_cfd_frame(cf, 2, length, src, 1);
+
+ return &desc->async_tx;
+}
+
+static int re_jr_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct re_jr *jr = container_of(chan, struct re_jr, chan);
+ struct fsl_re_dma_async_tx_desc *desc;
+ void *cf;
+ dma_addr_t paddr;
+
+ int i;
+
+ for (i = 0; i < MAX_DESCS_LIMIT; i++) {
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ cf = dma_pool_alloc(jr->re_dev->cf_desc_pool, GFP_KERNEL,
+ &paddr);
+ if (!desc || !cf) {
+ kfree(desc);
+ break;
+ }
+
+ INIT_LIST_HEAD(&desc->node);
+ re_jr_init_desc(jr, desc, cf, paddr);
+
+ list_add_tail(&desc->node, &jr->free_q);
+ jr->alloc_count++;
+ }
+ return jr->alloc_count;
+}
+
+static void re_jr_free_chan_resources(struct dma_chan *chan)
+{
+ struct re_jr *jr = container_of(chan, struct re_jr, chan);
+ struct fsl_re_dma_async_tx_desc *desc;
+
+ while (jr->alloc_count--) {
+ desc = list_first_entry(&jr->free_q,
+ struct fsl_re_dma_async_tx_desc,
+ node);
+
+ list_del(&desc->node);
+ dma_pool_free(jr->re_dev->cf_desc_pool, desc->cf_addr,
+ desc->cf_paddr);
+ kfree(desc);
+ }
+
+ BUG_ON(!list_empty(&jr->free_q));
+}
+
+int re_jr_probe(struct platform_device *ofdev,
+ struct device_node *np, u8 q, u32 off)
+{
+ struct device *dev;
+ struct re_drv_private *repriv;
+ struct re_jr *jr;
+ struct dma_device *dma_dev;
+ u32 ptr;
+ u32 status;
+ int ret = 0, rc;
+ struct platform_device *jr_ofdev;
+
+ dev = &ofdev->dev;
+ repriv = dev_get_drvdata(dev);
+ dma_dev = &repriv->dma_dev;
+
+ jr = devm_kzalloc(dev, sizeof(*jr), GFP_KERNEL);
+ if (!jr) {
+ dev_err(dev, "No free memory for allocating JR struct\n");
+ return -ENOMEM;
+ }
+
+ /* create platform device for jr node */
+ jr_ofdev = of_platform_device_create(np, NULL, dev);
+ if (jr_ofdev == NULL) {
+ dev_err(dev, "Not able to create ofdev for jr %d\n", q);
+ ret = -EINVAL;
+ goto err_free;
+ }
+ dev_set_drvdata(&jr_ofdev->dev, jr);
+
+ /* read reg property from dts */
+ rc = of_property_read_u32(np, "reg", &ptr);
+ if (rc) {
+ dev_err(dev, "Reg property not found in JR number %d\n", q);
+ ret = -ENODEV;
+ goto err_free;
+ }
+
+ jr->jrregs = (struct jr_config_regs *)((u8 *)repriv->re_regs +
+ off + ptr);
+
+ /* read irq property from dts */
+ jr->irq = irq_of_parse_and_map(np, 0);
+ if (jr->irq == NO_IRQ) {
+ dev_err(dev, "No IRQ defined for JR %d\n", q);
+ ret = -ENODEV;
+ goto err_free;
+ }
+
+ ret = devm_request_threaded_irq(&jr_ofdev->dev, jr->irq, re_jr_isr,
+ re_jr_isr_thread, 0, jr->name, jr);
+
+ if (ret) {
+ dev_err(dev, "Unable to register JR interrupt for JR %d\n", q);
+ ret = -EINVAL;
+ goto err_free;
+ }
+
+ snprintf(jr->name, sizeof(jr->name), "re_jr%02d", q);
+
+ repriv->re_jrs[q] = jr;
+ jr->chan.device = dma_dev;
+ jr->chan.private = jr;
+ jr->dev = &jr_ofdev->dev;
+ jr->re_dev = repriv;
+
+ spin_lock_init(&jr->desc_lock);
+ INIT_LIST_HEAD(&jr->ack_q);
+ INIT_LIST_HEAD(&jr->active_q);
+ INIT_LIST_HEAD(&jr->submit_q);
+ INIT_LIST_HEAD(&jr->free_q);
+
+ list_add_tail(&jr->chan.device_node, &dma_dev->channels);
+ dma_dev->chancnt++;
+
+ jr->inb_ring_virt_addr = dma_pool_alloc(jr->re_dev->hw_desc_pool,
+ GFP_KERNEL, &jr->inb_phys_addr);
+
+ if (!jr->inb_ring_virt_addr) {
+ dev_err(dev, "No dma memory for inb_ring_virt_addr\n");
+ ret = -ENOMEM;
+ goto err_free;
+ }
+
+ jr->oub_ring_virt_addr = dma_pool_alloc(jr->re_dev->hw_desc_pool,
+ GFP_KERNEL, &jr->oub_phys_addr);
+
+ if (!jr->oub_ring_virt_addr) {
+ dev_err(dev, "No dma memory for oub_ring_virt_addr\n");
+ ret = -ENOMEM;
+ goto err_free_1;
+ }
+
+ jr->inb_count = 0;
+ jr->oub_count = 0;
+ jr->alloc_count = 0;
+
+ /* Program the Inbound/Outbound ring base addresses and size */
+ out_be32(&jr->jrregs->inbring_base_h,
+ jr->inb_phys_addr & RE_JR_ADDRESS_BIT_MASK);
+ out_be32(&jr->jrregs->oubring_base_h,
+ jr->oub_phys_addr & RE_JR_ADDRESS_BIT_MASK);
+ out_be32(&jr->jrregs->inbring_base_l,
+ jr->inb_phys_addr >> RE_JR_ADDRESS_BIT_SHIFT);
+ out_be32(&jr->jrregs->oubring_base_l,
+ jr->oub_phys_addr >> RE_JR_ADDRESS_BIT_SHIFT);
+ out_be32(&jr->jrregs->inbring_size, RING_SIZE << RING_SIZE_SHIFT);
+ out_be32(&jr->jrregs->oubring_size, RING_SIZE << RING_SIZE_SHIFT);
+
+ /* Read LIODN value from u-boot */
+ status = in_be32(&jr->jrregs->jr_config_1) & RE_JR_REG_LIODN_MASK;
+
+ /* Program the CFG reg */
+ out_be32(&jr->jrregs->jr_config_1,
+ RE_JR_CFG1_CBSI | RE_JR_CFG1_CBS0 | status);
+
+ /* Enable RE/JR */
+ out_be32(&jr->jrregs->jr_command, RE_JR_ENABLE);
+
+ return 0;
+
+err_free_1:
+ dma_pool_free(jr->re_dev->hw_desc_pool, jr->inb_ring_virt_addr,
+ jr->inb_phys_addr);
+err_free:
+ return ret;
+}
+
+/* Probe function for RAID Engine */
+static int raide_probe(struct platform_device *ofdev)
+{
+ struct re_drv_private *repriv;
+ struct device_node *np;
+ struct device_node *child;
+ u32 off;
+ u8 ridx = 0;
+ struct dma_device *dma_dev;
+ struct resource *res;
+ int rc;
+ struct device *dev = &ofdev->dev;
+
+ dev_info(dev, "Freescale RAID Engine driver\n");
+
+ repriv = devm_kzalloc(dev, sizeof(*repriv), GFP_KERNEL);
+ if (!repriv)
+ return -ENOMEM;
+
+ res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ /* IOMAP the entire RAID Engine region */
+ repriv->re_regs = devm_ioremap(dev, res->start, resource_size(res));
+ if (!repriv->re_regs)
+ return -EBUSY;
+
+ dev_set_drvdata(dev, repriv);
+
+ /* Print the RE version */
+ dev_info(dev, "Ver = %x\n", in_be32(&repriv->re_regs->re_version_id));
+
+ /* Program the RE mode */
+ out_be32(&repriv->re_regs->global_config, RE_NON_DPAA_MODE);
+ dev_info(dev, "RE mode is %x\n",
+ in_be32(&repriv->re_regs->global_config));
+
+ /* Program Galois Field polynomial */
+ out_be32(&repriv->re_regs->galois_field_config, RE_GFM_POLY);
+ dev_info(dev, "Galois Field Polynomial is %x\n",
+ in_be32(&repriv->re_regs->galois_field_config));
+
+ dma_dev = &repriv->dma_dev;
+ dma_dev->dev = dev;
+ INIT_LIST_HEAD(&dma_dev->channels);
+ dma_set_mask(dev, DMA_BIT_MASK(40));
+
+ dma_dev->device_alloc_chan_resources = re_jr_alloc_chan_resources;
+ dma_dev->device_tx_status = re_jr_tx_status;
+ dma_dev->device_issue_pending = re_jr_issue_pending;
+
+ dma_dev->max_xor = MAX_XOR_SRCS;
+ dma_dev->device_prep_dma_xor = re_jr_prep_dma_xor;
+ dma_cap_set(DMA_XOR, dma_dev->cap_mask);
+
+ dma_dev->max_pq = MAX_PQ_SRCS;
+ dma_dev->device_prep_dma_pq = re_jr_prep_pq;
+ dma_cap_set(DMA_PQ, dma_dev->cap_mask);
+
+ dma_dev->device_prep_dma_memcpy = re_jr_prep_memcpy;
+ dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
+
+ dma_dev->device_free_chan_resources = re_jr_free_chan_resources;
+
+ repriv->total_jrs = 0;
+
+ repriv->cf_desc_pool = dmam_pool_create("re_cf_desc_pool", dev,
+ RE_CF_CDB_SIZE,
+ RE_CF_CDB_ALIGN, 0);
+
+ if (!repriv->cf_desc_pool) {
+ pr_err("No memory for dma desc pool\n");
+ return -ENOMEM;
+ }
+
+ repriv->hw_desc_pool = dmam_pool_create("re_hw_desc_pool", dev,
+ sizeof(struct jr_hw_desc) * RING_SIZE,
+ FRAME_DESC_ALIGNMENT, 0);
+ if (!repriv->hw_desc_pool) {
+ pr_err("No memory for hw desc pool\n");
+ return -ENOMEM;
+ }
+
+ /* Parse Device tree to find out the total number of JQs present */
+ for_each_compatible_node(np, NULL, "fsl,raideng-v1.0-job-queue") {
+ rc = of_property_read_u32(np, "reg", &off);
+ if (rc) {
+ dev_err(dev, "Reg property not found in JQ node\n");
+ return -ENODEV;
+ }
+ /* Find out the Job Rings present under each JQ */
+ for_each_child_of_node(np, child) {
+ rc = of_device_is_compatible(child,
+ "fsl,raideng-v1.0-job-ring");
+ if (rc) {
+ re_jr_probe(ofdev, child, ridx++, off);
+ repriv->total_jrs++;
+ }
+ }
+ }
+
+ dma_async_device_register(dma_dev);
+
+ return 0;
+}
+
+static void release_jr(struct re_jr *jr)
+{
+ dma_pool_free(jr->re_dev->hw_desc_pool, jr->inb_ring_virt_addr,
+ jr->inb_phys_addr);
+
+ dma_pool_free(jr->re_dev->hw_desc_pool, jr->oub_ring_virt_addr,
+ jr->oub_phys_addr);
+}
+
+static int raide_remove(struct platform_device *ofdev)
+{
+ struct re_drv_private *repriv;
+ struct device *dev;
+ int i;
+
+ dev = &ofdev->dev;
+ repriv = dev_get_drvdata(dev);
+
+ /* Cleanup JR related memory areas */
+ for (i = 0; i < repriv->total_jrs; i++)
+ release_jr(repriv->re_jrs[i]);
+
+ /* Unregister the driver */
+ dma_async_device_unregister(&repriv->dma_dev);
+
+ return 0;
+}
+
+static struct of_device_id raide_ids[] = {
+ { .compatible = "fsl,raideng-v1.0", },
+ {}
+};
+
+static struct platform_driver raide_driver = {
+ .driver = {
+ .name = "fsl-raideng",
+ .owner = THIS_MODULE,
+ .of_match_table = raide_ids,
+ },
+ .probe = raide_probe,
+ .remove = raide_remove,
+};
+
+module_platform_driver(raide_driver);
+
+MODULE_AUTHOR("Harninder Rai <harninder.rai@freescale.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Freescale RAID Engine Device Driver");
diff --git a/drivers/dma/fsl_raid.h b/drivers/dma/fsl_raid.h
new file mode 100644
index 0000000..225dbf2
--- /dev/null
+++ b/drivers/dma/fsl_raid.h
@@ -0,0 +1,307 @@
+/*
+ * drivers/dma/fsl_raid.h
+ *
+ * Freescale RAID Engine device driver
+ *
+ * Author:
+ * Harninder Rai <harninder.rai@freescale.com>
+ * Naveen Burmi <naveenburmi@freescale.com>
+ *
+ * Rewrite:
+ * Xuelin Shi <xuelin.shi@freescale.com>
+
+ * Copyright (c) 2010-2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define MAX_RE_JRS 4
+
+#define RE_DPAA_MODE (1 << 30)
+#define RE_NON_DPAA_MODE (1 << 31)
+#define RE_GFM_POLY 0x1d000000
+#define RE_JR_INB_JOB_ADD(x) ((x) << 16)
+#define RE_JR_OUB_JOB_RMVD(x) ((x) << 16)
+#define RE_JR_CFG1_CBSI 0x08000000
+#define RE_JR_CFG1_CBS0 0x00080000
+#define RE_JR_OUB_SLOT_FULL_SHIFT 8
+#define RE_JR_OUB_SLOT_FULL(x) ((x) >> RE_JR_OUB_SLOT_FULL_SHIFT)
+#define RE_JR_INB_SLOT_AVAIL_SHIFT 8
+#define RE_JR_INB_SLOT_AVAIL(x) ((x) >> RE_JR_INB_SLOT_AVAIL_SHIFT)
+#define RE_PQ_OPCODE 0x1B
+#define RE_XOR_OPCODE 0x1A
+#define RE_MOVE_OPCODE 0x8
+#define FRAME_DESC_ALIGNMENT 16
+#define RE_BLOCK_SIZE 0x3 /* 4096 bytes */
+#define CACHEABLE_INPUT_OUTPUT 0x0
+#define BUFFERABLE_OUTPUT 0x0
+#define INTERRUPT_ON_ERROR 0x1
+#define DATA_DEPENDENCY 0x1
+#define ENABLE_DPI 0x0
+#define RING_SIZE 0x400
+#define RING_SIZE_MASK (RING_SIZE - 1)
+#define RING_SIZE_SHIFT 8
+#define RE_JR_ADDRESS_BIT_SHIFT 4
+#define RE_JR_ADDRESS_BIT_MASK ((1 << RE_JR_ADDRESS_BIT_SHIFT) - 1)
+#define RE_JR_ERROR 0x40000000
+#define RE_JR_INTERRUPT 0x80000000
+#define RE_JR_CLEAR_INT 0x80000000
+#define RE_JR_PAUSE 0x80000000
+#define RE_JR_ENABLE 0x80000000
+
+#define RE_JR_REG_LIODN_MASK 0x00000FFF
+#define RE_CF_CDB_ALIGN 64
+
+#define RE_CDB_OPCODE_MASK 0xF8000000
+#define RE_CDB_OPCODE_SHIFT 27
+#define RE_CDB_EXCLEN_MASK 0x03000000
+#define RE_CDB_EXCLEN_SHIFT 24
+#define RE_CDB_EXCLQ1_MASK 0x00F00000
+#define RE_CDB_EXCLQ1_SHIFT 20
+#define RE_CDB_EXCLQ2_MASK 0x000F0000
+#define RE_CDB_EXCLQ2_SHIFT 16
+#define RE_CDB_BLKSIZE_MASK 0x0000C000
+#define RE_CDB_BLKSIZE_SHIFT 14
+#define RE_CDB_CACHE_MASK 0x00003000
+#define RE_CDB_CACHE_SHIFT 12
+#define RE_CDB_BUFFER_MASK 0x00000800
+#define RE_CDB_BUFFER_SHIFT 11
+#define RE_CDB_ERROR_MASK 0x00000400
+#define RE_CDB_ERROR_SHIFT 10
+#define RE_CDB_NRCS_MASK 0x0000003C
+#define RE_CDB_NRCS_SHIFT 6
+#define RE_CDB_DEPEND_MASK 0x00000008
+#define RE_CDB_DEPEND_SHIFT 3
+#define RE_CDB_DPI_MASK 0x00000004
+#define RE_CDB_DPI_SHIFT 2
+
+/*
+ * the largest cf block is 19*sizeof(struct cmpnd_frame), which is 304 bytes.
+ * here 19 = 1(cdb)+2(dest)+16(src), align to 64bytes, that is 320 bytes.
+ * the largest cdb block: struct pq_cdb which is 180 bytes, adding to cf block
+ * 320+180=500, align to 64bytes, that is 512 bytes.
+ */
+#define RE_CF_DESC_SIZE 320
+#define RE_CF_CDB_SIZE 512
+
+struct re_ctrl {
+ /* General Configuration Registers */
+ __be32 global_config; /* Global Configuration Register */
+ u8 rsvd1[4];
+ __be32 galois_field_config; /* Galois Field Configuration Register */
+ u8 rsvd2[4];
+ __be32 jq_wrr_config; /* WRR Configuration register */
+ u8 rsvd3[4];
+ __be32 crc_config; /* CRC Configuration register */
+ u8 rsvd4[228];
+ __be32 system_reset; /* System Reset Register */
+ u8 rsvd5[252];
+ __be32 global_status; /* Global Status Register */
+ u8 rsvd6[832];
+ __be32 re_liodn_base; /* LIODN Base Register */
+ u8 rsvd7[1712];
+ __be32 re_version_id; /* Version ID register of RE */
+ __be32 re_version_id_2; /* Version ID 2 register of RE */
+ u8 rsvd8[512];
+ __be32 host_config; /* Host I/F Configuration Register */
+};
+
+struct jr_config_regs {
+ /* Registers for JR interface */
+ __be32 jr_config_0; /* Job Queue Configuration 0 Register */
+ __be32 jr_config_1; /* Job Queue Configuration 1 Register */
+ __be32 jr_interrupt_status; /* Job Queue Interrupt Status Register */
+ u8 rsvd1[4];
+ __be32 jr_command; /* Job Queue Command Register */
+ u8 rsvd2[4];
+ __be32 jr_status; /* Job Queue Status Register */
+ u8 rsvd3[228];
+
+ /* Input Ring */
+ __be32 inbring_base_h; /* Inbound Ring Base Address Register - High */
+ __be32 inbring_base_l; /* Inbound Ring Base Address Register - Low */
+ __be32 inbring_size; /* Inbound Ring Size Register */
+ u8 rsvd4[4];
+ __be32 inbring_slot_avail; /* Inbound Ring Slot Available Register */
+ u8 rsvd5[4];
+ __be32 inbring_add_job; /* Inbound Ring Add Job Register */
+ u8 rsvd6[4];
+ __be32 inbring_cnsmr_indx; /* Inbound Ring Consumer Index Register */
+ u8 rsvd7[220];
+
+ /* Output Ring */
+ __be32 oubring_base_h; /* Outbound Ring Base Address Register - High */
+ __be32 oubring_base_l; /* Outbound Ring Base Address Register - Low */
+ __be32 oubring_size; /* Outbound Ring Size Register */
+ u8 rsvd8[4];
+ __be32 oubring_job_rmvd; /* Outbound Ring Job Removed Register */
+ u8 rsvd9[4];
+ __be32 oubring_slot_full; /* Outbound Ring Slot Full Register */
+ u8 rsvd10[4];
+ __be32 oubring_prdcr_indx; /* Outbound Ring Producer Index */
+};
+
+/*
+ * Command Descriptor Block (CDB) for unicast move command.
+ * In RAID Engine terms, memcpy is done through move command
+ */
+struct move_cdb {
+ __be32 cdb32;
+};
+
+/* Data protection/integrity related fields */
+#define DPI_APPS_MASK 0xC0000000
+#define DPI_APPS_SHIFT 30
+#define DPI_REF_MASK 0x30000000
+#define DPI_REF_SHIFT 28
+#define DPI_GUARD_MASK 0x0C000000
+#define DPI_GUARD_SHIFT 26
+#define DPI_ATTR_MASK 0x03000000
+#define DPI_ATTR_SHIFT 24
+#define DPI_META_MASK 0x0000FFFF
+
+struct dpi_related {
+ __be32 dpi32;
+ __be32 ref;
+};
+
+/*
+ * CDB for GenQ command. In RAID Engine terminology, XOR is
+ * done through this command
+ */
+struct xor_cdb {
+ __be32 cdb32;
+ u8 gfm[16];
+ struct dpi_related dpi_dest_spec;
+ struct dpi_related dpi_src_spec[16];
+};
+
+/* CDB for no-op command */
+struct noop_cdb {
+ __be32 cdb32;
+};
+
+/*
+ * CDB for GenQQ command. In RAID Engine terminology, P/Q is
+ * done through this command
+ */
+struct pq_cdb {
+ __be32 cdb32;
+ u8 gfm_q1[16];
+ u8 gfm_q2[16];
+ struct dpi_related dpi_dest_spec[2];
+ struct dpi_related dpi_src_spec[16];
+};
+
+/* Compound frame */
+#define CF_ADDR_HIGH_MASK 0x000000FF
+#define CF_EXT_MASK 0x80000000
+#define CF_EXT_SHIFT 31
+#define CF_FINAL_MASK 0x40000000
+#define CF_FINAL_SHIFT 30
+#define CF_LENGTH_MASK 0x000FFFFF
+#define CF_BPID_MASK 0x00FF0000
+#define CF_BPID_SHIFT 16
+#define CF_OFFSET_MASK 0x00001FFF
+
+struct cmpnd_frame {
+ __be32 addr_high;
+ __be32 addr_low;
+ __be32 efrl32;
+ __be32 rbro32;
+};
+
+/* Frame descriptor */
+#define HWDESC_LIODN_MASK 0x3F000000
+#define HWDESC_LIODN_SHIFT 24
+#define HWDESC_BPID_MASK 0x00FF0000
+#define HWDESC_BPID_SHIFT 16
+#define HWDESC_ELIODN_MASK 0x0000F000
+#define HWDESC_ELIODN_SHIFT 12
+#define HWDESC_FMT_SHIFT 29
+#define HWDESC_FMT_MASK (0x3 << HWDESC_FMT_SHIFT)
+
+struct jr_hw_desc {
+ __be32 lbea32;
+ __be32 addr_low;
+ __be32 fmt32;
+ __be32 status;
+};
+
+/* Raid Engine device private data */
+struct re_drv_private {
+ u8 total_jrs;
+ struct dma_device dma_dev;
+ struct re_ctrl *re_regs;
+ struct re_jr *re_jrs[MAX_RE_JRS];
+ struct dma_pool *cf_desc_pool;
+ struct dma_pool *hw_desc_pool;
+};
+
+/* Per job ring data structure */
+struct re_jr {
+ char name[16];
+ spinlock_t desc_lock; /* queue lock */
+ struct list_head ack_q; /* wait to acked queue */
+ struct list_head active_q; /* already issued on hw, not completed */
+ struct list_head submit_q;
+ struct list_head free_q; /* alloc available queue */
+ struct device *dev;
+ struct re_drv_private *re_dev;
+ struct dma_chan chan;
+ struct jr_config_regs *jrregs;
+ int irq;
+ u32 alloc_count;
+
+ /* hw descriptor ring for inbound queue*/
+ dma_addr_t inb_phys_addr;
+ struct jr_hw_desc *inb_ring_virt_addr;
+ u32 inb_count;
+
+ /* hw descriptor ring for outbound queue */
+ dma_addr_t oub_phys_addr;
+ struct jr_hw_desc *oub_ring_virt_addr;
+ u32 oub_count;
+};
+
+/* Async transaction descriptor */
+struct fsl_re_dma_async_tx_desc {
+ struct dma_async_tx_descriptor async_tx;
+ struct list_head node;
+ struct jr_hw_desc hwdesc;
+ struct re_jr *jr;
+
+ /* hwdesc will point to cf_addr */
+ void *cf_addr;
+ dma_addr_t cf_paddr;
+
+ void *cdb_addr;
+ dma_addr_t cdb_paddr;
+ int status;
+};
--
1.8.3.2
^ permalink raw reply related
* Re: [PATCH] drivers/crypto/nx: prevent oops on module exit
From: Seth Jennings @ 2014-10-17 8:02 UTC (permalink / raw)
To: sjennings; +Cc: Robert Jennings, linuxppc-dev, Dan Streetman
In-Reply-To: <f05dbb0844d1f0431532a186b56034f3.squirrel@www.variantweb.net>
>> On Fri, 2014-10-17 at 09:43 +1100, Michael Ellerman wrote:
>>> On Thu, 2014-10-16 at 15:30 -0400, Dan Streetman wrote:
>>> > Check old_devdata->dev in nx-842 driver before accessing it, as
>>> > on systems without any nx-842 hardware, the ->dev will never be
>>> > set. Currently, the module will cause an oops during unload
>>> > since old_devdata->dev is null.
>>>
>>> Hi Dan,
>>>
>>> Patch looks reasonable. But I can't merge it, at least not without an
>>> ACK:
>>>
>>> $ ./scripts/get_maintainer.pl -f drivers/crypto/nx/
>>> Nathan Fontenot <nfont@linux.vnet.ibm.com> (supporter:IBM Power 842
>>> com...)
>>> Marcelo Henrique Cerri <mhcerri@linux.vnet.ibm.com> (supporter:IBM
>>> Power
>>> in-Nest...)
>>> Fionnuala Gunter <fin@linux.vnet.ibm.com> (supporter:IBM Power
>>> in-Nest...)
>>> Herbert Xu <herbert@gondor.apana.org.au> (maintainer:CRYPTO API)
>>> "David S. Miller" <davem@davemloft.net> (maintainer:CRYPTO API)
>>> linux-crypto@vger.kernel.org (open list:IBM Power in-Nest...)
>>> linux-kernel@vger.kernel.org (open list)
>>>
>>>
>>> If any of the above is out of date please send me a patch for
>>> MAINTAINERS.
>>
>> I think Dan now owns that driver, Dan, please confirm.
>
> I guess I'm not on the maintainer list anymore, as I shouldn't be
> since I don't work at IBM anymore.
Wow, I messed that up. Repeating myself :-/ Sorry for the noise.
Seth
>
> So... yeah. I was the original co-author of driver so I acked it
> but I'm not the maintainer anymore. Which I shouldn't be, since
> I don't work at IBM anymore.
>
> Seth
>
>>
>> Cheers,
>> Ben.
>>
>>
>>
>
>
^ permalink raw reply
* Re: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms
From: Viresh Kumar @ 2014-10-17 8:08 UTC (permalink / raw)
To: Tang Yuantian-B29983
Cc: Tang Yuantian, linuxppc-dev@ozlabs.org, Rafael J. Wysocki,
Linux Kernel Mailing List, linux-pm@vger.kernel.org
In-Reply-To: <1413515616-15874-1-git-send-email-B29983@freescale.com>
On 17 October 2014 08:43, <B29983@freescale.com> wrote:
Hi B29983 :)
> From: Tang Yuantian <Yuantian.Tang@freescale.com>
>
> Freescale introduced new ARM core-based SoCs which support dynamic
> frequency switch feature. DFS on new SoCs are compatible with current
> PowerPC CoreNet platforms. In order to support those new platforms,
> this driver needs to be slightly adjusted. The main changes include:
>
> 1. Changed the names of driver and functions in driver.
> 2. Added two new functions get_cpu_physical_id() and get_bus_freq().
> 3. Used a new way to get all the CPUs which sharing clock wire.
>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> ---
> drivers/cpufreq/Kconfig.arm | 8 ++
> drivers/cpufreq/Kconfig.powerpc | 11 +-
> drivers/cpufreq/Makefile | 2 +-
> .../{ppc-corenet-cpufreq.c => qoriq-cpufreq.c} | 150 ++++++++++++++-------
> 4 files changed, 114 insertions(+), 57 deletions(-)
> rename drivers/cpufreq/{ppc-corenet-cpufreq.c => qoriq-cpufreq.c} (72%)
>
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index 83a75dc..1925ae94 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -247,3 +247,11 @@ config ARM_TEGRA_CPUFREQ
> default y
> help
> This adds the CPUFreq driver support for TEGRA SOCs.
> +
> +config QORIQ_CPUFREQ
> + tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
> + depends on OF && COMMON_CLK
> + select CLK_PPC_CORENET
> + help
> + This adds the CPUFreq driver support for Freescale QorIQ SoCs
> + which are capable of changing the CPU's frequency dynamically.
> diff --git a/drivers/cpufreq/Kconfig.powerpc b/drivers/cpufreq/Kconfig.powerpc
> index 72564b7..3a34248 100644
> --- a/drivers/cpufreq/Kconfig.powerpc
> +++ b/drivers/cpufreq/Kconfig.powerpc
> @@ -23,14 +23,13 @@ config CPU_FREQ_MAPLE
> This adds support for frequency switching on Maple 970FX
> Evaluation Board and compatible boards (IBM JS2x blades).
>
> -config PPC_CORENET_CPUFREQ
> - tristate "CPU frequency scaling driver for Freescale E500MC SoCs"
> - depends on PPC_E500MC && OF && COMMON_CLK
> +config QORIQ_CPUFREQ
> + tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
> + depends on OF && COMMON_CLK
> select CLK_PPC_CORENET
> help
> - This adds the CPUFreq driver support for Freescale e500mc,
> - e5500 and e6500 series SoCs which are capable of changing
> - the CPU's frequency dynamically.
> + This adds the CPUFreq driver support for Freescale QorIQ SoCs
> + which are capable of changing the CPU's frequency dynamically.
>
> config CPU_FREQ_PMAC
> bool "Support for Apple PowerBooks"
Don't need this duplication at all. Just move this to Kconfig instead
of .arm and ppc.
> diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
> /**
> * struct cpu_data - per CPU data struct
> @@ -69,9 +68,6 @@ static const u32 *fmask;
>
> static DEFINE_PER_CPU(struct cpu_data *, cpu_data);
>
> -/* cpumask in a cluster */
> -static DEFINE_PER_CPU(cpumask_var_t, cpu_mask);
> -
> #ifndef CONFIG_SMP
> static inline const struct cpumask *cpu_core_mask(int cpu)
> {
> @@ -79,6 +75,79 @@ static inline const struct cpumask *cpu_core_mask(int cpu)
> }
> #endif
>
> +#if defined(CONFIG_PPC_E500MC)
> +static int get_cpu_physical_id(int cpu)
> +{
> + return get_hard_smp_processor_id(cpu);
> +}
> +#elif defined(CONFIG_ARM)
Wouldn't a #else work here as there are just two platforms we are
talking about ?
> +static int get_cpu_physical_id(int cpu)
> +{
> + return topology_core_id(cpu);
> +}
> +#endif
> +
> +static u32 get_bus_freq(void)
> +{
> + struct device_node *soc;
> + u32 sysfreq;
> +
> + soc = of_find_node_by_type(NULL, "soc");
> + if (!soc)
> + return 0;
> +
> + if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
> + sysfreq = 0;
> +
> + of_node_put(soc);
> +
> + return sysfreq;
> +}
> +
> +static struct device_node *cpu_to_clk_node(int cpu)
> +{
> + struct device_node *np, *clk_np;
> +
> + if (!cpu_present(cpu))
> + return NULL;
> +
> + np = of_get_cpu_node(cpu, NULL);
> + if (!np)
> + return NULL;
> +
> + clk_np = of_parse_phandle(np, "clocks", 0);
> + if (!clk_np)
> + return NULL;
> +
> + of_node_put(np);
> +
> + return clk_np;
> +}
> +
> +/* traverse cpu nodes to get cpu mask of sharing clock wire */
> +static void set_affected_cpus(struct cpufreq_policy *policy)
> +{
> + struct device_node *np, *clk_np;
> + struct cpumask *dstp = policy->cpus;
> + int i;
> +
> + np = cpu_to_clk_node(policy->cpu);
> + if (!np)
> + return;
> +
> + for_each_present_cpu(i) {
> + clk_np = cpu_to_clk_node(i);
> + if (!clk_np)
> + continue;
> +
> + if (clk_np == np)
> + cpumask_set_cpu(i, dstp);
So you are depending on matching the clock-nodes from DT for
getting this information, right ? There is nothing that the architecture
gives?
> +
> + of_node_put(clk_np);
> + }
> + of_node_put(np);
> +}
> +
> /* reduce the duplicated frequencies in frequency table */
> static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
> int count)
> @@ -105,6 +174,7 @@ static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
> int i, j, ind;
> unsigned int freq, max_freq;
> struct cpufreq_frequency_table table;
> +
> for (i = 0; i < count - 1; i++) {
> max_freq = freq_table[i].frequency;
> ind = i;
> @@ -129,7 +199,7 @@ static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
> }
> }
>
> -static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy)
> +static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
> {
> struct device_node *np;
> int i, count, ret;
> @@ -145,10 +215,8 @@ static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy)
> return -ENODEV;
>
> data = kzalloc(sizeof(*data), GFP_KERNEL);
> - if (!data) {
> - pr_err("%s: no memory\n", __func__);
Wasn't this useful ?
> + if (!data)
> goto err_np;
> - }
>
> policy->clk = of_clk_get(np, 0);
> if (IS_ERR(policy->clk)) {
> @@ -170,7 +238,7 @@ static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy)
> }
>
> if (fmask)
> - mask = fmask[get_hard_smp_processor_id(cpu)];
> + mask = fmask[get_cpu_physical_id(cpu)];
> else
> mask = 0x0;
>
> @@ -201,13 +269,13 @@ static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy)
> data->table = table;
>
> /* update ->cpus if we have cluster, no harm if not */
> - cpumask_copy(policy->cpus, per_cpu(cpu_mask, cpu));
> - for_each_cpu(i, per_cpu(cpu_mask, cpu))
> + set_affected_cpus(policy);
> + for_each_cpu(i, policy->cpus)
> per_cpu(cpu_data, i) = data;
Get rid of this per-cpu data and use policy->driver_data instead.
>
> /* Minimum transition latency is 12 platform clocks */
> u64temp = 12ULL * NSEC_PER_SEC;
> - do_div(u64temp, fsl_get_sys_freq());
> + do_div(u64temp, get_bus_freq());
> policy->cpuinfo.transition_latency = u64temp + 1;
>
> of_node_put(np);
> @@ -227,7 +295,7 @@ err_np:
> return -ENODEV;
> }
>
> -static int __exit corenet_cpufreq_cpu_exit(struct cpufreq_policy *policy)
> +static int __exit qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
> {
> struct cpu_data *data = per_cpu(cpu_data, policy->cpu);
> unsigned int cpu;
> @@ -236,13 +304,13 @@ static int __exit corenet_cpufreq_cpu_exit(struct cpufreq_policy *policy)
> kfree(data->table);
> kfree(data);
>
> - for_each_cpu(cpu, per_cpu(cpu_mask, policy->cpu))
> + for_each_cpu(cpu, policy->cpus)
> per_cpu(cpu_data, cpu) = NULL;
>
> return 0;
> }
>
> -static int corenet_cpufreq_target(struct cpufreq_policy *policy,
> +static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
> unsigned int index)
> {
> struct clk *parent;
> @@ -252,18 +320,18 @@ static int corenet_cpufreq_target(struct cpufreq_policy *policy,
> return clk_set_parent(policy->clk, parent);
> }
>
> -static struct cpufreq_driver ppc_corenet_cpufreq_driver = {
> - .name = "ppc_cpufreq",
> +static struct cpufreq_driver qoriq_cpufreq_driver = {
> + .name = "qoriq_cpufreq",
> .flags = CPUFREQ_CONST_LOOPS,
> - .init = corenet_cpufreq_cpu_init,
> - .exit = __exit_p(corenet_cpufreq_cpu_exit),
> + .init = qoriq_cpufreq_cpu_init,
> + .exit = __exit_p(qoriq_cpufreq_cpu_exit),
> .verify = cpufreq_generic_frequency_table_verify,
> - .target_index = corenet_cpufreq_target,
> + .target_index = qoriq_cpufreq_target,
> .get = cpufreq_generic_get,
> .attr = cpufreq_generic_attr,
> };
>
> -static const struct of_device_id node_matches[] __initdata = {
> +static const struct of_device_id node_matches[] __initconst = {
> { .compatible = "fsl,p2041-clockgen", .data = &sdata[0], },
> { .compatible = "fsl,p3041-clockgen", .data = &sdata[0], },
> { .compatible = "fsl,p5020-clockgen", .data = &sdata[1], },
> @@ -273,61 +341,43 @@ static const struct of_device_id node_matches[] __initdata = {
> {}
> };
>
> -static int __init ppc_corenet_cpufreq_init(void)
> +static int __init qoriq_cpufreq_init(void)
> {
> int ret;
> struct device_node *np;
> const struct of_device_id *match;
> const struct soc_data *data;
> - unsigned int cpu;
>
> np = of_find_matching_node(NULL, node_matches);
> if (!np)
> return -ENODEV;
>
> - for_each_possible_cpu(cpu) {
> - if (!alloc_cpumask_var(&per_cpu(cpu_mask, cpu), GFP_KERNEL))
> - goto err_mask;
> - cpumask_copy(per_cpu(cpu_mask, cpu), cpu_core_mask(cpu));
> - }
> -
> match = of_match_node(node_matches, np);
> data = match->data;
> if (data) {
> if (data->flag)
> fmask = data->freq_mask;
> - min_cpufreq = fsl_get_sys_freq();
> + min_cpufreq = get_bus_freq();
> } else {
> - min_cpufreq = fsl_get_sys_freq() / 2;
> + min_cpufreq = get_bus_freq() / 2;
> }
>
> of_node_put(np);
>
> - ret = cpufreq_register_driver(&ppc_corenet_cpufreq_driver);
> + ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
> if (!ret)
> - pr_info("Freescale PowerPC corenet CPU frequency scaling driver\n");
> + pr_info("Freescale QorIQ CPU frequency scaling driver\n");
>
> return ret;
> -
> -err_mask:
> - for_each_possible_cpu(cpu)
> - free_cpumask_var(per_cpu(cpu_mask, cpu));
> -
> - return -ENOMEM;
> }
> -module_init(ppc_corenet_cpufreq_init);
> +module_init(qoriq_cpufreq_init);
>
> -static void __exit ppc_corenet_cpufreq_exit(void)
> +static void __exit qoriq_cpufreq_exit(void)
> {
> - unsigned int cpu;
> -
> - for_each_possible_cpu(cpu)
> - free_cpumask_var(per_cpu(cpu_mask, cpu));
> -
> - cpufreq_unregister_driver(&ppc_corenet_cpufreq_driver);
> + cpufreq_unregister_driver(&qoriq_cpufreq_driver);
> }
> -module_exit(ppc_corenet_cpufreq_exit);
> +module_exit(qoriq_cpufreq_exit);
>
> MODULE_LICENSE("GPL");
> MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
> -MODULE_DESCRIPTION("cpufreq driver for Freescale e500mc series SoCs");
> +MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");
+ comments from Kumar Gala :)
^ permalink raw reply
* Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.
From: Vinod Koul @ 2014-10-17 7:30 UTC (permalink / raw)
To: Xuelin Shi
Cc: Harninder Rai, andriy.shevchenko@intel.com, Naveen Burmi,
dmaengine@vger.kernel.org, Dan Williams, linuxppc-dev
In-Reply-To: <4cd56c90d1e44249bd2d417005183ec7@BL2PR03MB147.namprd03.prod.outlook.com>
On Fri, Oct 17, 2014 at 02:13:20AM +0000, Xuelin Shi wrote:
> Hi Dan & Vinod,
>
> I have sent out the v4 of this patch and not received any further feedback yet.
>
> This patch looks ruled out from the patchwork. https://patchwork.kernel.org/project/linux-dmaengine/list/?page=2
>
> So do you know what happened to this patch?
First pls do not top post on mailing list
Yes I did clean patchworks this week for older patches, can you please
resubmit and we can review them
Thanks
--
~Vinod
>
> Thanks,
> Xuelin Shi
>
>
> -----Original Message-----
> From: Shi Xuelin-B29237
> Sent: 2014年4月15日 11:08
> To: 'Dan Williams'
> Cc: Koul, Vinod; andriy.shevchenko@intel.com; dmaengine@vger.kernel.org; linuxppc-dev; Rai Harninder-B01044; Burmi Naveen-B16502
> Subject: RE: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.
>
> Yes, "depend on !ASYNC_TX_CHANNEL_SWITCH" is better since fsldma selects this condition.
>
> Thanks,
> Xuelin Shi
>
> -----Original Message-----
> From: Dan Williams [mailto:dan.j.williams@intel.com]
> Sent: 2014年4月15日 8:30
> To: Shi Xuelin-B29237
> Cc: Koul, Vinod; andriy.shevchenko@intel.com; dmaengine@vger.kernel.org; linuxppc-dev; Rai Harninder-B01044; Burmi Naveen-B16502
> Subject: Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.
>
> On Sun, Apr 13, 2014 at 7:48 PM, Xuelin Shi <xuelin.shi@freescale.com> wrote:
> > Hi Dan,
> >
> > fsl dma device and fsl raid device are two differenct devices that
> > both provide async_memcpy capability, so I use !FSL_DMA to disable the fsl dma device.
> >
> > That's to say, either select fsldma device, either fsl raid device.
> >
>
> Right, but that's not what your proposed Kconfig dependency line does.
>
> You want something like "depends on FSL_SOC && !(FSL_DMA || FSL_DMA=m)"
>
> However, the more problematic option is ASYNC_TX_CHANNEL_SWITCH. That option is problematic for RAID, so I propose "depend on !ASYNC_TX_CHANNEL_SWITCH" since that addresses both problems.
>
>
--
^ permalink raw reply
* Re: [PATCH] drivers/crypto/nx: prevent oops on module exit
From: Seth Jennings @ 2014-10-17 7:59 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Seth Jennings, Dan Streetman, Robert Jennings
In-Reply-To: <1413499949.4567.3.camel@pasglop>
> On Fri, 2014-10-17 at 09:43 +1100, Michael Ellerman wrote:
>> On Thu, 2014-10-16 at 15:30 -0400, Dan Streetman wrote:
>> > Check old_devdata->dev in nx-842 driver before accessing it, as
>> > on systems without any nx-842 hardware, the ->dev will never be
>> > set. Currently, the module will cause an oops during unload
>> > since old_devdata->dev is null.
>>
>> Hi Dan,
>>
>> Patch looks reasonable. But I can't merge it, at least not without an
>> ACK:
>>
>> $ ./scripts/get_maintainer.pl -f drivers/crypto/nx/
>> Nathan Fontenot <nfont@linux.vnet.ibm.com> (supporter:IBM Power 842
>> com...)
>> Marcelo Henrique Cerri <mhcerri@linux.vnet.ibm.com> (supporter:IBM Power
>> in-Nest...)
>> Fionnuala Gunter <fin@linux.vnet.ibm.com> (supporter:IBM Power
>> in-Nest...)
>> Herbert Xu <herbert@gondor.apana.org.au> (maintainer:CRYPTO API)
>> "David S. Miller" <davem@davemloft.net> (maintainer:CRYPTO API)
>> linux-crypto@vger.kernel.org (open list:IBM Power in-Nest...)
>> linux-kernel@vger.kernel.org (open list)
>>
>>
>> If any of the above is out of date please send me a patch for
>> MAINTAINERS.
>
> I think Dan now owns that driver, Dan, please confirm.
I guess I'm not on the maintainer list anymore, as I shouldn't be
since I don't work at IBM anymore.
So... yeah. I was the original co-author of driver so I acked it
but I'm not the maintainer anymore. Which I shouldn't be, since
I don't work at IBM anymore.
Seth
>
> Cheers,
> Ben.
>
>
>
^ permalink raw reply
* Re: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms
From: Kumar Gala @ 2014-10-17 8:03 UTC (permalink / raw)
To: b29983
Cc: Tang Yuantian, viresh.kumar, linux-pm, rjw, linux-kernel,
linuxppc-dev
In-Reply-To: <1413515616-15874-1-git-send-email-B29983@freescale.com>
On Oct 17, 2014, at 5:13 AM, b29983@freescale.com wrote:
> From: Tang Yuantian <Yuantian.Tang@freescale.com>
>=20
> Freescale introduced new ARM core-based SoCs which support dynamic
> frequency switch feature. DFS on new SoCs are compatible with current
> PowerPC CoreNet platforms. In order to support those new platforms,
> this driver needs to be slightly adjusted. The main changes include:
>=20
> 1. Changed the names of driver and functions in driver.
split the name changes/renaming into a separate patch from the other =
changes.
> 2. Added two new functions get_cpu_physical_id() and get_bus_freq().
> 3. Used a new way to get all the CPUs which sharing clock wire.
>=20
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> ---
> drivers/cpufreq/Kconfig.arm | 8 ++
> drivers/cpufreq/Kconfig.powerpc | 11 +-
> drivers/cpufreq/Makefile | 2 +-
> .../{ppc-corenet-cpufreq.c =3D> qoriq-cpufreq.c} | 150 =
++++++++++++++-------
> 4 files changed, 114 insertions(+), 57 deletions(-)
> rename drivers/cpufreq/{ppc-corenet-cpufreq.c =3D> qoriq-cpufreq.c} =
(72%)
>=20
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index 83a75dc..1925ae94 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -247,3 +247,11 @@ config ARM_TEGRA_CPUFREQ
> default y
> help
> This adds the CPUFreq driver support for TEGRA SOCs.
> +
> +config QORIQ_CPUFREQ
> + tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
> + depends on OF && COMMON_CLK
> + select CLK_PPC_CORENET
Why are you not also renaming =91CLK_PPC_CORENET=92 to =91CLK_QORIQ=92 =
or something like that? Seems rather odd to select a PPC CLK support on =
ARM ;)
> + help
> + This adds the CPUFreq driver support for Freescale QorIQ SoCs
> + which are capable of changing the CPU's frequency dynamically.
> diff --git a/drivers/cpufreq/Kconfig.powerpc =
b/drivers/cpufreq/Kconfig.powerpc
> index 72564b7..3a34248 100644
> --- a/drivers/cpufreq/Kconfig.powerpc
> +++ b/drivers/cpufreq/Kconfig.powerpc
> @@ -23,14 +23,13 @@ config CPU_FREQ_MAPLE
> This adds support for frequency switching on Maple 970FX
> Evaluation Board and compatible boards (IBM JS2x blades).
>=20
> -config PPC_CORENET_CPUFREQ
> - tristate "CPU frequency scaling driver for Freescale E500MC =
SoCs"
> - depends on PPC_E500MC && OF && COMMON_CLK
> +config QORIQ_CPUFREQ
> + tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
> + depends on OF && COMMON_CLK
> select CLK_PPC_CORENET
> help
> - This adds the CPUFreq driver support for Freescale e500mc,
> - e5500 and e6500 series SoCs which are capable of changing
> - the CPU's frequency dynamically.
> + This adds the CPUFreq driver support for Freescale QorIQ SoCs
> + which are capable of changing the CPU's frequency dynamically.
>=20
> config CPU_FREQ_PMAC
> bool "Support for Apple PowerBooks"
> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> index 40c53dc..0020049 100644
> --- a/drivers/cpufreq/Makefile
> +++ b/drivers/cpufreq/Makefile
> @@ -84,7 +84,7 @@ obj-$(CONFIG_CPU_FREQ_CBE) +=3D =
ppc-cbe-cpufreq.o
> ppc-cbe-cpufreq-y +=3D ppc_cbe_cpufreq_pervasive.o =
ppc_cbe_cpufreq.o
> obj-$(CONFIG_CPU_FREQ_CBE_PMI) +=3D =
ppc_cbe_cpufreq_pmi.o
> obj-$(CONFIG_CPU_FREQ_MAPLE) +=3D maple-cpufreq.o
> -obj-$(CONFIG_PPC_CORENET_CPUFREQ) +=3D ppc-corenet-cpufreq.o
> +obj-$(CONFIG_QORIQ_CPUFREQ) +=3D qoriq-cpufreq.o
> obj-$(CONFIG_CPU_FREQ_PMAC) +=3D pmac32-cpufreq.o
> obj-$(CONFIG_CPU_FREQ_PMAC64) +=3D pmac64-cpufreq.o
> obj-$(CONFIG_PPC_PASEMI_CPUFREQ) +=3D pasemi-cpufreq.o
> diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c =
b/drivers/cpufreq/qoriq-cpufreq.c
> similarity index 72%
> rename from drivers/cpufreq/ppc-corenet-cpufreq.c
> rename to drivers/cpufreq/qoriq-cpufreq.c
> index bee5df7..80def0c 100644
> --- a/drivers/cpufreq/ppc-corenet-cpufreq.c
> +++ b/drivers/cpufreq/qoriq-cpufreq.c
> @@ -1,7 +1,7 @@
> /*
> * Copyright 2013 Freescale Semiconductor, Inc.
> *
> - * CPU Frequency Scaling driver for Freescale PowerPC corenet SoCs.
> + * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
> *
> * This program is free software; you can redistribute it and/or =
modify
> * it under the terms of the GNU General Public License version 2 as
> @@ -20,7 +20,6 @@
> #include <linux/of.h>
> #include <linux/slab.h>
> #include <linux/smp.h>
> -#include <sysdev/fsl_soc.h>
>=20
> /**
> * struct cpu_data - per CPU data struct
> @@ -69,9 +68,6 @@ static const u32 *fmask;
>=20
> static DEFINE_PER_CPU(struct cpu_data *, cpu_data);
>=20
> -/* cpumask in a cluster */
> -static DEFINE_PER_CPU(cpumask_var_t, cpu_mask);
> -
> #ifndef CONFIG_SMP
> static inline const struct cpumask *cpu_core_mask(int cpu)
> {
> @@ -79,6 +75,79 @@ static inline const struct cpumask =
*cpu_core_mask(int cpu)
> }
> #endif
>=20
> +#if defined(CONFIG_PPC_E500MC)
Probably should just be CONFIG_PPC, but do we need this at all. Can=92t =
we just use topology_core_id() on both ARM & PPC?
> +static int get_cpu_physical_id(int cpu)
> +{
> + return get_hard_smp_processor_id(cpu);
> +}
> +#elif defined(CONFIG_ARM)
> +static int get_cpu_physical_id(int cpu)
> +{
> + return topology_core_id(cpu);
> +}
> +#endif
> +
> +static u32 get_bus_freq(void)
> +{
> + struct device_node *soc;
> + u32 sysfreq;
> +
> + soc =3D of_find_node_by_type(NULL, "soc");
> + if (!soc)
> + return 0;
> +
> + if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
> + sysfreq =3D 0;
> +
> + of_node_put(soc);
> +
> + return sysfreq;
> +}
> +
> +static struct device_node *cpu_to_clk_node(int cpu)
> +{
> + struct device_node *np, *clk_np;
> +
> + if (!cpu_present(cpu))
> + return NULL;
> +
> + np =3D of_get_cpu_node(cpu, NULL);
> + if (!np)
> + return NULL;
> +
> + clk_np =3D of_parse_phandle(np, "clocks", 0);
> + if (!clk_np)
> + return NULL;
> +
> + of_node_put(np);
> +
> + return clk_np;
> +}
> +
> +/* traverse cpu nodes to get cpu mask of sharing clock wire */
> +static void set_affected_cpus(struct cpufreq_policy *policy)
> +{
> + struct device_node *np, *clk_np;
> + struct cpumask *dstp =3D policy->cpus;
> + int i;
> +
> + np =3D cpu_to_clk_node(policy->cpu);
> + if (!np)
> + return;
> +
> + for_each_present_cpu(i) {
> + clk_np =3D cpu_to_clk_node(i);
> + if (!clk_np)
> + continue;
> +
> + if (clk_np =3D=3D np)
> + cpumask_set_cpu(i, dstp);
> +
> + of_node_put(clk_np);
> + }
> + of_node_put(np);
> +}
> +
> /* reduce the duplicated frequencies in frequency table */
> static void freq_table_redup(struct cpufreq_frequency_table =
*freq_table,
> int count)
> @@ -105,6 +174,7 @@ static void freq_table_sort(struct =
cpufreq_frequency_table *freq_table,
> int i, j, ind;
> unsigned int freq, max_freq;
> struct cpufreq_frequency_table table;
> +
> for (i =3D 0; i < count - 1; i++) {
> max_freq =3D freq_table[i].frequency;
> ind =3D i;
> @@ -129,7 +199,7 @@ static void freq_table_sort(struct =
cpufreq_frequency_table *freq_table,
> }
> }
>=20
> -static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy)
> +static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
> {
> struct device_node *np;
> int i, count, ret;
> @@ -145,10 +215,8 @@ static int corenet_cpufreq_cpu_init(struct =
cpufreq_policy *policy)
> return -ENODEV;
>=20
> data =3D kzalloc(sizeof(*data), GFP_KERNEL);
> - if (!data) {
> - pr_err("%s: no memory\n", __func__);
> + if (!data)
> goto err_np;
> - }
>=20
> policy->clk =3D of_clk_get(np, 0);
> if (IS_ERR(policy->clk)) {
> @@ -170,7 +238,7 @@ static int corenet_cpufreq_cpu_init(struct =
cpufreq_policy *policy)
> }
>=20
> if (fmask)
> - mask =3D fmask[get_hard_smp_processor_id(cpu)];
> + mask =3D fmask[get_cpu_physical_id(cpu)];
> else
> mask =3D 0x0;
>=20
> @@ -201,13 +269,13 @@ static int corenet_cpufreq_cpu_init(struct =
cpufreq_policy *policy)
> data->table =3D table;
>=20
> /* update ->cpus if we have cluster, no harm if not */
> - cpumask_copy(policy->cpus, per_cpu(cpu_mask, cpu));
> - for_each_cpu(i, per_cpu(cpu_mask, cpu))
> + set_affected_cpus(policy);
> + for_each_cpu(i, policy->cpus)
> per_cpu(cpu_data, i) =3D data;
>=20
> /* Minimum transition latency is 12 platform clocks */
> u64temp =3D 12ULL * NSEC_PER_SEC;
> - do_div(u64temp, fsl_get_sys_freq());
> + do_div(u64temp, get_bus_freq());
> policy->cpuinfo.transition_latency =3D u64temp + 1;
>=20
> of_node_put(np);
> @@ -227,7 +295,7 @@ err_np:
> return -ENODEV;
> }
>=20
> -static int __exit corenet_cpufreq_cpu_exit(struct cpufreq_policy =
*policy)
> +static int __exit qoriq_cpufreq_cpu_exit(struct cpufreq_policy =
*policy)
> {
> struct cpu_data *data =3D per_cpu(cpu_data, policy->cpu);
> unsigned int cpu;
> @@ -236,13 +304,13 @@ static int __exit =
corenet_cpufreq_cpu_exit(struct cpufreq_policy *policy)
> kfree(data->table);
> kfree(data);
>=20
> - for_each_cpu(cpu, per_cpu(cpu_mask, policy->cpu))
> + for_each_cpu(cpu, policy->cpus)
> per_cpu(cpu_data, cpu) =3D NULL;
>=20
> return 0;
> }
>=20
> -static int corenet_cpufreq_target(struct cpufreq_policy *policy,
> +static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
> unsigned int index)
> {
> struct clk *parent;
> @@ -252,18 +320,18 @@ static int corenet_cpufreq_target(struct =
cpufreq_policy *policy,
> return clk_set_parent(policy->clk, parent);
> }
>=20
> -static struct cpufreq_driver ppc_corenet_cpufreq_driver =3D {
> - .name =3D "ppc_cpufreq",
> +static struct cpufreq_driver qoriq_cpufreq_driver =3D {
> + .name =3D "qoriq_cpufreq",
> .flags =3D CPUFREQ_CONST_LOOPS,
> - .init =3D corenet_cpufreq_cpu_init,
> - .exit =3D __exit_p(corenet_cpufreq_cpu_exit),
> + .init =3D qoriq_cpufreq_cpu_init,
> + .exit =3D __exit_p(qoriq_cpufreq_cpu_exit),
> .verify =3D cpufreq_generic_frequency_table_verify,
> - .target_index =3D corenet_cpufreq_target,
> + .target_index =3D qoriq_cpufreq_target,
> .get =3D cpufreq_generic_get,
> .attr =3D cpufreq_generic_attr,
> };
>=20
> -static const struct of_device_id node_matches[] __initdata =3D {
> +static const struct of_device_id node_matches[] __initconst =3D {
> { .compatible =3D "fsl,p2041-clockgen", .data =3D &sdata[0], },
> { .compatible =3D "fsl,p3041-clockgen", .data =3D &sdata[0], },
> { .compatible =3D "fsl,p5020-clockgen", .data =3D &sdata[1], },
> @@ -273,61 +341,43 @@ static const struct of_device_id node_matches[] =
__initdata =3D {
> {}
> };
>=20
> -static int __init ppc_corenet_cpufreq_init(void)
> +static int __init qoriq_cpufreq_init(void)
> {
> int ret;
> struct device_node *np;
> const struct of_device_id *match;
> const struct soc_data *data;
> - unsigned int cpu;
>=20
> np =3D of_find_matching_node(NULL, node_matches);
> if (!np)
> return -ENODEV;
>=20
> - for_each_possible_cpu(cpu) {
> - if (!alloc_cpumask_var(&per_cpu(cpu_mask, cpu), =
GFP_KERNEL))
> - goto err_mask;
> - cpumask_copy(per_cpu(cpu_mask, cpu), =
cpu_core_mask(cpu));
> - }
> -
> match =3D of_match_node(node_matches, np);
> data =3D match->data;
> if (data) {
> if (data->flag)
> fmask =3D data->freq_mask;
> - min_cpufreq =3D fsl_get_sys_freq();
> + min_cpufreq =3D get_bus_freq();
> } else {
> - min_cpufreq =3D fsl_get_sys_freq() / 2;
> + min_cpufreq =3D get_bus_freq() / 2;
> }
>=20
> of_node_put(np);
>=20
> - ret =3D cpufreq_register_driver(&ppc_corenet_cpufreq_driver);
> + ret =3D cpufreq_register_driver(&qoriq_cpufreq_driver);
> if (!ret)
> - pr_info("Freescale PowerPC corenet CPU frequency scaling =
driver\n");
> + pr_info("Freescale QorIQ CPU frequency scaling =
driver\n");
>=20
> return ret;
> -
> -err_mask:
> - for_each_possible_cpu(cpu)
> - free_cpumask_var(per_cpu(cpu_mask, cpu));
> -
> - return -ENOMEM;
> }
> -module_init(ppc_corenet_cpufreq_init);
> +module_init(qoriq_cpufreq_init);
>=20
> -static void __exit ppc_corenet_cpufreq_exit(void)
> +static void __exit qoriq_cpufreq_exit(void)
> {
> - unsigned int cpu;
> -
> - for_each_possible_cpu(cpu)
> - free_cpumask_var(per_cpu(cpu_mask, cpu));
> -
> - cpufreq_unregister_driver(&ppc_corenet_cpufreq_driver);
> + cpufreq_unregister_driver(&qoriq_cpufreq_driver);
> }
> -module_exit(ppc_corenet_cpufreq_exit);
> +module_exit(qoriq_cpufreq_exit);
>=20
> MODULE_LICENSE("GPL");
> MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
> -MODULE_DESCRIPTION("cpufreq driver for Freescale e500mc series =
SoCs");
> +MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");
> --=20
> 2.1.0.27.g96db324
>=20
> --
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