* [PATCH v2 3/6] powerpc/cache: add cache flush operation for various e500
From: Ran Wang @ 2018-04-11 6:35 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Rob Herring, Mark Rutland, Scott Wood, Kumar Gala, Li Yang
Cc: Zhao Chenhui, linuxppc-dev, linux-kernel, devicetree,
linux-arm-kernel, Ran Wang
In-Reply-To: <20180411063551.30368-1-ran.wang_1@nxp.com>
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback function will flush all caches in the current cpu.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Changes in v2:
- no change
arch/powerpc/include/asm/cputable.h | 12 ++++
arch/powerpc/kernel/asm-offsets.c | 3 +
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 81 +++++++++++++++++++++++++++++
arch/powerpc/kernel/cputable.c | 4 ++
4 files changed, 100 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 2e2bacb..d04c46d 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -44,6 +44,14 @@ enum powerpc_pmc_type {
extern int machine_check_e500(struct pt_regs *regs);
extern int machine_check_e200(struct pt_regs *regs);
extern int machine_check_47x(struct pt_regs *regs);
+
+#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC)
+extern void __flush_caches_e500v2(void);
+extern void __flush_caches_e500mc(void);
+extern void __flush_caches_e5500(void);
+extern void __flush_caches_e6500(void);
+#endif
+
int machine_check_8xx(struct pt_regs *regs);
extern void cpu_down_flush_e500v2(void);
@@ -70,6 +78,10 @@ struct cpu_spec {
/* flush caches inside the current cpu */
void (*cpu_down_flush)(void);
+#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC)
+ /* flush caches of the cpu which is running the function */
+ void (*cpu_flush_caches)(void);
+#endif
/* number of performance monitor counters */
unsigned int num_pmcs;
enum powerpc_pmc_type pmc_type;
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index ea5eb91..cb4b869 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -351,6 +351,9 @@ int main(void)
OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
+#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC)
+ OFFSET(CPU_FLUSH_CACHES, cpu_spec, cpu_flush_caches);
+#endif
OFFSET(pbe_address, pbe, address);
OFFSET(pbe_orig_address, pbe, orig_address);
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 462aed9..e94eb41 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -345,3 +345,84 @@ _GLOBAL(cpu_down_flush_e5500)
/* L1 Data Cache of e6500 contains no modified data, no flush is required */
_GLOBAL(cpu_down_flush_e6500)
blr
+
+_GLOBAL(__flush_caches_e500v2)
+ mflr r0
+ bl flush_dcache_L1
+ mtlr r0
+ blr
+
+_GLOBAL(__flush_caches_e500mc)
+_GLOBAL(__flush_caches_e5500)
+ mflr r0
+ bl flush_dcache_L1
+ bl flush_backside_L2_cache
+ mtlr r0
+ blr
+
+/* L1 Data Cache of e6500 contains no modified data, no flush is required */
+_GLOBAL(__flush_caches_e6500)
+ blr
+
+ /* r3 = virtual address of L2 controller, WIMG = 01xx */
+_GLOBAL(flush_disable_L2)
+ /* It's a write-through cache, so only invalidation is needed. */
+ mbar
+ isync
+ lwz r4, 0(r3)
+ li r5, 1
+ rlwimi r4, r5, 30, 0xc0000000
+ stw r4, 0(r3)
+
+ /* Wait for the invalidate to finish */
+1: lwz r4, 0(r3)
+ andis. r4, r4, 0x4000
+ bne 1b
+ mbar
+
+ blr
+
+ /* r3 = virtual address of L2 controller, WIMG = 01xx */
+_GLOBAL(invalidate_enable_L2)
+ mbar
+ isync
+ lwz r4, 0(r3)
+ li r5, 3
+ rlwimi r4, r5, 30, 0xc0000000
+ stw r4, 0(r3)
+
+ /* Wait for the invalidate to finish */
+1: lwz r4, 0(r3)
+ andis. r4, r4, 0x4000
+ bne 1b
+ mbar
+
+ blr
+
+/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
+_GLOBAL(__flush_disable_L1)
+ mflr r10
+ bl flush_dcache_L1 /* Flush L1 d-cache */
+ mtlr r10
+
+ mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
+ li r5, 2
+ rlwimi r4, r5, 0, 3
+
+ msync
+ isync
+ mtspr SPRN_L1CSR0, r4
+ isync
+
+1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
+ andi. r4, r4, 2
+ bne 1b
+
+ mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */
+ li r5, 2
+ rlwimi r4, r5, 0, 3
+
+ mtspr SPRN_L1CSR1, r4
+ isync
+
+ blr
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index c40a9fc..eec3ca7 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -2100,6 +2100,7 @@
.machine_check = machine_check_e500,
.platform = "ppc8548",
.cpu_down_flush = cpu_down_flush_e500v2,
+ .cpu_flush_caches = __flush_caches_e500v2,
},
#else
{ /* e500mc */
@@ -2120,6 +2121,7 @@
.machine_check = machine_check_e500mc,
.platform = "ppce500mc",
.cpu_down_flush = cpu_down_flush_e500mc,
+ .cpu_flush_caches = __flush_caches_e500mc,
},
#endif /* CONFIG_PPC_E500MC */
#endif /* CONFIG_PPC32 */
@@ -2145,6 +2147,7 @@
.machine_check = machine_check_e500mc,
.platform = "ppce5500",
.cpu_down_flush = cpu_down_flush_e5500,
+ .cpu_flush_caches = __flush_caches_e5500,
},
{ /* e6500 */
.pvr_mask = 0xffff0000,
@@ -2168,6 +2171,7 @@
.machine_check = machine_check_e500mc,
.platform = "ppce6500",
.cpu_down_flush = cpu_down_flush_e6500,
+ .cpu_flush_caches = __flush_caches_e6500,
},
#endif /* CONFIG_PPC_E500MC */
#ifdef CONFIG_PPC32
--
1.7.1
^ permalink raw reply related
* [PATCH v2 2/6] drivers/soc/fsl: add EPU FSM configuration for deep sleep
From: Ran Wang @ 2018-04-11 6:35 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Rob Herring, Mark Rutland, Scott Wood, Kumar Gala, Li Yang
Cc: Zhao Chenhui, linuxppc-dev, linux-kernel, devicetree,
linux-arm-kernel, Ran Wang
In-Reply-To: <20180411063551.30368-1-ran.wang_1@nxp.com>
In the last stage of deep sleep, software will trigger a Finite
State Machine (FSM) to control the hardware procedure, such a
board isolation, killing PLLs, removing power, and so on.
When the system is waked up by an interrupt, the FSM controls
the hardware to complete the early resume procedure.
This patch configure the EPU FSM preparing for deep sleep.
Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Changes in v2:
- Resolve warnning of scripts/checkpatch.pl
drivers/soc/fsl/Kconfig | 7 +
drivers/soc/fsl/Makefile | 1 +
drivers/soc/fsl/sleep_fsm.c | 279 +++++++++++++++++++++++++++++++++++++++++++
drivers/soc/fsl/sleep_fsm.h | 130 ++++++++++++++++++++
4 files changed, 417 insertions(+), 0 deletions(-)
create mode 100644 drivers/soc/fsl/sleep_fsm.c
create mode 100644 drivers/soc/fsl/sleep_fsm.h
diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig
index 7a9fb9b..4222bd5 100644
--- a/drivers/soc/fsl/Kconfig
+++ b/drivers/soc/fsl/Kconfig
@@ -16,3 +16,10 @@ config FSL_GUTS
Initially only reading SVR and registering soc device are supported.
Other guts accesses, such as reading RCW, should eventually be moved
into this driver as well.
+
+config FSL_SLEEP_FSM
+ bool
+ help
+ This driver configures a hardware FSM (Finite State Machine) for deep sleep.
+ The FSM is used to finish clean-ups at the last stage of system entering deep
+ sleep, and also wakes up system when a wake up event happens.
diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile
index 44b3beb..28c38c3 100644
--- a/drivers/soc/fsl/Makefile
+++ b/drivers/soc/fsl/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_FSL_DPAA) += qbman/
obj-$(CONFIG_QUICC_ENGINE) += qe/
obj-$(CONFIG_CPM) += qe/
obj-$(CONFIG_FSL_GUTS) += guts.o
+obj-$(CONFIG_FSL_SLEEP_FSM) += sleep_fsm.o
diff --git a/drivers/soc/fsl/sleep_fsm.c b/drivers/soc/fsl/sleep_fsm.c
new file mode 100644
index 0000000..a303098
--- /dev/null
+++ b/drivers/soc/fsl/sleep_fsm.c
@@ -0,0 +1,279 @@
+/*
+ * deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2018 NXP
+ *
+ * Author: Hongbo Zhang <hongbo.zhang@freescale.com>
+ * Chenhui Zhao <chenhui.zhao@freescale.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/types.h>
+
+#include "sleep_fsm.h"
+/*
+ * These values are from chip's reference manual. For example,
+ * the values for T1040 can be found in "8.4.3.8 Programming
+ * supporting deep sleep mode" of Chapter 8 "Run Control and
+ * Power Management (RCPM)".
+ * The default value can be applied to T104x, LS1021.
+ */
+struct fsm_reg_vals epu_default_val[] = {
+ /* EPGCR (Event Processor Global Control Register) */
+ {EPGCR, 0},
+ /* EPECR (Event Processor Event Control Registers) */
+ {EPECR0 + EPECR_STRIDE * 0, 0},
+ {EPECR0 + EPECR_STRIDE * 1, 0},
+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+ {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
+ {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
+ {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
+ {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
+ {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
+ {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
+ {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
+ /*
+ * EPEVTCR (Event Processor EVT Pin Control Registers)
+ * SCU8 triger EVT2, and SCU11 triger EVT9
+ */
+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
+ /* EPCMPR (Event Processor Counter Compare Registers) */
+ {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
+ {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
+ /* EPCCR (Event Processor Counter Control Registers) */
+ {EPCCR0 + EPCCR_STRIDE * 0, 0},
+ {EPCCR0 + EPCCR_STRIDE * 1, 0},
+ {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 3, 0},
+ {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 6, 0},
+ {EPCCR0 + EPCCR_STRIDE * 7, 0},
+ {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 13, 0},
+ {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
+ /* EPSMCR (Event Processor SCU Mux Control Registers) */
+ {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
+ {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
+ {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
+ {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
+ {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
+ {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
+ {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
+ {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
+ {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
+ {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
+ /* EPACR (Event Processor Action Control Registers) */
+ {EPACR0 + EPACR_STRIDE * 0, 0},
+ {EPACR0 + EPACR_STRIDE * 1, 0},
+ {EPACR0 + EPACR_STRIDE * 2, 0},
+ {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
+ {EPACR0 + EPACR_STRIDE * 4, 0},
+ {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
+ {EPACR0 + EPACR_STRIDE * 6, 0},
+ {EPACR0 + EPACR_STRIDE * 7, 0},
+ {EPACR0 + EPACR_STRIDE * 8, 0},
+ {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
+ {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
+ {EPACR0 + EPACR_STRIDE * 11, 0},
+ {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
+ {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
+ {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
+ {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
+ /* EPIMCR (Event Processor Input Mux Control Registers) */
+ {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
+ /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+ {EPXTRIGCR, 0x0000FFDF},
+ /* end */
+ {FSM_END_FLAG, 0},
+};
+
+struct fsm_reg_vals npc_default_val[] = {
+ /* NPC triggered Memory-Mapped Access Registers */
+ {NCR, 0x80000000},
+ {MCCR1, 0},
+ {MCSR1, 0},
+ {MMAR1LO, 0},
+ {MMAR1HI, 0},
+ {MMDR1, 0},
+ {MCSR2, 0},
+ {MMAR2LO, 0},
+ {MMAR2HI, 0},
+ {MMDR2, 0},
+ {MCSR3, 0x80000000},
+ {MMAR3LO, 0x000E2130},
+ {MMAR3HI, 0x00030000},
+ {MMDR3, 0x00020000},
+ /* end */
+ {FSM_END_FLAG, 0},
+};
+
+/**
+ * fsl_fsm_setup - Configure EPU's FSM registers
+ * @base: the base address of registers
+ * @val: Pointer to address-value pairs for FSM registers
+ */
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
+{
+ struct fsm_reg_vals *data = val;
+
+ WARN_ON(!base || !data);
+ while (data->offset != FSM_END_FLAG) {
+ iowrite32be(data->value, base + data->offset);
+ data++;
+ }
+}
+
+void fsl_epu_setup_default(void __iomem *epu_base)
+{
+ fsl_fsm_setup(epu_base, epu_default_val);
+}
+
+void fsl_npc_setup_default(void __iomem *npc_base)
+{
+ fsl_fsm_setup(npc_base, npc_default_val);
+}
+
+void fsl_epu_clean_default(void __iomem *epu_base)
+{
+ u32 offset;
+
+ /* follow the exact sequence to clear the registers */
+ /* Clear EPACRn */
+ for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPEVTCRn */
+ for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPGCR */
+ iowrite32be(0, epu_base + EPGCR);
+
+ /* Clear EPSMCRn */
+ for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCCRn */
+ for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCMPRn */
+ for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCTRn */
+ for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPIMCRn */
+ for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPXTRIGCRn */
+ iowrite32be(0, epu_base + EPXTRIGCR);
+
+ /* Clear EPECRn */
+ for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+}
diff --git a/drivers/soc/fsl/sleep_fsm.h b/drivers/soc/fsl/sleep_fsm.h
new file mode 100644
index 0000000..e0013c0
--- /dev/null
+++ b/drivers/soc/fsl/sleep_fsm.h
@@ -0,0 +1,130 @@
+/*
+ * deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_SLEEP_FSM_H
+#define _FSL_SLEEP_FSM_H
+
+#define FSL_STRIDE_4B 4
+#define FSL_STRIDE_8B 8
+
+/* End flag */
+#define FSM_END_FLAG 0xFFFFFFFFUL
+
+/* Block offsets */
+#define RCPM_BLOCK_OFFSET 0x00022000
+#define EPU_BLOCK_OFFSET 0x00000000
+#define NPC_BLOCK_OFFSET 0x00001000
+
+/* EPGCR (Event Processor Global Control Register) */
+#define EPGCR 0x000
+
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
+#define EPEVTCR0 0x050
+#define EPEVTCR9 0x074
+#define EPEVTCR_STRIDE FSL_STRIDE_4B
+
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+#define EPXTRIGCR 0x090
+
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
+#define EPIMCR0 0x100
+#define EPIMCR31 0x17C
+#define EPIMCR_STRIDE FSL_STRIDE_4B
+
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
+#define EPSMCR0 0x200
+#define EPSMCR15 0x278
+#define EPSMCR_STRIDE FSL_STRIDE_8B
+
+/* EPECR0-15 (Event Processor Event Control Registers) */
+#define EPECR0 0x300
+#define EPECR15 0x33C
+#define EPECR_STRIDE FSL_STRIDE_4B
+
+/* EPACR0-15 (Event Processor Action Control Registers) */
+#define EPACR0 0x400
+#define EPACR15 0x43C
+#define EPACR_STRIDE FSL_STRIDE_4B
+
+/* EPCCRi0-15 (Event Processor Counter Control Registers) */
+#define EPCCR0 0x800
+#define EPCCR15 0x83C
+#define EPCCR31 0x87C
+#define EPCCR_STRIDE FSL_STRIDE_4B
+
+/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
+#define EPCMPR0 0x900
+#define EPCMPR15 0x93C
+#define EPCMPR31 0x97C
+#define EPCMPR_STRIDE FSL_STRIDE_4B
+
+/* EPCTR0-31 (Event Processor Counter Register) */
+#define EPCTR0 0xA00
+#define EPCTR31 0xA7C
+#define EPCTR_STRIDE FSL_STRIDE_4B
+
+/* NPC triggered Memory-Mapped Access Registers */
+#define NCR 0x000
+#define MCCR1 0x0CC
+#define MCSR1 0x0D0
+#define MMAR1LO 0x0D4
+#define MMAR1HI 0x0D8
+#define MMDR1 0x0DC
+#define MCSR2 0x0E0
+#define MMAR2LO 0x0E4
+#define MMAR2HI 0x0E8
+#define MMDR2 0x0EC
+#define MCSR3 0x0F0
+#define MMAR3LO 0x0F4
+#define MMAR3HI 0x0F8
+#define MMDR3 0x0FC
+
+/* RCPM Core State Action Control Register 0 */
+#define CSTTACR0 0xB00
+
+/* RCPM Core Group 1 Configuration Register 0 */
+#define CG1CR0 0x31C
+
+struct fsm_reg_vals {
+ u32 offset;
+ u32 value;
+};
+
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val);
+void fsl_epu_setup_default(void __iomem *epu_base);
+void fsl_npc_setup_default(void __iomem *npc_base);
+void fsl_epu_clean_default(void __iomem *epu_base);
+
+#endif /* _FSL_SLEEP_FSM_H */
--
1.7.1
^ permalink raw reply related
* [PATCH v2 1/6] powerpc/pm: Fix suspend=n in menuconfig for e500mc platforms.
From: Ran Wang @ 2018-04-11 6:35 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Rob Herring, Mark Rutland, Scott Wood, Kumar Gala, Li Yang
Cc: Zhao Chenhui, linuxppc-dev, linux-kernel, devicetree,
linux-arm-kernel, Ran Wang
Also, unselect FSL_PMC which is for older platfroms instead.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Changes in v2:
- no change
arch/powerpc/Kconfig | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 73ce5dd..ed60c83 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -316,7 +316,7 @@ config ARCH_HIBERNATION_POSSIBLE
config ARCH_SUSPEND_POSSIBLE
def_bool y
depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
- (PPC_85xx && !PPC_E500MC) || PPC_86xx || PPC_PSERIES \
+ FSL_SOC_BOOKE || PPC_86xx || PPC_PSERIES \
|| 44x || 40x
config PPC_DCR_NATIVE
@@ -940,8 +940,6 @@ config FSL_PCI
config FSL_PMC
bool
- default y
- depends on SUSPEND && (PPC_85xx || PPC_86xx)
help
Freescale MPC85xx/MPC86xx power management controller support
(suspend/resume). For MPC83xx see platforms/83xx/suspend.c
--
1.7.1
^ permalink raw reply related
* [PATCH 2/2] powernv/npu: Prevent overwriting of pnv_npu2_init_contex() callback parameters
From: Alistair Popple @ 2018-04-11 6:38 UTC (permalink / raw)
To: linuxppc-dev, mpe; +Cc: mhairgrove, arbab, bsingharora, Alistair Popple
In-Reply-To: <20180411063855.5451-1-alistair@popple.id.au>
There is a single npu context per set of callback parameters. Callers
should be prevented from overwriting existing callback values so instead
return an error if different parameters are passed.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
arch/powerpc/include/asm/powernv.h | 2 +-
arch/powerpc/platforms/powernv/npu-dma.c | 16 +++++++++++++---
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/powernv.h b/arch/powerpc/include/asm/powernv.h
index dc5f6a5d4575..362ea12a4501 100644
--- a/arch/powerpc/include/asm/powernv.h
+++ b/arch/powerpc/include/asm/powernv.h
@@ -15,7 +15,7 @@
extern void powernv_set_nmmu_ptcr(unsigned long ptcr);
extern struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
unsigned long flags,
- struct npu_context *(*cb)(struct npu_context *, void *),
+ void (*cb)(struct npu_context *, void *),
void *priv);
extern void pnv_npu2_destroy_context(struct npu_context *context,
struct pci_dev *gpdev);
diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c
index cb77162f4e7a..193f43ea3fbc 100644
--- a/arch/powerpc/platforms/powernv/npu-dma.c
+++ b/arch/powerpc/platforms/powernv/npu-dma.c
@@ -407,7 +407,7 @@ struct npu_context {
bool nmmu_flush;
/* Callback to stop translation requests on a given GPU */
- struct npu_context *(*release_cb)(struct npu_context *, void *);
+ void (*release_cb)(struct npu_context *context, void *priv);
/*
* Private pointer passed to the above callback for usage by
@@ -705,7 +705,7 @@ static const struct mmu_notifier_ops nv_nmmu_notifier_ops = {
*/
struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
unsigned long flags,
- struct npu_context *(*cb)(struct npu_context *, void *),
+ void (*cb)(struct npu_context *, void *),
void *priv)
{
int rc;
@@ -763,8 +763,18 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
*/
spin_lock(&npu_context_lock);
npu_context = mm->context.npu_context;
- if (npu_context)
+ if (npu_context) {
+ if (npu_context->release_cb != cb ||
+ npu_context->priv != priv) {
+ spin_unlock(&npu_context_lock);
+ opal_npu_destroy_context(nphb->opal_id, mm->context.id,
+ PCI_DEVID(gpdev->bus->number,
+ gpdev->devfn));
+ return ERR_PTR(-EINVAL);
+ }
+
WARN_ON(!kref_get_unless_zero(&npu_context->kref));
+ }
spin_unlock(&npu_context_lock);
if (!npu_context) {
--
2.11.0
^ permalink raw reply related
* [PATCH 1/2] powernv/npu: Add lock to prevent race in concurrent context init/destroy
From: Alistair Popple @ 2018-04-11 6:38 UTC (permalink / raw)
To: linuxppc-dev, mpe; +Cc: mhairgrove, arbab, bsingharora, Alistair Popple
The pnv_npu2_init_context() and pnv_npu2_destroy_context() functions are
used to allocate/free contexts to allow address translation and shootdown
by the NPU on a particular GPU. Context initialisation is implicitly safe
as it is protected by the requirement mmap_sem be held in write mode,
however pnv_npu2_destroy_context() does not require mmap_sem to be held and
it is not safe to call with a concurrent initialisation for a different
GPU.
It was assumed the driver would ensure destruction was not called
concurrently with initialisation. However the driver may be simplified by
allowing concurrent initialisation and destruction for different GPUs. As
npu context creation/destruction is not a performance critical path and the
critical section is not large a single spinlock is used for simplicity.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
arch/powerpc/platforms/powernv/npu-dma.c | 51 ++++++++++++++++++++++++++------
1 file changed, 42 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c
index 1cbef1f9cd37..cb77162f4e7a 100644
--- a/arch/powerpc/platforms/powernv/npu-dma.c
+++ b/arch/powerpc/platforms/powernv/npu-dma.c
@@ -34,6 +34,12 @@
#define npu_to_phb(x) container_of(x, struct pnv_phb, npu)
/*
+ * spinlock to protect initialisation of an npu_context for a particular
+ * mm_struct.
+ */
+DEFINE_SPINLOCK(npu_context_lock);
+
+/*
* Other types of TCE cache invalidation are not functional in the
* hardware.
*/
@@ -694,7 +700,8 @@ static const struct mmu_notifier_ops nv_nmmu_notifier_ops = {
* Returns an error if there no contexts are currently available or a
* npu_context which should be passed to pnv_npu2_handle_fault().
*
- * mmap_sem must be held in write mode.
+ * mmap_sem must be held in write mode and must not be called from interrupt
+ * context.
*/
struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
unsigned long flags,
@@ -741,7 +748,9 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
/*
* Setup the NPU context table for a particular GPU. These need to be
* per-GPU as we need the tables to filter ATSDs when there are no
- * active contexts on a particular GPU.
+ * active contexts on a particular GPU. It is safe for these to be
+ * called concurrently with destroy as the OPAL call takes appropriate
+ * locks and refcounts on init/destroy.
*/
rc = opal_npu_init_context(nphb->opal_id, mm->context.id, flags,
PCI_DEVID(gpdev->bus->number, gpdev->devfn));
@@ -752,8 +761,19 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
* We store the npu pci device so we can more easily get at the
* associated npus.
*/
+ spin_lock(&npu_context_lock);
npu_context = mm->context.npu_context;
+ if (npu_context)
+ WARN_ON(!kref_get_unless_zero(&npu_context->kref));
+ spin_unlock(&npu_context_lock);
+
if (!npu_context) {
+ /*
+ * We can set up these fields without holding the
+ * npu_context_lock as the npu_context hasn't been returned to
+ * the caller meaning it can't be destroyed. Parallel allocation
+ * is protected against by mmap_sem.
+ */
rc = -ENOMEM;
npu_context = kzalloc(sizeof(struct npu_context), GFP_KERNEL);
if (npu_context) {
@@ -772,8 +792,6 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
}
mm->context.npu_context = npu_context;
- } else {
- WARN_ON(!kref_get_unless_zero(&npu_context->kref));
}
npu_context->release_cb = cb;
@@ -811,15 +829,16 @@ static void pnv_npu2_release_context(struct kref *kref)
mm_context_remove_copro(npu_context->mm);
npu_context->mm->context.npu_context = NULL;
- mmu_notifier_unregister(&npu_context->mn,
- npu_context->mm);
-
- kfree(npu_context);
}
+/*
+ * Destroy a context on the given GPU. May free the npu_context if it is no
+ * longer active on any GPUs. Must not be called from interrupt context.
+ */
void pnv_npu2_destroy_context(struct npu_context *npu_context,
struct pci_dev *gpdev)
{
+ int removed;
struct pnv_phb *nphb;
struct npu *npu;
struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
@@ -841,7 +860,21 @@ void pnv_npu2_destroy_context(struct npu_context *npu_context,
WRITE_ONCE(npu_context->npdev[npu->index][nvlink_index], NULL);
opal_npu_destroy_context(nphb->opal_id, npu_context->mm->context.id,
PCI_DEVID(gpdev->bus->number, gpdev->devfn));
- kref_put(&npu_context->kref, pnv_npu2_release_context);
+ spin_lock(&npu_context_lock);
+ removed = kref_put(&npu_context->kref, pnv_npu2_release_context);
+ spin_unlock(&npu_context_lock);
+
+ /*
+ * We need to do this outside of pnv_npu2_release_context so that it is
+ * outside the spinlock as mmu_notifier_destroy uses SRCU.
+ */
+ if (removed) {
+ mmu_notifier_unregister(&npu_context->mn,
+ npu_context->mm);
+
+ kfree(npu_context);
+ }
+
}
EXPORT_SYMBOL(pnv_npu2_destroy_context);
--
2.11.0
^ permalink raw reply related
* Re: [PATCH 1/3] powerpc/xive: Fix trying to "push" an already active pool VP
From: Benjamin Herrenschmidt @ 2018-04-11 5:20 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20180411051801.30194-1-benh@kernel.crashing.org>
On Wed, 2018-04-11 at 15:17 +1000, Benjamin Herrenschmidt wrote:
> When setting up a CPU, we "push" (activate) a pool VP for it.
>
> However it's an error to do so if it already has an active
> pool VP.
>
> This happens when doing soft CPU hotplug on powernv since we
> don't tear down the CPU on unplug. The HW flags the error which
> gets captured by the diagnostics.
>
> Fix this by making sure to "pull" out any already active pool
> first.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: stable@vger.kernel.org...
> ---
> arch/powerpc/sysdev/xive/native.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
> index d22aeb0b69e1..b48454be5b98 100644
> --- a/arch/powerpc/sysdev/xive/native.c
> +++ b/arch/powerpc/sysdev/xive/native.c
> @@ -389,6 +389,10 @@ static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
> if (xive_pool_vps == XIVE_INVALID_VP)
> return;
>
> + /* Check if pool VP already active, if it is, pull it */
> + if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP)
> + in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
> +
> /* Enable the pool VP */
> vp = xive_pool_vps + cpu;
> pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp);
^ permalink raw reply
* [PATCH 2/3] powerpc/xive: Remove now useless pr_debug statements
From: Benjamin Herrenschmidt @ 2018-04-11 5:18 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20180411051801.30194-1-benh@kernel.crashing.org>
Those overly verbose statement in the setup of the pool VP
aren't particularly useful (esp. considering we don't actually
use the pool, we configure it bcs HW requires it only). So
remove them which improves the code readability.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/sysdev/xive/native.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
index b48454be5b98..c7088a35eb89 100644
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -395,7 +395,6 @@ static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
/* Enable the pool VP */
vp = xive_pool_vps + cpu;
- pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp);
for (;;) {
rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
if (rc != OPAL_BUSY)
@@ -415,16 +414,9 @@ static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
}
vp_cam = be64_to_cpu(vp_cam_be);
- pr_debug("VP CAM = %llx\n", vp_cam);
-
/* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
- pr_debug("(Old HW value: %08x)\n",
- in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
- out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2,
- TM_QW2W2_VP | vp_cam);
- pr_debug("(New HW value: %08x)\n",
- in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
+ out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam);
}
static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
--
2.14.3
^ permalink raw reply related
* [PATCH 3/3] powerpc/xive: Remove xive_kexec_teardown_cpu()
From: Benjamin Herrenschmidt @ 2018-04-11 5:18 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20180411051801.30194-1-benh@kernel.crashing.org>
It's identical to xive_teardown_cpu() so just use the latter
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/include/asm/xive.h | 1 -
arch/powerpc/platforms/powernv/setup.c | 2 +-
arch/powerpc/platforms/pseries/kexec.c | 2 +-
arch/powerpc/sysdev/xive/common.c | 22 ----------------------
4 files changed, 2 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index 8d1a2792484f..3c704f5dd3ae 100644
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -87,7 +87,6 @@ extern int xive_smp_prepare_cpu(unsigned int cpu);
extern void xive_smp_setup_cpu(void);
extern void xive_smp_disable_cpu(void);
extern void xive_teardown_cpu(void);
-extern void xive_kexec_teardown_cpu(int secondary);
extern void xive_shutdown(void);
extern void xive_flush_interrupt(void);
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 092715b9674b..5b4b09816791 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -282,7 +282,7 @@ static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
u64 reinit_flags;
if (xive_enabled())
- xive_kexec_teardown_cpu(secondary);
+ xive_teardown_cpu();
else
xics_kexec_teardown_cpu(secondary);
diff --git a/arch/powerpc/platforms/pseries/kexec.c b/arch/powerpc/platforms/pseries/kexec.c
index eeb13429d685..9dabf019556b 100644
--- a/arch/powerpc/platforms/pseries/kexec.c
+++ b/arch/powerpc/platforms/pseries/kexec.c
@@ -53,7 +53,7 @@ void pseries_kexec_cpu_down(int crash_shutdown, int secondary)
}
if (xive_enabled())
- xive_kexec_teardown_cpu(secondary);
+ xive_teardown_cpu();
else
xics_kexec_teardown_cpu(secondary);
}
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index 40c06110821c..c8db51b60b4b 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -1408,28 +1408,6 @@ void xive_teardown_cpu(void)
xive_cleanup_cpu_queues(cpu, xc);
}
-void xive_kexec_teardown_cpu(int secondary)
-{
- struct xive_cpu *xc = __this_cpu_read(xive_cpu);
- unsigned int cpu = smp_processor_id();
-
- /* Set CPPR to 0 to disable flow of interrupts */
- xc->cppr = 0;
- out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
-
- /* Backend cleanup if any */
- if (xive_ops->teardown_cpu)
- xive_ops->teardown_cpu(cpu, xc);
-
-#ifdef CONFIG_SMP
- /* Get rid of IPI */
- xive_cleanup_cpu_ipi(cpu, xc);
-#endif
-
- /* Disable and free the queues */
- xive_cleanup_cpu_queues(cpu, xc);
-}
-
void xive_shutdown(void)
{
xive_ops->shutdown();
--
2.14.3
^ permalink raw reply related
* [PATCH 1/3] powerpc/xive: Fix trying to "push" an already active pool VP
From: Benjamin Herrenschmidt @ 2018-04-11 5:17 UTC (permalink / raw)
To: linuxppc-dev
When setting up a CPU, we "push" (activate) a pool VP for it.
However it's an error to do so if it already has an active
pool VP.
This happens when doing soft CPU hotplug on powernv since we
don't tear down the CPU on unplug. The HW flags the error which
gets captured by the diagnostics.
Fix this by making sure to "pull" out any already active pool
first.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/sysdev/xive/native.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
index d22aeb0b69e1..b48454be5b98 100644
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -389,6 +389,10 @@ static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
if (xive_pool_vps == XIVE_INVALID_VP)
return;
+ /* Check if pool VP already active, if it is, pull it */
+ if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP)
+ in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
+
/* Enable the pool VP */
vp = xive_pool_vps + cpu;
pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp);
--
2.14.3
^ permalink raw reply related
* Re: [PATCH 2/2] powerpc/mm/memtrace: Let the arch hotunplug code flush cache
From: rashmica @ 2018-04-11 4:01 UTC (permalink / raw)
To: Balbir Singh, linuxppc-dev; +Cc: mpe, rashmica.g, benh
In-Reply-To: <20180406052424.29841-2-bsingharora@gmail.com>
On 06/04/18 15:24, Balbir Singh wrote:
> Don't do this via custom code, instead now that we have support
> in the arch hotplug/hotunplug code, rely on those routines
> to do the right thing.
>
> Fixes: 9d5171a8f248 ("powerpc/powernv: Enable removal of memory for in memory tracing")
> because the older code uses ppc64_caches.l1d.size instead of
> ppc64_caches.l1d.line_size
>
> Signed-off-by: Balbir Singh <bsingharora@gmail.com>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/mm: Flush cache on memory hot(un)plug
From: rashmica @ 2018-04-11 4:00 UTC (permalink / raw)
To: Balbir Singh, linuxppc-dev; +Cc: mpe, rashmica.g, benh
In-Reply-To: <20180406052424.29841-1-bsingharora@gmail.com>
On 06/04/18 15:24, Balbir Singh wrote:
> This patch adds support for flushing potentially dirty
> cache lines when memory is hot-plugged/hot-un-plugged.
> The support is currently limited to 64 bit systems.
>
> The bug was exposed when mappings for a device were
> actually hot-unplugged and plugged in back later.
> A similar issue was observed during the development
> of memtrace, but memtrace does it's own flushing of
> region via a custom routine.
>
> These patches do a flush both on hotplug/unplug to
> clear any stale data in the cache w.r.t mappings,
> there is a small race window where a clean cache
> line may be created again just prior to tearing
> down the mapping.
>
> The patches were tested by disabling the flush
> routines in memtrace and doing I/O on the trace
> file. The system immediately checkstops (quite
> reliablly if prior to the hot-unplug of the memtrace
> region, we memset the regions we are about to
> hot unplug). After these patches no custom flushing
> is needed in the memtrace code.
>
> Signed-off-by: Balbir Singh <bsingharora@gmail.com>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
^ permalink raw reply
* [PATCH] powerpc/eeh: Fix enabling bridge MMIO windows
From: Michael Neuling @ 2018-04-11 3:37 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, benh, Pridhiviraj Paidipeddi, ruscur, sam.bobroff
On boot we save the configuration space of PCIe bridges. We do this so
when we get an EEH event and everything gets reset that we can restore
them.
Unfortunately we save this state before we've enabled the MMIO space
on the bridges. Hence if we have to reset the bridge when we come back
MMIO is not enabled and we end up taking an PE freeze when the driver
starts accessing again.
This patch forces the memory/MMIO and bus mastering on when restoring
bridges on EEH. Ideally we'd do this correctly by saving the
configuration space writes later, but that will have to come later in
a larger EEH rewrite. For now we have this simple fix.
The original bug can be triggered on a boston machine by doing:
echo 0x8000000000000000 > /sys/kernel/debug/powerpc/PCI0001/err_injct_outbound
On boston, this PHB has a PCIe switch on it. Without this patch,
you'll see two EEH events, 1 expected and 1 the failure we are fixing
here. The second EEH event causes the anything under the PHB to
disappear (i.e. the i40e eth).
With this patch, only 1 EEH event occurs and devices properly recover.
Reported-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Cc: stable@vger.kernel.org
---
arch/powerpc/kernel/eeh_pe.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index 2d4956e97a..ee5a67d57a 100644
--- a/arch/powerpc/kernel/eeh_pe.c
+++ b/arch/powerpc/kernel/eeh_pe.c
@@ -807,7 +807,8 @@ static void eeh_restore_bridge_bars(struct eeh_dev *edev)
eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
/* PCI Command: 0x4 */
- eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1]);
+ eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1] |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Check the PCIe link is ready */
eeh_bridge_check_link(edev);
--
2.14.1
^ permalink raw reply related
* Re: [RFC PATCH 4/5] KVM: PPC: Book3S HV: handle need_tlb_flush in C before low-level guest entry
From: Nicholas Piggin @ 2018-04-11 2:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: kvm-ppc, linuxppc-dev
In-Reply-To: <1523410332.11062.116.camel@au1.ibm.com>
On Wed, 11 Apr 2018 11:32:12 +1000
Benjamin Herrenschmidt <benh@au1.ibm.com> wrote:
> On Tue, 2018-04-10 at 22:48 +1000, Nicholas Piggin wrote:
> >
> > + /*
> > + * Do we need to flush the TLB for the LPAR? (see TLB comment above)
> > + * On POWER9, individual threads can come in here, but the
> > + * TLB is shared between the 4 threads in a core, hence
> > + * invalidating on one thread invalidates for all.
> > + * Thus we make all 4 threads use the same bit here.
> > + */
>
> This might be true of P9 implementation but isn't architecturally
> correct. From an ISA perspective, the threads could have dedicatd
> tagged TLB entries. Do we need to be careful here vs. backward
> compatiblity ?
I think so. I noticed that, just trying to do like for like replacement
with this patch.
Yes it should have a feature bit test for this optimization IMO. That
can be expanded if other CPUs have the same ability... Is it even
a worthwhile optimisation to do at this point, I wonder? I didn't see
it being hit a lot in traces.
> Also this won't flush ERAT entries for another thread afaik.
Yeah, I'm still not entirely clear exactly when ERATs get invalidated.
I would like to see more commentary here to show why it's okay.
>
> > + tmp = pcpu;
> > + if (cpu_has_feature(CPU_FTR_ARCH_300))
> > + tmp &= ~0x3UL;
> > + if (cpumask_test_cpu(tmp, &vc->kvm->arch.need_tlb_flush)) {
> > + if (kvm_is_radix(vc->kvm))
> > + radix__local_flush_tlb_lpid(vc->kvm->arch.lpid);
> > + else
> > + hash__local_flush_tlb_lpid(vc->kvm->arch.lpid);
> > + /* Clear the bit after the TLB flush */
> > + cpumask_clear_cpu(tmp, &vc->kvm->arch.need_tlb_flush);
> > + }
> > +
>
^ permalink raw reply
* Re: [RFC PATCH 4/5] KVM: PPC: Book3S HV: handle need_tlb_flush in C before low-level guest entry
From: Benjamin Herrenschmidt @ 2018-04-11 1:32 UTC (permalink / raw)
To: Nicholas Piggin, kvm-ppc; +Cc: linuxppc-dev
In-Reply-To: <20180410124842.30184-5-npiggin@gmail.com>
On Tue, 2018-04-10 at 22:48 +1000, Nicholas Piggin wrote:
>
> + /*
> + * Do we need to flush the TLB for the LPAR? (see TLB comment above)
> + * On POWER9, individual threads can come in here, but the
> + * TLB is shared between the 4 threads in a core, hence
> + * invalidating on one thread invalidates for all.
> + * Thus we make all 4 threads use the same bit here.
> + */
This might be true of P9 implementation but isn't architecturally
correct. From an ISA perspective, the threads could have dedicatd
tagged TLB entries. Do we need to be careful here vs. backward
compatiblity ?
Also this won't flush ERAT entries for another thread afaik.
> + tmp = pcpu;
> + if (cpu_has_feature(CPU_FTR_ARCH_300))
> + tmp &= ~0x3UL;
> + if (cpumask_test_cpu(tmp, &vc->kvm->arch.need_tlb_flush)) {
> + if (kvm_is_radix(vc->kvm))
> + radix__local_flush_tlb_lpid(vc->kvm->arch.lpid);
> + else
> + hash__local_flush_tlb_lpid(vc->kvm->arch.lpid);
> + /* Clear the bit after the TLB flush */
> + cpumask_clear_cpu(tmp, &vc->kvm->arch.need_tlb_flush);
> + }
> +
^ permalink raw reply
* [PATCH] ibmvnic: Define vnic_login_client_data name field as unsized array
From: Kees Cook @ 2018-04-10 22:26 UTC (permalink / raw)
To: Thomas Falcon
Cc: John Allen, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman, netdev, linuxppc-dev, linux-kernel,
Daniel Micay
The "name" field of struct vnic_login_client_data is a char array of
undefined length. This should be written as "char name[]" so the compiler
can make better decisions about the field (for example, not assuming
it's a single character). This was noticed while trying to tighten the
CONFIG_FORTIFY_SOURCE checking.
Signed-off-by: Kees Cook <keescook@chromium.org>
---
drivers/net/ethernet/ibm/ibmvnic.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
index aad5658d79d5..35fbb41cd2d4 100644
--- a/drivers/net/ethernet/ibm/ibmvnic.c
+++ b/drivers/net/ethernet/ibm/ibmvnic.c
@@ -3170,7 +3170,7 @@ static int send_version_xchg(struct ibmvnic_adapter *adapter)
struct vnic_login_client_data {
u8 type;
__be16 len;
- char name;
+ char name[];
} __packed;
static int vnic_client_data_len(struct ibmvnic_adapter *adapter)
@@ -3199,21 +3199,21 @@ static void vnic_add_client_data(struct ibmvnic_adapter *adapter,
vlcd->type = 1;
len = strlen(os_name) + 1;
vlcd->len = cpu_to_be16(len);
- strncpy(&vlcd->name, os_name, len);
- vlcd = (struct vnic_login_client_data *)((char *)&vlcd->name + len);
+ strncpy(vlcd->name, os_name, len);
+ vlcd = (struct vnic_login_client_data *)(vlcd->name + len);
/* Type 2 - LPAR name */
vlcd->type = 2;
len = strlen(utsname()->nodename) + 1;
vlcd->len = cpu_to_be16(len);
- strncpy(&vlcd->name, utsname()->nodename, len);
- vlcd = (struct vnic_login_client_data *)((char *)&vlcd->name + len);
+ strncpy(vlcd->name, utsname()->nodename, len);
+ vlcd = (struct vnic_login_client_data *)(vlcd->name + len);
/* Type 3 - device name */
vlcd->type = 3;
len = strlen(adapter->netdev->name) + 1;
vlcd->len = cpu_to_be16(len);
- strncpy(&vlcd->name, adapter->netdev->name, len);
+ strncpy(vlcd->name, adapter->netdev->name, len);
}
static int send_login(struct ibmvnic_adapter *adapter)
--
2.7.4
--
Kees Cook
Pixel Security
^ permalink raw reply related
* Re: [PATCH v2 1/2] mm: introduce ARCH_HAS_PTE_SPECIAL
From: David Rientjes @ 2018-04-10 20:51 UTC (permalink / raw)
To: Laurent Dufour
Cc: Matthew Wilcox, linux-kernel, linux-mm, linuxppc-dev, x86,
linux-doc, linux-snps-arc, linux-arm-kernel, linux-riscv,
linux-s390, linux-sh, sparclinux, Jerome Glisse, mhocko,
aneesh.kumar, akpm, mpe, benh, paulus, Jonathan Corbet,
Catalin Marinas, Will Deacon, Yoshinori Sato, Rich Felker,
David S . Miller, Thomas Gleixner, Ingo Molnar, Vineet Gupta,
Palmer Dabbelt, Albert Ou, Martin Schwidefsky, Heiko Carstens
In-Reply-To: <a732ef2b-445f-9ad8-014b-247c8c5d500b@linux.vnet.ibm.com>
On Tue, 10 Apr 2018, Laurent Dufour wrote:
> > On Tue, Apr 10, 2018 at 05:25:50PM +0200, Laurent Dufour wrote:
> >> arch/powerpc/include/asm/pte-common.h | 3 ---
> >> arch/riscv/Kconfig | 1 +
> >> arch/s390/Kconfig | 1 +
> >
> > You forgot to delete __HAVE_ARCH_PTE_SPECIAL from
> > arch/riscv/include/asm/pgtable-bits.h
>
> Damned !
> Thanks for catching it.
>
Squashing the two patches together at least allowed it to be caught
easily. After it's fixed, feel free to add
Acked-by: David Rientjes <rientjes@google.com>
Thanks for doing this!
^ permalink raw reply
* Re: [PATCH v2 1/2] mm: introduce ARCH_HAS_PTE_SPECIAL
From: Palmer Dabbelt @ 2018-04-10 20:44 UTC (permalink / raw)
To: willy
Cc: ldufour, linux-kernel, linux-mm, linuxppc-dev, x86, linux-doc,
linux-snps-arc, linux-arm-kernel, linux-riscv, linux-s390,
linux-sh, sparclinux, jglisse, mhocko, aneesh.kumar, akpm, mpe,
benh, paulus, corbet, catalin.marinas, Will Deacon, ysato, dalias,
davem, tglx, mingo, vgupta, albert, schwidefsky, heiko.carstens,
rientjes
In-Reply-To: <20180410160932.GB3614@bombadil.infradead.org>
On Tue, 10 Apr 2018 09:09:32 PDT (-0700), willy@infradead.org wrote:
> On Tue, Apr 10, 2018 at 05:25:50PM +0200, Laurent Dufour wrote:
>> arch/powerpc/include/asm/pte-common.h | 3 ---
>> arch/riscv/Kconfig | 1 +
>> arch/s390/Kconfig | 1 +
>
> You forgot to delete __HAVE_ARCH_PTE_SPECIAL from
> arch/riscv/include/asm/pgtable-bits.h
Thanks -- I was looking for that but couldn't find it and assumed I'd just
misunderstood something.
^ permalink raw reply
* Re: [PATCH, RESEND, pci, v2] pci: Delete PCI disabling informational messages
From: Desnes A. Nunes do Rosario @ 2018-04-10 19:58 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: linux-kernel, linux-pci, linuxppc-dev, bhelgaas
In-Reply-To: <20180410195556.GF54986@bhelgaas-glaptop.roam.corp.google.com>
Bjorn,
On 04/10/2018 04:55 PM, Bjorn Helgaas wrote:
> On Tue, Apr 10, 2018 at 02:36:31PM -0500, Bjorn Helgaas wrote:
>> On Wed, Apr 04, 2018 at 12:10:35PM -0300, Desnes A. Nunes do Rosario wrote:
>>> The disabling informational messages on the PCI subsystem should be deleted
>>> since they do not represent any real value for the system logs.
>>>
>>> These messages are either not presented, or presented for all PCI devices
>>> (e.g., powerpc now realigns all PCI devices to its page size). Thus, they
>>> are flooding system logs and can be interpreted as a false positive for
>>> total PCI failure on the system.
>>>
>>> [root@system user]# dmesg | grep -i disabling
>>> [ 0.692270] pci 0000:00:00.0: Disabling memory decoding and releasing memory resources
>>> [ 0.692324] pci 0000:00:00.0: disabling bridge mem windows
>>> [ 0.729134] pci 0001:00:00.0: Disabling memory decoding and releasing memory resources
>>> [ 0.737352] pci 0001:00:00.0: disabling bridge mem windows
>>> [ 0.776295] pci 0002:00:00.0: Disabling memory decoding and releasing memory resources
>>> [ 0.784509] pci 0002:00:00.0: disabling bridge mem windows
>>> ... and goes on for all PCI devices on the system ...
>>>
>>> Fixes: 38274637699 ("powerpc/powernv: Override pcibios_default_alignment() to force PCI devices to be page aligned")
>>> Signed-off-by: Desnes A. Nunes do Rosario <desnesn@linux.vnet.ibm.com>
>>
>> Applied to pci/resource for v4.18, thanks!
>>
>> I should have gotten this in for v4.17, but I didn't; sorry about that.
>
> This is trivial and I'm planning to squeeze a few more things into v4.17,
> so I moved this to my "for-linus" branch for v4.17.
No need for apologies.
On the contrary, thank you very much for your review and branch change.
>
>>> ---
>>> drivers/pci/pci.c | 1 -
>>> drivers/pci/setup-res.c | 2 --
>>> 2 files changed, 3 deletions(-)
>>>
>>> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
>>> index 8c71d1a66cdd..1563ce1ee091 100644
>>> --- a/drivers/pci/pci.c
>>> +++ b/drivers/pci/pci.c
>>> @@ -5505,7 +5505,6 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev)
>>> return;
>>> }
>>>
>>> - pci_info(dev, "Disabling memory decoding and releasing memory resources\n");
>>> pci_read_config_word(dev, PCI_COMMAND, &command);
>>> command &= ~PCI_COMMAND_MEMORY;
>>> pci_write_config_word(dev, PCI_COMMAND, command);
>>> diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
>>> index 369d48d6c6f1..6bd35e8e7cde 100644
>>> --- a/drivers/pci/setup-res.c
>>> +++ b/drivers/pci/setup-res.c
>>> @@ -172,8 +172,6 @@ EXPORT_SYMBOL(pci_claim_resource);
>>>
>>> void pci_disable_bridge_window(struct pci_dev *dev)
>>> {
>>> - pci_info(dev, "disabling bridge mem windows\n");
>>> -
>>> /* MMIO Base/Limit */
>>> pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
>>>
>>> --
>>> 2.14.3
>>>
>
--
Desnes A. Nunes do Rosario
--------------------------
Linux Developer - IBM
^ permalink raw reply
* Re: [PATCH 5/5] powerpc:dts:pm: add power management node
From: Li Yang @ 2018-04-10 19:57 UTC (permalink / raw)
To: Ran Wang
Cc: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Rob Herring, Mark Rutland, Scott Wood, Kumar Gala, Zhao Chenhui,
linuxppc-dev, lkml,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel
In-Reply-To: <20180329013143.22527-5-ran.wang_1@nxp.com>
On Wed, Mar 28, 2018 at 8:31 PM, Ran Wang <ran.wang_1@nxp.com> wrote:
> Enable Power Management feature on device tree, including MPC8536,
> MPC8544, MPC8548, MPC8572, P1010, P1020, P1021, P1022, P2020, P2041,
> P3041, T104X, T1024.
There are no device tree bindings documented for the properties and
compatible strings used in the patch. Please update the binding
documents first before adding them into device tree.
>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> ---
> arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi | 14 ++++++-
> arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi | 2 +
> arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi | 2 +
> arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi | 2 +
> arch/powerpc/boot/dts/fsl/p1010si-post.dtsi | 8 ++++
> arch/powerpc/boot/dts/fsl/p1020si-post.dtsi | 5 +++
> arch/powerpc/boot/dts/fsl/p1021si-post.dtsi | 5 +++
> arch/powerpc/boot/dts/fsl/p1022si-post.dtsi | 9 +++--
> arch/powerpc/boot/dts/fsl/p2020si-post.dtsi | 14 +++++++
> arch/powerpc/boot/dts/fsl/pq3-power.dtsi | 48 +++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/t1024rdb.dts | 2 +-
> arch/powerpc/boot/dts/fsl/t1040rdb.dts | 2 +-
> arch/powerpc/boot/dts/fsl/t1042rdb.dts | 2 +-
> arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts | 2 +-
> 14 files changed, 108 insertions(+), 9 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/fsl/pq3-power.dtsi
>
> diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
> index 4193570..fba40a1 100644
> --- a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
> @@ -199,6 +199,10 @@
>
> /include/ "pq3-dma-0.dtsi"
> /include/ "pq3-etsec1-0.dtsi"
> + enet0: ethernet@24000 {
> + fsl,wake-on-filer;
> + fsl,pmc-handle = <&etsec1_clk>;
> + };
> /include/ "pq3-etsec1-timer-0.dtsi"
>
> usb@22000 {
> @@ -222,9 +226,10 @@
> };
>
> /include/ "pq3-etsec1-2.dtsi"
> -
> - ethernet@26000 {
> + enet2: ethernet@26000 {
> cell-index = <1>;
> + fsl,wake-on-filer;
> + fsl,pmc-handle = <&etsec3_clk>;
> };
>
> usb@2b000 {
> @@ -249,4 +254,9 @@
> reg = <0xe0000 0x1000>;
> fsl,has-rstcr;
> };
> +
> +/include/ "pq3-power.dtsi"
> + power@e0070 {
> + compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
> + };
> };
> diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
> index b68eb11..ea7416a 100644
> --- a/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
> @@ -188,4 +188,6 @@
> reg = <0xe0000 0x1000>;
> fsl,has-rstcr;
> };
> +
> +/include/ "pq3-power.dtsi"
> };
> diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
> index 579d76c..dddb737 100644
> --- a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
> @@ -156,4 +156,6 @@
> reg = <0xe0000 0x1000>;
> fsl,has-rstcr;
> };
> +
> +/include/ "pq3-power.dtsi"
> };
> diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
> index 49294cf..40a6cff 100644
> --- a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
> @@ -193,4 +193,6 @@
> reg = <0xe0000 0x1000>;
> fsl,has-rstcr;
> };
> +
> +/include/ "pq3-power.dtsi"
> };
> diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
> index 1b4aafc..47b62a8 100644
> --- a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
> @@ -173,6 +173,8 @@
>
> /include/ "pq3-etsec2-0.dtsi"
> enet0: ethernet@b0000 {
> + fsl,pmc-handle = <&etsec1_clk>;
> +
> queue-group@b0000 {
> fsl,rx-bit-map = <0xff>;
> fsl,tx-bit-map = <0xff>;
> @@ -181,6 +183,8 @@
>
> /include/ "pq3-etsec2-1.dtsi"
> enet1: ethernet@b1000 {
> + fsl,pmc-handle = <&etsec2_clk>;
> +
> queue-group@b1000 {
> fsl,rx-bit-map = <0xff>;
> fsl,tx-bit-map = <0xff>;
> @@ -189,6 +193,8 @@
>
> /include/ "pq3-etsec2-2.dtsi"
> enet2: ethernet@b2000 {
> + fsl,pmc-handle = <&etsec3_clk>;
> +
> queue-group@b2000 {
> fsl,rx-bit-map = <0xff>;
> fsl,tx-bit-map = <0xff>;
> @@ -201,4 +207,6 @@
> reg = <0xe0000 0x1000>;
> fsl,has-rstcr;
> };
> +
> +/include/ "pq3-power.dtsi"
> };
> diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
> index 642dc3a..cc4c746 100644
> --- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
> @@ -163,14 +163,17 @@
>
> /include/ "pq3-etsec2-0.dtsi"
> enet0: enet0_grp2: ethernet@b0000 {
> + fsl,pmc-handle = <&etsec1_clk>;
> };
>
> /include/ "pq3-etsec2-1.dtsi"
> enet1: enet1_grp2: ethernet@b1000 {
> + fsl,pmc-handle = <&etsec2_clk>;
> };
>
> /include/ "pq3-etsec2-2.dtsi"
> enet2: enet2_grp2: ethernet@b2000 {
> + fsl,pmc-handle = <&etsec3_clk>;
> };
>
> global-utilities@e0000 {
> @@ -178,6 +181,8 @@
> reg = <0xe0000 0x1000>;
> fsl,has-rstcr;
> };
> +
> +/include/ "pq3-power.dtsi"
> };
>
> /include/ "pq3-etsec2-grp2-0.dtsi"
> diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
> index 407cb5f..378195d 100644
> --- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
> @@ -159,14 +159,17 @@
>
> /include/ "pq3-etsec2-0.dtsi"
> enet0: enet0_grp2: ethernet@b0000 {
> + fsl,pmc-handle = <&etsec1_clk>;
> };
>
> /include/ "pq3-etsec2-1.dtsi"
> enet1: enet1_grp2: ethernet@b1000 {
> + fsl,pmc-handle = <&etsec2_clk>;
> };
>
> /include/ "pq3-etsec2-2.dtsi"
> enet2: enet2_grp2: ethernet@b2000 {
> + fsl,pmc-handle = <&etsec3_clk>;
> };
>
> global-utilities@e0000 {
> @@ -174,6 +177,8 @@
> reg = <0xe0000 0x1000>;
> fsl,has-rstcr;
> };
> +
> +/include/ "pq3-power.dtsi"
> };
>
> &qe {
> diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
> index 5f51b7b..6ac21e8 100644
> --- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
> @@ -225,11 +225,13 @@
> /include/ "pq3-etsec2-0.dtsi"
> enet0: enet0_grp2: ethernet@b0000 {
> fsl,wake-on-filer;
> + fsl,pmc-handle = <&etsec1_clk>;
> };
>
> /include/ "pq3-etsec2-1.dtsi"
> enet1: enet1_grp2: ethernet@b1000 {
> fsl,wake-on-filer;
> + fsl,pmc-handle = <&etsec2_clk>;
> };
>
> global-utilities@e0000 {
> @@ -238,9 +240,10 @@
> fsl,has-rstcr;
> };
>
> - power@e0070{
> - compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
> - reg = <0xe0070 0x20>;
> +/include/ "pq3-power.dtsi"
> + power@e0070 {
> + compatible = "fsl,p1022-pmc", "fsl,mpc8536-pmc",
> + "fsl,mpc8548-pmc";
> };
>
> };
> diff --git a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
> index 884e01b..2c4787c 100644
> --- a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
> @@ -175,6 +175,10 @@
> compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
> };
> /include/ "pq3-etsec1-0.dtsi"
> + enet0: ethernet@24000 {
> + fsl,pmc-handle = <&etsec1_clk>;
> +
> + };
> /include/ "pq3-etsec1-timer-0.dtsi"
>
> ptp_clock@24e00 {
> @@ -183,7 +187,15 @@
>
>
> /include/ "pq3-etsec1-1.dtsi"
> + enet1: ethernet@25000 {
> + fsl,pmc-handle = <&etsec2_clk>;
> + };
> +
> /include/ "pq3-etsec1-2.dtsi"
> + enet2: ethernet@26000 {
> + fsl,pmc-handle = <&etsec3_clk>;
> + };
> +
> /include/ "pq3-esdhc-0.dtsi"
> sdhc@2e000 {
> compatible = "fsl,p2020-esdhc", "fsl,esdhc";
> @@ -198,4 +210,6 @@
> reg = <0xe0000 0x1000>;
> fsl,has-rstcr;
> };
> +
> +/include/ "pq3-power.dtsi"
> };
> diff --git a/arch/powerpc/boot/dts/fsl/pq3-power.dtsi b/arch/powerpc/boot/dts/fsl/pq3-power.dtsi
> new file mode 100644
> index 0000000..5a760b3
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/pq3-power.dtsi
> @@ -0,0 +1,48 @@
> +/*
> + * PQ3 Power Management device tree stub
> + *
> + * Copyright 2012-2013 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are met:
> + * * Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * * Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in the
> + * documentation and/or other materials provided with the distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote products
> + * derived from this software without specific prior written permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of the
> + * GNU General Public License ("GPL") as published by the Free Software
> + * Foundation, either version 2 of that License or (at your option) any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +power@e0070 {
> + compatible = "fsl,mpc8548-pmc";
> + reg = <0xe0070 0x20>;
> +
> + etsec1_clk: soc-clk@24 {
> + fsl,pmcdr-mask = <0x00000080>;
> + };
> + etsec2_clk: soc-clk@25 {
> + fsl,pmcdr-mask = <0x00000040>;
> + };
> + etsec3_clk: soc-clk@26 {
> + fsl,pmcdr-mask = <0x00000020>;
> + };
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/t1024rdb.dts b/arch/powerpc/boot/dts/fsl/t1024rdb.dts
> index 73a6453..95fc694 100644
> --- a/arch/powerpc/boot/dts/fsl/t1024rdb.dts
> +++ b/arch/powerpc/boot/dts/fsl/t1024rdb.dts
> @@ -91,7 +91,7 @@
> board-control@2,0 {
> #address-cells = <1>;
> #size-cells = <1>;
> - compatible = "fsl,t1024-cpld";
> + compatible = "fsl,t1024-cpld", "fsl,deepsleep-cpld";
> reg = <3 0 0x300>;
> ranges = <0 3 0 0x300>;
> bank-width = <1>;
> diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
> index 65ff34c..825665c 100644
> --- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
> +++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
> @@ -70,7 +70,7 @@
>
> ifc: localbus@ffe124000 {
> cpld@3,0 {
> - compatible = "fsl,t1040rdb-cpld";
> + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld";
> };
> };
> };
> diff --git a/arch/powerpc/boot/dts/fsl/t1042rdb.dts b/arch/powerpc/boot/dts/fsl/t1042rdb.dts
> index 3ebb712..0997643 100644
> --- a/arch/powerpc/boot/dts/fsl/t1042rdb.dts
> +++ b/arch/powerpc/boot/dts/fsl/t1042rdb.dts
> @@ -68,7 +68,7 @@
>
> ifc: localbus@ffe124000 {
> cpld@3,0 {
> - compatible = "fsl,t1042rdb-cpld";
> + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld";
> };
> };
> };
> diff --git a/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts b/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts
> index 8ec3ff4..b10cab1 100644
> --- a/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts
> +++ b/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts
> @@ -41,7 +41,7 @@
>
> ifc: localbus@ffe124000 {
> cpld@3,0 {
> - compatible = "fsl,t1042rdb_pi-cpld";
> + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld";
> };
> };
>
> --
> 1.7.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH, RESEND, pci, v2] pci: Delete PCI disabling informational messages
From: Bjorn Helgaas @ 2018-04-10 19:55 UTC (permalink / raw)
To: Desnes A. Nunes do Rosario
Cc: linux-kernel, linux-pci, linuxppc-dev, bhelgaas
In-Reply-To: <20180410193631.GC54986@bhelgaas-glaptop.roam.corp.google.com>
On Tue, Apr 10, 2018 at 02:36:31PM -0500, Bjorn Helgaas wrote:
> On Wed, Apr 04, 2018 at 12:10:35PM -0300, Desnes A. Nunes do Rosario wrote:
> > The disabling informational messages on the PCI subsystem should be deleted
> > since they do not represent any real value for the system logs.
> >
> > These messages are either not presented, or presented for all PCI devices
> > (e.g., powerpc now realigns all PCI devices to its page size). Thus, they
> > are flooding system logs and can be interpreted as a false positive for
> > total PCI failure on the system.
> >
> > [root@system user]# dmesg | grep -i disabling
> > [ 0.692270] pci 0000:00:00.0: Disabling memory decoding and releasing memory resources
> > [ 0.692324] pci 0000:00:00.0: disabling bridge mem windows
> > [ 0.729134] pci 0001:00:00.0: Disabling memory decoding and releasing memory resources
> > [ 0.737352] pci 0001:00:00.0: disabling bridge mem windows
> > [ 0.776295] pci 0002:00:00.0: Disabling memory decoding and releasing memory resources
> > [ 0.784509] pci 0002:00:00.0: disabling bridge mem windows
> > ... and goes on for all PCI devices on the system ...
> >
> > Fixes: 38274637699 ("powerpc/powernv: Override pcibios_default_alignment() to force PCI devices to be page aligned")
> > Signed-off-by: Desnes A. Nunes do Rosario <desnesn@linux.vnet.ibm.com>
>
> Applied to pci/resource for v4.18, thanks!
>
> I should have gotten this in for v4.17, but I didn't; sorry about that.
This is trivial and I'm planning to squeeze a few more things into v4.17,
so I moved this to my "for-linus" branch for v4.17.
> > ---
> > drivers/pci/pci.c | 1 -
> > drivers/pci/setup-res.c | 2 --
> > 2 files changed, 3 deletions(-)
> >
> > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> > index 8c71d1a66cdd..1563ce1ee091 100644
> > --- a/drivers/pci/pci.c
> > +++ b/drivers/pci/pci.c
> > @@ -5505,7 +5505,6 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev)
> > return;
> > }
> >
> > - pci_info(dev, "Disabling memory decoding and releasing memory resources\n");
> > pci_read_config_word(dev, PCI_COMMAND, &command);
> > command &= ~PCI_COMMAND_MEMORY;
> > pci_write_config_word(dev, PCI_COMMAND, command);
> > diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
> > index 369d48d6c6f1..6bd35e8e7cde 100644
> > --- a/drivers/pci/setup-res.c
> > +++ b/drivers/pci/setup-res.c
> > @@ -172,8 +172,6 @@ EXPORT_SYMBOL(pci_claim_resource);
> >
> > void pci_disable_bridge_window(struct pci_dev *dev)
> > {
> > - pci_info(dev, "disabling bridge mem windows\n");
> > -
> > /* MMIO Base/Limit */
> > pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
> >
> > --
> > 2.14.3
> >
^ permalink raw reply
* Re: [PATCH, RESEND, pci, v2] pci: Delete PCI disabling informational messages
From: Bjorn Helgaas @ 2018-04-10 19:36 UTC (permalink / raw)
To: Desnes A. Nunes do Rosario
Cc: linux-kernel, linux-pci, linuxppc-dev, bhelgaas
In-Reply-To: <20180404151035.12140-1-desnesn@linux.vnet.ibm.com>
On Wed, Apr 04, 2018 at 12:10:35PM -0300, Desnes A. Nunes do Rosario wrote:
> The disabling informational messages on the PCI subsystem should be deleted
> since they do not represent any real value for the system logs.
>
> These messages are either not presented, or presented for all PCI devices
> (e.g., powerpc now realigns all PCI devices to its page size). Thus, they
> are flooding system logs and can be interpreted as a false positive for
> total PCI failure on the system.
>
> [root@system user]# dmesg | grep -i disabling
> [ 0.692270] pci 0000:00:00.0: Disabling memory decoding and releasing memory resources
> [ 0.692324] pci 0000:00:00.0: disabling bridge mem windows
> [ 0.729134] pci 0001:00:00.0: Disabling memory decoding and releasing memory resources
> [ 0.737352] pci 0001:00:00.0: disabling bridge mem windows
> [ 0.776295] pci 0002:00:00.0: Disabling memory decoding and releasing memory resources
> [ 0.784509] pci 0002:00:00.0: disabling bridge mem windows
> ... and goes on for all PCI devices on the system ...
>
> Fixes: 38274637699 ("powerpc/powernv: Override pcibios_default_alignment() to force PCI devices to be page aligned")
> Signed-off-by: Desnes A. Nunes do Rosario <desnesn@linux.vnet.ibm.com>
Applied to pci/resource for v4.18, thanks!
I should have gotten this in for v4.17, but I didn't; sorry about that.
> ---
> drivers/pci/pci.c | 1 -
> drivers/pci/setup-res.c | 2 --
> 2 files changed, 3 deletions(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 8c71d1a66cdd..1563ce1ee091 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -5505,7 +5505,6 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev)
> return;
> }
>
> - pci_info(dev, "Disabling memory decoding and releasing memory resources\n");
> pci_read_config_word(dev, PCI_COMMAND, &command);
> command &= ~PCI_COMMAND_MEMORY;
> pci_write_config_word(dev, PCI_COMMAND, command);
> diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
> index 369d48d6c6f1..6bd35e8e7cde 100644
> --- a/drivers/pci/setup-res.c
> +++ b/drivers/pci/setup-res.c
> @@ -172,8 +172,6 @@ EXPORT_SYMBOL(pci_claim_resource);
>
> void pci_disable_bridge_window(struct pci_dev *dev)
> {
> - pci_info(dev, "disabling bridge mem windows\n");
> -
> /* MMIO Base/Limit */
> pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
>
> --
> 2.14.3
>
^ permalink raw reply
* Re: [PATCH v3] powerpc/64: Fix section mismatch warnings for early boot symbols
From: Mauricio Faria de Oliveira @ 2018-04-10 19:18 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linux-kernel, jeyu, jeyu, akpm, npiggin, linuxppc-dev
In-Reply-To: <87lgdvbwp8.fsf@concordia.ellerman.id.au>
On 04/09/2018 11:51 PM, Michael Ellerman wrote:
> Thanks for picking this one up.
>
> I hate to be a pain ... but before we merge this and proliferate these
> names, I'd like to change the names of some of these early asm
> functions. They're terribly named due to historical reasons.
Indeed :) No worries.
> I haven't actually thought of good names yet though:)
>
> I'll try and come up with some and post a patch doing the renames.
Alright. Could you please copy me on that, and I can post an update.
cheers,
Mauricio
^ permalink raw reply
* Re: [PATCH v2 2/2] mm: remove odd HAVE_PTE_SPECIAL
From: Laurent Dufour @ 2018-04-10 16:44 UTC (permalink / raw)
To: Robin Murphy, linux-kernel, linux-mm, linuxppc-dev, x86,
linux-doc, linux-snps-arc, linux-arm-kernel, linux-riscv,
linux-s390, linux-sh, sparclinux, Jerome Glisse, mhocko,
aneesh.kumar, akpm, mpe, benh, paulus, Jonathan Corbet,
Catalin Marinas, Will Deacon, Yoshinori Sato, Rich Felker,
David S . Miller, Thomas Gleixner, Ingo Molnar, Vineet Gupta,
Palmer Dabbelt, Albert Ou, Martin Schwidefsky, Heiko Carstens,
David Rientjes
In-Reply-To: <3f20ac8b-20b8-f052-bc44-dcc0316354ca@arm.com>
On 10/04/2018 17:58, Robin Murphy wrote:
> On 10/04/18 16:25, Laurent Dufour wrote:
>> Remove the additional define HAVE_PTE_SPECIAL and rely directly on
>> CONFIG_ARCH_HAS_PTE_SPECIAL.
>>
>> There is no functional change introduced by this patch
>>
>> Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com>
>> ---
>> mm/memory.c | 23 ++++++++++-------------
>> 1 file changed, 10 insertions(+), 13 deletions(-)
>>
>> diff --git a/mm/memory.c b/mm/memory.c
>> index 96910c625daa..53b6344a90d2 100644
>> --- a/mm/memory.c
>> +++ b/mm/memory.c
>> @@ -817,19 +817,13 @@ static void print_bad_pte(struct vm_area_struct *vma,
>> unsigned long addr,
>> * PFNMAP mappings in order to support COWable mappings.
>> *
>> */
>> -#ifdef CONFIG_ARCH_HAS_PTE_SPECIAL
>> -# define HAVE_PTE_SPECIAL 1
>> -#else
>> -# define HAVE_PTE_SPECIAL 0
>> -#endif
>> struct page *_vm_normal_page(struct vm_area_struct *vma, unsigned long addr,
>> pte_t pte, bool with_public_device)
>> {
>> unsigned long pfn = pte_pfn(pte);
>> - if (HAVE_PTE_SPECIAL) {
>> - if (likely(!pte_special(pte)))
>> - goto check_pfn;
>> +#ifdef CONFIG_ARCH_HAS_PTE_SPECIAL
>
> Nit: Couldn't you use IS_ENABLED(CONFIG_ARCH_HAS_PTE_SPECIAL) within the
> existing code structure to avoid having to add these #ifdefs?
I agree, that would be better. I didn't thought about this option..
Thanks for reporting this.
^ permalink raw reply
* Re: [PATCH v2 1/2] mm: introduce ARCH_HAS_PTE_SPECIAL
From: Laurent Dufour @ 2018-04-10 16:42 UTC (permalink / raw)
To: Matthew Wilcox
Cc: linux-kernel, linux-mm, linuxppc-dev, x86, linux-doc,
linux-snps-arc, linux-arm-kernel, linux-riscv, linux-s390,
linux-sh, sparclinux, Jerome Glisse, mhocko, aneesh.kumar, akpm,
mpe, benh, paulus, Jonathan Corbet, Catalin Marinas, Will Deacon,
Yoshinori Sato, Rich Felker, David S . Miller, Thomas Gleixner,
Ingo Molnar, Vineet Gupta, Palmer Dabbelt, Albert Ou,
Martin Schwidefsky, Heiko Carstens, David Rientjes
In-Reply-To: <20180410160932.GB3614@bombadil.infradead.org>
On 10/04/2018 18:09, Matthew Wilcox wrote:
> On Tue, Apr 10, 2018 at 05:25:50PM +0200, Laurent Dufour wrote:
>> arch/powerpc/include/asm/pte-common.h | 3 ---
>> arch/riscv/Kconfig | 1 +
>> arch/s390/Kconfig | 1 +
>
> You forgot to delete __HAVE_ARCH_PTE_SPECIAL from
> arch/riscv/include/asm/pgtable-bits.h
Damned !
Thanks for catching it.
^ permalink raw reply
* Re: [PATCH v9 16/24] mm: Introduce __page_add_new_anon_rmap()
From: Laurent Dufour @ 2018-04-10 16:30 UTC (permalink / raw)
To: David Rientjes
Cc: paulmck, peterz, akpm, kirill, ak, mhocko, dave, jack,
Matthew Wilcox, benh, mpe, paulus, Thomas Gleixner, Ingo Molnar,
hpa, Will Deacon, Sergey Senozhatsky, Andrea Arcangeli,
Alexei Starovoitov, kemi.wang, sergey.senozhatsky.work,
Daniel Jordan, linux-kernel, linux-mm, haren, khandual, npiggin,
bsingharora, Tim Chen, linuxppc-dev, x86
In-Reply-To: <alpine.DEB.2.20.1804021655100.253461@chino.kir.corp.google.com>
On 03/04/2018 01:57, David Rientjes wrote:
> On Tue, 13 Mar 2018, Laurent Dufour wrote:
>
>> When dealing with speculative page fault handler, we may race with VMA
>> being split or merged. In this case the vma->vm_start and vm->vm_end
>> fields may not match the address the page fault is occurring.
>>
>> This can only happens when the VMA is split but in that case, the
>> anon_vma pointer of the new VMA will be the same as the original one,
>> because in __split_vma the new->anon_vma is set to src->anon_vma when
>> *new = *vma.
>>
>> So even if the VMA boundaries are not correct, the anon_vma pointer is
>> still valid.
>>
>> If the VMA has been merged, then the VMA in which it has been merged
>> must have the same anon_vma pointer otherwise the merge can't be done.
>>
>> So in all the case we know that the anon_vma is valid, since we have
>> checked before starting the speculative page fault that the anon_vma
>> pointer is valid for this VMA and since there is an anon_vma this
>> means that at one time a page has been backed and that before the VMA
>> is cleaned, the page table lock would have to be grab to clean the
>> PTE, and the anon_vma field is checked once the PTE is locked.
>>
>> This patch introduce a new __page_add_new_anon_rmap() service which
>> doesn't check for the VMA boundaries, and create a new inline one
>> which do the check.
>>
>> When called from a page fault handler, if this is not a speculative one,
>> there is a guarantee that vm_start and vm_end match the faulting address,
>> so this check is useless. In the context of the speculative page fault
>> handler, this check may be wrong but anon_vma is still valid as explained
>> above.
>>
>> Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com>
>
> I'm indifferent on this: it could be argued both sides that the new
> function and its variant for a simple VM_BUG_ON() isn't worth it and it
> would should rather be done in the callers of page_add_new_anon_rmap().
> It feels like it would be better left to the caller and add a comment to
> page_add_anon_rmap() itself in mm/rmap.c.
Well there are 11 calls to page_add_new_anon_rmap() which will need to be
impacted and future ones too.
By introducing __page_add_new_anon_rmap() my goal was to make clear that this
call is *special* and that calling it is not the usual way. This also implies
that most of the time the check is done (when build with the right config) and
that we will not miss some.
^ permalink raw reply
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