* Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers
From: Haren Myneni @ 2018-06-04 4:52 UTC (permalink / raw)
To: Stewart Smith; +Cc: linuxppc-dev, herbert, linux-crypto
In-Reply-To: <878t7v2nxt.fsf@linux.vnet.ibm.com>
On 06/03/2018 09:08 PM, Stewart Smith wrote:
> Haren Myneni <haren@linux.vnet.ibm.com> writes:
>> On 06/03/2018 05:41 PM, Stewart Smith wrote:
>>> Haren Myneni <haren@linux.vnet.ibm.com> writes:
>>>> On 06/01/2018 12:41 AM, Stewart Smith wrote:
>>>>> Haren Myneni <haren@linux.vnet.ibm.com> writes:
>>>>>> NX increments readOffset by FIFO size in receive FIFO control register
>>>>>> when CRB is read. But the index in RxFIFO has to match with the
>>>>>> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
>>>>>> may be processing incorrect CRBs and can cause CRB timeout.
>>>>>>
>>>>>> VAS FIFO offset is 0 when the receive window is opened during
>>>>>> initialization. When the module is reloaded or in kexec boot, readOffset
>>>>>> in FIFO control register may not match with VAS entry. This patch adds
>>>>>> nx_coproc_init OPAL call to reset readOffset and queued entries in FIFO
>>>>>> control register for both high and normal FIFOs.
>>>>>>
>>>>>> Signed-off-by: Haren Myneni <haren@us.ibm.com>
>>>>>>
>>>>>> diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
>>>>>> index d886a5b..ff61e4b 100644
>>>>>> --- a/arch/powerpc/include/asm/opal-api.h
>>>>>> +++ b/arch/powerpc/include/asm/opal-api.h
>>>>>> @@ -206,7 +206,8 @@
>>>>>> #define OPAL_NPU_TL_SET 161
>>>>>> #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164
>>>>>> #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165
>>>>>> -#define OPAL_LAST 165
>>>>>> +#define OPAL_NX_COPROC_INIT 167
>>>>>> +#define OPAL_LAST 167
>>>>>>
>>>>>> /* Device tree flags */
>>>>>>
>>>>>> diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
>>>>>> index 7159e1a..d79eb82 100644
>>>>>> --- a/arch/powerpc/include/asm/opal.h
>>>>>> +++ b/arch/powerpc/include/asm/opal.h
>>>>>> @@ -288,6 +288,7 @@ int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
>>>>>> int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
>>>>>> int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
>>>>>> int opal_sensor_group_clear(u32 group_hndl, int token);
>>>>>> +int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
>>>>>>
>>>>>> s64 opal_signal_system_reset(s32 cpu);
>>>>>>
>>>>>> diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
>>>>>> index 3da30c2..c7541a9 100644
>>>>>> --- a/arch/powerpc/platforms/powernv/opal-wrappers.S
>>>>>> +++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
>>>>>> @@ -325,3 +325,4 @@ OPAL_CALL(opal_npu_spa_clear_cache, OPAL_NPU_SPA_CLEAR_CACHE);
>>>>>> OPAL_CALL(opal_npu_tl_set, OPAL_NPU_TL_SET);
>>>>>> OPAL_CALL(opal_pci_get_pbcq_tunnel_bar, OPAL_PCI_GET_PBCQ_TUNNEL_BAR);
>>>>>> OPAL_CALL(opal_pci_set_pbcq_tunnel_bar, OPAL_PCI_SET_PBCQ_TUNNEL_BAR);
>>>>>> +OPAL_CALL(opal_nx_coproc_init, OPAL_NX_COPROC_INIT);
>>>>>> diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
>>>>>> index 48fbb41..5e13908 100644
>>>>>> --- a/arch/powerpc/platforms/powernv/opal.c
>>>>>> +++ b/arch/powerpc/platforms/powernv/opal.c
>>>>>> @@ -1035,3 +1035,5 @@ void powernv_set_nmmu_ptcr(unsigned long ptcr)
>>>>>> EXPORT_SYMBOL_GPL(opal_int_set_mfrr);
>>>>>> EXPORT_SYMBOL_GPL(opal_int_eoi);
>>>>>> EXPORT_SYMBOL_GPL(opal_error_code);
>>>>>> +/* Export the below symbol for NX compression */
>>>>>> +EXPORT_SYMBOL(opal_nx_coproc_init);
>>>>>> diff --git a/drivers/crypto/nx/nx-842-powernv.c b/drivers/crypto/nx/nx-842-powernv.c
>>>>>> index 1e87637..6c4784d 100644
>>>>>> --- a/drivers/crypto/nx/nx-842-powernv.c
>>>>>> +++ b/drivers/crypto/nx/nx-842-powernv.c
>>>>>> @@ -24,6 +24,8 @@
>>>>>> #include <asm/icswx.h>
>>>>>> #include <asm/vas.h>
>>>>>> #include <asm/reg.h>
>>>>>> +#include <asm/opal-api.h>
>>>>>> +#include <asm/opal.h>
>>>>>>
>>>>>> MODULE_LICENSE("GPL");
>>>>>> MODULE_AUTHOR("Dan Streetman <ddstreet@ieee.org>");
>>>>>> @@ -803,9 +805,26 @@ static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
>>>>>> if (!coproc)
>>>>>> return -ENOMEM;
>>>>>>
>>>>>> - if (!strcmp(priority, "High"))
>>>>>> + if (!strcmp(priority, "High")) {
>>>>>> + /*
>>>>>> + * (lpid, pid, tid) combination has to be unique for each
>>>>>> + * coprocessor instance in the system. So to make it
>>>>>> + * unique, skiboot uses coprocessor type such as 842 or
>>>>>> + * GZIP for pid and provides this value to kernel in pid
>>>>>> + * device-tree property.
>>>>>> + *
>>>>>> + * Initialize each NX instance for both high and normal
>>>>>> + * priority FIFOs.
>>>>>> + */
>>>>>> + ret = opal_nx_coproc_init(chip_id, pid);
>>>>>> + if (ret) {
>>>>>> + pr_err("Failed to initialize NX coproc: %d\n", ret);
>>>>>> + ret = opal_error_code(ret);
>>>>>> + goto err_out;
>>>>>> + }
>>>>>> +
>>>>>> coproc->ct = VAS_COP_TYPE_842_HIPRI;
>>>>>
>>>>> I think this should be called for all priority queues as it would be at
>>>>> least theoretically possible to only have Normal priority queues, in
>>>>> which case this patch wouldn't fix the problem.
>>>>
>>>> device tree exports separate nodes for high and normal priority FIFOs
>>>> per each NX instance. But NX init OPAL function is called once per
>>>> each NX instance when high-FIFO device node is parsed to reset high
>>>> and normal FIFO control registers. As you see in skiboot patch, resets
>>>> both priority registers. Thought we should minimize the number of OPAL
>>>> calla execution and also should have generic NX init OPAL call. We can
>>>> extend this call to reset default values for any other registers if
>>>> needed.
>>>
>>> This code does'nt do that though, it calls it for "high" priority, so if
>>> for whatever reason there was a DT without a "High" priority node there,
>>> it'd not call it.
>>
>> Skiboot exports high and normal FIFO nodes for each coprocessor type
>> per NX instance. We will never see only normal FIFO node without high
>> FIFO node. As we see in skiboot code, configure high FIFO and export
>> this node first, and then normal FIFO. In case if xscom read/ write
>> for high FIFO failed, we do not proceed for normal FIFO.
>
> Currently that's true, yes. But in the future it may not be. Imagine if
> we found a hardware bug that would mean disabling the 'High' priority
> one, or a future chip revision just had a single priority.
Correct, does not work for HW bug or NX does not support different priorities. But the current skiboot and kernel code has to be modified to support new chip revision anyway.
How about the following change - moved the OPAL caLL to nx842_powernv_probe_vas().
static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
- int vasid)
+ int vasid, int *ct)
{
struct vas_window *rxwin = NULL;
struct vas_rx_win_attr rxattr;
@@ -837,6 +839,15 @@ static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
coproc->vas.id = vasid;
nx842_add_coprocs_list(coproc, chip_id);
+ /*
+ * (lpid, pid, tid) combination has to be unique for each
+ * coprocessor instance in the system. So to make it
+ * unique, skiboot uses coprocessor type such as 842 or
+ * GZIP for pid and provides this value to kernel in pid
+ * device-tree property.
+ */
+ *ct = pid;
+
return 0;
err_out:
@@ -848,7 +859,7 @@ static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
static int __init nx842_powernv_probe_vas(struct device_node *pn)
{
struct device_node *dn;
- int chip_id, vasid, ret = 0;
+ int chip_id, vasid, ct, ret = 0;
int nx_fifo_found = 0;
chip_id = of_get_ibm_chip_id(pn);
@@ -865,7 +876,7 @@ static int __init nx842_powernv_probe_vas(struct device_node *pn)
for_each_child_of_node(pn, dn) {
if (of_device_is_compatible(dn, "ibm,p9-nx-842")) {
- ret = vas_cfg_coproc_info(dn, chip_id, vasid);
+ ret = vas_cfg_coproc_info(dn, chip_id, vasid, &ct);
if (ret) {
of_node_put(dn);
return ret;
@@ -879,6 +890,16 @@ static int __init nx842_powernv_probe_vas(struct device_node *pn)
ret = -EINVAL;
}
+ /*
+ * Initialize each NX instance for both high and normal
+ * priority FIFOs.
+ */
+ ret = opal_nx_coproc_init(chip_id, ct);
+ if (ret) {
+ pr_err("Failed to initialize NX coproc: %d\n", ret);
+ ret = opal_error_code(ret);
+ }
+
return ret;
}
^ permalink raw reply
* Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers
From: Stewart Smith @ 2018-06-04 4:08 UTC (permalink / raw)
To: Haren Myneni; +Cc: mpe, linuxppc-dev, herbert, linux-crypto
In-Reply-To: <5B14A797.2050306@linux.vnet.ibm.com>
Haren Myneni <haren@linux.vnet.ibm.com> writes:
> On 06/03/2018 05:41 PM, Stewart Smith wrote:
>> Haren Myneni <haren@linux.vnet.ibm.com> writes:
>>> On 06/01/2018 12:41 AM, Stewart Smith wrote:
>>>> Haren Myneni <haren@linux.vnet.ibm.com> writes:
>>>>> NX increments readOffset by FIFO size in receive FIFO control register
>>>>> when CRB is read. But the index in RxFIFO has to match with the
>>>>> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
>>>>> may be processing incorrect CRBs and can cause CRB timeout.
>>>>>
>>>>> VAS FIFO offset is 0 when the receive window is opened during
>>>>> initialization. When the module is reloaded or in kexec boot, readOffset
>>>>> in FIFO control register may not match with VAS entry. This patch adds
>>>>> nx_coproc_init OPAL call to reset readOffset and queued entries in FIFO
>>>>> control register for both high and normal FIFOs.
>>>>>
>>>>> Signed-off-by: Haren Myneni <haren@us.ibm.com>
>>>>>
>>>>> diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
>>>>> index d886a5b..ff61e4b 100644
>>>>> --- a/arch/powerpc/include/asm/opal-api.h
>>>>> +++ b/arch/powerpc/include/asm/opal-api.h
>>>>> @@ -206,7 +206,8 @@
>>>>> #define OPAL_NPU_TL_SET 161
>>>>> #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164
>>>>> #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165
>>>>> -#define OPAL_LAST 165
>>>>> +#define OPAL_NX_COPROC_INIT 167
>>>>> +#define OPAL_LAST 167
>>>>>
>>>>> /* Device tree flags */
>>>>>
>>>>> diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
>>>>> index 7159e1a..d79eb82 100644
>>>>> --- a/arch/powerpc/include/asm/opal.h
>>>>> +++ b/arch/powerpc/include/asm/opal.h
>>>>> @@ -288,6 +288,7 @@ int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
>>>>> int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
>>>>> int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
>>>>> int opal_sensor_group_clear(u32 group_hndl, int token);
>>>>> +int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
>>>>>
>>>>> s64 opal_signal_system_reset(s32 cpu);
>>>>>
>>>>> diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
>>>>> index 3da30c2..c7541a9 100644
>>>>> --- a/arch/powerpc/platforms/powernv/opal-wrappers.S
>>>>> +++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
>>>>> @@ -325,3 +325,4 @@ OPAL_CALL(opal_npu_spa_clear_cache, OPAL_NPU_SPA_CLEAR_CACHE);
>>>>> OPAL_CALL(opal_npu_tl_set, OPAL_NPU_TL_SET);
>>>>> OPAL_CALL(opal_pci_get_pbcq_tunnel_bar, OPAL_PCI_GET_PBCQ_TUNNEL_BAR);
>>>>> OPAL_CALL(opal_pci_set_pbcq_tunnel_bar, OPAL_PCI_SET_PBCQ_TUNNEL_BAR);
>>>>> +OPAL_CALL(opal_nx_coproc_init, OPAL_NX_COPROC_INIT);
>>>>> diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
>>>>> index 48fbb41..5e13908 100644
>>>>> --- a/arch/powerpc/platforms/powernv/opal.c
>>>>> +++ b/arch/powerpc/platforms/powernv/opal.c
>>>>> @@ -1035,3 +1035,5 @@ void powernv_set_nmmu_ptcr(unsigned long ptcr)
>>>>> EXPORT_SYMBOL_GPL(opal_int_set_mfrr);
>>>>> EXPORT_SYMBOL_GPL(opal_int_eoi);
>>>>> EXPORT_SYMBOL_GPL(opal_error_code);
>>>>> +/* Export the below symbol for NX compression */
>>>>> +EXPORT_SYMBOL(opal_nx_coproc_init);
>>>>> diff --git a/drivers/crypto/nx/nx-842-powernv.c b/drivers/crypto/nx/nx-842-powernv.c
>>>>> index 1e87637..6c4784d 100644
>>>>> --- a/drivers/crypto/nx/nx-842-powernv.c
>>>>> +++ b/drivers/crypto/nx/nx-842-powernv.c
>>>>> @@ -24,6 +24,8 @@
>>>>> #include <asm/icswx.h>
>>>>> #include <asm/vas.h>
>>>>> #include <asm/reg.h>
>>>>> +#include <asm/opal-api.h>
>>>>> +#include <asm/opal.h>
>>>>>
>>>>> MODULE_LICENSE("GPL");
>>>>> MODULE_AUTHOR("Dan Streetman <ddstreet@ieee.org>");
>>>>> @@ -803,9 +805,26 @@ static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
>>>>> if (!coproc)
>>>>> return -ENOMEM;
>>>>>
>>>>> - if (!strcmp(priority, "High"))
>>>>> + if (!strcmp(priority, "High")) {
>>>>> + /*
>>>>> + * (lpid, pid, tid) combination has to be unique for each
>>>>> + * coprocessor instance in the system. So to make it
>>>>> + * unique, skiboot uses coprocessor type such as 842 or
>>>>> + * GZIP for pid and provides this value to kernel in pid
>>>>> + * device-tree property.
>>>>> + *
>>>>> + * Initialize each NX instance for both high and normal
>>>>> + * priority FIFOs.
>>>>> + */
>>>>> + ret = opal_nx_coproc_init(chip_id, pid);
>>>>> + if (ret) {
>>>>> + pr_err("Failed to initialize NX coproc: %d\n", ret);
>>>>> + ret = opal_error_code(ret);
>>>>> + goto err_out;
>>>>> + }
>>>>> +
>>>>> coproc->ct = VAS_COP_TYPE_842_HIPRI;
>>>>
>>>> I think this should be called for all priority queues as it would be at
>>>> least theoretically possible to only have Normal priority queues, in
>>>> which case this patch wouldn't fix the problem.
>>>
>>> device tree exports separate nodes for high and normal priority FIFOs
>>> per each NX instance. But NX init OPAL function is called once per
>>> each NX instance when high-FIFO device node is parsed to reset high
>>> and normal FIFO control registers. As you see in skiboot patch, resets
>>> both priority registers. Thought we should minimize the number of OPAL
>>> calla execution and also should have generic NX init OPAL call. We can
>>> extend this call to reset default values for any other registers if
>>> needed.
>>
>> This code does'nt do that though, it calls it for "high" priority, so if
>> for whatever reason there was a DT without a "High" priority node there,
>> it'd not call it.
>
> Skiboot exports high and normal FIFO nodes for each coprocessor type
> per NX instance. We will never see only normal FIFO node without high
> FIFO node. As we see in skiboot code, configure high FIFO and export
> this node first, and then normal FIFO. In case if xscom read/ write
> for high FIFO failed, we do not proceed for normal FIFO.
Currently that's true, yes. But in the future it may not be. Imagine if
we found a hardware bug that would mean disabling the 'High' priority
one, or a future chip revision just had a single priority.
--
Stewart Smith
OPAL Architect, IBM.
^ permalink raw reply
* Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers
From: Haren Myneni @ 2018-06-04 2:44 UTC (permalink / raw)
To: Stewart Smith; +Cc: mpe, linuxppc-dev, herbert, linux-crypto
In-Reply-To: <87bmcr2xj4.fsf@linux.vnet.ibm.com>
On 06/03/2018 05:41 PM, Stewart Smith wrote:
> Haren Myneni <haren@linux.vnet.ibm.com> writes:
>> On 06/01/2018 12:41 AM, Stewart Smith wrote:
>>> Haren Myneni <haren@linux.vnet.ibm.com> writes:
>>>> NX increments readOffset by FIFO size in receive FIFO control register
>>>> when CRB is read. But the index in RxFIFO has to match with the
>>>> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
>>>> may be processing incorrect CRBs and can cause CRB timeout.
>>>>
>>>> VAS FIFO offset is 0 when the receive window is opened during
>>>> initialization. When the module is reloaded or in kexec boot, readOffset
>>>> in FIFO control register may not match with VAS entry. This patch adds
>>>> nx_coproc_init OPAL call to reset readOffset and queued entries in FIFO
>>>> control register for both high and normal FIFOs.
>>>>
>>>> Signed-off-by: Haren Myneni <haren@us.ibm.com>
>>>>
>>>> diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
>>>> index d886a5b..ff61e4b 100644
>>>> --- a/arch/powerpc/include/asm/opal-api.h
>>>> +++ b/arch/powerpc/include/asm/opal-api.h
>>>> @@ -206,7 +206,8 @@
>>>> #define OPAL_NPU_TL_SET 161
>>>> #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164
>>>> #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165
>>>> -#define OPAL_LAST 165
>>>> +#define OPAL_NX_COPROC_INIT 167
>>>> +#define OPAL_LAST 167
>>>>
>>>> /* Device tree flags */
>>>>
>>>> diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
>>>> index 7159e1a..d79eb82 100644
>>>> --- a/arch/powerpc/include/asm/opal.h
>>>> +++ b/arch/powerpc/include/asm/opal.h
>>>> @@ -288,6 +288,7 @@ int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
>>>> int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
>>>> int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
>>>> int opal_sensor_group_clear(u32 group_hndl, int token);
>>>> +int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
>>>>
>>>> s64 opal_signal_system_reset(s32 cpu);
>>>>
>>>> diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
>>>> index 3da30c2..c7541a9 100644
>>>> --- a/arch/powerpc/platforms/powernv/opal-wrappers.S
>>>> +++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
>>>> @@ -325,3 +325,4 @@ OPAL_CALL(opal_npu_spa_clear_cache, OPAL_NPU_SPA_CLEAR_CACHE);
>>>> OPAL_CALL(opal_npu_tl_set, OPAL_NPU_TL_SET);
>>>> OPAL_CALL(opal_pci_get_pbcq_tunnel_bar, OPAL_PCI_GET_PBCQ_TUNNEL_BAR);
>>>> OPAL_CALL(opal_pci_set_pbcq_tunnel_bar, OPAL_PCI_SET_PBCQ_TUNNEL_BAR);
>>>> +OPAL_CALL(opal_nx_coproc_init, OPAL_NX_COPROC_INIT);
>>>> diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
>>>> index 48fbb41..5e13908 100644
>>>> --- a/arch/powerpc/platforms/powernv/opal.c
>>>> +++ b/arch/powerpc/platforms/powernv/opal.c
>>>> @@ -1035,3 +1035,5 @@ void powernv_set_nmmu_ptcr(unsigned long ptcr)
>>>> EXPORT_SYMBOL_GPL(opal_int_set_mfrr);
>>>> EXPORT_SYMBOL_GPL(opal_int_eoi);
>>>> EXPORT_SYMBOL_GPL(opal_error_code);
>>>> +/* Export the below symbol for NX compression */
>>>> +EXPORT_SYMBOL(opal_nx_coproc_init);
>>>> diff --git a/drivers/crypto/nx/nx-842-powernv.c b/drivers/crypto/nx/nx-842-powernv.c
>>>> index 1e87637..6c4784d 100644
>>>> --- a/drivers/crypto/nx/nx-842-powernv.c
>>>> +++ b/drivers/crypto/nx/nx-842-powernv.c
>>>> @@ -24,6 +24,8 @@
>>>> #include <asm/icswx.h>
>>>> #include <asm/vas.h>
>>>> #include <asm/reg.h>
>>>> +#include <asm/opal-api.h>
>>>> +#include <asm/opal.h>
>>>>
>>>> MODULE_LICENSE("GPL");
>>>> MODULE_AUTHOR("Dan Streetman <ddstreet@ieee.org>");
>>>> @@ -803,9 +805,26 @@ static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
>>>> if (!coproc)
>>>> return -ENOMEM;
>>>>
>>>> - if (!strcmp(priority, "High"))
>>>> + if (!strcmp(priority, "High")) {
>>>> + /*
>>>> + * (lpid, pid, tid) combination has to be unique for each
>>>> + * coprocessor instance in the system. So to make it
>>>> + * unique, skiboot uses coprocessor type such as 842 or
>>>> + * GZIP for pid and provides this value to kernel in pid
>>>> + * device-tree property.
>>>> + *
>>>> + * Initialize each NX instance for both high and normal
>>>> + * priority FIFOs.
>>>> + */
>>>> + ret = opal_nx_coproc_init(chip_id, pid);
>>>> + if (ret) {
>>>> + pr_err("Failed to initialize NX coproc: %d\n", ret);
>>>> + ret = opal_error_code(ret);
>>>> + goto err_out;
>>>> + }
>>>> +
>>>> coproc->ct = VAS_COP_TYPE_842_HIPRI;
>>>
>>> I think this should be called for all priority queues as it would be at
>>> least theoretically possible to only have Normal priority queues, in
>>> which case this patch wouldn't fix the problem.
>>
>> device tree exports separate nodes for high and normal priority FIFOs
>> per each NX instance. But NX init OPAL function is called once per
>> each NX instance when high-FIFO device node is parsed to reset high
>> and normal FIFO control registers. As you see in skiboot patch, resets
>> both priority registers. Thought we should minimize the number of OPAL
>> calla execution and also should have generic NX init OPAL call. We can
>> extend this call to reset default values for any other registers if
>> needed.
>
> This code does'nt do that though, it calls it for "high" priority, so if
> for whatever reason there was a DT without a "High" priority node there,
> it'd not call it.
Skiboot exports high and normal FIFO nodes for each coprocessor type per NX instance. We will never see only normal FIFO node without high FIFO node. As we see in skiboot code, configure high FIFO and export this node first, and then normal FIFO. In case if xscom read/ write for high FIFO failed, we do not proceed for normal FIFO.
Also, we use only high priority FIFOs in kernel (nx-842). Normal FIFOs are reserved only for user space use (NX GZIP in future).
So we will not get in to the case that you described. Normal FIFO DT node will be available only with high FIFO node per each NX instance.
>
>> If you prefer calling separately based on priority, we can have
>> opal_nx_coproc_FIFO_init(chip_id, pid, priority). Please let me know.
>
> I think the call is okay, it's just that if it needs to be called once
> per accellerator, then we should ensure it does that.
>
^ permalink raw reply
* Re: powerpc/powernv: copy/paste - Mask XERS0 bit in CR
From: Haren Myneni @ 2018-06-04 2:15 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, sukadev
In-Reply-To: <87r2lokuxb.fsf@concordia.ellerman.id.au>
On 06/03/2018 03:48 AM, Michael Ellerman wrote:
> Hi Haren,
>
> Haren Myneni <haren@linux.vnet.ibm.com> writes:
>>
>> NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
>> which is not related to paste request. The current paste function
>> returns failure for the successful request when this bit is set.
>> So mask this bit and check the proper return status.
>>
>> Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
>> Cc: stable@vger.kernel.org # v4.14+
>> Signed-off-by: Haren Myneni <haren@us.ibm.com>
>>
>> diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
>> index c9a5036..82392e3 100644
>> --- a/arch/powerpc/platforms/powernv/copy-paste.h
>> +++ b/arch/powerpc/platforms/powernv/copy-paste.h
>> @@ -9,7 +9,8 @@
>> #include <asm/ppc-opcode.h>
>>
>> #define CR0_SHIFT 28
>> -#define CR0_MASK 0xF
>> +#define CR0_MASK 0xE /* 3rd bit undefined or set for XER[SO] */
>> +
>> /*
>> * Copy/paste instructions:
>> *
>
> Unfortunately this no longer applies to my next branch, because those
> macros have been moved out of this header as part of an unrelated patch.
>
> The following patch should work instead, can you please confirm by
> testing it?
>
> diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
> index 3fa62de96d9c..c46a326776cf 100644
> --- a/arch/powerpc/platforms/powernv/copy-paste.h
> +++ b/arch/powerpc/platforms/powernv/copy-paste.h
> @@ -41,5 +41,7 @@ static inline int vas_paste(void *paste_address, int offset)
> : "b" (offset), "b" (paste_address)
> : "memory", "cr0");
>
> - return (cr >> CR0_SHIFT) & CR0_MASK;
> +
> + /* We mask with 0xE to ignore SO */
> + return (cr >> CR0_SHIFT) & 0xE;
> }
>
>
Tested with this patch and it works.
Thanks
Haren
> cheers
>
^ permalink raw reply
* Re: [PATCH v2 07/13] powerpc/eeh: Clean up pci_ers_result handling
From: Sam Bobroff @ 2018-06-04 1:28 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
In-Reply-To: <87muwe3475.fsf@concordia.ellerman.id.au>
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On Sat, Jun 02, 2018 at 01:40:46AM +1000, Michael Ellerman wrote:
> Sam Bobroff <sbobroff@linux.ibm.com> writes:
>
> > As EEH event handling progresses, a cumulative result of type
> > pci_ers_result is built up by (some of) the eeh_report_*() functions
> > using either:
> > if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
> > if (*res == PCI_ERS_RESULT_NONE) *res = rc;
> > or:
> > if ((*res == PCI_ERS_RESULT_NONE) ||
> > (*res == PCI_ERS_RESULT_RECOVERED)) *res = rc;
> > if (*res == PCI_ERS_RESULT_DISCONNECT &&
> > rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
> > (Where *res is the accumulator.)
> >
> > However, the intent is not immediately clear and the result in some
> > situations is order dependent.
> >
> > Address this by assigning a priority to each result value, and always
> > merging to the highest priority. This renders the intent clear, and
> > provides a stable value for all orderings.
> >
> > Signed-off-by: Sam Bobroff <sbobroff@linux.ibm.com>
> > ---
> > ====== v1 -> v2: ======
> >
> > * Added the value, and missing newline, to some WARN()s.
> > * Improved name of merge_result() to pci_ers_merge_result().
> > * Adjusted the result priorities so that unknown doesn't overlap with _NONE.
>
> These === markers seem to have confused patchwork, they ended up in the
> patch, and then git put them in the changelog.
>
> http://patchwork.ozlabs.org/patch/920194/
>
> The usual format is just something like:
>
> v2 - Added the value, and missing newline, to some WARN()s.
> - Improved name of merge_result() to pci_ers_merge_result().
> - Adjusted the result priorities so that unknown doesn't overlap with _NONE.
>
> cheers
Oh! I'll change it!
Sam.
>
> > arch/powerpc/kernel/eeh_driver.c | 36 ++++++++++++++++++++++++++----------
> > 1 file changed, 26 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/powerpc/kernel/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c
> > index 188d15c4fe3a..2d3cac584899 100644
> > --- a/arch/powerpc/kernel/eeh_driver.c
> > +++ b/arch/powerpc/kernel/eeh_driver.c
> > @@ -39,6 +39,29 @@ struct eeh_rmv_data {
> > int removed;
> > };
> >
> > +static int eeh_result_priority(enum pci_ers_result result)
> > +{
> > + switch (result) {
> > + case PCI_ERS_RESULT_NONE: return 1;
> > + case PCI_ERS_RESULT_NO_AER_DRIVER: return 2;
> > + case PCI_ERS_RESULT_RECOVERED: return 3;
> > + case PCI_ERS_RESULT_CAN_RECOVER: return 4;
> > + case PCI_ERS_RESULT_DISCONNECT: return 5;
> > + case PCI_ERS_RESULT_NEED_RESET: return 6;
> > + default:
> > + WARN_ONCE(1, "Unknown pci_ers_result value: %d\n", (int)result);
> > + return 0;
> > + }
> > +};
> > +
> > +static enum pci_ers_result pci_ers_merge_result(enum pci_ers_result old,
> > + enum pci_ers_result new)
> > +{
> > + if (eeh_result_priority(new) > eeh_result_priority(old))
> > + return new;
> > + return old;
> > +}
> > +
> > /**
> > * eeh_pcid_get - Get the PCI device driver
> > * @pdev: PCI device
> > @@ -206,9 +229,7 @@ static void *eeh_report_error(struct eeh_dev *edev, void *userdata)
> >
> > rc = driver->err_handler->error_detected(dev, pci_channel_io_frozen);
> >
> > - /* A driver that needs a reset trumps all others */
> > - if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
> > - if (*res == PCI_ERS_RESULT_NONE) *res = rc;
> > + *res = pci_ers_merge_result(*res, rc);
> >
> > edev->in_error = true;
> > pci_uevent_ers(dev, PCI_ERS_RESULT_NONE);
> > @@ -249,9 +270,7 @@ static void *eeh_report_mmio_enabled(struct eeh_dev *edev, void *userdata)
> >
> > rc = driver->err_handler->mmio_enabled(dev);
> >
> > - /* A driver that needs a reset trumps all others */
> > - if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
> > - if (*res == PCI_ERS_RESULT_NONE) *res = rc;
> > + *res = pci_ers_merge_result(*res, rc);
> >
> > out:
> > eeh_pcid_put(dev);
> > @@ -294,10 +313,7 @@ static void *eeh_report_reset(struct eeh_dev *edev, void *userdata)
> > goto out;
> >
> > rc = driver->err_handler->slot_reset(dev);
> > - if ((*res == PCI_ERS_RESULT_NONE) ||
> > - (*res == PCI_ERS_RESULT_RECOVERED)) *res = rc;
> > - if (*res == PCI_ERS_RESULT_DISCONNECT &&
> > - rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
> > + *res = pci_ers_merge_result(*res, rc);
> >
> > out:
> > eeh_pcid_put(dev);
> > --
> > 2.16.1.74.g9b0b1f47b
>
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^ permalink raw reply
* Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers
From: Stewart Smith @ 2018-06-04 0:41 UTC (permalink / raw)
To: Haren Myneni; +Cc: mpe, linuxppc-dev, herbert, linux-crypto
In-Reply-To: <5B117946.8010100@linux.vnet.ibm.com>
Haren Myneni <haren@linux.vnet.ibm.com> writes:
> On 06/01/2018 12:41 AM, Stewart Smith wrote:
>> Haren Myneni <haren@linux.vnet.ibm.com> writes:
>>> NX increments readOffset by FIFO size in receive FIFO control register
>>> when CRB is read. But the index in RxFIFO has to match with the
>>> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
>>> may be processing incorrect CRBs and can cause CRB timeout.
>>>
>>> VAS FIFO offset is 0 when the receive window is opened during
>>> initialization. When the module is reloaded or in kexec boot, readOffset
>>> in FIFO control register may not match with VAS entry. This patch adds
>>> nx_coproc_init OPAL call to reset readOffset and queued entries in FIFO
>>> control register for both high and normal FIFOs.
>>>
>>> Signed-off-by: Haren Myneni <haren@us.ibm.com>
>>>
>>> diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
>>> index d886a5b..ff61e4b 100644
>>> --- a/arch/powerpc/include/asm/opal-api.h
>>> +++ b/arch/powerpc/include/asm/opal-api.h
>>> @@ -206,7 +206,8 @@
>>> #define OPAL_NPU_TL_SET 161
>>> #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164
>>> #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165
>>> -#define OPAL_LAST 165
>>> +#define OPAL_NX_COPROC_INIT 167
>>> +#define OPAL_LAST 167
>>>
>>> /* Device tree flags */
>>>
>>> diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
>>> index 7159e1a..d79eb82 100644
>>> --- a/arch/powerpc/include/asm/opal.h
>>> +++ b/arch/powerpc/include/asm/opal.h
>>> @@ -288,6 +288,7 @@ int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
>>> int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
>>> int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
>>> int opal_sensor_group_clear(u32 group_hndl, int token);
>>> +int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
>>>
>>> s64 opal_signal_system_reset(s32 cpu);
>>>
>>> diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
>>> index 3da30c2..c7541a9 100644
>>> --- a/arch/powerpc/platforms/powernv/opal-wrappers.S
>>> +++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
>>> @@ -325,3 +325,4 @@ OPAL_CALL(opal_npu_spa_clear_cache, OPAL_NPU_SPA_CLEAR_CACHE);
>>> OPAL_CALL(opal_npu_tl_set, OPAL_NPU_TL_SET);
>>> OPAL_CALL(opal_pci_get_pbcq_tunnel_bar, OPAL_PCI_GET_PBCQ_TUNNEL_BAR);
>>> OPAL_CALL(opal_pci_set_pbcq_tunnel_bar, OPAL_PCI_SET_PBCQ_TUNNEL_BAR);
>>> +OPAL_CALL(opal_nx_coproc_init, OPAL_NX_COPROC_INIT);
>>> diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
>>> index 48fbb41..5e13908 100644
>>> --- a/arch/powerpc/platforms/powernv/opal.c
>>> +++ b/arch/powerpc/platforms/powernv/opal.c
>>> @@ -1035,3 +1035,5 @@ void powernv_set_nmmu_ptcr(unsigned long ptcr)
>>> EXPORT_SYMBOL_GPL(opal_int_set_mfrr);
>>> EXPORT_SYMBOL_GPL(opal_int_eoi);
>>> EXPORT_SYMBOL_GPL(opal_error_code);
>>> +/* Export the below symbol for NX compression */
>>> +EXPORT_SYMBOL(opal_nx_coproc_init);
>>> diff --git a/drivers/crypto/nx/nx-842-powernv.c b/drivers/crypto/nx/nx-842-powernv.c
>>> index 1e87637..6c4784d 100644
>>> --- a/drivers/crypto/nx/nx-842-powernv.c
>>> +++ b/drivers/crypto/nx/nx-842-powernv.c
>>> @@ -24,6 +24,8 @@
>>> #include <asm/icswx.h>
>>> #include <asm/vas.h>
>>> #include <asm/reg.h>
>>> +#include <asm/opal-api.h>
>>> +#include <asm/opal.h>
>>>
>>> MODULE_LICENSE("GPL");
>>> MODULE_AUTHOR("Dan Streetman <ddstreet@ieee.org>");
>>> @@ -803,9 +805,26 @@ static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
>>> if (!coproc)
>>> return -ENOMEM;
>>>
>>> - if (!strcmp(priority, "High"))
>>> + if (!strcmp(priority, "High")) {
>>> + /*
>>> + * (lpid, pid, tid) combination has to be unique for each
>>> + * coprocessor instance in the system. So to make it
>>> + * unique, skiboot uses coprocessor type such as 842 or
>>> + * GZIP for pid and provides this value to kernel in pid
>>> + * device-tree property.
>>> + *
>>> + * Initialize each NX instance for both high and normal
>>> + * priority FIFOs.
>>> + */
>>> + ret = opal_nx_coproc_init(chip_id, pid);
>>> + if (ret) {
>>> + pr_err("Failed to initialize NX coproc: %d\n", ret);
>>> + ret = opal_error_code(ret);
>>> + goto err_out;
>>> + }
>>> +
>>> coproc->ct = VAS_COP_TYPE_842_HIPRI;
>>
>> I think this should be called for all priority queues as it would be at
>> least theoretically possible to only have Normal priority queues, in
>> which case this patch wouldn't fix the problem.
>
> device tree exports separate nodes for high and normal priority FIFOs
> per each NX instance. But NX init OPAL function is called once per
> each NX instance when high-FIFO device node is parsed to reset high
> and normal FIFO control registers. As you see in skiboot patch, resets
> both priority registers. Thought we should minimize the number of OPAL
> calla execution and also should have generic NX init OPAL call. We can
> extend this call to reset default values for any other registers if
> needed.
This code does'nt do that though, it calls it for "high" priority, so if
for whatever reason there was a DT without a "High" priority node there,
it'd not call it.
> If you prefer calling separately based on priority, we can have
> opal_nx_coproc_FIFO_init(chip_id, pid, priority). Please let me know.
I think the call is okay, it's just that if it needs to be called once
per accellerator, then we should ensure it does that.
--
Stewart Smith
OPAL Architect, IBM.
^ permalink raw reply
* Re: pkeys on POWER: Access rights not reset on execve
From: Ram Pai @ 2018-06-03 20:18 UTC (permalink / raw)
To: Florian Weimer; +Cc: Andy Lutomirski, Linux-MM, linuxppc-dev, Dave Hansen
In-Reply-To: <aae1952c-886b-cfc8-e98b-fa3be5fab0fa@redhat.com>
On Mon, May 21, 2018 at 01:29:11PM +0200, Florian Weimer wrote:
> On 05/20/2018 09:11 PM, Ram Pai wrote:
> >Florian,
> >
> > Does the following patch fix the problem for you? Just like x86
> > I am enabling all keys in the UAMOR register during
> > initialization itself. Hence any key created by any thread at
> > any time, will get activated on all threads. So any thread
> > can change the permission on that key. Smoke tested it
> > with your test program.
>
> I think this goes in the right direction, but the AMR value after
> fork is still strange:
>
> AMR (PID 34912): 0x0000000000000000
> AMR after fork (PID 34913): 0x0000000000000000
> AMR (PID 34913): 0x0000000000000000
> Allocated key in subprocess (PID 34913): 2
> Allocated key (PID 34912): 2
> Setting AMR: 0xffffffffffffffff
> New AMR value (PID 34912): 0x0fffffffffffffff
> About to call execl (PID 34912) ...
> AMR (PID 34912): 0x0fffffffffffffff
> AMR after fork (PID 34914): 0x0000000000000003
> AMR (PID 34914): 0x0000000000000003
> Allocated key in subprocess (PID 34914): 2
> Allocated key (PID 34912): 2
> Setting AMR: 0xffffffffffffffff
> New AMR value (PID 34912): 0x0fffffffffffffff
>
> I mean this line:
>
> AMR after fork (PID 34914): 0x0000000000000003
>
> Shouldn't it be the same as in the parent process?
Fixed it. Please try this patch. If it all works to your satisfaction, I
will clean it up further and send to Michael Ellermen(ppc maintainer).
commit 51f4208ed5baeab1edb9b0f8b68d7144449b3527
Author: Ram Pai <linuxram@us.ibm.com>
Date: Sun Jun 3 14:44:32 2018 -0500
Fix for the fork bug.
Signed-off-by: Ram Pai <linuxram@us.ibm.com>
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 1237f13..999dd08 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -582,6 +582,7 @@ static void save_all(struct task_struct *tsk)
__giveup_spe(tsk);
msr_check_and_clear(msr_all_available);
+ thread_pkey_regs_save(&tsk->thread);
}
void flush_all_to_thread(struct task_struct *tsk)
diff --git a/arch/powerpc/mm/pkeys.c b/arch/powerpc/mm/pkeys.c
index ab4519a..af6aa4a 100644
--- a/arch/powerpc/mm/pkeys.c
+++ b/arch/powerpc/mm/pkeys.c
@@ -294,6 +294,7 @@ void thread_pkey_regs_save(struct thread_struct *thread)
*/
thread->amr = read_amr();
thread->iamr = read_iamr();
+ thread->uamor = read_uamor();
}
void thread_pkey_regs_restore(struct thread_struct *new_thread,
@@ -315,9 +316,13 @@ void thread_pkey_regs_init(struct thread_struct *thread)
if (static_branch_likely(&pkey_disabled))
return;
- thread->amr = read_amr() & pkey_amr_mask;
- thread->iamr = read_iamr() & pkey_iamr_mask;
+ thread->amr = pkey_amr_mask;
+ thread->iamr = pkey_iamr_mask;
thread->uamor = pkey_uamor_mask;
+
+ write_uamor(pkey_uamor_mask);
+ write_amr(pkey_amr_mask);
+ write_iamr(pkey_iamr_mask);
}
static inline bool pkey_allows_readwrite(int pkey)
>
> Thanks,
> Florian
--
Ram Pai
^ permalink raw reply related
* [RFC v9 4/4] mobility/numa: Ensure numa update does not overlap
From: Michael Bringmann @ 2018-06-03 20:04 UTC (permalink / raw)
To: open list:LINUX FOR POWERPC (32-BIT AND 64-BIT), linuxppc-dev
Cc: Michael Bringmann, Nathan Fontenot, John Allen, Tyrel Datwyler,
Thomas Falcon
In-Reply-To: <95c97180-37b7-85da-a82f-17dbc73f5ed6@linux.vnet.ibm.com>
[Testing delayed due to internal SAN problems.]
mobility/numa: Ensure that numa_update_cpu_topology() can not be
entered multiple times concurrently. It may be accessed through
many different paths / concurrent work functions, and the lock
ordering may be difficult to ensure otherwise.
Signed-off-by: Michael Bringmann <mwb@linux.vnet.ibm.com>
---
arch/powerpc/mm/numa.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 8802e7d..d4543b3 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -1079,6 +1079,7 @@ struct topology_update_data {
static int topology_timer_secs = 1;
static int topology_inited;
static int topology_update_needed;
+static struct mutex topology_update_lock;
/*
* Change polling interval for associativity changes.
@@ -1320,6 +1321,11 @@ int numa_update_cpu_topology(bool cpus_locked)
if (!updates)
return 0;
+ if (!mutex_trylock(&topology_update_lock)) {
+ kfree(updates);
+ return 0;
+ }
+
cpumask_clear(&updated_cpus);
for_each_cpu(cpu, &cpu_associativity_changes_mask) {
@@ -1424,6 +1430,7 @@ int numa_update_cpu_topology(bool cpus_locked)
out:
kfree(updates);
topology_update_needed = 0;
+ mutex_unlock(&topology_update_lock);
return changed;
}
@@ -1598,6 +1605,8 @@ static ssize_t topology_write(struct file *file, const char __user *buf,
static int topology_update_init(void)
{
+ mutex_init(&topology_update_lock);
+
/* Do not poll for changes if disabled at boot */
if (topology_updates_enabled)
start_topology_update();
^ permalink raw reply related
* [RFC v9 3/4] hotplug/dlpar/cpu: Provide CPU readd operation
From: Michael Bringmann @ 2018-06-03 20:04 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michael Bringmann, Nathan Fontenot, John Allen, Tyrel Datwyler,
Thomas Falcon
In-Reply-To: <95c97180-37b7-85da-a82f-17dbc73f5ed6@linux.vnet.ibm.com>
[Testing delayed due to internal SAN problems.]
powerpc/dlpar: Provide hotplug CPU 'readd by index' operation to
support LPAR Post Migration state updates. When such changes are
invoked by the PowerPC 'mobility' code, they will be queued up so
that modifications to CPU properties will take place after the new
property value is written to the device-tree.
Signed-off-by: Michael Bringmann <mwb@linux.vnet.ibm.com>
---
Changes in RFC:
-- Add CPU validity check to pseries_smp_notifier
-- Improve check on 'ibm,associativity' property
---
arch/powerpc/platforms/pseries/hotplug-cpu.c | 61 ++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index 3632db2..be7ff7c 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -305,6 +305,37 @@ static int pseries_add_processor(struct device_node *np)
return err;
}
+static int pseries_update_processor(struct of_reconfig_data *pr)
+{
+ int old_entries, new_entries, rc = 0;
+ __be32 *old_assoc, *new_assoc;
+
+ /* We only handle changes due to 'ibm,associativity' property
+ */
+ old_assoc = pr->old_prop->value;
+ old_entries = be32_to_cpu(*old_assoc++);
+
+ new_assoc = pr->prop->value;
+ new_entries = be32_to_cpu(*new_assoc++);
+
+ if (old_entries == new_entries) {
+ int sz = old_entries * sizeof(int);
+
+ if (memcmp(old_assoc, new_assoc, sz))
+ rc = dlpar_delayed_queue_action(
+ PSERIES_HP_ELOG_RESOURCE_CPU,
+ PSERIES_HP_ELOG_ACTION_READD,
+ pr->dn->phandle);
+ } else {
+ rc = dlpar_delayed_queue_action(
+ PSERIES_HP_ELOG_RESOURCE_CPU,
+ PSERIES_HP_ELOG_ACTION_READD,
+ pr->dn->phandle);
+ }
+
+ return rc;
+}
+
/*
* Update the present map for a cpu node which is going away, and set
* the hard id in the paca(s) to -1 to be consistent with boot time
@@ -649,6 +680,26 @@ static int dlpar_cpu_remove_by_index(u32 drc_index, bool release_drc)
return rc;
}
+static int dlpar_cpu_readd_by_index(u32 drc_index)
+{
+ int rc = 0;
+
+ pr_info("Attempting to re-add CPU, drc index %x\n", drc_index);
+
+ rc = dlpar_cpu_remove_by_index(drc_index, false);
+ if (!rc)
+ rc = dlpar_cpu_add(drc_index, false);
+
+ if (rc)
+ pr_info("Failed to update cpu at drc_index %lx\n",
+ (unsigned long int)drc_index);
+ else
+ pr_info("CPU at drc_index %lx was updated\n",
+ (unsigned long int)drc_index);
+
+ return rc;
+}
+
static int find_dlpar_cpus_to_remove(u32 *cpu_drcs, int cpus_to_remove)
{
struct device_node *dn;
@@ -839,6 +890,9 @@ int dlpar_cpu(struct pseries_hp_errorlog *hp_elog)
else
rc = -EINVAL;
break;
+ case PSERIES_HP_ELOG_ACTION_READD:
+ rc = dlpar_cpu_readd_by_index(drc_index);
+ break;
default:
pr_err("Invalid action (%d) specified\n", hp_elog->action);
rc = -EINVAL;
@@ -895,6 +949,9 @@ static int pseries_smp_notifier(struct notifier_block *nb,
struct of_reconfig_data *rd = data;
int err = 0;
+ if (strcmp(rd->dn->type, "cpu"))
+ return notifier_from_errno(err);
+
switch (action) {
case OF_RECONFIG_ATTACH_NODE:
err = pseries_add_processor(rd->dn);
@@ -902,6 +959,10 @@ static int pseries_smp_notifier(struct notifier_block *nb,
case OF_RECONFIG_DETACH_NODE:
pseries_remove_processor(rd->dn);
break;
+ case OF_RECONFIG_UPDATE_PROPERTY:
+ if (!strcmp(rd->prop->name, "ibm,associativity"))
+ pseries_update_processor(rd);
+ break;
}
return notifier_from_errno(err);
}
^ permalink raw reply related
* [RFC v9 2/4] hotplug/cpu: Add operation queuing function
From: Michael Bringmann @ 2018-06-03 20:04 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michael Bringmann, Nathan Fontenot, John Allen, Tyrel Datwyler,
Thomas Falcon
In-Reply-To: <95c97180-37b7-85da-a82f-17dbc73f5ed6@linux.vnet.ibm.com>
[Testing delayed due to internal SAN problems.]
migration/dlpar: This patch adds function dlpar_queue_action()
which will add information about a CPU/Memory 'readd' operation
according to resource type, action code, and DRC index. Initial
usage is for the 'readd' CPU and Memory blocks identified as
having changed their associativity during a migration event.
Signed-off-by: Michael Bringmann <mwb@linux.vnet.ibm.com>
---
Changes in RFC:
-- Correct drc_index for dlpar_queue_action worker invocation
-- Correct text of notice
-- Revise queuing model to save up all of the DLPAR actions for
later execution.
---
arch/powerpc/platforms/pseries/dlpar.c | 51 ++++++++++++++++++++++++++++++
arch/powerpc/platforms/pseries/pseries.h | 2 +
2 files changed, 53 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
index a0b20c0..a1300d2 100644
--- a/arch/powerpc/platforms/pseries/dlpar.c
+++ b/arch/powerpc/platforms/pseries/dlpar.c
@@ -407,6 +407,57 @@ void queue_hotplug_event(struct pseries_hp_errorlog *hp_errlog,
}
}
+struct DlparWork {
+ struct list_head list;
+ int resource;
+ int action;
+ u32 drc_index;
+} DlparWorkQ;
+
+int dlpar_delayed_queue_action(int resource, int action, u32 drc_index)
+{
+ struct DlparWork *dwq;
+
+ dwq = kmalloc(sizeof(struct DlparWork), GFP_KERNEL);
+ if (!dwq)
+ return -ENOMEM;
+
+ dwq->resource = resource;
+ dwq->action = action;
+ dwq->drc_index = drc_index;
+
+ list_add_tail(&dwq->list, &DlparWorkQ.list);
+
+ return 0;
+}
+
+int dlpar_schedule_delayed_queue(void)
+{
+ struct DlparWork *iter;
+ struct list_head *pos, *q;
+
+ list_for_each_entry(iter, &DlparWorkQ.list, list) {
+ struct pseries_hp_errorlog hp_elog;
+
+ hp_elog.resource = iter->resource;
+ hp_elog.action = iter->action;
+ hp_elog.id_type = PSERIES_HP_ELOG_ID_DRC_INDEX;
+ hp_elog._drc_u.drc_index = cpu_to_be32(iter->drc_index);
+
+ handle_dlpar_errorlog(&hp_elog);
+ }
+
+ list_for_each_safe(pos, q, &DlparWorkQ.list) {
+ struct DlparWork *tmp;
+
+ tmp = list_entry(pos, struct DlparWork, list);
+ list_del(pos);
+ kfree(tmp);
+ }
+
+ return 0;
+}
+
static int dlpar_parse_resource(char **cmd, struct pseries_hp_errorlog *hp_elog)
{
char *arg;
diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index 60db2ee..de73fda 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -61,6 +61,8 @@ extern struct device_node *dlpar_configure_connector(__be32,
void queue_hotplug_event(struct pseries_hp_errorlog *hp_errlog,
struct completion *hotplug_done, int *rc);
+int dlpar_delayed_queue_action(int resource, int action, u32 drc_index);
+int dlpar_schedule_delayed_queue(void);
#ifdef CONFIG_MEMORY_HOTPLUG
int dlpar_memory(struct pseries_hp_errorlog *hp_elog);
#else
^ permalink raw reply related
* [RFC v9 1/4] hotplug/cpu: Conditionally acquire/release DRC index
From: Michael Bringmann @ 2018-06-03 20:04 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michael Bringmann, Nathan Fontenot, John Allen, Tyrel Datwyler,
Thomas Falcon
In-Reply-To: <95c97180-37b7-85da-a82f-17dbc73f5ed6@linux.vnet.ibm.com>
[Testing delayed due to internal SAN problems.]
powerpc/cpu: Modify dlpar_cpu_add and dlpar_cpu_remove to allow the
skipping of DRC index acquire or release operations during the CPU
add or remove operations. This is intended to support subsequent
changes to provide a 'CPU readd' operation.
Signed-off-by: Michael Bringmann <mwb@linux.vnet.ibm.com>
---
Changes in RFC:
-- Move new validity check added to pseries_smp_notifier
to another patch
---
arch/powerpc/platforms/pseries/hotplug-cpu.c | 68 +++++++++++++++-----------
1 file changed, 39 insertions(+), 29 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index 6ef77ca..3632db2 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -432,7 +432,7 @@ static bool valid_cpu_drc_index(struct device_node *parent, u32 drc_index)
return found;
}
-static ssize_t dlpar_cpu_add(u32 drc_index)
+static ssize_t dlpar_cpu_add(u32 drc_index, bool acquire_drc)
{
struct device_node *dn, *parent;
int rc, saved_rc;
@@ -457,19 +457,22 @@ static ssize_t dlpar_cpu_add(u32 drc_index)
return -EINVAL;
}
- rc = dlpar_acquire_drc(drc_index);
- if (rc) {
- pr_warn("Failed to acquire DRC, rc: %d, drc index: %x\n",
- rc, drc_index);
- of_node_put(parent);
- return -EINVAL;
+ if (acquire_drc) {
+ rc = dlpar_acquire_drc(drc_index);
+ if (rc) {
+ pr_warn("Failed to acquire DRC, rc: %d, drc index: %x\n",
+ rc, drc_index);
+ of_node_put(parent);
+ return -EINVAL;
+ }
}
dn = dlpar_configure_connector(cpu_to_be32(drc_index), parent);
if (!dn) {
pr_warn("Failed call to configure-connector, drc index: %x\n",
drc_index);
- dlpar_release_drc(drc_index);
+ if (acquire_drc)
+ dlpar_release_drc(drc_index);
of_node_put(parent);
return -EINVAL;
}
@@ -484,8 +487,9 @@ static ssize_t dlpar_cpu_add(u32 drc_index)
pr_warn("Failed to attach node %s, rc: %d, drc index: %x\n",
dn->name, rc, drc_index);
- rc = dlpar_release_drc(drc_index);
- if (!rc)
+ if (acquire_drc)
+ rc = dlpar_release_drc(drc_index);
+ if (!rc || acquire_drc)
dlpar_free_cc_nodes(dn);
return saved_rc;
@@ -498,7 +502,7 @@ static ssize_t dlpar_cpu_add(u32 drc_index)
dn->name, rc, drc_index);
rc = dlpar_detach_node(dn);
- if (!rc)
+ if (!rc && acquire_drc)
dlpar_release_drc(drc_index);
return saved_rc;
@@ -566,7 +570,8 @@ static int dlpar_offline_cpu(struct device_node *dn)
}
-static ssize_t dlpar_cpu_remove(struct device_node *dn, u32 drc_index)
+static ssize_t dlpar_cpu_remove(struct device_node *dn, u32 drc_index,
+ bool release_drc)
{
int rc;
@@ -579,12 +584,14 @@ static ssize_t dlpar_cpu_remove(struct device_node *dn, u32 drc_index)
return -EINVAL;
}
- rc = dlpar_release_drc(drc_index);
- if (rc) {
- pr_warn("Failed to release drc (%x) for CPU %s, rc: %d\n",
- drc_index, dn->name, rc);
- dlpar_online_cpu(dn);
- return rc;
+ if (release_drc) {
+ rc = dlpar_release_drc(drc_index);
+ if (rc) {
+ pr_warn("Failed to release drc (%x) for CPU %s, rc: %d\n",
+ drc_index, dn->name, rc);
+ dlpar_online_cpu(dn);
+ return rc;
+ }
}
rc = dlpar_detach_node(dn);
@@ -593,7 +600,10 @@ static ssize_t dlpar_cpu_remove(struct device_node *dn, u32 drc_index)
pr_warn("Failed to detach CPU %s, rc: %d", dn->name, rc);
- rc = dlpar_acquire_drc(drc_index);
+ if (release_drc)
+ rc = dlpar_acquire_drc(drc_index);
+ else
+ rc = 0;
if (!rc)
dlpar_online_cpu(dn);
@@ -622,7 +632,7 @@ static struct device_node *cpu_drc_index_to_dn(u32 drc_index)
return dn;
}
-static int dlpar_cpu_remove_by_index(u32 drc_index)
+static int dlpar_cpu_remove_by_index(u32 drc_index, bool release_drc)
{
struct device_node *dn;
int rc;
@@ -634,7 +644,7 @@ static int dlpar_cpu_remove_by_index(u32 drc_index)
return -ENODEV;
}
- rc = dlpar_cpu_remove(dn, drc_index);
+ rc = dlpar_cpu_remove(dn, drc_index, release_drc);
of_node_put(dn);
return rc;
}
@@ -699,7 +709,7 @@ static int dlpar_cpu_remove_by_count(u32 cpus_to_remove)
}
for (i = 0; i < cpus_to_remove; i++) {
- rc = dlpar_cpu_remove_by_index(cpu_drcs[i]);
+ rc = dlpar_cpu_remove_by_index(cpu_drcs[i], true);
if (rc)
break;
@@ -710,7 +720,7 @@ static int dlpar_cpu_remove_by_count(u32 cpus_to_remove)
pr_warn("CPU hot-remove failed, adding back removed CPUs\n");
for (i = 0; i < cpus_removed; i++)
- dlpar_cpu_add(cpu_drcs[i]);
+ dlpar_cpu_add(cpu_drcs[i], true);
rc = -EINVAL;
} else {
@@ -780,7 +790,7 @@ static int dlpar_cpu_add_by_count(u32 cpus_to_add)
}
for (i = 0; i < cpus_to_add; i++) {
- rc = dlpar_cpu_add(cpu_drcs[i]);
+ rc = dlpar_cpu_add(cpu_drcs[i], true);
if (rc)
break;
@@ -791,7 +801,7 @@ static int dlpar_cpu_add_by_count(u32 cpus_to_add)
pr_warn("CPU hot-add failed, removing any added CPUs\n");
for (i = 0; i < cpus_added; i++)
- dlpar_cpu_remove_by_index(cpu_drcs[i]);
+ dlpar_cpu_remove_by_index(cpu_drcs[i], true);
rc = -EINVAL;
} else {
@@ -817,7 +827,7 @@ int dlpar_cpu(struct pseries_hp_errorlog *hp_elog)
if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_COUNT)
rc = dlpar_cpu_remove_by_count(count);
else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX)
- rc = dlpar_cpu_remove_by_index(drc_index);
+ rc = dlpar_cpu_remove_by_index(drc_index, true);
else
rc = -EINVAL;
break;
@@ -825,7 +835,7 @@ int dlpar_cpu(struct pseries_hp_errorlog *hp_elog)
if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_COUNT)
rc = dlpar_cpu_add_by_count(count);
else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX)
- rc = dlpar_cpu_add(drc_index);
+ rc = dlpar_cpu_add(drc_index, true);
else
rc = -EINVAL;
break;
@@ -850,7 +860,7 @@ static ssize_t dlpar_cpu_probe(const char *buf, size_t count)
if (rc)
return -EINVAL;
- rc = dlpar_cpu_add(drc_index);
+ rc = dlpar_cpu_add(drc_index, true);
return rc ? rc : count;
}
@@ -871,7 +881,7 @@ static ssize_t dlpar_cpu_release(const char *buf, size_t count)
return -EINVAL;
}
- rc = dlpar_cpu_remove(dn, drc_index);
+ rc = dlpar_cpu_remove(dn, drc_index, true);
of_node_put(dn);
return rc ? rc : count;
^ permalink raw reply related
* [RFC v9 0/4] powerpc/hotplug: Update affinity for migrated CPUs
From: Michael Bringmann @ 2018-06-03 20:03 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michael Bringmann, Nathan Fontenot, John Allen, Tyrel Datwyler,
Thomas Falcon
[Testing delayed due to internal SAN problems.]
The migration of LPARs across Power systems affects many attributes
including that of the associativity of CPUs. The patches in this
set execute when a system is coming up fresh upon a migration target.
They are intended to,
* Recognize changes to the associativity of CPUs recorded in internal
data structures when compared to the latest copies in the device tree.
* Generate calls to other code layers to reset the data structures
related to associativity of the CPUs.
* Re-register the 'changed' entities into the target system.
Re-registration of CPUs mostly entails acting as if they have been
newly hot-added into the target system.
Signed-off-by: Michael Bringmann <mwb@linux.vnet.ibm.com>
Michael Bringmann (4):
hotplug/cpu: Conditionally acquire/release DRC index
hotplug/cpu: Add operation queuing function
hotplug/dlpar/cpu: Provide CPU readd operation
mobility/numa: Ensure numa update does not overlap
---
Changes in RFC:
-- Restructure and rearrange content of patches to co-locate
similar or related modifications
-- Rename pseries_update_drconf_cpu to pseries_update_cpu
-- Simplify code to update CPU nodes during mobility checks.
Remove functions to generate extra HP_ELOG messages in favor
of direct function calls to dlpar_cpu_readd_by_index.
-- Revise code order in dlpar_cpu_readd_by_index() to present
more appropriate error codes from underlying layers of the
implementation.
-- Add hotplug device lock around all property updates
-- Schedule all CPU updates as workqueue operations
-- Rebase to 4.17-rc5 kernel
-- Various code cleanups and compaction
^ permalink raw reply
* linux-next: Signed-off-by missing for commit in the powerpc tree
From: Stephen Rothwell @ 2018-06-03 18:26 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, PowerPC
Cc: Linux-Next Mailing List, Linux Kernel Mailing List,
Michal Suchanek
[-- Attachment #1: Type: text/plain, Size: 184 bytes --]
Hi all,
Commit
cb3d6759a93c ("powerpc/64s: Enable barrier_nospec based on firmware settings")
is missing a Signed-off-by from its author.
--
Cheers,
Stephen Rothwell
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH] powerpc/perf: Remove sched_task function defined for thread-imc
From: Madhavan Srinivasan @ 2018-06-03 18:10 UTC (permalink / raw)
To: Anju T Sudhakar, mpe; +Cc: linuxppc-dev
In-Reply-To: <1526628925-31075-1-git-send-email-anju@linux.vnet.ibm.com>
On Friday 18 May 2018 01:05 PM, Anju T Sudhakar wrote:
> Call trace observed while running perf-fuzzer:
>
> [ 329.228068] CPU: 43 PID: 9088 Comm: perf_fuzzer Not tainted 4.13.0-32-generic #35~lp1746225
> [ 329.228070] task: c000003f776ac900 task.stack: c000003f77728000
> [ 329.228071] NIP: c000000000299b70 LR: c0000000002a4534 CTR: c00000000029bb80
> [ 329.228073] REGS: c000003f7772b760 TRAP: 0700 Not tainted (4.13.0-32-generic)
> [ 329.228073] MSR: 900000000282b033 <SF,HV,VEC,VSX,EE,FP,ME,IR,DR,RI,LE>
> [ 329.228079] CR: 24008822 XER: 00000000
> [ 329.228080] CFAR: c000000000299a70 SOFTE: 0
> GPR00: c0000000002a4534 c000003f7772b9e0 c000000001606200 c000003fef858908
> GPR04: c000003f776ac900 0000000000000001 ffffffffffffffff 0000003fee730000
> GPR08: 0000000000000000 0000000000000000 c0000000011220d8 0000000000000002
> GPR12: c00000000029bb80 c000000007a3d900 0000000000000000 0000000000000000
> GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
> GPR20: 0000000000000000 0000000000000000 c000003f776ad090 c000000000c71354
> GPR24: c000003fef716780 0000003fee730000 c000003fe69d4200 c000003f776ad330
> GPR28: c0000000011220d8 0000000000000001 c0000000014c6108 c000003fef858900
> [ 329.228098] NIP [c000000000299b70] perf_pmu_sched_task+0x170/0x180
> [ 329.228100] LR [c0000000002a4534] __perf_event_task_sched_in+0xc4/0x230
> [ 329.228101] Call Trace:
> [ 329.228102] [c000003f7772b9e0] [c0000000002a0678] perf_iterate_sb+0x158/0x2a0 (unreliable)
> [ 329.228105] [c000003f7772ba30] [c0000000002a4534] __perf_event_task_sched_in+0xc4/0x230
> [ 329.228107] [c000003f7772bab0] [c0000000001396dc] finish_task_switch+0x21c/0x310
> [ 329.228109] [c000003f7772bb60] [c000000000c71354] __schedule+0x304/0xb80
> [ 329.228111] [c000003f7772bc40] [c000000000c71c10] schedule+0x40/0xc0
> [ 329.228113] [c000003f7772bc60] [c0000000001033f4] do_wait+0x254/0x2e0
> [ 329.228115] [c000003f7772bcd0] [c000000000104ac0] kernel_wait4+0xa0/0x1a0
> [ 329.228117] [c000003f7772bd70] [c000000000104c24] SyS_wait4+0x64/0xc0
> [ 329.228121] [c000003f7772be30] [c00000000000b184] system_call+0x58/0x6c
> [ 329.228121] Instruction dump:
> [ 329.228123] 3beafea0 7faa4800 409eff18 e8010060 eb610028 ebc10040 7c0803a6 38210050
> [ 329.228127] eb81ffe0 eba1ffe8 ebe1fff8 4e800020 <0fe00000> 4bffffbc 60000000 60420000
> [ 329.228131] ---[ end trace 8c46856d314c1811 ]---
> [ 375.755943] hrtimer: interrupt took 31601 ns
>
>
> The context switch call-backs for thread-imc are defined in sched_task function.
> So when thread-imc events are grouped with software pmu events,
> perf_pmu_sched_task hits the WARN_ON_ONCE condition, since software PMUs are
> assumed not to have a sched_task defined.
>
> Patch to move the thread_imc enable/disable opal call back from sched_task to
> event_[add/del] function
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
>
> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
> ---
> arch/powerpc/perf/imc-pmu.c | 108 +++++++++++++++++++++-----------------------
> 1 file changed, 51 insertions(+), 57 deletions(-)
>
> diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c
> index d7532e7..71d9ba7 100644
> --- a/arch/powerpc/perf/imc-pmu.c
> +++ b/arch/powerpc/perf/imc-pmu.c
> @@ -866,59 +866,6 @@ static int thread_imc_cpu_init(void)
> ppc_thread_imc_cpu_offline);
> }
>
> -void thread_imc_pmu_sched_task(struct perf_event_context *ctx,
> - bool sched_in)
> -{
> - int core_id;
> - struct imc_pmu_ref *ref;
> -
> - if (!is_core_imc_mem_inited(smp_processor_id()))
> - return;
> -
> - core_id = smp_processor_id() / threads_per_core;
> - /*
> - * imc pmus are enabled only when it is used.
> - * See if this is triggered for the first time.
> - * If yes, take the mutex lock and enable the counters.
> - * If not, just increment the count in ref count struct.
> - */
> - ref = &core_imc_refc[core_id];
> - if (!ref)
> - return;
> -
> - if (sched_in) {
> - mutex_lock(&ref->lock);
> - if (ref->refc == 0) {
> - if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
> - get_hard_smp_processor_id(smp_processor_id()))) {
> - mutex_unlock(&ref->lock);
> - pr_err("thread-imc: Unable to start the counter\
> - for core %d\n", core_id);
> - return;
> - }
> - }
> - ++ref->refc;
> - mutex_unlock(&ref->lock);
> - } else {
> - mutex_lock(&ref->lock);
> - ref->refc--;
> - if (ref->refc == 0) {
> - if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
> - get_hard_smp_processor_id(smp_processor_id()))) {
> - mutex_unlock(&ref->lock);
> - pr_err("thread-imc: Unable to stop the counters\
> - for core %d\n", core_id);
> - return;
> - }
> - } else if (ref->refc < 0) {
> - ref->refc = 0;
> - }
> - mutex_unlock(&ref->lock);
> - }
> -
> - return;
> -}
> -
> static int thread_imc_event_init(struct perf_event *event)
> {
> u32 config = event->attr.config;
> @@ -1045,22 +992,70 @@ static int imc_event_add(struct perf_event *event, int flags)
>
> static int thread_imc_event_add(struct perf_event *event, int flags)
> {
> + int core_id;
> + struct imc_pmu_ref *ref;
> +
> if (flags & PERF_EF_START)
> imc_event_start(event, flags);
>
> - /* Enable the sched_task to start the engine */
> - perf_sched_cb_inc(event->ctx->pmu);
> + if (!is_core_imc_mem_inited(smp_processor_id()))
> + return -EINVAL;
> +
> + core_id = smp_processor_id() / threads_per_core;
> + /*
> + * imc pmus are enabled only when it is used.
> + * See if this is triggered for the first time.
> + * If yes, take the mutex lock and enable the counters.
> + * If not, just increment the count in ref count struct.
> + */
> + ref = &core_imc_refc[core_id];
> + if (!ref)
> + return -EINVAL;
> +
> + mutex_lock(&ref->lock);
> + if (ref->refc == 0) {
> + if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
> + get_hard_smp_processor_id(smp_processor_id()))) {
> + mutex_unlock(&ref->lock);
> + pr_err("thread-imc: Unable to start the counter\
> + for core %d\n", core_id);
> + return -EINVAL;
> + }
> + }
> + ++ref->refc;
> + mutex_unlock(&ref->lock);
> return 0;
> }
>
> static void thread_imc_event_del(struct perf_event *event, int flags)
> {
> +
> + int core_id;
> + struct imc_pmu_ref *ref;
> +
> /*
> * Take a snapshot and calculate the delta and update
> * the event counter values.
> */
> imc_event_update(event);
> - perf_sched_cb_dec(event->ctx->pmu);
> +
> + core_id = smp_processor_id() / threads_per_core;
> + ref = &core_imc_refc[core_id];
> +
> + mutex_lock(&ref->lock);
> + ref->refc--;
> + if (ref->refc == 0) {
> + if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
> + get_hard_smp_processor_id(smp_processor_id()))) {
> + mutex_unlock(&ref->lock);
> + pr_err("thread-imc: Unable to stop the counters\
> + for core %d\n", core_id);
> + return;
> + }
> + } else if (ref->refc < 0) {
> + ref->refc = 0;
> + }
> + mutex_unlock(&ref->lock);
> }
>
> /* update_pmu_ops : Populate the appropriate operations for "pmu" */
> @@ -1086,7 +1081,6 @@ static int update_pmu_ops(struct imc_pmu *pmu)
> break;
> case IMC_DOMAIN_THREAD:
> pmu->pmu.event_init = thread_imc_event_init;
> - pmu->pmu.sched_task = thread_imc_pmu_sched_task;
> pmu->pmu.add = thread_imc_event_add;
> pmu->pmu.del = thread_imc_event_del;
> pmu->pmu.start_txn = thread_imc_pmu_start_txn;
^ permalink raw reply
* [PATCH v2] powerpc/64s: make PACA_IRQ_HARD_DIS track MSR[EE] closely
From: Nicholas Piggin @ 2018-06-03 12:24 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin, Michael Ellerman
When the masked interrupt handler clears MSR[EE] for an interrupt in
the PACA_IRQ_MUST_HARD_MASK set, it does not set PACA_IRQ_HARD_DIS.
This makes them get out of synch.
With that taken into account, it's only low level irq manipulation
(and interrupt entry before reconcile) where they can be out of synch.
This makes the code less surprising.
It also allows the IRQ replay code to rely on the IRQ_HARD_DIS value
and not have to mtmsrd again in this case (e.g., for an external
interrupt that has been masked). The bigger benefit might just be
that there is not such an element of surprise in these two bits of
state.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Changes since v1:
- Several fixes for 64e exception and idle code.
- Bug: "ld r4,PACAIRQHAPPENED(r13)" should be lbz, resulted in random
hangs on booke.
arch/powerpc/include/asm/hw_irq.h | 10 ++++----
arch/powerpc/kernel/entry_64.S | 8 +++++++
arch/powerpc/kernel/exceptions-64e.S | 4 ++++
arch/powerpc/kernel/exceptions-64s.S | 5 +++-
arch/powerpc/kernel/idle_book3e.S | 7 +++++-
arch/powerpc/kernel/irq.c | 34 ++++++++++++++++++++--------
6 files changed, 52 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 855e17d158b1..8004d7887ff6 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -248,14 +248,16 @@ static inline bool lazy_irq_pending(void)
/*
* This is called by asynchronous interrupts to conditionally
- * re-enable hard interrupts when soft-disabled after having
- * cleared the source of the interrupt
+ * re-enable hard interrupts after having cleared the source
+ * of the interrupt. They are kept disabled if there is a different
+ * soft-masked interrupt pending that requires hard masking.
*/
static inline void may_hard_irq_enable(void)
{
- get_paca()->irq_happened &= ~PACA_IRQ_HARD_DIS;
- if (!(get_paca()->irq_happened & PACA_IRQ_MUST_HARD_MASK))
+ if (!(get_paca()->irq_happened & PACA_IRQ_MUST_HARD_MASK)) {
+ get_paca()->irq_happened &= ~PACA_IRQ_HARD_DIS;
__hard_irq_enable();
+ }
}
static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 51695608c68b..c5e3938f8e6f 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -973,6 +973,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
or r4,r4,r3
std r4,_TRAP(r1)
+ /*
+ * PACA_IRQ_HARD_DIS won't always be set here, so set it now
+ * to reconcile the IRQ state. Tracing is already accounted for.
+ */
+ lbz r4,PACAIRQHAPPENED(r13)
+ ori r4,r4,PACA_IRQ_HARD_DIS
+ stb r4,PACAIRQHAPPENED(r13)
+
/*
* Then find the right handler and call it. Interrupts are
* still soft-disabled and we keep them that way.
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 9b6e653e501a..3325f721e7b2 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -949,7 +949,11 @@ kernel_dbg_exc:
.macro masked_interrupt_book3e paca_irq full_mask
lbz r10,PACAIRQHAPPENED(r13)
+ .if \full_mask == 1
+ ori r10,r10,\paca_irq | PACA_IRQ_HARD_DIS
+ .else
ori r10,r10,\paca_irq
+ .endif
stb r10,PACAIRQHAPPENED(r13)
.if \full_mask == 1
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index ae6a849db60b..69172dd41b11 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1498,7 +1498,10 @@ masked_##_H##interrupt: \
mfspr r10,SPRN_##_H##SRR1; \
xori r10,r10,MSR_EE; /* clear MSR_EE */ \
mtspr SPRN_##_H##SRR1,r10; \
-2: mtcrf 0x80,r9; \
+ ori r11,r11,PACA_IRQ_HARD_DIS; \
+ stb r11,PACAIRQHAPPENED(r13); \
+2: /* done */ \
+ mtcrf 0x80,r9; \
ld r9,PACA_EXGEN+EX_R9(r13); \
ld r10,PACA_EXGEN+EX_R10(r13); \
ld r11,PACA_EXGEN+EX_R11(r13); \
diff --git a/arch/powerpc/kernel/idle_book3e.S b/arch/powerpc/kernel/idle_book3e.S
index 2b269315d377..4e0d94d02030 100644
--- a/arch/powerpc/kernel/idle_book3e.S
+++ b/arch/powerpc/kernel/idle_book3e.S
@@ -36,7 +36,7 @@ _GLOBAL(\name)
*/
lbz r3,PACAIRQHAPPENED(r13)
cmpwi cr0,r3,0
- bnelr
+ bne 2f
/* Now we are going to mark ourselves as soft and hard enabled in
* order to be able to take interrupts while asleep. We inform lockdep
@@ -72,6 +72,11 @@ _GLOBAL(\name)
wrteei 1
\loop
+2:
+ lbz r10,PACAIRQHAPPENED(r13)
+ ori r10,r10,PACA_IRQ_HARD_DIS
+ stb r10,PACAIRQHAPPENED(r13)
+ blr
.endm
.macro BOOK3E_IDLE_LOOP
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 061aa0f47bb1..50b6cbedf549 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -145,8 +145,20 @@ notrace unsigned int __check_irq_replay(void)
trace_hardirqs_on();
trace_hardirqs_off();
+ /*
+ * We are always hard disabled here, but PACA_IRQ_HARD_DIS may
+ * not be set, which means interrupts have only just been hard
+ * disabled as part of the local_irq_restore or interrupt return
+ * code. In that case, skip the decrementr check becaus it's
+ * expensive to read the TB.
+ *
+ * HARD_DIS then gets cleared here, but it's reconciled later.
+ * Either local_irq_disable will replay the interrupt and that
+ * will reconcile state like other hard interrupts. Or interrupt
+ * retur will replay the interrupt and in that case it sets
+ * PACA_IRQ_HARD_DIS by hand (see comments in entry_64.S).
+ */
if (happened & PACA_IRQ_HARD_DIS) {
- /* Clear bit 0 which we wouldn't clear otherwise */
local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
/*
@@ -248,24 +260,26 @@ notrace void arch_local_irq_restore(unsigned long mask)
* cannot have preempted.
*/
irq_happened = get_irq_happened();
- if (!irq_happened)
+ if (!irq_happened) {
+#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
+ WARN_ON(!(mfmsr() & MSR_EE));
+#endif
return;
+ }
/*
* We need to hard disable to get a trusted value from
* __check_irq_replay(). We also need to soft-disable
* again to avoid warnings in there due to the use of
* per-cpu variables.
- *
- * We know that if the value in irq_happened is exactly 0x01
- * then we are already hard disabled (there are other less
- * common cases that we'll ignore for now), so we skip the
- * (expensive) mtmsrd.
*/
- if (unlikely(irq_happened != PACA_IRQ_HARD_DIS))
+ if (!(irq_happened & PACA_IRQ_HARD_DIS)) {
+#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
+ WARN_ON(!(mfmsr() & MSR_EE));
+#endif
__hard_irq_disable();
#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
- else {
+ } else {
/*
* We should already be hard disabled here. We had bugs
* where that wasn't the case so let's dbl check it and
@@ -274,8 +288,8 @@ notrace void arch_local_irq_restore(unsigned long mask)
*/
if (WARN_ON(mfmsr() & MSR_EE))
__hard_irq_disable();
- }
#endif
+ }
irq_soft_mask_set(IRQS_ALL_DISABLED);
trace_hardirqs_off();
--
2.17.0
^ permalink raw reply related
* Re: powerpc/powernv: copy/paste - Mask XERS0 bit in CR
From: Michael Ellerman @ 2018-06-03 10:48 UTC (permalink / raw)
To: Haren Myneni; +Cc: linuxppc-dev, sukadev
In-Reply-To: <1527740956.5945.12.camel@hbabu-laptop>
Hi Haren,
Haren Myneni <haren@linux.vnet.ibm.com> writes:
>
> NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
> which is not related to paste request. The current paste function
> returns failure for the successful request when this bit is set.
> So mask this bit and check the proper return status.
>
> Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
> Cc: stable@vger.kernel.org # v4.14+
> Signed-off-by: Haren Myneni <haren@us.ibm.com>
>
> diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
> index c9a5036..82392e3 100644
> --- a/arch/powerpc/platforms/powernv/copy-paste.h
> +++ b/arch/powerpc/platforms/powernv/copy-paste.h
> @@ -9,7 +9,8 @@
> #include <asm/ppc-opcode.h>
>
> #define CR0_SHIFT 28
> -#define CR0_MASK 0xF
> +#define CR0_MASK 0xE /* 3rd bit undefined or set for XER[SO] */
> +
> /*
> * Copy/paste instructions:
> *
Unfortunately this no longer applies to my next branch, because those
macros have been moved out of this header as part of an unrelated patch.
The following patch should work instead, can you please confirm by
testing it?
diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
index 3fa62de96d9c..c46a326776cf 100644
--- a/arch/powerpc/platforms/powernv/copy-paste.h
+++ b/arch/powerpc/platforms/powernv/copy-paste.h
@@ -41,5 +41,7 @@ static inline int vas_paste(void *paste_address, int offset)
: "b" (offset), "b" (paste_address)
: "memory", "cr0");
- return (cr >> CR0_SHIFT) & CR0_MASK;
+
+ /* We mask with 0xE to ignore SO */
+ return (cr >> CR0_SHIFT) & 0xE;
}
cheers
^ permalink raw reply related
* Re: [PATCH stable 4.9 00/23] powerpc backports for 4.9
From: Michael Ellerman @ 2018-06-03 10:22 UTC (permalink / raw)
To: Greg KH; +Cc: stable, linuxppc-dev
In-Reply-To: <20180602133058.GA22989@kroah.com>
Greg KH <gregkh@linuxfoundation.org> writes:
> On Sat, Jun 02, 2018 at 09:08:45PM +1000, Michael Ellerman wrote:
>> Hi Greg,
>>
>> Please queue up this series of patches for 4.9 if you have no objections.
>>
>> The first one is not a backport but a fix for a previous backport.
>
> Looks good, all now queued up, thanks.
Thanks.
cheers
^ permalink raw reply
* Re: [PATCH 4.14 2/4] powerpc/mm/slice: create header files dedicated to slices
From: Greg Kroah-Hartman @ 2018-06-03 9:23 UTC (permalink / raw)
To: Christophe Leroy; +Cc: stable, linux-kernel, linuxppc-dev
In-Reply-To: <20180603092145.GA10556@kroah.com>
On Sun, Jun 03, 2018 at 11:21:45AM +0200, Greg Kroah-Hartman wrote:
> On Sat, Jun 02, 2018 at 10:55:31PM +0200, Christophe Leroy wrote:
> >
> >
> > On 06/02/2018 03:21 PM, Greg Kroah-Hartman wrote:
> > > On Thu, May 31, 2018 at 08:54:52AM +0000, Christophe Leroy wrote:
> > > > [ Upstream commit a3286f05bc5a5bc7fc73a9783ec89de78fcd07f8 ]
> > > >
> > > > In preparation for the following patch which will enhance 'slices'
> > > > for supporting PPC32 in order to fix an issue on hugepages on 8xx,
> > > > this patch takes out of page*.h all bits related to 'slices' and put
> > > > them into newly created slice.h header files.
> > > > While common parts go into asm/slice.h, subarch specific
> > > > parts go into respective books3s/64/slice.c and nohash/64/slice.c
> > > > 'slices'
> > > >
> > > > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> > > > Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> > > > Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
> > > > ---
> > > > arch/powerpc/include/asm/book3s/64/slice.h | 27 ++++++++++++++
> > > > arch/powerpc/include/asm/nohash/64/slice.h | 12 ++++++
> > > > arch/powerpc/include/asm/page.h | 1 +
> > > > arch/powerpc/include/asm/page_64.h | 59 ------------------------------
> > > > arch/powerpc/include/asm/slice.h | 40 ++++++++++++++++++++
> > > > 5 files changed, 80 insertions(+), 59 deletions(-)
> > > > create mode 100644 arch/powerpc/include/asm/book3s/64/slice.h
> > > > create mode 100644 arch/powerpc/include/asm/nohash/64/slice.h
> > > > create mode 100644 arch/powerpc/include/asm/slice.h
> > >
> > > This patch does not apply :(
> >
> > I tried again, it applies well for me:
> >
> > [root@localhost linux-stable]# git checkout v4.14.47 -b 4.14.47
> > Checking out files: 100% (27111/27111), done.
> > Switched to a new branch '4.14.47'
> > [root@localhost linux-stable]# git am /root/Downloads/4.14-1-4-powerpc-mm-slice-Remove-intermediate-bitmap-copy.patch
> >
> > Applying: powerpc/mm/slice: Remove intermediate bitmap copy
> > Applying: powerpc/mm/slice: create header files dedicated to slices
> > Applying: powerpc/mm/slice: Enhance for supporting PPC32
> > Applying: powerpc/mm/slice: Fix hugepage allocation at hint address on 8xx
> > [root@localhost linux-stable]#
> >
> > >
> > > Can you fix this series up and resend the whole thing?
> >
> > Is there any conflicting patch in the queue ?
> > What should I rebase on ?
>
> Ah, the problem is I was taking the upstream version of this patch, not
> your backported one. Next time be a bit more specific and say you
> changed something here, otherwise I will always default to what is in
> Linus's tree.
>
> Let me go work on this again...
Ok, that worked, all now queued up properly, sorry for the confusion.
greg k-h
^ permalink raw reply
* Re: [PATCH 4.14 2/4] powerpc/mm/slice: create header files dedicated to slices
From: Greg Kroah-Hartman @ 2018-06-03 9:21 UTC (permalink / raw)
To: Christophe Leroy; +Cc: stable, linux-kernel, linuxppc-dev
In-Reply-To: <f18dc860-6007-9955-8c73-25faf43097e8@c-s.fr>
On Sat, Jun 02, 2018 at 10:55:31PM +0200, Christophe Leroy wrote:
>
>
> On 06/02/2018 03:21 PM, Greg Kroah-Hartman wrote:
> > On Thu, May 31, 2018 at 08:54:52AM +0000, Christophe Leroy wrote:
> > > [ Upstream commit a3286f05bc5a5bc7fc73a9783ec89de78fcd07f8 ]
> > >
> > > In preparation for the following patch which will enhance 'slices'
> > > for supporting PPC32 in order to fix an issue on hugepages on 8xx,
> > > this patch takes out of page*.h all bits related to 'slices' and put
> > > them into newly created slice.h header files.
> > > While common parts go into asm/slice.h, subarch specific
> > > parts go into respective books3s/64/slice.c and nohash/64/slice.c
> > > 'slices'
> > >
> > > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> > > Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> > > Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
> > > ---
> > > arch/powerpc/include/asm/book3s/64/slice.h | 27 ++++++++++++++
> > > arch/powerpc/include/asm/nohash/64/slice.h | 12 ++++++
> > > arch/powerpc/include/asm/page.h | 1 +
> > > arch/powerpc/include/asm/page_64.h | 59 ------------------------------
> > > arch/powerpc/include/asm/slice.h | 40 ++++++++++++++++++++
> > > 5 files changed, 80 insertions(+), 59 deletions(-)
> > > create mode 100644 arch/powerpc/include/asm/book3s/64/slice.h
> > > create mode 100644 arch/powerpc/include/asm/nohash/64/slice.h
> > > create mode 100644 arch/powerpc/include/asm/slice.h
> >
> > This patch does not apply :(
>
> I tried again, it applies well for me:
>
> [root@localhost linux-stable]# git checkout v4.14.47 -b 4.14.47
> Checking out files: 100% (27111/27111), done.
> Switched to a new branch '4.14.47'
> [root@localhost linux-stable]# git am /root/Downloads/4.14-1-4-powerpc-mm-slice-Remove-intermediate-bitmap-copy.patch
>
> Applying: powerpc/mm/slice: Remove intermediate bitmap copy
> Applying: powerpc/mm/slice: create header files dedicated to slices
> Applying: powerpc/mm/slice: Enhance for supporting PPC32
> Applying: powerpc/mm/slice: Fix hugepage allocation at hint address on 8xx
> [root@localhost linux-stable]#
>
> >
> > Can you fix this series up and resend the whole thing?
>
> Is there any conflicting patch in the queue ?
> What should I rebase on ?
Ah, the problem is I was taking the upstream version of this patch, not
your backported one. Next time be a bit more specific and say you
changed something here, otherwise I will always default to what is in
Linus's tree.
Let me go work on this again...
thanks,
greg k-h
^ permalink raw reply
* Re: [PATCH 4.14 2/4] powerpc/mm/slice: create header files dedicated to slices
From: Christophe Leroy @ 2018-06-02 20:55 UTC (permalink / raw)
To: Greg Kroah-Hartman; +Cc: stable, linux-kernel, linuxppc-dev
In-Reply-To: <20180602132107.GH31493@kroah.com>
On 06/02/2018 03:21 PM, Greg Kroah-Hartman wrote:
> On Thu, May 31, 2018 at 08:54:52AM +0000, Christophe Leroy wrote:
>> [ Upstream commit a3286f05bc5a5bc7fc73a9783ec89de78fcd07f8 ]
>>
>> In preparation for the following patch which will enhance 'slices'
>> for supporting PPC32 in order to fix an issue on hugepages on 8xx,
>> this patch takes out of page*.h all bits related to 'slices' and put
>> them into newly created slice.h header files.
>> While common parts go into asm/slice.h, subarch specific
>> parts go into respective books3s/64/slice.c and nohash/64/slice.c
>> 'slices'
>>
>> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
>> Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
>> ---
>> arch/powerpc/include/asm/book3s/64/slice.h | 27 ++++++++++++++
>> arch/powerpc/include/asm/nohash/64/slice.h | 12 ++++++
>> arch/powerpc/include/asm/page.h | 1 +
>> arch/powerpc/include/asm/page_64.h | 59 ----------------------=
--------
>> arch/powerpc/include/asm/slice.h | 40 ++++++++++++++++++++
>> 5 files changed, 80 insertions(+), 59 deletions(-)
>> create mode 100644 arch/powerpc/include/asm/book3s/64/slice.h
>> create mode 100644 arch/powerpc/include/asm/nohash/64/slice.h
>> create mode 100644 arch/powerpc/include/asm/slice.h
>
> This patch does not apply :(
I tried again, it applies well for me:
[root@localhost linux-stable]# git checkout v4.14.47 -b 4.14.47
Checking out files: 100% (27111/27111), done.
Switched to a new branch '4.14.47'
[root@localhost linux-stable]# git am
/root/Downloads/4.14-1-4-powerpc-mm-slice-Remove-intermediate-bitmap-copy.p=
atch
Applying: powerpc/mm/slice: Remove intermediate bitmap copy
Applying: powerpc/mm/slice: create header files dedicated to slices
Applying: powerpc/mm/slice: Enhance for supporting PPC32
Applying: powerpc/mm/slice: Fix hugepage allocation at hint address on 8xx
[root@localhost linux-stable]#
>
> Can you fix this series up and resend the whole thing?
Is there any conflicting patch in the queue ?
What should I rebase on ?
Thanks,
Christophe
>
> thanks,
>
> greg k-h
>
---
L'absence de virus dans ce courrier =C3=A9lectronique a =C3=A9t=C3=A9 v=C3=
=A9rifi=C3=A9e par le logiciel antivirus Avast.
https://www.avast.com/antivirus
^ permalink raw reply
* Patch "powerpc/rfi-flush: Move the logic to avoid a redo into the debugfs code" has been added to the 4.9-stable tree
From: gregkh @ 2018-06-02 13:35 UTC (permalink / raw)
To: gregkh, linuxppc-dev, mauricfo, mpe; +Cc: stable-commits
In-Reply-To: <20180602110908.29773-5-mpe@ellerman.id.au>
This is a note to let you know that I've just added the patch titled
powerpc/rfi-flush: Move the logic to avoid a redo into the debugfs code
to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-rfi-flush-move-the-logic-to-avoid-a-redo-into-the-debugfs-code.patch
and it can be found in the queue-4.9 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From foo@baz Sat Jun 2 15:29:05 CEST 2018
From: Michael Ellerman <mpe@ellerman.id.au>
Date: Sat, 2 Jun 2018 21:08:49 +1000
Subject: powerpc/rfi-flush: Move the logic to avoid a redo into the debugfs code
To: gregkh@linuxfoundation.org
Cc: stable@vger.kernel.org, linuxppc-dev@ozlabs.org
Message-ID: <20180602110908.29773-5-mpe@ellerman.id.au>
From: Michael Ellerman <mpe@ellerman.id.au>
commit 1e2a9fc7496955faacbbed49461d611b704a7505 upstream.
rfi_flush_enable() includes a check to see if we're already
enabled (or disabled), and in that case does nothing.
But that means calling setup_rfi_flush() a 2nd time doesn't actually
work, which is a bit confusing.
Move that check into the debugfs code, where it really belongs.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Mauricio Faria de Oliveira <mauricfo@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/powerpc/kernel/setup_64.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -717,9 +717,6 @@ static void do_nothing(void *unused)
void rfi_flush_enable(bool enable)
{
- if (rfi_flush == enable)
- return;
-
if (enable) {
do_rfi_flush_fixups(enabled_flush_types);
on_each_cpu(do_nothing, NULL, 1);
@@ -773,13 +770,19 @@ void __init setup_rfi_flush(enum l1d_flu
#ifdef CONFIG_DEBUG_FS
static int rfi_flush_set(void *data, u64 val)
{
+ bool enable;
+
if (val == 1)
- rfi_flush_enable(true);
+ enable = true;
else if (val == 0)
- rfi_flush_enable(false);
+ enable = false;
else
return -EINVAL;
+ /* Only do anything if we're changing state */
+ if (enable != rfi_flush)
+ rfi_flush_enable(enable);
+
return 0;
}
Patches currently in stable-queue which might be from mpe@ellerman.id.au are
queue-4.9/powerpc-64s-clear-pcr-on-boot.patch
queue-4.9/powerpc-rfi-flush-differentiate-enabled-and-patched-flush-types.patch
queue-4.9/powerpc-64s-fix-section-mismatch-warnings-from-setup_rfi_flush.patch
queue-4.9/powerpc-pseries-fix-clearing-of-security-feature-flags.patch
queue-4.9/powerpc-powernv-set-or-clear-security-feature-flags.patch
queue-4.9/powerpc-64s-move-cpu_show_meltdown.patch
queue-4.9/powerpc-rfi-flush-call-setup_rfi_flush-after-lpm-migration.patch
queue-4.9/powerpc-pseries-set-or-clear-security-feature-flags.patch
queue-4.9/powerpc-rfi-flush-make-it-possible-to-call-setup_rfi_flush-again.patch
queue-4.9/powerpc-move-default-security-feature-flags.patch
queue-4.9/powerpc-powernv-use-the-security-flags-in-pnv_setup_rfi_flush.patch
queue-4.9/powerpc-add-security-feature-flags-for-spectre-meltdown.patch
queue-4.9/powerpc-pseries-use-the-security-flags-in-pseries_setup_rfi_flush.patch
queue-4.9/powerpc-64s-enhance-the-information-in-cpu_show_meltdown.patch
queue-4.9/powerpc-rfi-flush-move-out-of-hardlockup_detector-ifdef.patch
queue-4.9/powerpc-rfi-flush-always-enable-fallback-flush-on-pseries.patch
queue-4.9/powerpc-rfi-flush-move-the-logic-to-avoid-a-redo-into-the-debugfs-code.patch
queue-4.9/powerpc-pseries-restore-default-security-feature-flags-on-setup.patch
queue-4.9/powerpc-pseries-add-new-h_get_cpu_characteristics-flags.patch
queue-4.9/powerpc-64s-add-support-for-a-store-forwarding-barrier-at-kernel-entry-exit.patch
queue-4.9/powerpc-64s-wire-up-cpu_show_spectre_v1.patch
queue-4.9/powerpc-powernv-support-firmware-disable-of-rfi-flush.patch
queue-4.9/powerpc-pseries-support-firmware-disable-of-rfi-flush.patch
queue-4.9/powerpc-64s-wire-up-cpu_show_spectre_v2.patch
^ permalink raw reply
* Patch "powerpc/pseries: Use the security flags in pseries_setup_rfi_flush()" has been added to the 4.9-stable tree
From: gregkh @ 2018-06-02 13:35 UTC (permalink / raw)
To: gregkh, linuxppc-dev, mpe; +Cc: stable-commits
In-Reply-To: <20180602110908.29773-17-mpe@ellerman.id.au>
This is a note to let you know that I've just added the patch titled
powerpc/pseries: Use the security flags in pseries_setup_rfi_flush()
to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-pseries-use-the-security-flags-in-pseries_setup_rfi_flush.patch
and it can be found in the queue-4.9 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From foo@baz Sat Jun 2 15:29:05 CEST 2018
From: Michael Ellerman <mpe@ellerman.id.au>
Date: Sat, 2 Jun 2018 21:09:01 +1000
Subject: powerpc/pseries: Use the security flags in pseries_setup_rfi_flush()
To: gregkh@linuxfoundation.org
Cc: stable@vger.kernel.org, linuxppc-dev@ozlabs.org
Message-ID: <20180602110908.29773-17-mpe@ellerman.id.au>
From: Michael Ellerman <mpe@ellerman.id.au>
commit 2e4a16161fcd324b1f9bf6cb6856529f7eaf0689 upstream.
Now that we have the security flags we can simplify the code in
pseries_setup_rfi_flush() because the security flags have pessimistic
defaults.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/powerpc/platforms/pseries/setup.c | 27 ++++++++++++---------------
1 file changed, 12 insertions(+), 15 deletions(-)
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -492,30 +492,27 @@ void pseries_setup_rfi_flush(void)
bool enable;
long rc;
- /* Enable by default */
- enable = true;
- types = L1D_FLUSH_FALLBACK;
-
rc = plpar_get_cpu_characteristics(&result);
- if (rc == H_SUCCESS) {
+ if (rc == H_SUCCESS)
init_cpu_char_feature_flags(&result);
- if (result.character & H_CPU_CHAR_L1D_FLUSH_TRIG2)
- types |= L1D_FLUSH_MTTRIG;
- if (result.character & H_CPU_CHAR_L1D_FLUSH_ORI30)
- types |= L1D_FLUSH_ORI;
-
- if ((!(result.behaviour & H_CPU_BEHAV_L1D_FLUSH_PR)) ||
- (!(result.behaviour & H_CPU_BEHAV_FAVOUR_SECURITY)))
- enable = false;
- }
-
/*
* We're the guest so this doesn't apply to us, clear it to simplify
* handling of it elsewhere.
*/
security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
+ types = L1D_FLUSH_FALLBACK;
+
+ if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
+ types |= L1D_FLUSH_MTTRIG;
+
+ if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
+ types |= L1D_FLUSH_ORI;
+
+ enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
+ security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR);
+
setup_rfi_flush(types, enable);
}
Patches currently in stable-queue which might be from mpe@ellerman.id.au are
queue-4.9/powerpc-64s-clear-pcr-on-boot.patch
queue-4.9/powerpc-rfi-flush-differentiate-enabled-and-patched-flush-types.patch
queue-4.9/powerpc-64s-fix-section-mismatch-warnings-from-setup_rfi_flush.patch
queue-4.9/powerpc-pseries-fix-clearing-of-security-feature-flags.patch
queue-4.9/powerpc-powernv-set-or-clear-security-feature-flags.patch
queue-4.9/powerpc-64s-move-cpu_show_meltdown.patch
queue-4.9/powerpc-rfi-flush-call-setup_rfi_flush-after-lpm-migration.patch
queue-4.9/powerpc-pseries-set-or-clear-security-feature-flags.patch
queue-4.9/powerpc-rfi-flush-make-it-possible-to-call-setup_rfi_flush-again.patch
queue-4.9/powerpc-move-default-security-feature-flags.patch
queue-4.9/powerpc-powernv-use-the-security-flags-in-pnv_setup_rfi_flush.patch
queue-4.9/powerpc-add-security-feature-flags-for-spectre-meltdown.patch
queue-4.9/powerpc-pseries-use-the-security-flags-in-pseries_setup_rfi_flush.patch
queue-4.9/powerpc-64s-enhance-the-information-in-cpu_show_meltdown.patch
queue-4.9/powerpc-rfi-flush-move-out-of-hardlockup_detector-ifdef.patch
queue-4.9/powerpc-rfi-flush-always-enable-fallback-flush-on-pseries.patch
queue-4.9/powerpc-rfi-flush-move-the-logic-to-avoid-a-redo-into-the-debugfs-code.patch
queue-4.9/powerpc-pseries-restore-default-security-feature-flags-on-setup.patch
queue-4.9/powerpc-pseries-add-new-h_get_cpu_characteristics-flags.patch
queue-4.9/powerpc-64s-add-support-for-a-store-forwarding-barrier-at-kernel-entry-exit.patch
queue-4.9/powerpc-64s-wire-up-cpu_show_spectre_v1.patch
queue-4.9/powerpc-powernv-support-firmware-disable-of-rfi-flush.patch
queue-4.9/powerpc-pseries-support-firmware-disable-of-rfi-flush.patch
queue-4.9/powerpc-64s-wire-up-cpu_show_spectre_v2.patch
^ permalink raw reply
* Patch "powerpc/rfi-flush: Move out of HARDLOCKUP_DETECTOR #ifdef" has been added to the 4.9-stable tree
From: gregkh @ 2018-06-02 13:35 UTC (permalink / raw)
To: gregkh, linuxppc-dev, mpe; +Cc: stable-commits
In-Reply-To: <20180602110908.29773-2-mpe@ellerman.id.au>
This is a note to let you know that I've just added the patch titled
powerpc/rfi-flush: Move out of HARDLOCKUP_DETECTOR #ifdef
to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-rfi-flush-move-out-of-hardlockup_detector-ifdef.patch
and it can be found in the queue-4.9 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From foo@baz Sat Jun 2 15:29:05 CEST 2018
From: Michael Ellerman <mpe@ellerman.id.au>
Date: Sat, 2 Jun 2018 21:08:46 +1000
Subject: powerpc/rfi-flush: Move out of HARDLOCKUP_DETECTOR #ifdef
To: gregkh@linuxfoundation.org
Cc: stable@vger.kernel.org, linuxppc-dev@ozlabs.org
Message-ID: <20180602110908.29773-2-mpe@ellerman.id.au>
From: Michael Ellerman <mpe@ellerman.id.au>
The backport of the RFI flush support, done by me, has a minor bug in
that the code is inside an #ifdef CONFIG_HARDLOCKUP_DETECTOR, which is
incorrect.
This doesn't matter with common configs because we enable
HARDLOCKUP_DETECTOR, but with future patches it will break the build.
So fix it.
Fixes: c3b82ebee6e0 ("powerpc/64s: Add support for RFI flush of L1-D cache")
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/powerpc/kernel/setup_64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -679,6 +679,7 @@ static int __init disable_hardlockup_det
return 0;
}
early_initcall(disable_hardlockup_detector);
+#endif /* CONFIG_HARDLOCKUP_DETECTOR */
#ifdef CONFIG_PPC_BOOK3S_64
static enum l1d_flush_type enabled_flush_types;
@@ -806,4 +807,3 @@ ssize_t cpu_show_meltdown(struct device
return sprintf(buf, "Vulnerable\n");
}
#endif /* CONFIG_PPC_BOOK3S_64 */
-#endif
Patches currently in stable-queue which might be from mpe@ellerman.id.au are
queue-4.9/powerpc-64s-clear-pcr-on-boot.patch
queue-4.9/powerpc-rfi-flush-differentiate-enabled-and-patched-flush-types.patch
queue-4.9/powerpc-64s-fix-section-mismatch-warnings-from-setup_rfi_flush.patch
queue-4.9/powerpc-pseries-fix-clearing-of-security-feature-flags.patch
queue-4.9/powerpc-powernv-set-or-clear-security-feature-flags.patch
queue-4.9/powerpc-64s-move-cpu_show_meltdown.patch
queue-4.9/powerpc-rfi-flush-call-setup_rfi_flush-after-lpm-migration.patch
queue-4.9/powerpc-pseries-set-or-clear-security-feature-flags.patch
queue-4.9/powerpc-rfi-flush-make-it-possible-to-call-setup_rfi_flush-again.patch
queue-4.9/powerpc-move-default-security-feature-flags.patch
queue-4.9/powerpc-powernv-use-the-security-flags-in-pnv_setup_rfi_flush.patch
queue-4.9/powerpc-add-security-feature-flags-for-spectre-meltdown.patch
queue-4.9/powerpc-pseries-use-the-security-flags-in-pseries_setup_rfi_flush.patch
queue-4.9/powerpc-64s-enhance-the-information-in-cpu_show_meltdown.patch
queue-4.9/powerpc-rfi-flush-move-out-of-hardlockup_detector-ifdef.patch
queue-4.9/powerpc-rfi-flush-always-enable-fallback-flush-on-pseries.patch
queue-4.9/powerpc-rfi-flush-move-the-logic-to-avoid-a-redo-into-the-debugfs-code.patch
queue-4.9/powerpc-pseries-restore-default-security-feature-flags-on-setup.patch
queue-4.9/powerpc-pseries-add-new-h_get_cpu_characteristics-flags.patch
queue-4.9/powerpc-64s-add-support-for-a-store-forwarding-barrier-at-kernel-entry-exit.patch
queue-4.9/powerpc-64s-wire-up-cpu_show_spectre_v1.patch
queue-4.9/powerpc-powernv-support-firmware-disable-of-rfi-flush.patch
queue-4.9/powerpc-pseries-support-firmware-disable-of-rfi-flush.patch
queue-4.9/powerpc-64s-wire-up-cpu_show_spectre_v2.patch
^ permalink raw reply
* Patch "powerpc/rfi-flush: Make it possible to call setup_rfi_flush() again" has been added to the 4.9-stable tree
From: gregkh @ 2018-06-02 13:35 UTC (permalink / raw)
To: gregkh, linuxppc-dev, mauricfo, mpe; +Cc: stable-commits
In-Reply-To: <20180602110908.29773-6-mpe@ellerman.id.au>
This is a note to let you know that I've just added the patch titled
powerpc/rfi-flush: Make it possible to call setup_rfi_flush() again
to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-rfi-flush-make-it-possible-to-call-setup_rfi_flush-again.patch
and it can be found in the queue-4.9 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From foo@baz Sat Jun 2 15:29:05 CEST 2018
From: Michael Ellerman <mpe@ellerman.id.au>
Date: Sat, 2 Jun 2018 21:08:50 +1000
Subject: powerpc/rfi-flush: Make it possible to call setup_rfi_flush() again
To: gregkh@linuxfoundation.org
Cc: stable@vger.kernel.org, linuxppc-dev@ozlabs.org
Message-ID: <20180602110908.29773-6-mpe@ellerman.id.au>
From: Michael Ellerman <mpe@ellerman.id.au>
commit abf110f3e1cea40f5ea15e85f5d67c39c14568a7 upstream.
For PowerVM migration we want to be able to call setup_rfi_flush()
again after we've migrated the partition.
To support that we need to check that we're not trying to allocate the
fallback flush area after memblock has gone away (i.e., boot-time only).
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Mauricio Faria de Oliveira <mauricfo@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/powerpc/include/asm/setup.h | 2 +-
arch/powerpc/kernel/setup_64.c | 6 +++++-
2 files changed, 6 insertions(+), 2 deletions(-)
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -48,7 +48,7 @@ enum l1d_flush_type {
L1D_FLUSH_MTTRIG = 0x8,
};
-void __init setup_rfi_flush(enum l1d_flush_type, bool enable);
+void setup_rfi_flush(enum l1d_flush_type, bool enable);
void do_rfi_flush_fixups(enum l1d_flush_type types);
#endif /* !__ASSEMBLY__ */
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -731,6 +731,10 @@ static void init_fallback_flush(void)
u64 l1d_size, limit;
int cpu;
+ /* Only allocate the fallback flush area once (at boot time). */
+ if (l1d_flush_fallback_area)
+ return;
+
l1d_size = ppc64_caches.dsize;
limit = min(safe_stack_limit(), ppc64_rma_size);
@@ -748,7 +752,7 @@ static void init_fallback_flush(void)
}
}
-void __init setup_rfi_flush(enum l1d_flush_type types, bool enable)
+void setup_rfi_flush(enum l1d_flush_type types, bool enable)
{
if (types & L1D_FLUSH_FALLBACK) {
pr_info("rfi-flush: Using fallback displacement flush\n");
Patches currently in stable-queue which might be from mpe@ellerman.id.au are
queue-4.9/powerpc-64s-clear-pcr-on-boot.patch
queue-4.9/powerpc-rfi-flush-differentiate-enabled-and-patched-flush-types.patch
queue-4.9/powerpc-64s-fix-section-mismatch-warnings-from-setup_rfi_flush.patch
queue-4.9/powerpc-pseries-fix-clearing-of-security-feature-flags.patch
queue-4.9/powerpc-powernv-set-or-clear-security-feature-flags.patch
queue-4.9/powerpc-64s-move-cpu_show_meltdown.patch
queue-4.9/powerpc-rfi-flush-call-setup_rfi_flush-after-lpm-migration.patch
queue-4.9/powerpc-pseries-set-or-clear-security-feature-flags.patch
queue-4.9/powerpc-rfi-flush-make-it-possible-to-call-setup_rfi_flush-again.patch
queue-4.9/powerpc-move-default-security-feature-flags.patch
queue-4.9/powerpc-powernv-use-the-security-flags-in-pnv_setup_rfi_flush.patch
queue-4.9/powerpc-add-security-feature-flags-for-spectre-meltdown.patch
queue-4.9/powerpc-pseries-use-the-security-flags-in-pseries_setup_rfi_flush.patch
queue-4.9/powerpc-64s-enhance-the-information-in-cpu_show_meltdown.patch
queue-4.9/powerpc-rfi-flush-move-out-of-hardlockup_detector-ifdef.patch
queue-4.9/powerpc-rfi-flush-always-enable-fallback-flush-on-pseries.patch
queue-4.9/powerpc-rfi-flush-move-the-logic-to-avoid-a-redo-into-the-debugfs-code.patch
queue-4.9/powerpc-pseries-restore-default-security-feature-flags-on-setup.patch
queue-4.9/powerpc-pseries-add-new-h_get_cpu_characteristics-flags.patch
queue-4.9/powerpc-64s-add-support-for-a-store-forwarding-barrier-at-kernel-entry-exit.patch
queue-4.9/powerpc-64s-wire-up-cpu_show_spectre_v1.patch
queue-4.9/powerpc-powernv-support-firmware-disable-of-rfi-flush.patch
queue-4.9/powerpc-pseries-support-firmware-disable-of-rfi-flush.patch
queue-4.9/powerpc-64s-wire-up-cpu_show_spectre_v2.patch
^ permalink raw reply
* Patch "powerpc/rfi-flush: Differentiate enabled and patched flush types" has been added to the 4.9-stable tree
From: gregkh @ 2018-06-02 13:35 UTC (permalink / raw)
To: gregkh, linuxppc-dev, mauricfo, mpe; +Cc: stable-commits
In-Reply-To: <20180602110908.29773-8-mpe@ellerman.id.au>
This is a note to let you know that I've just added the patch titled
powerpc/rfi-flush: Differentiate enabled and patched flush types
to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-rfi-flush-differentiate-enabled-and-patched-flush-types.patch
and it can be found in the queue-4.9 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From foo@baz Sat Jun 2 15:29:05 CEST 2018
From: Michael Ellerman <mpe@ellerman.id.au>
Date: Sat, 2 Jun 2018 21:08:52 +1000
Subject: powerpc/rfi-flush: Differentiate enabled and patched flush types
To: gregkh@linuxfoundation.org
Cc: stable@vger.kernel.org, linuxppc-dev@ozlabs.org
Message-ID: <20180602110908.29773-8-mpe@ellerman.id.au>
From: Mauricio Faria de Oliveira <mauricfo@linux.vnet.ibm.com>
commit 0063d61ccfc011f379a31acaeba6de7c926fed2c upstream.
Currently the rfi-flush messages print 'Using <type> flush' for all
enabled_flush_types, but that is not necessarily true -- as now the
fallback flush is always enabled on pseries, but the fixup function
overwrites its nop/branch slot with other flush types, if available.
So, replace the 'Using <type> flush' messages with '<type> flush is
available'.
Also, print the patched flush types in the fixup function, so users
can know what is (not) being used (e.g., the slower, fallback flush,
or no flush type at all if flush is disabled via the debugfs switch).
Suggested-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Mauricio Faria de Oliveira <mauricfo@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/powerpc/kernel/setup_64.c | 6 +++---
arch/powerpc/lib/feature-fixups.c | 9 ++++++++-
2 files changed, 11 insertions(+), 4 deletions(-)
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -755,15 +755,15 @@ static void init_fallback_flush(void)
void setup_rfi_flush(enum l1d_flush_type types, bool enable)
{
if (types & L1D_FLUSH_FALLBACK) {
- pr_info("rfi-flush: Using fallback displacement flush\n");
+ pr_info("rfi-flush: fallback displacement flush available\n");
init_fallback_flush();
}
if (types & L1D_FLUSH_ORI)
- pr_info("rfi-flush: Using ori type flush\n");
+ pr_info("rfi-flush: ori type flush available\n");
if (types & L1D_FLUSH_MTTRIG)
- pr_info("rfi-flush: Using mttrig type flush\n");
+ pr_info("rfi-flush: mttrig type flush available\n");
enabled_flush_types = types;
--- a/arch/powerpc/lib/feature-fixups.c
+++ b/arch/powerpc/lib/feature-fixups.c
@@ -153,7 +153,14 @@ void do_rfi_flush_fixups(enum l1d_flush_
patch_instruction(dest + 2, instrs[2]);
}
- printk(KERN_DEBUG "rfi-flush: patched %d locations\n", i);
+ printk(KERN_DEBUG "rfi-flush: patched %d locations (%s flush)\n", i,
+ (types == L1D_FLUSH_NONE) ? "no" :
+ (types == L1D_FLUSH_FALLBACK) ? "fallback displacement" :
+ (types & L1D_FLUSH_ORI) ? (types & L1D_FLUSH_MTTRIG)
+ ? "ori+mttrig type"
+ : "ori type" :
+ (types & L1D_FLUSH_MTTRIG) ? "mttrig type"
+ : "unknown");
}
#endif /* CONFIG_PPC_BOOK3S_64 */
Patches currently in stable-queue which might be from mpe@ellerman.id.au are
queue-4.9/powerpc-64s-clear-pcr-on-boot.patch
queue-4.9/powerpc-rfi-flush-differentiate-enabled-and-patched-flush-types.patch
queue-4.9/powerpc-64s-fix-section-mismatch-warnings-from-setup_rfi_flush.patch
queue-4.9/powerpc-pseries-fix-clearing-of-security-feature-flags.patch
queue-4.9/powerpc-powernv-set-or-clear-security-feature-flags.patch
queue-4.9/powerpc-64s-move-cpu_show_meltdown.patch
queue-4.9/powerpc-rfi-flush-call-setup_rfi_flush-after-lpm-migration.patch
queue-4.9/powerpc-pseries-set-or-clear-security-feature-flags.patch
queue-4.9/powerpc-rfi-flush-make-it-possible-to-call-setup_rfi_flush-again.patch
queue-4.9/powerpc-move-default-security-feature-flags.patch
queue-4.9/powerpc-powernv-use-the-security-flags-in-pnv_setup_rfi_flush.patch
queue-4.9/powerpc-add-security-feature-flags-for-spectre-meltdown.patch
queue-4.9/powerpc-pseries-use-the-security-flags-in-pseries_setup_rfi_flush.patch
queue-4.9/powerpc-64s-enhance-the-information-in-cpu_show_meltdown.patch
queue-4.9/powerpc-rfi-flush-move-out-of-hardlockup_detector-ifdef.patch
queue-4.9/powerpc-rfi-flush-always-enable-fallback-flush-on-pseries.patch
queue-4.9/powerpc-rfi-flush-move-the-logic-to-avoid-a-redo-into-the-debugfs-code.patch
queue-4.9/powerpc-pseries-restore-default-security-feature-flags-on-setup.patch
queue-4.9/powerpc-pseries-add-new-h_get_cpu_characteristics-flags.patch
queue-4.9/powerpc-64s-add-support-for-a-store-forwarding-barrier-at-kernel-entry-exit.patch
queue-4.9/powerpc-64s-wire-up-cpu_show_spectre_v1.patch
queue-4.9/powerpc-powernv-support-firmware-disable-of-rfi-flush.patch
queue-4.9/powerpc-pseries-support-firmware-disable-of-rfi-flush.patch
queue-4.9/powerpc-64s-wire-up-cpu_show_spectre_v2.patch
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