* [PATCH 08/10] ASoC: dt-bindings: Document fcomb_mode property
From: Daniel Baluta @ 2019-07-22 12:48 UTC (permalink / raw)
To: broonie
Cc: Daniel Baluta, alsa-devel, viorel.suman, timur, Xiubo.Lee,
linuxppc-dev, shengjiu.wang, angus, tiwai, perex, nicoleotsuka,
linux-imx, kernel, festevam, linux-kernel, l.stach
In-Reply-To: <20190722124833.28757-1-daniel.baluta@nxp.com>
This allows combining multiple-data-line FIFOs into a
single-data-line FIFO.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
Documentation/devicetree/bindings/sound/fsl-sai.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index 59f4d965a5fb..ca27afd840ba 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -54,6 +54,10 @@ Optional properties:
represents first data line, bit 1 represents second
data line and so on. Data line is enabled if
corresponding bit is set to 1.
+ - fsl,fcomb_mode : list of two integers (first for RX, second for TX)
+ representing FIFO combine mode. Possible values for
+ combined mode are: 0 - disabled, 1 - Rx/Tx from shift
+ registers, 2 - Rx/Tx by software, 3 - both.
Optional properties (for mx6ul):
--
2.17.1
^ permalink raw reply related
* [PATCH 00/10] Add support for new SAI IP version
From: Daniel Baluta @ 2019-07-22 12:48 UTC (permalink / raw)
To: broonie
Cc: Daniel Baluta, alsa-devel, viorel.suman, timur, Xiubo.Lee,
linuxppc-dev, shengjiu.wang, angus, tiwai, perex, nicoleotsuka,
linux-imx, kernel, festevam, linux-kernel, l.stach
So far SAI IPs integrated with imx6 only supported one data line.
Starting with imx7 and imx8 SAI integration support up to 8 data
lines and multiple ways of combining the fifos for each data line.
New SAI IP version introduces two new registers (Version and Parmeter
registers) which are placed at the beginning of register address space.
For this reason we need to fix the register's address.
Patches 1 and 2 from Lucas enhance per SOC handling of SAI properties.
Patches 3,4,5,6,7,8 allow SAI driver to read active data lines and
fifo combine mode from DT.
Patch 9 fixes new SAI register address space.
Patch 10 enable SAI for imx7ulp and imx8mq.
This patch introduces
Daniel Baluta (8):
ASoC: fsl_sai: Add registers definition for multiple datalines
ASoC: fsl_sai: Update Tx/Rx channel enable mask
ASoC: fsl_sai: Add support to enable multiple data lines
ASoC: dt-bindings: Document dl_mask property
ASoC: fsl_sai: Add support for FIFO combine mode
ASoC: dt-bindings: Document fcomb_mode property
ASoC: fsl_sai: Add support for SAI new version
ASoC: fsl_sai: Add support for imx7ulp/imx8mq
Lucas Stach (2):
ASoC: fsl_sai: add of_match data
ASoC: fsl_sai: derive TX FIFO watermark from FIFO depth
.../devicetree/bindings/sound/fsl-sai.txt | 9 +
sound/soc/fsl/fsl_sai.c | 393 +++++++++++++-----
sound/soc/fsl/fsl_sai.h | 98 +++--
3 files changed, 361 insertions(+), 139 deletions(-)
--
2.17.1
^ permalink raw reply
* [PATCH 03/10] ASoC: fsl_sai: Add registers definition for multiple datalines
From: Daniel Baluta @ 2019-07-22 12:48 UTC (permalink / raw)
To: broonie
Cc: Daniel Baluta, alsa-devel, viorel.suman, timur, Xiubo.Lee,
linuxppc-dev, shengjiu.wang, angus, tiwai, perex, nicoleotsuka,
linux-imx, kernel, festevam, linux-kernel, l.stach
In-Reply-To: <20190722124833.28757-1-daniel.baluta@nxp.com>
SAI IP supports up to 8 data lines. The configuration of
supported number of data lines is decided at SoC integration
time.
This patch adds definitions for all related data TX/RX registers:
* TDR0..7, Transmit data register
* TFR0..7, Transmit FIFO register
* RDR0..7, Receive data register
* RFR0..7, Receive FIFO register
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
sound/soc/fsl/fsl_sai.c | 76 +++++++++++++++++++++++++++++++++++------
sound/soc/fsl/fsl_sai.h | 36 ++++++++++++++++---
2 files changed, 98 insertions(+), 14 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 1d1a447163e3..7f8823fe4b90 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -685,7 +685,14 @@ static struct reg_default fsl_sai_reg_defaults[] = {
{FSL_SAI_TCR3, 0},
{FSL_SAI_TCR4, 0},
{FSL_SAI_TCR5, 0},
- {FSL_SAI_TDR, 0},
+ {FSL_SAI_TDR0, 0},
+ {FSL_SAI_TDR1, 0},
+ {FSL_SAI_TDR2, 0},
+ {FSL_SAI_TDR3, 0},
+ {FSL_SAI_TDR4, 0},
+ {FSL_SAI_TDR5, 0},
+ {FSL_SAI_TDR6, 0},
+ {FSL_SAI_TDR7, 0},
{FSL_SAI_TMR, 0},
{FSL_SAI_RCR1, 0},
{FSL_SAI_RCR2, 0},
@@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
case FSL_SAI_TCR3:
case FSL_SAI_TCR4:
case FSL_SAI_TCR5:
- case FSL_SAI_TFR:
+ case FSL_SAI_TFR0:
+ case FSL_SAI_TFR1:
+ case FSL_SAI_TFR2:
+ case FSL_SAI_TFR3:
+ case FSL_SAI_TFR4:
+ case FSL_SAI_TFR5:
+ case FSL_SAI_TFR6:
+ case FSL_SAI_TFR7:
case FSL_SAI_TMR:
case FSL_SAI_RCSR:
case FSL_SAI_RCR1:
@@ -712,8 +726,22 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
case FSL_SAI_RCR3:
case FSL_SAI_RCR4:
case FSL_SAI_RCR5:
- case FSL_SAI_RDR:
- case FSL_SAI_RFR:
+ case FSL_SAI_RDR0:
+ case FSL_SAI_RDR1:
+ case FSL_SAI_RDR2:
+ case FSL_SAI_RDR3:
+ case FSL_SAI_RDR4:
+ case FSL_SAI_RDR5:
+ case FSL_SAI_RDR6:
+ case FSL_SAI_RDR7:
+ case FSL_SAI_RFR0:
+ case FSL_SAI_RFR1:
+ case FSL_SAI_RFR2:
+ case FSL_SAI_RFR3:
+ case FSL_SAI_RFR4:
+ case FSL_SAI_RFR5:
+ case FSL_SAI_RFR6:
+ case FSL_SAI_RFR7:
case FSL_SAI_RMR:
return true;
default:
@@ -726,9 +754,30 @@ static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
switch (reg) {
case FSL_SAI_TCSR:
case FSL_SAI_RCSR:
- case FSL_SAI_TFR:
- case FSL_SAI_RFR:
- case FSL_SAI_RDR:
+ case FSL_SAI_TFR0:
+ case FSL_SAI_TFR1:
+ case FSL_SAI_TFR2:
+ case FSL_SAI_TFR3:
+ case FSL_SAI_TFR4:
+ case FSL_SAI_TFR5:
+ case FSL_SAI_TFR6:
+ case FSL_SAI_TFR7:
+ case FSL_SAI_RFR0:
+ case FSL_SAI_RFR1:
+ case FSL_SAI_RFR2:
+ case FSL_SAI_RFR3:
+ case FSL_SAI_RFR4:
+ case FSL_SAI_RFR5:
+ case FSL_SAI_RFR6:
+ case FSL_SAI_RFR7:
+ case FSL_SAI_RDR0:
+ case FSL_SAI_RDR1:
+ case FSL_SAI_RDR2:
+ case FSL_SAI_RDR3:
+ case FSL_SAI_RDR4:
+ case FSL_SAI_RDR5:
+ case FSL_SAI_RDR6:
+ case FSL_SAI_RDR7:
return true;
default:
return false;
@@ -744,7 +793,14 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
case FSL_SAI_TCR3:
case FSL_SAI_TCR4:
case FSL_SAI_TCR5:
- case FSL_SAI_TDR:
+ case FSL_SAI_TDR0:
+ case FSL_SAI_TDR1:
+ case FSL_SAI_TDR2:
+ case FSL_SAI_TDR3:
+ case FSL_SAI_TDR4:
+ case FSL_SAI_TDR5:
+ case FSL_SAI_TDR6:
+ case FSL_SAI_TDR7:
case FSL_SAI_TMR:
case FSL_SAI_RCSR:
case FSL_SAI_RCR1:
@@ -884,8 +940,8 @@ static int fsl_sai_probe(struct platform_device *pdev)
MCLK_DIR(index));
}
- sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
- sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
+ sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
+ sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 7c1ef671da28..4bb478041d67 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -20,8 +20,22 @@
#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */
#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */
#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */
-#define FSL_SAI_TDR 0x20 /* SAI Transmit Data */
-#define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */
+#define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */
+#define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */
+#define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */
+#define FSL_SAI_TDR3 0x2C /* SAI Transmit Data 3 */
+#define FSL_SAI_TDR4 0x30 /* SAI Transmit Data 4 */
+#define FSL_SAI_TDR5 0x34 /* SAI Transmit Data 5 */
+#define FSL_SAI_TDR6 0x38 /* SAI Transmit Data 6 */
+#define FSL_SAI_TDR7 0x3C /* SAI Transmit Data 7 */
+#define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO 0 */
+#define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO 1 */
+#define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO 2 */
+#define FSL_SAI_TFR3 0x4C /* SAI Transmit FIFO 3 */
+#define FSL_SAI_TFR4 0x50 /* SAI Transmit FIFO 4 */
+#define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO 5 */
+#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */
+#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */
#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */
#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */
@@ -29,8 +43,22 @@
#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */
#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */
#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */
-#define FSL_SAI_RDR 0xa0 /* SAI Receive Data */
-#define FSL_SAI_RFR 0xc0 /* SAI Receive FIFO */
+#define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
+#define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
+#define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
+#define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */
+#define FSL_SAI_RDR4 0xb0 /* SAI Receive Data 4 */
+#define FSL_SAI_RDR5 0xb4 /* SAI Receive Data 5 */
+#define FSL_SAI_RDR6 0xb8 /* SAI Receive Data 6 */
+#define FSL_SAI_RDR7 0xbc /* SAI Receive Data 7 */
+#define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO 0 */
+#define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO 1 */
+#define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO 2 */
+#define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO 3 */
+#define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO 4 */
+#define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO 5 */
+#define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */
+#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)
--
2.17.1
^ permalink raw reply related
* [PATCH 06/10] ASoC: dt-bindings: Document dl_mask property
From: Daniel Baluta @ 2019-07-22 12:48 UTC (permalink / raw)
To: broonie
Cc: Daniel Baluta, alsa-devel, viorel.suman, timur, Xiubo.Lee,
linuxppc-dev, shengjiu.wang, angus, tiwai, perex, nicoleotsuka,
linux-imx, kernel, festevam, linux-kernel, l.stach
In-Reply-To: <20190722124833.28757-1-daniel.baluta@nxp.com>
SAI supports up to 8 data lines. This property let the user
configure how many data lines should be used per transfer
direction (Tx/Rx).
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
Documentation/devicetree/bindings/sound/fsl-sai.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index 2e726b983845..59f4d965a5fb 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -49,6 +49,11 @@ Optional properties:
- big-endian : Boolean property, required if all the SAI
registers are big-endian rather than little-endian.
+ - fsl,dl_mask : list of two integers (bitmask, first for RX, second
+ for TX) representing enabled datalines. Bit 0
+ represents first data line, bit 1 represents second
+ data line and so on. Data line is enabled if
+ corresponding bit is set to 1.
Optional properties (for mx6ul):
--
2.17.1
^ permalink raw reply related
* [PATCH 05/10] ASoC: fsl_sai: Add support to enable multiple data lines
From: Daniel Baluta @ 2019-07-22 12:48 UTC (permalink / raw)
To: broonie
Cc: Daniel Baluta, alsa-devel, viorel.suman, timur, Xiubo.Lee,
linuxppc-dev, shengjiu.wang, angus, tiwai, perex, nicoleotsuka,
linux-imx, kernel, festevam, linux-kernel, l.stach
In-Reply-To: <20190722124833.28757-1-daniel.baluta@nxp.com>
SAI supports up to 8 Rx/Tx data lines which can be enabled
using TCE/RCE bits of TCR3/RCR3 registers.
Data lines to be enabled are read from DT fsl,dl_mask property.
By default (if no DT entry is provided) only data line 0 is enabled.
Note:
We can only enable consecutive data lines starting with data line #0.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
sound/soc/fsl/fsl_sai.c | 10 +++++++++-
sound/soc/fsl/fsl_sai.h | 6 ++++--
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 768341608695..d0fa02188b7c 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -601,7 +601,7 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
FSL_SAI_CR3_TRCE_MASK,
- FSL_SAI_CR3_TRCE);
+ FSL_SAI_CR3_TRCE(sai->soc_data->dl_mask[tx]);
ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
@@ -887,6 +887,14 @@ static int fsl_sai_probe(struct platform_device *pdev)
}
}
+ /* active data lines mask for TX/RX, defaults to 1 (only the first
+ * data line is enabled
+ */
+ sai->dl_mask[RX] = 1;
+ sai->dl_mask[TX] = 1;
+ of_property_read_u32_index(np, "fsl,dl_mask", RX, &sai->dl_mask[RX]);
+ of_property_read_u32_index(np, "fsl,dl_mask", TX, &sai->dl_mask[TX]);
+
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index b1abeed2f78e..6d32f0950ec5 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -109,8 +109,8 @@
#define FSL_SAI_CR2_DIV_MASK 0xff
/* SAI Transmit and Receive Configuration 3 Register */
-#define FSL_SAI_CR3_TRCE BIT(16)
-#define FSL_SAI_CR3_TRCE_MASK GENMASK(16, 23)
+#define FSL_SAI_CR3_TRCE(x) ((x) << 16)
+#define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16)
#define FSL_SAI_CR3_WDFL(x) (x)
#define FSL_SAI_CR3_WDFL_MASK 0x1f
@@ -176,6 +176,8 @@ struct fsl_sai {
unsigned int slots;
unsigned int slot_width;
+ unsigned int dl_mask[2];
+
const struct fsl_sai_soc_data *soc_data;
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct snd_dmaengine_dai_dma_data dma_params_tx;
--
2.17.1
^ permalink raw reply related
* Applied "ASoC: fsl_esai: Wrap some operations to be functions" to the asoc tree
From: Mark Brown @ 2019-07-22 12:22 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, timur, Xiubo.Lee, festevam, tiwai, lgirdwood,
linux-kernel, Nicolin Chen, Mark Brown, perex, linuxppc-dev
In-Reply-To: <804d7e75ae7e06a913479912b578b3538ca7cd3f.1562842206.git.shengjiu.wang@nxp.com>
The patch
ASoC: fsl_esai: Wrap some operations to be functions
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.4
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
From 5be6155b50bbf7083b4bfa219e4ce6d1491f42f0 Mon Sep 17 00:00:00 2001
From: Shengjiu Wang <shengjiu.wang@nxp.com>
Date: Thu, 11 Jul 2019 18:49:45 +0800
Subject: [PATCH] ASoC: fsl_esai: Wrap some operations to be functions
Extract the operation to be functions, to improve the
readability.
In this patch, fsl_esai_hw_init, fsl_esai_register_restore,
fsl_esai_trigger_start and fsl_esai_trigger_stop are
extracted.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/804d7e75ae7e06a913479912b578b3538ca7cd3f.1562842206.git.shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
sound/soc/fsl/fsl_esai.c | 188 ++++++++++++++++++++++++---------------
1 file changed, 117 insertions(+), 71 deletions(-)
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index 10d2210c91ef..ab460d6d7432 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -35,6 +35,7 @@
* @fifo_depth: depth of tx/rx FIFO
* @slot_width: width of each DAI slot
* @slots: number of slots
+ * @channels: channel num for tx or rx
* @hck_rate: clock rate of desired HCKx clock
* @sck_rate: clock rate of desired SCKx clock
* @hck_dir: the direction of HCKx pads
@@ -57,6 +58,7 @@ struct fsl_esai {
u32 slots;
u32 tx_mask;
u32 rx_mask;
+ u32 channels[2];
u32 hck_rate[2];
u32 sck_rate[2];
bool hck_dir[2];
@@ -543,64 +545,132 @@ static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
return 0;
}
+static int fsl_esai_hw_init(struct fsl_esai *esai_priv)
+{
+ struct platform_device *pdev = esai_priv->pdev;
+ int ret;
+
+ /* Reset ESAI unit */
+ ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
+ ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
+ ESAI_ECR_ESAIEN | ESAI_ECR_ERST);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * We need to enable ESAI so as to access some of its registers.
+ * Otherwise, we would fail to dump regmap from user space.
+ */
+ ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
+ ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
+ ESAI_ECR_ESAIEN);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
+ return ret;
+ }
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
+ ESAI_PRRC_PDC_MASK, 0);
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
+ ESAI_PCRC_PC_MASK, 0);
+
+ return 0;
+}
+
+static int fsl_esai_register_restore(struct fsl_esai *esai_priv)
+{
+ int ret;
+
+ /* FIFO reset for safety */
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR,
+ ESAI_xFCR_xFR, ESAI_xFCR_xFR);
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR,
+ ESAI_xFCR_xFR, ESAI_xFCR_xFR);
+
+ regcache_mark_dirty(esai_priv->regmap);
+ ret = regcache_sync(esai_priv->regmap);
+ if (ret)
+ return ret;
+
+ /* FIFO reset done */
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
+
+ return 0;
+}
+
+static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx)
+{
+ u8 i, channels = esai_priv->channels[tx];
+ u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
+ u32 mask;
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
+ ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
+
+ /* Write initial words reqiured by ESAI as normal procedure */
+ for (i = 0; tx && i < channels; i++)
+ regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
+
+ /*
+ * When set the TE/RE in the end of enablement flow, there
+ * will be channel swap issue for multi data line case.
+ * In order to workaround this issue, we switch the bit
+ * enablement sequence to below sequence
+ * 1) clear the xSMB & xSMA: which is done in probe and
+ * stop state.
+ * 2) set TE/RE
+ * 3) set xSMB
+ * 4) set xSMA: xSMA is the last one in this flow, which
+ * will trigger esai to start.
+ */
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
+ tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
+ tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
+ mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
+ ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
+ ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
+}
+
+static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx)
+{
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
+ tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
+ ESAI_xSMA_xS_MASK, 0);
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
+ ESAI_xSMB_xS_MASK, 0);
+
+ /* Disable and reset FIFO */
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
+ ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
+ ESAI_xFCR_xFR, 0);
+}
+
static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
- u8 i, channels = substream->runtime->channels;
- u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
- u32 mask;
+
+ esai_priv->channels[tx] = substream->runtime->channels;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
- regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
- ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
-
- /* Write initial words reqiured by ESAI as normal procedure */
- for (i = 0; tx && i < channels; i++)
- regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
-
- /*
- * When set the TE/RE in the end of enablement flow, there
- * will be channel swap issue for multi data line case.
- * In order to workaround this issue, we switch the bit
- * enablement sequence to below sequence
- * 1) clear the xSMB & xSMA: which is done in probe and
- * stop state.
- * 2) set TE/RE
- * 3) set xSMB
- * 4) set xSMA: xSMA is the last one in this flow, which
- * will trigger esai to start.
- */
- regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
- tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
- tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
- mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
-
- regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
- ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
- regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
- ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
-
+ fsl_esai_trigger_start(esai_priv, tx);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
- regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
- tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
- regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
- ESAI_xSMA_xS_MASK, 0);
- regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
- ESAI_xSMB_xS_MASK, 0);
-
- /* Disable and reset FIFO */
- regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
- ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
- regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
- ESAI_xFCR_xFR, 0);
+ fsl_esai_trigger_stop(esai_priv, tx);
break;
default:
return -EINVAL;
@@ -866,22 +936,9 @@ static int fsl_esai_probe(struct platform_device *pdev)
dev_set_drvdata(&pdev->dev, esai_priv);
- /* Reset ESAI unit */
- ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
- if (ret) {
- dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
- return ret;
- }
-
- /*
- * We need to enable ESAI so as to access some of its registers.
- * Otherwise, we would fail to dump regmap from user space.
- */
- ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
- if (ret) {
- dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
+ ret = fsl_esai_hw_init(esai_priv);
+ if (ret)
return ret;
- }
esai_priv->tx_mask = 0xFFFFFFFF;
esai_priv->rx_mask = 0xFFFFFFFF;
@@ -955,20 +1012,10 @@ static int fsl_esai_runtime_resume(struct device *dev)
regcache_cache_only(esai->regmap, false);
- /* FIFO reset for safety */
- regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
- ESAI_xFCR_xFR, ESAI_xFCR_xFR);
- regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
- ESAI_xFCR_xFR, ESAI_xFCR_xFR);
-
- ret = regcache_sync(esai->regmap);
+ ret = fsl_esai_register_restore(esai);
if (ret)
goto err_regcache_sync;
- /* FIFO reset done */
- regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
- regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
-
return 0;
err_regcache_sync:
@@ -991,7 +1038,6 @@ static int fsl_esai_runtime_suspend(struct device *dev)
struct fsl_esai *esai = dev_get_drvdata(dev);
regcache_cache_only(esai->regmap, true);
- regcache_mark_dirty(esai->regmap);
if (!IS_ERR(esai->fsysclk))
clk_disable_unprepare(esai->fsysclk);
--
2.20.1
^ permalink raw reply related
* Re: [PATCH] powerpc/dma: Fix invalid DMA mmap behavior
From: Michael Ellerman @ 2019-07-22 12:16 UTC (permalink / raw)
To: Arnd Bergmann, Christoph Hellwig
Cc: Shawn Anastasio, Alexey Kardashevskiy, Sam Bobroff,
open list:IOMMU DRIVERS, Oliver O'Halloran, linuxppc-dev,
Marek Szyprowski
In-Reply-To: <CAK8P3a1ChtE10D=enp_a+isBCGgRW1nX6-0jChuAvTcUAWECBg@mail.gmail.com>
Arnd Bergmann <arnd@arndb.de> writes:
> On Thu, Jul 18, 2019 at 11:52 AM Christoph Hellwig <hch@lst.de> wrote:
>> On Thu, Jul 18, 2019 at 10:49:34AM +0200, Christoph Hellwig wrote:
>> > On Thu, Jul 18, 2019 at 01:45:16PM +1000, Oliver O'Halloran wrote:
>> > > > Other than m68k, mips, and arm64, everybody else that doesn't have
>> > > > ARCH_NO_COHERENT_DMA_MMAP set uses this default implementation, so
>> > > > I assume this behavior is acceptable on those architectures.
>> > >
>> > > It might be acceptable, but there's no reason to use pgport_noncached
>> > > if the platform supports cache-coherent DMA.
>> > >
>> > > Christoph (+cc) made the change so maybe he saw something we're missing.
>> >
>> > I always found the forcing of noncached access even for coherent
>> > devices a little odd, but this was inherited from the previous
>> > implementation, which surprised me a bit as the different attributes
>> > are usually problematic even on x86. Let me dig into the history a
>> > bit more, but I suspect the righ fix is to default to cached mappings
>> > for coherent devices.
>>
>> Ok, some history:
>>
>> The generic dma mmap implementation, which we are effectively still
>> using today was added by:
>>
>> commit 64ccc9c033c6089b2d426dad3c56477ab066c999
>> Author: Marek Szyprowski <m.szyprowski@samsung.com>
>> Date: Thu Jun 14 13:03:04 2012 +0200
>>
>> common: dma-mapping: add support for generic dma_mmap_* calls
>>
>> and unconditionally uses pgprot_noncached in dma_common_mmap, which is
>> then used as the fallback by dma_mmap_attrs if no ->mmap method is
>> present. At that point we already had the powerpc implementation
>> that only uses pgprot_noncached for non-coherent mappings, and
>> the arm one, which uses pgprot_writecombine if DMA_ATTR_WRITE_COMBINE
>> is set and otherwise pgprot_dmacoherent, which seems to be uncached.
>> Arm did support coherent platforms at that time, but they might have
>> been an afterthought and not handled properly.
>
> Cache-coherent devices are still very rare on 32-bit ARM.
>
> Among the callers of dma_mmap_coherent(), almost all are in platform
> specific device drivers that only ever run on noncoherent ARM SoCs,
> which explains why nobody would have noticed problems.
>
> There is also a difference in behavior between ARM and PowerPC
> when dealing with mismatched cacheability attributes: If the same
> page is mapped as both cached and uncached to, this may
> cause silent undefined behavior on ARM, while PowerPC should
> enter a checkstop as soon as it notices.
On newer Power CPUs it's actually more like the ARM behaviour.
I don't know for sure that it will *never* checkstop but there are at
least cases where it won't. There's some (not much) detail in the
Power8/9 user manuals.
cheers
^ permalink raw reply
* Re: [PATCH v4 7/8] KVM: PPC: Ultravisor: Enter a secure guest
From: Michael Ellerman @ 2019-07-22 11:05 UTC (permalink / raw)
To: Sukadev Bhattiprolu
Cc: Madhavan Srinivasan, Michael Anderson, Ram Pai, Claudio Carvalho,
kvm-ppc, Bharata B Rao, linuxppc-dev, Ryan Grimm,
Thiago Bauermann, Anshuman Khandual
In-Reply-To: <20190718024724.GB13492@us.ibm.com>
Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> writes:
> Michael Ellerman [mpe@ellerman.id.au] wrote:
>> Claudio Carvalho <cclaudio@linux.ibm.com> writes:
>> > From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
>> >
>> > To enter a secure guest, we have to go through the ultravisor, therefore
>> > we do a ucall when we are entering a secure guest.
>> >
>> > This change is needed for any sort of entry to the secure guest from the
>> > hypervisor, whether it is a return from an hcall, a return from a
>> > hypervisor interrupt, or the first time that a secure guest vCPU is run.
>> >
>> > If we are returning from an hcall, the results are already in the
>> > appropriate registers R3:12, except for R3, R6 and R7. R3 has the status
>> > of the reflected hcall, therefore we move it to R0 for the ultravisor and
>> > set R3 to the UV_RETURN ucall number. R6,7 were used as temporary
>> > registers, hence we restore them.
>>
>> This is another case where some documentation would help people to
>> review the code.
>>
>> > Have fast_guest_return check the kvm_arch.secure_guest field so that a
>> > new CPU enters UV when started (in response to a RTAS start-cpu call).
>> >
>> > Thanks to input from Paul Mackerras, Ram Pai and Mike Anderson.
>> >
>> > Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
>> > [ Pass SRR1 in r11 for UV_RETURN, fix kvmppc_msr_interrupt to preserve
>> > the MSR_S bit ]
>> > Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
>> > [ Fix UV_RETURN ucall number and arch.secure_guest check ]
>> > Signed-off-by: Ram Pai <linuxram@us.ibm.com>
>> > [ Save the actual R3 in R0 for the ultravisor and use R3 for the
>> > UV_RETURN ucall number. Update commit message and ret_to_ultra comment ]
>> > Signed-off-by: Claudio Carvalho <cclaudio@linux.ibm.com>
>> > ---
>> > arch/powerpc/include/asm/kvm_host.h | 1 +
>> > arch/powerpc/include/asm/ultravisor-api.h | 1 +
>> > arch/powerpc/kernel/asm-offsets.c | 1 +
>> > arch/powerpc/kvm/book3s_hv_rmhandlers.S | 40 +++++++++++++++++++----
>> > 4 files changed, 37 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
>> > index cffb365d9d02..89813ca987c2 100644
>> > --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
>> > +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
>> > @@ -36,6 +36,7 @@
>> > #include <asm/asm-compat.h>
>> > #include <asm/feature-fixups.h>
>> > #include <asm/cpuidle.h>
>> > +#include <asm/ultravisor-api.h>
>> >
>> > /* Sign-extend HDEC if not on POWER9 */
>> > #define EXTEND_HDEC(reg) \
>> > @@ -1092,16 +1093,12 @@ BEGIN_FTR_SECTION
>> > END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
>> >
>> > ld r5, VCPU_LR(r4)
>> > - ld r6, VCPU_CR(r4)
>> > mtlr r5
>> > - mtcr r6
>> >
>> > ld r1, VCPU_GPR(R1)(r4)
>> > ld r2, VCPU_GPR(R2)(r4)
>> > ld r3, VCPU_GPR(R3)(r4)
>> > ld r5, VCPU_GPR(R5)(r4)
>> > - ld r6, VCPU_GPR(R6)(r4)
>> > - ld r7, VCPU_GPR(R7)(r4)
>> > ld r8, VCPU_GPR(R8)(r4)
>> > ld r9, VCPU_GPR(R9)(r4)
>> > ld r10, VCPU_GPR(R10)(r4)
>> > @@ -1119,10 +1116,38 @@ BEGIN_FTR_SECTION
>> > mtspr SPRN_HDSISR, r0
>> > END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
>> >
>> > + ld r6, VCPU_KVM(r4)
>> > + lbz r7, KVM_SECURE_GUEST(r6)
>> > + cmpdi r7, 0
>>
>> You could hoist the load of r6 and r7 to here?
>
> we could move 'ld r7' here. r6 is used to restore CR below so
> it (r6) has to stay there?
It's used to restore CR in both paths, so both paths load VCPU_CR(r4)
into r6. So we could instead do that load once, before the branch?
>> > + bne ret_to_ultra
>> > +
>> > + lwz r6, VCPU_CR(r4)
>> > + mtcr r6
>> > +
>> > + ld r7, VCPU_GPR(R7)(r4)
>> > + ld r6, VCPU_GPR(R6)(r4)
>> > ld r0, VCPU_GPR(R0)(r4)
>> > ld r4, VCPU_GPR(R4)(r4)
>> > HRFI_TO_GUEST
>> > b .
>> > +/*
>> > + * We are entering a secure guest, so we have to invoke the ultravisor to do
>> > + * that. If we are returning from a hcall, the results are already in the
>> > + * appropriate registers R3:12, except for R3, R6 and R7. R3 has the status of
>> > + * the reflected hcall, therefore we move it to R0 for the ultravisor and set
>> > + * R3 to the UV_RETURN ucall number. R6,7 were used as temporary registers
>> > + * above, hence we restore them.
>> > + */
>> > +ret_to_ultra:
>> > + lwz r6, VCPU_CR(r4)
>> > + mtcr r6
>> > + mfspr r11, SPRN_SRR1
>> > + mr r0, r3
>> > + LOAD_REG_IMMEDIATE(r3, UV_RETURN)
>>
>> Worth open coding to save three instructions?
>
> Yes, good point:
>
> - LOAD_REG_IMMEDIATE(r3, UV_RETURN)
> +
> + li r3, 0
> + oris r3, r3, (UV_RETURN)@__AS_ATHIGH
> + ori r3, r3, (UV_RETURN)@l
This should do it no?
li r3, 0
oris r3, r3, UV_RETURN
cheers
^ permalink raw reply
* Re: [PATCH 2/2] powerpc: expose secure variables via sysfs
From: Oliver O'Halloran @ 2019-07-22 10:19 UTC (permalink / raw)
To: Nayna Jain, linuxppc-dev, linux-efi
Cc: Ard Biesheuvel, Eric Ricther, Greg Kroah-Hartman,
Claudio Carvalho, Mimi Zohar, linux-kernel, Matthew Garret,
Paul Mackerras, Jeremy Kerr, Elaine Palmer, linux-integrity,
George Wilson
In-Reply-To: <1560459027-5248-3-git-send-email-nayna@linux.ibm.com>
On Thu, 2019-06-13 at 16:50 -0400, Nayna Jain wrote:
> As part of PowerNV secure boot support, OS verification keys are stored
> and controlled by OPAL as secure variables. These need to be exposed to
> the userspace so that sysadmins can perform key management tasks.
>
> This patch adds the support to expose secure variables via a sysfs
> interface It reuses the the existing efi defined hooks and backend in
> order to maintain the compatibility with the userspace tools.
>
> Though it reuses a great deal of efi, POWER platforms do not use EFI.
> A new config, POWER_SECVAR_SYSFS, is defined to enable this new sysfs
> interface.
I spent all day staring at the skiboot bits of this, so I figured I
should see what the kernel bits looked like too...
On the last version of this patch set (posted by Claudio) Matthew
Garret was pretty explicit about the interface here not conforming to
the expectations of efivars[1], so what's changed in this patch set to
fix that?
As far as I can tell it's has the same basic problems as before, just
with a slightly different OPAL interface.
[1] https://www.spinics.net/lists/linux-efi/msg15897.html
>
> Signed-off-by: Nayna Jain <nayna@linux.ibm.com>
> ---
> arch/powerpc/Kconfig | 2 +
> drivers/firmware/Makefile | 1 +
> drivers/firmware/efi/efivars.c | 2 +-
> drivers/firmware/powerpc/Kconfig | 12 +
> drivers/firmware/powerpc/Makefile | 3 +
> drivers/firmware/powerpc/efi_error.c | 46 ++++
> drivers/firmware/powerpc/secvar.c | 326 +++++++++++++++++++++++++++
> 7 files changed, 391 insertions(+), 1 deletion(-)
> create mode 100644 drivers/firmware/powerpc/Kconfig
> create mode 100644 drivers/firmware/powerpc/Makefile
> create mode 100644 drivers/firmware/powerpc/efi_error.c
> create mode 100644 drivers/firmware/powerpc/secvar.c
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 9de77bb14f54..1548dd8cf1a0 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -916,6 +916,8 @@ config PPC_SECURE_BOOT
> allows user to enable OS Secure Boot on PowerPC systems that
> have firmware secure boot support.
>
> +source "drivers/firmware/powerpc/Kconfig"
> +
> endmenu
All of this is *very* powernv specific, so why is it here and not in
arch/powerpc/platforms/powernv/ with the rest of the powernv platform
code? Also, nothing about this is generic to powerpc as a whole so the
Kconfig symbol should probably be change the Kconfig symbol to
POWERNV_SECURE_BOOT or OPAL_SECURE_BOOT
> config ISA_DMA_API
> diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
> index 3fa0b34eb72f..8cfaf7e6769d 100644
> --- a/drivers/firmware/Makefile
> +++ b/drivers/firmware/Makefile
> @@ -33,3 +33,4 @@ obj-$(CONFIG_UEFI_CPER) += efi/
> obj-y += imx/
> obj-y += tegra/
> obj-y += xilinx/
> +obj-$(CONFIG_POWER_SECVAR_SYSFS) += powerpc/
> diff --git a/drivers/firmware/efi/efivars.c b/drivers/firmware/efi/efivars.c
> index 7576450c8254..30ef53003c24 100644
> --- a/drivers/firmware/efi/efivars.c
> +++ b/drivers/firmware/efi/efivars.c
> @@ -664,7 +664,7 @@ int efivars_sysfs_init(void)
> struct kobject *parent_kobj = efivars_kobject();
> int error = 0;
>
> - if (!efi_enabled(EFI_RUNTIME_SERVICES))
> + if (IS_ENABLED(CONFIG_EFI) && !efi_enabled(EFI_RUNTIME_SERVICES))
> return -ENODEV;
>
> /* No efivars has been registered yet */
Seems a bit sketch.
> diff --git a/drivers/firmware/powerpc/Kconfig b/drivers/firmware/powerpc/Kconfig
> new file mode 100644
> index 000000000000..e0303fc517d5
> --- /dev/null
> +++ b/drivers/firmware/powerpc/Kconfig
> @@ -0,0 +1,12 @@
> +config POWER_SECVAR_SYSFS
> + tristate "Enable sysfs interface for POWER secure variables"
> + default n
> + depends on PPC_SECURE_BOOT
> + select UCS2_STRING
> + help
> + POWER secure variables are managed and controlled by OPAL.
> + These variables are exposed to userspace via sysfs to allow
> + user to read/write these variables. Say Y if you have secure
> + boot enabled and want to expose variables to userspace.
> +
> +source "drivers/firmware/efi/Kconfig"
Again, this is all powernv specific and not generic to all powerpc
platforms.
> diff --git a/drivers/firmware/powerpc/Makefile b/drivers/firmware/powerpc/Makefile
> new file mode 100644
> index 000000000000..d5fa3b007315
> --- /dev/null
> +++ b/drivers/firmware/powerpc/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-$(CONFIG_POWER_SECVAR_SYSFS) += ../efi/efivars.o efi_error.o ../efi/vars.o secvar.o
Uh... That is going to need an Ack from someone in EFI land.
> diff --git a/drivers/firmware/powerpc/efi_error.c b/drivers/firmware/powerpc/efi_error.c
> new file mode 100644
> index 000000000000..b5cabd52e6b4
> --- /dev/null
> +++ b/drivers/firmware/powerpc/efi_error.c
> @@ -0,0 +1,46 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 IBM Corporation
> + * Author: Nayna Jain <nayna@linux.ibm.com>
> + *
> + * efi_error.c
> + * - Error codes as understood by efi based tools
> + * Taken from drivers/firmware/efi/efi.c
> + */
> +#include<linux/efi.h>
> +
> +int efi_status_to_err(efi_status_t status)
> +{
> + int err;
> +
> + switch (status) {
> + case EFI_SUCCESS:
> + err = 0;
> + break;
> + case EFI_INVALID_PARAMETER:
> + err = -EINVAL;
> + break;
> + case EFI_OUT_OF_RESOURCES:
> + err = -ENOSPC;
> + break;
> + case EFI_DEVICE_ERROR:
> + err = -EIO;
> + break;
> + case EFI_WRITE_PROTECTED:
> + err = -EROFS;
> + break;
> + case EFI_SECURITY_VIOLATION:
> + err = -EACCES;
> + break;
> + case EFI_NOT_FOUND:
> + err = -ENOENT;
> + break;
> + case EFI_ABORTED:
> + err = -EINTR;
> + break;
> + default:
> + err = -EINVAL;
> + }
> +
> + return err;
> +}
what calls this?
> diff --git a/drivers/firmware/powerpc/secvar.c b/drivers/firmware/powerpc/secvar.c
> new file mode 100644
> index 000000000000..f1f134a0bb7c
> --- /dev/null
> +++ b/drivers/firmware/powerpc/secvar.c
> @@ -0,0 +1,326 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 IBM Corporation
> + * Author: Nayna Jain <nayna@linux.ibm.com>
> + *
> + * secvar.c
> + * - wrappers to expose secure variables to userspace
> + */
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/types.h>
> +#include <linux/errno.h>
> +#include <linux/string.h>
> +#include <linux/spinlock.h>
> +#include <linux/fs.h>
> +#include <linux/slab.h>
> +#include <linux/ioctl.h>
> +#include <linux/uaccess.h>
> +#include <linux/kdebug.h>
> +#include <linux/efi.h>
> +#include <linux/module.h>
> +#include <linux/ucs2_string.h>
> +#include <asm/opal-secvar.h>
> +#include <asm/opal.h>
> +
> +static struct efivars efivars;
> +struct kobject *powerpc_kobj;
> +
> +efi_status_t opal_to_efi_status_log(int rc, const char *func_name)
> +{
> + efi_status_t status;
> +
> + switch (rc) {
> + case OPAL_EMPTY:
> + status = EFI_NOT_FOUND;
> + break;
> + case OPAL_HARDWARE:
> + status = EFI_DEVICE_ERROR;
> + break;
> + case OPAL_NO_MEM:
> + pr_err("%s: No space in the volatile storage\n", func_name);
> + status = EFI_OUT_OF_RESOURCES;
> + break;
> + case OPAL_PARAMETER:
> + status = EFI_INVALID_PARAMETER;
> + break;
> + case OPAL_PARTIAL:
> + status = EFI_BUFFER_TOO_SMALL;
> + break;
> + case OPAL_PERMISSION:
> + status = EFI_WRITE_PROTECTED;
> + break;
> + case OPAL_RESOURCE:
> + pr_err("%s: No space in the non-volatile storage\n", func_name);
> + status = EFI_OUT_OF_RESOURCES;
> + break;
> + case OPAL_SUCCESS:
> + status = EFI_SUCCESS;
> + break;
> + default:
> + pr_err("%s: Unknown OPAL error %d\n", func_name, rc);
> + status = EFI_DEVICE_ERROR;
> + break;
> + }
> +
> + return status;
> +}
> +
> +#define opal_to_efi_status(rc) opal_to_efi_status_log(rc, __func__)
> +
> +static void createkey(efi_char16_t *name, u8 **key, unsigned long *keylen)
> +{
> + *keylen = ucs2_utf8size(name) + 1;
> +
> + *key = kzalloc(*keylen, GFP_KERNEL);
> + if (!*key) {
> + *keylen = 0;
> + *key = NULL;
> + return;
> + }
> +
> + ucs2_as_utf8(*key, name, *keylen);
> +}
>
> +static void createmetadata(efi_char16_t *name, efi_guid_t *vendor, u32 *attr,
> + u8 **mdata, unsigned long *mdsize)
> +{
> + int size = 0;
> +
> + *mdsize = ucs2_strsize(name, 1024) + sizeof(efi_guid_t) + sizeof(u32);
> + *mdata = kzalloc(*mdsize, GFP_KERNEL);
> +
> + memcpy(*mdata, name, ucs2_strsize(name, 1024));
> + size = ucs2_strsize(name, 1024);
> +
> + memcpy(*mdata + size, vendor, sizeof(efi_guid_t));
> + size += sizeof(efi_guid_t);
> +
> + if (attr != NULL)
> + memcpy(*mdata + size, attr, sizeof(u32));
> + else
> + memset(*mdata + size, 0, sizeof(u32));
> +}
> +static int convert_buffer_to_efi_guid(u8 *buffer, efi_guid_t *guid)
> +{
> + u32 *a1;
> + u16 *a2;
> + u16 *a3;
> +
> + a1 = kzalloc(4, GFP_KERNEL);
> + memcpy(a1, buffer, 4);
> + *a1 = be32_to_cpu(*a1);
> +
> + a2 = kzalloc(2, GFP_KERNEL);
> + memcpy(a2, buffer+4, 2);
> + *a2 = be16_to_cpu(*a2);
> +
> + a3 = kzalloc(2, GFP_KERNEL);
> + memcpy(a3, buffer+6, 2);
> + *a3 = be16_to_cpu(*a3);
> +
> + *guid = EFI_GUID(*a1, *a2, *a3, *(buffer + 8),
> + *(buffer + 9),
> + *(buffer + 10),
> + *(buffer + 11),
> + *(buffer + 12),
> + *(buffer + 13),
> + *(buffer + 14),
> + *(buffer + 15));
> +
> + kfree(a1);
> + kfree(a2);
> + kfree(a3);
These should be on the stack, They're small and you free them almost
immediately after allocating them.
> + return 0;
> +}
> +static efi_status_t powerpc_get_variable(efi_char16_t *name, efi_guid_t *vendor,
> + u32 *attr, unsigned long *data_size,
> + void *data)
> +{
> + int rc;
> + u8 *key;
> + unsigned long keylen;
> + u8 *metadata;
> + unsigned long mdsize;
> + unsigned long dsize;
> + unsigned long namesize;
> +
> + if (!name)
> + return EFI_INVALID_PARAMETER;
> +
> + if (!vendor)
> + return EFI_INVALID_PARAMETER;
> +
> + if (*data_size == 0) {
> + /* If *data_size is zero, it implies data size is being asked */
> + createkey(name, &key, &keylen);
> + rc = opal_get_variable_size(key, keylen, &mdsize, &dsize);
> + *data_size = dsize;
> + kfree(key);
> + return opal_to_efi_status(rc);
> + }
> +
> + createkey(name, &key, &keylen);
> + createmetadata(name, vendor, attr, &metadata, &mdsize);
> +
> + rc = opal_get_variable(key, keylen, metadata, &mdsize, data, data_size);
> +
> + if (rc)
> + return opal_to_efi_status(rc);
> +
> + if (mdsize > 0) {
> + namesize = mdsize - sizeof(efi_guid_t) - sizeof(u32);
> + if (!attr)
> + return opal_to_efi_status(rc);
> + memset(attr, 0, sizeof(u32));
> + memcpy(attr, metadata + namesize + sizeof(efi_guid_t),
> + sizeof(u32));
> + *attr = be32_to_cpu(*attr);
> + }
> +
> + kfree(key);
> + kfree(metadata);
> +
> + return opal_to_efi_status(rc);
> +}
> +
> +
> +static efi_status_t powerpc_get_next_variable(unsigned long *name_size,
> + efi_char16_t *name,
> + efi_guid_t *vendor)
> +{
> + int rc;
> + u8 *key;
> + int namesize;
> + unsigned long keylen;
> + unsigned long keysize = 1024;
> + unsigned long *mdsize;
> + u8 *mdata = NULL;
> + efi_guid_t guid;
> +
> + if (ucs2_strnlen(name, 1024) > 0) {
> + createkey(name, &key, &keylen);
> + } else {
> + keylen = 0;
> + key = kzalloc(1024, GFP_KERNEL);
> + }
> +
> + pr_info("%s: powerpc get next variable, key is %s\n", __func__, key);
> +
> + rc = opal_get_next_variable(key, &keylen, keysize);
As far as I can tell the UEFI spec says the key namespace is really
made up of (vendor, key) tuples. This seems broken to me since it's
ignoring the vendor GUID part and treating it purely as an output, so
if we had two vendors (OS vendors maybe?) writing using the same key
name it'll cause problems.
You could fix that by concatenating the vendor GUID and the ucs-2 name
string, then passing that to OPAL as the key. Based on what the gsmi
driver does I don't think we really need to store the attributes either
so the metadata channel can be ditched entirely.
> + if (rc) {
> + kfree(key);
> + return opal_to_efi_status(rc);
> + }
> +
> + mdsize = kzalloc(sizeof(unsigned long), GFP_KERNEL);
> + rc = opal_get_variable_size(key, keylen, mdsize, NULL);
> + if (rc)
> + goto out;
> +
> + if (*mdsize <= 0)
> + goto out;
> +
> + mdata = kzalloc(*mdsize, GFP_KERNEL);
> +
> + rc = opal_get_variable(key, keylen, mdata, mdsize, NULL, NULL);
> + if (rc)
> + goto out;
> +
> + if (*mdsize > 0) {
> + namesize = *mdsize - sizeof(efi_guid_t) - sizeof(u32);
> + if (namesize > 0) {
> + memset(&guid, 0, sizeof(efi_guid_t));
> + convert_buffer_to_efi_guid(mdata + namesize, &guid);
> + memcpy(vendor, &guid, sizeof(efi_guid_t));
> + memset(name, 0, namesize + 2);
> + memcpy(name, mdata, namesize);
> + *name_size = namesize + 2;
> + name[namesize++] = 0;
> + name[namesize] = 0;
> + }
> + }
> +
> +out:
> + kfree(mdsize);
> + kfree(mdata);
> +
> + return opal_to_efi_status(rc);
> +}
> +
> +static efi_status_t powerpc_set_variable(efi_char16_t *name, efi_guid_t *vendor,
> + u32 attr, unsigned long data_size,
> + void *data)
> +{
> + int rc;
> + u8 *key;
> + unsigned long keylen;
> + u8 *metadata;
> + unsigned long mdsize;
> +
> + if (!name)
> + return EFI_INVALID_PARAMETER;
> +
> + if (!vendor)
> + return EFI_INVALID_PARAMETER;
> +
> + createkey(name, &key, &keylen);
> + pr_info("%s: nayna key is %s\n", __func__, key);
> +
> + createmetadata(name, vendor, &attr, &metadata, &mdsize);
> + rc = opal_set_variable(key, keylen, metadata, mdsize, data, data_size);
> +
> + return opal_to_efi_status(rc);
> +}
> +
> +
> +static const struct efivar_operations efivar_ops = {
> + .get_variable = powerpc_get_variable,
> + .set_variable = powerpc_set_variable,
> + .get_next_variable = powerpc_get_next_variable,
> +};
> +
> +
> +static __init int power_secvar_init(void)
> +{
> + int rc = 0;
> + unsigned long ver = 0;
> +
> + rc = opal_variable_version(&ver);
> + if (ver != BACKEND_TC_COMPAT_V1) {
> + pr_info("Compatible backend unsupported\n");
> + return -1;
> + }
> +
> + powerpc_kobj = kobject_create_and_add("secvar", firmware_kobj);
> + if (!powerpc_kobj) {
> + pr_info("secvar: Failed to create firmware kobj\n");
> + goto out_err;
> + }
> +
> + rc = efivars_register(&efivars, &efivar_ops, powerpc_kobj);
> + if (rc) {
> + pr_info("powerpc: Failed to register efivars\n");
> + return rc;
> + }
> +
> + return 0;
> +out_err:
> + kobject_put(powerpc_kobj);
> + pr_info("powerpc: failed to load: %d\n", rc);
> + return rc;
> +}
> +arch_initcall(power_secvar_init);
> +
> +static void __exit power_secvar_exit(void)
> +{
> + efivars_unregister(&efivars);
> + kobject_put(powerpc_kobj);
> +}
> +module_exit(power_secvar_exit);
> +
> +MODULE_AUTHOR("Nayna Jain");
> +MODULE_LICENSE("GPL");
^ permalink raw reply
* Re: [PATCH v2] powerpc: slightly improve cache helpers
From: Michael Ellerman @ 2019-07-22 10:15 UTC (permalink / raw)
To: Segher Boessenkool, Nathan Chancellor
Cc: linux-kernel, clang-built-linux, Paul Mackerras, linuxppc-dev
In-Reply-To: <20190721180150.GN20882@gate.crashing.org>
Segher Boessenkool <segher@kernel.crashing.org> writes:
> On Sun, Jul 21, 2019 at 12:58:46AM -0700, Nathan Chancellor wrote:
>> I have attached the disassembly of arch/powerpc/kernel/mem.o with
>> clear_page (working) and broken_clear_page (broken), along with the side
>> by side diff. My assembly knowledge is fairly limited as it stands and
>> it is certainly not up to snuff on PowerPC so I have no idea what I am
>> looking for. Please let me know if anything immediately looks off or if
>> there is anything else I can do to help out.
>
> You might want to use a disassembler that shows most simplified mnemonics,
> and you crucially should show the relocations. "objdump -dr" works nicely.
>
>> 0000017c clear_user_page:
>> 17c: 38 80 00 80 li 4, 128
>> 180: 7c 89 03 a6 mtctr 4
>> 184: 7c 00 1f ec dcbz 0, 3
>> 188: 38 63 00 20 addi 3, 3, 32
>> 18c: 42 00 ff f8 bdnz .+65528
>
> That offset is incorrectly disassembled, btw (it's a signed field, not
> unsigned).
>
>> 0000017c clear_user_page:
>> 17c: 94 21 ff f0 stwu 1, -16(1)
>> 180: 38 80 00 80 li 4, 128
>> 184: 38 63 ff e0 addi 3, 3, -32
>> 188: 7c 89 03 a6 mtctr 4
>> 18c: 38 81 00 0f addi 4, 1, 15
>> 190: 8c c3 00 20 lbzu 6, 32(3)
>> 194: 98 c1 00 0f stb 6, 15(1)
>> 198: 7c 00 27 ec dcbz 0, 4
>> 19c: 42 00 ff f4 bdnz .+65524
>
> Uh, yeah, well, I have no idea what clang tried here, but that won't
> work. It's copying a byte from each target cache line to the stack,
> and then does clears the cache line containing that byte on the stack.
So it seems like this is a clang bug.
None of the distros we support use clang, but we would still like to
keep it working if we can.
Looking at the original patch, the only upside is that the compiler
can use both RA and RB to compute the address, rather than us forcing RA
to 0.
But at least with my compiler here (GCC 8 vintage) I don't actually see
GCC ever using both GPRs even with the patch. Or at least, there's no
difference before/after the patch as far as I can see.
So my inclination is to revert the original patch. We can try again in a
few years :D
Thoughts?
cheers
^ permalink raw reply
* Re: question on "powerpc/pseries/dma: Allow SWIOTLB"
From: Christoph Hellwig @ 2019-07-22 9:23 UTC (permalink / raw)
To: Alexey Kardashevskiy; +Cc: Christoph Hellwig, linuxppc-dev
In-Reply-To: <5c38b824-f703-bf97-3752-0f315b79b5a7@ozlabs.ru>
On Sat, Jul 20, 2019 at 09:22:49PM +1000, Alexey Kardashevskiy wrote:
>
>
> On 19/07/2019 22:25, Christoph Hellwig wrote:
> > On Fri, Jul 19, 2019 at 06:23:59PM +1000, Alexey Kardashevskiy wrote:
> >> It is getting there and I still do not see why "swiotlb=force" should not
> >> work if chosed in the cmdline.
> >
> > Ok, makes sense. But that means we also have the issue in a few
> > other places..
>
> Hmm, where? I got broadcom ethernet working with this.
In all the other IOMMU drivers that conditionally forward to the dma
direct ops. So it shouldn't affect powerpc.
^ permalink raw reply
* Re: Non deterministic kernel crashes after minimal devicetree changes.
From: Maik Nassauer @ 2019-07-22 9:14 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <513a3742d2a3a932b4958dc1b5fd68342aa43e41.camel@kernelconcepts.de>
[-- Attachment #1: Type: text/plain, Size: 357 bytes --]
Any ideas how to deal with this problem?
Best regards
--
kernel concepts GmbH Maik Nassauer
Hauptstraße 16
maik.nassauer@kernelconcepts.de
D-57074 Siegen Tel: +49 271-338857-21
http://www.kernelconcepts.de/
HR Siegen, HR B 9613
Geschäftsführer: Ole Reinhardt
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 878 bytes --]
^ permalink raw reply
* [PATCH kernel] powerpc/pseries/iommu: Add cond_resched() for huge updates
From: Alexey Kardashevskiy @ 2019-07-22 8:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Alexey Kardashevskiy
Mapping ~5.000.000 TCEs currently takes about 40s; this is the amount
required for a 300GB VM with 64k IOMMU page size. Anything bigger than
this produces RCU stall warnings.
This adds cond_resched() to allow the scheduler to do context switching
when it decides to.
This loop is called from dma_set_mask() which is a sleepable context.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
arch/powerpc/platforms/pseries/iommu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index 889dc2e44b89..2b8de822272f 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -459,6 +459,7 @@ static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
unsigned long num_pfn, void *arg)
{
+ cond_resched();
return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
}
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v2] powerpc: slightly improve cache helpers
From: Segher Boessenkool @ 2019-07-22 6:19 UTC (permalink / raw)
To: Nathan Chancellor
Cc: linux-kernel, clang-built-linux, Paul Mackerras, linuxppc-dev
In-Reply-To: <20190722024140.GA55142@archlinux-threadripper>
On Sun, Jul 21, 2019 at 07:41:40PM -0700, Nathan Chancellor wrote:
> Hi Segher,
>
> On Sun, Jul 21, 2019 at 01:01:50PM -0500, Segher Boessenkool wrote:
> > On Sun, Jul 21, 2019 at 12:58:46AM -0700, Nathan Chancellor wrote:
> > > 0000017c clear_user_page:
> > > 17c: 94 21 ff f0 stwu 1, -16(1)
> > > 180: 38 80 00 80 li 4, 128
> > > 184: 38 63 ff e0 addi 3, 3, -32
> > > 188: 7c 89 03 a6 mtctr 4
> > > 18c: 38 81 00 0f addi 4, 1, 15
> > > 190: 8c c3 00 20 lbzu 6, 32(3)
> > > 194: 98 c1 00 0f stb 6, 15(1)
> > > 198: 7c 00 27 ec dcbz 0, 4
> > > 19c: 42 00 ff f4 bdnz .+65524
> >
> > Uh, yeah, well, I have no idea what clang tried here, but that won't
> > work. It's copying a byte from each target cache line to the stack,
> > and then does clears the cache line containing that byte on the stack.
> >
> > I *guess* this is about "Z" and not about "%y", but you'll have to ask
> > the clang people.
> >
> > Or it may be that they do not treat inline asm operands as lvalues
> > properly? That rings some bells. Yeah that looks like it.
The code is
__asm__ __volatile__ ("dcbz %y0" : : "Z"(*(u8 *)addr) : "memory");
so yeah it looks like clang took that *(u8 *)addr as rvalue, and
stored that in stack, and then used *that* as memory.
Maybe clang simply does not not to treat "Z" the same as "m"? (And "Y"
and "Q" and "es" and a whole bunch of "w*", what about those?)
Segher
^ permalink raw reply
* Re: [PATCH v2] PCI: rpaphp: Avoid a sometimes-uninitialized warning
From: Michael Ellerman @ 2019-07-22 4:05 UTC (permalink / raw)
To: Nathan Chancellor, Tyrel Datwyler, Benjamin Herrenschmidt,
Paul Mackerras
Cc: linux-pci, Nick Desaulniers, linux-kernel, clang-built-linux,
Bjorn Helgaas, linuxppc-dev
In-Reply-To: <20190722024313.GB55142@archlinux-threadripper>
Nathan Chancellor <natechancellor@gmail.com> writes:
> On Mon, Jun 03, 2019 at 03:11:58PM -0700, Nathan Chancellor wrote:
>> When building with -Wsometimes-uninitialized, clang warns:
>>
>> drivers/pci/hotplug/rpaphp_core.c:243:14: warning: variable 'fndit' is
>> used uninitialized whenever 'for' loop exits because its condition is
>> false [-Wsometimes-uninitialized]
>> for (j = 0; j < entries; j++) {
>> ^~~~~~~~~~~
>> drivers/pci/hotplug/rpaphp_core.c:256:6: note: uninitialized use occurs
>> here
>> if (fndit)
>> ^~~~~
>> drivers/pci/hotplug/rpaphp_core.c:243:14: note: remove the condition if
>> it is always true
>> for (j = 0; j < entries; j++) {
>> ^~~~~~~~~~~
>> drivers/pci/hotplug/rpaphp_core.c:233:14: note: initialize the variable
>> 'fndit' to silence this warning
>> int j, fndit;
>> ^
>> = 0
>>
>> fndit is only used to gate a sprintf call, which can be moved into the
>> loop to simplify the code and eliminate the local variable, which will
>> fix this warning.
>>
>> Link: https://github.com/ClangBuiltLinux/linux/issues/504
>> Fixes: 2fcf3ae508c2 ("hotplug/drc-info: Add code to search ibm,drc-info property")
>> Suggested-by: Nick Desaulniers <ndesaulniers@google.com>
>> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
>> ---
>>
>> v1 -> v2:
>>
>> * Eliminate fndit altogether by shuffling the sprintf call into the for
>> loop and changing the if conditional, as suggested by Nick.
>>
>> drivers/pci/hotplug/rpaphp_core.c | 18 +++++++-----------
>> 1 file changed, 7 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/pci/hotplug/rpaphp_core.c b/drivers/pci/hotplug/rpaphp_core.c
>> index bcd5d357ca23..c3899ee1db99 100644
>> --- a/drivers/pci/hotplug/rpaphp_core.c
>> +++ b/drivers/pci/hotplug/rpaphp_core.c
>> @@ -230,7 +230,7 @@ static int rpaphp_check_drc_props_v2(struct device_node *dn, char *drc_name,
>> struct of_drc_info drc;
>> const __be32 *value;
>> char cell_drc_name[MAX_DRC_NAME_LEN];
>> - int j, fndit;
>> + int j;
>>
>> info = of_find_property(dn->parent, "ibm,drc-info", NULL);
>> if (info == NULL)
>> @@ -245,17 +245,13 @@ static int rpaphp_check_drc_props_v2(struct device_node *dn, char *drc_name,
>>
>> /* Should now know end of current entry */
>>
>> - if (my_index > drc.last_drc_index)
>> - continue;
>> -
>> - fndit = 1;
>> - break;
>> + /* Found it */
>> + if (my_index <= drc.last_drc_index) {
>> + sprintf(cell_drc_name, "%s%d", drc.drc_name_prefix,
>> + my_index);
>> + break;
>> + }
>> }
>> - /* Found it */
>> -
>> - if (fndit)
>> - sprintf(cell_drc_name, "%s%d", drc.drc_name_prefix,
>> - my_index);
>>
>> if (((drc_name == NULL) ||
>> (drc_name && !strcmp(drc_name, cell_drc_name))) &&
>> --
>> 2.22.0.rc3
>>
>
> Hi all,
>
> Could someone please pick this up?
I'll take it.
I was expecting Bjorn to take it as a PCI patch, but I realise now that
I merged that code in the first place so may as well take this too.
I'll put it in my next branch once that opens next week.
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/tm: Fix oops on sigreturn on systems without TM
From: Michael Ellerman @ 2019-07-22 3:20 UTC (permalink / raw)
To: Michael Ellerman, Michael Neuling
Cc: mikey, Praveen Pandey, gromero, linuxppc-dev, Breno Leitao,
Haren Myneni
In-Reply-To: <45sQyl2WrQz9sLt@ozlabs.org>
Michael Ellerman <patch-notifications@ellerman.id.au> writes:
> On Fri, 2019-07-19 at 05:05:02 UTC, Michael Neuling wrote:
>> On systems like P9 powernv where we have no TM (or P8 booted with
>> ppc_tm=off), userspace can construct a signal context which still has
>> the MSR TS bits set. The kernel tries to restore this context which
>> results in the following crash:
>>
>> [ 74.980557] Unexpected TM Bad Thing exception at c0000000000022fc (msr 0x8000000102a03031) tm_scratch=800000020280f033
>> [ 74.980741] Oops: Unrecoverable exception, sig: 6 [#1]
>> [ 74.980820] LE PAGE_SIZE=64K MMU=Hash SMP NR_CPUS=2048 NUMA pSeries
>> [ 74.980917] Modules linked in:
>> [ 74.980980] CPU: 0 PID: 1636 Comm: sigfuz Not tainted 5.2.0-11043-g0a8ad0ffa4 #69
>> [ 74.981096] NIP: c0000000000022fc LR: 00007fffb2d67e48 CTR: 0000000000000000
>> [ 74.981212] REGS: c00000003fffbd70 TRAP: 0700 Not tainted (5.2.0-11045-g7142b497d8)
>> [ 74.981325] MSR: 8000000102a03031 <SF,VEC,VSX,FP,ME,IR,DR,LE,TM[E]> CR: 42004242 XER: 00000000
>> [ 74.981463] CFAR: c0000000000022e0 IRQMASK: 0
>> [ 74.981463] GPR00: 0000000000000072 00007fffb2b6e560 00007fffb2d87f00 0000000000000669
>> [ 74.981463] GPR04: 00007fffb2b6e728 0000000000000000 0000000000000000 00007fffb2b6f2a8
>> [ 74.981463] GPR08: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
>> [ 74.981463] GPR12: 0000000000000000 00007fffb2b76900 0000000000000000 0000000000000000
>> [ 74.981463] GPR16: 00007fffb2370000 00007fffb2d84390 00007fffea3a15ac 000001000a250420
>> [ 74.981463] GPR20: 00007fffb2b6f260 0000000010001770 0000000000000000 0000000000000000
>> [ 74.981463] GPR24: 00007fffb2d843a0 00007fffea3a14a0 0000000000010000 0000000000800000
>> [ 74.981463] GPR28: 00007fffea3a14d8 00000000003d0f00 0000000000000000 00007fffb2b6e728
>> [ 74.982420] NIP [c0000000000022fc] rfi_flush_fallback+0x7c/0x80
>> [ 74.982517] LR [00007fffb2d67e48] 0x7fffb2d67e48
>> [ 74.982593] Call Trace:
>> [ 74.982632] Instruction dump:
>> [ 74.982691] e96a0220 e96a02a8 e96a0330 e96a03b8 394a0400 4200ffdc 7d2903a6 e92d0c00
>> [ 74.982809] e94d0c08 e96d0c10 e82d0c18 7db242a6 <4c000024> 7db243a6 7db142a6 f82d0c18
>>
>> The problem is the signal code assumes TM is enabled when
>> CONFIG_PPC_TRANSACTIONAL_MEM is on. This may not be the case as with
>> P9 powernv or if `ppc_tm=off` is used on P8.
>>
>> This means any local user can crash the system.
>>
>> Fix the problem by returning a bad stack frame to the user if they try
>> to set the MSR TS bits with sigreturn() on systems where TM is not
>> supported.
>>
>> Found with sigfuz kernel selftest on P9.
>>
>> This fixes CVE-2019-13648.
>>
>> Fixes: 2b0a576d15 ("powerpc: Add new transactional memory state to the signal context")
>> Cc: stable@vger.kernel.org # v3.9
>> Reported-by: Praveen Pandey <Praveen.Pandey@in.ibm.com>
>> Signed-off-by: Michael Neuling <mikey@neuling.org>
>
> Applied to powerpc fixes, thanks.
>
> https://git.kernel.org/powerpc/c/c7ce5fe9288c5692fa456a804cf5ea5976d842f1
Ignore this one.
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/tm: Fix oops on sigreturn on systems without TM
From: Michael Ellerman @ 2019-07-22 3:14 UTC (permalink / raw)
To: Michael Neuling
Cc: mikey, Praveen Pandey, gromero, linuxppc-dev, Breno Leitao,
Haren Myneni
In-Reply-To: <20190719050502.405-1-mikey@neuling.org>
On Fri, 2019-07-19 at 05:05:02 UTC, Michael Neuling wrote:
> On systems like P9 powernv where we have no TM (or P8 booted with
> ppc_tm=off), userspace can construct a signal context which still has
> the MSR TS bits set. The kernel tries to restore this context which
> results in the following crash:
>
> [ 74.980557] Unexpected TM Bad Thing exception at c0000000000022fc (msr 0x8000000102a03031) tm_scratch=800000020280f033
> [ 74.980741] Oops: Unrecoverable exception, sig: 6 [#1]
> [ 74.980820] LE PAGE_SIZE=64K MMU=Hash SMP NR_CPUS=2048 NUMA pSeries
> [ 74.980917] Modules linked in:
> [ 74.980980] CPU: 0 PID: 1636 Comm: sigfuz Not tainted 5.2.0-11043-g0a8ad0ffa4 #69
> [ 74.981096] NIP: c0000000000022fc LR: 00007fffb2d67e48 CTR: 0000000000000000
> [ 74.981212] REGS: c00000003fffbd70 TRAP: 0700 Not tainted (5.2.0-11045-g7142b497d8)
> [ 74.981325] MSR: 8000000102a03031 <SF,VEC,VSX,FP,ME,IR,DR,LE,TM[E]> CR: 42004242 XER: 00000000
> [ 74.981463] CFAR: c0000000000022e0 IRQMASK: 0
> [ 74.981463] GPR00: 0000000000000072 00007fffb2b6e560 00007fffb2d87f00 0000000000000669
> [ 74.981463] GPR04: 00007fffb2b6e728 0000000000000000 0000000000000000 00007fffb2b6f2a8
> [ 74.981463] GPR08: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
> [ 74.981463] GPR12: 0000000000000000 00007fffb2b76900 0000000000000000 0000000000000000
> [ 74.981463] GPR16: 00007fffb2370000 00007fffb2d84390 00007fffea3a15ac 000001000a250420
> [ 74.981463] GPR20: 00007fffb2b6f260 0000000010001770 0000000000000000 0000000000000000
> [ 74.981463] GPR24: 00007fffb2d843a0 00007fffea3a14a0 0000000000010000 0000000000800000
> [ 74.981463] GPR28: 00007fffea3a14d8 00000000003d0f00 0000000000000000 00007fffb2b6e728
> [ 74.982420] NIP [c0000000000022fc] rfi_flush_fallback+0x7c/0x80
> [ 74.982517] LR [00007fffb2d67e48] 0x7fffb2d67e48
> [ 74.982593] Call Trace:
> [ 74.982632] Instruction dump:
> [ 74.982691] e96a0220 e96a02a8 e96a0330 e96a03b8 394a0400 4200ffdc 7d2903a6 e92d0c00
> [ 74.982809] e94d0c08 e96d0c10 e82d0c18 7db242a6 <4c000024> 7db243a6 7db142a6 f82d0c18
>
> The problem is the signal code assumes TM is enabled when
> CONFIG_PPC_TRANSACTIONAL_MEM is on. This may not be the case as with
> P9 powernv or if `ppc_tm=off` is used on P8.
>
> This means any local user can crash the system.
>
> Fix the problem by returning a bad stack frame to the user if they try
> to set the MSR TS bits with sigreturn() on systems where TM is not
> supported.
>
> Found with sigfuz kernel selftest on P9.
>
> This fixes CVE-2019-13648.
>
> Fixes: 2b0a576d15 ("powerpc: Add new transactional memory state to the signal context")
> Cc: stable@vger.kernel.org # v3.9
> Reported-by: Praveen Pandey <Praveen.Pandey@in.ibm.com>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
Applied to powerpc fixes, thanks.
https://git.kernel.org/powerpc/c/f16d80b75a096c52354c6e0a574993f3b0dfbdfe
cheers
^ permalink raw reply
* Re: Re: Crash in kvmppc_xive_release()
From: Michael Ellerman @ 2019-07-22 2:48 UTC (permalink / raw)
To: Cédric Le Goater, linuxppc-dev, Greg Kurz,
Satheesh Rajendran, Paul Mackerras
In-Reply-To: <6ea6998b-a890-2511-01d1-747d7621eb19@kaod.org>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 1131 bytes --]
On Thu, 2019-07-18 at 21:51:54 UTC, =?UTF-8?Q?C=c3=a9dric_Le_Goater?= wrote:
> On 18/07/2019 15:14, Cédric Le Goater wrote:
...
>
> Here is a fix. Could you give it a try on your system ?
>
> Thanks,
>
> C.
>
> >From b6f728ca19a9540c8bf4f5a56991c4e3dab4cf56 Mon Sep 17 00:00:00 2001
> From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>
> Date: Thu, 18 Jul 2019 22:15:31 +0200
> Subject: [PATCH] KVM: PPC: Book3S HV: XIVE: fix rollback when
> kvmppc_xive_create fails
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
>
> The XIVE device structure is now allocated in kvmppc_xive_get_device()
> and kfree'd in kvmppc_core_destroy_vm(). In case of an OPAL error when
> allocating the XIVE VPs, the kfree() call in kvmppc_xive_*create()
> will result in a double free and corrupt the host memory.
>
> Fixes: 5422e95103cf ("KVM: PPC: Book3S HV: XIVE: Replace the 'destroy' method by a 'release' method")
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Applied to powerpc fixes, thanks.
https://git.kernel.org/powerpc/c/9798f4ea71eaf8eaad7e688c5b298528089c7bf8
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/tm: Fix oops on sigreturn on systems without TM
From: Michael Ellerman @ 2019-07-22 2:48 UTC (permalink / raw)
To: Michael Neuling
Cc: mikey, Praveen Pandey, gromero, linuxppc-dev, Breno Leitao,
Haren Myneni
In-Reply-To: <20190719050502.405-1-mikey@neuling.org>
On Fri, 2019-07-19 at 05:05:02 UTC, Michael Neuling wrote:
> On systems like P9 powernv where we have no TM (or P8 booted with
> ppc_tm=off), userspace can construct a signal context which still has
> the MSR TS bits set. The kernel tries to restore this context which
> results in the following crash:
>
> [ 74.980557] Unexpected TM Bad Thing exception at c0000000000022fc (msr 0x8000000102a03031) tm_scratch=800000020280f033
> [ 74.980741] Oops: Unrecoverable exception, sig: 6 [#1]
> [ 74.980820] LE PAGE_SIZE=64K MMU=Hash SMP NR_CPUS=2048 NUMA pSeries
> [ 74.980917] Modules linked in:
> [ 74.980980] CPU: 0 PID: 1636 Comm: sigfuz Not tainted 5.2.0-11043-g0a8ad0ffa4 #69
> [ 74.981096] NIP: c0000000000022fc LR: 00007fffb2d67e48 CTR: 0000000000000000
> [ 74.981212] REGS: c00000003fffbd70 TRAP: 0700 Not tainted (5.2.0-11045-g7142b497d8)
> [ 74.981325] MSR: 8000000102a03031 <SF,VEC,VSX,FP,ME,IR,DR,LE,TM[E]> CR: 42004242 XER: 00000000
> [ 74.981463] CFAR: c0000000000022e0 IRQMASK: 0
> [ 74.981463] GPR00: 0000000000000072 00007fffb2b6e560 00007fffb2d87f00 0000000000000669
> [ 74.981463] GPR04: 00007fffb2b6e728 0000000000000000 0000000000000000 00007fffb2b6f2a8
> [ 74.981463] GPR08: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
> [ 74.981463] GPR12: 0000000000000000 00007fffb2b76900 0000000000000000 0000000000000000
> [ 74.981463] GPR16: 00007fffb2370000 00007fffb2d84390 00007fffea3a15ac 000001000a250420
> [ 74.981463] GPR20: 00007fffb2b6f260 0000000010001770 0000000000000000 0000000000000000
> [ 74.981463] GPR24: 00007fffb2d843a0 00007fffea3a14a0 0000000000010000 0000000000800000
> [ 74.981463] GPR28: 00007fffea3a14d8 00000000003d0f00 0000000000000000 00007fffb2b6e728
> [ 74.982420] NIP [c0000000000022fc] rfi_flush_fallback+0x7c/0x80
> [ 74.982517] LR [00007fffb2d67e48] 0x7fffb2d67e48
> [ 74.982593] Call Trace:
> [ 74.982632] Instruction dump:
> [ 74.982691] e96a0220 e96a02a8 e96a0330 e96a03b8 394a0400 4200ffdc 7d2903a6 e92d0c00
> [ 74.982809] e94d0c08 e96d0c10 e82d0c18 7db242a6 <4c000024> 7db243a6 7db142a6 f82d0c18
>
> The problem is the signal code assumes TM is enabled when
> CONFIG_PPC_TRANSACTIONAL_MEM is on. This may not be the case as with
> P9 powernv or if `ppc_tm=off` is used on P8.
>
> This means any local user can crash the system.
>
> Fix the problem by returning a bad stack frame to the user if they try
> to set the MSR TS bits with sigreturn() on systems where TM is not
> supported.
>
> Found with sigfuz kernel selftest on P9.
>
> This fixes CVE-2019-13648.
>
> Fixes: 2b0a576d15 ("powerpc: Add new transactional memory state to the signal context")
> Cc: stable@vger.kernel.org # v3.9
> Reported-by: Praveen Pandey <Praveen.Pandey@in.ibm.com>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
Applied to powerpc fixes, thanks.
https://git.kernel.org/powerpc/c/c7ce5fe9288c5692fa456a804cf5ea5976d842f1
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/dma: Fix invalid DMA mmap behavior
From: Michael Ellerman @ 2019-07-22 2:48 UTC (permalink / raw)
To: Shawn Anastasio, linuxppc-dev; +Cc: aik, sbobroff
In-Reply-To: <20190717235437.12908-1-shawn@anastas.io>
On Wed, 2019-07-17 at 23:54:37 UTC, Shawn Anastasio wrote:
> The refactor of powerpc DMA functions in commit 6666cc17d780
> ("powerpc/dma: remove dma_nommu_mmap_coherent") incorrectly
> changes the way DMA mappings are handled on powerpc.
> Since this change, all mapped pages are marked as cache-inhibited
> through the default implementation of arch_dma_mmap_pgprot.
> This differs from the previous behavior of only marking pages
> in noncoherent mappings as cache-inhibited and has resulted in
> sporadic system crashes in certain hardware configurations and
> workloads (see Bugzilla).
>
> This commit restores the previous correct behavior by providing
> an implementation of arch_dma_mmap_pgprot that only marks
> pages in noncoherent mappings as cache-inhibited. As this behavior
> should be universal for all powerpc platforms a new file,
> dma-generic.c, was created to store it.
>
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204145
> Fixes: 6666cc17d780 ("powerpc/dma: remove dma_nommu_mmap_coherent")
> Signed-off-by: Shawn Anastasio <shawn@anastas.io>
> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> Reviewed-by: Christoph Hellwig <hch@lst.de>
Applied to powerpc fixes, thanks.
https://git.kernel.org/powerpc/c/b4fc36e60f25cf22bf8b7b015a701015740c3743
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/xive: Fix loop exit-condition in xive_find_target_in_mask()
From: Michael Ellerman @ 2019-07-22 2:48 UTC (permalink / raw)
To: Gautham R. Shenoy, Benjamin Herrenschmidt, Paul Mackerras,
Breno Leitao, Vaidyanathan Srinivasan
Cc: Gautham R. Shenoy, linuxppc-dev, linux-kernel, stable
In-Reply-To: <1563359724-13931-1-git-send-email-ego@linux.vnet.ibm.com>
On Wed, 2019-07-17 at 10:35:24 UTC, "Gautham R. Shenoy" wrote:
> From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
>
> xive_find_target_in_mask() has the following for(;;) loop which has a
> bug when @first == cpumask_first(@mask) and condition 1 fails to hold
> for every CPU in @mask. In this case we loop forever in the for-loop.
>
> first = cpu;
> for (;;) {
> if (cpu_online(cpu) && xive_try_pick_target(cpu)) // condition 1
> return cpu;
> cpu = cpumask_next(cpu, mask);
> if (cpu == first) // condition 2
> break;
>
> if (cpu >= nr_cpu_ids) // condition 3
> cpu = cpumask_first(mask);
> }
>
> This is because, when @first == cpumask_first(@mask), we never hit the
> condition 2 (cpu == first) since prior to this check, we would have
> executed "cpu = cpumask_next(cpu, mask)" which will set the value of
> @cpu to a value greater than @first or to nr_cpus_ids. When this is
> coupled with the fact that condition 1 is not met, we will never exit
> this loop.
>
> This was discovered by the hard-lockup detector while running LTP test
> concurrently with SMT switch tests.
>
> watchdog: CPU 12 detected hard LOCKUP on other CPUs 68
> watchdog: CPU 12 TB:85587019220796, last SMP heartbeat TB:85578827223399 (15999ms ago)
> watchdog: CPU 68 Hard LOCKUP
> watchdog: CPU 68 TB:85587019361273, last heartbeat TB:85576815065016 (19930ms ago)
> CPU: 68 PID: 45050 Comm: hxediag Kdump: loaded Not tainted 4.18.0-100.el8.ppc64le #1
> NIP: c0000000006f5578 LR: c000000000cba9ec CTR: 0000000000000000
> REGS: c000201fff3c7d80 TRAP: 0100 Not tainted (4.18.0-100.el8.ppc64le)
> MSR: 9000000002883033 <SF,HV,VEC,VSX,FP,ME,IR,DR,RI,LE> CR: 24028424 XER: 00000000
> CFAR: c0000000006f558c IRQMASK: 1
> GPR00: c0000000000afc58 c000201c01c43400 c0000000015ce500 c000201cae26ec18
> GPR04: 0000000000000800 0000000000000540 0000000000000800 00000000000000f8
> GPR08: 0000000000000020 00000000000000a8 0000000080000000 c00800001a1beed8
> GPR12: c0000000000b1410 c000201fff7f4c00 0000000000000000 0000000000000000
> GPR16: 0000000000000000 0000000000000000 0000000000000540 0000000000000001
> GPR20: 0000000000000048 0000000010110000 c00800001a1e3780 c000201cae26ed18
> GPR24: 0000000000000000 c000201cae26ed8c 0000000000000001 c000000001116bc0
> GPR28: c000000001601ee8 c000000001602494 c000201cae26ec18 000000000000001f
> NIP [c0000000006f5578] find_next_bit+0x38/0x90
> LR [c000000000cba9ec] cpumask_next+0x2c/0x50
> Call Trace:
> [c000201c01c43400] [c000201cae26ec18] 0xc000201cae26ec18 (unreliable)
> [c000201c01c43420] [c0000000000afc58] xive_find_target_in_mask+0x1b8/0x240
> [c000201c01c43470] [c0000000000b0228] xive_pick_irq_target.isra.3+0x168/0x1f0
> [c000201c01c435c0] [c0000000000b1470] xive_irq_startup+0x60/0x260
> [c000201c01c43640] [c0000000001d8328] __irq_startup+0x58/0xf0
> [c000201c01c43670] [c0000000001d844c] irq_startup+0x8c/0x1a0
> [c000201c01c436b0] [c0000000001d57b0] __setup_irq+0x9f0/0xa90
> [c000201c01c43760] [c0000000001d5aa0] request_threaded_irq+0x140/0x220
> [c000201c01c437d0] [c00800001a17b3d4] bnx2x_nic_load+0x188c/0x3040 [bnx2x]
> [c000201c01c43950] [c00800001a187c44] bnx2x_self_test+0x1fc/0x1f70 [bnx2x]
> [c000201c01c43a90] [c000000000adc748] dev_ethtool+0x11d8/0x2cb0
> [c000201c01c43b60] [c000000000b0b61c] dev_ioctl+0x5ac/0xa50
> [c000201c01c43bf0] [c000000000a8d4ec] sock_do_ioctl+0xbc/0x1b0
> [c000201c01c43c60] [c000000000a8dfb8] sock_ioctl+0x258/0x4f0
> [c000201c01c43d20] [c0000000004c9704] do_vfs_ioctl+0xd4/0xa70
> [c000201c01c43de0] [c0000000004ca274] sys_ioctl+0xc4/0x160
> [c000201c01c43e30] [c00000000000b388] system_call+0x5c/0x70
> Instruction dump:
> 78aad182 54a806be 3920ffff 78a50664 794a1f24 7d294036 7d43502a 7d295039
> 4182001c 48000034 78a9d182 79291f24 <7d23482a> 2fa90000 409e0020 38a50040
>
> To fix this, move the check for condition 2 after the check for
> condition 3, so that we are able to break out of the loop soon after
> iterating through all the CPUs in the @mask in the problem case. Use
> do..while() to achieve this.
>
> Fixes: 243e25112d06 ("powerpc/xive: Native exploitation of the XIVE
> interrupt controller")
> Cc: <stable@vger.kernel.org> # 4.12+
> Reported-by: Indira P. Joga <indira.priya@in.ibm.com>
> Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Applied to powerpc fixes, thanks.
https://git.kernel.org/powerpc/c/4d202c8c8ed3822327285747db1765967110b274
cheers
^ permalink raw reply
* Re: [PATCH v2] PCI: rpaphp: Avoid a sometimes-uninitialized warning
From: Nathan Chancellor @ 2019-07-22 2:43 UTC (permalink / raw)
To: Tyrel Datwyler, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman
Cc: linux-pci, Nick Desaulniers, linux-kernel, clang-built-linux,
Bjorn Helgaas, linuxppc-dev
In-Reply-To: <20190603221157.58502-1-natechancellor@gmail.com>
On Mon, Jun 03, 2019 at 03:11:58PM -0700, Nathan Chancellor wrote:
> When building with -Wsometimes-uninitialized, clang warns:
>
> drivers/pci/hotplug/rpaphp_core.c:243:14: warning: variable 'fndit' is
> used uninitialized whenever 'for' loop exits because its condition is
> false [-Wsometimes-uninitialized]
> for (j = 0; j < entries; j++) {
> ^~~~~~~~~~~
> drivers/pci/hotplug/rpaphp_core.c:256:6: note: uninitialized use occurs
> here
> if (fndit)
> ^~~~~
> drivers/pci/hotplug/rpaphp_core.c:243:14: note: remove the condition if
> it is always true
> for (j = 0; j < entries; j++) {
> ^~~~~~~~~~~
> drivers/pci/hotplug/rpaphp_core.c:233:14: note: initialize the variable
> 'fndit' to silence this warning
> int j, fndit;
> ^
> = 0
>
> fndit is only used to gate a sprintf call, which can be moved into the
> loop to simplify the code and eliminate the local variable, which will
> fix this warning.
>
> Link: https://github.com/ClangBuiltLinux/linux/issues/504
> Fixes: 2fcf3ae508c2 ("hotplug/drc-info: Add code to search ibm,drc-info property")
> Suggested-by: Nick Desaulniers <ndesaulniers@google.com>
> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
> ---
>
> v1 -> v2:
>
> * Eliminate fndit altogether by shuffling the sprintf call into the for
> loop and changing the if conditional, as suggested by Nick.
>
> drivers/pci/hotplug/rpaphp_core.c | 18 +++++++-----------
> 1 file changed, 7 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/hotplug/rpaphp_core.c b/drivers/pci/hotplug/rpaphp_core.c
> index bcd5d357ca23..c3899ee1db99 100644
> --- a/drivers/pci/hotplug/rpaphp_core.c
> +++ b/drivers/pci/hotplug/rpaphp_core.c
> @@ -230,7 +230,7 @@ static int rpaphp_check_drc_props_v2(struct device_node *dn, char *drc_name,
> struct of_drc_info drc;
> const __be32 *value;
> char cell_drc_name[MAX_DRC_NAME_LEN];
> - int j, fndit;
> + int j;
>
> info = of_find_property(dn->parent, "ibm,drc-info", NULL);
> if (info == NULL)
> @@ -245,17 +245,13 @@ static int rpaphp_check_drc_props_v2(struct device_node *dn, char *drc_name,
>
> /* Should now know end of current entry */
>
> - if (my_index > drc.last_drc_index)
> - continue;
> -
> - fndit = 1;
> - break;
> + /* Found it */
> + if (my_index <= drc.last_drc_index) {
> + sprintf(cell_drc_name, "%s%d", drc.drc_name_prefix,
> + my_index);
> + break;
> + }
> }
> - /* Found it */
> -
> - if (fndit)
> - sprintf(cell_drc_name, "%s%d", drc.drc_name_prefix,
> - my_index);
>
> if (((drc_name == NULL) ||
> (drc_name && !strcmp(drc_name, cell_drc_name))) &&
> --
> 2.22.0.rc3
>
Hi all,
Could someone please pick this up?
Thanks,
Nathan
^ permalink raw reply
* Re: [PATCH v2] powerpc: slightly improve cache helpers
From: Nathan Chancellor @ 2019-07-22 2:41 UTC (permalink / raw)
To: Segher Boessenkool
Cc: linux-kernel, clang-built-linux, Paul Mackerras, linuxppc-dev
In-Reply-To: <20190721180150.GN20882@gate.crashing.org>
[-- Attachment #1: Type: text/plain, Size: 2413 bytes --]
Hi Segher,
On Sun, Jul 21, 2019 at 01:01:50PM -0500, Segher Boessenkool wrote:
> On Sun, Jul 21, 2019 at 12:58:46AM -0700, Nathan Chancellor wrote:
> > I have attached the disassembly of arch/powerpc/kernel/mem.o with
> > clear_page (working) and broken_clear_page (broken), along with the side
> > by side diff. My assembly knowledge is fairly limited as it stands and
> > it is certainly not up to snuff on PowerPC so I have no idea what I am
> > looking for. Please let me know if anything immediately looks off or if
> > there is anything else I can do to help out.
>
> You might want to use a disassembler that shows most simplified mnemonics,
> and you crucially should show the relocations. "objdump -dr" works nicely.
Copy, those are attached below if you want to take a further look at
them.
> > 0000017c clear_user_page:
> > 17c: 38 80 00 80 li 4, 128
> > 180: 7c 89 03 a6 mtctr 4
> > 184: 7c 00 1f ec dcbz 0, 3
> > 188: 38 63 00 20 addi 3, 3, 32
> > 18c: 42 00 ff f8 bdnz .+65528
>
> That offset is incorrectly disassembled, btw (it's a signed field, not
> unsigned).
>
> > 0000017c clear_user_page:
> > 17c: 94 21 ff f0 stwu 1, -16(1)
> > 180: 38 80 00 80 li 4, 128
> > 184: 38 63 ff e0 addi 3, 3, -32
> > 188: 7c 89 03 a6 mtctr 4
> > 18c: 38 81 00 0f addi 4, 1, 15
> > 190: 8c c3 00 20 lbzu 6, 32(3)
> > 194: 98 c1 00 0f stb 6, 15(1)
> > 198: 7c 00 27 ec dcbz 0, 4
> > 19c: 42 00 ff f4 bdnz .+65524
>
> Uh, yeah, well, I have no idea what clang tried here, but that won't
> work. It's copying a byte from each target cache line to the stack,
> and then does clears the cache line containing that byte on the stack.
>
> I *guess* this is about "Z" and not about "%y", but you'll have to ask
> the clang people.
>
> Or it may be that they do not treat inline asm operands as lvalues
> properly? That rings some bells. Yeah that looks like it.
>
>
> Segher
Okay, I think I understand... I think this is enough to bring up an LLVM
bug report but I'll ask some of the LLVM folks I know before doing so.
Thank you for all of the input, I really appreciate it,
Nathan
[-- Attachment #2: mem-working.txt --]
[-- Type: text/plain, Size: 19428 bytes --]
mem-working.o: file format elf32-powerpc
Disassembly of section .text:
00000000 <phys_mem_access_prot>:
0: 7c 08 02 a6 mflr r0
4: 90 01 00 04 stw r0,4(r1)
8: 94 21 ff e0 stwu r1,-32(r1)
c: 93 a1 00 14 stw r29,20(r1)
10: 7c fd 3b 78 mr r29,r7
14: 3c e0 00 00 lis r7,0
16: R_PPC_ADDR16_HA ppc_md
18: 38 e7 00 00 addi r7,r7,0
1a: R_PPC_ADDR16_LO ppc_md
1c: 81 07 00 a0 lwz r8,160(r7)
20: 93 c1 00 18 stw r30,24(r1)
24: 28 08 00 00 cmplwi r8,0
28: 7c 7e 1b 78 mr r30,r3
2c: 41 82 00 20 beq 4c <phys_mem_access_prot+0x4c>
30: 80 7d 00 00 lwz r3,0(r29)
34: 38 e1 00 08 addi r7,r1,8
38: 7d 09 03 a6 mtctr r8
3c: 90 61 00 08 stw r3,8(r1)
40: 7f c3 f3 78 mr r3,r30
44: 4e 80 04 21 bctrl
48: 48 00 00 28 b 70 <phys_mem_access_prot+0x70>
4c: 7c a3 2b 78 mr r3,r5
50: 48 00 00 01 bl 50 <phys_mem_access_prot+0x50>
50: R_PPC_PLTREL24 page_is_ram
54: 28 03 00 00 cmplwi r3,0
58: 80 7d 00 00 lwz r3,0(r29)
5c: 40 82 00 10 bne 6c <phys_mem_access_prot+0x6c>
60: 54 63 06 26 rlwinm r3,r3,0,24,19
64: 60 63 05 00 ori r3,r3,1280
68: 90 7d 00 00 stw r3,0(r29)
6c: 90 7e 00 00 stw r3,0(r30)
70: 83 c1 00 18 lwz r30,24(r1)
74: 83 a1 00 14 lwz r29,20(r1)
78: 80 01 00 24 lwz r0,36(r1)
7c: 38 21 00 20 addi r1,r1,32
80: 7c 08 03 a6 mtlr r0
84: 4e 80 00 20 blr
00000088 <free_initmem>:
88: 7c 08 02 a6 mflr r0
8c: 90 01 00 04 stw r0,4(r1)
90: 94 21 ff f0 stwu r1,-16(r1)
94: 3c 60 00 00 lis r3,0
96: R_PPC_ADDR16_HA ppc_md
98: 3c 80 00 00 lis r4,0
9a: R_PPC_ADDR16_HA ppc_printk_progress
9c: 38 63 00 00 addi r3,r3,0
9e: R_PPC_ADDR16_LO ppc_md
a0: 38 84 00 00 addi r4,r4,0
a2: R_PPC_ADDR16_LO ppc_printk_progress
a4: 90 83 00 60 stw r4,96(r3)
a8: 48 00 00 01 bl a8 <free_initmem+0x20>
a8: R_PPC_PLTREL24 mark_initmem_nx
ac: 3c 60 00 00 lis r3,0
ae: R_PPC_ADDR16_HA init_mem_is_free
b0: 38 80 00 01 li r4,1
b4: 98 83 00 00 stb r4,0(r3)
b6: R_PPC_ADDR16_LO init_mem_is_free
b8: 3c 60 00 00 lis r3,0
ba: R_PPC_ADDR16_HA __init_begin
bc: 3c 80 00 00 lis r4,0
be: R_PPC_ADDR16_HA __init_end
c0: 3c a0 00 00 lis r5,0
c2: R_PPC_ADDR16_HA .rodata.str1.1+0x107
c4: 38 63 00 00 addi r3,r3,0
c6: R_PPC_ADDR16_LO __init_begin
c8: 38 84 00 00 addi r4,r4,0
ca: R_PPC_ADDR16_LO __init_end
cc: 38 c5 00 00 addi r6,r5,0
ce: R_PPC_ADDR16_LO .rodata.str1.1+0x107
d0: 38 a0 00 cc li r5,204
d4: 48 00 00 01 bl d4 <free_initmem+0x4c>
d4: R_PPC_PLTREL24 free_reserved_area
d8: 80 01 00 14 lwz r0,20(r1)
dc: 38 21 00 10 addi r1,r1,16
e0: 7c 08 03 a6 mtlr r0
e4: 4e 80 00 20 blr
000000e8 <flush_dcache_page>:
e8: 80 83 00 00 lwz r4,0(r3)
ec: 70 84 08 00 andi. r4,r4,2048
f0: 4d 82 00 20 beqlr
f4: 38 80 08 00 li r4,2048
f8: 7c a0 18 28 lwarx r5,0,r3
fc: 7c a5 20 78 andc r5,r5,r4
100: 7c a0 19 2d stwcx. r5,0,r3
104: 40 a2 ff f4 bne f8 <flush_dcache_page+0x10>
108: 4e 80 00 20 blr
0000010c <flush_dcache_icache_page>:
10c: 7c 08 02 a6 mflr r0
110: 90 01 00 04 stw r0,4(r1)
114: 94 21 ff f0 stwu r1,-16(r1)
118: 80 82 00 00 lwz r4,0(r2)
11c: 38 84 00 01 addi r4,r4,1
120: 90 82 00 00 stw r4,0(r2)
124: 80 82 0a e4 lwz r4,2788(r2)
128: 38 84 00 01 addi r4,r4,1
12c: 90 82 0a e4 stw r4,2788(r2)
130: 3c 80 00 00 lis r4,0
132: R_PPC_ADDR16_HA mem_map
134: 80 84 00 00 lwz r4,0(r4)
136: R_PPC_ADDR16_LO mem_map
138: 7c 64 18 50 subf r3,r4,r3
13c: 3c 80 cc cc lis r4,-13108
140: 54 63 e8 fe rlwinm r3,r3,29,3,31
144: 60 84 d0 00 ori r4,r4,53248
148: 7c 63 21 d6 mullw r3,r3,r4
14c: 3c 63 c0 00 addis r3,r3,-16384
150: 48 00 00 01 bl 150 <flush_dcache_icache_page+0x44>
150: R_PPC_PLTREL24 __flush_dcache_icache
154: 80 62 0a e4 lwz r3,2788(r2)
158: 38 63 ff ff addi r3,r3,-1
15c: 90 62 0a e4 stw r3,2788(r2)
160: 80 62 00 00 lwz r3,0(r2)
164: 38 63 ff ff addi r3,r3,-1
168: 90 62 00 00 stw r3,0(r2)
16c: 80 01 00 14 lwz r0,20(r1)
170: 38 21 00 10 addi r1,r1,16
174: 7c 08 03 a6 mtlr r0
178: 4e 80 00 20 blr
0000017c <clear_user_page>:
17c: 38 80 00 80 li r4,128
180: 7c 89 03 a6 mtctr r4
184: 7c 00 1f ec dcbz 0,r3
188: 38 63 00 20 addi r3,r3,32
18c: 42 00 ff f8 bdnz 184 <clear_user_page+0x8>
190: 80 65 00 00 lwz r3,0(r5)
194: 70 63 08 00 andi. r3,r3,2048
198: 4d 82 00 20 beqlr
19c: 38 60 08 00 li r3,2048
1a0: 7c 80 28 28 lwarx r4,0,r5
1a4: 7c 84 18 78 andc r4,r4,r3
1a8: 7c 80 29 2d stwcx. r4,0,r5
1ac: 40 a2 ff f4 bne 1a0 <clear_user_page+0x24>
1b0: 4e 80 00 20 blr
000001b4 <copy_user_page>:
1b4: 7c 08 02 a6 mflr r0
1b8: 90 01 00 04 stw r0,4(r1)
1bc: 94 21 ff f0 stwu r1,-16(r1)
1c0: 93 c1 00 08 stw r30,8(r1)
1c4: 7c de 33 78 mr r30,r6
1c8: 48 00 00 01 bl 1c8 <copy_user_page+0x14>
1c8: R_PPC_PLTREL24 copy_page
1cc: 80 7e 00 00 lwz r3,0(r30)
1d0: 70 63 08 00 andi. r3,r3,2048
1d4: 41 82 00 18 beq 1ec <copy_user_page+0x38>
1d8: 38 60 08 00 li r3,2048
1dc: 7c 80 f0 28 lwarx r4,0,r30
1e0: 7c 84 18 78 andc r4,r4,r3
1e4: 7c 80 f1 2d stwcx. r4,0,r30
1e8: 40 a2 ff f4 bne 1dc <copy_user_page+0x28>
1ec: 83 c1 00 08 lwz r30,8(r1)
1f0: 80 01 00 14 lwz r0,20(r1)
1f4: 38 21 00 10 addi r1,r1,16
1f8: 7c 08 03 a6 mtlr r0
1fc: 4e 80 00 20 blr
00000200 <flush_icache_user_range>:
200: 7c 08 02 a6 mflr r0
204: 90 01 00 04 stw r0,4(r1)
208: 94 21 ff e0 stwu r1,-32(r1)
20c: 3c 60 00 00 lis r3,0
20e: R_PPC_ADDR16_HA .rodata.str1.1+0x115
210: 93 81 00 10 stw r28,16(r1)
214: 7c 9c 23 78 mr r28,r4
218: 38 63 00 00 addi r3,r3,0
21a: R_PPC_ADDR16_LO .rodata.str1.1+0x115
21c: 38 80 00 53 li r4,83
220: 93 a1 00 14 stw r29,20(r1)
224: 7c bd 2b 78 mr r29,r5
228: 38 a0 00 00 li r5,0
22c: 93 c1 00 18 stw r30,24(r1)
230: 7c de 33 78 mr r30,r6
234: 48 00 00 01 bl 234 <flush_icache_user_range+0x34>
234: R_PPC_PLTREL24 __might_sleep
238: 3c 60 00 00 lis r3,0
23a: R_PPC_ADDR16_HA mem_map
23c: 3c 80 cc cc lis r4,-13108
240: 80 63 00 00 lwz r3,0(r3)
242: R_PPC_ADDR16_LO mem_map
244: 60 84 d0 00 ori r4,r4,53248
248: 7c 63 e0 50 subf r3,r3,r28
24c: 54 63 e8 fe rlwinm r3,r3,29,3,31
250: 7c 63 21 d6 mullw r3,r3,r4
254: 57 a4 05 3e clrlwi r4,r29,20
258: 50 64 00 26 rlwimi r4,r3,0,0,19
25c: 3c 64 c0 00 addis r3,r4,-16384
260: 7c 83 f2 14 add r4,r3,r30
264: 48 00 00 01 bl 264 <flush_icache_user_range+0x64>
264: R_PPC_PLTREL24 flush_icache_range
268: 83 c1 00 18 lwz r30,24(r1)
26c: 83 a1 00 14 lwz r29,20(r1)
270: 83 81 00 10 lwz r28,16(r1)
274: 80 01 00 24 lwz r0,36(r1)
278: 38 21 00 20 addi r1,r1,32
27c: 7c 08 03 a6 mtlr r0
280: 4e 80 00 20 blr
00000284 <update_mmu_cache>:
284: 4e 80 00 20 blr
00000288 <devmem_is_allowed>:
288: 7c 08 02 a6 mflr r0
28c: 90 01 00 04 stw r0,4(r1)
290: 94 21 ff f0 stwu r1,-16(r1)
294: 93 c1 00 08 stw r30,8(r1)
298: 7c 7e 1b 78 mr r30,r3
29c: 54 63 65 3e rlwinm r3,r3,12,20,31
2a0: 57 c4 60 26 rlwinm r4,r30,12,0,19
2a4: 48 00 00 01 bl 2a4 <devmem_is_allowed+0x1c>
2a4: R_PPC_PLTREL24 iomem_is_exclusive
2a8: 70 63 00 01 andi. r3,r3,1
2ac: 38 60 00 00 li r3,0
2b0: 41 81 00 14 bgt 2c4 <devmem_is_allowed+0x3c>
2b4: 7f c3 f3 78 mr r3,r30
2b8: 48 00 00 01 bl 2b8 <devmem_is_allowed+0x30>
2b8: R_PPC_PLTREL24 page_is_ram
2bc: 7c 63 00 34 cntlzw r3,r3
2c0: 54 63 df fe rlwinm r3,r3,27,31,31
2c4: 83 c1 00 08 lwz r30,8(r1)
2c8: 80 01 00 14 lwz r0,20(r1)
2cc: 38 21 00 10 addi r1,r1,16
2d0: 7c 08 03 a6 mtlr r0
2d4: 4e 80 00 20 blr
Disassembly of section .init.text:
00000000 <mem_topology_setup>:
0: 7c 08 02 a6 mflr r0
4: 90 01 00 04 stw r0,4(r1)
8: 94 21 ff f0 stwu r1,-16(r1)
c: 48 00 00 01 bl c <mem_topology_setup+0xc>
c: R_PPC_PLTREL24 memblock_end_of_DRAM
10: 54 84 a0 3e rotlwi r4,r4,20
14: 3c a0 00 00 lis r5,0
16: R_PPC_ADDR16_HA max_pfn
18: 50 64 a0 16 rlwimi r4,r3,20,0,11
1c: 3c 60 00 00 lis r3,0
1e: R_PPC_ADDR16_HA max_low_pfn
20: 90 85 00 00 stw r4,0(r5)
22: R_PPC_ADDR16_LO max_pfn
24: 38 a0 ff ff li r5,-1
28: 90 83 00 00 stw r4,0(r3)
2a: R_PPC_ADDR16_LO max_low_pfn
2c: 3c 60 00 00 lis r3,0
2e: R_PPC_ADDR16_HA min_low_pfn
30: 38 80 00 00 li r4,0
34: 38 c0 ff ff li r6,-1
38: 39 00 00 00 li r8,0
3c: 90 83 00 00 stw r4,0(r3)
3e: R_PPC_ADDR16_LO min_low_pfn
40: 3c 60 00 00 lis r3,0
42: R_PPC_ADDR16_HA memblock
44: 38 80 00 00 li r4,0
48: 38 63 00 00 addi r3,r3,0
4a: R_PPC_ADDR16_LO memblock
4c: 38 e3 00 10 addi r7,r3,16
50: 38 60 00 00 li r3,0
54: 48 00 00 01 bl 54 <mem_topology_setup+0x54>
54: R_PPC_PLTREL24 memblock_set_node
58: 80 01 00 14 lwz r0,20(r1)
5c: 38 21 00 10 addi r1,r1,16
60: 7c 08 03 a6 mtlr r0
64: 4e 80 00 20 blr
00000068 <initmem_init>:
68: 7c 08 02 a6 mflr r0
6c: 90 01 00 04 stw r0,4(r1)
70: 94 21 ff f0 stwu r1,-16(r1)
74: 38 60 00 00 li r3,0
78: 48 00 00 01 bl 78 <initmem_init+0x10>
78: R_PPC_PLTREL24 sparse_memory_present_with_active_regions
7c: 80 01 00 14 lwz r0,20(r1)
80: 38 21 00 10 addi r1,r1,16
84: 7c 08 03 a6 mtlr r0
88: 4e 80 00 20 blr
0000008c <paging_init>:
8c: 7c 08 02 a6 mflr r0
90: 90 01 00 04 stw r0,4(r1)
94: 94 21 ff d0 stwu r1,-48(r1)
98: 93 21 00 14 stw r25,20(r1)
9c: 93 41 00 18 stw r26,24(r1)
a0: 93 61 00 1c stw r27,28(r1)
a4: 93 81 00 20 stw r28,32(r1)
a8: 93 a1 00 24 stw r29,36(r1)
ac: 93 c1 00 28 stw r30,40(r1)
b0: 48 00 00 01 bl b0 <paging_init+0x24>
b0: R_PPC_PLTREL24 memblock_phys_mem_size
b4: 7c 7e 1b 78 mr r30,r3
b8: 7c 9d 23 78 mr r29,r4
bc: 3f 40 ff fe lis r26,-2
c0: 48 00 00 01 bl c0 <paging_init+0x34>
c0: R_PPC_PLTREL24 memblock_end_of_DRAM
c4: 7c 7c 1b 78 mr r28,r3
c8: 7c 9b 23 78 mr r27,r4
cc: 3b 20 00 00 li r25,0
d0: 38 e1 00 08 addi r7,r1,8
d4: 7f 43 d3 78 mr r3,r26
d8: 93 21 00 10 stw r25,16(r1)
dc: 38 a0 00 00 li r5,0
e0: 38 c0 00 00 li r6,0
e4: 93 21 00 08 stw r25,8(r1)
e8: 48 00 00 01 bl e8 <paging_init+0x5c>
e8: R_PPC_PLTREL24 map_kernel_page
ec: 3b 5a 10 00 addi r26,r26,4096
f0: 2c 1a f0 00 cmpwi r26,-4096
f4: 40 82 ff dc bne d0 <paging_init+0x44>
f8: 3c 60 00 00 lis r3,0
fa: R_PPC_ADDR16_HA .rodata.str1.1
fc: 4c c6 31 82 crclr 4*cr1+eq
100: 7f 85 e3 78 mr r5,r28
104: 38 63 00 00 addi r3,r3,0
106: R_PPC_ADDR16_LO .rodata.str1.1
108: 7f 66 db 78 mr r6,r27
10c: 7f c7 f3 78 mr r7,r30
110: 7f a8 eb 78 mr r8,r29
114: 48 00 00 01 bl 114 <paging_init+0x88>
114: R_PPC_PLTREL24 printk
118: 7c 7d d8 10 subfc r3,r29,r27
11c: 4c c6 31 82 crclr 4*cr1+eq
120: 7c be e1 10 subfe r5,r30,r28
124: 54 64 60 3e rotlwi r4,r3,12
128: 3c 60 00 00 lis r3,0
12a: R_PPC_ADDR16_HA .rodata.str1.1+0x29
12c: 50 a4 60 26 rlwimi r4,r5,12,0,19
130: 38 63 00 00 addi r3,r3,0
132: R_PPC_ADDR16_LO .rodata.str1.1+0x29
134: 48 00 00 01 bl 134 <paging_init+0xa8>
134: R_PPC_PLTREL24 printk
138: 3c 60 00 00 lis r3,0
13a: R_PPC_ADDR16_HA max_low_pfn
13c: 80 83 00 00 lwz r4,0(r3)
13e: R_PPC_ADDR16_LO max_low_pfn
140: 3c 60 00 00 lis r3,0
142: R_PPC_ADDR16_HA .bss+0x10
144: 94 83 00 00 stwu r4,0(r3)
146: R_PPC_ADDR16_LO .bss+0x10
148: 48 00 00 01 bl 148 <paging_init+0xbc>
148: R_PPC_PLTREL24 free_area_init_nodes
14c: 83 c1 00 28 lwz r30,40(r1)
150: 83 a1 00 24 lwz r29,36(r1)
154: 83 81 00 20 lwz r28,32(r1)
158: 83 61 00 1c lwz r27,28(r1)
15c: 83 41 00 18 lwz r26,24(r1)
160: 83 21 00 14 lwz r25,20(r1)
164: 80 01 00 34 lwz r0,52(r1)
168: 38 21 00 30 addi r1,r1,48
16c: 7c 08 03 a6 mtlr r0
170: 4e 80 00 20 blr
00000174 <mem_init>:
174: 7c 08 02 a6 mflr r0
178: 90 01 00 04 stw r0,4(r1)
17c: 94 21 ff e0 stwu r1,-32(r1)
180: 3c 60 00 00 lis r3,0
182: R_PPC_ADDR16_HA max_low_pfn
184: 3c 80 00 00 lis r4,0
186: R_PPC_ADDR16_HA max_pfn
188: 93 81 00 10 stw r28,16(r1)
18c: 3f 80 00 00 lis r28,0
18e: R_PPC_ADDR16_HA high_memory
190: 80 63 00 00 lwz r3,0(r3)
192: R_PPC_ADDR16_LO max_low_pfn
194: 80 84 00 00 lwz r4,0(r4)
196: R_PPC_ADDR16_LO max_pfn
198: 54 63 60 26 rlwinm r3,r3,12,0,19
19c: 3c 63 c0 00 addis r3,r3,-16384
1a0: 90 7c 00 00 stw r3,0(r28)
1a2: R_PPC_ADDR16_LO high_memory
1a4: 3c 60 00 00 lis r3,0
1a6: R_PPC_ADDR16_HA max_mapnr
1a8: 93 a1 00 14 stw r29,20(r1)
1ac: 93 c1 00 18 stw r30,24(r1)
1b0: 90 83 00 00 stw r4,0(r3)
1b2: R_PPC_ADDR16_LO max_mapnr
1b4: 48 00 00 01 bl 1b4 <mem_init+0x40>
1b4: R_PPC_PLTREL24 memblock_free_all
1b8: 38 60 00 00 li r3,0
1bc: 48 00 00 01 bl 1bc <mem_init+0x48>
1bc: R_PPC_PLTREL24 mem_init_print_info
1c0: 3c 60 00 00 lis r3,0
1c2: R_PPC_ADDR16_HA .rodata.str1.1+0x44
1c4: 4c c6 31 82 crclr 4*cr1+eq
1c8: 38 63 00 00 addi r3,r3,0
1ca: R_PPC_ADDR16_LO .rodata.str1.1+0x44
1cc: 48 00 00 01 bl 1cc <mem_init+0x58>
1cc: R_PPC_PLTREL24 printk
1d0: 3c 80 ff fd lis r4,-3
1d4: 3c 60 00 00 lis r3,0
1d6: R_PPC_ADDR16_HA .rodata.str1.1+0x65
1d8: 4c c6 31 82 crclr 4*cr1+eq
1dc: 60 9e f0 00 ori r30,r4,61440
1e0: 38 63 00 00 addi r3,r3,0
1e2: R_PPC_ADDR16_LO .rodata.str1.1+0x65
1e4: 7f c4 f3 78 mr r4,r30
1e8: 38 a0 f0 00 li r5,-4096
1ec: 48 00 00 01 bl 1ec <mem_init+0x78>
1ec: R_PPC_PLTREL24 printk
1f0: 3c 80 ff dd lis r4,-35
1f4: 3c 60 00 00 lis r3,0
1f6: R_PPC_ADDR16_HA .rodata.str1.1+0x87
1f8: 4c c6 31 82 crclr 4*cr1+eq
1fc: 60 9d f0 00 ori r29,r4,61440
200: 38 63 00 00 addi r3,r3,0
202: R_PPC_ADDR16_LO .rodata.str1.1+0x87
204: 7f a4 eb 78 mr r4,r29
208: 7f c5 f3 78 mr r5,r30
20c: 48 00 00 01 bl 20c <mem_init+0x98>
20c: R_PPC_PLTREL24 printk
210: 3f c0 00 00 lis r30,0
212: R_PPC_ADDR16_HA ioremap_bot
214: 3c 60 00 00 lis r3,0
216: R_PPC_ADDR16_HA .rodata.str1.1+0xb1
218: 4c c6 31 82 crclr 4*cr1+eq
21c: 80 9e 00 00 lwz r4,0(r30)
21e: R_PPC_ADDR16_LO ioremap_bot
220: 38 63 00 00 addi r3,r3,0
222: R_PPC_ADDR16_LO .rodata.str1.1+0xb1
224: 7f a5 eb 78 mr r5,r29
228: 48 00 00 01 bl 228 <mem_init+0xb4>
228: R_PPC_PLTREL24 printk
22c: 80 7c 00 00 lwz r3,0(r28)
22e: R_PPC_ADDR16_LO high_memory
230: 3c 80 01 00 lis r4,256
234: 4c c6 31 82 crclr 4*cr1+eq
238: 38 63 ff ff addi r3,r3,-1
23c: 80 be 00 00 lwz r5,0(r30)
23e: R_PPC_ADDR16_LO ioremap_bot
240: 3c 63 10 00 addis r3,r3,4096
244: 54 63 00 06 rlwinm r3,r3,0,0,3
248: 50 64 02 0c rlwimi r4,r3,0,8,6
24c: 3c 60 00 00 lis r3,0
24e: R_PPC_ADDR16_HA .rodata.str1.1+0xda
250: 38 63 00 00 addi r3,r3,0
252: R_PPC_ADDR16_LO .rodata.str1.1+0xda
254: 48 00 00 01 bl 254 <mem_init+0xe0>
254: R_PPC_PLTREL24 printk
258: 83 c1 00 18 lwz r30,24(r1)
25c: 83 a1 00 14 lwz r29,20(r1)
260: 83 81 00 10 lwz r28,16(r1)
264: 80 01 00 24 lwz r0,36(r1)
268: 38 21 00 20 addi r1,r1,32
26c: 7c 08 03 a6 mtlr r0
270: 4e 80 00 20 blr
00000274 <add_system_ram_resources>:
274: 7c 08 02 a6 mflr r0
278: 90 01 00 04 stw r0,4(r1)
27c: 94 21 ff c0 stwu r1,-64(r1)
280: 3c 60 00 00 lis r3,0
282: R_PPC_ADDR16_HA memblock
284: 93 a1 00 34 stw r29,52(r1)
288: 3b a3 00 00 addi r29,r3,0
28a: R_PPC_ADDR16_LO memblock
28c: 80 7d 00 10 lwz r3,16(r29)
290: 93 81 00 30 stw r28,48(r1)
294: 1c 63 00 18 mulli r3,r3,24
298: 83 9d 00 20 lwz r28,32(r29)
29c: 7c 7c 1a 14 add r3,r28,r3
2a0: 92 a1 00 14 stw r21,20(r1)
2a4: 7c 1c 18 40 cmplw r28,r3
2a8: 92 c1 00 18 stw r22,24(r1)
2ac: 92 e1 00 1c stw r23,28(r1)
2b0: 93 01 00 20 stw r24,32(r1)
2b4: 93 21 00 24 stw r25,36(r1)
2b8: 93 41 00 28 stw r26,40(r1)
2bc: 93 61 00 2c stw r27,44(r1)
2c0: 93 c1 00 38 stw r30,56(r1)
2c4: 40 80 00 ac bge 370 <add_system_ram_resources+0xfc>
2c8: 3c 60 00 00 lis r3,0
2ca: R_PPC_ADDR16_HA kmalloc_caches
2cc: 3c 80 00 00 lis r4,0
2ce: R_PPC_ADDR16_HA .rodata.str1.1+0x199
2d0: 3c a0 81 00 lis r5,-32512
2d4: 3c c0 00 00 lis r6,0
2d6: R_PPC_ADDR16_HA iomem_resource
2d8: 3b 7c ff e8 addi r27,r28,-24
2dc: 3b 40 00 00 li r26,0
2e0: 3b 23 00 00 addi r25,r3,0
2e2: R_PPC_ADDR16_LO kmalloc_caches
2e4: 3b 04 00 00 addi r24,r4,0
2e6: R_PPC_ADDR16_LO .rodata.str1.1+0x199
2e8: 60 b7 02 00 ori r23,r5,512
2ec: 3b c6 00 00 addi r30,r6,0
2ee: R_PPC_ADDR16_LO iomem_resource
2f0: 80 79 00 18 lwz r3,24(r25)
2f4: 38 80 0d c0 li r4,3520
2f8: 38 a0 00 28 li r5,40
2fc: 82 db 00 1c lwz r22,28(r27)
300: 82 bb 00 24 lwz r21,36(r27)
304: 48 00 00 01 bl 304 <add_system_ram_resources+0x90>
304: R_PPC_PLTREL24 kmem_cache_alloc_trace
308: 7c 64 1b 78 mr r4,r3
30c: 7c 63 00 34 cntlzw r3,r3
310: 28 04 00 00 cmplwi r4,0
314: 54 63 df fe rlwinm r3,r3,27,31,31
318: 0f 03 00 00 twnei r3,0
31c: 41 82 00 34 beq 350 <add_system_ram_resources+0xdc>
320: 7c 76 aa 14 add r3,r22,r21
324: 93 04 00 10 stw r24,16(r4)
328: 38 63 ff ff addi r3,r3,-1
32c: 90 64 00 0c stw r3,12(r4)
330: 7f c3 f3 78 mr r3,r30
334: 93 44 00 00 stw r26,0(r4)
338: 92 c4 00 04 stw r22,4(r4)
33c: 93 44 00 08 stw r26,8(r4)
340: 92 e4 00 14 stw r23,20(r4)
344: 48 00 00 01 bl 344 <add_system_ram_resources+0xd0>
344: R_PPC_PLTREL24 request_resource
348: 54 63 0f fe rlwinm r3,r3,1,31,31
34c: 0f 03 00 00 twnei r3,0
350: 80 7d 00 10 lwz r3,16(r29)
354: 3b 9c 00 18 addi r28,r28,24
358: 3b 7b 00 18 addi r27,r27,24
35c: 80 9d 00 20 lwz r4,32(r29)
360: 1c 63 00 18 mulli r3,r3,24
364: 7c 64 1a 14 add r3,r4,r3
368: 7c 1c 18 40 cmplw r28,r3
36c: 41 80 ff 84 blt 2f0 <add_system_ram_resources+0x7c>
370: 38 60 00 00 li r3,0
374: 83 c1 00 38 lwz r30,56(r1)
378: 83 a1 00 34 lwz r29,52(r1)
37c: 83 81 00 30 lwz r28,48(r1)
380: 83 61 00 2c lwz r27,44(r1)
384: 83 41 00 28 lwz r26,40(r1)
388: 83 21 00 24 lwz r25,36(r1)
38c: 83 01 00 20 lwz r24,32(r1)
390: 82 e1 00 1c lwz r23,28(r1)
394: 82 c1 00 18 lwz r22,24(r1)
398: 82 a1 00 14 lwz r21,20(r1)
39c: 80 01 00 44 lwz r0,68(r1)
3a0: 38 21 00 40 addi r1,r1,64
3a4: 7c 08 03 a6 mtlr r0
3a8: 4e 80 00 20 blr
[-- Attachment #3: mem-broken.txt --]
[-- Type: text/plain, Size: 19642 bytes --]
mem-broken.o: file format elf32-powerpc
Disassembly of section .text:
00000000 <phys_mem_access_prot>:
0: 7c 08 02 a6 mflr r0
4: 90 01 00 04 stw r0,4(r1)
8: 94 21 ff e0 stwu r1,-32(r1)
c: 93 a1 00 14 stw r29,20(r1)
10: 7c fd 3b 78 mr r29,r7
14: 3c e0 00 00 lis r7,0
16: R_PPC_ADDR16_HA ppc_md
18: 38 e7 00 00 addi r7,r7,0
1a: R_PPC_ADDR16_LO ppc_md
1c: 81 07 00 a0 lwz r8,160(r7)
20: 93 c1 00 18 stw r30,24(r1)
24: 28 08 00 00 cmplwi r8,0
28: 7c 7e 1b 78 mr r30,r3
2c: 41 82 00 20 beq 4c <phys_mem_access_prot+0x4c>
30: 80 7d 00 00 lwz r3,0(r29)
34: 38 e1 00 08 addi r7,r1,8
38: 7d 09 03 a6 mtctr r8
3c: 90 61 00 08 stw r3,8(r1)
40: 7f c3 f3 78 mr r3,r30
44: 4e 80 04 21 bctrl
48: 48 00 00 28 b 70 <phys_mem_access_prot+0x70>
4c: 7c a3 2b 78 mr r3,r5
50: 48 00 00 01 bl 50 <phys_mem_access_prot+0x50>
50: R_PPC_PLTREL24 page_is_ram
54: 28 03 00 00 cmplwi r3,0
58: 80 7d 00 00 lwz r3,0(r29)
5c: 40 82 00 10 bne 6c <phys_mem_access_prot+0x6c>
60: 54 63 06 26 rlwinm r3,r3,0,24,19
64: 60 63 05 00 ori r3,r3,1280
68: 90 7d 00 00 stw r3,0(r29)
6c: 90 7e 00 00 stw r3,0(r30)
70: 83 c1 00 18 lwz r30,24(r1)
74: 83 a1 00 14 lwz r29,20(r1)
78: 80 01 00 24 lwz r0,36(r1)
7c: 38 21 00 20 addi r1,r1,32
80: 7c 08 03 a6 mtlr r0
84: 4e 80 00 20 blr
00000088 <free_initmem>:
88: 7c 08 02 a6 mflr r0
8c: 90 01 00 04 stw r0,4(r1)
90: 94 21 ff f0 stwu r1,-16(r1)
94: 3c 60 00 00 lis r3,0
96: R_PPC_ADDR16_HA ppc_md
98: 3c 80 00 00 lis r4,0
9a: R_PPC_ADDR16_HA ppc_printk_progress
9c: 38 63 00 00 addi r3,r3,0
9e: R_PPC_ADDR16_LO ppc_md
a0: 38 84 00 00 addi r4,r4,0
a2: R_PPC_ADDR16_LO ppc_printk_progress
a4: 90 83 00 60 stw r4,96(r3)
a8: 48 00 00 01 bl a8 <free_initmem+0x20>
a8: R_PPC_PLTREL24 mark_initmem_nx
ac: 3c 60 00 00 lis r3,0
ae: R_PPC_ADDR16_HA init_mem_is_free
b0: 38 80 00 01 li r4,1
b4: 98 83 00 00 stb r4,0(r3)
b6: R_PPC_ADDR16_LO init_mem_is_free
b8: 3c 60 00 00 lis r3,0
ba: R_PPC_ADDR16_HA __init_begin
bc: 3c 80 00 00 lis r4,0
be: R_PPC_ADDR16_HA __init_end
c0: 3c a0 00 00 lis r5,0
c2: R_PPC_ADDR16_HA .rodata.str1.1+0x107
c4: 38 63 00 00 addi r3,r3,0
c6: R_PPC_ADDR16_LO __init_begin
c8: 38 84 00 00 addi r4,r4,0
ca: R_PPC_ADDR16_LO __init_end
cc: 38 c5 00 00 addi r6,r5,0
ce: R_PPC_ADDR16_LO .rodata.str1.1+0x107
d0: 38 a0 00 cc li r5,204
d4: 48 00 00 01 bl d4 <free_initmem+0x4c>
d4: R_PPC_PLTREL24 free_reserved_area
d8: 80 01 00 14 lwz r0,20(r1)
dc: 38 21 00 10 addi r1,r1,16
e0: 7c 08 03 a6 mtlr r0
e4: 4e 80 00 20 blr
000000e8 <flush_dcache_page>:
e8: 80 83 00 00 lwz r4,0(r3)
ec: 70 84 08 00 andi. r4,r4,2048
f0: 4d 82 00 20 beqlr
f4: 38 80 08 00 li r4,2048
f8: 7c a0 18 28 lwarx r5,0,r3
fc: 7c a5 20 78 andc r5,r5,r4
100: 7c a0 19 2d stwcx. r5,0,r3
104: 40 a2 ff f4 bne f8 <flush_dcache_page+0x10>
108: 4e 80 00 20 blr
0000010c <flush_dcache_icache_page>:
10c: 7c 08 02 a6 mflr r0
110: 90 01 00 04 stw r0,4(r1)
114: 94 21 ff f0 stwu r1,-16(r1)
118: 80 82 00 00 lwz r4,0(r2)
11c: 38 84 00 01 addi r4,r4,1
120: 90 82 00 00 stw r4,0(r2)
124: 80 82 0a e4 lwz r4,2788(r2)
128: 38 84 00 01 addi r4,r4,1
12c: 90 82 0a e4 stw r4,2788(r2)
130: 3c 80 00 00 lis r4,0
132: R_PPC_ADDR16_HA mem_map
134: 80 84 00 00 lwz r4,0(r4)
136: R_PPC_ADDR16_LO mem_map
138: 7c 64 18 50 subf r3,r4,r3
13c: 3c 80 cc cc lis r4,-13108
140: 54 63 e8 fe rlwinm r3,r3,29,3,31
144: 60 84 d0 00 ori r4,r4,53248
148: 7c 63 21 d6 mullw r3,r3,r4
14c: 3c 63 c0 00 addis r3,r3,-16384
150: 48 00 00 01 bl 150 <flush_dcache_icache_page+0x44>
150: R_PPC_PLTREL24 __flush_dcache_icache
154: 80 62 0a e4 lwz r3,2788(r2)
158: 38 63 ff ff addi r3,r3,-1
15c: 90 62 0a e4 stw r3,2788(r2)
160: 80 62 00 00 lwz r3,0(r2)
164: 38 63 ff ff addi r3,r3,-1
168: 90 62 00 00 stw r3,0(r2)
16c: 80 01 00 14 lwz r0,20(r1)
170: 38 21 00 10 addi r1,r1,16
174: 7c 08 03 a6 mtlr r0
178: 4e 80 00 20 blr
0000017c <clear_user_page>:
17c: 94 21 ff f0 stwu r1,-16(r1)
180: 38 80 00 80 li r4,128
184: 38 63 ff e0 addi r3,r3,-32
188: 7c 89 03 a6 mtctr r4
18c: 38 81 00 0f addi r4,r1,15
190: 8c c3 00 20 lbzu r6,32(r3)
194: 98 c1 00 0f stb r6,15(r1)
198: 7c 00 27 ec dcbz 0,r4
19c: 42 00 ff f4 bdnz 190 <clear_user_page+0x14>
1a0: 80 65 00 00 lwz r3,0(r5)
1a4: 70 63 08 00 andi. r3,r3,2048
1a8: 41 82 00 18 beq 1c0 <clear_user_page+0x44>
1ac: 38 60 08 00 li r3,2048
1b0: 7c 80 28 28 lwarx r4,0,r5
1b4: 7c 84 18 78 andc r4,r4,r3
1b8: 7c 80 29 2d stwcx. r4,0,r5
1bc: 40 a2 ff f4 bne 1b0 <clear_user_page+0x34>
1c0: 38 21 00 10 addi r1,r1,16
1c4: 4e 80 00 20 blr
000001c8 <copy_user_page>:
1c8: 7c 08 02 a6 mflr r0
1cc: 90 01 00 04 stw r0,4(r1)
1d0: 94 21 ff f0 stwu r1,-16(r1)
1d4: 93 c1 00 08 stw r30,8(r1)
1d8: 7c de 33 78 mr r30,r6
1dc: 48 00 00 01 bl 1dc <copy_user_page+0x14>
1dc: R_PPC_PLTREL24 copy_page
1e0: 80 7e 00 00 lwz r3,0(r30)
1e4: 70 63 08 00 andi. r3,r3,2048
1e8: 41 82 00 18 beq 200 <copy_user_page+0x38>
1ec: 38 60 08 00 li r3,2048
1f0: 7c 80 f0 28 lwarx r4,0,r30
1f4: 7c 84 18 78 andc r4,r4,r3
1f8: 7c 80 f1 2d stwcx. r4,0,r30
1fc: 40 a2 ff f4 bne 1f0 <copy_user_page+0x28>
200: 83 c1 00 08 lwz r30,8(r1)
204: 80 01 00 14 lwz r0,20(r1)
208: 38 21 00 10 addi r1,r1,16
20c: 7c 08 03 a6 mtlr r0
210: 4e 80 00 20 blr
00000214 <flush_icache_user_range>:
214: 7c 08 02 a6 mflr r0
218: 90 01 00 04 stw r0,4(r1)
21c: 94 21 ff e0 stwu r1,-32(r1)
220: 3c 60 00 00 lis r3,0
222: R_PPC_ADDR16_HA .rodata.str1.1+0x115
224: 93 81 00 10 stw r28,16(r1)
228: 7c 9c 23 78 mr r28,r4
22c: 38 63 00 00 addi r3,r3,0
22e: R_PPC_ADDR16_LO .rodata.str1.1+0x115
230: 38 80 00 53 li r4,83
234: 93 a1 00 14 stw r29,20(r1)
238: 7c bd 2b 78 mr r29,r5
23c: 38 a0 00 00 li r5,0
240: 93 c1 00 18 stw r30,24(r1)
244: 7c de 33 78 mr r30,r6
248: 48 00 00 01 bl 248 <flush_icache_user_range+0x34>
248: R_PPC_PLTREL24 __might_sleep
24c: 3c 60 00 00 lis r3,0
24e: R_PPC_ADDR16_HA mem_map
250: 3c 80 cc cc lis r4,-13108
254: 80 63 00 00 lwz r3,0(r3)
256: R_PPC_ADDR16_LO mem_map
258: 60 84 d0 00 ori r4,r4,53248
25c: 7c 63 e0 50 subf r3,r3,r28
260: 54 63 e8 fe rlwinm r3,r3,29,3,31
264: 7c 63 21 d6 mullw r3,r3,r4
268: 57 a4 05 3e clrlwi r4,r29,20
26c: 50 64 00 26 rlwimi r4,r3,0,0,19
270: 3c 64 c0 00 addis r3,r4,-16384
274: 7c 83 f2 14 add r4,r3,r30
278: 48 00 00 01 bl 278 <flush_icache_user_range+0x64>
278: R_PPC_PLTREL24 flush_icache_range
27c: 83 c1 00 18 lwz r30,24(r1)
280: 83 a1 00 14 lwz r29,20(r1)
284: 83 81 00 10 lwz r28,16(r1)
288: 80 01 00 24 lwz r0,36(r1)
28c: 38 21 00 20 addi r1,r1,32
290: 7c 08 03 a6 mtlr r0
294: 4e 80 00 20 blr
00000298 <update_mmu_cache>:
298: 4e 80 00 20 blr
0000029c <devmem_is_allowed>:
29c: 7c 08 02 a6 mflr r0
2a0: 90 01 00 04 stw r0,4(r1)
2a4: 94 21 ff f0 stwu r1,-16(r1)
2a8: 93 c1 00 08 stw r30,8(r1)
2ac: 7c 7e 1b 78 mr r30,r3
2b0: 54 63 65 3e rlwinm r3,r3,12,20,31
2b4: 57 c4 60 26 rlwinm r4,r30,12,0,19
2b8: 48 00 00 01 bl 2b8 <devmem_is_allowed+0x1c>
2b8: R_PPC_PLTREL24 iomem_is_exclusive
2bc: 70 63 00 01 andi. r3,r3,1
2c0: 38 60 00 00 li r3,0
2c4: 41 81 00 14 bgt 2d8 <devmem_is_allowed+0x3c>
2c8: 7f c3 f3 78 mr r3,r30
2cc: 48 00 00 01 bl 2cc <devmem_is_allowed+0x30>
2cc: R_PPC_PLTREL24 page_is_ram
2d0: 7c 63 00 34 cntlzw r3,r3
2d4: 54 63 df fe rlwinm r3,r3,27,31,31
2d8: 83 c1 00 08 lwz r30,8(r1)
2dc: 80 01 00 14 lwz r0,20(r1)
2e0: 38 21 00 10 addi r1,r1,16
2e4: 7c 08 03 a6 mtlr r0
2e8: 4e 80 00 20 blr
Disassembly of section .init.text:
00000000 <mem_topology_setup>:
0: 7c 08 02 a6 mflr r0
4: 90 01 00 04 stw r0,4(r1)
8: 94 21 ff f0 stwu r1,-16(r1)
c: 48 00 00 01 bl c <mem_topology_setup+0xc>
c: R_PPC_PLTREL24 memblock_end_of_DRAM
10: 54 84 a0 3e rotlwi r4,r4,20
14: 3c a0 00 00 lis r5,0
16: R_PPC_ADDR16_HA max_pfn
18: 50 64 a0 16 rlwimi r4,r3,20,0,11
1c: 3c 60 00 00 lis r3,0
1e: R_PPC_ADDR16_HA max_low_pfn
20: 90 85 00 00 stw r4,0(r5)
22: R_PPC_ADDR16_LO max_pfn
24: 38 a0 ff ff li r5,-1
28: 90 83 00 00 stw r4,0(r3)
2a: R_PPC_ADDR16_LO max_low_pfn
2c: 3c 60 00 00 lis r3,0
2e: R_PPC_ADDR16_HA min_low_pfn
30: 38 80 00 00 li r4,0
34: 38 c0 ff ff li r6,-1
38: 39 00 00 00 li r8,0
3c: 90 83 00 00 stw r4,0(r3)
3e: R_PPC_ADDR16_LO min_low_pfn
40: 3c 60 00 00 lis r3,0
42: R_PPC_ADDR16_HA memblock
44: 38 80 00 00 li r4,0
48: 38 63 00 00 addi r3,r3,0
4a: R_PPC_ADDR16_LO memblock
4c: 38 e3 00 10 addi r7,r3,16
50: 38 60 00 00 li r3,0
54: 48 00 00 01 bl 54 <mem_topology_setup+0x54>
54: R_PPC_PLTREL24 memblock_set_node
58: 80 01 00 14 lwz r0,20(r1)
5c: 38 21 00 10 addi r1,r1,16
60: 7c 08 03 a6 mtlr r0
64: 4e 80 00 20 blr
00000068 <initmem_init>:
68: 7c 08 02 a6 mflr r0
6c: 90 01 00 04 stw r0,4(r1)
70: 94 21 ff f0 stwu r1,-16(r1)
74: 38 60 00 00 li r3,0
78: 48 00 00 01 bl 78 <initmem_init+0x10>
78: R_PPC_PLTREL24 sparse_memory_present_with_active_regions
7c: 80 01 00 14 lwz r0,20(r1)
80: 38 21 00 10 addi r1,r1,16
84: 7c 08 03 a6 mtlr r0
88: 4e 80 00 20 blr
0000008c <paging_init>:
8c: 7c 08 02 a6 mflr r0
90: 90 01 00 04 stw r0,4(r1)
94: 94 21 ff d0 stwu r1,-48(r1)
98: 93 21 00 14 stw r25,20(r1)
9c: 93 41 00 18 stw r26,24(r1)
a0: 93 61 00 1c stw r27,28(r1)
a4: 93 81 00 20 stw r28,32(r1)
a8: 93 a1 00 24 stw r29,36(r1)
ac: 93 c1 00 28 stw r30,40(r1)
b0: 48 00 00 01 bl b0 <paging_init+0x24>
b0: R_PPC_PLTREL24 memblock_phys_mem_size
b4: 7c 7e 1b 78 mr r30,r3
b8: 7c 9d 23 78 mr r29,r4
bc: 3f 40 ff fe lis r26,-2
c0: 48 00 00 01 bl c0 <paging_init+0x34>
c0: R_PPC_PLTREL24 memblock_end_of_DRAM
c4: 7c 7c 1b 78 mr r28,r3
c8: 7c 9b 23 78 mr r27,r4
cc: 3b 20 00 00 li r25,0
d0: 38 e1 00 08 addi r7,r1,8
d4: 7f 43 d3 78 mr r3,r26
d8: 93 21 00 10 stw r25,16(r1)
dc: 38 a0 00 00 li r5,0
e0: 38 c0 00 00 li r6,0
e4: 93 21 00 08 stw r25,8(r1)
e8: 48 00 00 01 bl e8 <paging_init+0x5c>
e8: R_PPC_PLTREL24 map_kernel_page
ec: 3b 5a 10 00 addi r26,r26,4096
f0: 2c 1a f0 00 cmpwi r26,-4096
f4: 40 82 ff dc bne d0 <paging_init+0x44>
f8: 3c 60 00 00 lis r3,0
fa: R_PPC_ADDR16_HA .rodata.str1.1
fc: 4c c6 31 82 crclr 4*cr1+eq
100: 7f 85 e3 78 mr r5,r28
104: 38 63 00 00 addi r3,r3,0
106: R_PPC_ADDR16_LO .rodata.str1.1
108: 7f 66 db 78 mr r6,r27
10c: 7f c7 f3 78 mr r7,r30
110: 7f a8 eb 78 mr r8,r29
114: 48 00 00 01 bl 114 <paging_init+0x88>
114: R_PPC_PLTREL24 printk
118: 7c 7d d8 10 subfc r3,r29,r27
11c: 4c c6 31 82 crclr 4*cr1+eq
120: 7c be e1 10 subfe r5,r30,r28
124: 54 64 60 3e rotlwi r4,r3,12
128: 3c 60 00 00 lis r3,0
12a: R_PPC_ADDR16_HA .rodata.str1.1+0x29
12c: 50 a4 60 26 rlwimi r4,r5,12,0,19
130: 38 63 00 00 addi r3,r3,0
132: R_PPC_ADDR16_LO .rodata.str1.1+0x29
134: 48 00 00 01 bl 134 <paging_init+0xa8>
134: R_PPC_PLTREL24 printk
138: 3c 60 00 00 lis r3,0
13a: R_PPC_ADDR16_HA max_low_pfn
13c: 80 83 00 00 lwz r4,0(r3)
13e: R_PPC_ADDR16_LO max_low_pfn
140: 3c 60 00 00 lis r3,0
142: R_PPC_ADDR16_HA .bss+0x10
144: 94 83 00 00 stwu r4,0(r3)
146: R_PPC_ADDR16_LO .bss+0x10
148: 48 00 00 01 bl 148 <paging_init+0xbc>
148: R_PPC_PLTREL24 free_area_init_nodes
14c: 83 c1 00 28 lwz r30,40(r1)
150: 83 a1 00 24 lwz r29,36(r1)
154: 83 81 00 20 lwz r28,32(r1)
158: 83 61 00 1c lwz r27,28(r1)
15c: 83 41 00 18 lwz r26,24(r1)
160: 83 21 00 14 lwz r25,20(r1)
164: 80 01 00 34 lwz r0,52(r1)
168: 38 21 00 30 addi r1,r1,48
16c: 7c 08 03 a6 mtlr r0
170: 4e 80 00 20 blr
00000174 <mem_init>:
174: 7c 08 02 a6 mflr r0
178: 90 01 00 04 stw r0,4(r1)
17c: 94 21 ff e0 stwu r1,-32(r1)
180: 3c 60 00 00 lis r3,0
182: R_PPC_ADDR16_HA max_low_pfn
184: 3c 80 00 00 lis r4,0
186: R_PPC_ADDR16_HA max_pfn
188: 93 81 00 10 stw r28,16(r1)
18c: 3f 80 00 00 lis r28,0
18e: R_PPC_ADDR16_HA high_memory
190: 80 63 00 00 lwz r3,0(r3)
192: R_PPC_ADDR16_LO max_low_pfn
194: 80 84 00 00 lwz r4,0(r4)
196: R_PPC_ADDR16_LO max_pfn
198: 54 63 60 26 rlwinm r3,r3,12,0,19
19c: 3c 63 c0 00 addis r3,r3,-16384
1a0: 90 7c 00 00 stw r3,0(r28)
1a2: R_PPC_ADDR16_LO high_memory
1a4: 3c 60 00 00 lis r3,0
1a6: R_PPC_ADDR16_HA max_mapnr
1a8: 93 a1 00 14 stw r29,20(r1)
1ac: 93 c1 00 18 stw r30,24(r1)
1b0: 90 83 00 00 stw r4,0(r3)
1b2: R_PPC_ADDR16_LO max_mapnr
1b4: 48 00 00 01 bl 1b4 <mem_init+0x40>
1b4: R_PPC_PLTREL24 memblock_free_all
1b8: 38 60 00 00 li r3,0
1bc: 48 00 00 01 bl 1bc <mem_init+0x48>
1bc: R_PPC_PLTREL24 mem_init_print_info
1c0: 3c 60 00 00 lis r3,0
1c2: R_PPC_ADDR16_HA .rodata.str1.1+0x44
1c4: 4c c6 31 82 crclr 4*cr1+eq
1c8: 38 63 00 00 addi r3,r3,0
1ca: R_PPC_ADDR16_LO .rodata.str1.1+0x44
1cc: 48 00 00 01 bl 1cc <mem_init+0x58>
1cc: R_PPC_PLTREL24 printk
1d0: 3c 80 ff fd lis r4,-3
1d4: 3c 60 00 00 lis r3,0
1d6: R_PPC_ADDR16_HA .rodata.str1.1+0x65
1d8: 4c c6 31 82 crclr 4*cr1+eq
1dc: 60 9e f0 00 ori r30,r4,61440
1e0: 38 63 00 00 addi r3,r3,0
1e2: R_PPC_ADDR16_LO .rodata.str1.1+0x65
1e4: 7f c4 f3 78 mr r4,r30
1e8: 38 a0 f0 00 li r5,-4096
1ec: 48 00 00 01 bl 1ec <mem_init+0x78>
1ec: R_PPC_PLTREL24 printk
1f0: 3c 80 ff dd lis r4,-35
1f4: 3c 60 00 00 lis r3,0
1f6: R_PPC_ADDR16_HA .rodata.str1.1+0x87
1f8: 4c c6 31 82 crclr 4*cr1+eq
1fc: 60 9d f0 00 ori r29,r4,61440
200: 38 63 00 00 addi r3,r3,0
202: R_PPC_ADDR16_LO .rodata.str1.1+0x87
204: 7f a4 eb 78 mr r4,r29
208: 7f c5 f3 78 mr r5,r30
20c: 48 00 00 01 bl 20c <mem_init+0x98>
20c: R_PPC_PLTREL24 printk
210: 3f c0 00 00 lis r30,0
212: R_PPC_ADDR16_HA ioremap_bot
214: 3c 60 00 00 lis r3,0
216: R_PPC_ADDR16_HA .rodata.str1.1+0xb1
218: 4c c6 31 82 crclr 4*cr1+eq
21c: 80 9e 00 00 lwz r4,0(r30)
21e: R_PPC_ADDR16_LO ioremap_bot
220: 38 63 00 00 addi r3,r3,0
222: R_PPC_ADDR16_LO .rodata.str1.1+0xb1
224: 7f a5 eb 78 mr r5,r29
228: 48 00 00 01 bl 228 <mem_init+0xb4>
228: R_PPC_PLTREL24 printk
22c: 80 7c 00 00 lwz r3,0(r28)
22e: R_PPC_ADDR16_LO high_memory
230: 3c 80 01 00 lis r4,256
234: 4c c6 31 82 crclr 4*cr1+eq
238: 38 63 ff ff addi r3,r3,-1
23c: 80 be 00 00 lwz r5,0(r30)
23e: R_PPC_ADDR16_LO ioremap_bot
240: 3c 63 10 00 addis r3,r3,4096
244: 54 63 00 06 rlwinm r3,r3,0,0,3
248: 50 64 02 0c rlwimi r4,r3,0,8,6
24c: 3c 60 00 00 lis r3,0
24e: R_PPC_ADDR16_HA .rodata.str1.1+0xda
250: 38 63 00 00 addi r3,r3,0
252: R_PPC_ADDR16_LO .rodata.str1.1+0xda
254: 48 00 00 01 bl 254 <mem_init+0xe0>
254: R_PPC_PLTREL24 printk
258: 83 c1 00 18 lwz r30,24(r1)
25c: 83 a1 00 14 lwz r29,20(r1)
260: 83 81 00 10 lwz r28,16(r1)
264: 80 01 00 24 lwz r0,36(r1)
268: 38 21 00 20 addi r1,r1,32
26c: 7c 08 03 a6 mtlr r0
270: 4e 80 00 20 blr
00000274 <add_system_ram_resources>:
274: 7c 08 02 a6 mflr r0
278: 90 01 00 04 stw r0,4(r1)
27c: 94 21 ff c0 stwu r1,-64(r1)
280: 3c 60 00 00 lis r3,0
282: R_PPC_ADDR16_HA memblock
284: 93 a1 00 34 stw r29,52(r1)
288: 3b a3 00 00 addi r29,r3,0
28a: R_PPC_ADDR16_LO memblock
28c: 80 7d 00 10 lwz r3,16(r29)
290: 93 81 00 30 stw r28,48(r1)
294: 1c 63 00 18 mulli r3,r3,24
298: 83 9d 00 20 lwz r28,32(r29)
29c: 7c 7c 1a 14 add r3,r28,r3
2a0: 92 a1 00 14 stw r21,20(r1)
2a4: 7c 1c 18 40 cmplw r28,r3
2a8: 92 c1 00 18 stw r22,24(r1)
2ac: 92 e1 00 1c stw r23,28(r1)
2b0: 93 01 00 20 stw r24,32(r1)
2b4: 93 21 00 24 stw r25,36(r1)
2b8: 93 41 00 28 stw r26,40(r1)
2bc: 93 61 00 2c stw r27,44(r1)
2c0: 93 c1 00 38 stw r30,56(r1)
2c4: 40 80 00 ac bge 370 <add_system_ram_resources+0xfc>
2c8: 3c 60 00 00 lis r3,0
2ca: R_PPC_ADDR16_HA kmalloc_caches
2cc: 3c 80 00 00 lis r4,0
2ce: R_PPC_ADDR16_HA .rodata.str1.1+0x199
2d0: 3c a0 81 00 lis r5,-32512
2d4: 3c c0 00 00 lis r6,0
2d6: R_PPC_ADDR16_HA iomem_resource
2d8: 3b 7c ff e8 addi r27,r28,-24
2dc: 3b 40 00 00 li r26,0
2e0: 3b 23 00 00 addi r25,r3,0
2e2: R_PPC_ADDR16_LO kmalloc_caches
2e4: 3b 04 00 00 addi r24,r4,0
2e6: R_PPC_ADDR16_LO .rodata.str1.1+0x199
2e8: 60 b7 02 00 ori r23,r5,512
2ec: 3b c6 00 00 addi r30,r6,0
2ee: R_PPC_ADDR16_LO iomem_resource
2f0: 80 79 00 18 lwz r3,24(r25)
2f4: 38 80 0d c0 li r4,3520
2f8: 38 a0 00 28 li r5,40
2fc: 82 db 00 1c lwz r22,28(r27)
300: 82 bb 00 24 lwz r21,36(r27)
304: 48 00 00 01 bl 304 <add_system_ram_resources+0x90>
304: R_PPC_PLTREL24 kmem_cache_alloc_trace
308: 7c 64 1b 78 mr r4,r3
30c: 7c 63 00 34 cntlzw r3,r3
310: 28 04 00 00 cmplwi r4,0
314: 54 63 df fe rlwinm r3,r3,27,31,31
318: 0f 03 00 00 twnei r3,0
31c: 41 82 00 34 beq 350 <add_system_ram_resources+0xdc>
320: 7c 76 aa 14 add r3,r22,r21
324: 93 04 00 10 stw r24,16(r4)
328: 38 63 ff ff addi r3,r3,-1
32c: 90 64 00 0c stw r3,12(r4)
330: 7f c3 f3 78 mr r3,r30
334: 93 44 00 00 stw r26,0(r4)
338: 92 c4 00 04 stw r22,4(r4)
33c: 93 44 00 08 stw r26,8(r4)
340: 92 e4 00 14 stw r23,20(r4)
344: 48 00 00 01 bl 344 <add_system_ram_resources+0xd0>
344: R_PPC_PLTREL24 request_resource
348: 54 63 0f fe rlwinm r3,r3,1,31,31
34c: 0f 03 00 00 twnei r3,0
350: 80 7d 00 10 lwz r3,16(r29)
354: 3b 9c 00 18 addi r28,r28,24
358: 3b 7b 00 18 addi r27,r27,24
35c: 80 9d 00 20 lwz r4,32(r29)
360: 1c 63 00 18 mulli r3,r3,24
364: 7c 64 1a 14 add r3,r4,r3
368: 7c 1c 18 40 cmplw r28,r3
36c: 41 80 ff 84 blt 2f0 <add_system_ram_resources+0x7c>
370: 38 60 00 00 li r3,0
374: 83 c1 00 38 lwz r30,56(r1)
378: 83 a1 00 34 lwz r29,52(r1)
37c: 83 81 00 30 lwz r28,48(r1)
380: 83 61 00 2c lwz r27,44(r1)
384: 83 41 00 28 lwz r26,40(r1)
388: 83 21 00 24 lwz r25,36(r1)
38c: 83 01 00 20 lwz r24,32(r1)
390: 82 e1 00 1c lwz r23,28(r1)
394: 82 c1 00 18 lwz r22,24(r1)
398: 82 a1 00 14 lwz r21,20(r1)
39c: 80 01 00 44 lwz r0,68(r1)
3a0: 38 21 00 40 addi r1,r1,64
3a4: 7c 08 03 a6 mtlr r0
3a8: 4e 80 00 20 blr
[-- Attachment #4: mem-diff.txt --]
[-- Type: text/plain, Size: 40265 bytes --]
mem-working.o: file format elf32-powerpc | mem-broken.o: file format elf32-powerpc
Disassembly of section .text: Disassembly of section .text:
00000000 <phys_mem_access_prot>: 00000000 <phys_mem_access_prot>:
0: 7c 08 02 a6 mflr r0 0: 7c 08 02 a6 mflr r0
4: 90 01 00 04 stw r0,4(r1) 4: 90 01 00 04 stw r0,4(r1)
8: 94 21 ff e0 stwu r1,-32(r1) 8: 94 21 ff e0 stwu r1,-32(r1)
c: 93 a1 00 14 stw r29,20(r1) c: 93 a1 00 14 stw r29,20(r1)
10: 7c fd 3b 78 mr r29,r7 10: 7c fd 3b 78 mr r29,r7
14: 3c e0 00 00 lis r7,0 14: 3c e0 00 00 lis r7,0
16: R_PPC_ADDR16_HA ppc_md 16: R_PPC_ADDR16_HA ppc_md
18: 38 e7 00 00 addi r7,r7,0 18: 38 e7 00 00 addi r7,r7,0
1a: R_PPC_ADDR16_LO ppc_md 1a: R_PPC_ADDR16_LO ppc_md
1c: 81 07 00 a0 lwz r8,160(r7) 1c: 81 07 00 a0 lwz r8,160(r7)
20: 93 c1 00 18 stw r30,24(r1) 20: 93 c1 00 18 stw r30,24(r1)
24: 28 08 00 00 cmplwi r8,0 24: 28 08 00 00 cmplwi r8,0
28: 7c 7e 1b 78 mr r30,r3 28: 7c 7e 1b 78 mr r30,r3
2c: 41 82 00 20 beq 4c <phys_mem_access_prot+0x4c 2c: 41 82 00 20 beq 4c <phys_mem_access_prot+0x4c
30: 80 7d 00 00 lwz r3,0(r29) 30: 80 7d 00 00 lwz r3,0(r29)
34: 38 e1 00 08 addi r7,r1,8 34: 38 e1 00 08 addi r7,r1,8
38: 7d 09 03 a6 mtctr r8 38: 7d 09 03 a6 mtctr r8
3c: 90 61 00 08 stw r3,8(r1) 3c: 90 61 00 08 stw r3,8(r1)
40: 7f c3 f3 78 mr r3,r30 40: 7f c3 f3 78 mr r3,r30
44: 4e 80 04 21 bctrl 44: 4e 80 04 21 bctrl
48: 48 00 00 28 b 70 <phys_mem_access_prot+0x70 48: 48 00 00 28 b 70 <phys_mem_access_prot+0x70
4c: 7c a3 2b 78 mr r3,r5 4c: 7c a3 2b 78 mr r3,r5
50: 48 00 00 01 bl 50 <phys_mem_access_prot+0x50 50: 48 00 00 01 bl 50 <phys_mem_access_prot+0x50
50: R_PPC_PLTREL24 page_is_ram 50: R_PPC_PLTREL24 page_is_ram
54: 28 03 00 00 cmplwi r3,0 54: 28 03 00 00 cmplwi r3,0
58: 80 7d 00 00 lwz r3,0(r29) 58: 80 7d 00 00 lwz r3,0(r29)
5c: 40 82 00 10 bne 6c <phys_mem_access_prot+0x6c 5c: 40 82 00 10 bne 6c <phys_mem_access_prot+0x6c
60: 54 63 06 26 rlwinm r3,r3,0,24,19 60: 54 63 06 26 rlwinm r3,r3,0,24,19
64: 60 63 05 00 ori r3,r3,1280 64: 60 63 05 00 ori r3,r3,1280
68: 90 7d 00 00 stw r3,0(r29) 68: 90 7d 00 00 stw r3,0(r29)
6c: 90 7e 00 00 stw r3,0(r30) 6c: 90 7e 00 00 stw r3,0(r30)
70: 83 c1 00 18 lwz r30,24(r1) 70: 83 c1 00 18 lwz r30,24(r1)
74: 83 a1 00 14 lwz r29,20(r1) 74: 83 a1 00 14 lwz r29,20(r1)
78: 80 01 00 24 lwz r0,36(r1) 78: 80 01 00 24 lwz r0,36(r1)
7c: 38 21 00 20 addi r1,r1,32 7c: 38 21 00 20 addi r1,r1,32
80: 7c 08 03 a6 mtlr r0 80: 7c 08 03 a6 mtlr r0
84: 4e 80 00 20 blr 84: 4e 80 00 20 blr
00000088 <free_initmem>: 00000088 <free_initmem>:
88: 7c 08 02 a6 mflr r0 88: 7c 08 02 a6 mflr r0
8c: 90 01 00 04 stw r0,4(r1) 8c: 90 01 00 04 stw r0,4(r1)
90: 94 21 ff f0 stwu r1,-16(r1) 90: 94 21 ff f0 stwu r1,-16(r1)
94: 3c 60 00 00 lis r3,0 94: 3c 60 00 00 lis r3,0
96: R_PPC_ADDR16_HA ppc_md 96: R_PPC_ADDR16_HA ppc_md
98: 3c 80 00 00 lis r4,0 98: 3c 80 00 00 lis r4,0
9a: R_PPC_ADDR16_HA ppc_printk_pr 9a: R_PPC_ADDR16_HA ppc_printk_pr
9c: 38 63 00 00 addi r3,r3,0 9c: 38 63 00 00 addi r3,r3,0
9e: R_PPC_ADDR16_LO ppc_md 9e: R_PPC_ADDR16_LO ppc_md
a0: 38 84 00 00 addi r4,r4,0 a0: 38 84 00 00 addi r4,r4,0
a2: R_PPC_ADDR16_LO ppc_printk_pr a2: R_PPC_ADDR16_LO ppc_printk_pr
a4: 90 83 00 60 stw r4,96(r3) a4: 90 83 00 60 stw r4,96(r3)
a8: 48 00 00 01 bl a8 <free_initmem+0x20> a8: 48 00 00 01 bl a8 <free_initmem+0x20>
a8: R_PPC_PLTREL24 mark_initmem_ a8: R_PPC_PLTREL24 mark_initmem_
ac: 3c 60 00 00 lis r3,0 ac: 3c 60 00 00 lis r3,0
ae: R_PPC_ADDR16_HA init_mem_is_f ae: R_PPC_ADDR16_HA init_mem_is_f
b0: 38 80 00 01 li r4,1 b0: 38 80 00 01 li r4,1
b4: 98 83 00 00 stb r4,0(r3) b4: 98 83 00 00 stb r4,0(r3)
b6: R_PPC_ADDR16_LO init_mem_is_f b6: R_PPC_ADDR16_LO init_mem_is_f
b8: 3c 60 00 00 lis r3,0 b8: 3c 60 00 00 lis r3,0
ba: R_PPC_ADDR16_HA __init_begin ba: R_PPC_ADDR16_HA __init_begin
bc: 3c 80 00 00 lis r4,0 bc: 3c 80 00 00 lis r4,0
be: R_PPC_ADDR16_HA __init_end be: R_PPC_ADDR16_HA __init_end
c0: 3c a0 00 00 lis r5,0 c0: 3c a0 00 00 lis r5,0
c2: R_PPC_ADDR16_HA .rodata.str1. c2: R_PPC_ADDR16_HA .rodata.str1.
c4: 38 63 00 00 addi r3,r3,0 c4: 38 63 00 00 addi r3,r3,0
c6: R_PPC_ADDR16_LO __init_begin c6: R_PPC_ADDR16_LO __init_begin
c8: 38 84 00 00 addi r4,r4,0 c8: 38 84 00 00 addi r4,r4,0
ca: R_PPC_ADDR16_LO __init_end ca: R_PPC_ADDR16_LO __init_end
cc: 38 c5 00 00 addi r6,r5,0 cc: 38 c5 00 00 addi r6,r5,0
ce: R_PPC_ADDR16_LO .rodata.str1. ce: R_PPC_ADDR16_LO .rodata.str1.
d0: 38 a0 00 cc li r5,204 d0: 38 a0 00 cc li r5,204
d4: 48 00 00 01 bl d4 <free_initmem+0x4c> d4: 48 00 00 01 bl d4 <free_initmem+0x4c>
d4: R_PPC_PLTREL24 free_reserved d4: R_PPC_PLTREL24 free_reserved
d8: 80 01 00 14 lwz r0,20(r1) d8: 80 01 00 14 lwz r0,20(r1)
dc: 38 21 00 10 addi r1,r1,16 dc: 38 21 00 10 addi r1,r1,16
e0: 7c 08 03 a6 mtlr r0 e0: 7c 08 03 a6 mtlr r0
e4: 4e 80 00 20 blr e4: 4e 80 00 20 blr
000000e8 <flush_dcache_page>: 000000e8 <flush_dcache_page>:
e8: 80 83 00 00 lwz r4,0(r3) e8: 80 83 00 00 lwz r4,0(r3)
ec: 70 84 08 00 andi. r4,r4,2048 ec: 70 84 08 00 andi. r4,r4,2048
f0: 4d 82 00 20 beqlr f0: 4d 82 00 20 beqlr
f4: 38 80 08 00 li r4,2048 f4: 38 80 08 00 li r4,2048
f8: 7c a0 18 28 lwarx r5,0,r3 f8: 7c a0 18 28 lwarx r5,0,r3
fc: 7c a5 20 78 andc r5,r5,r4 fc: 7c a5 20 78 andc r5,r5,r4
100: 7c a0 19 2d stwcx. r5,0,r3 100: 7c a0 19 2d stwcx. r5,0,r3
104: 40 a2 ff f4 bne f8 <flush_dcache_page+0x10> 104: 40 a2 ff f4 bne f8 <flush_dcache_page+0x10>
108: 4e 80 00 20 blr 108: 4e 80 00 20 blr
0000010c <flush_dcache_icache_page>: 0000010c <flush_dcache_icache_page>:
10c: 7c 08 02 a6 mflr r0 10c: 7c 08 02 a6 mflr r0
110: 90 01 00 04 stw r0,4(r1) 110: 90 01 00 04 stw r0,4(r1)
114: 94 21 ff f0 stwu r1,-16(r1) 114: 94 21 ff f0 stwu r1,-16(r1)
118: 80 82 00 00 lwz r4,0(r2) 118: 80 82 00 00 lwz r4,0(r2)
11c: 38 84 00 01 addi r4,r4,1 11c: 38 84 00 01 addi r4,r4,1
120: 90 82 00 00 stw r4,0(r2) 120: 90 82 00 00 stw r4,0(r2)
124: 80 82 0a e4 lwz r4,2788(r2) 124: 80 82 0a e4 lwz r4,2788(r2)
128: 38 84 00 01 addi r4,r4,1 128: 38 84 00 01 addi r4,r4,1
12c: 90 82 0a e4 stw r4,2788(r2) 12c: 90 82 0a e4 stw r4,2788(r2)
130: 3c 80 00 00 lis r4,0 130: 3c 80 00 00 lis r4,0
132: R_PPC_ADDR16_HA mem_map 132: R_PPC_ADDR16_HA mem_map
134: 80 84 00 00 lwz r4,0(r4) 134: 80 84 00 00 lwz r4,0(r4)
136: R_PPC_ADDR16_LO mem_map 136: R_PPC_ADDR16_LO mem_map
138: 7c 64 18 50 subf r3,r4,r3 138: 7c 64 18 50 subf r3,r4,r3
13c: 3c 80 cc cc lis r4,-13108 13c: 3c 80 cc cc lis r4,-13108
140: 54 63 e8 fe rlwinm r3,r3,29,3,31 140: 54 63 e8 fe rlwinm r3,r3,29,3,31
144: 60 84 d0 00 ori r4,r4,53248 144: 60 84 d0 00 ori r4,r4,53248
148: 7c 63 21 d6 mullw r3,r3,r4 148: 7c 63 21 d6 mullw r3,r3,r4
14c: 3c 63 c0 00 addis r3,r3,-16384 14c: 3c 63 c0 00 addis r3,r3,-16384
150: 48 00 00 01 bl 150 <flush_dcache_icache_page 150: 48 00 00 01 bl 150 <flush_dcache_icache_page
150: R_PPC_PLTREL24 __flush_dcach 150: R_PPC_PLTREL24 __flush_dcach
154: 80 62 0a e4 lwz r3,2788(r2) 154: 80 62 0a e4 lwz r3,2788(r2)
158: 38 63 ff ff addi r3,r3,-1 158: 38 63 ff ff addi r3,r3,-1
15c: 90 62 0a e4 stw r3,2788(r2) 15c: 90 62 0a e4 stw r3,2788(r2)
160: 80 62 00 00 lwz r3,0(r2) 160: 80 62 00 00 lwz r3,0(r2)
164: 38 63 ff ff addi r3,r3,-1 164: 38 63 ff ff addi r3,r3,-1
168: 90 62 00 00 stw r3,0(r2) 168: 90 62 00 00 stw r3,0(r2)
16c: 80 01 00 14 lwz r0,20(r1) 16c: 80 01 00 14 lwz r0,20(r1)
170: 38 21 00 10 addi r1,r1,16 170: 38 21 00 10 addi r1,r1,16
174: 7c 08 03 a6 mtlr r0 174: 7c 08 03 a6 mtlr r0
178: 4e 80 00 20 blr 178: 4e 80 00 20 blr
0000017c <clear_user_page>: 0000017c <clear_user_page>:
17c: 38 80 00 80 li r4,128 | 17c: 94 21 ff f0 stwu r1,-16(r1)
180: 7c 89 03 a6 mtctr r4 | 180: 38 80 00 80 li r4,128
184: 7c 00 1f ec dcbz 0,r3 | 184: 38 63 ff e0 addi r3,r3,-32
188: 38 63 00 20 addi r3,r3,32 | 188: 7c 89 03 a6 mtctr r4
18c: 42 00 ff f8 bdnz 184 <clear_user_page+0x8> | 18c: 38 81 00 0f addi r4,r1,15
190: 80 65 00 00 lwz r3,0(r5) | 190: 8c c3 00 20 lbzu r6,32(r3)
194: 70 63 08 00 andi. r3,r3,2048 | 194: 98 c1 00 0f stb r6,15(r1)
198: 4d 82 00 20 beqlr | 198: 7c 00 27 ec dcbz 0,r4
19c: 38 60 08 00 li r3,2048 | 19c: 42 00 ff f4 bdnz 190 <clear_user_page+0x14>
1a0: 7c 80 28 28 lwarx r4,0,r5 | 1a0: 80 65 00 00 lwz r3,0(r5)
1a4: 7c 84 18 78 andc r4,r4,r3 | 1a4: 70 63 08 00 andi. r3,r3,2048
1a8: 7c 80 29 2d stwcx. r4,0,r5 | 1a8: 41 82 00 18 beq 1c0 <clear_user_page+0x44>
1ac: 40 a2 ff f4 bne 1a0 <clear_user_page+0x24> | 1ac: 38 60 08 00 li r3,2048
1b0: 4e 80 00 20 blr | 1b0: 7c 80 28 28 lwarx r4,0,r5
| 1b4: 7c 84 18 78 andc r4,r4,r3
000001b4 <copy_user_page>: | 1b8: 7c 80 29 2d stwcx. r4,0,r5
1b4: 7c 08 02 a6 mflr r0 | 1bc: 40 a2 ff f4 bne 1b0 <clear_user_page+0x34>
1b8: 90 01 00 04 stw r0,4(r1) | 1c0: 38 21 00 10 addi r1,r1,16
1bc: 94 21 ff f0 stwu r1,-16(r1) | 1c4: 4e 80 00 20 blr
1c0: 93 c1 00 08 stw r30,8(r1) |
1c4: 7c de 33 78 mr r30,r6 | 000001c8 <copy_user_page>:
1c8: 48 00 00 01 bl 1c8 <copy_user_page+0x14> | 1c8: 7c 08 02 a6 mflr r0
1c8: R_PPC_PLTREL24 copy_page | 1cc: 90 01 00 04 stw r0,4(r1)
1cc: 80 7e 00 00 lwz r3,0(r30) | 1d0: 94 21 ff f0 stwu r1,-16(r1)
1d0: 70 63 08 00 andi. r3,r3,2048 | 1d4: 93 c1 00 08 stw r30,8(r1)
1d4: 41 82 00 18 beq 1ec <copy_user_page+0x38> | 1d8: 7c de 33 78 mr r30,r6
1d8: 38 60 08 00 li r3,2048 | 1dc: 48 00 00 01 bl 1dc <copy_user_page+0x14>
1dc: 7c 80 f0 28 lwarx r4,0,r30 | 1dc: R_PPC_PLTREL24 copy_page
1e0: 7c 84 18 78 andc r4,r4,r3 | 1e0: 80 7e 00 00 lwz r3,0(r30)
1e4: 7c 80 f1 2d stwcx. r4,0,r30 | 1e4: 70 63 08 00 andi. r3,r3,2048
1e8: 40 a2 ff f4 bne 1dc <copy_user_page+0x28> | 1e8: 41 82 00 18 beq 200 <copy_user_page+0x38>
1ec: 83 c1 00 08 lwz r30,8(r1) | 1ec: 38 60 08 00 li r3,2048
1f0: 80 01 00 14 lwz r0,20(r1) | 1f0: 7c 80 f0 28 lwarx r4,0,r30
1f4: 38 21 00 10 addi r1,r1,16 | 1f4: 7c 84 18 78 andc r4,r4,r3
1f8: 7c 08 03 a6 mtlr r0 | 1f8: 7c 80 f1 2d stwcx. r4,0,r30
1fc: 4e 80 00 20 blr | 1fc: 40 a2 ff f4 bne 1f0 <copy_user_page+0x28>
| 200: 83 c1 00 08 lwz r30,8(r1)
00000200 <flush_icache_user_range>: | 204: 80 01 00 14 lwz r0,20(r1)
200: 7c 08 02 a6 mflr r0 | 208: 38 21 00 10 addi r1,r1,16
204: 90 01 00 04 stw r0,4(r1) | 20c: 7c 08 03 a6 mtlr r0
208: 94 21 ff e0 stwu r1,-32(r1) | 210: 4e 80 00 20 blr
20c: 3c 60 00 00 lis r3,0 |
20e: R_PPC_ADDR16_HA .rodata.str1. | 00000214 <flush_icache_user_range>:
210: 93 81 00 10 stw r28,16(r1) | 214: 7c 08 02 a6 mflr r0
214: 7c 9c 23 78 mr r28,r4 | 218: 90 01 00 04 stw r0,4(r1)
218: 38 63 00 00 addi r3,r3,0 | 21c: 94 21 ff e0 stwu r1,-32(r1)
21a: R_PPC_ADDR16_LO .rodata.str1. | 220: 3c 60 00 00 lis r3,0
21c: 38 80 00 53 li r4,83 | 222: R_PPC_ADDR16_HA .rodata.str1.
220: 93 a1 00 14 stw r29,20(r1) | 224: 93 81 00 10 stw r28,16(r1)
224: 7c bd 2b 78 mr r29,r5 | 228: 7c 9c 23 78 mr r28,r4
228: 38 a0 00 00 li r5,0 | 22c: 38 63 00 00 addi r3,r3,0
22c: 93 c1 00 18 stw r30,24(r1) | 22e: R_PPC_ADDR16_LO .rodata.str1.
230: 7c de 33 78 mr r30,r6 | 230: 38 80 00 53 li r4,83
234: 48 00 00 01 bl 234 <flush_icache_user_range+ | 234: 93 a1 00 14 stw r29,20(r1)
234: R_PPC_PLTREL24 __might_sleep | 238: 7c bd 2b 78 mr r29,r5
238: 3c 60 00 00 lis r3,0 | 23c: 38 a0 00 00 li r5,0
23a: R_PPC_ADDR16_HA mem_map | 240: 93 c1 00 18 stw r30,24(r1)
23c: 3c 80 cc cc lis r4,-13108 | 244: 7c de 33 78 mr r30,r6
240: 80 63 00 00 lwz r3,0(r3) | 248: 48 00 00 01 bl 248 <flush_icache_user_range+
242: R_PPC_ADDR16_LO mem_map | 248: R_PPC_PLTREL24 __might_sleep
244: 60 84 d0 00 ori r4,r4,53248 | 24c: 3c 60 00 00 lis r3,0
248: 7c 63 e0 50 subf r3,r3,r28 | 24e: R_PPC_ADDR16_HA mem_map
24c: 54 63 e8 fe rlwinm r3,r3,29,3,31 | 250: 3c 80 cc cc lis r4,-13108
250: 7c 63 21 d6 mullw r3,r3,r4 | 254: 80 63 00 00 lwz r3,0(r3)
254: 57 a4 05 3e clrlwi r4,r29,20 | 256: R_PPC_ADDR16_LO mem_map
258: 50 64 00 26 rlwimi r4,r3,0,0,19 | 258: 60 84 d0 00 ori r4,r4,53248
25c: 3c 64 c0 00 addis r3,r4,-16384 | 25c: 7c 63 e0 50 subf r3,r3,r28
260: 7c 83 f2 14 add r4,r3,r30 | 260: 54 63 e8 fe rlwinm r3,r3,29,3,31
264: 48 00 00 01 bl 264 <flush_icache_user_range+ | 264: 7c 63 21 d6 mullw r3,r3,r4
264: R_PPC_PLTREL24 flush_icache_ | 268: 57 a4 05 3e clrlwi r4,r29,20
268: 83 c1 00 18 lwz r30,24(r1) | 26c: 50 64 00 26 rlwimi r4,r3,0,0,19
26c: 83 a1 00 14 lwz r29,20(r1) | 270: 3c 64 c0 00 addis r3,r4,-16384
270: 83 81 00 10 lwz r28,16(r1) | 274: 7c 83 f2 14 add r4,r3,r30
274: 80 01 00 24 lwz r0,36(r1) | 278: 48 00 00 01 bl 278 <flush_icache_user_range+
278: 38 21 00 20 addi r1,r1,32 | 278: R_PPC_PLTREL24 flush_icache_
27c: 7c 08 03 a6 mtlr r0 | 27c: 83 c1 00 18 lwz r30,24(r1)
280: 4e 80 00 20 blr | 280: 83 a1 00 14 lwz r29,20(r1)
| 284: 83 81 00 10 lwz r28,16(r1)
00000284 <update_mmu_cache>: | 288: 80 01 00 24 lwz r0,36(r1)
284: 4e 80 00 20 blr | 28c: 38 21 00 20 addi r1,r1,32
| 290: 7c 08 03 a6 mtlr r0
00000288 <devmem_is_allowed>: | 294: 4e 80 00 20 blr
288: 7c 08 02 a6 mflr r0 |
28c: 90 01 00 04 stw r0,4(r1) | 00000298 <update_mmu_cache>:
290: 94 21 ff f0 stwu r1,-16(r1) | 298: 4e 80 00 20 blr
294: 93 c1 00 08 stw r30,8(r1) |
298: 7c 7e 1b 78 mr r30,r3 | 0000029c <devmem_is_allowed>:
29c: 54 63 65 3e rlwinm r3,r3,12,20,31 | 29c: 7c 08 02 a6 mflr r0
2a0: 57 c4 60 26 rlwinm r4,r30,12,0,19 | 2a0: 90 01 00 04 stw r0,4(r1)
2a4: 48 00 00 01 bl 2a4 <devmem_is_allowed+0x1c> | 2a4: 94 21 ff f0 stwu r1,-16(r1)
2a4: R_PPC_PLTREL24 iomem_is_excl | 2a8: 93 c1 00 08 stw r30,8(r1)
2a8: 70 63 00 01 andi. r3,r3,1 | 2ac: 7c 7e 1b 78 mr r30,r3
2ac: 38 60 00 00 li r3,0 | 2b0: 54 63 65 3e rlwinm r3,r3,12,20,31
2b0: 41 81 00 14 bgt 2c4 <devmem_is_allowed+0x3c> | 2b4: 57 c4 60 26 rlwinm r4,r30,12,0,19
2b4: 7f c3 f3 78 mr r3,r30 | 2b8: 48 00 00 01 bl 2b8 <devmem_is_allowed+0x1c>
2b8: 48 00 00 01 bl 2b8 <devmem_is_allowed+0x30> | 2b8: R_PPC_PLTREL24 iomem_is_excl
2b8: R_PPC_PLTREL24 page_is_ram | 2bc: 70 63 00 01 andi. r3,r3,1
2bc: 7c 63 00 34 cntlzw r3,r3 | 2c0: 38 60 00 00 li r3,0
2c0: 54 63 df fe rlwinm r3,r3,27,31,31 | 2c4: 41 81 00 14 bgt 2d8 <devmem_is_allowed+0x3c>
2c4: 83 c1 00 08 lwz r30,8(r1) | 2c8: 7f c3 f3 78 mr r3,r30
2c8: 80 01 00 14 lwz r0,20(r1) | 2cc: 48 00 00 01 bl 2cc <devmem_is_allowed+0x30>
2cc: 38 21 00 10 addi r1,r1,16 | 2cc: R_PPC_PLTREL24 page_is_ram
2d0: 7c 08 03 a6 mtlr r0 | 2d0: 7c 63 00 34 cntlzw r3,r3
2d4: 4e 80 00 20 blr | 2d4: 54 63 df fe rlwinm r3,r3,27,31,31
> 2d8: 83 c1 00 08 lwz r30,8(r1)
> 2dc: 80 01 00 14 lwz r0,20(r1)
> 2e0: 38 21 00 10 addi r1,r1,16
> 2e4: 7c 08 03 a6 mtlr r0
> 2e8: 4e 80 00 20 blr
Disassembly of section .init.text: Disassembly of section .init.text:
00000000 <mem_topology_setup>: 00000000 <mem_topology_setup>:
0: 7c 08 02 a6 mflr r0 0: 7c 08 02 a6 mflr r0
4: 90 01 00 04 stw r0,4(r1) 4: 90 01 00 04 stw r0,4(r1)
8: 94 21 ff f0 stwu r1,-16(r1) 8: 94 21 ff f0 stwu r1,-16(r1)
c: 48 00 00 01 bl c <mem_topology_setup+0xc> c: 48 00 00 01 bl c <mem_topology_setup+0xc>
c: R_PPC_PLTREL24 memblock_end_ c: R_PPC_PLTREL24 memblock_end_
10: 54 84 a0 3e rotlwi r4,r4,20 10: 54 84 a0 3e rotlwi r4,r4,20
14: 3c a0 00 00 lis r5,0 14: 3c a0 00 00 lis r5,0
16: R_PPC_ADDR16_HA max_pfn 16: R_PPC_ADDR16_HA max_pfn
18: 50 64 a0 16 rlwimi r4,r3,20,0,11 18: 50 64 a0 16 rlwimi r4,r3,20,0,11
1c: 3c 60 00 00 lis r3,0 1c: 3c 60 00 00 lis r3,0
1e: R_PPC_ADDR16_HA max_low_pfn 1e: R_PPC_ADDR16_HA max_low_pfn
20: 90 85 00 00 stw r4,0(r5) 20: 90 85 00 00 stw r4,0(r5)
22: R_PPC_ADDR16_LO max_pfn 22: R_PPC_ADDR16_LO max_pfn
24: 38 a0 ff ff li r5,-1 24: 38 a0 ff ff li r5,-1
28: 90 83 00 00 stw r4,0(r3) 28: 90 83 00 00 stw r4,0(r3)
2a: R_PPC_ADDR16_LO max_low_pfn 2a: R_PPC_ADDR16_LO max_low_pfn
2c: 3c 60 00 00 lis r3,0 2c: 3c 60 00 00 lis r3,0
2e: R_PPC_ADDR16_HA min_low_pfn 2e: R_PPC_ADDR16_HA min_low_pfn
30: 38 80 00 00 li r4,0 30: 38 80 00 00 li r4,0
34: 38 c0 ff ff li r6,-1 34: 38 c0 ff ff li r6,-1
38: 39 00 00 00 li r8,0 38: 39 00 00 00 li r8,0
3c: 90 83 00 00 stw r4,0(r3) 3c: 90 83 00 00 stw r4,0(r3)
3e: R_PPC_ADDR16_LO min_low_pfn 3e: R_PPC_ADDR16_LO min_low_pfn
40: 3c 60 00 00 lis r3,0 40: 3c 60 00 00 lis r3,0
42: R_PPC_ADDR16_HA memblock 42: R_PPC_ADDR16_HA memblock
44: 38 80 00 00 li r4,0 44: 38 80 00 00 li r4,0
48: 38 63 00 00 addi r3,r3,0 48: 38 63 00 00 addi r3,r3,0
4a: R_PPC_ADDR16_LO memblock 4a: R_PPC_ADDR16_LO memblock
4c: 38 e3 00 10 addi r7,r3,16 4c: 38 e3 00 10 addi r7,r3,16
50: 38 60 00 00 li r3,0 50: 38 60 00 00 li r3,0
54: 48 00 00 01 bl 54 <mem_topology_setup+0x54> 54: 48 00 00 01 bl 54 <mem_topology_setup+0x54>
54: R_PPC_PLTREL24 memblock_set_ 54: R_PPC_PLTREL24 memblock_set_
58: 80 01 00 14 lwz r0,20(r1) 58: 80 01 00 14 lwz r0,20(r1)
5c: 38 21 00 10 addi r1,r1,16 5c: 38 21 00 10 addi r1,r1,16
60: 7c 08 03 a6 mtlr r0 60: 7c 08 03 a6 mtlr r0
64: 4e 80 00 20 blr 64: 4e 80 00 20 blr
00000068 <initmem_init>: 00000068 <initmem_init>:
68: 7c 08 02 a6 mflr r0 68: 7c 08 02 a6 mflr r0
6c: 90 01 00 04 stw r0,4(r1) 6c: 90 01 00 04 stw r0,4(r1)
70: 94 21 ff f0 stwu r1,-16(r1) 70: 94 21 ff f0 stwu r1,-16(r1)
74: 38 60 00 00 li r3,0 74: 38 60 00 00 li r3,0
78: 48 00 00 01 bl 78 <initmem_init+0x10> 78: 48 00 00 01 bl 78 <initmem_init+0x10>
78: R_PPC_PLTREL24 sparse_memory 78: R_PPC_PLTREL24 sparse_memory
7c: 80 01 00 14 lwz r0,20(r1) 7c: 80 01 00 14 lwz r0,20(r1)
80: 38 21 00 10 addi r1,r1,16 80: 38 21 00 10 addi r1,r1,16
84: 7c 08 03 a6 mtlr r0 84: 7c 08 03 a6 mtlr r0
88: 4e 80 00 20 blr 88: 4e 80 00 20 blr
0000008c <paging_init>: 0000008c <paging_init>:
8c: 7c 08 02 a6 mflr r0 8c: 7c 08 02 a6 mflr r0
90: 90 01 00 04 stw r0,4(r1) 90: 90 01 00 04 stw r0,4(r1)
94: 94 21 ff d0 stwu r1,-48(r1) 94: 94 21 ff d0 stwu r1,-48(r1)
98: 93 21 00 14 stw r25,20(r1) 98: 93 21 00 14 stw r25,20(r1)
9c: 93 41 00 18 stw r26,24(r1) 9c: 93 41 00 18 stw r26,24(r1)
a0: 93 61 00 1c stw r27,28(r1) a0: 93 61 00 1c stw r27,28(r1)
a4: 93 81 00 20 stw r28,32(r1) a4: 93 81 00 20 stw r28,32(r1)
a8: 93 a1 00 24 stw r29,36(r1) a8: 93 a1 00 24 stw r29,36(r1)
ac: 93 c1 00 28 stw r30,40(r1) ac: 93 c1 00 28 stw r30,40(r1)
b0: 48 00 00 01 bl b0 <paging_init+0x24> b0: 48 00 00 01 bl b0 <paging_init+0x24>
b0: R_PPC_PLTREL24 memblock_phys b0: R_PPC_PLTREL24 memblock_phys
b4: 7c 7e 1b 78 mr r30,r3 b4: 7c 7e 1b 78 mr r30,r3
b8: 7c 9d 23 78 mr r29,r4 b8: 7c 9d 23 78 mr r29,r4
bc: 3f 40 ff fe lis r26,-2 bc: 3f 40 ff fe lis r26,-2
c0: 48 00 00 01 bl c0 <paging_init+0x34> c0: 48 00 00 01 bl c0 <paging_init+0x34>
c0: R_PPC_PLTREL24 memblock_end_ c0: R_PPC_PLTREL24 memblock_end_
c4: 7c 7c 1b 78 mr r28,r3 c4: 7c 7c 1b 78 mr r28,r3
c8: 7c 9b 23 78 mr r27,r4 c8: 7c 9b 23 78 mr r27,r4
cc: 3b 20 00 00 li r25,0 cc: 3b 20 00 00 li r25,0
d0: 38 e1 00 08 addi r7,r1,8 d0: 38 e1 00 08 addi r7,r1,8
d4: 7f 43 d3 78 mr r3,r26 d4: 7f 43 d3 78 mr r3,r26
d8: 93 21 00 10 stw r25,16(r1) d8: 93 21 00 10 stw r25,16(r1)
dc: 38 a0 00 00 li r5,0 dc: 38 a0 00 00 li r5,0
e0: 38 c0 00 00 li r6,0 e0: 38 c0 00 00 li r6,0
e4: 93 21 00 08 stw r25,8(r1) e4: 93 21 00 08 stw r25,8(r1)
e8: 48 00 00 01 bl e8 <paging_init+0x5c> e8: 48 00 00 01 bl e8 <paging_init+0x5c>
e8: R_PPC_PLTREL24 map_kernel_pa e8: R_PPC_PLTREL24 map_kernel_pa
ec: 3b 5a 10 00 addi r26,r26,4096 ec: 3b 5a 10 00 addi r26,r26,4096
f0: 2c 1a f0 00 cmpwi r26,-4096 f0: 2c 1a f0 00 cmpwi r26,-4096
f4: 40 82 ff dc bne d0 <paging_init+0x44> f4: 40 82 ff dc bne d0 <paging_init+0x44>
f8: 3c 60 00 00 lis r3,0 f8: 3c 60 00 00 lis r3,0
fa: R_PPC_ADDR16_HA .rodata.str1. fa: R_PPC_ADDR16_HA .rodata.str1.
fc: 4c c6 31 82 crclr 4*cr1+eq fc: 4c c6 31 82 crclr 4*cr1+eq
100: 7f 85 e3 78 mr r5,r28 100: 7f 85 e3 78 mr r5,r28
104: 38 63 00 00 addi r3,r3,0 104: 38 63 00 00 addi r3,r3,0
106: R_PPC_ADDR16_LO .rodata.str1. 106: R_PPC_ADDR16_LO .rodata.str1.
108: 7f 66 db 78 mr r6,r27 108: 7f 66 db 78 mr r6,r27
10c: 7f c7 f3 78 mr r7,r30 10c: 7f c7 f3 78 mr r7,r30
110: 7f a8 eb 78 mr r8,r29 110: 7f a8 eb 78 mr r8,r29
114: 48 00 00 01 bl 114 <paging_init+0x88> 114: 48 00 00 01 bl 114 <paging_init+0x88>
114: R_PPC_PLTREL24 printk 114: R_PPC_PLTREL24 printk
118: 7c 7d d8 10 subfc r3,r29,r27 118: 7c 7d d8 10 subfc r3,r29,r27
11c: 4c c6 31 82 crclr 4*cr1+eq 11c: 4c c6 31 82 crclr 4*cr1+eq
120: 7c be e1 10 subfe r5,r30,r28 120: 7c be e1 10 subfe r5,r30,r28
124: 54 64 60 3e rotlwi r4,r3,12 124: 54 64 60 3e rotlwi r4,r3,12
128: 3c 60 00 00 lis r3,0 128: 3c 60 00 00 lis r3,0
12a: R_PPC_ADDR16_HA .rodata.str1. 12a: R_PPC_ADDR16_HA .rodata.str1.
12c: 50 a4 60 26 rlwimi r4,r5,12,0,19 12c: 50 a4 60 26 rlwimi r4,r5,12,0,19
130: 38 63 00 00 addi r3,r3,0 130: 38 63 00 00 addi r3,r3,0
132: R_PPC_ADDR16_LO .rodata.str1. 132: R_PPC_ADDR16_LO .rodata.str1.
134: 48 00 00 01 bl 134 <paging_init+0xa8> 134: 48 00 00 01 bl 134 <paging_init+0xa8>
134: R_PPC_PLTREL24 printk 134: R_PPC_PLTREL24 printk
138: 3c 60 00 00 lis r3,0 138: 3c 60 00 00 lis r3,0
13a: R_PPC_ADDR16_HA max_low_pfn 13a: R_PPC_ADDR16_HA max_low_pfn
13c: 80 83 00 00 lwz r4,0(r3) 13c: 80 83 00 00 lwz r4,0(r3)
13e: R_PPC_ADDR16_LO max_low_pfn 13e: R_PPC_ADDR16_LO max_low_pfn
140: 3c 60 00 00 lis r3,0 140: 3c 60 00 00 lis r3,0
142: R_PPC_ADDR16_HA .bss+0x10 142: R_PPC_ADDR16_HA .bss+0x10
144: 94 83 00 00 stwu r4,0(r3) 144: 94 83 00 00 stwu r4,0(r3)
146: R_PPC_ADDR16_LO .bss+0x10 146: R_PPC_ADDR16_LO .bss+0x10
148: 48 00 00 01 bl 148 <paging_init+0xbc> 148: 48 00 00 01 bl 148 <paging_init+0xbc>
148: R_PPC_PLTREL24 free_area_ini 148: R_PPC_PLTREL24 free_area_ini
14c: 83 c1 00 28 lwz r30,40(r1) 14c: 83 c1 00 28 lwz r30,40(r1)
150: 83 a1 00 24 lwz r29,36(r1) 150: 83 a1 00 24 lwz r29,36(r1)
154: 83 81 00 20 lwz r28,32(r1) 154: 83 81 00 20 lwz r28,32(r1)
158: 83 61 00 1c lwz r27,28(r1) 158: 83 61 00 1c lwz r27,28(r1)
15c: 83 41 00 18 lwz r26,24(r1) 15c: 83 41 00 18 lwz r26,24(r1)
160: 83 21 00 14 lwz r25,20(r1) 160: 83 21 00 14 lwz r25,20(r1)
164: 80 01 00 34 lwz r0,52(r1) 164: 80 01 00 34 lwz r0,52(r1)
168: 38 21 00 30 addi r1,r1,48 168: 38 21 00 30 addi r1,r1,48
16c: 7c 08 03 a6 mtlr r0 16c: 7c 08 03 a6 mtlr r0
170: 4e 80 00 20 blr 170: 4e 80 00 20 blr
00000174 <mem_init>: 00000174 <mem_init>:
174: 7c 08 02 a6 mflr r0 174: 7c 08 02 a6 mflr r0
178: 90 01 00 04 stw r0,4(r1) 178: 90 01 00 04 stw r0,4(r1)
17c: 94 21 ff e0 stwu r1,-32(r1) 17c: 94 21 ff e0 stwu r1,-32(r1)
180: 3c 60 00 00 lis r3,0 180: 3c 60 00 00 lis r3,0
182: R_PPC_ADDR16_HA max_low_pfn 182: R_PPC_ADDR16_HA max_low_pfn
184: 3c 80 00 00 lis r4,0 184: 3c 80 00 00 lis r4,0
186: R_PPC_ADDR16_HA max_pfn 186: R_PPC_ADDR16_HA max_pfn
188: 93 81 00 10 stw r28,16(r1) 188: 93 81 00 10 stw r28,16(r1)
18c: 3f 80 00 00 lis r28,0 18c: 3f 80 00 00 lis r28,0
18e: R_PPC_ADDR16_HA high_memory 18e: R_PPC_ADDR16_HA high_memory
190: 80 63 00 00 lwz r3,0(r3) 190: 80 63 00 00 lwz r3,0(r3)
192: R_PPC_ADDR16_LO max_low_pfn 192: R_PPC_ADDR16_LO max_low_pfn
194: 80 84 00 00 lwz r4,0(r4) 194: 80 84 00 00 lwz r4,0(r4)
196: R_PPC_ADDR16_LO max_pfn 196: R_PPC_ADDR16_LO max_pfn
198: 54 63 60 26 rlwinm r3,r3,12,0,19 198: 54 63 60 26 rlwinm r3,r3,12,0,19
19c: 3c 63 c0 00 addis r3,r3,-16384 19c: 3c 63 c0 00 addis r3,r3,-16384
1a0: 90 7c 00 00 stw r3,0(r28) 1a0: 90 7c 00 00 stw r3,0(r28)
1a2: R_PPC_ADDR16_LO high_memory 1a2: R_PPC_ADDR16_LO high_memory
1a4: 3c 60 00 00 lis r3,0 1a4: 3c 60 00 00 lis r3,0
1a6: R_PPC_ADDR16_HA max_mapnr 1a6: R_PPC_ADDR16_HA max_mapnr
1a8: 93 a1 00 14 stw r29,20(r1) 1a8: 93 a1 00 14 stw r29,20(r1)
1ac: 93 c1 00 18 stw r30,24(r1) 1ac: 93 c1 00 18 stw r30,24(r1)
1b0: 90 83 00 00 stw r4,0(r3) 1b0: 90 83 00 00 stw r4,0(r3)
1b2: R_PPC_ADDR16_LO max_mapnr 1b2: R_PPC_ADDR16_LO max_mapnr
1b4: 48 00 00 01 bl 1b4 <mem_init+0x40> 1b4: 48 00 00 01 bl 1b4 <mem_init+0x40>
1b4: R_PPC_PLTREL24 memblock_free 1b4: R_PPC_PLTREL24 memblock_free
1b8: 38 60 00 00 li r3,0 1b8: 38 60 00 00 li r3,0
1bc: 48 00 00 01 bl 1bc <mem_init+0x48> 1bc: 48 00 00 01 bl 1bc <mem_init+0x48>
1bc: R_PPC_PLTREL24 mem_init_prin 1bc: R_PPC_PLTREL24 mem_init_prin
1c0: 3c 60 00 00 lis r3,0 1c0: 3c 60 00 00 lis r3,0
1c2: R_PPC_ADDR16_HA .rodata.str1. 1c2: R_PPC_ADDR16_HA .rodata.str1.
1c4: 4c c6 31 82 crclr 4*cr1+eq 1c4: 4c c6 31 82 crclr 4*cr1+eq
1c8: 38 63 00 00 addi r3,r3,0 1c8: 38 63 00 00 addi r3,r3,0
1ca: R_PPC_ADDR16_LO .rodata.str1. 1ca: R_PPC_ADDR16_LO .rodata.str1.
1cc: 48 00 00 01 bl 1cc <mem_init+0x58> 1cc: 48 00 00 01 bl 1cc <mem_init+0x58>
1cc: R_PPC_PLTREL24 printk 1cc: R_PPC_PLTREL24 printk
1d0: 3c 80 ff fd lis r4,-3 1d0: 3c 80 ff fd lis r4,-3
1d4: 3c 60 00 00 lis r3,0 1d4: 3c 60 00 00 lis r3,0
1d6: R_PPC_ADDR16_HA .rodata.str1. 1d6: R_PPC_ADDR16_HA .rodata.str1.
1d8: 4c c6 31 82 crclr 4*cr1+eq 1d8: 4c c6 31 82 crclr 4*cr1+eq
1dc: 60 9e f0 00 ori r30,r4,61440 1dc: 60 9e f0 00 ori r30,r4,61440
1e0: 38 63 00 00 addi r3,r3,0 1e0: 38 63 00 00 addi r3,r3,0
1e2: R_PPC_ADDR16_LO .rodata.str1. 1e2: R_PPC_ADDR16_LO .rodata.str1.
1e4: 7f c4 f3 78 mr r4,r30 1e4: 7f c4 f3 78 mr r4,r30
1e8: 38 a0 f0 00 li r5,-4096 1e8: 38 a0 f0 00 li r5,-4096
1ec: 48 00 00 01 bl 1ec <mem_init+0x78> 1ec: 48 00 00 01 bl 1ec <mem_init+0x78>
1ec: R_PPC_PLTREL24 printk 1ec: R_PPC_PLTREL24 printk
1f0: 3c 80 ff dd lis r4,-35 1f0: 3c 80 ff dd lis r4,-35
1f4: 3c 60 00 00 lis r3,0 1f4: 3c 60 00 00 lis r3,0
1f6: R_PPC_ADDR16_HA .rodata.str1. 1f6: R_PPC_ADDR16_HA .rodata.str1.
1f8: 4c c6 31 82 crclr 4*cr1+eq 1f8: 4c c6 31 82 crclr 4*cr1+eq
1fc: 60 9d f0 00 ori r29,r4,61440 1fc: 60 9d f0 00 ori r29,r4,61440
200: 38 63 00 00 addi r3,r3,0 200: 38 63 00 00 addi r3,r3,0
202: R_PPC_ADDR16_LO .rodata.str1. 202: R_PPC_ADDR16_LO .rodata.str1.
204: 7f a4 eb 78 mr r4,r29 204: 7f a4 eb 78 mr r4,r29
208: 7f c5 f3 78 mr r5,r30 208: 7f c5 f3 78 mr r5,r30
20c: 48 00 00 01 bl 20c <mem_init+0x98> 20c: 48 00 00 01 bl 20c <mem_init+0x98>
20c: R_PPC_PLTREL24 printk 20c: R_PPC_PLTREL24 printk
210: 3f c0 00 00 lis r30,0 210: 3f c0 00 00 lis r30,0
212: R_PPC_ADDR16_HA ioremap_bot 212: R_PPC_ADDR16_HA ioremap_bot
214: 3c 60 00 00 lis r3,0 214: 3c 60 00 00 lis r3,0
216: R_PPC_ADDR16_HA .rodata.str1. 216: R_PPC_ADDR16_HA .rodata.str1.
218: 4c c6 31 82 crclr 4*cr1+eq 218: 4c c6 31 82 crclr 4*cr1+eq
21c: 80 9e 00 00 lwz r4,0(r30) 21c: 80 9e 00 00 lwz r4,0(r30)
21e: R_PPC_ADDR16_LO ioremap_bot 21e: R_PPC_ADDR16_LO ioremap_bot
220: 38 63 00 00 addi r3,r3,0 220: 38 63 00 00 addi r3,r3,0
222: R_PPC_ADDR16_LO .rodata.str1. 222: R_PPC_ADDR16_LO .rodata.str1.
224: 7f a5 eb 78 mr r5,r29 224: 7f a5 eb 78 mr r5,r29
228: 48 00 00 01 bl 228 <mem_init+0xb4> 228: 48 00 00 01 bl 228 <mem_init+0xb4>
228: R_PPC_PLTREL24 printk 228: R_PPC_PLTREL24 printk
22c: 80 7c 00 00 lwz r3,0(r28) 22c: 80 7c 00 00 lwz r3,0(r28)
22e: R_PPC_ADDR16_LO high_memory 22e: R_PPC_ADDR16_LO high_memory
230: 3c 80 01 00 lis r4,256 230: 3c 80 01 00 lis r4,256
234: 4c c6 31 82 crclr 4*cr1+eq 234: 4c c6 31 82 crclr 4*cr1+eq
238: 38 63 ff ff addi r3,r3,-1 238: 38 63 ff ff addi r3,r3,-1
23c: 80 be 00 00 lwz r5,0(r30) 23c: 80 be 00 00 lwz r5,0(r30)
23e: R_PPC_ADDR16_LO ioremap_bot 23e: R_PPC_ADDR16_LO ioremap_bot
240: 3c 63 10 00 addis r3,r3,4096 240: 3c 63 10 00 addis r3,r3,4096
244: 54 63 00 06 rlwinm r3,r3,0,0,3 244: 54 63 00 06 rlwinm r3,r3,0,0,3
248: 50 64 02 0c rlwimi r4,r3,0,8,6 248: 50 64 02 0c rlwimi r4,r3,0,8,6
24c: 3c 60 00 00 lis r3,0 24c: 3c 60 00 00 lis r3,0
24e: R_PPC_ADDR16_HA .rodata.str1. 24e: R_PPC_ADDR16_HA .rodata.str1.
250: 38 63 00 00 addi r3,r3,0 250: 38 63 00 00 addi r3,r3,0
252: R_PPC_ADDR16_LO .rodata.str1. 252: R_PPC_ADDR16_LO .rodata.str1.
254: 48 00 00 01 bl 254 <mem_init+0xe0> 254: 48 00 00 01 bl 254 <mem_init+0xe0>
254: R_PPC_PLTREL24 printk 254: R_PPC_PLTREL24 printk
258: 83 c1 00 18 lwz r30,24(r1) 258: 83 c1 00 18 lwz r30,24(r1)
25c: 83 a1 00 14 lwz r29,20(r1) 25c: 83 a1 00 14 lwz r29,20(r1)
260: 83 81 00 10 lwz r28,16(r1) 260: 83 81 00 10 lwz r28,16(r1)
264: 80 01 00 24 lwz r0,36(r1) 264: 80 01 00 24 lwz r0,36(r1)
268: 38 21 00 20 addi r1,r1,32 268: 38 21 00 20 addi r1,r1,32
26c: 7c 08 03 a6 mtlr r0 26c: 7c 08 03 a6 mtlr r0
270: 4e 80 00 20 blr 270: 4e 80 00 20 blr
00000274 <add_system_ram_resources>: 00000274 <add_system_ram_resources>:
274: 7c 08 02 a6 mflr r0 274: 7c 08 02 a6 mflr r0
278: 90 01 00 04 stw r0,4(r1) 278: 90 01 00 04 stw r0,4(r1)
27c: 94 21 ff c0 stwu r1,-64(r1) 27c: 94 21 ff c0 stwu r1,-64(r1)
280: 3c 60 00 00 lis r3,0 280: 3c 60 00 00 lis r3,0
282: R_PPC_ADDR16_HA memblock 282: R_PPC_ADDR16_HA memblock
284: 93 a1 00 34 stw r29,52(r1) 284: 93 a1 00 34 stw r29,52(r1)
288: 3b a3 00 00 addi r29,r3,0 288: 3b a3 00 00 addi r29,r3,0
28a: R_PPC_ADDR16_LO memblock 28a: R_PPC_ADDR16_LO memblock
28c: 80 7d 00 10 lwz r3,16(r29) 28c: 80 7d 00 10 lwz r3,16(r29)
290: 93 81 00 30 stw r28,48(r1) 290: 93 81 00 30 stw r28,48(r1)
294: 1c 63 00 18 mulli r3,r3,24 294: 1c 63 00 18 mulli r3,r3,24
298: 83 9d 00 20 lwz r28,32(r29) 298: 83 9d 00 20 lwz r28,32(r29)
29c: 7c 7c 1a 14 add r3,r28,r3 29c: 7c 7c 1a 14 add r3,r28,r3
2a0: 92 a1 00 14 stw r21,20(r1) 2a0: 92 a1 00 14 stw r21,20(r1)
2a4: 7c 1c 18 40 cmplw r28,r3 2a4: 7c 1c 18 40 cmplw r28,r3
2a8: 92 c1 00 18 stw r22,24(r1) 2a8: 92 c1 00 18 stw r22,24(r1)
2ac: 92 e1 00 1c stw r23,28(r1) 2ac: 92 e1 00 1c stw r23,28(r1)
2b0: 93 01 00 20 stw r24,32(r1) 2b0: 93 01 00 20 stw r24,32(r1)
2b4: 93 21 00 24 stw r25,36(r1) 2b4: 93 21 00 24 stw r25,36(r1)
2b8: 93 41 00 28 stw r26,40(r1) 2b8: 93 41 00 28 stw r26,40(r1)
2bc: 93 61 00 2c stw r27,44(r1) 2bc: 93 61 00 2c stw r27,44(r1)
2c0: 93 c1 00 38 stw r30,56(r1) 2c0: 93 c1 00 38 stw r30,56(r1)
2c4: 40 80 00 ac bge 370 <add_system_ram_resources 2c4: 40 80 00 ac bge 370 <add_system_ram_resources
2c8: 3c 60 00 00 lis r3,0 2c8: 3c 60 00 00 lis r3,0
2ca: R_PPC_ADDR16_HA kmalloc_cache 2ca: R_PPC_ADDR16_HA kmalloc_cache
2cc: 3c 80 00 00 lis r4,0 2cc: 3c 80 00 00 lis r4,0
2ce: R_PPC_ADDR16_HA .rodata.str1. 2ce: R_PPC_ADDR16_HA .rodata.str1.
2d0: 3c a0 81 00 lis r5,-32512 2d0: 3c a0 81 00 lis r5,-32512
2d4: 3c c0 00 00 lis r6,0 2d4: 3c c0 00 00 lis r6,0
2d6: R_PPC_ADDR16_HA iomem_resourc 2d6: R_PPC_ADDR16_HA iomem_resourc
2d8: 3b 7c ff e8 addi r27,r28,-24 2d8: 3b 7c ff e8 addi r27,r28,-24
2dc: 3b 40 00 00 li r26,0 2dc: 3b 40 00 00 li r26,0
2e0: 3b 23 00 00 addi r25,r3,0 2e0: 3b 23 00 00 addi r25,r3,0
2e2: R_PPC_ADDR16_LO kmalloc_cache 2e2: R_PPC_ADDR16_LO kmalloc_cache
2e4: 3b 04 00 00 addi r24,r4,0 2e4: 3b 04 00 00 addi r24,r4,0
2e6: R_PPC_ADDR16_LO .rodata.str1. 2e6: R_PPC_ADDR16_LO .rodata.str1.
2e8: 60 b7 02 00 ori r23,r5,512 2e8: 60 b7 02 00 ori r23,r5,512
2ec: 3b c6 00 00 addi r30,r6,0 2ec: 3b c6 00 00 addi r30,r6,0
2ee: R_PPC_ADDR16_LO iomem_resourc 2ee: R_PPC_ADDR16_LO iomem_resourc
2f0: 80 79 00 18 lwz r3,24(r25) 2f0: 80 79 00 18 lwz r3,24(r25)
2f4: 38 80 0d c0 li r4,3520 2f4: 38 80 0d c0 li r4,3520
2f8: 38 a0 00 28 li r5,40 2f8: 38 a0 00 28 li r5,40
2fc: 82 db 00 1c lwz r22,28(r27) 2fc: 82 db 00 1c lwz r22,28(r27)
300: 82 bb 00 24 lwz r21,36(r27) 300: 82 bb 00 24 lwz r21,36(r27)
304: 48 00 00 01 bl 304 <add_system_ram_resources 304: 48 00 00 01 bl 304 <add_system_ram_resources
304: R_PPC_PLTREL24 kmem_cache_al 304: R_PPC_PLTREL24 kmem_cache_al
308: 7c 64 1b 78 mr r4,r3 308: 7c 64 1b 78 mr r4,r3
30c: 7c 63 00 34 cntlzw r3,r3 30c: 7c 63 00 34 cntlzw r3,r3
310: 28 04 00 00 cmplwi r4,0 310: 28 04 00 00 cmplwi r4,0
314: 54 63 df fe rlwinm r3,r3,27,31,31 314: 54 63 df fe rlwinm r3,r3,27,31,31
318: 0f 03 00 00 twnei r3,0 318: 0f 03 00 00 twnei r3,0
31c: 41 82 00 34 beq 350 <add_system_ram_resources 31c: 41 82 00 34 beq 350 <add_system_ram_resources
320: 7c 76 aa 14 add r3,r22,r21 320: 7c 76 aa 14 add r3,r22,r21
324: 93 04 00 10 stw r24,16(r4) 324: 93 04 00 10 stw r24,16(r4)
328: 38 63 ff ff addi r3,r3,-1 328: 38 63 ff ff addi r3,r3,-1
32c: 90 64 00 0c stw r3,12(r4) 32c: 90 64 00 0c stw r3,12(r4)
330: 7f c3 f3 78 mr r3,r30 330: 7f c3 f3 78 mr r3,r30
334: 93 44 00 00 stw r26,0(r4) 334: 93 44 00 00 stw r26,0(r4)
338: 92 c4 00 04 stw r22,4(r4) 338: 92 c4 00 04 stw r22,4(r4)
33c: 93 44 00 08 stw r26,8(r4) 33c: 93 44 00 08 stw r26,8(r4)
340: 92 e4 00 14 stw r23,20(r4) 340: 92 e4 00 14 stw r23,20(r4)
344: 48 00 00 01 bl 344 <add_system_ram_resources 344: 48 00 00 01 bl 344 <add_system_ram_resources
344: R_PPC_PLTREL24 request_resou 344: R_PPC_PLTREL24 request_resou
348: 54 63 0f fe rlwinm r3,r3,1,31,31 348: 54 63 0f fe rlwinm r3,r3,1,31,31
34c: 0f 03 00 00 twnei r3,0 34c: 0f 03 00 00 twnei r3,0
350: 80 7d 00 10 lwz r3,16(r29) 350: 80 7d 00 10 lwz r3,16(r29)
354: 3b 9c 00 18 addi r28,r28,24 354: 3b 9c 00 18 addi r28,r28,24
358: 3b 7b 00 18 addi r27,r27,24 358: 3b 7b 00 18 addi r27,r27,24
35c: 80 9d 00 20 lwz r4,32(r29) 35c: 80 9d 00 20 lwz r4,32(r29)
360: 1c 63 00 18 mulli r3,r3,24 360: 1c 63 00 18 mulli r3,r3,24
364: 7c 64 1a 14 add r3,r4,r3 364: 7c 64 1a 14 add r3,r4,r3
368: 7c 1c 18 40 cmplw r28,r3 368: 7c 1c 18 40 cmplw r28,r3
36c: 41 80 ff 84 blt 2f0 <add_system_ram_resources 36c: 41 80 ff 84 blt 2f0 <add_system_ram_resources
370: 38 60 00 00 li r3,0 370: 38 60 00 00 li r3,0
374: 83 c1 00 38 lwz r30,56(r1) 374: 83 c1 00 38 lwz r30,56(r1)
378: 83 a1 00 34 lwz r29,52(r1) 378: 83 a1 00 34 lwz r29,52(r1)
37c: 83 81 00 30 lwz r28,48(r1) 37c: 83 81 00 30 lwz r28,48(r1)
380: 83 61 00 2c lwz r27,44(r1) 380: 83 61 00 2c lwz r27,44(r1)
384: 83 41 00 28 lwz r26,40(r1) 384: 83 41 00 28 lwz r26,40(r1)
388: 83 21 00 24 lwz r25,36(r1) 388: 83 21 00 24 lwz r25,36(r1)
38c: 83 01 00 20 lwz r24,32(r1) 38c: 83 01 00 20 lwz r24,32(r1)
390: 82 e1 00 1c lwz r23,28(r1) 390: 82 e1 00 1c lwz r23,28(r1)
394: 82 c1 00 18 lwz r22,24(r1) 394: 82 c1 00 18 lwz r22,24(r1)
398: 82 a1 00 14 lwz r21,20(r1) 398: 82 a1 00 14 lwz r21,20(r1)
39c: 80 01 00 44 lwz r0,68(r1) 39c: 80 01 00 44 lwz r0,68(r1)
3a0: 38 21 00 40 addi r1,r1,64 3a0: 38 21 00 40 addi r1,r1,64
3a4: 7c 08 03 a6 mtlr r0 3a4: 7c 08 03 a6 mtlr r0
3a8: 4e 80 00 20 blr 3a8: 4e 80 00 20 blr
^ permalink raw reply
* Re: [PATCH] powerpc: Test broken dcbz
From: kbuild test robot @ 2019-07-22 0:53 UTC (permalink / raw)
To: Nathan Chancellor
Cc: linux-kernel, clang-built-linux, Paul Mackerras, kbuild-all,
linuxppc-dev
In-Reply-To: <20190721075846.GA97701@archlinux-threadripper>
[-- Attachment #1: Type: text/plain, Size: 1368 bytes --]
Hi Nathan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to v5.3-rc1 next-20190719]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Nathan-Chancellor/powerpc-Test-broken-dcbz/20190722-051054
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
arch/powerpc/mm/mem.c: In function 'clear_user_page':
>> arch/powerpc/mm/mem.c:364:2: error: implicit declaration of function 'broken_clear_page'; did you mean 'bdev_read_page'? [-Werror=implicit-function-declaration]
broken_clear_page(page);
^~~~~~~~~~~~~~~~~
bdev_read_page
cc1: all warnings being treated as errors
vim +364 arch/powerpc/mm/mem.c
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 25327 bytes --]
^ permalink raw reply
* Re: [PATCH v2] powerpc: slightly improve cache helpers
From: Segher Boessenkool @ 2019-07-21 18:01 UTC (permalink / raw)
To: Nathan Chancellor
Cc: linux-kernel, clang-built-linux, Paul Mackerras, linuxppc-dev
In-Reply-To: <20190721075846.GA97701@archlinux-threadripper>
On Sun, Jul 21, 2019 at 12:58:46AM -0700, Nathan Chancellor wrote:
> I have attached the disassembly of arch/powerpc/kernel/mem.o with
> clear_page (working) and broken_clear_page (broken), along with the side
> by side diff. My assembly knowledge is fairly limited as it stands and
> it is certainly not up to snuff on PowerPC so I have no idea what I am
> looking for. Please let me know if anything immediately looks off or if
> there is anything else I can do to help out.
You might want to use a disassembler that shows most simplified mnemonics,
and you crucially should show the relocations. "objdump -dr" works nicely.
> 0000017c clear_user_page:
> 17c: 38 80 00 80 li 4, 128
> 180: 7c 89 03 a6 mtctr 4
> 184: 7c 00 1f ec dcbz 0, 3
> 188: 38 63 00 20 addi 3, 3, 32
> 18c: 42 00 ff f8 bdnz .+65528
That offset is incorrectly disassembled, btw (it's a signed field, not
unsigned).
> 0000017c clear_user_page:
> 17c: 94 21 ff f0 stwu 1, -16(1)
> 180: 38 80 00 80 li 4, 128
> 184: 38 63 ff e0 addi 3, 3, -32
> 188: 7c 89 03 a6 mtctr 4
> 18c: 38 81 00 0f addi 4, 1, 15
> 190: 8c c3 00 20 lbzu 6, 32(3)
> 194: 98 c1 00 0f stb 6, 15(1)
> 198: 7c 00 27 ec dcbz 0, 4
> 19c: 42 00 ff f4 bdnz .+65524
Uh, yeah, well, I have no idea what clang tried here, but that won't
work. It's copying a byte from each target cache line to the stack,
and then does clears the cache line containing that byte on the stack.
I *guess* this is about "Z" and not about "%y", but you'll have to ask
the clang people.
Or it may be that they do not treat inline asm operands as lvalues
properly? That rings some bells. Yeah that looks like it.
Segher
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