* [PATCH AUTOSEL 5.5 11/41] powerpc: Include .BTF section
From: Sasha Levin @ 2020-03-16 2:32 UTC (permalink / raw)
To: linux-kernel, stable; +Cc: Sasha Levin, Naveen N. Rao, linuxppc-dev
In-Reply-To: <20200316023319.749-1-sashal@kernel.org>
From: "Naveen N. Rao" <naveen.n.rao@linux.vnet.ibm.com>
[ Upstream commit cb0cc635c7a9fa8a3a0f75d4d896721819c63add ]
Selecting CONFIG_DEBUG_INFO_BTF results in the below warning from ld:
ld: warning: orphan section `.BTF' from `.btf.vmlinux.bin.o' being placed in section `.BTF'
Include .BTF section in vmlinux explicitly to fix the same.
Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200220113132.857132-1-naveen.n.rao@linux.vnet.ibm.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/powerpc/kernel/vmlinux.lds.S | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 8834220036a51..857ab49750f18 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -303,6 +303,12 @@ SECTIONS
*(.branch_lt)
}
+#ifdef CONFIG_DEBUG_INFO_BTF
+ .BTF : AT(ADDR(.BTF) - LOAD_OFFSET) {
+ *(.BTF)
+ }
+#endif
+
.opd : AT(ADDR(.opd) - LOAD_OFFSET) {
__start_opd = .;
KEEP(*(.opd))
--
2.20.1
^ permalink raw reply related
* [RFC PATCH v1] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor.
From: Ram Pai @ 2020-03-15 22:37 UTC (permalink / raw)
To: kvm-ppc, linuxppc-dev; +Cc: aik, andmike, groug, clg, sukadev, bauerman, david
XIVE interrupt controller maintains a Event-Queue(EQ) page. This page is
used to communicate events with the Hypervisor/Qemu. In Secure-VM,
unless a page is shared with the Hypervisor, the Hypervisor will
not be able to read/write to that page.
Explicitly share the EQ page with the Hypervisor, and unshare it
during cleanup. This enables SVM to use XIVE.
(NOTE: If the Hypervisor/Ultravisor is unable to target interrupts
directly to Secure VM, use "kernel_irqchip=off" on the qemu command
line).
Cc: kvm-ppc@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Thiago Jung Bauermann <bauerman@linux.ibm.com>
Cc: Michael Anderson <andmike@linux.ibm.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
Cc: Paul Mackerras <paulus@ozlabs.org>
Cc: Greg Kurz <groug@kaod.org>
Cc: Cedric Le Goater <clg@fr.ibm.com>
Cc: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Ram Pai <linuxram@us.ibm.com>
---
arch/powerpc/sysdev/xive/spapr.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
index 55dc61c..608b52f 100644
--- a/arch/powerpc/sysdev/xive/spapr.c
+++ b/arch/powerpc/sysdev/xive/spapr.c
@@ -26,6 +26,8 @@
#include <asm/xive.h>
#include <asm/xive-regs.h>
#include <asm/hvcall.h>
+#include <asm/svm.h>
+#include <asm/ultravisor.h>
#include "xive-internal.h"
@@ -501,6 +503,9 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
rc = -EIO;
} else {
q->qpage = qpage;
+ if (is_secure_guest())
+ uv_share_page(PHYS_PFN(qpage_phys),
+ 1 << xive_alloc_order(order));
}
fail:
return rc;
@@ -534,6 +539,8 @@ static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
hw_cpu, prio);
alloc_order = xive_alloc_order(xive_queue_shift);
+ if (is_secure_guest())
+ uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order);
free_pages((unsigned long)q->qpage, alloc_order);
q->qpage = NULL;
}
--
1.8.3.1
^ permalink raw reply related
* Re: [PATCH 3/3] mm/page_alloc: Keep memoryless cpuless node 0 offline
From: Christopher Lameter @ 2020-03-15 14:20 UTC (permalink / raw)
To: Srikar Dronamraju
Cc: Michal Hocko, Linus Torvalds, linux-kernel, linux-mm, Mel Gorman,
Kirill A. Shutemov, Andrew Morton, linuxppc-dev, Vlastimil Babka
In-Reply-To: <20200311110237.5731-4-srikar@linux.vnet.ibm.com>
On Wed, 11 Mar 2020, Srikar Dronamraju wrote:
> Currently Linux kernel with CONFIG_NUMA on a system with multiple
> possible nodes, marks node 0 as online at boot. However in practice,
> there are systems which have node 0 as memoryless and cpuless.
Would it not be better and simpler to require that node 0 always has
memory (and processors)? A mininum operational set?
We can dynamically number the nodes right? So just make sure that the
firmware properly creates memory on node 0?
^ permalink raw reply
* Re: [RESEND PATCH v2 1/9] iomap: Constify ioreadX() iomem argument (as in generic implementation)
From: Krzysztof Kozlowski @ 2020-03-14 11:02 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Rich Felker, Jiri Slaby, Geert Uytterhoeven, Michael S. Tsirkin,
David Airlie, Jason Wang, dri-devel, virtualization,
James E.J. Bottomley, netdev, Paul Mackerras, linux-arch,
Dave Jiang, Yoshinori Sato, Helge Deller, linux-sh,
Alexey Brodkin, Ben Skeggs, nouveau, Dave Airlie, Matt Turner,
linux-snps-arc, Nick Kossifidis, Allen Hubbe, linux-alpha,
Ivan Kokshaysky, Thomas Gleixner, Mauro Carvalho Chehab,
Kalle Valo, Richard Henderson, linux-parisc, Vineet Gupta,
linux-wireless, linux-kernel, Luis Chamberlain, Daniel Vetter,
Jon Mason, linux-ntb, Andrew Morton, linux-media, linuxppc-dev,
David S. Miller
In-Reply-To: <20200219175007.13627-2-krzk@kernel.org>
On Wed, Feb 19, 2020 at 06:49:59PM +0100, Krzysztof Kozlowski wrote:
> The ioreadX() and ioreadX_rep() helpers have inconsistent interface. On
> some architectures void *__iomem address argument is a pointer to const,
> on some not.
>
> Implementations of ioreadX() do not modify the memory under the address
> so they can be converted to a "const" version for const-safety and
> consistency among architectures.
>
> Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Hi Arnd,
This patch touches multipel file systems so no one is brave enough to
pick it up. However you are mentioned as maintainer of generic asm
headers so maybe you could apply it to arm-soc?
Best regards,
Krzysztof
>
> ---
>
> Changes since v1:
> 1. Constify also ioreadX_rep() and mmio_insX(),
> 2. Squash lib+alpha+powerpc+parisc+sh into one patch for bisectability,
> 3. Add Geert's review.
> 4. Add Arnd's review.
> ---
> arch/alpha/include/asm/core_apecs.h | 6 +--
> arch/alpha/include/asm/core_cia.h | 6 +--
> arch/alpha/include/asm/core_lca.h | 6 +--
> arch/alpha/include/asm/core_marvel.h | 4 +-
> arch/alpha/include/asm/core_mcpcia.h | 6 +--
> arch/alpha/include/asm/core_t2.h | 2 +-
> arch/alpha/include/asm/io.h | 12 ++---
> arch/alpha/include/asm/io_trivial.h | 16 +++---
> arch/alpha/include/asm/jensen.h | 2 +-
> arch/alpha/include/asm/machvec.h | 6 +--
> arch/alpha/kernel/core_marvel.c | 2 +-
> arch/alpha/kernel/io.c | 12 ++---
> arch/parisc/include/asm/io.h | 4 +-
> arch/parisc/lib/iomap.c | 72 +++++++++++++--------------
> arch/powerpc/kernel/iomap.c | 28 +++++------
> arch/sh/kernel/iomap.c | 22 ++++----
> include/asm-generic/iomap.h | 28 +++++------
> include/linux/io-64-nonatomic-hi-lo.h | 4 +-
> include/linux/io-64-nonatomic-lo-hi.h | 4 +-
> lib/iomap.c | 30 +++++------
> 20 files changed, 136 insertions(+), 136 deletions(-)
>
^ permalink raw reply
* Re: [RESEND PATCH v2 6/9] drm/mgag200: Constify ioreadX() iomem argument (as in generic implementation)
From: Krzysztof Kozlowski @ 2020-03-14 10:59 UTC (permalink / raw)
To: Thomas Zimmermann
Cc: Rich Felker, Jiri Slaby, Geert Uytterhoeven, Michael S. Tsirkin,
David Airlie, Jason Wang, dri-devel, virtualization,
James E.J. Bottomley, netdev, Paul Mackerras, linux-arch,
Dave Jiang, Yoshinori Sato, Helge Deller, linux-sh,
Alexey Brodkin, Ben Skeggs, nouveau, Dave Airlie, Matt Turner,
linux-snps-arc, Nick Kossifidis, Allen Hubbe, Arnd Bergmann,
linux-alpha, Ivan Kokshaysky, Thomas Gleixner,
Mauro Carvalho Chehab, Kalle Valo, Richard Henderson,
linux-parisc, Vineet Gupta, linux-wireless, linux-kernel,
Luis Chamberlain, Daniel Vetter, Jon Mason, linux-ntb,
Andrew Morton, linux-media, linuxppc-dev, David S. Miller
In-Reply-To: <90baef2d-25fe-fac4-6a7e-b103b4b6721e@suse.de>
On Thu, Mar 12, 2020 at 11:49:05AM +0100, Thomas Zimmermann wrote:
> Hi Krzysztof,
>
> I just received a resend email from 3 weeks ago :/
>
> Do you want me to merge the mgag200 patch into drm-misc-next?
Thanks but it depends on the first patch in the series so either it
could go with your ack through other tree or I will send it later (once
1st patch gets to mainline).
Best regards,
Krzysztof
^ permalink raw reply
* [Bug 206669] Little-endian kernel crashing on POWER8 on heavy big-endian PowerKVM load
From: bugzilla-daemon @ 2020-03-14 10:08 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <bug-206669-206035@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=206669
--- Comment #11 from John Paul Adrian Glaubitz (glaubitz@physik.fu-berlin.de) ---
It seems I can provoke the crash by running the glibc testsuite in a big-endian
guest VM.
The machine just crashed with the IPMI console open but the only message the
kernel printed was:
"watson login: [ 1809.138398] KVM: couldn't grab cpu 115"
I have not observed the kernel buffer though. But I will try to provoke the
crash now while having the kernel log open.
--
You are receiving this mail because:
You are watching the assignee of the bug.
^ permalink raw reply
* Re: [5.6.0-rc2-next-20200218/powerpc] Boot failure on POWER9
From: Sachin Sant @ 2020-03-14 8:10 UTC (permalink / raw)
To: Vlastimil Babka, Michael Ellerman
Cc: Srikar Dronamraju, Michal Hocko, Pekka Enberg,
Linux-Next Mailing List, Paul Mackerras, David Rientjes,
Christopher Lameter, linuxppc-dev, Joonsoo Kim, Kirill Tkhai
In-Reply-To: <11e69587-8b64-6088-cb5c-d7d719842535@suse.cz>
[-- Attachment #1: Type: text/plain, Size: 3673 bytes --]
> On 13-Mar-2020, at 5:05 PM, Vlastimil Babka <vbabka@suse.cz> wrote:
>
> On 3/13/20 12:12 PM, Srikar Dronamraju wrote:
>> * Michael Ellerman <mpe@ellerman.id.au> [2020-03-13 21:48:06]:
>>
>>> Sachin Sant <sachinp@linux.vnet.ibm.com> writes:
>>>>> The patch below might work. Sachin can you test this? I tried faking up
>>>>> a system with a memoryless node zero but couldn't get it to even start
>>>>> booting.
>>>>>
>>>> The patch did not help. The kernel crashed during
>>>> the boot with the same call trace.
>>>>
>>>> BUG_ON() introduced with the patch was not triggered.
>>>
>>> OK, that's weird.
>>>
>>> I eventually managed to get a memoryless node going in sim, and it
>>> appears to work there.
>>>
>>> eg in dmesg:
>>>
>>> [ 0.000000][ T0] numa: NODE_DATA [mem 0x2000fffa2f80-0x2000fffa7fff]
>>> [ 0.000000][ T0] numa: NODE_DATA(0) on node 1
>>> [ 0.000000][ T0] numa: NODE_DATA [mem 0x2000fff9df00-0x2000fffa2f7f]
>>> ...
>>> [ 0.000000][ T0] Early memory node ranges
>>> [ 0.000000][ T0] node 1: [mem 0x0000000000000000-0x00000000ffffffff]
>>> [ 0.000000][ T0] node 1: [mem 0x0000200000000000-0x00002000ffffffff]
>>> [ 0.000000][ T0] Could not find start_pfn for node 0
>>> [ 0.000000][ T0] Initmem setup node 0 [mem 0x0000000000000000-0x0000000000000000]
>>> [ 0.000000][ T0] On node 0 totalpages: 0
>>> [ 0.000000][ T0] Initmem setup node 1 [mem 0x0000000000000000-0x00002000ffffffff]
>>> [ 0.000000][ T0] On node 1 totalpages: 131072
>>>
>>> # dmesg | grep set_numa
>>> [ 0.000000][ T0] set_numa_mem: mem node for 0 = 1
>>> [ 0.005654][ T0] set_numa_mem: mem node for 1 = 1
>>>
>>> So is the problem more than just node zero having no memory?
>>>
I tried with just the patch Michael suggested on top of March 13 next tree.
I still see the same failure. Here is a snippet from the log
[ 0.000000] numa: NODE_DATA [mem 0x8bfedc900-0x8bfee3fff]
[ 0.000000] numa: NODE_DATA(0) on node 1
[ 0.000000] numa: NODE_DATA [mem 0x8bfed5200-0x8bfedc8ff]
[ 0.000000] rfi-flush: fallback displacement flush available
[ 0.000000] rfi-flush: mttrig type flush available
[ 0.000000] link-stack-flush: software flush enabled.
[ 0.000000] count-cache-flush: software flush disabled.
[ 0.000000] stf-barrier: eieio barrier available
[ 0.000000] lpar: H_BLOCK_REMOVE supports base psize:0 psize:0 block size:8
[ 0.000000] lpar: H_BLOCK_REMOVE supports base psize:0 psize:2 block size:8
[ 0.000000] lpar: H_BLOCK_REMOVE supports base psize:0 psize:10 block size:8
[ 0.000000] lpar: H_BLOCK_REMOVE supports base psize:2 psize:2 block size:8
[ 0.000000] lpar: H_BLOCK_REMOVE supports base psize:2 psize:10 block size:8
[ 0.000000] PPC64 nvram contains 15360 bytes
[ 0.000000] barrier-nospec: using ORI speculation barrier
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000000000000-0x00000008bfffffff]
[ 0.000000] Device empty
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 1: [mem 0x0000000000000000-0x00000008bfffffff]
[ 0.000000] Could not find start_pfn for node 0
[ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000000000000]
[ 0.000000] Initmem setup node 1 [mem 0x0000000000000000-0x00000008bfffffff]
[ 0.000000] percpu: Embedded 11 pages/cpu s624024 r0 d96872 u1048576
[ 0.000000] Built 2 zonelists, mobility grouping on. Total pages: 572880
Have attached the complete boot log.
Thanks
-Sachin
[-- Attachment #2: kernel-boot.log --]
[-- Type: application/octet-stream, Size: 20143 bytes --]
[ 1076.006474] kexec_core: Starting new kernel
[ 1076.026510] kexec: waiting for cpu 2 (physical 2) to enter 1 state
[ 1076.026522] kexec: waiting for cpu 27 (physical 27) to enter 1 state
[ 1076.026531] kexec: waiting for cpu 1 (physical 1) to enter 2 state
[ 1076.026580] kexec: waiting for cpu 2 (physical 2) to enter 2 state
[ 1076.026594] kexec: waiting for cpu 3 (physical 3) to enter 2 state
[ 1076.026602] kexec: waiting for cpu 4 (physical 4) to enter 2 state
[ 1076.026609] kexec: waiting for cpu 6 (physical 6) to enter 2 state
[ 1076.026617] kexec: waiting for cpu 11 (physical 11) to enter 2 state
[ 1076.026625] kexec: waiting for cpu 12 (physical 12) to enter 2 state
[ 1076.026632] kexec: waiting for cpu 13 (physical 13) to enter 2 state
[ 1076.190318] kexec: Starting switchover sequence.
I'm in purgatory
[ 0.000000] hash-mmu: Page sizes from device-tree:
[ 0.000000] hash-mmu: base_shift=12: shift=12, sllp=0x0000, avpnm=0x00000000, tlbiel=1, penc=0
[ 0.000000] hash-mmu: base_shift=12: shift=16, sllp=0x0000, avpnm=0x00000000, tlbiel=1, penc=7
[ 0.000000] hash-mmu: base_shift=12: shift=24, sllp=0x0000, avpnm=0x00000000, tlbiel=1, penc=56
[ 0.000000] hash-mmu: base_shift=16: shift=16, sllp=0x0110, avpnm=0x00000000, tlbiel=1, penc=1
[ 0.000000] hash-mmu: base_shift=16: shift=24, sllp=0x0110, avpnm=0x00000000, tlbiel=1, penc=8
[ 0.000000] hash-mmu: base_shift=24: shift=24, sllp=0x0100, avpnm=0x00000001, tlbiel=0, penc=0
[ 0.000000] hash-mmu: base_shift=34: shift=34, sllp=0x0120, avpnm=0x000007ff, tlbiel=0, penc=3
[ 0.000000] Using 1TB segments
[ 0.000000] hash-mmu: Initializing hash mmu with SLB
[ 0.000000] Linux version 5.6.0-rc5-next-20200313-autotest+ (root@ltc-zzci-2.aus.stglabs.ibm.com) (gcc version 8.3.1 20190507 (Red Hat 8.3.1-4) (GCC)) #2 SMP Sat Mar 14 02:57:33 CDT 2020
[ 0.000000] Found initrd at 0xc000000003350000:0xc000000004d9bd2d
[ 0.000000] Using pSeries machine description
[ 0.000000] printk: bootconsole [udbg0] enabled
[ 0.000000] Partition configured for 32 cpus.
[ 0.000000] CPU maps initialized for 8 threads per core
[ 0.000000] -----------------------------------------------------
[ 0.000000] phys_mem_size = 0x8c0000000
[ 0.000000] dcache_bsize = 0x80
[ 0.000000] icache_bsize = 0x80
[ 0.000000] cpu_features = 0x0001c07f8f5f91a7
[ 0.000000] possible = 0x0003fbffcf5fb1a7
[ 0.000000] always = 0x00000003800081a1
[ 0.000000] cpu_user_features = 0xdc0065c2 0xefe00000
[ 0.000000] mmu_features = 0x7c006001
[ 0.000000] firmware_features = 0x00000097c45bfc57
[ 0.000000] vmalloc start = 0xc008000000000000
[ 0.000000] IO start = 0xc00a000000000000
[ 0.000000] vmemmap start = 0xc00c000000000000
[ 0.000000] hash-mmu: ppc64_pft_size = 0x1c
[ 0.000000] hash-mmu: htab_hash_mask = 0x1fffff
[ 0.000000] -----------------------------------------------------
[ 0.000000] numa: NODE_DATA [mem 0x8bfedc900-0x8bfee3fff]
[ 0.000000] numa: NODE_DATA(0) on node 1
[ 0.000000] numa: NODE_DATA [mem 0x8bfed5200-0x8bfedc8ff]
[ 0.000000] rfi-flush: fallback displacement flush available
[ 0.000000] rfi-flush: mttrig type flush available
[ 0.000000] link-stack-flush: software flush enabled.
[ 0.000000] count-cache-flush: software flush disabled.
[ 0.000000] stf-barrier: eieio barrier available
[ 0.000000] lpar: H_BLOCK_REMOVE supports base psize:0 psize:0 block size:8
[ 0.000000] lpar: H_BLOCK_REMOVE supports base psize:0 psize:2 block size:8
[ 0.000000] lpar: H_BLOCK_REMOVE supports base psize:0 psize:10 block size:8
[ 0.000000] lpar: H_BLOCK_REMOVE supports base psize:2 psize:2 block size:8
[ 0.000000] lpar: H_BLOCK_REMOVE supports base psize:2 psize:10 block size:8
[ 0.000000] PPC64 nvram contains 15360 bytes
[ 0.000000] barrier-nospec: using ORI speculation barrier
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000000000000-0x00000008bfffffff]
[ 0.000000] Device empty
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 1: [mem 0x0000000000000000-0x00000008bfffffff]
[ 0.000000] Could not find start_pfn for node 0
[ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000000000000]
[ 0.000000] Initmem setup node 1 [mem 0x0000000000000000-0x00000008bfffffff]
[ 0.000000] percpu: Embedded 11 pages/cpu s624024 r0 d96872 u1048576
[ 0.000000] Built 2 zonelists, mobility grouping on. Total pages: 572880
[ 0.000000] Policy zone: Normal
[ 0.000000] Kernel command line: root=UUID=681ebf25-b7c8-49b9-b247-35a96bc8183f
[ 0.000000] Dentry cache hash table entries: 8388608 (order: 10, 67108864 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 4194304 (order: 9, 33554432 bytes, linear)
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] Memory: 36388416K/36700160K available (11840K kernel code, 1728K rwdata, 3712K rodata, 4992K init, 2847K bss, 311744K reserved, 0K cma-reserved)
[ 0.000000] SLUB: HWalign=128, Order=0-3, MinObjects=0, CPUs=32, Nodes=32
[ 0.000000] ftrace: allocating 29850 entries in 11 pages
[ 0.000000] ftrace: allocated 11 pages with 3 groups
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=2048 to nr_cpu_ids=32.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=32
[ 0.000000] NR_IRQS: 512, nr_irqs: 512, preallocated irqs: 16
[ 0.000000] xive: Using IRQ range [94000-9401f]
[ 0.000000] xive: Interrupt handling initialized with spapr backend
[ 0.000000] xive: Using priority 7 for all interrupts
[ 0.000000] xive: Using 64kB queues
[ 0.000000] rcu: Offload RCU callbacks from CPUs: (none).
[ 0.000000] random: get_random_u64 called from start_kernel+0x748/0x9a4 with crng_init=0
[ 0.000001] time_init: 56 bit decrementer (max: 7fffffffffffff)
[ 0.000064] clocksource: timebase: mask: 0xffffffffffffffff max_cycles: 0x761537d007, max_idle_ns: 440795202126 ns
[ 0.000172] clocksource: timebase mult[1f40000] shift[24] registered
[ 0.000299] Console: colour dummy device 80x25
[ 0.000349] printk: console [hvc0] enabled
[ 0.000349] printk: console [hvc0] enabled
[ 0.000395] printk: bootconsole [udbg0] disabled
[ 0.000395] printk: bootconsole [udbg0] disabled
[ 0.000472] mempolicy: Enabling automatic NUMA balancing. Configure with numa_balancing= or the kernel.numa_balancing sysctl
[ 0.000486] pid_max: default: 32768 minimum: 301
[ 0.000645] Mount-cache hash table entries: 131072 (order: 4, 1048576 bytes, linear)
[ 0.000716] Mountpoint-cache hash table entries: 131072 (order: 4, 1048576 bytes, linear)
[ 0.001517] EEH: pSeries platform initialized
[ 0.001525] POWER9 performance monitor hardware support registered
[ 0.001558] rcu: Hierarchical SRCU implementation.
[ 0.002269] smp: Bringing up secondary CPUs ...
[ 0.011609] smp: Brought up 2 nodes, 32 CPUs
[ 0.011617] numa: Node 0 CPUs:
[ 0.011620] numa: Node 1 CPUs: 0-31
[ 0.011624] Using small cores at SMT level
[ 0.011627] Using shared cache scheduler topology
[ 0.012586] devtmpfs: initialized
[ 0.015708] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.015720] futex hash table entries: 8192 (order: 4, 1048576 bytes, linear)
[ 0.015945] thermal_sys: Registered thermal governor 'fair_share'
[ 0.015946] thermal_sys: Registered thermal governor 'step_wise'
[ 0.016053] NET: Registered protocol family 16
[ 0.016196] audit: initializing netlink subsys (disabled)
[ 0.016247] audit: type=2000 audit(1584172954.010:1): state=initialized audit_enabled=0 res=1
[ 0.016358] cpuidle: using governor menu
[ 0.016532] pstore: Registered nvram as persistent store backend
[ 0.021111] PCI: Probing PCI hardware
[ 0.021118] EEH: No capable adapters found: recovery disabled.
[ 0.021183] pseries-rng: Registering arch random hook.
[ 0.022869] HugeTLB registered 16.0 MiB page size, pre-allocated 0 pages
[ 0.022876] HugeTLB registered 16.0 GiB page size, pre-allocated 0 pages
[ 0.263654] random: fast init done
[ 0.264788] iommu: Default domain type: Translated
[ 0.264827] vgaarb: loaded
[ 0.264909] SCSI subsystem initialized
[ 0.264939] usbcore: registered new interface driver usbfs
[ 0.264949] usbcore: registered new interface driver hub
[ 0.265029] usbcore: registered new device driver usb
[ 0.265148] EDAC MC: Ver: 3.0.0
[ 0.265428] clocksource: Switched to clocksource timebase
[ 0.276297] VFS: Disk quotas dquot_6.6.0
[ 0.276323] VFS: Dquot-cache hash table entries: 8192 (order 0, 65536 bytes)
[ 0.277822] NET: Registered protocol family 2
[ 0.277997] tcp_listen_portaddr_hash hash table entries: 32768 (order: 3, 524288 bytes, linear)
[ 0.278051] TCP established hash table entries: 524288 (order: 6, 4194304 bytes, linear)
[ 0.278910] TCP bind hash table entries: 65536 (order: 4, 1048576 bytes, linear)
[ 0.279002] TCP: Hash tables configured (established 524288 bind 65536)
[ 0.279041] UDP hash table entries: 32768 (order: 4, 1048576 bytes, linear)
[ 0.279142] UDP-Lite hash table entries: 32768 (order: 4, 1048576 bytes, linear)
[ 0.279300] NET: Registered protocol family 1
[ 0.279309] PCI: CLS 0 bytes, default 128
[ 0.279345] Trying to unpack rootfs image as initramfs...
[ 0.691840] Freeing initrd memory: 26880K
[ 0.694449] IOMMU table initialized, virtual merging enabled
[ 0.715112] hv-24x7: read 1530 catalog entries, created 537 event attrs (0 failures), 275 descs
[ 0.716123] workingset: timestamp_bits=38 max_order=20 bucket_order=0
[ 0.717188] zbud: loaded
[ 0.725830] NET: Registered protocol family 38
[ 0.725837] Key type asymmetric registered
[ 0.725841] Asymmetric key parser 'x509' registered
[ 0.725851] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
[ 0.725934] io scheduler mq-deadline registered
[ 0.725939] io scheduler kyber registered
[ 0.726367] atomic64_test: passed
[ 0.726400] PowerPC PowerNV PCI Hotplug Driver version: 0.1
[ 0.726708] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 0.726934] Non-volatile memory driver v1.3
[ 0.726961] Linux agpgart interface v0.103
[ 6.005618] tpm_ibmvtpm 30000003: CRQ initialization completed
[ 6.005625] tpm_ibmvtpm 30000003: ibmvtpm device is not ready
[ 6.005633] tpm_ibmvtpm 30000003: ibmvtpm device is not ready
[ 6.005859] rdac: device handler registered
[ 6.005900] hp_sw: device handler registered
[ 6.005904] emc: device handler registered
[ 6.005969] alua: device handler registered
[ 6.006050] libphy: Fixed MDIO Bus: probed
[ 6.006087] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 6.006097] ehci-pci: EHCI PCI platform driver
[ 6.006105] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 6.006114] ohci-pci: OHCI PCI platform driver
[ 6.006122] uhci_hcd: USB Universal Host Controller Interface driver
[ 6.006151] usbcore: registered new interface driver usbserial_generic
[ 6.006159] usbserial: USB Serial support registered for generic
[ 6.006211] mousedev: PS/2 mouse device common for all mice
[ 6.006305] rtc-generic rtc-generic: registered as rtc0
[ 6.006636] nx_compress_pseries ibm,compression-v1: nx842_OF_upd: max_sync_size new:65536 old:0
[ 6.006646] nx_compress_pseries ibm,compression-v1: nx842_OF_upd: max_sync_sg new:510 old:0
[ 6.006652] nx_compress_pseries ibm,compression-v1: nx842_OF_upd: max_sg_len new:4080 old:0
[ 6.006699] alg: No test for 842 (842-nx)
[ 6.007796] hid: raw HID events driver (C) Jiri Kosina
[ 6.007883] usbcore: registered new interface driver usbhid
[ 6.007886] usbhid: USB HID core driver
[ 6.007932] drop_monitor: Initializing network drop monitor service
[ 6.008011] Initializing XFRM netlink socket
[ 6.008150] NET: Registered protocol family 10
[ 6.008417] Segment Routing with IPv6
[ 6.008434] NET: Registered protocol family 17
[ 6.008976] registered taskstats version 1
[ 6.009008] zswap: loaded using pool lzo/zbud
[ 6.009141] pstore: Using crash dump compression: deflate
[ 6.013169] Key type big_key registered
[ 6.013328] rtc-generic rtc-generic: setting system clock to 2020-03-14T08:02:40 UTC (1584172960)
[ 6.014708] Freeing unused kernel memory: 4992K
[ 6.014713] Kernel memory protection not selected by kernel config.
[ 6.014718] Run /init as init process
[ 6.023848] systemd[1]: systemd 239 running in system mode. (+PAM +AUDIT +SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=legacy)
[ 6.024035] systemd[1]: Detected architecture ppc64-le.
[ 6.024041] systemd[1]: Running in initial RAM disk.
Welcome to Red Hat Enterprise Linux 8.1 Beta (Ootpa) dracut-049-26.git20190806.el8 (Initramfs)!
[ 6.075728] systemd[1]: Set hostname to <ltc-zzci-2.aus.stglabs.ibm.com>.
[ 6.128043] random: systemd: uninitialized urandom read (16 bytes read)
[ 6.128067] systemd[1]: Reached target Timers.
[ OK ] Reached target Timers.
[ 6.128205] random: systemd: uninitialized urandom read (16 bytes read)
[ 6.128261] systemd[1]: Listening on udev Kernel Socket.
[ OK ] Listening on udev Kernel Socket.
[ 6.128324] random: systemd: uninitialized urandom read (16 bytes read)
[ 6.128391] systemd[1]: Listening on udev Control Socket.
[ OK ] Listening on udev Control Socket.
[ 6.128524] systemd[1]: Listening on Journal Socket.
[ OK ] Listening on Journal Socket.
[ 6.129551] BUG: Kernel NULL pointer dereference on read at 0x000073b0
[ 6.129557] Faulting instruction address: 0xc0000000003d5d44
[ 6.129562] Oops: Kernel access of bad area, sig: 11 [#1]
[ 6.129567] LE PAGE_SIZE=64K MMU=Hash SMP NR_CPUS=2048 NUMA pSeries
[ 6.129571] Modules linked in:
[ 6.129576] CPU: 10 PID: 1 Comm: systemd Not tainted 5.6.0-rc5-next-20200313-autotest+ #2
[ 6.129581] NIP: c0000000003d5d44 LR: c0000000003d62e4 CTR: 0000000000000000
[ 6.129587] REGS: c0000008b37836d0 TRAP: 0300 Not tainted (5.6.0-rc5-next-20200313-autotest+)
[ 6.129593] MSR: 8000000000009033 <SF,EE,ME,IR,DR,RI,LE> CR: 24004844 XER: 00000000
[ 6.129600] CFAR: c00000000000dec4 DAR: 00000000000073b0 DSISR: 40000000 IRQMASK: 1
[ 6.129600] GPR00: c0000000003d62e4 c0000008b3783960 c00000000155e300 c0000008b301f500
[ 6.129600] GPR04: 0000000000000dc0 0000000000000002 c000000000343938 c0000008baa98620
[ 6.129600] GPR08: 00000008b99f0000 0000000000000001 0000000000000000 0000000000000000
[ 6.129600] GPR12: 0000000024004844 c00000001eca1a00 0000000000000000 0000000000000000
[ 6.129600] GPR16: c0000008a3f62048 c000000001595818 c000000001750ca8 0000000000000002
[ 6.129600] GPR20: c000000001750cb8 c000000001624478 0000000fffffffe0 5deadbeef0000122
[ 6.129600] GPR24: 0000000000000001 0000000000000dc0 0000000000000002 c000000000343938
[ 6.129600] GPR28: c0000008b301f500 c0000008baa98620 0000000000000000 c00c00000000d100
[ 6.129647] NIP [c0000000003d5d44] ___slab_alloc+0x1f4/0x760
[ 6.129652] LR [c0000000003d62e4] __slab_alloc+0x34/0x60
[ 6.129656] Call Trace:
[ 6.129659] [c0000008b3783960] [c0000000003d5e84] ___slab_alloc+0x334/0x760 (unreliable)
[ 6.129666] [c0000008b3783a40] [c0000000003d62e4] __slab_alloc+0x34/0x60
[ 6.129671] [c0000008b3783a70] [c0000000003d76f0] __kmalloc_node+0x110/0x490
[ 6.129677] [c0000008b3783af0] [c000000000343938] kvmalloc_node+0x58/0x110
[ 6.129683] [c0000008b3783b30] [c0000000003ffb84] mem_cgroup_css_online+0x104/0x270
[ 6.129689] [c0000008b3783b90] [c000000000234d88] online_css+0x48/0xd0
[ 6.129695] [c0000008b3783bc0] [c00000000023de5c] cgroup_apply_control_enable+0x2ec/0x4d0
[ 6.129701] [c0000008b3783ca0] [c000000000241678] cgroup_mkdir+0x228/0x5f0
[ 6.129706] [c0000008b3783d10] [c0000000005201a0] kernfs_iop_mkdir+0x90/0xf0
[ 6.129713] [c0000008b3783d50] [c00000000043e240] vfs_mkdir+0x110/0x230
[ 6.129718] [c0000008b3783da0] [c000000000441d20] do_mkdirat+0xb0/0x1a0
[ 6.129724] [c0000008b3783e20] [c00000000000b278] system_call+0x5c/0x68
[ 6.129728] Instruction dump:
[ 6.129731] 7c421378 e95f0000 714a0001 4082fff0 4bffff64 60000000 60000000 faa10088
[ 6.129738] 3ea2000c 3ab56178 7b4a1f24 7d55502a <e94a73b0> 2faa0000 409e0394 3d02002a
[ 6.129746] ---[ end trace fb1a7e13ad04058f ]---
[ 6.131789]
[ 7.131801] Kernel panic - not syncing: Fatal exception
[ 7.138925] ------------[ cut here ]------------
[ 7.138935] WARNING: CPU: 10 PID: 1 at drivers/tty/vt/vt.c:4266 do_unblank_screen+0x190/0x250
[ 7.138943] Modules linked in:
[ 7.138949] CPU: 10 PID: 1 Comm: systemd Tainted: G D 5.6.0-rc5-next-20200313-autotest+ #2
[ 7.138958] NIP: c0000000006ec1c0 LR: c0000000006ec1ac CTR: c000000000b7d410
[ 7.138966] REGS: c0000008b37831b0 TRAP: 0700 Tainted: G D (5.6.0-rc5-next-20200313-autotest+)
[ 7.138975] MSR: 8000000000021033 <SF,ME,IR,DR,RI,LE> CR: 28002242 XER: 2004000c
[ 7.138986] CFAR: c0000000001c67d8 IRQMASK: 3
[ 7.138986] GPR00: c0000000006ec1ac c0000008b3783440 c00000000155e300 0000000000000000
[ 7.138986] GPR04: 0000000000000003 c0000008aea8a00e 0000000000001dd7 c0000008b3783380
[ 7.138986] GPR08: c0000000014234e0 0000000000000000 0000000000000000 c0000008b37831ff
[ 7.138986] GPR12: 0000000028002448 c00000001eca1a00 0000000000000000 0000000000000000
[ 7.138986] GPR16: c0000008a3f62048 c000000001595818 c000000001750ca8 0000000000000002
[ 7.138986] GPR20: c000000001750cb8 c000000001624478 0000000fffffffe0 5deadbeef0000122
[ 7.138986] GPR24: 0000000000000001 0000000000000dc0 c00000000142c5b0 c000000000343938
[ 7.138986] GPR28: c000000001636f58 c000000001636f80 0000000000000000 c000000001745a88
[ 7.139053] NIP [c0000000006ec1c0] do_unblank_screen+0x190/0x250
[ 7.139060] LR [c0000000006ec1ac] do_unblank_screen+0x17c/0x250
[ 7.139067] Call Trace:
[ 7.139071] [c0000008b3783440] [c0000000006ec1dc] do_unblank_screen+0x1ac/0x250 (unreliable)
[ 7.139082] [c0000008b37834c0] [c00000000013caa4] panic+0x1e8/0x414
[ 7.139091] [c0000008b3783560] [c00000000002a70c] oops_end+0x1ac/0x1b0
[ 7.139099] [c0000008b37835e0] [c0000000000848a0] bad_page_fault+0x190/0x1e0
[ 7.139108] [c0000008b3783660] [c00000000000a8a4] handle_page_fault+0x2c/0x30
[ 7.139118] --- interrupt: 300 at ___slab_alloc+0x1f4/0x760
[ 7.139118] LR = __slab_alloc+0x34/0x60
[ 7.139128] [c0000008b3783960] [c0000000003d5e84] ___slab_alloc+0x334/0x760 (unreliable)
[ 7.139137] [c0000008b3783a40] [c0000000003d62e4] __slab_alloc+0x34/0x60
[ 7.139145] [c0000008b3783a70] [c0000000003d76f0] __kmalloc_node+0x110/0x490
[ 7.139153] [c0000008b3783af0] [c000000000343938] kvmalloc_node+0x58/0x110
[ 7.139162] [c0000008b3783b30] [c0000000003ffb84] mem_cgroup_css_online+0x104/0x270
[ 7.139171] [c0000008b3783b90] [c000000000234d88] online_css+0x48/0xd0
[ 7.139178] [c0000008b3783bc0] [c00000000023de5c] cgroup_apply_control_enable+0x2ec/0x4d0
[ 7.139187] [c0000008b3783ca0] [c000000000241678] cgroup_mkdir+0x228/0x5f0
[ 7.139196] [c0000008b3783d10] [c0000000005201a0] kernfs_iop_mkdir+0x90/0xf0
[ 7.139205] [c0000008b3783d50] [c00000000043e240] vfs_mkdir+0x110/0x230
[ 7.139213] [c0000008b3783da0] [c000000000441d20] do_mkdirat+0xb0/0x1a0
[ 7.139221] [c0000008b3783e20] [c00000000000b278] system_call+0x5c/0x68
[ 7.139227] Instruction dump:
[ 7.139232] 4e800020 60000000 60000000 60000000 7c0802a6 f8010090 4bada621 60000000
[ 7.139243] 813f0000 7d231b78 2f830000 409e0034 <0fe00000> e8010090 7c0803a6 4bfffeac
[ 7.139254] ---[ end trace fb1a7e13ad040590 ]---
[ 7.139260] Rebooting in 10 seconds..
^ permalink raw reply
* Re: [PATCH v3] powerpc/fsl-85xx: fix compile error
From: Christophe Leroy @ 2020-03-14 7:26 UTC (permalink / raw)
To: WANG Wenhu, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman, Allison Randal, Richard Fontana,
Greg Kroah-Hartman, Thomas Gleixner, linuxppc-dev, linux-kernel
Cc: kernel, trivial, stable
In-Reply-To: <20200314051035.64552-1-wenhu.wang@vivo.com>
Le 14/03/2020 à 06:10, WANG Wenhu a écrit :
> Include "linux/of_address.h" to fix the compile error for
> mpc85xx_l2ctlr_of_probe() when compiling fsl_85xx_cache_sram.c.
>
> CC arch/powerpc/sysdev/fsl_85xx_l2ctlr.o
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c: In function ‘mpc85xx_l2ctlr_of_probe’:
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:90:11: error: implicit declaration of function ‘of_iomap’; did you mean ‘pci_iomap’? [-Werror=implicit-function-declaration]
> l2ctlr = of_iomap(dev->dev.of_node, 0);
> ^~~~~~~~
> pci_iomap
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:90:9: error: assignment makes pointer from integer without a cast [-Werror=int-conversion]
> l2ctlr = of_iomap(dev->dev.of_node, 0);
> ^
> cc1: all warnings being treated as errors
> scripts/Makefile.build:267: recipe for target 'arch/powerpc/sysdev/fsl_85xx_l2ctlr.o' failed
> make[2]: *** [arch/powerpc/sysdev/fsl_85xx_l2ctlr.o] Error 1
>
> Fixes: commit 6db92cc9d07d ("powerpc/85xx: add cache-sram support")
> Cc: stable <stable@vger.kernel.org>
> Signed-off-by: WANG Wenhu <wenhu.wang@vivo.com>
Reviewed-by: Christophe Leroy <christophe.leroy@c-s.fr>
^ permalink raw reply
* [PATCH v3] powerpc/fsl-85xx: fix compile error
From: WANG Wenhu @ 2020-03-14 5:10 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
WANG Wenhu, Allison Randal, Richard Fontana, Greg Kroah-Hartman,
Thomas Gleixner, linuxppc-dev, linux-kernel
Cc: kernel, trivial, stable
Include "linux/of_address.h" to fix the compile error for
mpc85xx_l2ctlr_of_probe() when compiling fsl_85xx_cache_sram.c.
CC arch/powerpc/sysdev/fsl_85xx_l2ctlr.o
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c: In function ‘mpc85xx_l2ctlr_of_probe’:
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:90:11: error: implicit declaration of function ‘of_iomap’; did you mean ‘pci_iomap’? [-Werror=implicit-function-declaration]
l2ctlr = of_iomap(dev->dev.of_node, 0);
^~~~~~~~
pci_iomap
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:90:9: error: assignment makes pointer from integer without a cast [-Werror=int-conversion]
l2ctlr = of_iomap(dev->dev.of_node, 0);
^
cc1: all warnings being treated as errors
scripts/Makefile.build:267: recipe for target 'arch/powerpc/sysdev/fsl_85xx_l2ctlr.o' failed
make[2]: *** [arch/powerpc/sysdev/fsl_85xx_l2ctlr.o] Error 1
Fixes: commit 6db92cc9d07d ("powerpc/85xx: add cache-sram support")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: WANG Wenhu <wenhu.wang@vivo.com>
---
Changes since v1:
1. v3: Cc stable into the sign-off area;
2. v2: modified the label: "Fixed: " -> "Fixes: ";
Link: https://lore.kernel.org/linuxppc-dev/ACMAbgCmCMyKfKbub-5A5qo0.3.1584161421763.Hmail.wenhu.wang@vivo.com
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index 2d0af0c517bb..7533572492f0 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -10,6 +10,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_platform.h>
+#include <linux/of_address.h>
#include <asm/io.h>
#include "fsl_85xx_cache_ctlr.h"
--
2.17.1
^ permalink raw reply related
* Re:Re: [PATCH v2] powerpc/fsl-85xx: fix compile error
From: 王文虎 @ 2020-03-14 4:50 UTC (permalink / raw)
To: Christophe Leroy
Cc: Kate Stewart, trivial, kernel, linux-kernel, Richard Fontana,
Paul Mackerras, Thomas Gleixner, linuxppc-dev, Allison Randal
In-Reply-To: <6eba5d46-bb3a-03bb-376d-2a6e684d018e@c-s.fr>
发件人：Christophe Leroy <christophe.leroy@c-s.fr>
发送日期：2020-03-14 03:24:20
收件人："王文虎" <wenhu.wang@vivo.com>
抄送人：Benjamin Herrenschmidt <benh@kernel.crashing.org>,Paul Mackerras <paulus@samba.org>,Michael Ellerman <mpe@ellerman.id.au>,Richard Fontana <rfontana@redhat.com>,Kate Stewart <kstewart@linuxfoundation.org>,Allison Randal <allison@lohutok.net>,Thomas Gleixner <tglx@linutronix.de>,linuxppc-dev@lists.ozlabs.org,linux-kernel@vger.kernel.org,kernel@vivo.com,trivial@kernel.org
主题：Re: [PATCH v2] powerpc/fsl-85xx: fix compile error>
>
>Le 13/03/2020 à 19:17, 王文虎 a écrit :
>> 发件人：Christophe Leroy <christophe.leroy@c-s.fr>
>> 发送日期：2020-03-14 01:45:11
>> 收件人：WANG Wenhu <wenhu.wang@vivo.com>,Benjamin Herrenschmidt <benh@kernel.crashing.org>,Paul Mackerras <paulus@samba.org>,Michael Ellerman <mpe@ellerman.id.au>,Richard Fontana <rfontana@redhat.com>,Kate Stewart <kstewart@linuxfoundation.org>,Allison Randal <allison@lohutok.net>,Thomas Gleixner <tglx@linutronix.de>,linuxppc-dev@lists.ozlabs.org,linux-kernel@vger.kernel.org
>> 抄送人：kernel@vivo.com,trivial@kernel.org
>> 主题：Re: [PATCH v2] powerpc/fsl-85xx: fix compile error>
>>>
>>> Le 13/03/2020 à 18:19, WANG Wenhu a écrit :
>>>> Include "linux/of_address.h" to fix the compile error for
>>>> mpc85xx_l2ctlr_of_probe() when compiling fsl_85xx_cache_sram.c.
>>>>
>>>> CC arch/powerpc/sysdev/fsl_85xx_l2ctlr.o
>>>> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c: In function ‘mpc85xx_l2ctlr_of_probe’:
>>>> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:90:11: error: implicit declaration of function ‘of_iomap’; did you mean ‘pci_iomap’? [-Werror=implicit-function-declaration]
>>>> l2ctlr = of_iomap(dev->dev.of_node, 0);
>>>> ^~~~~~~~
>>>> pci_iomap
>>>> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:90:9: error: assignment makes pointer from integer without a cast [-Werror=int-conversion]
>>>> l2ctlr = of_iomap(dev->dev.of_node, 0);
>>>> ^
>>>> cc1: all warnings being treated as errors
>>>> scripts/Makefile.build:267: recipe for target 'arch/powerpc/sysdev/fsl_85xx_l2ctlr.o' failed
>>>> make[2]: *** [arch/powerpc/sysdev/fsl_85xx_l2ctlr.o] Error 1
>>>>
>>>> Fixes: commit 6db92cc9d07d ("powerpc/85xx: add cache-sram support")
>>>
>>> Shouldn't you Cc stable as well ?
>> Pretty sure if it makes a difference(that I did not recognize).
>> Does the inconsistency of Cc lead to a failure on classification
>> or something else which may confuse you?
>
>See
>https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/Documentation/process/submitting-patches.rst?h=v5.1.9#n299
Seen, and I 'll do a repatch of v3 with stable being added
to sign-off area as Cc list. Thanks a lot.
Wenhu
>
>>>
>>>> Signed-off-by: WANG Wenhu <wenhu.wang@vivo.com>
>>>> ---
>>>
>>> What's the difference between v1 and v2 ?
>> The label field modification: "Fixed" -> "Fixes", which now is
>> identified successfully. Really sorry for the fault on v1.
>
>Ok. Usually people tell here (just below the ---) what is the difference
>between the different versions. It helps people understand what the
>changes are.
>
>Christophe
^ permalink raw reply
* Re: [PATCH] powerpc/pseries: Fix MCE handling on pseries
From: Nicholas Piggin @ 2020-03-14 3:48 UTC (permalink / raw)
To: Ganesh Goudar, linuxppc-dev, mpe; +Cc: mahesh
In-Reply-To: <20200313140418.7940-1-ganeshgr@linux.ibm.com>
Ganesh Goudar's on March 14, 2020 12:04 am:
> MCE handling on pSeries platform fails as recent rework to use common
> code for pSeries and PowerNV in machine check error handling tries to
> access per-cpu variables in realmode. The per-cpu variables may be
> outside the RMO region on pSeries platform and needs translation to be
> enabled for access. Just moving these per-cpu variable into RMO region
> did'nt help because we queue some work to workqueues in real mode, which
> again tries to touch per-cpu variables.
Which queues are these? We should not be using Linux workqueues, but the
powerpc mce code which uses irq_work.
> Also fwnmi_release_errinfo()
> cannot be called when translation is not enabled.
Why not?
> This patch fixes this by enabling translation in the exception handler
> when all required real mode handling is done. This change only affects
> the pSeries platform.
Not supposed to do this, because we might not be in a state
where the MMU is ready to be turned on at this point.
I'd like to understand better which accesses are a problem, and whether
we can fix them all to be in the RMO.
Thanks,
Nick
^ permalink raw reply
* [PATCH v6 11/11] misc: pci_endpoint_test: Add LS1088a in pci_device_id table
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>
Add LS1088a in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in LS1088a.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
---
v2:
- No change.
v3:
- No change.
v4:
- Use a maco to define the LS1088a device ID.
v5:
- No change.
v6:
- No change.
drivers/misc/pci_endpoint_test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index a5e3170..72d694f 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -65,6 +65,7 @@
#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
#define PCI_DEVICE_ID_TI_AM654 0xb00c
+#define PCI_DEVICE_ID_LS1088A 0x80c0
#define is_am654_pci_dev(pdev) \
((pdev)->device == PCI_DEVICE_ID_TI_AM654)
@@ -793,6 +794,7 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },
+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A) },
{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
.driver_data = (kernel_ulong_t)&am654_data
--
2.9.5
^ permalink raw reply related
* [PATCH v6 10/11] arm64: dts: layerscape: Add PCIe EP node for ls1088a
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>
Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
---
v2:
- Remove the pf-offset proparty.
v3:
- No change.
v4:
- No change.
v5:
- No change.
v6:
- No change.
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 ++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index ec6013a..cb0805b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -497,6 +497,17 @@
status = "disabled";
};
+ pcie_ep@3400000 {
+ compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x20 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <24>;
+ num-ob-windows = <128>;
+ max-functions = /bits/ 8 <2>;
+ status = "disabled";
+ };
+
pcie@3500000 {
compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -522,6 +533,16 @@
status = "disabled";
};
+ pcie_ep@3500000 {
+ compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x28 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ status = "disabled";
+ };
+
pcie@3600000 {
compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -547,6 +568,16 @@
status = "disabled";
};
+ pcie_ep@3600000 {
+ compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x30 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ status = "disabled";
+ };
+
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
--
2.9.5
^ permalink raw reply related
* [PATCH v6 09/11] PCI: layerscape: Add EP mode support for ls1088a and ls2088a
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>
Add PCIe EP mode support for ls1088a and ls2088a, there are some
difference between LS1 and LS2 platform, so refactor the code of
the EP driver.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v2:
- This is a new patch for supporting the ls1088a and ls2088a platform.
v3:
- Adjust the some struct assignment order in probe function.
v4:
- No change.
v5:
- No change.
v6:
- No change.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 72 +++++++++++++++++++-------
1 file changed, 53 insertions(+), 19 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index bfab1c6..84206f2 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -20,27 +20,29 @@
#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
-struct ls_pcie_ep {
- struct dw_pcie *pci;
- struct pci_epc_features *ls_epc;
+#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
+
+struct ls_pcie_ep_drvdata {
+ u32 func_offset;
+ const struct dw_pcie_ep_ops *ops;
+ const struct dw_pcie_ops *dw_pcie_ops;
};
-#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
+struct ls_pcie_ep {
+ struct dw_pcie *pci;
+ struct pci_epc_features *ls_epc;
+ const struct ls_pcie_ep_drvdata *drvdata;
+};
static int ls_pcie_establish_link(struct dw_pcie *pci)
{
return 0;
}
-static const struct dw_pcie_ops ls_pcie_ep_ops = {
+static const struct dw_pcie_ops dw_ls_pcie_ep_ops = {
.start_link = ls_pcie_establish_link,
};
-static const struct of_device_id ls_pcie_ep_of_match[] = {
- { .compatible = "fsl,ls-pcie-ep",},
- { },
-};
-
static const struct pci_epc_features*
ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
{
@@ -87,10 +89,39 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
}
}
-static const struct dw_pcie_ep_ops pcie_ep_ops = {
+static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
+ u8 func_no)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
+
+ WARN_ON(func_no && !pcie->drvdata->func_offset);
+ return pcie->drvdata->func_offset * func_no;
+}
+
+static const struct dw_pcie_ep_ops ls_pcie_ep_ops = {
.ep_init = ls_pcie_ep_init,
.raise_irq = ls_pcie_ep_raise_irq,
.get_features = ls_pcie_ep_get_features,
+ .func_conf_select = ls_pcie_ep_func_conf_select,
+};
+
+static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = {
+ .ops = &ls_pcie_ep_ops,
+ .dw_pcie_ops = &dw_ls_pcie_ep_ops,
+};
+
+static const struct ls_pcie_ep_drvdata ls2_ep_drvdata = {
+ .func_offset = 0x20000,
+ .ops = &ls_pcie_ep_ops,
+ .dw_pcie_ops = &dw_ls_pcie_ep_ops,
+};
+
+static const struct of_device_id ls_pcie_ep_of_match[] = {
+ { .compatible = "fsl,ls1046a-pcie-ep", .data = &ls1_ep_drvdata },
+ { .compatible = "fsl,ls1088a-pcie-ep", .data = &ls2_ep_drvdata },
+ { .compatible = "fsl,ls2088a-pcie-ep", .data = &ls2_ep_drvdata },
+ { },
};
static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
@@ -103,7 +134,7 @@ static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
int ret;
ep = &pci->ep;
- ep->ops = &pcie_ep_ops;
+ ep->ops = pcie->drvdata->ops;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
if (!res)
@@ -142,20 +173,23 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
if (!ls_epc)
return -ENOMEM;
- dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
- pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
- if (IS_ERR(pci->dbi_base))
- return PTR_ERR(pci->dbi_base);
+ pcie->drvdata = of_device_get_match_data(dev);
- pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
pci->dev = dev;
- pci->ops = &ls_pcie_ep_ops;
- pcie->pci = pci;
+ pci->ops = pcie->drvdata->dw_pcie_ops;
ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
+ pcie->pci = pci;
pcie->ls_epc = ls_epc;
+ dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
+ pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
+ if (IS_ERR(pci->dbi_base))
+ return PTR_ERR(pci->dbi_base);
+
+ pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
+
platform_set_drvdata(pdev, pcie);
ret = ls_add_pcie_ep(pcie, pdev);
--
2.9.5
^ permalink raw reply related
* [PATCH v6 08/11] PCI: layerscape: Modify the MSIX to the doorbell mode
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver
before, because the ls1046a platform don't support the MSIX feature
and msix_capable was always set to false.
Now that add the ls1088a platform with MSIX support, use the doorbell
method to support the MSIX feature.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
---
v2:
- No change
v3:
- Modify the commit message make it clearly.
v4:
- No change
v5:
- Modify the commit message.
v6:
- No change.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index 9601f9c..bfab1c6 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -79,7 +79,8 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
case PCI_EPC_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
case PCI_EPC_IRQ_MSIX:
- return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
+ return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
+ interrupt_num);
default:
dev_err(pci->dev, "UNKNOWN IRQ type\n");
return -EINVAL;
--
2.9.5
^ permalink raw reply related
* [PATCH v6 07/11] PCI: layerscape: Modify the way of getting capability with different PEX
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>
The different PCIe controller in one board may be have different
capability of MSI or MSIX, so change the way of getting the MSI
capability, make it more flexible.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v2:
- Remove the repeated assignment code.
v3:
- Use ep_func msi_cap and msix_cap to decide the msi_capable and
msix_capable of pci_epc_features struct.
v4:
- No change.
v5:
- No change.
v6:
- No change.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 31 +++++++++++++++++++-------
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index 0691d9a..9601f9c 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -22,6 +22,7 @@
struct ls_pcie_ep {
struct dw_pcie *pci;
+ struct pci_epc_features *ls_epc;
};
#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
@@ -40,26 +41,31 @@ static const struct of_device_id ls_pcie_ep_of_match[] = {
{ },
};
-static const struct pci_epc_features ls_pcie_epc_features = {
- .linkup_notifier = false,
- .msi_capable = true,
- .msix_capable = false,
- .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
-};
-
static const struct pci_epc_features*
ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
{
- return &ls_pcie_epc_features;
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
+
+ return pcie->ls_epc;
}
static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
+ struct dw_pcie_ep_func *ep_func;
enum pci_barno bar;
+ ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);
+ if (!ep_func)
+ return;
+
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
dw_pcie_ep_reset_bar(pci, bar);
+
+ pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;
+ pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
}
static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
@@ -119,6 +125,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct dw_pcie *pci;
struct ls_pcie_ep *pcie;
+ struct pci_epc_features *ls_epc;
struct resource *dbi_base;
int ret;
@@ -130,6 +137,10 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
if (!pci)
return -ENOMEM;
+ ls_epc = devm_kzalloc(dev, sizeof(*ls_epc), GFP_KERNEL);
+ if (!ls_epc)
+ return -ENOMEM;
+
dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
if (IS_ERR(pci->dbi_base))
@@ -140,6 +151,10 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
pci->ops = &ls_pcie_ep_ops;
pcie->pci = pci;
+ ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
+
+ pcie->ls_epc = ls_epc;
+
platform_set_drvdata(pdev, pcie);
ret = ls_add_pcie_ep(pcie, pdev);
--
2.9.5
^ permalink raw reply related
* [PATCH v6 06/11] PCI: layerscape: Fix some format issue of the code
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>
Fix some format issue of the code in EP driver.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
---
v2:
- No change.
v3:
- No change.
v4:
- No change.
v5:
- No change.
v6:
- No change.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index 0d151ce..0691d9a 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -63,7 +63,7 @@ static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
}
static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type, u16 interrupt_num)
+ enum pci_epc_irq_type type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -87,7 +87,7 @@ static const struct dw_pcie_ep_ops pcie_ep_ops = {
};
static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
- struct platform_device *pdev)
+ struct platform_device *pdev)
{
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
--
2.9.5
^ permalink raw reply related
* [PATCH v6 05/11] dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>
Add compatible strings for ls1088a and ls2088a.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2:
- No change.
v3:
- Use one valid combination of compatible strings.
v4:
- Add the comma between the two compatible.
v5:
- No change.
v6:
- No change.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 99a386e..daa99f7 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -24,6 +24,8 @@ Required properties:
"fsl,ls1028a-pcie"
EP mode:
"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
+ "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
+ "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
- reg: base addresses and lengths of the PCIe controller register blocks.
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
--
2.9.5
^ permalink raw reply related
* [PATCH v6 04/11] PCI: designware-ep: Modify MSI and MSIX CAP way of finding
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>
Each PF of EP device should have it's own MSI or MSIX capabitily
struct, so create a dw_pcie_ep_func struct and remove the msi_cap
and msix_cap to this struct from dw_pcie_ep, and manage the PFs
with a list.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v3:
- This is a new patch, to fix the issue of MSI and MSIX CAP way of
finding.
v4:
- Correct some word of commit message.
v5:
- No change.
v6:
- Fix up the compile error.
drivers/pci/controller/dwc/pcie-designware-ep.c | 135 +++++++++++++++++++++---
drivers/pci/controller/dwc/pcie-designware.h | 18 +++-
2 files changed, 134 insertions(+), 19 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 933bb89..fb915f2 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -19,6 +19,19 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
pci_epc_linkup(epc);
}
+struct dw_pcie_ep_func *
+dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
+{
+ struct dw_pcie_ep_func *ep_func;
+
+ list_for_each_entry(ep_func, &ep->func_list, list) {
+ if (ep_func->func_no == func_no)
+ return ep_func;
+ }
+
+ return NULL;
+}
+
static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
{
unsigned int func_offset = 0;
@@ -59,6 +72,47 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
__dw_pcie_ep_reset_bar(pci, func_no, bar, 0);
}
+static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no,
+ u8 cap_ptr, u8 cap)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ unsigned int func_offset = 0;
+ u8 cap_id, next_cap_ptr;
+ u16 reg;
+
+ if (!cap_ptr)
+ return 0;
+
+ func_offset = dw_pcie_ep_func_select(ep, func_no);
+
+ reg = dw_pcie_readw_dbi(pci, func_offset + cap_ptr);
+ cap_id = (reg & 0x00ff);
+
+ if (cap_id > PCI_CAP_ID_MAX)
+ return 0;
+
+ if (cap_id == cap)
+ return cap_ptr;
+
+ next_cap_ptr = (reg & 0xff00) >> 8;
+ return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap);
+}
+
+static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, u8 func_no, u8 cap)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ unsigned int func_offset = 0;
+ u8 next_cap_ptr;
+ u16 reg;
+
+ func_offset = dw_pcie_ep_func_select(ep, func_no);
+
+ reg = dw_pcie_readw_dbi(pci, func_offset + PCI_CAPABILITY_LIST);
+ next_cap_ptr = (reg & 0x00ff);
+
+ return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap);
+}
+
static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
struct pci_epf_header *hdr)
{
@@ -246,13 +300,18 @@ static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
u32 val, reg;
unsigned int func_offset = 0;
+ struct dw_pcie_ep_func *ep_func;
- if (!ep->msi_cap)
+ ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
+ if (!ep_func)
+ return -EINVAL;
+
+ if (!ep_func->msi_cap)
return -EINVAL;
func_offset = dw_pcie_ep_func_select(ep, func_no);
- reg = ep->msi_cap + func_offset + PCI_MSI_FLAGS;
+ reg = ep_func->msi_cap + func_offset + PCI_MSI_FLAGS;
val = dw_pcie_readw_dbi(pci, reg);
if (!(val & PCI_MSI_FLAGS_ENABLE))
return -EINVAL;
@@ -268,13 +327,18 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
u32 val, reg;
unsigned int func_offset = 0;
+ struct dw_pcie_ep_func *ep_func;
+
+ ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
+ if (!ep_func)
+ return -EINVAL;
- if (!ep->msi_cap)
+ if (!ep_func->msi_cap)
return -EINVAL;
func_offset = dw_pcie_ep_func_select(ep, func_no);
- reg = ep->msi_cap + func_offset + PCI_MSI_FLAGS;
+ reg = ep_func->msi_cap + func_offset + PCI_MSI_FLAGS;
val = dw_pcie_readw_dbi(pci, reg);
val &= ~PCI_MSI_FLAGS_QMASK;
val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
@@ -291,13 +355,18 @@ static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
u32 val, reg;
unsigned int func_offset = 0;
+ struct dw_pcie_ep_func *ep_func;
+
+ ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
+ if (!ep_func)
+ return -EINVAL;
- if (!ep->msix_cap)
+ if (!ep_func->msix_cap)
return -EINVAL;
func_offset = dw_pcie_ep_func_select(ep, func_no);
- reg = ep->msix_cap + func_offset + PCI_MSIX_FLAGS;
+ reg = ep_func->msix_cap + func_offset + PCI_MSIX_FLAGS;
val = dw_pcie_readw_dbi(pci, reg);
if (!(val & PCI_MSIX_FLAGS_ENABLE))
return -EINVAL;
@@ -313,13 +382,18 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
u32 val, reg;
unsigned int func_offset = 0;
+ struct dw_pcie_ep_func *ep_func;
- if (!ep->msix_cap)
+ ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
+ if (!ep_func)
+ return -EINVAL;
+
+ if (!ep_func->msix_cap)
return -EINVAL;
func_offset = dw_pcie_ep_func_select(ep, func_no);
- reg = ep->msix_cap + func_offset + PCI_MSIX_FLAGS;
+ reg = ep_func->msix_cap + func_offset + PCI_MSIX_FLAGS;
val = dw_pcie_readw_dbi(pci, reg);
val &= ~PCI_MSIX_FLAGS_QSIZE;
val |= interrupts;
@@ -404,6 +478,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct dw_pcie_ep_func *ep_func;
struct pci_epc *epc = ep->epc;
unsigned int aligned_offset;
unsigned int func_offset = 0;
@@ -413,25 +488,29 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
bool has_upper;
int ret;
- if (!ep->msi_cap)
+ ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
+ if (!ep_func)
+ return -EINVAL;
+
+ if (!ep_func->msi_cap)
return -EINVAL;
func_offset = dw_pcie_ep_func_select(ep, func_no);
/* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
- reg = ep->msi_cap + func_offset + PCI_MSI_FLAGS;
+ reg = ep_func->msi_cap + func_offset + PCI_MSI_FLAGS;
msg_ctrl = dw_pcie_readw_dbi(pci, reg);
has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
- reg = ep->msi_cap + func_offset + PCI_MSI_ADDRESS_LO;
+ reg = ep_func->msi_cap + func_offset + PCI_MSI_ADDRESS_LO;
msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
if (has_upper) {
- reg = ep->msi_cap + func_offset + PCI_MSI_ADDRESS_HI;
+ reg = ep_func->msi_cap + func_offset + PCI_MSI_ADDRESS_HI;
msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
- reg = ep->msi_cap + func_offset + PCI_MSI_DATA_64;
+ reg = ep_func->msi_cap + func_offset + PCI_MSI_DATA_64;
msg_data = dw_pcie_readw_dbi(pci, reg);
} else {
msg_addr_upper = 0;
- reg = ep->msi_cap + func_offset + PCI_MSI_DATA_32;
+ reg = ep_func->msi_cap + func_offset + PCI_MSI_DATA_32;
msg_data = dw_pcie_readw_dbi(pci, reg);
}
aligned_offset = msg_addr_lower & (epc->mem->page_size - 1);
@@ -467,6 +546,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct dw_pcie_ep_func *ep_func;
struct pci_epc *epc = ep->epc;
u16 tbl_offset, bir;
unsigned int func_offset = 0;
@@ -477,9 +557,16 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
void __iomem *msix_tbl;
int ret;
+ ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
+ if (!ep_func)
+ return -EINVAL;
+
+ if (!ep_func->msix_cap)
+ return -EINVAL;
+
func_offset = dw_pcie_ep_func_select(ep, func_no);
- reg = ep->msix_cap + func_offset + PCI_MSIX_TABLE;
+ reg = ep_func->msix_cap + func_offset + PCI_MSIX_TABLE;
tbl_offset = dw_pcie_readl_dbi(pci, reg);
bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
tbl_offset &= PCI_MSIX_TABLE_OFFSET;
@@ -558,6 +645,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
int i;
int ret;
u32 reg;
+ u8 func_no;
void *addr;
u8 hdr_type;
unsigned int nbars;
@@ -566,6 +654,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct device *dev = pci->dev;
struct device_node *np = dev->of_node;
+ struct dw_pcie_ep_func *ep_func;
+
+ INIT_LIST_HEAD(&ep->func_list);
if (!pci->dbi_base || !pci->dbi_base2) {
dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
@@ -632,9 +723,19 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
if (ret < 0)
epc->max_functions = 1;
- ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
+ for (func_no = 0; func_no < epc->max_functions; func_no++) {
+ ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
+ if (!ep_func)
+ return -ENOMEM;
- ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
+ ep_func->func_no = func_no;
+ ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSI);
+ ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSIX);
+
+ list_add_tail(&ep_func->list, &ep->func_list);
+ }
if (ep->ops->ep_init)
ep->ops->ep_init(ep);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index cb32afa..dd9b7b4 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -230,8 +230,16 @@ struct dw_pcie_ep_ops {
unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
};
+struct dw_pcie_ep_func {
+ struct list_head list;
+ u8 func_no;
+ u8 msi_cap; /* MSI capability offset */
+ u8 msix_cap; /* MSI-X capability offset */
+};
+
struct dw_pcie_ep {
struct pci_epc *epc;
+ struct list_head func_list;
const struct dw_pcie_ep_ops *ops;
phys_addr_t phys_base;
size_t addr_size;
@@ -244,8 +252,6 @@ struct dw_pcie_ep {
u32 num_ob_windows;
void __iomem *msi_mem;
phys_addr_t msi_mem_phys;
- u8 msi_cap; /* MSI capability offset */
- u8 msix_cap; /* MSI-X capability offset */
};
struct dw_pcie_ops {
@@ -437,6 +443,8 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
u16 interrupt_num);
void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
+struct dw_pcie_ep_func *
+dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no);
#else
static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
{
@@ -478,5 +486,11 @@ static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep,
static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
{
}
+
+static inline struct dw_pcie_ep_func *
+dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
+{
+ return NULL;
+}
#endif
#endif /* _PCIE_DESIGNWARE_H */
--
2.9.5
^ permalink raw reply related
* [PATCH v6 03/11] PCI: designware-ep: Move the function of getting MSI capability forward
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>
Move the function of getting MSI capability to the front of init
function, because the init function of the EP platform driver will use
the return value by the function of getting MSI capability.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
---
v2:
- No change.
v3:
- No change.
v4:
- No change.
v5:
- No change.
v6:
- No change.
drivers/pci/controller/dwc/pcie-designware-ep.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 44ece33..933bb89 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -632,6 +632,10 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
if (ret < 0)
epc->max_functions = 1;
+ ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
+
+ ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
+
if (ep->ops->ep_init)
ep->ops->ep_init(ep);
@@ -648,9 +652,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
return -ENOMEM;
}
- ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
-
- ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
if (offset) {
--
2.9.5
^ permalink raw reply related
* [PATCH v6 01/11] PCI: designware-ep: Add multiple PFs support for DWC
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>
Add multiple PFs support for DWC, due to different PF have different
config space, we use func_conf_select callback function to access
the different PF's config space, the different chip company need to
implement this callback function when use the DWC IP core and intend
to support multiple PFs feature.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
v2:
- Remove duplicate redundant code.
- Reimplement the PF config space access way.
v3:
- Integrate duplicate code for func_select.
- Move PCIE_ATU_FUNC_NUM(pf) (pf << 20) to ((pf) << 20).
- Add the comments for func_conf_select function.
v4:
- Correct the commit message.
v5:
- No change.
v6:
- No change.
drivers/pci/controller/dwc/pcie-designware-ep.c | 123 ++++++++++++++++--------
drivers/pci/controller/dwc/pcie-designware.c | 59 ++++++++----
drivers/pci/controller/dwc/pcie-designware.h | 18 +++-
3 files changed, 142 insertions(+), 58 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index cfeccd7..58d8556 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -19,12 +19,26 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
pci_epc_linkup(epc);
}
-static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
- int flags)
+static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
+{
+ unsigned int func_offset = 0;
+
+ if (ep->ops->func_conf_select)
+ func_offset = ep->ops->func_conf_select(ep, func_no);
+
+ return func_offset;
+}
+
+static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
+ enum pci_barno bar, int flags)
{
u32 reg;
+ unsigned int func_offset = 0;
+ struct dw_pcie_ep *ep = &pci->ep;
+
+ func_offset = dw_pcie_ep_func_select(ep, func_no);
- reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+ reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
dw_pcie_dbi_ro_wr_en(pci);
dw_pcie_writel_dbi2(pci, reg, 0x0);
dw_pcie_writel_dbi(pci, reg, 0x0);
@@ -37,7 +51,12 @@ static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
{
- __dw_pcie_ep_reset_bar(pci, bar, 0);
+ u8 func_no, funcs;
+
+ funcs = pci->ep.epc->max_functions;
+
+ for (func_no = 0; func_no < funcs; func_no++)
+ __dw_pcie_ep_reset_bar(pci, func_no, bar, 0);
}
static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
@@ -45,28 +64,31 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
{
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ unsigned int func_offset = 0;
+
+ func_offset = dw_pcie_ep_func_select(ep, func_no);
dw_pcie_dbi_ro_wr_en(pci);
- dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
- dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
- dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
- dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
- dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
+ dw_pcie_writew_dbi(pci, func_offset + PCI_VENDOR_ID, hdr->vendorid);
+ dw_pcie_writew_dbi(pci, func_offset + PCI_DEVICE_ID, hdr->deviceid);
+ dw_pcie_writeb_dbi(pci, func_offset + PCI_REVISION_ID, hdr->revid);
+ dw_pcie_writeb_dbi(pci, func_offset + PCI_CLASS_PROG, hdr->progif_code);
+ dw_pcie_writew_dbi(pci, func_offset + PCI_CLASS_DEVICE,
hdr->subclass_code | hdr->baseclass_code << 8);
- dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
+ dw_pcie_writeb_dbi(pci, func_offset + PCI_CACHE_LINE_SIZE,
hdr->cache_line_size);
- dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
+ dw_pcie_writew_dbi(pci, func_offset + PCI_SUBSYSTEM_VENDOR_ID,
hdr->subsys_vendor_id);
- dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
- dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
+ dw_pcie_writew_dbi(pci, func_offset + PCI_SUBSYSTEM_ID, hdr->subsys_id);
+ dw_pcie_writeb_dbi(pci, func_offset + PCI_INTERRUPT_PIN,
hdr->interrupt_pin);
dw_pcie_dbi_ro_wr_dis(pci);
return 0;
}
-static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
- dma_addr_t cpu_addr,
+static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no,
+ enum pci_barno bar, dma_addr_t cpu_addr,
enum dw_pcie_as_type as_type)
{
int ret;
@@ -79,7 +101,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
return -EINVAL;
}
- ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
+ ret = dw_pcie_prog_inbound_atu(pci, func_no, free_win, bar, cpu_addr,
as_type);
if (ret < 0) {
dev_err(pci->dev, "Failed to program IB window\n");
@@ -92,7 +114,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
return 0;
}
-static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
+static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
+ phys_addr_t phys_addr,
u64 pci_addr, size_t size)
{
u32 free_win;
@@ -104,8 +127,8 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
return -EINVAL;
}
- dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
- phys_addr, pci_addr, size);
+ dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM,
+ phys_addr, pci_addr, size);
set_bit(free_win, ep->ob_window_map);
ep->outbound_addr[free_win] = phys_addr;
@@ -121,7 +144,7 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
enum pci_barno bar = epf_bar->barno;
u32 atu_index = ep->bar_to_atu[bar];
- __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
+ __dw_pcie_ep_reset_bar(pci, func_no, bar, epf_bar->flags);
dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
clear_bit(atu_index, ep->ib_window_map);
@@ -137,14 +160,20 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
size_t size = epf_bar->size;
int flags = epf_bar->flags;
enum dw_pcie_as_type as_type;
- u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+ u32 reg;
+ unsigned int func_offset = 0;
+
+ func_offset = dw_pcie_ep_func_select(ep, func_no);
+
+ reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
if (!(flags & PCI_BASE_ADDRESS_SPACE))
as_type = DW_PCIE_AS_MEM;
else
as_type = DW_PCIE_AS_IO;
- ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type);
+ ret = dw_pcie_ep_inbound_atu(ep, func_no, bar,
+ epf_bar->phys_addr, as_type);
if (ret)
return ret;
@@ -202,7 +231,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
- ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
+ ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size);
if (ret) {
dev_err(pci->dev, "Failed to enable address\n");
return ret;
@@ -216,11 +245,14 @@ static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
u32 val, reg;
+ unsigned int func_offset = 0;
if (!ep->msi_cap)
return -EINVAL;
- reg = ep->msi_cap + PCI_MSI_FLAGS;
+ func_offset = dw_pcie_ep_func_select(ep, func_no);
+
+ reg = ep->msi_cap + func_offset + PCI_MSI_FLAGS;
val = dw_pcie_readw_dbi(pci, reg);
if (!(val & PCI_MSI_FLAGS_ENABLE))
return -EINVAL;
@@ -235,11 +267,14 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
u32 val, reg;
+ unsigned int func_offset = 0;
if (!ep->msi_cap)
return -EINVAL;
- reg = ep->msi_cap + PCI_MSI_FLAGS;
+ func_offset = dw_pcie_ep_func_select(ep, func_no);
+
+ reg = ep->msi_cap + func_offset + PCI_MSI_FLAGS;
val = dw_pcie_readw_dbi(pci, reg);
val &= ~PCI_MSI_FLAGS_QMASK;
val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
@@ -255,11 +290,14 @@ static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
u32 val, reg;
+ unsigned int func_offset = 0;
if (!ep->msix_cap)
return -EINVAL;
- reg = ep->msix_cap + PCI_MSIX_FLAGS;
+ func_offset = dw_pcie_ep_func_select(ep, func_no);
+
+ reg = ep->msix_cap + func_offset + PCI_MSIX_FLAGS;
val = dw_pcie_readw_dbi(pci, reg);
if (!(val & PCI_MSIX_FLAGS_ENABLE))
return -EINVAL;
@@ -274,11 +312,14 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
u32 val, reg;
+ unsigned int func_offset = 0;
if (!ep->msix_cap)
return -EINVAL;
- reg = ep->msix_cap + PCI_MSIX_FLAGS;
+ func_offset = dw_pcie_ep_func_select(ep, func_no);
+
+ reg = ep->msix_cap + func_offset + PCI_MSIX_FLAGS;
val = dw_pcie_readw_dbi(pci, reg);
val &= ~PCI_MSIX_FLAGS_QSIZE;
val |= interrupts;
@@ -365,6 +406,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct pci_epc *epc = ep->epc;
unsigned int aligned_offset;
+ unsigned int func_offset = 0;
u16 msg_ctrl, msg_data;
u32 msg_addr_lower, msg_addr_upper, reg;
u64 msg_addr;
@@ -374,20 +416,22 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
if (!ep->msi_cap)
return -EINVAL;
+ func_offset = dw_pcie_ep_func_select(ep, func_no);
+
/* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
- reg = ep->msi_cap + PCI_MSI_FLAGS;
+ reg = ep->msi_cap + func_offset + PCI_MSI_FLAGS;
msg_ctrl = dw_pcie_readw_dbi(pci, reg);
has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
- reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
+ reg = ep->msi_cap + func_offset + PCI_MSI_ADDRESS_LO;
msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
if (has_upper) {
- reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
+ reg = ep->msi_cap + func_offset + PCI_MSI_ADDRESS_HI;
msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
- reg = ep->msi_cap + PCI_MSI_DATA_64;
+ reg = ep->msi_cap + func_offset + PCI_MSI_DATA_64;
msg_data = dw_pcie_readw_dbi(pci, reg);
} else {
msg_addr_upper = 0;
- reg = ep->msi_cap + PCI_MSI_DATA_32;
+ reg = ep->msi_cap + func_offset + PCI_MSI_DATA_32;
msg_data = dw_pcie_readw_dbi(pci, reg);
}
aligned_offset = msg_addr_lower & (epc->mem->page_size - 1);
@@ -406,11 +450,12 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
}
int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
- u16 interrupt_num)
+ u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct pci_epc *epc = ep->epc;
u16 tbl_offset, bir;
+ unsigned int func_offset = 0;
u32 bar_addr_upper, bar_addr_lower;
u32 msg_addr_upper, msg_addr_lower;
u32 reg, msg_data, vec_ctrl;
@@ -418,12 +463,14 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
void __iomem *msix_tbl;
int ret;
- reg = ep->msix_cap + PCI_MSIX_TABLE;
+ func_offset = dw_pcie_ep_func_select(ep, func_no);
+
+ reg = ep->msix_cap + func_offset + PCI_MSIX_TABLE;
tbl_offset = dw_pcie_readl_dbi(pci, reg);
bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
tbl_offset &= PCI_MSIX_TABLE_OFFSET;
- reg = PCI_BASE_ADDRESS_0 + (4 * bir);
+ reg = PCI_BASE_ADDRESS_0 + func_offset + (4 * bir);
bar_addr_upper = 0;
bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
@@ -560,9 +607,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
ep->epc = epc;
epc_set_drvdata(epc, ep);
- if (ep->ops->ep_init)
- ep->ops->ep_init(ep);
-
hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
@@ -574,6 +618,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
if (ret < 0)
epc->max_functions = 1;
+ if (ep->ops->ep_init)
+ ep->ops->ep_init(ep);
+
ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
ep->page_size);
if (ret < 0) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 681548c..c5243cc 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -239,9 +239,10 @@ static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
dw_pcie_writel_atu(pci, offset + reg, val);
}
-static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
- int type, u64 cpu_addr,
- u64 pci_addr, u32 size)
+static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
+ int index, int type,
+ u64 cpu_addr, u64 pci_addr,
+ u32 size)
{
u32 retries, val;
@@ -256,7 +257,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
upper_32_bits(pci_addr));
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
- type);
+ type | PCIE_ATU_FUNC_NUM(func_no));
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
PCIE_ATU_ENABLE);
@@ -275,8 +276,9 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
dev_err(pci->dev, "Outbound iATU is not being enabled\n");
}
-void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
- u64 cpu_addr, u64 pci_addr, u32 size)
+static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
+ int index, int type, u64 cpu_addr,
+ u64 pci_addr, u32 size)
{
u32 retries, val;
@@ -284,8 +286,8 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
if (pci->iatu_unroll_enabled) {
- dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
- pci_addr, size);
+ dw_pcie_prog_outbound_atu_unroll(pci, func_no, index, type,
+ cpu_addr, pci_addr, size);
return;
}
@@ -301,7 +303,8 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
lower_32_bits(pci_addr));
dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
upper_32_bits(pci_addr));
- dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
+ dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
+ PCIE_ATU_FUNC_NUM(func_no));
dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
/*
@@ -318,6 +321,21 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
dev_err(pci->dev, "Outbound iATU is not being enabled\n");
}
+void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
+ u64 cpu_addr, u64 pci_addr, u32 size)
+{
+ __dw_pcie_prog_outbound_atu(pci, 0, index, type,
+ cpu_addr, pci_addr, size);
+}
+
+void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
+ int type, u64 cpu_addr, u64 pci_addr,
+ u32 size)
+{
+ __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
+ cpu_addr, pci_addr, size);
+}
+
static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
{
u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
@@ -333,8 +351,8 @@ static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
dw_pcie_writel_atu(pci, offset + reg, val);
}
-static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
- int bar, u64 cpu_addr,
+static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
+ int index, int bar, u64 cpu_addr,
enum dw_pcie_as_type as_type)
{
int type;
@@ -356,8 +374,10 @@ static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
return -EINVAL;
}
- dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
+ dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type |
+ PCIE_ATU_FUNC_NUM(func_no));
dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
+ PCIE_ATU_FUNC_NUM_MATCH_EN |
PCIE_ATU_ENABLE |
PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
@@ -378,14 +398,15 @@ static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
return -EBUSY;
}
-int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
- u64 cpu_addr, enum dw_pcie_as_type as_type)
+int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
+ int bar, u64 cpu_addr,
+ enum dw_pcie_as_type as_type)
{
int type;
u32 retries, val;
if (pci->iatu_unroll_enabled)
- return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
+ return dw_pcie_prog_inbound_atu_unroll(pci, func_no, index, bar,
cpu_addr, as_type);
dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
@@ -404,9 +425,11 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
return -EINVAL;
}
- dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
- dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
- | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
+ dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
+ PCIE_ATU_FUNC_NUM(func_no));
+ dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE |
+ PCIE_ATU_FUNC_NUM_MATCH_EN |
+ PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
/*
* Make sure ATU enable takes effect before any subsequent config
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index a22ea59..00d2d31 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -80,9 +80,11 @@
#define PCIE_ATU_TYPE_IO 0x2
#define PCIE_ATU_TYPE_CFG0 0x4
#define PCIE_ATU_TYPE_CFG1 0x5
+#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
#define PCIE_ATU_CR2 0x908
#define PCIE_ATU_ENABLE BIT(31)
#define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
+#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
#define PCIE_ATU_LOWER_BASE 0x90C
#define PCIE_ATU_UPPER_BASE 0x910
#define PCIE_ATU_LIMIT 0x914
@@ -215,6 +217,14 @@ struct dw_pcie_ep_ops {
int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
enum pci_epc_irq_type type, u16 interrupt_num);
const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
+ /*
+ * Provide a method to implement the different func config space
+ * access for different platform, if different func have different
+ * offset, return the offset of func. if use write a register way
+ * return a 0, and implement code in callback function of platform
+ * driver.
+ */
+ unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
};
struct dw_pcie_ep {
@@ -289,8 +299,12 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci);
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
int type, u64 cpu_addr, u64 pci_addr,
u32 size);
-int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
- u64 cpu_addr, enum dw_pcie_as_type as_type);
+void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
+ int type, u64 cpu_addr, u64 pci_addr,
+ u32 size);
+int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
+ int bar, u64 cpu_addr,
+ enum dw_pcie_as_type as_type);
void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
enum dw_pcie_region_type type);
void dw_pcie_setup(struct dw_pcie *pci);
--
2.9.5
^ permalink raw reply related
* [PATCH v6 02/11] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>
Add the doorbell mode of MSI-X in DWC EP driver.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
---
v2:
- Remove the macro of no used.
v3:
- No change.
v4:
- Modify the commit message.
v5:
- No change.
v6:
- No change.
drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++++++++++++++
drivers/pci/controller/dwc/pcie-designware.h | 12 ++++++++++++
2 files changed, 26 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 58d8556..44ece33 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -449,6 +449,20 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
+int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
+ u16 interrupt_num)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 msg_data;
+
+ msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) |
+ (interrupt_num - 1);
+
+ dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data);
+
+ return 0;
+}
+
int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
u16 interrupt_num)
{
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 00d2d31..cb32afa 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -97,6 +97,9 @@
#define PCIE_MISC_CONTROL_1_OFF 0x8BC
#define PCIE_DBI_RO_WR_EN BIT(0)
+#define PCIE_MSIX_DOORBELL 0x948
+#define PCIE_MSIX_DOORBELL_PF_SHIFT 24
+
#define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20
#define PCIE_PL_CHK_REG_CHK_REG_START BIT(0)
#define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1)
@@ -431,6 +434,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num);
int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
u16 interrupt_num);
+int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
+ u16 interrupt_num);
void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
#else
static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
@@ -463,6 +468,13 @@ static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
+static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep,
+ u8 func_no,
+ u16 interrupt_num)
+{
+ return 0;
+}
+
static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
{
}
--
2.9.5
^ permalink raw reply related
* [PATCH v6 00/11] Add the multiple PF support for DWC and Layerscape
From: Xiaowei Bao @ 2020-03-14 3:30 UTC (permalink / raw)
To: Zhiqiang.Hou, Minghuan.Lian, mingkai.hu, bhelgaas, robh+dt,
shawnguo, leoyang.li, kishon, lorenzo.pieralisi, roy.zang,
amurray, jingoohan1, gustavo.pimentel, andrew.murray, linux-pci,
devicetree, linux-kernel, linux-arm-kernel, linuxppc-dev
Cc: Xiaowei Bao
Add the PCIe EP multiple PF support for DWC and Layerscape, add
the doorbell MSIX function for DWC, use list to manage the PF of
one PCIe controller, and refactor the Layerscape EP driver due to
some platforms difference.
Xiaowei Bao (11):
PCI: designware-ep: Add multiple PFs support for DWC
PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode
PCI: designware-ep: Move the function of getting MSI capability
forward
PCI: designware-ep: Modify MSI and MSIX CAP way of finding
dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a
and ls2088a
PCI: layerscape: Fix some format issue of the code
PCI: layerscape: Modify the way of getting capability with different
PEX
PCI: layerscape: Modify the MSIX to the doorbell mode
PCI: layerscape: Add EP mode support for ls1088a and ls2088a
arm64: dts: layerscape: Add PCIe EP node for ls1088a
misc: pci_endpoint_test: Add LS1088a in pci_device_id table
.../devicetree/bindings/pci/layerscape-pci.txt | 2 +
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++
drivers/misc/pci_endpoint_test.c | 2 +
drivers/pci/controller/dwc/pci-layerscape-ep.c | 100 ++++++--
drivers/pci/controller/dwc/pcie-designware-ep.c | 255 +++++++++++++++++----
drivers/pci/controller/dwc/pcie-designware.c | 59 +++--
drivers/pci/controller/dwc/pcie-designware.h | 48 +++-
7 files changed, 404 insertions(+), 93 deletions(-)
--
2.9.5
^ permalink raw reply
* Re: [PATCH v3] powerpc: setup_64: set up PACA earlier to avoid kcov problems
From: Nicholas Piggin @ 2020-03-14 3:37 UTC (permalink / raw)
To: Daniel Axtens, linuxppc-dev, Michael Ellerman; +Cc: ajd
In-Reply-To: <87lfo7q0cb.fsf@dja-thinkpad.axtens.net>
Daniel Axtens's on March 11, 2020 9:03 am:
>>>> So:
>>>> - change the test when setting up a PACA to consider the actual value of
>>>> the MSR rather than the CPU feature.
>>>>
>>>> - move the PACA setup to before the cpu feature parsing.
>>>
>>> Hmm. Problem is that equally we want PACA to be sane before we call too
>>> far into the rest of the kernel ("generic dt parsing code").
>>
>> But currently we call into that code with no paca at all. Or rather,
>> with r13 pointing somewhere random that will be interpreted as being a
>> paca.
>>
>> This took a while for Daniel to debug because depending on how you boot
>> r13 contains a different junk value. That junk value may not point to
>> memory at all, or if it does the memory it points to may or may not send
>> you down the wrong path, depending on which exact bit you're looking at
>> in some random location.
>>
>> So this is really not about kcov from my POV, that's just how we
>> discovered it.
>
> Ah, yes. I agree with mpe, and reading back over my commit message I
> think I did a pretty poor job of explaining it. How about this for a
> commit message:
Sorry yeah I'm not quite sure what I was thinking there, because
you actually are moving the paca setup earlier. Hmm. Anyway it seems
okay to me. I would suggest putting a comment in the mfmsr() & MSR_HV
test so it doesn't get used elsewhere. Maybe include CPU_FTR_HVMODE
in the comment so grep shows it up.
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v2] powerpc/fsl-85xx: fix compile error
From: Christophe Leroy @ 2020-03-13 19:24 UTC (permalink / raw)
To: 王文虎
Cc: Kate Stewart, trivial, kernel, linux-kernel, Richard Fontana,
Paul Mackerras, Thomas Gleixner, linuxppc-dev, Allison Randal
In-Reply-To: <AIkAvQC8CBiKb1HKth-6ZqrH.3.1584123458318.Hmail.wenhu.wang@vivo.com>
Le 13/03/2020 à 19:17, 王文虎 a écrit :
> 发件人：Christophe Leroy <christophe.leroy@c-s.fr>
> 发送日期：2020-03-14 01:45:11
> 收件人：WANG Wenhu <wenhu.wang@vivo.com>,Benjamin Herrenschmidt <benh@kernel.crashing.org>,Paul Mackerras <paulus@samba.org>,Michael Ellerman <mpe@ellerman.id.au>,Richard Fontana <rfontana@redhat.com>,Kate Stewart <kstewart@linuxfoundation.org>,Allison Randal <allison@lohutok.net>,Thomas Gleixner <tglx@linutronix.de>,linuxppc-dev@lists.ozlabs.org,linux-kernel@vger.kernel.org
> 抄送人：kernel@vivo.com,trivial@kernel.org
> 主题：Re: [PATCH v2] powerpc/fsl-85xx: fix compile error>
>>
>> Le 13/03/2020 à 18:19, WANG Wenhu a écrit :
>>> Include "linux/of_address.h" to fix the compile error for
>>> mpc85xx_l2ctlr_of_probe() when compiling fsl_85xx_cache_sram.c.
>>>
>>> CC arch/powerpc/sysdev/fsl_85xx_l2ctlr.o
>>> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c: In function ‘mpc85xx_l2ctlr_of_probe’:
>>> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:90:11: error: implicit declaration of function ‘of_iomap’; did you mean ‘pci_iomap’? [-Werror=implicit-function-declaration]
>>> l2ctlr = of_iomap(dev->dev.of_node, 0);
>>> ^~~~~~~~
>>> pci_iomap
>>> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:90:9: error: assignment makes pointer from integer without a cast [-Werror=int-conversion]
>>> l2ctlr = of_iomap(dev->dev.of_node, 0);
>>> ^
>>> cc1: all warnings being treated as errors
>>> scripts/Makefile.build:267: recipe for target 'arch/powerpc/sysdev/fsl_85xx_l2ctlr.o' failed
>>> make[2]: *** [arch/powerpc/sysdev/fsl_85xx_l2ctlr.o] Error 1
>>>
>>> Fixes: commit 6db92cc9d07d ("powerpc/85xx: add cache-sram support")
>>
>> Shouldn't you Cc stable as well ?
> Pretty sure if it makes a difference(that I did not recognize).
> Does the inconsistency of Cc lead to a failure on classification
> or something else which may confuse you?
See
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/Documentation/process/submitting-patches.rst?h=v5.1.9#n299
>>
>>> Signed-off-by: WANG Wenhu <wenhu.wang@vivo.com>
>>> ---
>>
>> What's the difference between v1 and v2 ?
> The label field modification: "Fixed" -> "Fixes", which now is
> identified successfully. Really sorry for the fault on v1.
Ok. Usually people tell here (just below the ---) what is the difference
between the different versions. It helps people understand what the
changes are.
Christophe
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