* Re: [PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines
From: Michal Suchánek @ 2020-06-29 16:09 UTC (permalink / raw)
To: Aneesh Kumar K.V
Cc: Jan Kara, linux-nvdimm, Jeff Moyer, oohall, dan.j.williams,
linuxppc-dev
In-Reply-To: <20200629135722.73558-7-aneesh.kumar@linux.ibm.com>
Hello,
On Mon, Jun 29, 2020 at 07:27:20PM +0530, Aneesh Kumar K.V wrote:
> nvdimm expect the flush routines to just mark the cache clean. The barrier
> that mark the store globally visible is done in nvdimm_flush().
>
> Update the papr_scm driver to a simplified nvdim_flush callback that do
> only the required barrier.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> ---
> arch/powerpc/lib/pmem.c | 6 ------
> arch/powerpc/platforms/pseries/papr_scm.c | 13 +++++++++++++
> 2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/arch/powerpc/lib/pmem.c b/arch/powerpc/lib/pmem.c
> index 5a61aaeb6930..21210fa676e5 100644
> --- a/arch/powerpc/lib/pmem.c
> +++ b/arch/powerpc/lib/pmem.c
> @@ -19,9 +19,6 @@ static inline void __clean_pmem_range(unsigned long start, unsigned long stop)
>
> for (i = 0; i < size >> shift; i++, addr += bytes)
> asm volatile(PPC_DCBSTPS(%0, %1): :"i"(0), "r"(addr): "memory");
> -
> -
> - asm volatile(PPC_PHWSYNC ::: "memory");
> }
>
> static inline void __flush_pmem_range(unsigned long start, unsigned long stop)
> @@ -34,9 +31,6 @@ static inline void __flush_pmem_range(unsigned long start, unsigned long stop)
>
> for (i = 0; i < size >> shift; i++, addr += bytes)
> asm volatile(PPC_DCBFPS(%0, %1): :"i"(0), "r"(addr): "memory");
> -
> -
> - asm volatile(PPC_PHWSYNC ::: "memory");
> }
>
> static inline void clean_pmem_range(unsigned long start, unsigned long stop)
> diff --git a/arch/powerpc/platforms/pseries/papr_scm.c b/arch/powerpc/platforms/pseries/papr_scm.c
> index 9c569078a09f..9a9a0766f8b6 100644
> --- a/arch/powerpc/platforms/pseries/papr_scm.c
> +++ b/arch/powerpc/platforms/pseries/papr_scm.c
> @@ -630,6 +630,18 @@ static int papr_scm_ndctl(struct nvdimm_bus_descriptor *nd_desc,
>
> return 0;
> }
> +/*
> + * We have made sure the pmem writes are done such that before calling this
> + * all the caches are flushed/clean. We use dcbf/dcbfps to ensure this. Here
> + * we just need to add the necessary barrier to make sure the above flushes
> + * are have updated persistent storage before any data access or data transfer
> + * caused by subsequent instructions is initiated.
> + */
> +static int papr_scm_flush_sync(struct nd_region *nd_region, struct bio *bio)
> +{
> + arch_pmem_flush_barrier();
> + return 0;
> +}
>
> static ssize_t flags_show(struct device *dev,
> struct device_attribute *attr, char *buf)
> @@ -743,6 +755,7 @@ static int papr_scm_nvdimm_init(struct papr_scm_priv *p)
> ndr_desc.mapping = &mapping;
> ndr_desc.num_mappings = 1;
> ndr_desc.nd_set = &p->nd_set;
> + ndr_desc.flush = papr_scm_flush_sync;
AFAICT currently the only device that implements flush is virtio_pmem.
How does the nfit driver get away without implementing flush?
Also the flush takes arguments that are completely unused but a user of
the pmem region must assume they are used, and call flush() on the
region rather than arch_pmem_flush_barrier() directly. This may not
work well with md as discussed with earlier iteration of the patchest.
Thanks
Michal
^ permalink raw reply
* Re: [PATCH 4/8] asm-generic: pgalloc: provide generic pmd_alloc_one() and pmd_free_one()
From: Mike Rapoport @ 2020-06-29 15:59 UTC (permalink / raw)
To: Matthew Wilcox
Cc: linux-ia64, linux-sh, Peter Zijlstra, linux-mips, Max Filippov,
Satheesh Rajendran, linux-csky, sparclinux, linux-riscv,
linux-arch, Stephen Rothwell, linux-hexagon, Joerg Roedel,
Mike Rapoport, Abdul Haleem, linux-snps-arc, linux-xtensa,
Arnd Bergmann, linux-s390, linux-um, Steven Rostedt, linux-m68k,
openrisc, Andy Lutomirski, Stafford Horne, linux-arm-kernel,
linux-parisc, linux-mm, linux-kernel, linux-alpha, Andrew Morton,
linuxppc-dev
In-Reply-To: <20200627190304.GG25039@casper.infradead.org>
On Sat, Jun 27, 2020 at 08:03:04PM +0100, Matthew Wilcox wrote:
> On Sat, Jun 27, 2020 at 05:34:49PM +0300, Mike Rapoport wrote:
> > More elaborate versions on arm64 and x86 account memory for the user page
> > tables and call to pgtable_pmd_page_ctor() as the part of PMD page
> > initialization.
> >
> > Move the arm64 version to include/asm-generic/pgalloc.h and use the generic
> > version on several architectures.
> >
> > The pgtable_pmd_page_ctor() is a NOP when ARCH_ENABLE_SPLIT_PMD_PTLOCK is
> > not enabled, so there is no functional change for most architectures except
> > of the addition of __GFP_ACCOUNT for allocation of user page tables.
>
> Thanks for including this line; it reminded me that we're not setting
> the PageTable flag on the page, nor accounting it to the zone page stats.
> Hope you don't mind me tagging a patch to do that on as 9/8.
We also never set PageTable flag for early page tables and for the page
tables allocated directly with get_free_page(), e.g PTI, KASAN.
> We could also do with a pud_page_[cd]tor and maybe even p4d/pgd versions.
> But that brings me to the next question -- could/should some of this
> be moved over to asm-generic/pgalloc.h? The ctor/dtor aren't called
> from anywhere else, and there's value to reducing the total amount of
> code in mm.h, but then there's also value to keeping all the ifdef
> ARCH_ENABLE_SPLIT_PMD_PTLOCK code together too. So I'm a bit torn.
> What do you think?
--
Sincerely yours,
Mike.
^ permalink raw reply
* Re: [PATCH 6/8] asm-generic: pgalloc: provide generic pgd_free()
From: Geert Uytterhoeven @ 2020-06-29 15:42 UTC (permalink / raw)
To: Mike Rapoport
Cc: linux-ia64@vger.kernel.org, Linux-sh list, Peter Zijlstra,
open list:BROADCOM NVRAM DRIVER, Max Filippov, Satheesh Rajendran,
linux-csky, sparclinux, linux-riscv, Linux-Arch, Stephen Rothwell,
open list:QUALCOMM HEXAGON..., Joerg Roedel, Mike Rapoport,
Abdul Haleem, arcml, open list:TENSILICA XTENSA PORT (xtensa),
Arnd Bergmann, linux-s390, linux-um, Steven Rostedt, linux-m68k,
Openrisc, Andy Lutomirski, Stafford Horne, Linux ARM, Parisc List,
Linux MM, Linux Kernel Mailing List, alpha, Andrew Morton,
linuxppc-dev
In-Reply-To: <20200627143453.31835-7-rppt@kernel.org>
On Sat, Jun 27, 2020 at 4:36 PM Mike Rapoport <rppt@kernel.org> wrote:
> From: Mike Rapoport <rppt@linux.ibm.com>
>
> Most architectures define pgd_free() as a wrapper for free_page().
>
> Provide a generic version in asm-generic/pgalloc.h and enable its use for
> most architectures.
>
> Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
For the m68k part:
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 1/8] mm: remove unneeded includes of <asm/pgalloc.h>
From: Geert Uytterhoeven @ 2020-06-29 15:41 UTC (permalink / raw)
To: Mike Rapoport
Cc: linux-ia64@vger.kernel.org, Linux-sh list, Peter Zijlstra,
open list:BROADCOM NVRAM DRIVER, Max Filippov, Satheesh Rajendran,
linux-csky, sparclinux, linux-riscv, Linux-Arch, Stephen Rothwell,
open list:QUALCOMM HEXAGON..., Joerg Roedel, Mike Rapoport,
Abdul Haleem, arcml, open list:TENSILICA XTENSA PORT (xtensa),
Arnd Bergmann, linux-s390, linux-um, Steven Rostedt, linux-m68k,
Openrisc, Andy Lutomirski, Stafford Horne, Linux ARM, Parisc List,
Linux MM, Linux Kernel Mailing List, alpha, Andrew Morton,
linuxppc-dev
In-Reply-To: <20200627143453.31835-2-rppt@kernel.org>
On Sat, Jun 27, 2020 at 4:35 PM Mike Rapoport <rppt@kernel.org> wrote:
> From: Mike Rapoport <rppt@linux.ibm.com>
>
> In the most cases <asm/pgalloc.h> header is required only for allocations
> of page table memory. Most of the .c files that include that header do not
> use symbols declared in <asm/pgalloc.h> and do not require that header.
>
> As for the other header files that used to include <asm/pgalloc.h>, it is
> possible to move that include into the .c file that actually uses symbols
> from <asm/pgalloc.h> and drop the include from the header file.
>
> The process was somewhat automated using
>
> sed -i -E '/[<"]asm\/pgalloc\.h/d' \
> $(grep -L -w -f /tmp/xx \
> $(git grep -E -l '[<"]asm/pgalloc\.h'))
>
> where /tmp/xx contains all the symbols defined in
> arch/*/include/asm/pgalloc.h.
>
> Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
For the m68k part:
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v5 3/3] mm/page_alloc: Keep memoryless cpuless node 0 offline
From: Christopher Lameter @ 2020-06-29 14:58 UTC (permalink / raw)
To: Srikar Dronamraju
Cc: Gautham R Shenoy, Michal Hocko, David Hildenbrand, Linus Torvalds,
linux-kernel, linux-mm, Satheesh Rajendran, Mel Gorman,
Kirill A. Shutemov, Andrew Morton, linuxppc-dev, Vlastimil Babka
In-Reply-To: <20200624092846.9194-4-srikar@linux.vnet.ibm.com>
On Wed, 24 Jun 2020, Srikar Dronamraju wrote:
> Currently Linux kernel with CONFIG_NUMA on a system with multiple
> possible nodes, marks node 0 as online at boot. However in practice,
> there are systems which have node 0 as memoryless and cpuless.
Maybe add something to explain why you are not simply mapping the
existing memory to NUMA node 0 which is after all just a numbering scheme
used by the kernel and can be used arbitrarily?
This could be seen more as a bug in the arch code during the setup of NUMA
nodes. The two nodes are created by the firmwware / bootstrap code after
all. Just do not do it?
^ permalink raw reply
* [Bug 208181] BUG: KASAN: stack-out-of-bounds in strcmp+0x58/0xd8
From: bugzilla-daemon @ 2020-06-29 14:55 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <bug-208181-206035@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=208181
--- Comment #5 from Christophe Leroy (christophe.leroy@csgroup.eu) ---
Can we get a dump of /sys/kernel/debug/powerpc/block_address_translation
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* [Bug 208181] BUG: KASAN: stack-out-of-bounds in strcmp+0x58/0xd8
From: bugzilla-daemon @ 2020-06-29 14:42 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <bug-208181-206035@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=208181
--- Comment #4 from Erhard F. (erhard_f@mailbox.org) ---
Erm wait... there is some change.
In 5.8-rc1 stacktrace was:
BUG: KASAN: stack-out-of-bounds in strcmp+0x58/0xd8
Read of size 1 at addr c11c1a80 by task swapper/0
CPU: 0 PID: 0 Comm: swapper Not tainted 5.8.0-rc1-PowerMacG4 #2
Call Trace:
[c1ae97d0] [c0a2069c] dump_stack+0xfc/0x158 (unreliable)
[c1ae9800] [c04ac5cc] print_address_description.isra.0+0x30/0x3fc
[c1ae9870] [c04acb28] kasan_report+0x110/0x170
[c1ae98b0] [c0a44c00] strcmp+0x58/0xd8
[c1ae98d0] [c0170790] register_lock_class+0xfa4/0x10a0
[c1ae9990] [c0170a34] __lock_acquire+0x1a8/0x382c
[c1ae9b40] [c016f398] lock_acquire+0x5e0/0x854
[c1ae9c00] [c1144014] _raw_spin_lock_irqsave+0x48/0x70
[c1ae9c20] [c0ccbe84] of_find_property+0x2c/0x5c
[c1ae9c50] [c0ccbec8] of_get_property+0x14/0x6c
[c1ae9c70] [c0cdbcd8] unflatten_dt_nodes+0xc4c/0xcdc
[c1ae9ec0] [c0cdbe90] __unflatten_device_tree+0x114/0x1e0
[c1ae9ef0] [c184a294] unflatten_device_tree+0x38/0x54
[c1ae9f10] [c1808600] setup_arch+0xc8/0x630
[c1ae9f50] [c1803268] start_kernel+0xcc/0x4cc
[c1ae9ff0] [000038a0] 0x38a0
In 5.8-rc3 stacktrace is:
BUG: KASAN: stack-out-of-bounds in vprintk_func+0x100/0x4b4
Read of size 4 at addr c1919e14 by task swapper/0
CPU: 0 PID: 0 Comm: swapper Not tainted 5.8.0-rc3-PowerMacG4 #2
Call Trace:
[c1ae9c00] [c0a304dc] dump_stack+0xfc/0x158 (unreliable)
[c1ae9c30] [c04ac990] print_address_description.isra.0+0x30/0x3fc
[c1ae9ca0] [c04aceec] kasan_report+0x110/0x170
[c1ae9ce0] [c018c204] vprintk_func+0x100/0x4b4
[c1ae9d10] [c018afd4] printk+0xa8/0xd4
[c1ae9db0] [c003c8c4] __ioremap_caller+0x1c4/0x27c
[c1ae9df0] [c003c394] ioremap+0x20/0x30
[c1ae9e00] [c1813fe4] pmac_feature_init+0x288/0xd90
[c1ae9ed0] [c1812cb0] pmac_probe+0x13c/0x190
[c1ae9ef0] [c001d938] probe_machine+0xe8/0x13c
[c1ae9f10] [c1808614] setup_arch+0xdc/0x630
[c1ae9f50] [c1803268] start_kernel+0xcc/0x4cc
[c1ae9ff0] [000038a0] 0x38a0
What stays the same are the two "setbat: no BAT available" messages in both
cases.
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* [Bug 208181] BUG: KASAN: stack-out-of-bounds in strcmp+0x58/0xd8
From: bugzilla-daemon @ 2020-06-29 14:32 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <bug-208181-206035@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=208181
Erhard F. (erhard_f@mailbox.org) changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #289661|0 |1
is obsolete| |
--- Comment #3 from Erhard F. (erhard_f@mailbox.org) ---
Created attachment 289937
--> https://bugzilla.kernel.org/attachment.cgi?id=289937&action=edit
kernel .config (5.8-rc3, PowerMac G4 DP)
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* [Bug 208181] BUG: KASAN: stack-out-of-bounds in strcmp+0x58/0xd8
From: bugzilla-daemon @ 2020-06-29 14:31 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <bug-208181-206035@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=208181
Erhard F. (erhard_f@mailbox.org) changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #289659|0 |1
is obsolete| |
--- Comment #2 from Erhard F. (erhard_f@mailbox.org) ---
Created attachment 289935
--> https://bugzilla.kernel.org/attachment.cgi?id=289935&action=edit
dmesg (5.8-rc3, INLINE KASAN, PowerMac G4 DP
No change with 5.8-rc3.
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* [PATCH] ASoC: fsl_asrc: Add an option to select internal ratio mode
From: Shengjiu Wang @ 2020-06-29 13:58 UTC (permalink / raw)
To: timur, nicoleotsuka, Xiubo.Lee, festevam, broonie, alsa-devel,
lgirdwood, perex, tiwai
Cc: linuxppc-dev, linux-kernel
The ASRC not only supports ideal ratio mode, but also supports
internal ratio mode.
For internal rato mode, the rate of clock source should be divided
with no remainder by sample rate, otherwise there is sound
distortion.
Add function fsl_asrc_select_clk() to find proper clock source for
internal ratio mode, if the clock source is available then internal
ratio mode will be selected.
With change, the ideal ratio mode is not the only option for user.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
sound/soc/fsl/fsl_asrc.c | 58 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 56 insertions(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c
index 95f6a9617b0b..fcafc8ecb131 100644
--- a/sound/soc/fsl/fsl_asrc.c
+++ b/sound/soc/fsl/fsl_asrc.c
@@ -582,11 +582,59 @@ static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream,
SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints);
}
+/**
+ * Select proper clock source for internal ratio mode
+ */
+static int fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv,
+ struct fsl_asrc_pair *pair,
+ int in_rate,
+ int out_rate)
+{
+ struct fsl_asrc_pair_priv *pair_priv = pair->private;
+ struct asrc_config *config = pair_priv->config;
+ int rate[2], select_clk[2]; /* Array size 2 means IN and OUT */
+ int clk_rate, clk_index;
+ int i = 0, j = 0;
+ bool clk_sel[2];
+
+ rate[0] = in_rate;
+ rate[1] = out_rate;
+
+ /* Select proper clock source for internal ratio mode */
+ for (j = 0; j < 2; j++) {
+ for (i = 0; i < ASRC_CLK_MAP_LEN; i++) {
+ clk_index = asrc_priv->clk_map[j][i];
+ clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index]);
+ if (clk_rate != 0 && (clk_rate / rate[j]) <= 1024 &&
+ (clk_rate % rate[j]) == 0)
+ break;
+ }
+
+ if (i == ASRC_CLK_MAP_LEN) {
+ select_clk[j] = OUTCLK_ASRCK1_CLK;
+ clk_sel[j] = false;
+ } else {
+ select_clk[j] = i;
+ clk_sel[j] = true;
+ }
+ }
+
+ /* Switch to ideal ratio mode if there is no proper clock source */
+ if (!clk_sel[IN] || !clk_sel[OUT])
+ select_clk[IN] = INCLK_NONE;
+
+ config->inclk = select_clk[IN];
+ config->outclk = select_clk[OUT];
+
+ return 0;
+}
+
static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
+ struct fsl_asrc_priv *asrc_priv = asrc->private;
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *pair = runtime->private_data;
struct fsl_asrc_pair_priv *pair_priv = pair->private;
@@ -605,8 +653,6 @@ static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
config.pair = pair->index;
config.channel_num = channels;
- config.inclk = INCLK_NONE;
- config.outclk = OUTCLK_ASRCK1_CLK;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
config.input_format = params_format(params);
@@ -620,6 +666,14 @@ static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
config.output_sample_rate = rate;
}
+ ret = fsl_asrc_select_clk(asrc_priv, pair,
+ config.input_sample_rate,
+ config.output_sample_rate);
+ if (ret) {
+ dev_err(dai->dev, "fail to select clock\n");
+ return ret;
+ }
+
ret = fsl_asrc_config_pair(pair, false);
if (ret) {
dev_err(dai->dev, "fail to config asrc pair\n");
--
2.21.0
^ permalink raw reply related
* [PATCH v6 0/8] Support new pmem flush and sync instructions for POWER
From: Aneesh Kumar K.V @ 2020-06-29 13:57 UTC (permalink / raw)
To: linuxppc-dev, mpe, linux-nvdimm, dan.j.williams
Cc: Jan Kara, Jeff Moyer, msuchanek, oohall, Aneesh Kumar K.V
This patch series enables the usage os new pmem flush and sync instructions on POWER
architecture. POWER10 introduces two new variants of dcbf instructions (dcbstps and dcbfps)
that can be used to write modified locations back to persistent storage. Additionally,
POWER10 also introduce phwsync and plwsync which can be used to establish order of these
writes to persistent storage.
This series exposes these instructions to the rest of the kernel. The existing
dcbf and hwsync instructions in P8 and P9 are adequate to enable appropriate
synchronization with OpenCAPI-hosted persistent storage. Hence the new instructions
are added as a variant of the old ones that old hardware won't differentiate.
On POWER10, pmem devices will be represented by a different device tree compat
strings. This ensures that older kernels won't initialize pmem devices on POWER10.
With this:
1) vPMEM continues to work since it is a volatile region. That
doesn't need any flush instructions.
2) pmdk and other user applications get updated to use new instructions
and updated packages are made available to all distributions
3) On newer hardware, the device will appear with a new compat string.
Hence older distributions won't initialize pmem on newer hardware.
Changes from v5:
* Drop CONFIG_ARCH_MAP_SYNC_DISABLE and related changes
Changes from V4:
* Add namespace specific sychronous fault control.
Changes from V3:
* Add new compat string to be used for the device.
* Use arch_pmem_flush_barrier() in dm-writecache.
Aneesh Kumar K.V (8):
powerpc/pmem: Restrict papr_scm to P8 and above.
powerpc/pmem: Add new instructions for persistent storage and sync
powerpc/pmem: Add flush routines using new pmem store and sync
instruction
libnvdimm/nvdimm/flush: Allow architecture to override the flush
barrier
powerpc/pmem/of_pmem: Update of_pmem to use the new barrier
instruction.
powerpc/pmem: Avoid the barrier in flush routines
powerpc/pmem: Add WARN_ONCE to catch the wrong usage of pmem flush
functions.
powerpc/pmem: Initialize pmem device on newer hardware
arch/powerpc/include/asm/cacheflush.h | 10 +++++
arch/powerpc/include/asm/ppc-opcode.h | 12 ++++++
arch/powerpc/lib/pmem.c | 46 +++++++++++++++++++++--
arch/powerpc/platforms/pseries/papr_scm.c | 14 +++++++
arch/powerpc/platforms/pseries/pmem.c | 6 +++
drivers/md/dm-writecache.c | 2 +-
drivers/nvdimm/of_pmem.c | 1 +
drivers/nvdimm/region_devs.c | 8 ++--
include/asm-generic/cacheflush.h | 4 ++
9 files changed, 94 insertions(+), 9 deletions(-)
--
2.26.2
^ permalink raw reply
* [PATCH v6 8/8] powerpc/pmem: Initialize pmem device on newer hardware
From: Aneesh Kumar K.V @ 2020-06-29 13:57 UTC (permalink / raw)
To: linuxppc-dev, mpe, linux-nvdimm, dan.j.williams
Cc: Jan Kara, Jeff Moyer, msuchanek, oohall, Aneesh Kumar K.V
In-Reply-To: <20200629135722.73558-1-aneesh.kumar@linux.ibm.com>
With kernel now supporting new pmem flush/sync instructions, we can now
enable the kernel to initialize the device. On P10 these devices would
appear with a new compatible string. For PAPR device we have
compatible "ibm,pmemory-v2"
and for OF pmem device we have
compatible "pmem-region-v2"
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/platforms/pseries/papr_scm.c | 1 +
drivers/nvdimm/of_pmem.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c b/arch/powerpc/platforms/pseries/papr_scm.c
index 9a9a0766f8b6..617dfa4d7ec1 100644
--- a/arch/powerpc/platforms/pseries/papr_scm.c
+++ b/arch/powerpc/platforms/pseries/papr_scm.c
@@ -889,6 +889,7 @@ static int papr_scm_remove(struct platform_device *pdev)
static const struct of_device_id papr_scm_match[] = {
{ .compatible = "ibm,pmemory" },
+ { .compatible = "ibm,pmemory-v2" },
{ },
};
diff --git a/drivers/nvdimm/of_pmem.c b/drivers/nvdimm/of_pmem.c
index 6826a274a1f1..10dbdcdfb9ce 100644
--- a/drivers/nvdimm/of_pmem.c
+++ b/drivers/nvdimm/of_pmem.c
@@ -90,6 +90,7 @@ static int of_pmem_region_remove(struct platform_device *pdev)
static const struct of_device_id of_pmem_region_match[] = {
{ .compatible = "pmem-region" },
+ { .compatible = "pmem-region-v2" },
{ },
};
--
2.26.2
^ permalink raw reply related
* [PATCH v6 7/8] powerpc/pmem: Add WARN_ONCE to catch the wrong usage of pmem flush functions.
From: Aneesh Kumar K.V @ 2020-06-29 13:57 UTC (permalink / raw)
To: linuxppc-dev, mpe, linux-nvdimm, dan.j.williams
Cc: Jan Kara, Jeff Moyer, msuchanek, oohall, Aneesh Kumar K.V
In-Reply-To: <20200629135722.73558-1-aneesh.kumar@linux.ibm.com>
We only support persistent memory on P8 and above. This is enforced by the
firmware and further checked on virtualzied platform during platform init.
Add WARN_ONCE in pmem flush routines to catch the wrong usage of these.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/include/asm/cacheflush.h | 2 ++
arch/powerpc/lib/pmem.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index 95782f77d768..1ab0fa660497 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -103,6 +103,8 @@ static inline void arch_pmem_flush_barrier(void)
{
if (cpu_has_feature(CPU_FTR_ARCH_207S))
asm volatile(PPC_PHWSYNC ::: "memory");
+ else
+ WARN_ONCE(1, "Using pmem flush on older hardware.");
}
#include <asm-generic/cacheflush.h>
diff --git a/arch/powerpc/lib/pmem.c b/arch/powerpc/lib/pmem.c
index 21210fa676e5..f40bd908d28d 100644
--- a/arch/powerpc/lib/pmem.c
+++ b/arch/powerpc/lib/pmem.c
@@ -37,12 +37,14 @@ static inline void clean_pmem_range(unsigned long start, unsigned long stop)
{
if (cpu_has_feature(CPU_FTR_ARCH_207S))
return __clean_pmem_range(start, stop);
+ WARN_ONCE(1, "Using pmem flush on older hardware.");
}
static inline void flush_pmem_range(unsigned long start, unsigned long stop)
{
if (cpu_has_feature(CPU_FTR_ARCH_207S))
return __flush_pmem_range(start, stop);
+ WARN_ONCE(1, "Using pmem flush on older hardware.");
}
/*
--
2.26.2
^ permalink raw reply related
* [PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines
From: Aneesh Kumar K.V @ 2020-06-29 13:57 UTC (permalink / raw)
To: linuxppc-dev, mpe, linux-nvdimm, dan.j.williams
Cc: Jan Kara, Jeff Moyer, msuchanek, oohall, Aneesh Kumar K.V
In-Reply-To: <20200629135722.73558-1-aneesh.kumar@linux.ibm.com>
nvdimm expect the flush routines to just mark the cache clean. The barrier
that mark the store globally visible is done in nvdimm_flush().
Update the papr_scm driver to a simplified nvdim_flush callback that do
only the required barrier.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/lib/pmem.c | 6 ------
arch/powerpc/platforms/pseries/papr_scm.c | 13 +++++++++++++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/lib/pmem.c b/arch/powerpc/lib/pmem.c
index 5a61aaeb6930..21210fa676e5 100644
--- a/arch/powerpc/lib/pmem.c
+++ b/arch/powerpc/lib/pmem.c
@@ -19,9 +19,6 @@ static inline void __clean_pmem_range(unsigned long start, unsigned long stop)
for (i = 0; i < size >> shift; i++, addr += bytes)
asm volatile(PPC_DCBSTPS(%0, %1): :"i"(0), "r"(addr): "memory");
-
-
- asm volatile(PPC_PHWSYNC ::: "memory");
}
static inline void __flush_pmem_range(unsigned long start, unsigned long stop)
@@ -34,9 +31,6 @@ static inline void __flush_pmem_range(unsigned long start, unsigned long stop)
for (i = 0; i < size >> shift; i++, addr += bytes)
asm volatile(PPC_DCBFPS(%0, %1): :"i"(0), "r"(addr): "memory");
-
-
- asm volatile(PPC_PHWSYNC ::: "memory");
}
static inline void clean_pmem_range(unsigned long start, unsigned long stop)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c b/arch/powerpc/platforms/pseries/papr_scm.c
index 9c569078a09f..9a9a0766f8b6 100644
--- a/arch/powerpc/platforms/pseries/papr_scm.c
+++ b/arch/powerpc/platforms/pseries/papr_scm.c
@@ -630,6 +630,18 @@ static int papr_scm_ndctl(struct nvdimm_bus_descriptor *nd_desc,
return 0;
}
+/*
+ * We have made sure the pmem writes are done such that before calling this
+ * all the caches are flushed/clean. We use dcbf/dcbfps to ensure this. Here
+ * we just need to add the necessary barrier to make sure the above flushes
+ * are have updated persistent storage before any data access or data transfer
+ * caused by subsequent instructions is initiated.
+ */
+static int papr_scm_flush_sync(struct nd_region *nd_region, struct bio *bio)
+{
+ arch_pmem_flush_barrier();
+ return 0;
+}
static ssize_t flags_show(struct device *dev,
struct device_attribute *attr, char *buf)
@@ -743,6 +755,7 @@ static int papr_scm_nvdimm_init(struct papr_scm_priv *p)
ndr_desc.mapping = &mapping;
ndr_desc.num_mappings = 1;
ndr_desc.nd_set = &p->nd_set;
+ ndr_desc.flush = papr_scm_flush_sync;
if (p->is_volatile)
p->region = nvdimm_volatile_region_create(p->bus, &ndr_desc);
--
2.26.2
^ permalink raw reply related
* [PATCH v6 4/8] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier
From: Aneesh Kumar K.V @ 2020-06-29 13:57 UTC (permalink / raw)
To: linuxppc-dev, mpe, linux-nvdimm, dan.j.williams
Cc: Jan Kara, Jeff Moyer, msuchanek, oohall, Aneesh Kumar K.V
In-Reply-To: <20200629135722.73558-1-aneesh.kumar@linux.ibm.com>
Architectures like ppc64 provide persistent memory specific barriers
that will ensure that all stores for which the modifications are
written to persistent storage by preceding dcbfps and dcbstps
instructions have updated persistent storage before any data
access or data transfer caused by subsequent instructions is initiated.
This is in addition to the ordering done by wmb()
Update nvdimm core such that architecture can use barriers other than
wmb to ensure all previous writes are architecturally visible for
the platform buffer flush.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
drivers/md/dm-writecache.c | 2 +-
drivers/nvdimm/region_devs.c | 8 ++++----
include/asm-generic/cacheflush.h | 4 ++++
3 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/md/dm-writecache.c b/drivers/md/dm-writecache.c
index 74f3c506f084..8c6b6dce64e2 100644
--- a/drivers/md/dm-writecache.c
+++ b/drivers/md/dm-writecache.c
@@ -536,7 +536,7 @@ static void ssd_commit_superblock(struct dm_writecache *wc)
static void writecache_commit_flushed(struct dm_writecache *wc, bool wait_for_ios)
{
if (WC_MODE_PMEM(wc))
- wmb();
+ arch_pmem_flush_barrier();
else
ssd_commit_flushed(wc, wait_for_ios);
}
diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c
index 4502f9c4708d..b308ad09b63d 100644
--- a/drivers/nvdimm/region_devs.c
+++ b/drivers/nvdimm/region_devs.c
@@ -1206,13 +1206,13 @@ int generic_nvdimm_flush(struct nd_region *nd_region)
idx = this_cpu_add_return(flush_idx, hash_32(current->pid + idx, 8));
/*
- * The first wmb() is needed to 'sfence' all previous writes
- * such that they are architecturally visible for the platform
- * buffer flush. Note that we've already arranged for pmem
+ * The first arch_pmem_flush_barrier() is needed to 'sfence' all
+ * previous writes such that they are architecturally visible for
+ * the platform buffer flush. Note that we've already arranged for pmem
* writes to avoid the cache via memcpy_flushcache(). The final
* wmb() ensures ordering for the NVDIMM flush write.
*/
- wmb();
+ arch_pmem_flush_barrier();
for (i = 0; i < nd_region->ndr_mappings; i++)
if (ndrd_get_flush_wpq(ndrd, i, 0))
writeq(1, ndrd_get_flush_wpq(ndrd, i, idx));
diff --git a/include/asm-generic/cacheflush.h b/include/asm-generic/cacheflush.h
index 907fa5d16494..e30a9aa950dc 100644
--- a/include/asm-generic/cacheflush.h
+++ b/include/asm-generic/cacheflush.h
@@ -110,4 +110,8 @@ static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
memcpy(dst, src, len)
#endif
+#ifndef arch_pmem_flush_barrier
+#define arch_pmem_flush_barrier() wmb()
+#endif
+
#endif /* _ASM_GENERIC_CACHEFLUSH_H */
--
2.26.2
^ permalink raw reply related
* [PATCH v6 5/8] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction.
From: Aneesh Kumar K.V @ 2020-06-29 13:57 UTC (permalink / raw)
To: linuxppc-dev, mpe, linux-nvdimm, dan.j.williams
Cc: Jan Kara, Jeff Moyer, msuchanek, oohall, Aneesh Kumar K.V
In-Reply-To: <20200629135722.73558-1-aneesh.kumar@linux.ibm.com>
of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/include/asm/cacheflush.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index 54764c6e922d..95782f77d768 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -98,6 +98,13 @@ static inline void invalidate_dcache_range(unsigned long start,
mb(); /* sync */
}
+#define arch_pmem_flush_barrier arch_pmem_flush_barrier
+static inline void arch_pmem_flush_barrier(void)
+{
+ if (cpu_has_feature(CPU_FTR_ARCH_207S))
+ asm volatile(PPC_PHWSYNC ::: "memory");
+}
+
#include <asm-generic/cacheflush.h>
#endif /* _ASM_POWERPC_CACHEFLUSH_H */
--
2.26.2
^ permalink raw reply related
* [PATCH v6 3/8] powerpc/pmem: Add flush routines using new pmem store and sync instruction
From: Aneesh Kumar K.V @ 2020-06-29 13:57 UTC (permalink / raw)
To: linuxppc-dev, mpe, linux-nvdimm, dan.j.williams
Cc: Jan Kara, Jeff Moyer, msuchanek, oohall, Aneesh Kumar K.V
In-Reply-To: <20200629135722.73558-1-aneesh.kumar@linux.ibm.com>
Start using dcbstps; phwsync; sequence for flushing persistent memory range.
The new instructions are implemented as a variant of dcbf and hwsync and on
P8 and P9 they will be executed as those instructions. We avoid using them on
older hardware. This helps to avoid difficult to debug bugs.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/include/asm/cacheflush.h | 1 +
arch/powerpc/lib/pmem.c | 50 ++++++++++++++++++++++++---
2 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index de600b915a3c..54764c6e922d 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -6,6 +6,7 @@
#include <linux/mm.h>
#include <asm/cputable.h>
+#include <asm/cpu_has_feature.h>
#ifdef CONFIG_PPC_BOOK3S_64
/*
diff --git a/arch/powerpc/lib/pmem.c b/arch/powerpc/lib/pmem.c
index 0666a8d29596..5a61aaeb6930 100644
--- a/arch/powerpc/lib/pmem.c
+++ b/arch/powerpc/lib/pmem.c
@@ -9,20 +9,62 @@
#include <asm/cacheflush.h>
+static inline void __clean_pmem_range(unsigned long start, unsigned long stop)
+{
+ unsigned long shift = l1_dcache_shift();
+ unsigned long bytes = l1_dcache_bytes();
+ void *addr = (void *)(start & ~(bytes - 1));
+ unsigned long size = stop - (unsigned long)addr + (bytes - 1);
+ unsigned long i;
+
+ for (i = 0; i < size >> shift; i++, addr += bytes)
+ asm volatile(PPC_DCBSTPS(%0, %1): :"i"(0), "r"(addr): "memory");
+
+
+ asm volatile(PPC_PHWSYNC ::: "memory");
+}
+
+static inline void __flush_pmem_range(unsigned long start, unsigned long stop)
+{
+ unsigned long shift = l1_dcache_shift();
+ unsigned long bytes = l1_dcache_bytes();
+ void *addr = (void *)(start & ~(bytes - 1));
+ unsigned long size = stop - (unsigned long)addr + (bytes - 1);
+ unsigned long i;
+
+ for (i = 0; i < size >> shift; i++, addr += bytes)
+ asm volatile(PPC_DCBFPS(%0, %1): :"i"(0), "r"(addr): "memory");
+
+
+ asm volatile(PPC_PHWSYNC ::: "memory");
+}
+
+static inline void clean_pmem_range(unsigned long start, unsigned long stop)
+{
+ if (cpu_has_feature(CPU_FTR_ARCH_207S))
+ return __clean_pmem_range(start, stop);
+}
+
+static inline void flush_pmem_range(unsigned long start, unsigned long stop)
+{
+ if (cpu_has_feature(CPU_FTR_ARCH_207S))
+ return __flush_pmem_range(start, stop);
+}
+
/*
* CONFIG_ARCH_HAS_PMEM_API symbols
*/
void arch_wb_cache_pmem(void *addr, size_t size)
{
unsigned long start = (unsigned long) addr;
- flush_dcache_range(start, start + size);
+ clean_pmem_range(start, start + size);
}
EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
void arch_invalidate_pmem(void *addr, size_t size)
{
unsigned long start = (unsigned long) addr;
- flush_dcache_range(start, start + size);
+ flush_pmem_range(start, start + size);
}
EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
@@ -35,7 +77,7 @@ long __copy_from_user_flushcache(void *dest, const void __user *src,
unsigned long copied, start = (unsigned long) dest;
copied = __copy_from_user(dest, src, size);
- flush_dcache_range(start, start + size);
+ clean_pmem_range(start, start + size);
return copied;
}
@@ -45,7 +87,7 @@ void *memcpy_flushcache(void *dest, const void *src, size_t size)
unsigned long start = (unsigned long) dest;
memcpy(dest, src, size);
- flush_dcache_range(start, start + size);
+ clean_pmem_range(start, start + size);
return dest;
}
--
2.26.2
^ permalink raw reply related
* [PATCH v6 2/8] powerpc/pmem: Add new instructions for persistent storage and sync
From: Aneesh Kumar K.V @ 2020-06-29 13:57 UTC (permalink / raw)
To: linuxppc-dev, mpe, linux-nvdimm, dan.j.williams
Cc: Jan Kara, Jeff Moyer, msuchanek, oohall, Aneesh Kumar K.V
In-Reply-To: <20200629135722.73558-1-aneesh.kumar@linux.ibm.com>
POWER10 introduces two new variants of dcbf instructions (dcbstps and dcbfps)
that can be used to write modified locations back to persistent storage.
Additionally, POWER10 also introduce phwsync and plwsync which can be used
to establish order of these writes to persistent storage.
This patch exposes these instructions to the rest of the kernel. The existing
dcbf and hwsync instructions in P8 and P9 are adequate to enable appropriate
synchronization with OpenCAPI-hosted persistent storage. Hence the new
instructions are added as a variant of the old ones that old hardware
won't differentiate.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/include/asm/ppc-opcode.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 2a39c716c343..1ad014e4633e 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -219,6 +219,8 @@
#define PPC_INST_STWCX 0x7c00012d
#define PPC_INST_LWSYNC 0x7c2004ac
#define PPC_INST_SYNC 0x7c0004ac
+#define PPC_INST_PHWSYNC 0x7c8004ac
+#define PPC_INST_PLWSYNC 0x7ca004ac
#define PPC_INST_SYNC_MASK 0xfc0007fe
#define PPC_INST_ISYNC 0x4c00012c
#define PPC_INST_LXVD2X 0x7c000698
@@ -284,6 +286,8 @@
#define PPC_INST_TABORT 0x7c00071d
#define PPC_INST_TSR 0x7c0005dd
+#define PPC_INST_DCBF 0x7c0000ac
+
#define PPC_INST_NAP 0x4c000364
#define PPC_INST_SLEEP 0x4c0003a4
#define PPC_INST_WINKLE 0x4c0003e4
@@ -532,6 +536,14 @@
#define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \
__PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
+#define PPC_DCBFPS(a, b) stringify_in_c(.long PPC_INST_DCBF | \
+ ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21))
+#define PPC_DCBSTPS(a, b) stringify_in_c(.long PPC_INST_DCBF | \
+ ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21))
+
+#define PPC_PHWSYNC stringify_in_c(.long PPC_INST_PHWSYNC)
+#define PPC_PLWSYNC stringify_in_c(.long PPC_INST_PLWSYNC)
+
/*
* Define what the VSX XX1 form instructions will look like, then add
* the 128 bit load store instructions based on that.
--
2.26.2
^ permalink raw reply related
* [PATCH v6 1/8] powerpc/pmem: Restrict papr_scm to P8 and above.
From: Aneesh Kumar K.V @ 2020-06-29 13:57 UTC (permalink / raw)
To: linuxppc-dev, mpe, linux-nvdimm, dan.j.williams
Cc: Jan Kara, Jeff Moyer, msuchanek, oohall, Aneesh Kumar K.V
In-Reply-To: <20200629135722.73558-1-aneesh.kumar@linux.ibm.com>
The PAPR based virtualized persistent memory devices are only supported on
POWER9 and above. In the followup patch, the kernel will switch the persistent
memory cache flush functions to use a new `dcbf` variant instruction. The new
instructions even though added in ISA 3.1 works even on P8 and P9 because these
are implemented as a variant of existing `dcbf` and `hwsync` and on P8 and
P9 behaves as such.
Considering these devices are only supported on P8 and above, update the driver
to prevent a P7-compat guest from using persistent memory devices.
We don't update of_pmem driver with the same condition, because, on bare-metal,
the firmware enables pmem support only on P9 and above. There the kernel depends
on OPAL firmware to restrict exposing persistent memory related device tree
entries on older hardware. of_pmem.ko is written without any arch dependency and
we don't want to add ppc64 specific cpu feature check in of_pmem driver.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/platforms/pseries/pmem.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/pmem.c b/arch/powerpc/platforms/pseries/pmem.c
index f860a897a9e0..2347e1038f58 100644
--- a/arch/powerpc/platforms/pseries/pmem.c
+++ b/arch/powerpc/platforms/pseries/pmem.c
@@ -147,6 +147,12 @@ const struct of_device_id drc_pmem_match[] = {
static int pseries_pmem_init(void)
{
+ /*
+ * Only supported on POWER8 and above.
+ */
+ if (!cpu_has_feature(CPU_FTR_ARCH_207S))
+ return 0;
+
pmem_node = of_find_node_by_type(NULL, "ibm,persistent-memory");
if (!pmem_node)
return 0;
--
2.26.2
^ permalink raw reply related
* Re: [PATCH 1/3] powerpc/cacheinfo: Use cpumap_print to print cpumap
From: Tejun Heo @ 2020-06-29 13:26 UTC (permalink / raw)
To: Srikar Dronamraju; +Cc: Nathan Lynch, linuxppc-dev
In-Reply-To: <20200629103703.4538-2-srikar@linux.vnet.ibm.com>
On Mon, Jun 29, 2020 at 04:07:01PM +0530, Srikar Dronamraju wrote:
> Tejun Heo had modified shared_cpu_map_show to use scnprintf instead of
> cpumap_print during support for *pb[l] format.
> Refer commit 0c118b7bd09a ("powerpc: use %*pb[l] to print bitmaps including
> cpumasks and nodemasks")
>
> cpumap_print_to_pagebuf is a standard function to print cpumap. With
> commit 9cf79d115f0d ("bitmap: remove explicit newline handling using
> scnprintf format string"), there is no need to print explicit newline and
> trailing null character. cpumap_print_to_pagebuf internally uses
> scnprintf. Hence replace scnprintf with cpumap_print_to_pagebuf.
>
> Note: shared_cpu_map_show in drivers/base/cacheinfo.c already uses
> cpumap_print_to_pagebuf.
>
> Before this patch
> # cat /sys/devices/system/cpu0/cache/index1/shared_cpu_map
> 00ff
>
> #
> (Notice the extra blank line).
>
> After this patch
> # cat /sys/devices/system/cpu0/cache/index1/shared_cpu_map
> 00ff
> #
>
> Cc: Nathan Lynch <nathanl@linux.ibm.com>
> Cc: Tejun Heo <tj@kernel.org>
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Cc: linuxppc-dev@lists.ozlabs.org
> Signed-off-by: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Acked-by: Tejun Heo <tj@kernel.org>
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 01/11] kexec_file: allow archs to handle special regions while locating memory hole
From: Hari Bathini @ 2020-06-29 11:56 UTC (permalink / raw)
To: Petr Tesarik
Cc: Thiago Jung Bauermann, Pingfan Liu, Kexec-ml, Mahesh J Salgaonkar,
Mimi Zohar, lkml, linuxppc-dev, Sourabh Jain, Andrew Morton,
Dave Young, Vivek Goyal, Eric Biederman
In-Reply-To: <20200629133933.0787f562@ezekiel.suse.cz>
Hi Petr,
On 29/06/20 5:09 pm, Petr Tesarik wrote:
> Hi Hari,
>
> is there any good reason to add two more functions with a very similar
> name to an existing function? AFAICS all you need is a way to call a
> PPC64-specific function from within kexec_add_buffer (PATCH 4/11), so
> you could add something like this:
>
> int __weak arch_kexec_locate_mem_hole(struct kexec_buf *kbuf)
> {
> return 0;
> }
>
> Call this function from kexec_add_buffer where appropriate and then
> override it for PPC64 (it roughly corresponds to your
> kexec_locate_mem_hole_ppc64() from PATCH 4/11).
>
> FWIW it would make it easier for me to follow the resulting code.
Right, Petr.
I was trying out a few things before I ended up with what I sent here.
Bu yeah.. I did realize arch_kexec_locate_mem_hole() would have been better
after sending out v1. Will take care of that in v2.
Thanks
Hari
^ permalink raw reply
* Re: [PATCH 01/11] kexec_file: allow archs to handle special regions while locating memory hole
From: Petr Tesarik @ 2020-06-29 11:39 UTC (permalink / raw)
To: Hari Bathini
Cc: Pingfan Liu, Kexec-ml, Mahesh J Salgaonkar, Mimi Zohar, lkml,
linuxppc-dev, Sourabh Jain, Vivek Goyal, Andrew Morton,
Dave Young, Thiago Jung Bauermann, Eric Biederman
In-Reply-To: <159319828304.16351.6990340111766605842.stgit@hbathini.in.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 4136 bytes --]
Hi Hari,
is there any good reason to add two more functions with a very similar
name to an existing function? AFAICS all you need is a way to call a
PPC64-specific function from within kexec_add_buffer (PATCH 4/11), so
you could add something like this:
int __weak arch_kexec_locate_mem_hole(struct kexec_buf *kbuf)
{
return 0;
}
Call this function from kexec_add_buffer where appropriate and then
override it for PPC64 (it roughly corresponds to your
kexec_locate_mem_hole_ppc64() from PATCH 4/11).
FWIW it would make it easier for me to follow the resulting code.
Petr T
On Sat, 27 Jun 2020 00:34:43 +0530
Hari Bathini <hbathini@linux.ibm.com> wrote:
> Some archs can have special memory regions, within the given memory
> range, which can't be used for the buffer in a kexec segment. As
> kexec_add_buffer() function is being called from generic code as well,
> add weak arch_kexec_add_buffer definition for archs to override & take
> care of special regions before trying to locate a memory hole.
>
> Signed-off-by: Hari Bathini <hbathini@linux.ibm.com>
> ---
> include/linux/kexec.h | 5 +++++
> kernel/kexec_file.c | 37 +++++++++++++++++++++++++++++++++----
> 2 files changed, 38 insertions(+), 4 deletions(-)
>
> diff --git a/include/linux/kexec.h b/include/linux/kexec.h
> index 1776eb2..1237682 100644
> --- a/include/linux/kexec.h
> +++ b/include/linux/kexec.h
> @@ -195,6 +195,11 @@ int __weak arch_kexec_apply_relocations(struct purgatory_info *pi,
> const Elf_Shdr *relsec,
> const Elf_Shdr *symtab);
>
> +extern int arch_kexec_add_buffer(struct kexec_buf *kbuf);
> +
> +/* arch_kexec_add_buffer calls this when it is ready */
> +extern int __kexec_add_buffer(struct kexec_buf *kbuf);
> +
> extern int kexec_add_buffer(struct kexec_buf *kbuf);
> int kexec_locate_mem_hole(struct kexec_buf *kbuf);
>
> diff --git a/kernel/kexec_file.c b/kernel/kexec_file.c
> index bb05fd5..a0b4f7f 100644
> --- a/kernel/kexec_file.c
> +++ b/kernel/kexec_file.c
> @@ -669,10 +669,6 @@ int kexec_locate_mem_hole(struct kexec_buf *kbuf)
> */
> int kexec_add_buffer(struct kexec_buf *kbuf)
> {
> -
> - struct kexec_segment *ksegment;
> - int ret;
> -
> /* Currently adding segment this way is allowed only in file mode */
> if (!kbuf->image->file_mode)
> return -EINVAL;
> @@ -696,6 +692,25 @@ int kexec_add_buffer(struct kexec_buf *kbuf)
> kbuf->memsz = ALIGN(kbuf->memsz, PAGE_SIZE);
> kbuf->buf_align = max(kbuf->buf_align, PAGE_SIZE);
>
> + return arch_kexec_add_buffer(kbuf);
> +}
> +
> +/**
> + * __kexec_add_buffer - arch_kexec_add_buffer would call this function after
> + * updating kbuf, to place a buffer in a kexec segment.
> + * @kbuf: Buffer contents and memory parameters.
> + *
> + * This function assumes that kexec_mutex is held.
> + * On successful return, @kbuf->mem will have the physical address of
> + * the buffer in memory.
> + *
> + * Return: 0 on success, negative errno on error.
> + */
> +int __kexec_add_buffer(struct kexec_buf *kbuf)
> +{
> + struct kexec_segment *ksegment;
> + int ret;
> +
> /* Walk the RAM ranges and allocate a suitable range for the buffer */
> ret = kexec_locate_mem_hole(kbuf);
> if (ret)
> @@ -711,6 +726,20 @@ int kexec_add_buffer(struct kexec_buf *kbuf)
> return 0;
> }
>
> +/**
> + * arch_kexec_add_buffer - Some archs have memory regions within the given
> + * range that can't be used to place a kexec segment.
> + * Such archs can override this function to take care
> + * of them before trying to locate the memory hole.
> + * @kbuf: Buffer contents and memory parameters.
> + *
> + * Return: 0 on success, negative errno on error.
> + */
> +int __weak arch_kexec_add_buffer(struct kexec_buf *kbuf)
> +{
> + return __kexec_add_buffer(kbuf);
> +}
> +
> /* Calculate and store the digest of segments */
> static int kexec_calculate_store_digests(struct kimage *image)
> {
>
[-- Attachment #2: Digitální podpis OpenPGP --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH v2] powerpc/uaccess: Use flexible addressing with __put_user()/__get_user()
From: Michael Ellerman @ 2020-06-29 11:27 UTC (permalink / raw)
To: Christophe Leroy, Benjamin Herrenschmidt, Paul Mackerras, npiggin,
segher
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <7b916759-1683-b4df-0d4b-b04b3fcd9a02@csgroup.eu>
Christophe Leroy <christophe.leroy@csgroup.eu> writes:
> Hi Michael,
>
> I see this patch is marked as "defered" in patchwork, but I can't see
> any related discussion. Is it normal ?
Because it uses the "m<>" constraint which didn't work on GCC 4.6.
https://github.com/linuxppc/issues/issues/297
So we should be able to pick it up for v5.9 hopefully.
cheers
> Le 16/04/2020 à 14:39, Christophe Leroy a écrit :
>> At the time being, __put_user()/__get_user() and friends only use
>> D-form addressing, with 0 offset. Ex:
>>
>> lwz reg1, 0(reg2)
>>
>> Give the compiler the opportunity to use other adressing modes
>> whenever possible, to get more optimised code.
>>
>> Hereunder is a small exemple:
>>
>> struct test {
>> u32 item1;
>> u16 item2;
>> u8 item3;
>> u64 item4;
>> };
>>
>> int set_test_user(struct test __user *from, struct test __user *to)
>> {
>> int err;
>> u32 item1;
>> u16 item2;
>> u8 item3;
>> u64 item4;
>>
>> err = __get_user(item1, &from->item1);
>> err |= __get_user(item2, &from->item2);
>> err |= __get_user(item3, &from->item3);
>> err |= __get_user(item4, &from->item4);
>>
>> err |= __put_user(item1, &to->item1);
>> err |= __put_user(item2, &to->item2);
>> err |= __put_user(item3, &to->item3);
>> err |= __put_user(item4, &to->item4);
>>
>> return err;
>> }
>>
>> Before the patch:
>>
>> 00000df0 <set_test_user>:
>> df0: 94 21 ff f0 stwu r1,-16(r1)
>> df4: 39 40 00 00 li r10,0
>> df8: 93 c1 00 08 stw r30,8(r1)
>> dfc: 93 e1 00 0c stw r31,12(r1)
>> e00: 7d 49 53 78 mr r9,r10
>> e04: 80 a3 00 00 lwz r5,0(r3)
>> e08: 38 e3 00 04 addi r7,r3,4
>> e0c: 7d 46 53 78 mr r6,r10
>> e10: a0 e7 00 00 lhz r7,0(r7)
>> e14: 7d 29 33 78 or r9,r9,r6
>> e18: 39 03 00 06 addi r8,r3,6
>> e1c: 7d 46 53 78 mr r6,r10
>> e20: 89 08 00 00 lbz r8,0(r8)
>> e24: 7d 29 33 78 or r9,r9,r6
>> e28: 38 63 00 08 addi r3,r3,8
>> e2c: 7d 46 53 78 mr r6,r10
>> e30: 83 c3 00 00 lwz r30,0(r3)
>> e34: 83 e3 00 04 lwz r31,4(r3)
>> e38: 7d 29 33 78 or r9,r9,r6
>> e3c: 7d 43 53 78 mr r3,r10
>> e40: 90 a4 00 00 stw r5,0(r4)
>> e44: 7d 29 1b 78 or r9,r9,r3
>> e48: 38 c4 00 04 addi r6,r4,4
>> e4c: 7d 43 53 78 mr r3,r10
>> e50: b0 e6 00 00 sth r7,0(r6)
>> e54: 7d 29 1b 78 or r9,r9,r3
>> e58: 38 e4 00 06 addi r7,r4,6
>> e5c: 7d 43 53 78 mr r3,r10
>> e60: 99 07 00 00 stb r8,0(r7)
>> e64: 7d 23 1b 78 or r3,r9,r3
>> e68: 38 84 00 08 addi r4,r4,8
>> e6c: 93 c4 00 00 stw r30,0(r4)
>> e70: 93 e4 00 04 stw r31,4(r4)
>> e74: 7c 63 53 78 or r3,r3,r10
>> e78: 83 c1 00 08 lwz r30,8(r1)
>> e7c: 83 e1 00 0c lwz r31,12(r1)
>> e80: 38 21 00 10 addi r1,r1,16
>> e84: 4e 80 00 20 blr
>>
>> After the patch:
>>
>> 00000dbc <set_test_user>:
>> dbc: 39 40 00 00 li r10,0
>> dc0: 7d 49 53 78 mr r9,r10
>> dc4: 80 03 00 00 lwz r0,0(r3)
>> dc8: 7d 48 53 78 mr r8,r10
>> dcc: a1 63 00 04 lhz r11,4(r3)
>> dd0: 7d 29 43 78 or r9,r9,r8
>> dd4: 7d 48 53 78 mr r8,r10
>> dd8: 88 a3 00 06 lbz r5,6(r3)
>> ddc: 7d 29 43 78 or r9,r9,r8
>> de0: 7d 48 53 78 mr r8,r10
>> de4: 80 c3 00 08 lwz r6,8(r3)
>> de8: 80 e3 00 0c lwz r7,12(r3)
>> dec: 7d 29 43 78 or r9,r9,r8
>> df0: 7d 43 53 78 mr r3,r10
>> df4: 90 04 00 00 stw r0,0(r4)
>> df8: 7d 29 1b 78 or r9,r9,r3
>> dfc: 7d 43 53 78 mr r3,r10
>> e00: b1 64 00 04 sth r11,4(r4)
>> e04: 7d 29 1b 78 or r9,r9,r3
>> e08: 7d 43 53 78 mr r3,r10
>> e0c: 98 a4 00 06 stb r5,6(r4)
>> e10: 7d 23 1b 78 or r3,r9,r3
>> e14: 90 c4 00 08 stw r6,8(r4)
>> e18: 90 e4 00 0c stw r7,12(r4)
>> e1c: 7c 63 53 78 or r3,r3,r10
>> e20: 4e 80 00 20 blr
>>
>> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
>> Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org>
>> ---
>> v2:
>> - Added <> modifier in __put_user_asm() and __get_user_asm()
>> - Removed %U2 in __put_user_asm2() and __get_user_asm2()
>> - Reworded the commit log
>> ---
>> arch/powerpc/include/asm/uaccess.h | 28 ++++++++++++++--------------
>> 1 file changed, 14 insertions(+), 14 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/uaccess.h b/arch/powerpc/include/asm/uaccess.h
>> index 7c811442b607..9365b59495a2 100644
>> --- a/arch/powerpc/include/asm/uaccess.h
>> +++ b/arch/powerpc/include/asm/uaccess.h
>> @@ -114,7 +114,7 @@ extern long __put_user_bad(void);
>> */
>> #define __put_user_asm(x, addr, err, op) \
>> __asm__ __volatile__( \
>> - "1: " op " %1,0(%2) # put_user\n" \
>> + "1: " op "%U2%X2 %1,%2 # put_user\n" \
>> "2:\n" \
>> ".section .fixup,\"ax\"\n" \
>> "3: li %0,%3\n" \
>> @@ -122,7 +122,7 @@ extern long __put_user_bad(void);
>> ".previous\n" \
>> EX_TABLE(1b, 3b) \
>> : "=r" (err) \
>> - : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
>> + : "r" (x), "m<>" (*addr), "i" (-EFAULT), "0" (err))
>>
>> #ifdef __powerpc64__
>> #define __put_user_asm2(x, ptr, retval) \
>> @@ -130,8 +130,8 @@ extern long __put_user_bad(void);
>> #else /* __powerpc64__ */
>> #define __put_user_asm2(x, addr, err) \
>> __asm__ __volatile__( \
>> - "1: stw %1,0(%2)\n" \
>> - "2: stw %1+1,4(%2)\n" \
>> + "1: stw%X2 %1,%2\n" \
>> + "2: stw%X2 %L1,%L2\n" \
>> "3:\n" \
>> ".section .fixup,\"ax\"\n" \
>> "4: li %0,%3\n" \
>> @@ -140,7 +140,7 @@ extern long __put_user_bad(void);
>> EX_TABLE(1b, 4b) \
>> EX_TABLE(2b, 4b) \
>> : "=r" (err) \
>> - : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
>> + : "r" (x), "m" (*addr), "i" (-EFAULT), "0" (err))
>> #endif /* __powerpc64__ */
>>
>> #define __put_user_size_allowed(x, ptr, size, retval) \
>> @@ -260,7 +260,7 @@ extern long __get_user_bad(void);
>>
>> #define __get_user_asm(x, addr, err, op) \
>> __asm__ __volatile__( \
>> - "1: "op" %1,0(%2) # get_user\n" \
>> + "1: "op"%U2%X2 %1, %2 # get_user\n" \
>> "2:\n" \
>> ".section .fixup,\"ax\"\n" \
>> "3: li %0,%3\n" \
>> @@ -269,7 +269,7 @@ extern long __get_user_bad(void);
>> ".previous\n" \
>> EX_TABLE(1b, 3b) \
>> : "=r" (err), "=r" (x) \
>> - : "b" (addr), "i" (-EFAULT), "0" (err))
>> + : "m<>" (*addr), "i" (-EFAULT), "0" (err))
>>
>> #ifdef __powerpc64__
>> #define __get_user_asm2(x, addr, err) \
>> @@ -277,8 +277,8 @@ extern long __get_user_bad(void);
>> #else /* __powerpc64__ */
>> #define __get_user_asm2(x, addr, err) \
>> __asm__ __volatile__( \
>> - "1: lwz %1,0(%2)\n" \
>> - "2: lwz %1+1,4(%2)\n" \
>> + "1: lwz%X2 %1, %2\n" \
>> + "2: lwz%X2 %L1, %L2\n" \
>> "3:\n" \
>> ".section .fixup,\"ax\"\n" \
>> "4: li %0,%3\n" \
>> @@ -289,7 +289,7 @@ extern long __get_user_bad(void);
>> EX_TABLE(1b, 4b) \
>> EX_TABLE(2b, 4b) \
>> : "=r" (err), "=&r" (x) \
>> - : "b" (addr), "i" (-EFAULT), "0" (err))
>> + : "m" (*addr), "i" (-EFAULT), "0" (err))
>> #endif /* __powerpc64__ */
>>
>> #define __get_user_size_allowed(x, ptr, size, retval) \
>> @@ -299,10 +299,10 @@ do { \
>> if (size > sizeof(x)) \
>> (x) = __get_user_bad(); \
>> switch (size) { \
>> - case 1: __get_user_asm(x, ptr, retval, "lbz"); break; \
>> - case 2: __get_user_asm(x, ptr, retval, "lhz"); break; \
>> - case 4: __get_user_asm(x, ptr, retval, "lwz"); break; \
>> - case 8: __get_user_asm2(x, ptr, retval); break; \
>> + case 1: __get_user_asm(x, (u8 __user *)ptr, retval, "lbz"); break; \
>> + case 2: __get_user_asm(x, (u16 __user *)ptr, retval, "lhz"); break; \
>> + case 4: __get_user_asm(x, (u32 __user *)ptr, retval, "lwz"); break; \
>> + case 8: __get_user_asm2(x, (u64 __user *)ptr, retval); break; \
>> default: (x) = __get_user_bad(); \
>> } \
>> } while (0)
>>
^ permalink raw reply
* [PATCH v2 2/2] powerpc/ptdump: Refactor update of pg_state
From: Christophe Leroy @ 2020-06-29 11:17 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <610d6b1a60ad0bedef865a90153c1110cfaa507e.1593429426.git.christophe.leroy@csgroup.eu>
In note_page(), the pg_state is updated the same way in two places.
Add note_page_update_state() to do it.
Also include the display of boundary markers there as it is missing
"no level" leg, leading to a mismatch when the first two markers
are at the same address and the first displayed area uses that
address.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/mm/ptdump/ptdump.c | 34 +++++++++++++++++++--------------
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/ptdump.c b/arch/powerpc/mm/ptdump/ptdump.c
index 20a039867934..c911cd757f7d 100644
--- a/arch/powerpc/mm/ptdump/ptdump.c
+++ b/arch/powerpc/mm/ptdump/ptdump.c
@@ -199,6 +199,24 @@ static void note_prot_wx(struct pg_state *st, unsigned long addr)
st->wx_pages += (addr - st->start_address) / PAGE_SIZE;
}
+static void note_page_update_state(struct pg_state *st, unsigned long addr,
+ unsigned int level, u64 val, unsigned long page_size)
+{
+ u64 flag = val & pg_level[level].mask;
+ u64 pa = val & PTE_RPN_MASK;
+
+ st->level = level;
+ st->current_flags = flag;
+ st->start_address = addr;
+ st->start_pa = pa;
+ st->page_size = page_size;
+
+ while (addr >= st->marker[1].start_address) {
+ st->marker++;
+ pt_dump_seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
+ }
+}
+
static void note_page(struct pg_state *st, unsigned long addr,
unsigned int level, u64 val, unsigned long page_size)
{
@@ -207,12 +225,8 @@ static void note_page(struct pg_state *st, unsigned long addr,
/* At first no level is set */
if (!st->level) {
- st->level = level;
- st->current_flags = flag;
- st->start_address = addr;
- st->start_pa = pa;
- st->page_size = page_size;
pt_dump_seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
+ note_page_update_state(st, addr, level, val, page_size);
/*
* Dump the section of virtual memory when:
* - the PTE flags from one entry to the next differs.
@@ -244,15 +258,7 @@ static void note_page(struct pg_state *st, unsigned long addr,
* Address indicates we have passed the end of the
* current section of virtual memory
*/
- while (addr >= st->marker[1].start_address) {
- st->marker++;
- pt_dump_seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
- }
- st->start_address = addr;
- st->start_pa = pa;
- st->page_size = page_size;
- st->current_flags = flag;
- st->level = level;
+ note_page_update_state(st, addr, level, val, page_size);
}
st->last_pa = pa;
}
--
2.25.0
^ permalink raw reply related
* [PATCH v2 1/2] powerpc/ptdump: Refactor update of st->last_pa
From: Christophe Leroy @ 2020-06-29 11:17 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
st->last_pa is always updated in note_page() so it can
be done outside the if/elseif/else block.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/mm/ptdump/ptdump.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/ptdump.c b/arch/powerpc/mm/ptdump/ptdump.c
index b2ed1ca4f254..20a039867934 100644
--- a/arch/powerpc/mm/ptdump/ptdump.c
+++ b/arch/powerpc/mm/ptdump/ptdump.c
@@ -211,7 +211,6 @@ static void note_page(struct pg_state *st, unsigned long addr,
st->current_flags = flag;
st->start_address = addr;
st->start_pa = pa;
- st->last_pa = pa;
st->page_size = page_size;
pt_dump_seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
/*
@@ -251,13 +250,11 @@ static void note_page(struct pg_state *st, unsigned long addr,
}
st->start_address = addr;
st->start_pa = pa;
- st->last_pa = pa;
st->page_size = page_size;
st->current_flags = flag;
st->level = level;
- } else {
- st->last_pa = pa;
}
+ st->last_pa = pa;
}
static void walk_pte(struct pg_state *st, pmd_t *pmd, unsigned long start)
--
2.25.0
^ permalink raw reply related
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