* Re: [PATCH v2] powerpc: Allow relative pointers in bug table entries
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: Jordan Niethe, linuxppc-dev
In-Reply-To: <20201201005203.15210-1-jniethe5@gmail.com>
On Tue, 1 Dec 2020 11:52:03 +1100, Jordan Niethe wrote:
> This enables GENERIC_BUG_RELATIVE_POINTERS on Power so that 32-bit
> offsets are stored in the bug entries rather than 64-bit pointers.
> While this doesn't save space for 32-bit machines, use it anyway so
> there is only one code path.
Applied to powerpc/next.
[1/1] powerpc: Allow relative pointers in bug table entries
https://git.kernel.org/powerpc/c/1baa1f70ef77c4447628992ad50ab83213e2eb6c
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/64: Fix an EMIT_BUG_ENTRY in head_64.S
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: Jordan Niethe, linuxppc-dev
In-Reply-To: <20201130004404.30953-1-jniethe5@gmail.com>
On Mon, 30 Nov 2020 11:44:04 +1100, Jordan Niethe wrote:
> Commit 63ce271b5e37 ("powerpc/prom: convert PROM_BUG() to standard
> trap") added an EMIT_BUG_ENTRY for the trap after the branch to
> start_kernel(). The EMIT_BUG_ENTRY was for the address "0b", however the
> trap was not labeled with "0". Hence the address used for bug is in
> relative_toc() where the previous "0" label is. Label the trap as "0" so
> the correct address is used.
Applied to powerpc/next.
[1/1] powerpc/64: Fix an EMIT_BUG_ENTRY in head_64.S
https://git.kernel.org/powerpc/c/fe18a35e685c9bdabc8b11b3e19deb85a068b75d
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/boot: move the .got section to after the .dynamic section
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: Bill Wendling, linuxppc-dev; +Cc: Paul Mackerras, Fangrui Song, Alan Modra
In-Reply-To: <20201017000151.150788-1-morbo@google.com>
On Fri, 16 Oct 2020 17:01:51 -0700, Bill Wendling wrote:
> Both .dynamic and .got are RELRO sections and should be placed together,
> and LLD emits an error:
>
> ld.lld: error: section: .got is not contiguous with other relro sections
>
> Place them together to avoid this.
Applied to powerpc/next.
[1/1] powerpc/boot: Move the .got section to after the .dynamic section
https://git.kernel.org/powerpc/c/a538d184e3f0e3b5f800c5ab148e83bb5cdd0133
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/wrapper: add "-z rodynamic" when using LLD
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: Bill Wendling, linuxppc-dev, Michael Ellerman
Cc: Nick Desaulniers, Fangrui Song, Alan Modra
In-Reply-To: <20201118223910.2711337-1-morbo@google.com>
On Wed, 18 Nov 2020 14:39:10 -0800, Bill Wendling wrote:
> Normally all read-only sections precede SHF_WRITE sections. .dynamic and
> .got have the SHF_WRITE flag; .dynamic probably because of DT_DEBUG. LLD
> emits an error when this happens, so use "-z rodynamic" to mark .dynamic
> as read-only.
Applied to powerpc/next.
[1/1] powerpc/boot/wrapper: Add "-z rodynamic" when using LLD
https://git.kernel.org/powerpc/c/26ba9f9651d802ba38583138f43fea5dc7eb0fd6
cheers
^ permalink raw reply
* Re: [PATCH 1/3] powerpc: Make NUMA depend on SMP
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: linuxppc-dev, Michael Ellerman; +Cc: rdunlap, srikar
In-Reply-To: <20201124120547.1940635-1-mpe@ellerman.id.au>
On Tue, 24 Nov 2020 23:05:45 +1100, Michael Ellerman wrote:
> Our Kconfig allows NUMA to be enabled without SMP, but none of
> our defconfigs use that combination. This means it can easily be
> broken inadvertently by code changes, which has happened recently.
>
> Although it's theoretically possible to have a machine with a single
> CPU and multiple memory nodes, I can't think of any real systems where
> that's the case. Even so if such a system exists, it can just run an
> SMP kernel anyway.
>
> [...]
Applied to powerpc/next.
[1/3] powerpc: Make NUMA depend on SMP
https://git.kernel.org/powerpc/c/25395cd2f8cb24ce6a5ce073c898acfb091e06cf
[2/3] powerpc: Make NUMA default y for powernv
https://git.kernel.org/powerpc/c/4c28b32b886f1489c5f510ed8e3f0c4e3dcb59f5
[3/3] powerpc: Update NUMA Kconfig description & help text
https://git.kernel.org/powerpc/c/bae80c27fc2195b9e5723d7b05c592e0874f4ba9
cheers
^ permalink raw reply
* Re: [PATCH v14 1/9] powerpc/feature: Use CONFIG_PPC64 instead of __powerpc64__ to define possible features
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: linuxppc-dev, Michael Ellerman
In-Reply-To: <20201126131006.2431205-1-mpe@ellerman.id.au>
On Fri, 27 Nov 2020 00:09:58 +1100, Michael Ellerman wrote:
> In order to build VDSO32 for PPC64, we need to have CPU_FTRS_POSSIBLE
> and CPU_FTRS_ALWAYS independant of whether we are building the
> 32 bits VDSO or the 64 bits VDSO.
>
> Use #ifdef CONFIG_PPC64 instead of #ifdef __powerpc64__
Applied to powerpc/next.
[1/9] powerpc/feature: Use CONFIG_PPC64 instead of __powerpc64__ to define possible features
https://git.kernel.org/powerpc/c/8d1eeabf253657ae3e76970514f30b7e53a6898f
[2/9] powerpc/processor: Move cpu_relax() into asm/vdso/processor.h
https://git.kernel.org/powerpc/c/8f8cffd9df81612b5b06d2c57ebf74f8961b41be
[3/9] powerpc/time: Move timebase functions into new asm/vdso/timebase.h
https://git.kernel.org/powerpc/c/d26b3817d9eefae6b777739c1ea5daba5e72624e
[4/9] powerpc/time: Fix mftb()/get_tb() for use with the compat VDSO
https://git.kernel.org/powerpc/c/5c189c523e78d4a70e874477e4b0628fd74207e4
[5/9] powerpc/barrier: Use CONFIG_PPC64 for barrier selection
https://git.kernel.org/powerpc/c/1f1676bb2dd52c1054db8476d6387e6dcf62a1ba
[6/9] powerpc/vdso: Prepare for switching VDSO to generic C implementation.
https://git.kernel.org/powerpc/c/ce7d8056e38b770f070fc4499c577322b6ccb9c7
[7/9] powerpc/vdso: Save and restore TOC pointer on PPC64
https://git.kernel.org/powerpc/c/7fec9f5d41979dbe273ec337327d5939449562e7
[8/9] powerpc/vdso: Switch VDSO to generic C implementation.
https://git.kernel.org/powerpc/c/ab037dd87a2f946556850e204c06cbd7a2a19390
[9/9] powerpc/vdso: Provide __kernel_clock_gettime64() on vdso32
https://git.kernel.org/powerpc/c/d0e3fc69d00d1f50d22d6b6acfc555ccda80ad1e
cheers
^ permalink raw reply
* Re: [PATCH 0/8] powerpc/64s: fix and improve machine check handling
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev; +Cc: Mahesh Salgaonkar, kvm-ppc
In-Reply-To: <20201128070728.825934-1-npiggin@gmail.com>
On Sat, 28 Nov 2020 17:07:20 +1000, Nicholas Piggin wrote:
> First patch is a nasty memory scribble introduced by me :( That
> should go into fixes.
>
> The next ones could wait for next merge window. They get things to the
> point where misbehaving or buggy guest isn't so painful for the host,
> and also get the guest SLB dumping code working (because the host no
> longer clears them before delivering the MCE to the guest).
>
> [...]
Patches 2-8 applied to powerpc/next.
[2/8] powerpc/64s/powernv: Allow KVM to handle guest machine check details
https://git.kernel.org/powerpc/c/0ce2382657f39ced2adbb927355360c3aaeb05f8
[3/8] KVM: PPC: Book3S HV: Don't attempt to recover machine checks for FWNMI enabled guests
https://git.kernel.org/powerpc/c/067c9f9c98c8804b07751994c51d8557e440821e
[4/8] KVM: PPC: Book3S HV: Ratelimit machine check messages coming from guests
https://git.kernel.org/powerpc/c/1d15ffdfc94127d75e04a88344ee1ce8c79f05fd
[5/8] powerpc/64s/powernv: Ratelimit harmless HMI error printing
https://git.kernel.org/powerpc/c/f4b239e4c6bddf63d00cd460eabb933232dbc326
[6/8] powerpc/64s/pseries: Add ERAT specific machine check handler
https://git.kernel.org/powerpc/c/82f70a05108c98aea4f140067c44a606262d2af7
[7/8] powerpc/64s: Remove "Host" from MCE logging
https://git.kernel.org/powerpc/c/4a869531ddbf5939c45eab6ff389e4e58c8ed19c
[8/8] powerpc/64s: Tidy machine check SLB logging
https://git.kernel.org/powerpc/c/865ae6f27789dcc3f92341d935f4439e8730a9fe
cheers
^ permalink raw reply
* Re: [RFC PATCH] powerpc: show registers when unwinding interrupt frames
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev
In-Reply-To: <20201107023305.2384874-1-npiggin@gmail.com>
On Sat, 7 Nov 2020 12:33:05 +1000, Nicholas Piggin wrote:
> It's often useful to know the register state for interrupts in
> the stack frame. In the below example (with this patch applied),
> the important information is the state of the page fault.
>
> A blatant case like this probably rather should have the page
> fault regs passed down to the warning, but quite often there are
> less obvious cases where an interrupt shows up that might give
> some more clues.
>
> [...]
Applied to powerpc/next.
[1/1] powerpc: show registers when unwinding interrupt frames
https://git.kernel.org/powerpc/c/bf13718bc57ada25016d9fe80323238d0b94506e
cheers
^ permalink raw reply
* Re: [PATCH v3 0/2] powerpc/ptrace: Hard wire PT_SOFTE value to 1 in gpr_get() too
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Oleg Nesterov, Madhavan Srinivasan,
Michael Ellerman, Paul Mackerras
Cc: Christophe Leroy, linuxppc-dev, linux-kernel, Nicholas Piggin,
Al Viro, Aneesh Kumar K.V, Jan Kratochvil
In-Reply-To: <20201119160154.GA5183@redhat.com>
On Thu, 19 Nov 2020 17:01:54 +0100, Oleg Nesterov wrote:
> Can we finally fix this problem? ;)
>
> My previous attempt was ignored, see
>
> https://lore.kernel.org/lkml/20190917121256.GA8659@redhat.com/
>
> Now that gpr_get() was changed to use membuf API we can make a simpler fix.
>
> [...]
Applied to powerpc/next.
[1/2] powerpc/ptrace: Simplify gpr_get()/tm_cgpr_get()
https://git.kernel.org/powerpc/c/640586f8af356096e084d69a9909d217852bde48
[2/2] powerpc/ptrace: Hard wire PT_SOFTE value to 1 in gpr_get() too
https://git.kernel.org/powerpc/c/324a69467f12652b21b17f9644faa967d3d8bbdf
cheers
^ permalink raw reply
* Re: [PATCH] powernv/pci: Print an error when device enable is blocked
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: Oliver O'Halloran, linuxppc-dev
In-Reply-To: <20200409061337.9187-1-oohall@gmail.com>
On Thu, 9 Apr 2020 16:13:37 +1000, Oliver O'Halloran wrote:
> If the platform decides to block enabling the device nothing is printed
> currently. This can lead to some confusion since the dmesg output will
> usually print an error with no context e.g.
>
> e1000e: probe of 0022:01:00.0 failed with error -22
>
> This shouldn't be spammy since pci_enable_device() already prints a
> messages when it succeeds.
Applied to powerpc/next.
[1/1] powernv/pci: Print an error when device enable is blocked
https://git.kernel.org/powerpc/c/6c58b1b41b19c00099e4771ee55e21eb9aa245c1
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/xmon: Fix build failure for 8xx
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: mpe, Ravi Bangoria; +Cc: christophe.leroy, mikey, linuxppc-dev
In-Reply-To: <20201130034406.288047-1-ravi.bangoria@linux.ibm.com>
On Mon, 30 Nov 2020 09:14:06 +0530, Ravi Bangoria wrote:
> With CONFIG_PPC_8xx and CONFIG_XMON set, kernel build fails with
>
> arch/powerpc/xmon/xmon.c:1379:12: error: 'find_free_data_bpt' defined
> but not used [-Werror=unused-function]
>
> Fix it by enclosing find_free_data_bpt() inside #ifndef CONFIG_PPC_8xx.
Applied to powerpc/next.
[1/1] powerpc/xmon: Fix build failure for 8xx
https://git.kernel.org/powerpc/c/f3e90408019b353fd1fcd338091fb8d3c4a1c1a5
cheers
^ permalink raw reply
* Re: [PATCH v2 0/4] Powerpc: Better preemption for shared processor
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: Srikar Dronamraju, Michael Ellerman
Cc: Nathan Lynch, Gautham R Shenoy, Phil Auld, Juri Lelli,
Peter Zijlstra, LKML, Nicholas Piggin, Waiman Long, linuxppc-dev,
Valentin Schneider
In-Reply-To: <20201202050456.164005-1-srikar@linux.vnet.ibm.com>
On Wed, 2 Dec 2020 10:34:52 +0530, Srikar Dronamraju wrote:
> Currently, vcpu_is_preempted will return the yield_count for
> shared_processor. On a PowerVM LPAR, Phyp schedules at SMT8 core boundary
> i.e all CPUs belonging to a core are either group scheduled in or group
> scheduled out. This can be used to better predict non-preempted CPUs on
> PowerVM shared LPARs.
>
> perf stat -r 5 -a perf bench sched pipe -l 10000000 (lesser time is better)
>
> [...]
Applied to powerpc/next.
[1/4] powerpc: Refactor is_kvm_guest() declaration to new header
https://git.kernel.org/powerpc/c/92cc6bf01c7f4c5cfefd1963985c0064687ebeda
[2/4] powerpc: Rename is_kvm_guest() to check_kvm_guest()
https://git.kernel.org/powerpc/c/16520a858a995742c2d2248e86a6026bd0316562
[3/4] powerpc: Reintroduce is_kvm_guest() as a fast-path check
https://git.kernel.org/powerpc/c/a21d1becaa3f17a97b933ffa677b526afc514ec5
[4/4] powerpc/paravirt: Use is_kvm_guest() in vcpu_is_preempted()
https://git.kernel.org/powerpc/c/ca3f969dcb111d35674b66bdcb72beb2c426b9b5
cheers
^ permalink raw reply
* Re: [PATCH] powerpc: Use common STABS_DEBUG and DWARF_DEBUG and ELF_DETAILS macro
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: Youling Tang, Paul Mackerras, Benjamin Herrenschmidt,
Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <1606460857-2723-1-git-send-email-tangyouling@loongson.cn>
On Fri, 27 Nov 2020 15:07:37 +0800, Youling Tang wrote:
> Use the common STABS_DEBUG and DWARF_DEBUG and ELF_DETAILS macro rule for
> the linker script in an effort.
Applied to powerpc/next.
[1/1] powerpc: Use common STABS_DEBUG and DWARF_DEBUG and ELF_DETAILS macro
https://git.kernel.org/powerpc/c/a21df7a1d6ca9bd387a17841863a99431c4aa730
cheers
^ permalink raw reply
* Re: [PATCH 1/2] ALSA: ppc: drop if block with always false condition
From: Michael Ellerman @ 2020-12-10 11:30 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz, Arnd Bergmann, James E.J. Bottomley,
Jaroslav Kysela, Michael Ellerman, Geoff Levand, Jakub Kicinski,
Martin K. Petersen, Jens Axboe, Jim Paris, Takashi Iwai,
Uwe Kleine-König, David S. Miller, Alan Stern,
Greg Kroah-Hartman
Cc: linux-fbdev, linux-scsi, linux-usb, alsa-devel, dri-devel,
linux-block, Paul Mackerras, netdev, linuxppc-dev
In-Reply-To: <20201126165950.2554997-1-u.kleine-koenig@pengutronix.de>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 622 bytes --]
On Thu, 26 Nov 2020 17:59:49 +0100, Uwe Kleine-König wrote:
> The remove callback is only called for devices that were probed
> successfully before. As the matching probe function cannot complete
> without error if dev->match_id != PS3_MATCH_ID_SOUND, we don't have to
> check this here.
Applied to powerpc/next.
[1/2] ALSA: ppc: drop if block with always false condition
https://git.kernel.org/powerpc/c/7ff94669e7d8e50756cd57947283381ae9665759
[2/2] powerpc/ps3: make system bus's remove and shutdown callbacks return void
https://git.kernel.org/powerpc/c/6d247e4d264961aa3b871290f9b11a48d5a567f2
cheers
^ permalink raw reply
* Re: Linux kernel: powerpc: RTAS calls can be used to compromise kernel integrity
From: Andrew Donnellan @ 2020-12-10 12:47 UTC (permalink / raw)
To: oss-security, linuxppc-dev; +Cc: Tyrel Datwyler
In-Reply-To: <a2fd9901-d8fc-3ba7-4422-2616bbf23220@linux.ibm.com>
On 24/11/20 1:41 am, Andrew Donnellan wrote:
> On 9/10/20 12:20 pm, Andrew Donnellan wrote:
>> The Linux kernel for powerpc has an issue with the Run-Time
>> Abstraction Services (RTAS) interface, allowing root (or CAP_SYS_ADMIN
>> users) in a VM to overwrite some parts of memory, including kernel
>> memory.
>>
>> This issue impacts guests running on top of PowerVM or KVM hypervisors
>> (pseries platform), and does *not* impact bare-metal machines (powernv
>> platform).
> CVE-2020-27777 has been assigned.
A minor regression has been identified, affecting the ibm,open-errinjct
RTAS call.
A patch is available at
https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20201208195434.8289-1-tyreld@linux.ibm.com/
Thanks to Tyrel Datwyler for identifying and fixing this issue.
--
Andrew Donnellan OzLabs, ADL Canberra
ajd@linux.ibm.com IBM Australia Limited
^ permalink raw reply
* Re: [PATCH] powerpc/rtas: fix typo of ibm,open-errinjct in rtas filter
From: Andrew Donnellan @ 2020-12-10 12:47 UTC (permalink / raw)
To: Tyrel Datwyler, mpe; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <20201208195434.8289-1-tyreld@linux.ibm.com>
On 9/12/20 6:54 am, Tyrel Datwyler wrote:
> Commit bd59380c5ba4 ("powerpc/rtas: Restrict RTAS requests from userspace")
> introduced the following error when invoking the errinjct userspace
> tool.
>
> [root@ltcalpine2-lp5 librtas]# errinjct open
> [327884.071171] sys_rtas: RTAS call blocked - exploit attempt?
> [327884.071186] sys_rtas: token=0x26, nargs=0 (called by errinjct)
> errinjct: Could not open RTAS error injection facility
> errinjct: librtas: open: Unexpected I/O error
>
> The entry for ibm,open-errinjct in rtas_filter array has a typo where
> the "j" is omitted in the rtas call name. After fixing this typo the
> errinjct tool functions again as expected.
>
> [root@ltcalpine2-lp5 linux]# errinjct open
> RTAS error injection facility open, token = 1
>
> fixes: bd59380c5ba4 ("powerpc/rtas: Restrict RTAS requests from userspace")
> Signed-off-by: Tyrel Datwyler <tyreld@linux.ibm.com>
Thanks for catching this!
Acked-by: Andrew Donnellan <ajd@linux.ibm.com>
--
Andrew Donnellan OzLabs, ADL Canberra
ajd@linux.ibm.com IBM Australia Limited
^ permalink raw reply
* Re: [PATCH 09/13] powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_SHIFT_BUG
From: Cédric Le Goater @ 2020-12-10 13:18 UTC (permalink / raw)
To: Greg Kurz; +Cc: linuxppc-dev
In-Reply-To: <20201208183906.1740c594@bahia.lan>
On 12/8/20 6:39 PM, Greg Kurz wrote:
> On Tue, 8 Dec 2020 16:11:20 +0100
> Cédric Le Goater <clg@kaod.org> wrote:
>
>> This flag was used to support the PHB4 LSIs on P9 DD1 and we have
>> stopped supporting this CPU when DD2 came out. See skiboot commit:
>>
>> https://github.com/open-power/skiboot/commit/0b0d15e3c170
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
>
> Just a minor suggestion in case you need to post a v2. See below.
>
>> arch/powerpc/include/asm/opal-api.h | 2 +-
>> arch/powerpc/include/asm/xive.h | 2 +-
>> arch/powerpc/kvm/book3s_xive_native.c | 3 ---
>> arch/powerpc/kvm/book3s_xive_template.c | 3 ---
>> arch/powerpc/sysdev/xive/common.c | 8 --------
>> arch/powerpc/sysdev/xive/native.c | 2 --
>> 6 files changed, 2 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
>> index 1dffa3cb16ba..48ee604ca39a 100644
>> --- a/arch/powerpc/include/asm/opal-api.h
>> +++ b/arch/powerpc/include/asm/opal-api.h
>> @@ -1091,7 +1091,7 @@ enum {
>> OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001,
>> OPAL_XIVE_IRQ_STORE_EOI = 0x00000002,
>> OPAL_XIVE_IRQ_LSI = 0x00000004,
>> - OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008,
>> + OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, /* P9 DD1.0 workaround */
>
> Maybe you can even comment the entire line so that any future
> tentative to use that flag breaks build ?
This file is "copied" from OPAL. I think it is best to keep them
in sync.
>
>> OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010,
>> OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
>> };
>> diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
>> index d332dd9a18de..ff805885a028 100644
>> --- a/arch/powerpc/include/asm/xive.h
>> +++ b/arch/powerpc/include/asm/xive.h
>> @@ -60,7 +60,7 @@ struct xive_irq_data {
>> };
>> #define XIVE_IRQ_FLAG_STORE_EOI 0x01
>> #define XIVE_IRQ_FLAG_LSI 0x02
>> -#define XIVE_IRQ_FLAG_SHIFT_BUG 0x04
>> +#define XIVE_IRQ_FLAG_SHIFT_BUG 0x04 /* P9 DD1.0 workaround */
>
> Same here, with an extra cleanup to stop using it when initializing
> xive_irq_flags[] in common.c.
Yes. Since this is an internal flag, we can simply remove it.
Thanks,
C.
>
>> #define XIVE_IRQ_FLAG_MASK_FW 0x08
>> #define XIVE_IRQ_FLAG_EOI_FW 0x10
>> #define XIVE_IRQ_FLAG_H_INT_ESB 0x20
>> diff --git a/arch/powerpc/kvm/book3s_xive_native.c b/arch/powerpc/kvm/book3s_xive_native.c
>> index 9b395381179d..170d1d04e1d1 100644
>> --- a/arch/powerpc/kvm/book3s_xive_native.c
>> +++ b/arch/powerpc/kvm/book3s_xive_native.c
>> @@ -37,9 +37,6 @@ static u8 xive_vm_esb_load(struct xive_irq_data *xd, u32 offset)
>> * ordering.
>> */
>>
>> - if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
>> - offset |= offset << 4;
>> -
>> val = in_be64(xd->eoi_mmio + offset);
>> return (u8)val;
>> }
>> diff --git a/arch/powerpc/kvm/book3s_xive_template.c b/arch/powerpc/kvm/book3s_xive_template.c
>> index 4ad3c0279458..ece36e024a8f 100644
>> --- a/arch/powerpc/kvm/book3s_xive_template.c
>> +++ b/arch/powerpc/kvm/book3s_xive_template.c
>> @@ -61,9 +61,6 @@ static u8 GLUE(X_PFX,esb_load)(struct xive_irq_data *xd, u32 offset)
>> if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
>> offset |= XIVE_ESB_LD_ST_MO;
>>
>> - if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
>> - offset |= offset << 4;
>> -
>> val =__x_readq(__x_eoi_page(xd) + offset);
>> #ifdef __LITTLE_ENDIAN__
>> val >>= 64-8;
>> diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
>> index 411cba12d73b..a9259470bf9f 100644
>> --- a/arch/powerpc/sysdev/xive/common.c
>> +++ b/arch/powerpc/sysdev/xive/common.c
>> @@ -200,10 +200,6 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
>> if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
>> offset |= XIVE_ESB_LD_ST_MO;
>>
>> - /* Handle HW errata */
>> - if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
>> - offset |= offset << 4;
>> -
>> if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
>> val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
>> else
>> @@ -214,10 +210,6 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
>>
>> static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
>> {
>> - /* Handle HW errata */
>> - if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
>> - offset |= offset << 4;
>> -
>> if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
>> xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
>> else
>> diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
>> index 5f1e5aed8ab4..0310783241b5 100644
>> --- a/arch/powerpc/sysdev/xive/native.c
>> +++ b/arch/powerpc/sysdev/xive/native.c
>> @@ -64,8 +64,6 @@ int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
>> data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
>> if (opal_flags & OPAL_XIVE_IRQ_LSI)
>> data->flags |= XIVE_IRQ_FLAG_LSI;
>> - if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
>> - data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
>> if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
>> data->flags |= XIVE_IRQ_FLAG_MASK_FW;
>> if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
>
^ permalink raw reply
* Re: [PATCH] cxl: Reduce scope for the variable “mm” in cxllib_get_PE_attributes()
From: Greg Kroah-Hartman @ 2020-12-10 14:47 UTC (permalink / raw)
To: Markus Elfring
Cc: Andrew Donnellan, Arnd Bergmann, kernel-janitors, LKML,
Frederic Barrat, linuxppc-dev
In-Reply-To: <5cee2b25-71e0-15aa-fba6-12211b8308aa@web.de>
On Thu, Dec 10, 2020 at 03:35:38PM +0100, Markus Elfring wrote:
> From: Markus Elfring <elfring@users.sourceforge.net>
> Date: Thu, 10 Dec 2020 14:14:07 +0100
>
> A local variable was used only within an if branch.
> Thus move the definition for the variable “mm” into the corresponding
> code block.
You did nothing here except add a checkpatch warning :(
dropped.
greg k-h
^ permalink raw reply
* [PATCH] cxl: Reduce scope for the variable “mm” in cxllib_get_PE_attributes()
From: Markus Elfring @ 2020-12-10 14:35 UTC (permalink / raw)
To: linuxppc-dev, Andrew Donnellan, Arnd Bergmann, Frederic Barrat,
Greg Kroah-Hartman
Cc: kernel-janitors, LKML
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Thu, 10 Dec 2020 14:14:07 +0100
A local variable was used only within an if branch.
Thus move the definition for the variable “mm” into the corresponding
code block.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/misc/cxl/cxllib.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/misc/cxl/cxllib.c b/drivers/misc/cxl/cxllib.c
index 2a1783f32254..53b919856426 100644
--- a/drivers/misc/cxl/cxllib.c
+++ b/drivers/misc/cxl/cxllib.c
@@ -170,8 +170,6 @@ int cxllib_get_PE_attributes(struct task_struct *task,
unsigned long translation_mode,
struct cxllib_pe_attributes *attr)
{
- struct mm_struct *mm = NULL;
-
if (translation_mode != CXL_TRANSLATED_MODE &&
translation_mode != CXL_REAL_MODE)
return -EINVAL;
@@ -182,7 +180,7 @@ int cxllib_get_PE_attributes(struct task_struct *task,
true);
attr->lpid = mfspr(SPRN_LPID);
if (task) {
- mm = get_task_mm(task);
+ struct mm_struct *mm = get_task_mm(task);
if (mm == NULL)
return -EINVAL;
/*
--
2.29.2
^ permalink raw reply related
* Re: [PATCH] cxl: Reduce scope for the variable “mm” in cxllib_get_PE_attributes()
From: Markus Elfring @ 2020-12-10 16:04 UTC (permalink / raw)
To: Greg Kroah-Hartman, linuxppc-dev
Cc: Frederic Barrat, kernel-janitors, Andrew Donnellan, Arnd Bergmann,
LKML
In-Reply-To: <X9I1GLYCkw/q/xMu@kroah.com>
>> A local variable was used only within an if branch.
>> Thus move the definition for the variable “mm” into the corresponding
>> code block.
>
> You did nothing here except add a checkpatch warning :(
elfring@Sonne:~/Projekte/Linux/next-patched> scripts/checkpatch.pl /home/elfring/Projekte/Bau/Linux/scripts/Coccinelle/tuning1/next/20201204/Flicken/0001-cxl-Reduce-scope-for-the-variable-mm-in-cxllib_get_P.patch
total: 0 errors, 0 warnings, 16 lines checked
Regards,
Markus
^ permalink raw reply
* [PATCH v2 05/13] powerpc/xive: Add a name to the IRQ domain
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
We hope one day to handle multiple irq_domain in the XIVE driver.
Start simple by setting the name using the DT node.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/sysdev/xive/xive-internal.h | 4 ++--
arch/powerpc/sysdev/xive/common.c | 10 +++++-----
arch/powerpc/sysdev/xive/native.c | 2 +-
arch/powerpc/sysdev/xive/spapr.c | 2 +-
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/sysdev/xive/xive-internal.h b/arch/powerpc/sysdev/xive/xive-internal.h
index d701af7fb48c..c07fadb9d264 100644
--- a/arch/powerpc/sysdev/xive/xive-internal.h
+++ b/arch/powerpc/sysdev/xive/xive-internal.h
@@ -63,8 +63,8 @@ struct xive_ops {
const char *name;
};
-bool xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 offset,
- u8 max_prio);
+bool xive_core_init(struct device_node *np, const struct xive_ops *ops,
+ void __iomem *area, u32 offset, u8 max_prio);
__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift);
int xive_core_debug_init(void);
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index 605238ca65e4..7314b87d0b45 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -1310,9 +1310,9 @@ static const struct irq_domain_ops xive_irq_domain_ops = {
.xlate = xive_irq_domain_xlate,
};
-static void __init xive_init_host(void)
+static void __init xive_init_host(struct device_node *np)
{
- xive_irq_domain = irq_domain_add_nomap(NULL, XIVE_MAX_IRQ,
+ xive_irq_domain = irq_domain_add_nomap(np, XIVE_MAX_IRQ,
&xive_irq_domain_ops, NULL);
if (WARN_ON(xive_irq_domain == NULL))
return;
@@ -1508,8 +1508,8 @@ void xive_shutdown(void)
xive_ops->shutdown();
}
-bool __init xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 offset,
- u8 max_prio)
+bool __init xive_core_init(struct device_node *np, const struct xive_ops *ops,
+ void __iomem *area, u32 offset, u8 max_prio)
{
xive_tima = area;
xive_tima_offset = offset;
@@ -1520,7 +1520,7 @@ bool __init xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 o
__xive_enabled = true;
pr_devel("Initializing host..\n");
- xive_init_host();
+ xive_init_host(np);
pr_devel("Initializing boot CPU..\n");
diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
index cb58ec7ce77a..c3182ec9ed65 100644
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -622,7 +622,7 @@ bool __init xive_native_init(void)
xive_native_setup_pools();
/* Initialize XIVE core with our backend */
- if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS,
+ if (!xive_core_init(np, &xive_native_ops, tima, TM_QW3_HV_PHYS,
max_prio)) {
opal_xive_reset(OPAL_XIVE_MODE_EMU);
return false;
diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
index 1e3674d7ea7b..6610e5149d5a 100644
--- a/arch/powerpc/sysdev/xive/spapr.c
+++ b/arch/powerpc/sysdev/xive/spapr.c
@@ -857,7 +857,7 @@ bool __init xive_spapr_init(void)
}
/* Initialize XIVE core with our backend */
- if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio))
+ if (!xive_core_init(np, &xive_spapr_ops, tima, TM_QW1_OS, max_prio))
return false;
pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
--
2.26.2
^ permalink raw reply related
* [PATCH v2 04/13] powerpc/xive: Use cpu_to_node() instead of ibm, chip-id property
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
The 'chip_id' field of the XIVE CPU structure is used to choose a
target for a source located on the same chip when possible. This field
is assigned on the PowerNV platform using the "ibm,chip-id" property
on pSeries under KVM when NUMA nodes are defined but it is undefined
under PowerVM. The XIVE source structure has a similar field
'src_chip' which is only assigned on the PowerNV platform.
cpu_to_node() returns a compatible value on all platforms, 0 being the
default node. It will also give us the opportunity to set the affinity
of a source on pSeries when we can localize them.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/sysdev/xive/common.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index ee375daf8114..605238ca65e4 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -1342,16 +1342,11 @@ static int xive_prepare_cpu(unsigned int cpu)
xc = per_cpu(xive_cpu, cpu);
if (!xc) {
- struct device_node *np;
-
xc = kzalloc_node(sizeof(struct xive_cpu),
GFP_KERNEL, cpu_to_node(cpu));
if (!xc)
return -ENOMEM;
- np = of_get_cpu_node(cpu, NULL);
- if (np)
- xc->chip_id = of_get_ibm_chip_id(np);
- of_node_put(np);
+ xc->chip_id = cpu_to_node(cpu);
xc->hw_ipi = XIVE_BAD_IRQ;
per_cpu(xive_cpu, cpu) = xc;
--
2.26.2
^ permalink raw reply related
* [PATCH v2 11/13] powerpc/xive: Simplify xive_do_source_eoi()
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
Previous patches removed the need of the first argument which was a
hack for Firwmware EOI. Remove it and flatten the routine which has
became simpler.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/sysdev/xive/common.c | 72 ++++++++++++++-----------------
1 file changed, 33 insertions(+), 39 deletions(-)
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index ed9bc49f45a7..b8e456da28aa 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -348,39 +348,40 @@ static void xive_do_queue_eoi(struct xive_cpu *xc)
* EOI an interrupt at the source. There are several methods
* to do this depending on the HW version and source type
*/
-static void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
+static void xive_do_source_eoi(struct xive_irq_data *xd)
{
+ u8 eoi_val;
+
xd->stale_p = false;
+
/* If the XIVE supports the new "store EOI facility, use it */
- if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
+ if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI) {
xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
- else {
- u8 eoi_val;
+ return;
+ }
- /*
- * Otherwise for EOI, we use the special MMIO that does
- * a clear of both P and Q and returns the old Q,
- * except for LSIs where we use the "EOI cycle" special
- * load.
- *
- * This allows us to then do a re-trigger if Q was set
- * rather than synthesizing an interrupt in software
- *
- * For LSIs the HW EOI cycle is used rather than PQ bits,
- * as they are automatically re-triggred in HW when still
- * pending.
- */
- if (xd->flags & XIVE_IRQ_FLAG_LSI)
- xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
- else {
- eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
- DBG_VERBOSE("eoi_val=%x\n", eoi_val);
-
- /* Re-trigger if needed */
- if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
- out_be64(xd->trig_mmio, 0);
- }
+ /*
+ * For LSIs, we use the "EOI cycle" special load rather than
+ * PQ bits, as they are automatically re-triggered in HW when
+ * still pending.
+ */
+ if (xd->flags & XIVE_IRQ_FLAG_LSI) {
+ xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
+ return;
}
+
+ /*
+ * Otherwise, we use the special MMIO that does a clear of
+ * both P and Q and returns the old Q. This allows us to then
+ * do a re-trigger if Q was set rather than synthesizing an
+ * interrupt in software
+ */
+ eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
+ DBG_VERBOSE("eoi_val=%x\n", eoi_val);
+
+ /* Re-trigger if needed */
+ if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
+ out_be64(xd->trig_mmio, 0);
}
/* irq_chip eoi callback, called with irq descriptor lock held */
@@ -398,7 +399,7 @@ static void xive_irq_eoi(struct irq_data *d)
*/
if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
!(xd->flags & XIVE_IRQ_FLAG_NO_EOI))
- xive_do_source_eoi(irqd_to_hwirq(d), xd);
+ xive_do_source_eoi(xd);
else
xd->stale_p = true;
@@ -788,14 +789,7 @@ static int xive_irq_retrigger(struct irq_data *d)
* 11, then perform an EOI.
*/
xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
-
- /*
- * Note: We pass "0" to the hw_irq argument in order to
- * avoid calling into the backend EOI code which we don't
- * want to do in the case of a re-trigger. Backends typically
- * only do EOI for LSIs anyway.
- */
- xive_do_source_eoi(0, xd);
+ xive_do_source_eoi(xd);
return 1;
}
@@ -910,7 +904,7 @@ static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
* while masked, the generic code will re-mask it anyway.
*/
if (!xd->saved_p)
- xive_do_source_eoi(hw_irq, xd);
+ xive_do_source_eoi(xd);
}
return 0;
@@ -1054,7 +1048,7 @@ static void xive_ipi_eoi(struct irq_data *d)
DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",
d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);
- xive_do_source_eoi(xc->hw_ipi, &xc->ipi_data);
+ xive_do_source_eoi(&xc->ipi_data);
xive_do_queue_eoi(xc);
}
@@ -1440,7 +1434,7 @@ static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
* still asserted. Otherwise do an MSI retrigger.
*/
if (xd->flags & XIVE_IRQ_FLAG_LSI)
- xive_do_source_eoi(irqd_to_hwirq(d), xd);
+ xive_do_source_eoi(xd);
else
xive_irq_retrigger(d);
--
2.26.2
^ permalink raw reply related
* [PATCH v2 01/13] KVM: PPC: Book3S HV: XIVE: Show detailed configuration in debug output
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
This is useful to track allocation of the HW resources on per guest
basis. Making sure IPIs are local to the chip of the vCPUs reduces
rerouting between interrupt controllers and gives better performance
in case of pinning. Checking the distribution of VP structures on the
chips also helps in reducing PowerBUS traffic.
Signed-off-by: Greg Kurz <groug@kaod.org>
[ clg: resurrected show_sources and reworked ouput ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/kvm/book3s_xive.h | 2 +
arch/powerpc/kvm/book3s_xive.c | 76 ++++++++++++++++++++++-----
arch/powerpc/kvm/book3s_xive_native.c | 21 ++++++--
3 files changed, 82 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_xive.h b/arch/powerpc/kvm/book3s_xive.h
index 382e3a56e789..d5d4fee7ac94 100644
--- a/arch/powerpc/kvm/book3s_xive.h
+++ b/arch/powerpc/kvm/book3s_xive.h
@@ -290,6 +290,8 @@ extern int (*__xive_vm_h_eoi)(struct kvm_vcpu *vcpu, unsigned long xirr);
*/
void kvmppc_xive_disable_vcpu_interrupts(struct kvm_vcpu *vcpu);
int kvmppc_xive_debug_show_queues(struct seq_file *m, struct kvm_vcpu *vcpu);
+void kvmppc_xive_debug_show_sources(struct seq_file *m,
+ struct kvmppc_xive_src_block *sb);
struct kvmppc_xive_src_block *kvmppc_xive_create_src_block(
struct kvmppc_xive *xive, int irq);
void kvmppc_xive_free_sources(struct kvmppc_xive_src_block *sb);
diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index a0ebc29f30b2..18a6b75a3bfd 100644
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -2125,9 +2125,8 @@ int kvmppc_xive_debug_show_queues(struct seq_file *m, struct kvm_vcpu *vcpu)
if (!q->qpage && !xc->esc_virq[i])
continue;
- seq_printf(m, " [q%d]: ", i);
-
if (q->qpage) {
+ seq_printf(m, " q[%d]: ", i);
idx = q->idx;
i0 = be32_to_cpup(q->qpage + idx);
idx = (idx + 1) & q->msk;
@@ -2141,16 +2140,54 @@ int kvmppc_xive_debug_show_queues(struct seq_file *m, struct kvm_vcpu *vcpu)
irq_data_get_irq_handler_data(d);
u64 pq = xive_vm_esb_load(xd, XIVE_ESB_GET);
- seq_printf(m, "E:%c%c I(%d:%llx:%llx)",
- (pq & XIVE_ESB_VAL_P) ? 'P' : 'p',
- (pq & XIVE_ESB_VAL_Q) ? 'Q' : 'q',
- xc->esc_virq[i], pq, xd->eoi_page);
+ seq_printf(m, " ESC %d %c%c EOI @%llx",
+ xc->esc_virq[i],
+ (pq & XIVE_ESB_VAL_P) ? 'P' : '-',
+ (pq & XIVE_ESB_VAL_Q) ? 'Q' : '-',
+ xd->eoi_page);
seq_puts(m, "\n");
}
}
return 0;
}
+void kvmppc_xive_debug_show_sources(struct seq_file *m,
+ struct kvmppc_xive_src_block *sb)
+{
+ int i;
+
+ seq_puts(m, " LISN HW/CHIP TYPE PQ EISN CPU/PRIO\n");
+ for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
+ struct kvmppc_xive_irq_state *state = &sb->irq_state[i];
+ struct xive_irq_data *xd;
+ u64 pq;
+ u32 hw_num;
+
+ if (!state->valid)
+ continue;
+
+ kvmppc_xive_select_irq(state, &hw_num, &xd);
+
+ pq = xive_vm_esb_load(xd, XIVE_ESB_GET);
+
+ seq_printf(m, "%08x %08x/%02x", state->number, hw_num,
+ xd->src_chip);
+ if (state->lsi)
+ seq_printf(m, " %cLSI", state->asserted ? '^' : ' ');
+ else
+ seq_puts(m, " MSI");
+
+ seq_printf(m, " %s %c%c %08x % 4d/%d",
+ state->ipi_number == hw_num ? "IPI" : " PT",
+ pq & XIVE_ESB_VAL_P ? 'P' : '-',
+ pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
+ state->eisn, state->act_server,
+ state->act_priority);
+
+ seq_puts(m, "\n");
+ }
+}
+
static int xive_debug_show(struct seq_file *m, void *private)
{
struct kvmppc_xive *xive = m->private;
@@ -2171,7 +2208,7 @@ static int xive_debug_show(struct seq_file *m, void *private)
if (!kvm)
return 0;
- seq_printf(m, "=========\nVCPU state\n=========\n");
+ seq_puts(m, "=========\nVCPU state\n=========\n");
kvm_for_each_vcpu(i, vcpu, kvm) {
struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
@@ -2179,11 +2216,12 @@ static int xive_debug_show(struct seq_file *m, void *private)
if (!xc)
continue;
- seq_printf(m, "cpu server %#x VP:%#x CPPR:%#x HWCPPR:%#x"
- " MFRR:%#x PEND:%#x h_xirr: R=%lld V=%lld\n",
- xc->server_num, xc->vp_id, xc->cppr, xc->hw_cppr,
- xc->mfrr, xc->pending,
- xc->stat_rm_h_xirr, xc->stat_vm_h_xirr);
+ seq_printf(m, "VCPU %d: VP:%#x/%02x\n"
+ " CPPR:%#x HWCPPR:%#x MFRR:%#x PEND:%#x h_xirr: R=%lld V=%lld\n",
+ xc->server_num, xc->vp_id, xc->vp_chip_id,
+ xc->cppr, xc->hw_cppr,
+ xc->mfrr, xc->pending,
+ xc->stat_rm_h_xirr, xc->stat_vm_h_xirr);
kvmppc_xive_debug_show_queues(m, vcpu);
@@ -2199,13 +2237,25 @@ static int xive_debug_show(struct seq_file *m, void *private)
t_vm_h_ipi += xc->stat_vm_h_ipi;
}
- seq_printf(m, "Hcalls totals\n");
+ seq_puts(m, "Hcalls totals\n");
seq_printf(m, " H_XIRR R=%10lld V=%10lld\n", t_rm_h_xirr, t_vm_h_xirr);
seq_printf(m, " H_IPOLL R=%10lld V=%10lld\n", t_rm_h_ipoll, t_vm_h_ipoll);
seq_printf(m, " H_CPPR R=%10lld V=%10lld\n", t_rm_h_cppr, t_vm_h_cppr);
seq_printf(m, " H_EOI R=%10lld V=%10lld\n", t_rm_h_eoi, t_vm_h_eoi);
seq_printf(m, " H_IPI R=%10lld V=%10lld\n", t_rm_h_ipi, t_vm_h_ipi);
+ seq_puts(m, "=========\nSources\n=========\n");
+
+ for (i = 0; i <= xive->max_sbid; i++) {
+ struct kvmppc_xive_src_block *sb = xive->src_blocks[i];
+
+ if (sb) {
+ arch_spin_lock(&sb->lock);
+ kvmppc_xive_debug_show_sources(m, sb);
+ arch_spin_unlock(&sb->lock);
+ }
+ }
+
return 0;
}
diff --git a/arch/powerpc/kvm/book3s_xive_native.c b/arch/powerpc/kvm/book3s_xive_native.c
index 6aaaa4bedaaf..9b395381179d 100644
--- a/arch/powerpc/kvm/book3s_xive_native.c
+++ b/arch/powerpc/kvm/book3s_xive_native.c
@@ -1257,18 +1257,31 @@ static int xive_native_debug_show(struct seq_file *m, void *private)
if (!xc)
continue;
- seq_printf(m, "cpu server %#x VP=%#x NSR=%02x CPPR=%02x IBP=%02x PIPR=%02x w01=%016llx w2=%08x\n",
- xc->server_num, xc->vp_id,
+ seq_printf(m, "VCPU %d: VP=%#x/%02x\n"
+ " NSR=%02x CPPR=%02x IBP=%02x PIPR=%02x w01=%016llx w2=%08x\n",
+ xc->server_num, xc->vp_id, xc->vp_chip_id,
vcpu->arch.xive_saved_state.nsr,
vcpu->arch.xive_saved_state.cppr,
vcpu->arch.xive_saved_state.ipb,
vcpu->arch.xive_saved_state.pipr,
- vcpu->arch.xive_saved_state.w01,
- (u32) vcpu->arch.xive_cam_word);
+ be64_to_cpu(vcpu->arch.xive_saved_state.w01),
+ be32_to_cpu(vcpu->arch.xive_cam_word));
kvmppc_xive_debug_show_queues(m, vcpu);
}
+ seq_puts(m, "=========\nSources\n=========\n");
+
+ for (i = 0; i <= xive->max_sbid; i++) {
+ struct kvmppc_xive_src_block *sb = xive->src_blocks[i];
+
+ if (sb) {
+ arch_spin_lock(&sb->lock);
+ kvmppc_xive_debug_show_sources(m, sb);
+ arch_spin_unlock(&sb->lock);
+ }
+ }
+
return 0;
}
--
2.26.2
^ permalink raw reply related
* [PATCH v2 12/13] powerpc/xive: Improve error reporting of OPAL calls
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
Introduce a vp_err() macro to standardize error reporting.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/sysdev/xive/native.c | 28 ++++++++++++++++------------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
index e91519c42463..05a800a3104e 100644
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -122,6 +122,8 @@ static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
return rc == 0 ? 0 : -ENXIO;
}
+#define vp_err(vp, fmt, ...) pr_err("VP[0x%x]: " fmt, vp, ##__VA_ARGS__)
+
/* This can be called multiple time to change a queue configuration */
int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
__be32 *qpage, u32 order, bool can_escalate)
@@ -149,7 +151,7 @@ int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
&esc_irq_be,
NULL);
if (rc) {
- pr_err("Error %lld getting queue info prio %d\n", rc, prio);
+ vp_err(vp_id, "Failed to get queue %d info : %lld\n", prio, rc);
rc = -EIO;
goto fail;
}
@@ -172,7 +174,7 @@ int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
msleep(OPAL_BUSY_DELAY_MS);
}
if (rc) {
- pr_err("Error %lld setting queue for prio %d\n", rc, prio);
+ vp_err(vp_id, "Failed to set queue %d info: %lld\n", prio, rc);
rc = -EIO;
} else {
/*
@@ -199,7 +201,7 @@ static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
msleep(OPAL_BUSY_DELAY_MS);
}
if (rc)
- pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
+ vp_err(vp_id, "Failed to disable queue %d : %lld\n", prio, rc);
}
void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
@@ -698,6 +700,8 @@ int xive_native_enable_vp(u32 vp_id, bool single_escalation)
break;
msleep(OPAL_BUSY_DELAY_MS);
}
+ if (rc)
+ vp_err(vp_id, "Failed to enable VP : %lld\n", rc);
return rc ? -EIO : 0;
}
EXPORT_SYMBOL_GPL(xive_native_enable_vp);
@@ -712,6 +716,8 @@ int xive_native_disable_vp(u32 vp_id)
break;
msleep(OPAL_BUSY_DELAY_MS);
}
+ if (rc)
+ vp_err(vp_id, "Failed to disable VP : %lld\n", rc);
return rc ? -EIO : 0;
}
EXPORT_SYMBOL_GPL(xive_native_disable_vp);
@@ -723,8 +729,10 @@ int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id)
s64 rc;
rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
- if (rc)
+ if (rc) {
+ vp_err(vp_id, "Failed to get VP info : %lld\n", rc);
return -EIO;
+ }
*out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
*out_chip_id = be32_to_cpu(vp_chip_id_be);
@@ -755,8 +763,7 @@ int xive_native_get_queue_info(u32 vp_id, u32 prio,
rc = opal_xive_get_queue_info(vp_id, prio, &qpage, &qsize,
&qeoi_page, &escalate_irq, &qflags);
if (rc) {
- pr_err("OPAL failed to get queue info for VCPU %d/%d : %lld\n",
- vp_id, prio, rc);
+ vp_err(vp_id, "failed to get queue %d info : %lld\n", prio, rc);
return -EIO;
}
@@ -784,8 +791,7 @@ int xive_native_get_queue_state(u32 vp_id, u32 prio, u32 *qtoggle, u32 *qindex)
rc = opal_xive_get_queue_state(vp_id, prio, &opal_qtoggle,
&opal_qindex);
if (rc) {
- pr_err("OPAL failed to get queue state for VCPU %d/%d : %lld\n",
- vp_id, prio, rc);
+ vp_err(vp_id, "failed to get queue %d state : %lld\n", prio, rc);
return -EIO;
}
@@ -804,8 +810,7 @@ int xive_native_set_queue_state(u32 vp_id, u32 prio, u32 qtoggle, u32 qindex)
rc = opal_xive_set_queue_state(vp_id, prio, qtoggle, qindex);
if (rc) {
- pr_err("OPAL failed to set queue state for VCPU %d/%d : %lld\n",
- vp_id, prio, rc);
+ vp_err(vp_id, "failed to set queue %d state : %lld\n", prio, rc);
return -EIO;
}
@@ -827,8 +832,7 @@ int xive_native_get_vp_state(u32 vp_id, u64 *out_state)
rc = opal_xive_get_vp_state(vp_id, &state);
if (rc) {
- pr_err("OPAL failed to get vp state for VCPU %d : %lld\n",
- vp_id, rc);
+ vp_err(vp_id, "failed to get vp state : %lld\n", rc);
return -EIO;
}
--
2.26.2
^ permalink raw reply related
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