* Re: [PATCH v2] perf vendor events: Initial json/events list for power10 platform
From: Michael Ellerman @ 2021-04-19 12:38 UTC (permalink / raw)
To: Kajol Jain, acme
Cc: ravi.bangoria, atrajeev, kjain, linuxppc-dev, linux-kernel,
linux-perf-users, maddy, pc, jolsa
In-Reply-To: <20210419112001.71466-1-kjain@linux.ibm.com>
Kajol Jain <kjain@linux.ibm.com> writes:
> Patch adds initial json/events for POWER10.
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
cheers
> Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
> Tested-by: Paul A. Clarke <pc@us.ibm.com>
> Reviewed-by: Paul A. Clarke <pc@us.ibm.com>
> ---
> .../perf/pmu-events/arch/powerpc/mapfile.csv | 1 +
> .../arch/powerpc/power10/cache.json | 47 +++
> .../arch/powerpc/power10/floating_point.json | 7 +
> .../arch/powerpc/power10/frontend.json | 217 +++++++++++++
> .../arch/powerpc/power10/locks.json | 12 +
> .../arch/powerpc/power10/marked.json | 147 +++++++++
> .../arch/powerpc/power10/memory.json | 192 +++++++++++
> .../arch/powerpc/power10/others.json | 297 ++++++++++++++++++
> .../arch/powerpc/power10/pipeline.json | 297 ++++++++++++++++++
> .../pmu-events/arch/powerpc/power10/pmc.json | 22 ++
> .../arch/powerpc/power10/translation.json | 57 ++++
> 11 files changed, 1296 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/cache.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/frontend.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/locks.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/marked.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/memory.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/others.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/pmc.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/translation.json
>
> ---
> Changelog:
> v1 -> v2
> - Removed inconsistencies in "BriefDescription" field and make sure
> it will end with period without any space at the end.
> Suggested by : Paul A. Clarke
> - Added Tested-by and Reviewed-by tag.
> ---
> diff --git a/tools/perf/pmu-events/arch/powerpc/mapfile.csv b/tools/perf/pmu-events/arch/powerpc/mapfile.csv
> index 229150e7ab7d..4abdfc3f9692 100644
> --- a/tools/perf/pmu-events/arch/powerpc/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/powerpc/mapfile.csv
> @@ -15,3 +15,4 @@
> # Power8 entries
> 004[bcd][[:xdigit:]]{4},1,power8,core
> 004e[[:xdigit:]]{4},1,power9,core
> +0080[[:xdigit:]]{4},1,power10,core
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/cache.json b/tools/perf/pmu-events/arch/powerpc/power10/cache.json
> new file mode 100644
> index 000000000000..95e33531fbc6
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/cache.json
> @@ -0,0 +1,47 @@
> +[
> + {
> + "EventCode": "1003C",
> + "EventName": "PM_EXEC_STALL_DMISS_L2L3",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
> + },
> + {
> + "EventCode": "34056",
> + "EventName": "PM_EXEC_STALL_LOAD_FINISH",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the NTF instruction merged with another load in the LMQ."
> + },
> + {
> + "EventCode": "3006C",
> + "EventName": "PM_RUN_CYC_SMT2_MODE",
> + "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
> + },
> + {
> + "EventCode": "300F4",
> + "EventName": "PM_RUN_INST_CMPL_CONC",
> + "BriefDescription": "PowerPC instructions completed by this thread when all threads in the core had the run-latch set."
> + },
> + {
> + "EventCode": "4C016",
> + "EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."
> + },
> + {
> + "EventCode": "4D014",
> + "EventName": "PM_EXEC_STALL_LOAD",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit."
> + },
> + {
> + "EventCode": "4D016",
> + "EventName": "PM_EXEC_STALL_PTESYNC",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit."
> + },
> + {
> + "EventCode": "401EA",
> + "EventName": "PM_THRESH_EXC_128",
> + "BriefDescription": "Threshold counter exceeded a value of 128."
> + },
> + {
> + "EventCode": "400F6",
> + "EventName": "PM_BR_MPRED_CMPL",
> + "BriefDescription": "A mispredicted branch completed. Includes direction and target."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json b/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
> new file mode 100644
> index 000000000000..e9b92f282d3c
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
> @@ -0,0 +1,7 @@
> +[
> + {
> + "EventCode": "4016E",
> + "EventName": "PM_THRESH_NOT_MET",
> + "BriefDescription": "Threshold counter did not meet threshold."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/frontend.json b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json
> new file mode 100644
> index 000000000000..aebaf94bfdfe
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json
> @@ -0,0 +1,217 @@
> +[
> + {
> + "EventCode": "10004",
> + "EventName": "PM_EXEC_STALL_TRANSLATION",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or ERAT miss and waited for it to resolve."
> + },
> + {
> + "EventCode": "10010",
> + "EventName": "PM_PMC4_OVERFLOW",
> + "BriefDescription": "The event selected for PMC4 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "10020",
> + "EventName": "PM_PMC4_REWIND",
> + "BriefDescription": "The speculative event selected for PMC4 rewinds and the counter for PMC4 is not charged."
> + },
> + {
> + "EventCode": "10038",
> + "EventName": "PM_DISP_STALL_TRANSLATION",
> + "BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling a translation miss."
> + },
> + {
> + "EventCode": "1003A",
> + "EventName": "PM_DISP_STALL_BR_MPRED_IC_L2",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict."
> + },
> + {
> + "EventCode": "1E050",
> + "EventName": "PM_DISP_STALL_HELD_STF_MAPPER_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR."
> + },
> + {
> + "EventCode": "1F054",
> + "EventName": "PM_DTLB_HIT",
> + "BriefDescription": "The PTE required by the instruction was resident in the TLB (data TLB access). When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefetch. Applies to both HPT and RPT."
> + },
> + {
> + "EventCode": "101E8",
> + "EventName": "PM_THRESH_EXC_256",
> + "BriefDescription": "Threshold counter exceeded a count of 256."
> + },
> + {
> + "EventCode": "101EC",
> + "EventName": "PM_THRESH_MET",
> + "BriefDescription": "Threshold exceeded."
> + },
> + {
> + "EventCode": "100F2",
> + "EventName": "PM_1PLUS_PPC_CMPL",
> + "BriefDescription": "Cycles in which at least one instruction is completed by this thread."
> + },
> + {
> + "EventCode": "100F6",
> + "EventName": "PM_IERAT_MISS",
> + "BriefDescription": "IERAT Reloaded to satisfy an IERAT miss. All page sizes are counted by this event."
> + },
> + {
> + "EventCode": "100F8",
> + "EventName": "PM_DISP_STALL_CYC",
> + "BriefDescription": "Cycles the ICT has no itags assigned to this thread (no instructions were dispatched during these cycles)."
> + },
> + {
> + "EventCode": "20114",
> + "EventName": "PM_MRK_L2_RC_DISP",
> + "BriefDescription": "Marked instruction RC dispatched in L2."
> + },
> + {
> + "EventCode": "2C010",
> + "EventName": "PM_EXEC_STALL_LSU",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Load Store Unit. This does not include simple fixed point instructions."
> + },
> + {
> + "EventCode": "2C016",
> + "EventName": "PM_DISP_STALL_IERAT_ONLY_MISS",
> + "BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT miss."
> + },
> + {
> + "EventCode": "2C01E",
> + "EventName": "PM_DISP_STALL_BR_MPRED_IC_L3",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3 after suffering a branch mispredict."
> + },
> + {
> + "EventCode": "2D01A",
> + "EventName": "PM_DISP_STALL_IC_MISS",
> + "BriefDescription": "Cycles when dispatch was stalled for this thread due to an Icache Miss."
> + },
> + {
> + "EventCode": "2D01C",
> + "EventName": "PM_CMPL_STALL_STCX",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for resolution from the nest before completing."
> + },
> + {
> + "EventCode": "2E018",
> + "EventName": "PM_DISP_STALL_FETCH",
> + "BriefDescription": "Cycles when dispatch was stalled for this thread because Fetch was being held."
> + },
> + {
> + "EventCode": "2E01A",
> + "EventName": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the XVFC mapper/SRB was full."
> + },
> + {
> + "EventCode": "2C142",
> + "EventName": "PM_MRK_XFER_FROM_SRC_PMC2",
> + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "24050",
> + "EventName": "PM_IOPS_DISP",
> + "BriefDescription": "Internal Operations dispatched. PM_IOPS_DISP / PM_INST_DISP will show the average number of internal operations per PowerPC instruction."
> + },
> + {
> + "EventCode": "2405E",
> + "EventName": "PM_ISSUE_CANCEL",
> + "BriefDescription": "An instruction issued and the issue was later cancelled. Only one cancel per PowerPC instruction."
> + },
> + {
> + "EventCode": "200FA",
> + "EventName": "PM_BR_TAKEN_CMPL",
> + "BriefDescription": "Branch Taken instruction completed."
> + },
> + {
> + "EventCode": "30012",
> + "EventName": "PM_FLUSH_COMPLETION",
> + "BriefDescription": "The instruction that was next to complete (oldest in the pipeline) did not complete because it suffered a flush."
> + },
> + {
> + "EventCode": "30014",
> + "EventName": "PM_EXEC_STALL_STORE",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store instruction executing in the Load Store Unit."
> + },
> + {
> + "EventCode": "30018",
> + "EventName": "PM_DISP_STALL_HELD_SCOREBOARD_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."
> + },
> + {
> + "EventCode": "30026",
> + "EventName": "PM_EXEC_STALL_STORE_MISS",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store whose cache line was not resident in the L1 and was waiting for allocation of the missing line into the L1."
> + },
> + {
> + "EventCode": "3012A",
> + "EventName": "PM_MRK_L2_RC_DONE",
> + "BriefDescription": "L2 RC machine completed the transaction for the marked instruction."
> + },
> + {
> + "EventCode": "3F046",
> + "EventName": "PM_ITLB_HIT_1G",
> + "BriefDescription": "Instruction TLB hit (IERAT reload) page size 1G, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "34058",
> + "EventName": "PM_DISP_STALL_BR_MPRED_ICMISS",
> + "BriefDescription": "Cycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss."
> + },
> + {
> + "EventCode": "3D05C",
> + "EventName": "PM_DISP_STALL_HELD_RENAME_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC."
> + },
> + {
> + "EventCode": "3E052",
> + "EventName": "PM_DISP_STALL_IC_L3",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3."
> + },
> + {
> + "EventCode": "3E054",
> + "EventName": "PM_LD_MISS_L1",
> + "BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
> + },
> + {
> + "EventCode": "301EA",
> + "EventName": "PM_THRESH_EXC_1024",
> + "BriefDescription": "Threshold counter exceeded a value of 1024."
> + },
> + {
> + "EventCode": "300FA",
> + "EventName": "PM_INST_FROM_L3MISS",
> + "BriefDescription": "The processor's instruction cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."
> + },
> + {
> + "EventCode": "40006",
> + "EventName": "PM_ISSUE_KILL",
> + "BriefDescription": "Cycles in which an instruction or group of instructions were cancelled after being issued. This event increments once per occurrence, regardless of how many instructions are included in the issue group."
> + },
> + {
> + "EventCode": "40116",
> + "EventName": "PM_MRK_LARX_FIN",
> + "BriefDescription": "Marked load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "4C010",
> + "EventName": "PM_DISP_STALL_BR_MPRED_IC_L3MISS",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a mispredicted branch."
> + },
> + {
> + "EventCode": "4D01E",
> + "EventName": "PM_DISP_STALL_BR_MPRED",
> + "BriefDescription": "Cycles when dispatch was stalled for this thread due to a mispredicted branch."
> + },
> + {
> + "EventCode": "4E010",
> + "EventName": "PM_DISP_STALL_IC_L3MISS",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from any source beyond the local L3."
> + },
> + {
> + "EventCode": "4E01A",
> + "EventName": "PM_DISP_STALL_HELD_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any reason."
> + },
> + {
> + "EventCode": "44056",
> + "EventName": "PM_VECTOR_ST_CMPL",
> + "BriefDescription": "Vector store instructions completed."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/locks.json b/tools/perf/pmu-events/arch/powerpc/power10/locks.json
> new file mode 100644
> index 000000000000..fa81b470d21f
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/locks.json
> @@ -0,0 +1,12 @@
> +[
> + {
> + "EventCode": "1E058",
> + "EventName": "PM_STCX_FAIL_FIN",
> + "BriefDescription": "Conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "4E050",
> + "EventName": "PM_STCX_PASS_FIN",
> + "BriefDescription": "Conditional store instruction (STCX) passed. LARX and STCX are instructions used to acquire a lock."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/marked.json b/tools/perf/pmu-events/arch/powerpc/power10/marked.json
> new file mode 100644
> index 000000000000..ffe38525b18b
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/marked.json
> @@ -0,0 +1,147 @@
> +[
> + {
> + "EventCode": "1002C",
> + "EventName": "PM_LD_PREFETCH_CACHE_LINE_MISS",
> + "BriefDescription": "The L1 cache was reloaded with a line that fulfills a prefetch request."
> + },
> + {
> + "EventCode": "10132",
> + "EventName": "PM_MRK_INST_ISSUED",
> + "BriefDescription": "Marked instruction issued. Note that stores always get issued twice, the address gets issued to the LSU and the data gets issued to the VSU. Also, issues can sometimes get killed/cancelled and cause multiple sequential issues for the same instruction."
> + },
> + {
> + "EventCode": "101E0",
> + "EventName": "PM_MRK_INST_DISP",
> + "BriefDescription": "The thread has dispatched a randomly sampled marked instruction."
> + },
> + {
> + "EventCode": "101E2",
> + "EventName": "PM_MRK_BR_TAKEN_CMPL",
> + "BriefDescription": "Marked Branch Taken instruction completed."
> + },
> + {
> + "EventCode": "20112",
> + "EventName": "PM_MRK_NTF_FIN",
> + "BriefDescription": "The marked instruction became the oldest in the pipeline before it finished. It excludes instructions that finish at dispatch."
> + },
> + {
> + "EventCode": "2C01C",
> + "EventName": "PM_EXEC_STALL_DMISS_OFF_CHIP",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a remote chip."
> + },
> + {
> + "EventCode": "20138",
> + "EventName": "PM_MRK_ST_NEST",
> + "BriefDescription": "A store has been sampled/marked and is at the point of execution where it has completed in the core and can no longer be flushed. At this point the store is sent to the L2."
> + },
> + {
> + "EventCode": "2013A",
> + "EventName": "PM_MRK_BRU_FIN",
> + "BriefDescription": "Marked Branch instruction finished."
> + },
> + {
> + "EventCode": "2C144",
> + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC2",
> + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[15:27]."
> + },
> + {
> + "EventCode": "24156",
> + "EventName": "PM_MRK_STCX_FIN",
> + "BriefDescription": "Marked conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "24158",
> + "EventName": "PM_MRK_INST",
> + "BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens."
> + },
> + {
> + "EventCode": "2415C",
> + "EventName": "PM_MRK_BR_CMPL",
> + "BriefDescription": "A marked branch completed. All branches are included."
> + },
> + {
> + "EventCode": "200FD",
> + "EventName": "PM_L1_ICACHE_MISS",
> + "BriefDescription": "Demand iCache Miss."
> + },
> + {
> + "EventCode": "30130",
> + "EventName": "PM_MRK_INST_FIN",
> + "BriefDescription": "marked instruction finished. Excludes instructions that finish at dispatch. Note that stores always finish twice since the address gets issued to the LSU and the data gets issued to the VSU."
> + },
> + {
> + "EventCode": "34146",
> + "EventName": "PM_MRK_LD_CMPL",
> + "BriefDescription": "Marked loads completed."
> + },
> + {
> + "EventCode": "3E158",
> + "EventName": "PM_MRK_STCX_FAIL",
> + "BriefDescription": "Marked conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "3E15A",
> + "EventName": "PM_MRK_ST_FIN",
> + "BriefDescription": "The marked instruction was a store of any kind."
> + },
> + {
> + "EventCode": "30068",
> + "EventName": "PM_L1_ICACHE_RELOADED_PREF",
> + "BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)."
> + },
> + {
> + "EventCode": "301E4",
> + "EventName": "PM_MRK_BR_MPRED_CMPL",
> + "BriefDescription": "Marked Branch Mispredicted. Includes direction and target."
> + },
> + {
> + "EventCode": "300F6",
> + "EventName": "PM_LD_DEMAND_MISS_L1",
> + "BriefDescription": "The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish."
> + },
> + {
> + "EventCode": "300FE",
> + "EventName": "PM_DATA_FROM_L3MISS",
> + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."
> + },
> + {
> + "EventCode": "40012",
> + "EventName": "PM_L1_ICACHE_RELOADED_ALL",
> + "BriefDescription": "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch."
> + },
> + {
> + "EventCode": "40134",
> + "EventName": "PM_MRK_INST_TIMEO",
> + "BriefDescription": "Marked instruction finish timeout (instruction was lost)."
> + },
> + {
> + "EventCode": "4003C",
> + "EventName": "PM_DISP_STALL_HELD_SYNC_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch."
> + },
> + {
> + "EventCode": "4505A",
> + "EventName": "PM_SP_FLOP_CMPL",
> + "BriefDescription": "Single Precision floating point instructions completed."
> + },
> + {
> + "EventCode": "4D058",
> + "EventName": "PM_VECTOR_FLOP_CMPL",
> + "BriefDescription": "Vector floating point instructions completed."
> + },
> + {
> + "EventCode": "4D05A",
> + "EventName": "PM_NON_MATH_FLOP_CMPL",
> + "BriefDescription": "Non Math instructions completed."
> + },
> + {
> + "EventCode": "401E0",
> + "EventName": "PM_MRK_INST_CMPL",
> + "BriefDescription": "marked instruction completed."
> + },
> + {
> + "EventCode": "400FE",
> + "EventName": "PM_DATA_FROM_MEMORY",
> + "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/memory.json b/tools/perf/pmu-events/arch/powerpc/power10/memory.json
> new file mode 100644
> index 000000000000..6e47b96e2d66
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/memory.json
> @@ -0,0 +1,192 @@
> +[
> + {
> + "EventCode": "1000A",
> + "EventName": "PM_PMC3_REWIND",
> + "BriefDescription": "The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged."
> + },
> + {
> + "EventCode": "1C040",
> + "EventName": "PM_XFER_FROM_SRC_PMC1",
> + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "1C142",
> + "EventName": "PM_MRK_XFER_FROM_SRC_PMC1",
> + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "1C144",
> + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1",
> + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]."
> + },
> + {
> + "EventCode": "1C056",
> + "EventName": "PM_DERAT_MISS_4K",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "1C058",
> + "EventName": "PM_DTLB_MISS_16G",
> + "BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "1C05C",
> + "EventName": "PM_DTLB_MISS_2M",
> + "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "1E056",
> + "EventName": "PM_EXEC_STALL_STORE_PIPE",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions."
> + },
> + {
> + "EventCode": "1F150",
> + "EventName": "PM_MRK_ST_L2_CYC",
> + "BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion."
> + },
> + {
> + "EventCode": "10062",
> + "EventName": "PM_LD_L3MISS_PEND_CYC",
> + "BriefDescription": "Cycles L3 miss was pending for this thread."
> + },
> + {
> + "EventCode": "20010",
> + "EventName": "PM_PMC1_OVERFLOW",
> + "BriefDescription": "The event selected for PMC1 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "2001A",
> + "EventName": "PM_ITLB_HIT",
> + "BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "2003E",
> + "EventName": "PM_PTESYNC_FIN",
> + "BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time."
> + },
> + {
> + "EventCode": "2C040",
> + "EventName": "PM_XFER_FROM_SRC_PMC2",
> + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "2C054",
> + "EventName": "PM_DERAT_MISS_64K",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "2C056",
> + "EventName": "PM_DTLB_MISS_4K",
> + "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "2D154",
> + "EventName": "PM_MRK_DERAT_MISS_64K",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "200F6",
> + "EventName": "PM_DERAT_MISS",
> + "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "3000A",
> + "EventName": "PM_DISP_STALL_ITLB_MISS",
> + "BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction TLB miss."
> + },
> + {
> + "EventCode": "30016",
> + "EventName": "PM_EXEC_STALL_DERAT_DTLB_MISS",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve."
> + },
> + {
> + "EventCode": "3C040",
> + "EventName": "PM_XFER_FROM_SRC_PMC3",
> + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "3C142",
> + "EventName": "PM_MRK_XFER_FROM_SRC_PMC3",
> + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "3C144",
> + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC3",
> + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]."
> + },
> + {
> + "EventCode": "3C054",
> + "EventName": "PM_DERAT_MISS_16M",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "3C056",
> + "EventName": "PM_DTLB_MISS_64K",
> + "BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "3C058",
> + "EventName": "PM_LARX_FIN",
> + "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "301E2",
> + "EventName": "PM_MRK_ST_CMPL",
> + "BriefDescription": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores."
> + },
> + {
> + "EventCode": "300FC",
> + "EventName": "PM_DTLB_MISS",
> + "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity."
> + },
> + {
> + "EventCode": "4D02C",
> + "EventName": "PM_PMC1_REWIND",
> + "BriefDescription": "The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged."
> + },
> + {
> + "EventCode": "4003E",
> + "EventName": "PM_LD_CMPL",
> + "BriefDescription": "Loads completed."
> + },
> + {
> + "EventCode": "4C040",
> + "EventName": "PM_XFER_FROM_SRC_PMC4",
> + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "4C142",
> + "EventName": "PM_MRK_XFER_FROM_SRC_PMC4",
> + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "4C144",
> + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC4",
> + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]."
> + },
> + {
> + "EventCode": "4C056",
> + "EventName": "PM_DTLB_MISS_16M",
> + "BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "4C05A",
> + "EventName": "PM_DTLB_MISS_1G",
> + "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "4C15E",
> + "EventName": "PM_MRK_DTLB_MISS_64K",
> + "BriefDescription": "Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "4D056",
> + "EventName": "PM_NON_FMA_FLOP_CMPL",
> + "BriefDescription": "Non FMA instruction completed."
> + },
> + {
> + "EventCode": "40164",
> + "EventName": "PM_MRK_DERAT_MISS_2M",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/others.json b/tools/perf/pmu-events/arch/powerpc/power10/others.json
> new file mode 100644
> index 000000000000..2992f7961134
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/others.json
> @@ -0,0 +1,297 @@
> +[
> + {
> + "EventCode": "10016",
> + "EventName": "PM_VSU0_ISSUE",
> + "BriefDescription": "VSU instructions issued to VSU pipe 0."
> + },
> + {
> + "EventCode": "1001C",
> + "EventName": "PM_ULTRAVISOR_INST_CMPL",
> + "BriefDescription": "PowerPC instructions that completed while the thread was in ultravisor state."
> + },
> + {
> + "EventCode": "100F0",
> + "EventName": "PM_CYC",
> + "BriefDescription": "Processor cycles."
> + },
> + {
> + "EventCode": "10134",
> + "EventName": "PM_MRK_ST_DONE_L2",
> + "BriefDescription": "Marked stores completed in L2 (RC machine done)."
> + },
> + {
> + "EventCode": "1505E",
> + "EventName": "PM_LD_HIT_L1",
> + "BriefDescription": "Loads that finished without experiencing an L1 miss."
> + },
> + {
> + "EventCode": "1D05E",
> + "EventName": "PM_DISP_STALL_HELD_HALT_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of power management."
> + },
> + {
> + "EventCode": "1E054",
> + "EventName": "PM_EXEC_STALL_DMISS_L21_L31",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip."
> + },
> + {
> + "EventCode": "1E05A",
> + "EventName": "PM_CMPL_STALL_LWSYNC",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting to complete."
> + },
> + {
> + "EventCode": "1F056",
> + "EventName": "PM_DISP_SS0_2_INSTR_CYC",
> + "BriefDescription": "Cycles in which Superslice 0 dispatches either 1 or 2 instructions."
> + },
> + {
> + "EventCode": "1F15C",
> + "EventName": "PM_MRK_STCX_L2_CYC",
> + "BriefDescription": "Cycles spent in the nest portion of a marked Stcx instruction. It starts counting when the operation starts to drain to the L2 and it stops counting when the instruction retires from the Instruction Completion Table (ICT) in the Instruction Sequencing Unit (ISU)."
> + },
> + {
> + "EventCode": "10066",
> + "EventName": "PM_ADJUNCT_CYC",
> + "BriefDescription": "Cycles in which the thread is in Adjunct state. MSR[S HV PR] bits = 011."
> + },
> + {
> + "EventCode": "101E4",
> + "EventName": "PM_MRK_L1_ICACHE_MISS",
> + "BriefDescription": "Marked Instruction suffered an icache Miss."
> + },
> + {
> + "EventCode": "101EA",
> + "EventName": "PM_MRK_L1_RELOAD_VALID",
> + "BriefDescription": "Marked demand reload."
> + },
> + {
> + "EventCode": "100F4",
> + "EventName": "PM_FLOP_CMPL",
> + "BriefDescription": "Floating Point Operations Completed. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1|2|4|8_FLOP_CMPL events to count flops."
> + },
> + {
> + "EventCode": "100FA",
> + "EventName": "PM_RUN_LATCH_ANY_THREAD_CYC",
> + "BriefDescription": "Cycles when at least one thread has the run latch set."
> + },
> + {
> + "EventCode": "100FC",
> + "EventName": "PM_LD_REF_L1",
> + "BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included."
> + },
> + {
> + "EventCode": "20006",
> + "EventName": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue."
> + },
> + {
> + "EventCode": "2000C",
> + "EventName": "PM_RUN_LATCH_ALL_THREADS_CYC",
> + "BriefDescription": "Cycles when the run latch is set for all threads."
> + },
> + {
> + "EventCode": "2E010",
> + "EventName": "PM_ADJUNCT_INST_CMPL",
> + "BriefDescription": "PowerPC instructions that completed while the thread is in Adjunct state."
> + },
> + {
> + "EventCode": "2E014",
> + "EventName": "PM_STCX_FIN",
> + "BriefDescription": "Conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "20130",
> + "EventName": "PM_MRK_INST_DECODED",
> + "BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only."
> + },
> + {
> + "EventCode": "20132",
> + "EventName": "PM_MRK_DFU_ISSUE",
> + "BriefDescription": "The marked instruction was a decimal floating point operation issued to the VSU. Measured at issue time."
> + },
> + {
> + "EventCode": "20134",
> + "EventName": "PM_MRK_FXU_ISSUE",
> + "BriefDescription": "The marked instruction was a fixed point operation issued to the VSU. Measured at issue time."
> + },
> + {
> + "EventCode": "2505C",
> + "EventName": "PM_VSU_ISSUE",
> + "BriefDescription": "At least one VSU instruction was issued to one of the VSU pipes. Up to 4 per cycle. Includes fixed point operations."
> + },
> + {
> + "EventCode": "2F054",
> + "EventName": "PM_DISP_SS1_2_INSTR_CYC",
> + "BriefDescription": "Cycles in which Superslice 1 dispatches either 1 or 2 instructions."
> + },
> + {
> + "EventCode": "2F056",
> + "EventName": "PM_DISP_SS1_4_INSTR_CYC",
> + "BriefDescription": "Cycles in which Superslice 1 dispatches either 3 or 4 instructions."
> + },
> + {
> + "EventCode": "2006C",
> + "EventName": "PM_RUN_CYC_SMT4_MODE",
> + "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT4 mode."
> + },
> + {
> + "EventCode": "201E0",
> + "EventName": "PM_MRK_DATA_FROM_MEMORY",
> + "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked load."
> + },
> + {
> + "EventCode": "201E4",
> + "EventName": "PM_MRK_DATA_FROM_L3MISS",
> + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked load."
> + },
> + {
> + "EventCode": "201E8",
> + "EventName": "PM_THRESH_EXC_512",
> + "BriefDescription": "Threshold counter exceeded a value of 512."
> + },
> + {
> + "EventCode": "200F2",
> + "EventName": "PM_INST_DISP",
> + "BriefDescription": "PowerPC instructions dispatched."
> + },
> + {
> + "EventCode": "30132",
> + "EventName": "PM_MRK_VSU_FIN",
> + "BriefDescription": "VSU marked instructions finished. Excludes simple FX instructions issued to the Store Unit."
> + },
> + {
> + "EventCode": "30038",
> + "EventName": "PM_EXEC_STALL_DMISS_LMEM",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCapp cache, or local OpenCapp memory."
> + },
> + {
> + "EventCode": "3F04A",
> + "EventName": "PM_LSU_ST5_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST2 port."
> + },
> + {
> + "EventCode": "34054",
> + "EventName": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict."
> + },
> + {
> + "EventCode": "3405A",
> + "EventName": "PM_PRIVILEGED_INST_CMPL",
> + "BriefDescription": "PowerPC Instructions that completed while the thread is in Privileged state."
> + },
> + {
> + "EventCode": "3F150",
> + "EventName": "PM_MRK_ST_DRAIN_CYC",
> + "BriefDescription": "cycles to drain st from core to L2."
> + },
> + {
> + "EventCode": "3F054",
> + "EventName": "PM_DISP_SS0_4_INSTR_CYC",
> + "BriefDescription": "Cycles in which Superslice 0 dispatches either 3 or 4 instructions."
> + },
> + {
> + "EventCode": "3F056",
> + "EventName": "PM_DISP_SS0_8_INSTR_CYC",
> + "BriefDescription": "Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions."
> + },
> + {
> + "EventCode": "30162",
> + "EventName": "PM_MRK_ISSUE_DEPENDENT_LOAD",
> + "BriefDescription": "The marked instruction was dependent on a load. It is eligible for issue kill."
> + },
> + {
> + "EventCode": "40114",
> + "EventName": "PM_MRK_START_PROBE_NOP_DISP",
> + "BriefDescription": "Marked Start probe nop dispatched. Instruction AND R0,R0,R0."
> + },
> + {
> + "EventCode": "4001C",
> + "EventName": "PM_VSU_FIN",
> + "BriefDescription": "VSU instructions finished."
> + },
> + {
> + "EventCode": "4C01A",
> + "EventName": "PM_EXEC_STALL_DMISS_OFF_NODE",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a distant chip."
> + },
> + {
> + "EventCode": "4D012",
> + "EventName": "PM_PMC3_SAVED",
> + "BriefDescription": "The conditions for the speculative event selected for PMC3 are met and PMC3 is charged."
> + },
> + {
> + "EventCode": "4D022",
> + "EventName": "PM_HYPERVISOR_INST_CMPL",
> + "BriefDescription": "PowerPC instructions that completed while the thread is in hypervisor state."
> + },
> + {
> + "EventCode": "4D026",
> + "EventName": "PM_ULTRAVISOR_CYC",
> + "BriefDescription": "Cycles when the thread is in Ultravisor state. MSR[S HV PR]=110."
> + },
> + {
> + "EventCode": "4D028",
> + "EventName": "PM_PRIVILEGED_CYC",
> + "BriefDescription": "Cycles when the thread is in Privileged state. MSR[S HV PR]=x00."
> + },
> + {
> + "EventCode": "40030",
> + "EventName": "PM_INST_FIN",
> + "BriefDescription": "Instructions finished."
> + },
> + {
> + "EventCode": "44146",
> + "EventName": "PM_MRK_STCX_CORE_CYC",
> + "BriefDescription": "Cycles spent in the core portion of a marked Stcx instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2."
> + },
> + {
> + "EventCode": "44054",
> + "EventName": "PM_VECTOR_LD_CMPL",
> + "BriefDescription": "Vector load instructions completed."
> + },
> + {
> + "EventCode": "45054",
> + "EventName": "PM_FMA_CMPL",
> + "BriefDescription": "Two floating point instructions completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only."
> + },
> + {
> + "EventCode": "45056",
> + "EventName": "PM_SCALAR_FLOP_CMPL",
> + "BriefDescription": "Scalar floating point instructions completed."
> + },
> + {
> + "EventCode": "4505C",
> + "EventName": "PM_MATH_FLOP_CMPL",
> + "BriefDescription": "Math floating point instructions completed."
> + },
> + {
> + "EventCode": "4D05E",
> + "EventName": "PM_BR_CMPL",
> + "BriefDescription": "A branch completed. All branches are included."
> + },
> + {
> + "EventCode": "4E15E",
> + "EventName": "PM_MRK_INST_FLUSHED",
> + "BriefDescription": "The marked instruction was flushed."
> + },
> + {
> + "EventCode": "401E6",
> + "EventName": "PM_MRK_INST_FROM_L3MISS",
> + "BriefDescription": "The processor's instruction cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked instruction."
> + },
> + {
> + "EventCode": "401E8",
> + "EventName": "PM_MRK_DATA_FROM_L2MISS",
> + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1 or L2 due to a demand miss for a marked load."
> + },
> + {
> + "EventCode": "400F0",
> + "EventName": "PM_LD_DEMAND_MISS_L1_FIN",
> + "BriefDescription": "Load Missed L1, counted at finish time."
> + },
> + {
> + "EventCode": "400FA",
> + "EventName": "PM_RUN_INST_CMPL",
> + "BriefDescription": "Completed PowerPC instructions gated by the run latch."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json b/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
> new file mode 100644
> index 000000000000..33c1c39ea323
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
> @@ -0,0 +1,297 @@
> +[
> + {
> + "EventCode": "100FE",
> + "EventName": "PM_INST_CMPL",
> + "BriefDescription": "PowerPC instructions completed."
> + },
> + {
> + "EventCode": "10006",
> + "EventName": "PM_DISP_STALL_HELD_OTHER_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any other reason."
> + },
> + {
> + "EventCode": "1000C",
> + "EventName": "PM_LSU_LD0_FIN",
> + "BriefDescription": "LSU Finished an internal operation in LD0 port."
> + },
> + {
> + "EventCode": "1000E",
> + "EventName": "PM_MMA_ISSUED",
> + "BriefDescription": "MMA instructions issued."
> + },
> + {
> + "EventCode": "10012",
> + "EventName": "PM_LSU_ST0_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST0 port."
> + },
> + {
> + "EventCode": "10014",
> + "EventName": "PM_LSU_ST4_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST4 port."
> + },
> + {
> + "EventCode": "10018",
> + "EventName": "PM_IC_DEMAND_CYC",
> + "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss."
> + },
> + {
> + "EventCode": "10022",
> + "EventName": "PM_PMC2_SAVED",
> + "BriefDescription": "The conditions for the speculative event selected for PMC2 are met and PMC2 is charged."
> + },
> + {
> + "EventCode": "10024",
> + "EventName": "PM_PMC5_OVERFLOW",
> + "BriefDescription": "The event selected for PMC5 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "10058",
> + "EventName": "PM_EXEC_STALL_FIN_AT_DISP",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch and did not require execution in the LSU, BRU or VSU."
> + },
> + {
> + "EventCode": "1005A",
> + "EventName": "PM_FLUSH_MPRED",
> + "BriefDescription": "A flush occurred due to a mispredicted branch. Includes target and direction."
> + },
> + {
> + "EventCode": "1C05A",
> + "EventName": "PM_DERAT_MISS_2M",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "10064",
> + "EventName": "PM_DISP_STALL_IC_L2",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2."
> + },
> + {
> + "EventCode": "10068",
> + "EventName": "PM_BR_FIN",
> + "BriefDescription": "A branch instruction finished. Includes predicted/mispredicted/unconditional."
> + },
> + {
> + "EventCode": "1006A",
> + "EventName": "PM_FX_LSU_FIN",
> + "BriefDescription": "Simple fixed point instruction issued to the store unit. Measured at finish time."
> + },
> + {
> + "EventCode": "1006C",
> + "EventName": "PM_RUN_CYC_ST_MODE",
> + "BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
> + },
> + {
> + "EventCode": "20004",
> + "EventName": "PM_ISSUE_STALL",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not issued yet."
> + },
> + {
> + "EventCode": "2000A",
> + "EventName": "PM_HYPERVISOR_CYC",
> + "BriefDescription": "Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010."
> + },
> + {
> + "EventCode": "2000E",
> + "EventName": "PM_LSU_LD1_FIN",
> + "BriefDescription": "LSU Finished an internal operation in LD1 port."
> + },
> + {
> + "EventCode": "2C014",
> + "EventName": "PM_CMPL_STALL_SPECIAL",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handling before completing."
> + },
> + {
> + "EventCode": "2C018",
> + "EventName": "PM_EXEC_STALL_DMISS_L3MISS",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a source beyond the local L2 or local L3."
> + },
> + {
> + "EventCode": "2D010",
> + "EventName": "PM_LSU_ST1_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST1 port."
> + },
> + {
> + "EventCode": "2D012",
> + "EventName": "PM_VSU1_ISSUE",
> + "BriefDescription": "VSU instructions issued to VSU pipe 1."
> + },
> + {
> + "EventCode": "2D018",
> + "EventName": "PM_EXEC_STALL_VSU",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the VSU (includes FXU, VSU, CRU)."
> + },
> + {
> + "EventCode": "2E01E",
> + "EventName": "PM_EXEC_STALL_NTC_FLUSH",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in any unit before it was flushed. Note that if the flush of the oldest instruction happens after finish, the cycles from dispatch to issue will be included in PM_DISP_STALL and the cycles from issue to finish will be included in PM_EXEC_STALL and its corresponding children."
> + },
> + {
> + "EventCode": "2013C",
> + "EventName": "PM_MRK_FX_LSU_FIN",
> + "BriefDescription": "The marked instruction was simple fixed point that was issued to the store unit. Measured at finish time."
> + },
> + {
> + "EventCode": "2405A",
> + "EventName": "PM_NTC_FIN",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note that instructions can finish out of order, therefore not all the instructions that finish have a Next-to-complete status."
> + },
> + {
> + "EventCode": "201E2",
> + "EventName": "PM_MRK_LD_MISS_L1",
> + "BriefDescription": "Marked DL1 Demand Miss counted at finish time."
> + },
> + {
> + "EventCode": "200F4",
> + "EventName": "PM_RUN_CYC",
> + "BriefDescription": "Processor cycles gated by the run latch."
> + },
> + {
> + "EventCode": "30004",
> + "EventName": "PM_DISP_STALL_FLUSH",
> + "BriefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet NTC. PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC."
> + },
> + {
> + "EventCode": "30008",
> + "EventName": "PM_EXEC_STALL",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting to finish in one of the execution units (BRU, LSU, VSU). Only cycles between issue and finish are counted in this category."
> + },
> + {
> + "EventCode": "3001A",
> + "EventName": "PM_LSU_ST2_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST2 port."
> + },
> + {
> + "EventCode": "30020",
> + "EventName": "PM_PMC2_REWIND",
> + "BriefDescription": "The speculative event selected for PMC2 rewinds and the counter for PMC2 is not charged."
> + },
> + {
> + "EventCode": "30022",
> + "EventName": "PM_PMC4_SAVED",
> + "BriefDescription": "The conditions for the speculative event selected for PMC4 are met and PMC4 is charged."
> + },
> + {
> + "EventCode": "30024",
> + "EventName": "PM_PMC6_OVERFLOW",
> + "BriefDescription": "The event selected for PMC6 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "30028",
> + "EventName": "PM_CMPL_STALL_MEM_ECC",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC."
> + },
> + {
> + "EventCode": "30036",
> + "EventName": "PM_EXEC_STALL_SIMPLE_FX",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a simple fixed point instruction executing in the Load Store Unit."
> + },
> + {
> + "EventCode": "3003A",
> + "EventName": "PM_CMPL_STALL_EXCEPTION",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete."
> + },
> + {
> + "EventCode": "3F044",
> + "EventName": "PM_VSU2_ISSUE",
> + "BriefDescription": "VSU instructions issued to VSU pipe 2."
> + },
> + {
> + "EventCode": "30058",
> + "EventName": "PM_TLBIE_FIN",
> + "BriefDescription": "TLBIE instructions finished in the LSU. Two TLBIEs can finish each cycle. All will be counted."
> + },
> + {
> + "EventCode": "3D058",
> + "EventName": "PM_SCALAR_FSQRT_FDIV_ISSUE",
> + "BriefDescription": "Scalar versions of four floating point operations: fdiv,fsqrt (xvdivdp, xvdivsp, xvsqrtdp, xvsqrtsp)."
> + },
> + {
> + "EventCode": "30066",
> + "EventName": "PM_LSU_FIN",
> + "BriefDescription": "LSU Finished an internal operation (up to 4 per cycle)."
> + },
> + {
> + "EventCode": "40004",
> + "EventName": "PM_FXU_ISSUE",
> + "BriefDescription": "A fixed point instruction was issued to the VSU."
> + },
> + {
> + "EventCode": "40008",
> + "EventName": "PM_NTC_ALL_FIN",
> + "BriefDescription": "Cycles in which both instructions in the ICT entry pair show as finished. These are the cycles between finish and completion for the oldest pair of instructions in the pipeline."
> + },
> + {
> + "EventCode": "40010",
> + "EventName": "PM_PMC3_OVERFLOW",
> + "BriefDescription": "The event selected for PMC3 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "4C012",
> + "EventName": "PM_EXEC_STALL_DERAT_ONLY_MISS",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered an ERAT miss and waited for it resolve."
> + },
> + {
> + "EventCode": "4C018",
> + "EventName": "PM_CMPL_STALL",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline cannot complete because the thread was blocked for any reason."
> + },
> + {
> + "EventCode": "4C01E",
> + "EventName": "PM_LSU_ST3_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST3 port."
> + },
> + {
> + "EventCode": "4D018",
> + "EventName": "PM_EXEC_STALL_BRU",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Branch unit."
> + },
> + {
> + "EventCode": "4D01A",
> + "EventName": "PM_CMPL_STALL_HWSYNC",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a hwsync waiting for response from L2 before completing."
> + },
> + {
> + "EventCode": "4D01C",
> + "EventName": "PM_EXEC_STALL_TLBIEL",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIEL instruction executing in the Load Store Unit. TLBIEL instructions have lower overhead than TLBIE instructions because they don't get set to the nest."
> + },
> + {
> + "EventCode": "4E012",
> + "EventName": "PM_EXEC_STALL_UNKNOWN",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline completed without an ntf_type pulse. The ntf_pulse was missed by the ISU because the NTF finishes and completions came too close together."
> + },
> + {
> + "EventCode": "4D020",
> + "EventName": "PM_VSU3_ISSUE",
> + "BriefDescription": "VSU instruction was issued to VSU pipe 3."
> + },
> + {
> + "EventCode": "40132",
> + "EventName": "PM_MRK_LSU_FIN",
> + "BriefDescription": "LSU marked instruction finish."
> + },
> + {
> + "EventCode": "45058",
> + "EventName": "PM_IC_MISS_CMPL",
> + "BriefDescription": "Non-speculative icache miss, counted at completion."
> + },
> + {
> + "EventCode": "4D050",
> + "EventName": "PM_VSU_NON_FLOP_CMPL",
> + "BriefDescription": "Non-floating point VSU instructions completed."
> + },
> + {
> + "EventCode": "4D052",
> + "EventName": "PM_2FLOP_CMPL",
> + "BriefDescription": "Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg completed."
> + },
> + {
> + "EventCode": "400F2",
> + "EventName": "PM_1PLUS_PPC_DISP",
> + "BriefDescription": "Cycles at least one Instr Dispatched."
> + },
> + {
> + "EventCode": "400F8",
> + "EventName": "PM_FLUSH",
> + "BriefDescription": "Flush (any type)."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/pmc.json b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json
> new file mode 100644
> index 000000000000..60a0100ee996
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json
> @@ -0,0 +1,22 @@
> +[
> + {
> + "EventCode": "301E8",
> + "EventName": "PM_THRESH_EXC_64",
> + "BriefDescription": "Threshold counter exceeded a value of 64."
> + },
> + {
> + "EventCode": "45050",
> + "EventName": "PM_1FLOP_CMPL",
> + "BriefDescription": "One floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
> + },
> + {
> + "EventCode": "45052",
> + "EventName": "PM_4FLOP_CMPL",
> + "BriefDescription": "Four floating point instructions completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
> + },
> + {
> + "EventCode": "4D054",
> + "EventName": "PM_8FLOP_CMPL",
> + "BriefDescription": "Four Double Precision vector instructions completed."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/translation.json b/tools/perf/pmu-events/arch/powerpc/power10/translation.json
> new file mode 100644
> index 000000000000..da44d4ca6ef3
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/translation.json
> @@ -0,0 +1,57 @@
> +[
> + {
> + "EventCode": "1F15E",
> + "EventName": "PM_MRK_START_PROBE_NOP_CMPL",
> + "BriefDescription": "Marked Start probe nop (AND R0,R0,R0) completed."
> + },
> + {
> + "EventCode": "20016",
> + "EventName": "PM_ST_FIN",
> + "BriefDescription": "Store finish count. Includes speculative activity."
> + },
> + {
> + "EventCode": "20018",
> + "EventName": "PM_ST_FWD",
> + "BriefDescription": "Store forwards that finished."
> + },
> + {
> + "EventCode": "2011C",
> + "EventName": "PM_MRK_NTF_CYC",
> + "BriefDescription": "Cycles during which the marked instruction is the oldest in the pipeline (NTF or NTC)."
> + },
> + {
> + "EventCode": "2E01C",
> + "EventName": "PM_EXEC_STALL_TLBIE",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIE instruction executing in the Load Store Unit."
> + },
> + {
> + "EventCode": "201E6",
> + "EventName": "PM_THRESH_EXC_32",
> + "BriefDescription": "Threshold counter exceeded a value of 32."
> + },
> + {
> + "EventCode": "200F0",
> + "EventName": "PM_ST_CMPL",
> + "BriefDescription": "Stores completed from S2Q (2nd-level store queue). This event includes regular stores, stcx and cache inhibited stores. The following operations are excluded (pteupdate, snoop tlbie complete, store atomics, miso, load atomic payloads, tlbie, tlbsync, slbieg, isync, msgsnd, slbiag, cpabort, copy, tcheck, tend, stsync, dcbst, icbi, dcbf, hwsync, lwsync, ptesync, eieio, msgsync)."
> + },
> + {
> + "EventCode": "200FE",
> + "EventName": "PM_DATA_FROM_L2MISS",
> + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1 or L2 due to a demand miss."
> + },
> + {
> + "EventCode": "30010",
> + "EventName": "PM_PMC2_OVERFLOW",
> + "BriefDescription": "The event selected for PMC2 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "4D010",
> + "EventName": "PM_PMC1_SAVED",
> + "BriefDescription": "The conditions for the speculative event selected for PMC1 are met and PMC1 is charged."
> + },
> + {
> + "EventCode": "4D05C",
> + "EventName": "PM_DPP_FLOP_CMPL",
> + "BriefDescription": "Double-Precision or Quad-Precision instructions completed."
> + }
> +]
> --
> 2.27.0
^ permalink raw reply
* Re: linux-next: build failure after merge of the powerpc tree
From: Michael Ellerman @ 2021-04-19 12:24 UTC (permalink / raw)
To: Xiongwei Song, Stephen Rothwell
Cc: Linux Next Mailing List, PowerPC, Linux Kernel Mailing List
In-Reply-To: <CAEVVKH905HJoJ_WVVZadXiy3LG5y+XDpMBVVtUNOwF2MtYTv8Q@mail.gmail.com>
Xiongwei Song <sxwjean@gmail.com> writes:
> Thank you so much Stephen. Sorry for my negligence.
My fault. I forgot to run allyesconfig.
> Should I fix this myself on powerpc tree?
I'll fix it up.
cheers
^ permalink raw reply
* Re: [PATCH v4] powerpc/kexec_file: use current CPU info while setting up FDT
From: Michael Ellerman @ 2021-04-19 12:21 UTC (permalink / raw)
To: Hari Bathini, Sourabh Jain; +Cc: mahesh, stable, bauerman, linuxppc-dev
In-Reply-To: <3c004e09-7db2-1bb8-352a-0695278eea93@linux.ibm.com>
Hari Bathini <hbathini@linux.ibm.com> writes:
> On 19/04/21 2:06 pm, Sourabh Jain wrote:
>> kexec_file_load uses initial_boot_params in setting up the device-tree
>> for the kernel to be loaded. Though initial_boot_params holds info
>> about CPUs at the time of boot, it doesn't account for hot added CPUs.
>>
>> So, kexec'ing with kexec_file_load syscall would leave the kexec'ed
>> kernel with inaccurate CPU info. Also, if kdump kernel is loaded with
>> kexec_file_load syscall and the system crashes on a hot added CPU,
>> capture kernel hangs failing to identify the boot CPU.
>>
>> Kernel panic - not syncing: sysrq triggered crash
>> CPU: 24 PID: 6065 Comm: echo Kdump: loaded Not tainted 5.12.0-rc5upstream #54
>> Call Trace:
>> [c0000000e590fac0] [c0000000007b2400] dump_stack+0xc4/0x114 (unreliable)
>> [c0000000e590fb00] [c000000000145290] panic+0x16c/0x41c
>> [c0000000e590fba0] [c0000000008892e0] sysrq_handle_crash+0x30/0x40
>> [c0000000e590fc00] [c000000000889cdc] __handle_sysrq+0xcc/0x1f0
>> [c0000000e590fca0] [c00000000088a538] write_sysrq_trigger+0xd8/0x178
>> [c0000000e590fce0] [c0000000005e9b7c] proc_reg_write+0x10c/0x1b0
>> [c0000000e590fd10] [c0000000004f26d0] vfs_write+0xf0/0x330
>> [c0000000e590fd60] [c0000000004f2aec] ksys_write+0x7c/0x140
>> [c0000000e590fdb0] [c000000000031ee0] system_call_exception+0x150/0x290
>> [c0000000e590fe10] [c00000000000ca5c] system_call_common+0xec/0x278
>> --- interrupt: c00 at 0x7fff905b9664
>> NIP: 00007fff905b9664 LR: 00007fff905320c4 CTR: 0000000000000000
>> REGS: c0000000e590fe80 TRAP: 0c00 Not tainted (5.12.0-rc5upstream)
>> MSR: 800000000280f033 <SF,VEC,VSX,EE,PR,FP,ME,IR,DR,RI,LE> CR: 28000242
>> XER: 00000000
>> IRQMASK: 0
>> GPR00: 0000000000000004 00007ffff5fedf30 00007fff906a7300 0000000000000001
>> GPR04: 000001002a7355b0 0000000000000002 0000000000000001 00007ffff5fef616
>> GPR08: 0000000000000001 0000000000000000 0000000000000000 0000000000000000
>> GPR12: 0000000000000000 00007fff9073a160 0000000000000000 0000000000000000
>> GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
>> GPR20: 0000000000000000 00007fff906a4ee0 0000000000000002 0000000000000001
>> GPR24: 00007fff906a0898 0000000000000000 0000000000000002 000001002a7355b0
>> GPR28: 0000000000000002 00007fff906a1790 000001002a7355b0 0000000000000002
>> NIP [00007fff905b9664] 0x7fff905b9664
>> LR [00007fff905320c4] 0x7fff905320c4
>> --- interrupt: c00
>>
>> To avoid this from happening, extract current CPU info from of_root
>> device node and use it for setting up the fdt in kexec_file_load case.
>>
>> Fixes: 6ecd0163d360 ("powerpc/kexec_file: Add appropriate regions for memory reserve map")
>>
>> Signed-off-by: Sourabh Jain <sourabhjain@linux.ibm.com>
>> Reviewed-by: Hari Bathini <hbathini@linux.ibm.com>
>> Cc: <stable@vger.kernel.org>
>> ---
>> arch/powerpc/kexec/file_load_64.c | 98 +++++++++++++++++++++++++++++++
>> 1 file changed, 98 insertions(+)
>>
>> ---
>> Changelog:
>>
>> v1 -> v3
>> - https://lists.ozlabs.org/pipermail/linuxppc-dev/2021-April/227756.html
>>
>> v3 -> v4
>> - Rearranged if-else statement in update_cpus_node function to avoid
>> redundant checks for positive cpus_offset.
>> ---
>>
>> diff --git a/arch/powerpc/kexec/file_load_64.c b/arch/powerpc/kexec/file_load_64.c
>> index 02b9e4d0dc40..195ef303d530 100644
>> --- a/arch/powerpc/kexec/file_load_64.c
>> +++ b/arch/powerpc/kexec/file_load_64.c
>> @@ -960,6 +960,99 @@ unsigned int kexec_fdt_totalsize_ppc64(struct kimage *image)
>> return fdt_size;
>> }
>>
>> +/**
>> + * add_node_prop - Read property from device node structure and add
>> + * them to fdt.
>> + * @fdt: Flattened device tree of the kernel
>> + * @node_offset: offset of the node to add a property at
>> + * np: device node pointer
>> + *
>> + * Returns 0 on success, negative errno on error.
>> + */
>> +static int add_node_prop(void *fdt, int node_offset, const struct device_node *np)
>> +{
>> + int ret = 0;
>> + struct property *pp;
>> + unsigned long flags;
>> +
>> + if (!np)
>> + return -EINVAL;
>> +
>> + raw_spin_lock_irqsave(&devtree_lock, flags);
>> + for (pp = np->properties; pp; pp = pp->next) {
>> + ret = fdt_setprop(fdt, node_offset, pp->name,
>> + pp->value, pp->length);
>> + if (ret < 0) {
>> + pr_err("Unable to add %s property: %s\n",
>> + pp->name, fdt_strerror(ret));
>> + goto out;
>> + }
>> + }
>> +out:
>> + raw_spin_unlock_irqrestore(&devtree_lock, flags);
>> + return ret;
>> +}
>> +
>> +/**
>> + * update_cpus_node - Update cpus node of flattened device-tree using of_root
>> + * device node.
>> + * @fdt: Flattened device tree of the kernel.
>> + *
>> + * Returns 0 on success, negative errno on error.
>> + */
>> +static int update_cpus_node(void *fdt)
>> +{
>> + struct device_node *cpus_node, *dn;
>> + int cpus_offset, cpus_subnode_off, ret = 0;
>> +
>> + cpus_offset = fdt_path_offset(fdt, "/cpus");
>> + if (cpus_offset < 0 && cpus_offset != -FDT_ERR_NOTFOUND) {
>> + pr_err("Malformed device tree: error reading /cpus node: %s\n",
>> + fdt_strerror(cpus_offset));
>> + return cpus_offset;
>> + } else {
>
>
>> + if (cpus_offset > 0) {
>> + ret = fdt_del_node(fdt, cpus_offset);
>> + if (ret < 0) {
>> + pr_err("Error deleting /cpus node: %s\n",
>> + fdt_strerror(ret));
>> + return -EINVAL;
>> + }
>> + }
>> +
>> + /* Add cpus node to fdt */
>> + cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
>> + "cpus");
>> + if (cpus_offset < 0) {
>> + pr_err("Error creating /cpus node: %s\n",
>> + fdt_strerror(cpus_offset));
>> + return -EINVAL;
>> + }
>> +
>> + /* Add cpus node properties */
>> + cpus_node = of_find_node_by_path("/cpus");
>> + ret = add_node_prop(fdt, cpus_offset, cpus_node);
>> + if (ret < 0)
>> + return ret;
>> +
>> + /* Loop through all subnodes of cpus and add them to fdt */
>> + for_each_node_by_type(dn, "cpu") {
>> + cpus_subnode_off = fdt_add_subnode(fdt,
>> + cpus_offset,
>> + dn->full_name);
>> + if (cpus_subnode_off < 0) {
>> + pr_err("Unable to add %s subnode: %s\n",
>> + dn->full_name, fdt_strerror(cpus_subnode_off));
>> + return cpus_subnode_off;
>> + }
>> + ret = add_node_prop(fdt, cpus_subnode_off, dn);
>> + if (ret < 0)
>> + return ret;
>> + }
>
> The above code block doesn't really need an explicit else condition..
Yeah, use the early return to avoid having to indent all the rest of
that logic.
Please send a v5.
cheers
^ permalink raw reply
* [PATCH] powerpc/kvm: Fix PR KVM with KUAP/MEM_KEYS enabled
From: Michael Ellerman @ 2021-04-19 12:01 UTC (permalink / raw)
To: linuxppc-dev; +Cc: aneesh.kumar, kvm-ppc
The changes to add KUAP support with the hash MMU broke booting of KVM
PR guests. The symptom is no visible progress of the guest, or possibly
just "SLOF" being printed to the qemu console.
Host code is still executing, but breaking into xmon might show a stack
trace such as:
__might_fault+0x84/0xe0 (unreliable)
kvm_read_guest+0x1c8/0x2f0 [kvm]
kvmppc_ld+0x1b8/0x2d0 [kvm]
kvmppc_load_last_inst+0x50/0xa0 [kvm]
kvmppc_exit_pr_progint+0x178/0x220 [kvm_pr]
kvmppc_handle_exit_pr+0x31c/0xe30 [kvm_pr]
after_sprg3_load+0x80/0x90 [kvm_pr]
kvmppc_vcpu_run_pr+0x104/0x260 [kvm_pr]
kvmppc_vcpu_run+0x34/0x48 [kvm]
kvm_arch_vcpu_ioctl_run+0x340/0x450 [kvm]
kvm_vcpu_ioctl+0x2ac/0x8c0 [kvm]
sys_ioctl+0x320/0x1060
system_call_exception+0x160/0x270
system_call_common+0xf0/0x27c
Bisect points to commit b2ff33a10c8b ("powerpc/book3s64/hash/kuap:
Enable kuap on hash"), but that's just the commit that enabled KUAP with
hash and made the bug visible.
The root cause seems to be that KVM PR is creating kernel mappings that
don't use the correct key, since we switched to using key 3.
We have a helper for adding the right key value, however it's designed
to take a pteflags variable, which the KVM code doesn't have. But we can
make it work by passing 0 for the pteflags, and tell it explicitly that
it should use the kernel key.
With that changed guests boot successfully.
Fixes: d94b827e89dc ("powerpc/book3s64/kuap: Use Key 3 for kernel mapping with hash translation")
Cc: stable@vger.kernel.org # v5.11+
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
arch/powerpc/kvm/book3s_64_mmu_host.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
index e452158a18d7..5ac66be1cb3c 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -12,6 +12,7 @@
#include <asm/kvm_ppc.h>
#include <asm/kvm_book3s.h>
#include <asm/book3s/64/mmu-hash.h>
+#include <asm/book3s/64/pkeys.h>
#include <asm/machdep.h>
#include <asm/mmu_context.h>
#include <asm/hw_irq.h>
@@ -133,6 +134,7 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte,
else
kvmppc_mmu_flush_icache(pfn);
+ rflags |= pte_to_hpte_pkey_bits(0, HPTE_USE_KERNEL_KEY);
rflags = (rflags & ~HPTE_R_WIMG) | orig_pte->wimg;
/*
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v4] powerpc/kexec_file: use current CPU info while setting up FDT
From: Hari Bathini @ 2021-04-19 11:53 UTC (permalink / raw)
To: Sourabh Jain, mpe; +Cc: mahesh, stable, bauerman, linuxppc-dev
In-Reply-To: <20210419083624.1124390-1-sourabhjain@linux.ibm.com>
On 19/04/21 2:06 pm, Sourabh Jain wrote:
> kexec_file_load uses initial_boot_params in setting up the device-tree
> for the kernel to be loaded. Though initial_boot_params holds info
> about CPUs at the time of boot, it doesn't account for hot added CPUs.
>
> So, kexec'ing with kexec_file_load syscall would leave the kexec'ed
> kernel with inaccurate CPU info. Also, if kdump kernel is loaded with
> kexec_file_load syscall and the system crashes on a hot added CPU,
> capture kernel hangs failing to identify the boot CPU.
>
> Kernel panic - not syncing: sysrq triggered crash
> CPU: 24 PID: 6065 Comm: echo Kdump: loaded Not tainted 5.12.0-rc5upstream #54
> Call Trace:
> [c0000000e590fac0] [c0000000007b2400] dump_stack+0xc4/0x114 (unreliable)
> [c0000000e590fb00] [c000000000145290] panic+0x16c/0x41c
> [c0000000e590fba0] [c0000000008892e0] sysrq_handle_crash+0x30/0x40
> [c0000000e590fc00] [c000000000889cdc] __handle_sysrq+0xcc/0x1f0
> [c0000000e590fca0] [c00000000088a538] write_sysrq_trigger+0xd8/0x178
> [c0000000e590fce0] [c0000000005e9b7c] proc_reg_write+0x10c/0x1b0
> [c0000000e590fd10] [c0000000004f26d0] vfs_write+0xf0/0x330
> [c0000000e590fd60] [c0000000004f2aec] ksys_write+0x7c/0x140
> [c0000000e590fdb0] [c000000000031ee0] system_call_exception+0x150/0x290
> [c0000000e590fe10] [c00000000000ca5c] system_call_common+0xec/0x278
> --- interrupt: c00 at 0x7fff905b9664
> NIP: 00007fff905b9664 LR: 00007fff905320c4 CTR: 0000000000000000
> REGS: c0000000e590fe80 TRAP: 0c00 Not tainted (5.12.0-rc5upstream)
> MSR: 800000000280f033 <SF,VEC,VSX,EE,PR,FP,ME,IR,DR,RI,LE> CR: 28000242
> XER: 00000000
> IRQMASK: 0
> GPR00: 0000000000000004 00007ffff5fedf30 00007fff906a7300 0000000000000001
> GPR04: 000001002a7355b0 0000000000000002 0000000000000001 00007ffff5fef616
> GPR08: 0000000000000001 0000000000000000 0000000000000000 0000000000000000
> GPR12: 0000000000000000 00007fff9073a160 0000000000000000 0000000000000000
> GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
> GPR20: 0000000000000000 00007fff906a4ee0 0000000000000002 0000000000000001
> GPR24: 00007fff906a0898 0000000000000000 0000000000000002 000001002a7355b0
> GPR28: 0000000000000002 00007fff906a1790 000001002a7355b0 0000000000000002
> NIP [00007fff905b9664] 0x7fff905b9664
> LR [00007fff905320c4] 0x7fff905320c4
> --- interrupt: c00
>
> To avoid this from happening, extract current CPU info from of_root
> device node and use it for setting up the fdt in kexec_file_load case.
>
> Fixes: 6ecd0163d360 ("powerpc/kexec_file: Add appropriate regions for memory reserve map")
>
> Signed-off-by: Sourabh Jain <sourabhjain@linux.ibm.com>
> Reviewed-by: Hari Bathini <hbathini@linux.ibm.com>
> Cc: <stable@vger.kernel.org>
> ---
> arch/powerpc/kexec/file_load_64.c | 98 +++++++++++++++++++++++++++++++
> 1 file changed, 98 insertions(+)
>
> ---
> Changelog:
>
> v1 -> v3
> - https://lists.ozlabs.org/pipermail/linuxppc-dev/2021-April/227756.html
>
> v3 -> v4
> - Rearranged if-else statement in update_cpus_node function to avoid
> redundant checks for positive cpus_offset.
> ---
>
> diff --git a/arch/powerpc/kexec/file_load_64.c b/arch/powerpc/kexec/file_load_64.c
> index 02b9e4d0dc40..195ef303d530 100644
> --- a/arch/powerpc/kexec/file_load_64.c
> +++ b/arch/powerpc/kexec/file_load_64.c
> @@ -960,6 +960,99 @@ unsigned int kexec_fdt_totalsize_ppc64(struct kimage *image)
> return fdt_size;
> }
>
> +/**
> + * add_node_prop - Read property from device node structure and add
> + * them to fdt.
> + * @fdt: Flattened device tree of the kernel
> + * @node_offset: offset of the node to add a property at
> + * np: device node pointer
> + *
> + * Returns 0 on success, negative errno on error.
> + */
> +static int add_node_prop(void *fdt, int node_offset, const struct device_node *np)
> +{
> + int ret = 0;
> + struct property *pp;
> + unsigned long flags;
> +
> + if (!np)
> + return -EINVAL;
> +
> + raw_spin_lock_irqsave(&devtree_lock, flags);
> + for (pp = np->properties; pp; pp = pp->next) {
> + ret = fdt_setprop(fdt, node_offset, pp->name,
> + pp->value, pp->length);
> + if (ret < 0) {
> + pr_err("Unable to add %s property: %s\n",
> + pp->name, fdt_strerror(ret));
> + goto out;
> + }
> + }
> +out:
> + raw_spin_unlock_irqrestore(&devtree_lock, flags);
> + return ret;
> +}
> +
> +/**
> + * update_cpus_node - Update cpus node of flattened device-tree using of_root
> + * device node.
> + * @fdt: Flattened device tree of the kernel.
> + *
> + * Returns 0 on success, negative errno on error.
> + */
> +static int update_cpus_node(void *fdt)
> +{
> + struct device_node *cpus_node, *dn;
> + int cpus_offset, cpus_subnode_off, ret = 0;
> +
> + cpus_offset = fdt_path_offset(fdt, "/cpus");
> + if (cpus_offset < 0 && cpus_offset != -FDT_ERR_NOTFOUND) {
> + pr_err("Malformed device tree: error reading /cpus node: %s\n",
> + fdt_strerror(cpus_offset));
> + return cpus_offset;
> + } else {
> + if (cpus_offset > 0) {
> + ret = fdt_del_node(fdt, cpus_offset);
> + if (ret < 0) {
> + pr_err("Error deleting /cpus node: %s\n",
> + fdt_strerror(ret));
> + return -EINVAL;
> + }
> + }
> +
> + /* Add cpus node to fdt */
> + cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
> + "cpus");
> + if (cpus_offset < 0) {
> + pr_err("Error creating /cpus node: %s\n",
> + fdt_strerror(cpus_offset));
> + return -EINVAL;
> + }
> +
> + /* Add cpus node properties */
> + cpus_node = of_find_node_by_path("/cpus");
> + ret = add_node_prop(fdt, cpus_offset, cpus_node);
> + if (ret < 0)
> + return ret;
> +
> + /* Loop through all subnodes of cpus and add them to fdt */
> + for_each_node_by_type(dn, "cpu") {
> + cpus_subnode_off = fdt_add_subnode(fdt,
> + cpus_offset,
> + dn->full_name);
> + if (cpus_subnode_off < 0) {
> + pr_err("Unable to add %s subnode: %s\n",
> + dn->full_name, fdt_strerror(cpus_subnode_off));
> + return cpus_subnode_off;
> + }
> + ret = add_node_prop(fdt, cpus_subnode_off, dn);
> + if (ret < 0)
> + return ret;
> + }
The above code block doesn't really need an explicit else condition..
> + }
> + return ret;
> +}
Thanks
Hari
^ permalink raw reply
* [PATCH v2] perf vendor events: Initial json/events list for power10 platform
From: Kajol Jain @ 2021-04-19 11:20 UTC (permalink / raw)
To: acme
Cc: ravi.bangoria, atrajeev, kjain, linuxppc-dev, linux-kernel,
linux-perf-users, maddy, pc, jolsa
Patch adds initial json/events for POWER10.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Tested-by: Paul A. Clarke <pc@us.ibm.com>
Reviewed-by: Paul A. Clarke <pc@us.ibm.com>
---
.../perf/pmu-events/arch/powerpc/mapfile.csv | 1 +
.../arch/powerpc/power10/cache.json | 47 +++
.../arch/powerpc/power10/floating_point.json | 7 +
.../arch/powerpc/power10/frontend.json | 217 +++++++++++++
.../arch/powerpc/power10/locks.json | 12 +
.../arch/powerpc/power10/marked.json | 147 +++++++++
.../arch/powerpc/power10/memory.json | 192 +++++++++++
.../arch/powerpc/power10/others.json | 297 ++++++++++++++++++
.../arch/powerpc/power10/pipeline.json | 297 ++++++++++++++++++
.../pmu-events/arch/powerpc/power10/pmc.json | 22 ++
.../arch/powerpc/power10/translation.json | 57 ++++
11 files changed, 1296 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/cache.json
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/frontend.json
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/locks.json
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/marked.json
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/memory.json
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/others.json
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/pmc.json
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/translation.json
---
Changelog:
v1 -> v2
- Removed inconsistencies in "BriefDescription" field and make sure
it will end with period without any space at the end.
Suggested by : Paul A. Clarke
- Added Tested-by and Reviewed-by tag.
---
diff --git a/tools/perf/pmu-events/arch/powerpc/mapfile.csv b/tools/perf/pmu-events/arch/powerpc/mapfile.csv
index 229150e7ab7d..4abdfc3f9692 100644
--- a/tools/perf/pmu-events/arch/powerpc/mapfile.csv
+++ b/tools/perf/pmu-events/arch/powerpc/mapfile.csv
@@ -15,3 +15,4 @@
# Power8 entries
004[bcd][[:xdigit:]]{4},1,power8,core
004e[[:xdigit:]]{4},1,power9,core
+0080[[:xdigit:]]{4},1,power10,core
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/cache.json b/tools/perf/pmu-events/arch/powerpc/power10/cache.json
new file mode 100644
index 000000000000..95e33531fbc6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/cache.json
@@ -0,0 +1,47 @@
+[
+ {
+ "EventCode": "1003C",
+ "EventName": "PM_EXEC_STALL_DMISS_L2L3",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
+ },
+ {
+ "EventCode": "34056",
+ "EventName": "PM_EXEC_STALL_LOAD_FINISH",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the NTF instruction merged with another load in the LMQ."
+ },
+ {
+ "EventCode": "3006C",
+ "EventName": "PM_RUN_CYC_SMT2_MODE",
+ "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
+ },
+ {
+ "EventCode": "300F4",
+ "EventName": "PM_RUN_INST_CMPL_CONC",
+ "BriefDescription": "PowerPC instructions completed by this thread when all threads in the core had the run-latch set."
+ },
+ {
+ "EventCode": "4C016",
+ "EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."
+ },
+ {
+ "EventCode": "4D014",
+ "EventName": "PM_EXEC_STALL_LOAD",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit."
+ },
+ {
+ "EventCode": "4D016",
+ "EventName": "PM_EXEC_STALL_PTESYNC",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit."
+ },
+ {
+ "EventCode": "401EA",
+ "EventName": "PM_THRESH_EXC_128",
+ "BriefDescription": "Threshold counter exceeded a value of 128."
+ },
+ {
+ "EventCode": "400F6",
+ "EventName": "PM_BR_MPRED_CMPL",
+ "BriefDescription": "A mispredicted branch completed. Includes direction and target."
+ }
+]
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json b/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
new file mode 100644
index 000000000000..e9b92f282d3c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
@@ -0,0 +1,7 @@
+[
+ {
+ "EventCode": "4016E",
+ "EventName": "PM_THRESH_NOT_MET",
+ "BriefDescription": "Threshold counter did not meet threshold."
+ }
+]
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/frontend.json b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json
new file mode 100644
index 000000000000..aebaf94bfdfe
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json
@@ -0,0 +1,217 @@
+[
+ {
+ "EventCode": "10004",
+ "EventName": "PM_EXEC_STALL_TRANSLATION",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or ERAT miss and waited for it to resolve."
+ },
+ {
+ "EventCode": "10010",
+ "EventName": "PM_PMC4_OVERFLOW",
+ "BriefDescription": "The event selected for PMC4 caused the event counter to overflow."
+ },
+ {
+ "EventCode": "10020",
+ "EventName": "PM_PMC4_REWIND",
+ "BriefDescription": "The speculative event selected for PMC4 rewinds and the counter for PMC4 is not charged."
+ },
+ {
+ "EventCode": "10038",
+ "EventName": "PM_DISP_STALL_TRANSLATION",
+ "BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling a translation miss."
+ },
+ {
+ "EventCode": "1003A",
+ "EventName": "PM_DISP_STALL_BR_MPRED_IC_L2",
+ "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict."
+ },
+ {
+ "EventCode": "1E050",
+ "EventName": "PM_DISP_STALL_HELD_STF_MAPPER_CYC",
+ "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR."
+ },
+ {
+ "EventCode": "1F054",
+ "EventName": "PM_DTLB_HIT",
+ "BriefDescription": "The PTE required by the instruction was resident in the TLB (data TLB access). When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefetch. Applies to both HPT and RPT."
+ },
+ {
+ "EventCode": "101E8",
+ "EventName": "PM_THRESH_EXC_256",
+ "BriefDescription": "Threshold counter exceeded a count of 256."
+ },
+ {
+ "EventCode": "101EC",
+ "EventName": "PM_THRESH_MET",
+ "BriefDescription": "Threshold exceeded."
+ },
+ {
+ "EventCode": "100F2",
+ "EventName": "PM_1PLUS_PPC_CMPL",
+ "BriefDescription": "Cycles in which at least one instruction is completed by this thread."
+ },
+ {
+ "EventCode": "100F6",
+ "EventName": "PM_IERAT_MISS",
+ "BriefDescription": "IERAT Reloaded to satisfy an IERAT miss. All page sizes are counted by this event."
+ },
+ {
+ "EventCode": "100F8",
+ "EventName": "PM_DISP_STALL_CYC",
+ "BriefDescription": "Cycles the ICT has no itags assigned to this thread (no instructions were dispatched during these cycles)."
+ },
+ {
+ "EventCode": "20114",
+ "EventName": "PM_MRK_L2_RC_DISP",
+ "BriefDescription": "Marked instruction RC dispatched in L2."
+ },
+ {
+ "EventCode": "2C010",
+ "EventName": "PM_EXEC_STALL_LSU",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Load Store Unit. This does not include simple fixed point instructions."
+ },
+ {
+ "EventCode": "2C016",
+ "EventName": "PM_DISP_STALL_IERAT_ONLY_MISS",
+ "BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT miss."
+ },
+ {
+ "EventCode": "2C01E",
+ "EventName": "PM_DISP_STALL_BR_MPRED_IC_L3",
+ "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3 after suffering a branch mispredict."
+ },
+ {
+ "EventCode": "2D01A",
+ "EventName": "PM_DISP_STALL_IC_MISS",
+ "BriefDescription": "Cycles when dispatch was stalled for this thread due to an Icache Miss."
+ },
+ {
+ "EventCode": "2D01C",
+ "EventName": "PM_CMPL_STALL_STCX",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for resolution from the nest before completing."
+ },
+ {
+ "EventCode": "2E018",
+ "EventName": "PM_DISP_STALL_FETCH",
+ "BriefDescription": "Cycles when dispatch was stalled for this thread because Fetch was being held."
+ },
+ {
+ "EventCode": "2E01A",
+ "EventName": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC",
+ "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the XVFC mapper/SRB was full."
+ },
+ {
+ "EventCode": "2C142",
+ "EventName": "PM_MRK_XFER_FROM_SRC_PMC2",
+ "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
+ },
+ {
+ "EventCode": "24050",
+ "EventName": "PM_IOPS_DISP",
+ "BriefDescription": "Internal Operations dispatched. PM_IOPS_DISP / PM_INST_DISP will show the average number of internal operations per PowerPC instruction."
+ },
+ {
+ "EventCode": "2405E",
+ "EventName": "PM_ISSUE_CANCEL",
+ "BriefDescription": "An instruction issued and the issue was later cancelled. Only one cancel per PowerPC instruction."
+ },
+ {
+ "EventCode": "200FA",
+ "EventName": "PM_BR_TAKEN_CMPL",
+ "BriefDescription": "Branch Taken instruction completed."
+ },
+ {
+ "EventCode": "30012",
+ "EventName": "PM_FLUSH_COMPLETION",
+ "BriefDescription": "The instruction that was next to complete (oldest in the pipeline) did not complete because it suffered a flush."
+ },
+ {
+ "EventCode": "30014",
+ "EventName": "PM_EXEC_STALL_STORE",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store instruction executing in the Load Store Unit."
+ },
+ {
+ "EventCode": "30018",
+ "EventName": "PM_DISP_STALL_HELD_SCOREBOARD_CYC",
+ "BriefDescription": "Cycles in which the NTC instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."
+ },
+ {
+ "EventCode": "30026",
+ "EventName": "PM_EXEC_STALL_STORE_MISS",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store whose cache line was not resident in the L1 and was waiting for allocation of the missing line into the L1."
+ },
+ {
+ "EventCode": "3012A",
+ "EventName": "PM_MRK_L2_RC_DONE",
+ "BriefDescription": "L2 RC machine completed the transaction for the marked instruction."
+ },
+ {
+ "EventCode": "3F046",
+ "EventName": "PM_ITLB_HIT_1G",
+ "BriefDescription": "Instruction TLB hit (IERAT reload) page size 1G, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "34058",
+ "EventName": "PM_DISP_STALL_BR_MPRED_ICMISS",
+ "BriefDescription": "Cycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss."
+ },
+ {
+ "EventCode": "3D05C",
+ "EventName": "PM_DISP_STALL_HELD_RENAME_CYC",
+ "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC."
+ },
+ {
+ "EventCode": "3E052",
+ "EventName": "PM_DISP_STALL_IC_L3",
+ "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3."
+ },
+ {
+ "EventCode": "3E054",
+ "EventName": "PM_LD_MISS_L1",
+ "BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
+ },
+ {
+ "EventCode": "301EA",
+ "EventName": "PM_THRESH_EXC_1024",
+ "BriefDescription": "Threshold counter exceeded a value of 1024."
+ },
+ {
+ "EventCode": "300FA",
+ "EventName": "PM_INST_FROM_L3MISS",
+ "BriefDescription": "The processor's instruction cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."
+ },
+ {
+ "EventCode": "40006",
+ "EventName": "PM_ISSUE_KILL",
+ "BriefDescription": "Cycles in which an instruction or group of instructions were cancelled after being issued. This event increments once per occurrence, regardless of how many instructions are included in the issue group."
+ },
+ {
+ "EventCode": "40116",
+ "EventName": "PM_MRK_LARX_FIN",
+ "BriefDescription": "Marked load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
+ },
+ {
+ "EventCode": "4C010",
+ "EventName": "PM_DISP_STALL_BR_MPRED_IC_L3MISS",
+ "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a mispredicted branch."
+ },
+ {
+ "EventCode": "4D01E",
+ "EventName": "PM_DISP_STALL_BR_MPRED",
+ "BriefDescription": "Cycles when dispatch was stalled for this thread due to a mispredicted branch."
+ },
+ {
+ "EventCode": "4E010",
+ "EventName": "PM_DISP_STALL_IC_L3MISS",
+ "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from any source beyond the local L3."
+ },
+ {
+ "EventCode": "4E01A",
+ "EventName": "PM_DISP_STALL_HELD_CYC",
+ "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any reason."
+ },
+ {
+ "EventCode": "44056",
+ "EventName": "PM_VECTOR_ST_CMPL",
+ "BriefDescription": "Vector store instructions completed."
+ }
+]
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/locks.json b/tools/perf/pmu-events/arch/powerpc/power10/locks.json
new file mode 100644
index 000000000000..fa81b470d21f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/locks.json
@@ -0,0 +1,12 @@
+[
+ {
+ "EventCode": "1E058",
+ "EventName": "PM_STCX_FAIL_FIN",
+ "BriefDescription": "Conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock."
+ },
+ {
+ "EventCode": "4E050",
+ "EventName": "PM_STCX_PASS_FIN",
+ "BriefDescription": "Conditional store instruction (STCX) passed. LARX and STCX are instructions used to acquire a lock."
+ }
+]
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/marked.json b/tools/perf/pmu-events/arch/powerpc/power10/marked.json
new file mode 100644
index 000000000000..ffe38525b18b
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/marked.json
@@ -0,0 +1,147 @@
+[
+ {
+ "EventCode": "1002C",
+ "EventName": "PM_LD_PREFETCH_CACHE_LINE_MISS",
+ "BriefDescription": "The L1 cache was reloaded with a line that fulfills a prefetch request."
+ },
+ {
+ "EventCode": "10132",
+ "EventName": "PM_MRK_INST_ISSUED",
+ "BriefDescription": "Marked instruction issued. Note that stores always get issued twice, the address gets issued to the LSU and the data gets issued to the VSU. Also, issues can sometimes get killed/cancelled and cause multiple sequential issues for the same instruction."
+ },
+ {
+ "EventCode": "101E0",
+ "EventName": "PM_MRK_INST_DISP",
+ "BriefDescription": "The thread has dispatched a randomly sampled marked instruction."
+ },
+ {
+ "EventCode": "101E2",
+ "EventName": "PM_MRK_BR_TAKEN_CMPL",
+ "BriefDescription": "Marked Branch Taken instruction completed."
+ },
+ {
+ "EventCode": "20112",
+ "EventName": "PM_MRK_NTF_FIN",
+ "BriefDescription": "The marked instruction became the oldest in the pipeline before it finished. It excludes instructions that finish at dispatch."
+ },
+ {
+ "EventCode": "2C01C",
+ "EventName": "PM_EXEC_STALL_DMISS_OFF_CHIP",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a remote chip."
+ },
+ {
+ "EventCode": "20138",
+ "EventName": "PM_MRK_ST_NEST",
+ "BriefDescription": "A store has been sampled/marked and is at the point of execution where it has completed in the core and can no longer be flushed. At this point the store is sent to the L2."
+ },
+ {
+ "EventCode": "2013A",
+ "EventName": "PM_MRK_BRU_FIN",
+ "BriefDescription": "Marked Branch instruction finished."
+ },
+ {
+ "EventCode": "2C144",
+ "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC2",
+ "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[15:27]."
+ },
+ {
+ "EventCode": "24156",
+ "EventName": "PM_MRK_STCX_FIN",
+ "BriefDescription": "Marked conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."
+ },
+ {
+ "EventCode": "24158",
+ "EventName": "PM_MRK_INST",
+ "BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens."
+ },
+ {
+ "EventCode": "2415C",
+ "EventName": "PM_MRK_BR_CMPL",
+ "BriefDescription": "A marked branch completed. All branches are included."
+ },
+ {
+ "EventCode": "200FD",
+ "EventName": "PM_L1_ICACHE_MISS",
+ "BriefDescription": "Demand iCache Miss."
+ },
+ {
+ "EventCode": "30130",
+ "EventName": "PM_MRK_INST_FIN",
+ "BriefDescription": "marked instruction finished. Excludes instructions that finish at dispatch. Note that stores always finish twice since the address gets issued to the LSU and the data gets issued to the VSU."
+ },
+ {
+ "EventCode": "34146",
+ "EventName": "PM_MRK_LD_CMPL",
+ "BriefDescription": "Marked loads completed."
+ },
+ {
+ "EventCode": "3E158",
+ "EventName": "PM_MRK_STCX_FAIL",
+ "BriefDescription": "Marked conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock."
+ },
+ {
+ "EventCode": "3E15A",
+ "EventName": "PM_MRK_ST_FIN",
+ "BriefDescription": "The marked instruction was a store of any kind."
+ },
+ {
+ "EventCode": "30068",
+ "EventName": "PM_L1_ICACHE_RELOADED_PREF",
+ "BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)."
+ },
+ {
+ "EventCode": "301E4",
+ "EventName": "PM_MRK_BR_MPRED_CMPL",
+ "BriefDescription": "Marked Branch Mispredicted. Includes direction and target."
+ },
+ {
+ "EventCode": "300F6",
+ "EventName": "PM_LD_DEMAND_MISS_L1",
+ "BriefDescription": "The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish."
+ },
+ {
+ "EventCode": "300FE",
+ "EventName": "PM_DATA_FROM_L3MISS",
+ "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."
+ },
+ {
+ "EventCode": "40012",
+ "EventName": "PM_L1_ICACHE_RELOADED_ALL",
+ "BriefDescription": "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch."
+ },
+ {
+ "EventCode": "40134",
+ "EventName": "PM_MRK_INST_TIMEO",
+ "BriefDescription": "Marked instruction finish timeout (instruction was lost)."
+ },
+ {
+ "EventCode": "4003C",
+ "EventName": "PM_DISP_STALL_HELD_SYNC_CYC",
+ "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch."
+ },
+ {
+ "EventCode": "4505A",
+ "EventName": "PM_SP_FLOP_CMPL",
+ "BriefDescription": "Single Precision floating point instructions completed."
+ },
+ {
+ "EventCode": "4D058",
+ "EventName": "PM_VECTOR_FLOP_CMPL",
+ "BriefDescription": "Vector floating point instructions completed."
+ },
+ {
+ "EventCode": "4D05A",
+ "EventName": "PM_NON_MATH_FLOP_CMPL",
+ "BriefDescription": "Non Math instructions completed."
+ },
+ {
+ "EventCode": "401E0",
+ "EventName": "PM_MRK_INST_CMPL",
+ "BriefDescription": "marked instruction completed."
+ },
+ {
+ "EventCode": "400FE",
+ "EventName": "PM_DATA_FROM_MEMORY",
+ "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss."
+ }
+]
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/memory.json b/tools/perf/pmu-events/arch/powerpc/power10/memory.json
new file mode 100644
index 000000000000..6e47b96e2d66
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/memory.json
@@ -0,0 +1,192 @@
+[
+ {
+ "EventCode": "1000A",
+ "EventName": "PM_PMC3_REWIND",
+ "BriefDescription": "The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged."
+ },
+ {
+ "EventCode": "1C040",
+ "EventName": "PM_XFER_FROM_SRC_PMC1",
+ "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
+ },
+ {
+ "EventCode": "1C142",
+ "EventName": "PM_MRK_XFER_FROM_SRC_PMC1",
+ "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
+ },
+ {
+ "EventCode": "1C144",
+ "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1",
+ "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]."
+ },
+ {
+ "EventCode": "1C056",
+ "EventName": "PM_DERAT_MISS_4K",
+ "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "1C058",
+ "EventName": "PM_DTLB_MISS_16G",
+ "BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "1C05C",
+ "EventName": "PM_DTLB_MISS_2M",
+ "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "1E056",
+ "EventName": "PM_EXEC_STALL_STORE_PIPE",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions."
+ },
+ {
+ "EventCode": "1F150",
+ "EventName": "PM_MRK_ST_L2_CYC",
+ "BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion."
+ },
+ {
+ "EventCode": "10062",
+ "EventName": "PM_LD_L3MISS_PEND_CYC",
+ "BriefDescription": "Cycles L3 miss was pending for this thread."
+ },
+ {
+ "EventCode": "20010",
+ "EventName": "PM_PMC1_OVERFLOW",
+ "BriefDescription": "The event selected for PMC1 caused the event counter to overflow."
+ },
+ {
+ "EventCode": "2001A",
+ "EventName": "PM_ITLB_HIT",
+ "BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "2003E",
+ "EventName": "PM_PTESYNC_FIN",
+ "BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time."
+ },
+ {
+ "EventCode": "2C040",
+ "EventName": "PM_XFER_FROM_SRC_PMC2",
+ "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
+ },
+ {
+ "EventCode": "2C054",
+ "EventName": "PM_DERAT_MISS_64K",
+ "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "2C056",
+ "EventName": "PM_DTLB_MISS_4K",
+ "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "2D154",
+ "EventName": "PM_MRK_DERAT_MISS_64K",
+ "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "200F6",
+ "EventName": "PM_DERAT_MISS",
+ "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "3000A",
+ "EventName": "PM_DISP_STALL_ITLB_MISS",
+ "BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction TLB miss."
+ },
+ {
+ "EventCode": "30016",
+ "EventName": "PM_EXEC_STALL_DERAT_DTLB_MISS",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve."
+ },
+ {
+ "EventCode": "3C040",
+ "EventName": "PM_XFER_FROM_SRC_PMC3",
+ "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
+ },
+ {
+ "EventCode": "3C142",
+ "EventName": "PM_MRK_XFER_FROM_SRC_PMC3",
+ "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
+ },
+ {
+ "EventCode": "3C144",
+ "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC3",
+ "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]."
+ },
+ {
+ "EventCode": "3C054",
+ "EventName": "PM_DERAT_MISS_16M",
+ "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "3C056",
+ "EventName": "PM_DTLB_MISS_64K",
+ "BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "3C058",
+ "EventName": "PM_LARX_FIN",
+ "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
+ },
+ {
+ "EventCode": "301E2",
+ "EventName": "PM_MRK_ST_CMPL",
+ "BriefDescription": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores."
+ },
+ {
+ "EventCode": "300FC",
+ "EventName": "PM_DTLB_MISS",
+ "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity."
+ },
+ {
+ "EventCode": "4D02C",
+ "EventName": "PM_PMC1_REWIND",
+ "BriefDescription": "The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged."
+ },
+ {
+ "EventCode": "4003E",
+ "EventName": "PM_LD_CMPL",
+ "BriefDescription": "Loads completed."
+ },
+ {
+ "EventCode": "4C040",
+ "EventName": "PM_XFER_FROM_SRC_PMC4",
+ "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
+ },
+ {
+ "EventCode": "4C142",
+ "EventName": "PM_MRK_XFER_FROM_SRC_PMC4",
+ "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
+ },
+ {
+ "EventCode": "4C144",
+ "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC4",
+ "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]."
+ },
+ {
+ "EventCode": "4C056",
+ "EventName": "PM_DTLB_MISS_16M",
+ "BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "4C05A",
+ "EventName": "PM_DTLB_MISS_1G",
+ "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "4C15E",
+ "EventName": "PM_MRK_DTLB_MISS_64K",
+ "BriefDescription": "Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "4D056",
+ "EventName": "PM_NON_FMA_FLOP_CMPL",
+ "BriefDescription": "Non FMA instruction completed."
+ },
+ {
+ "EventCode": "40164",
+ "EventName": "PM_MRK_DERAT_MISS_2M",
+ "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ }
+]
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/others.json b/tools/perf/pmu-events/arch/powerpc/power10/others.json
new file mode 100644
index 000000000000..2992f7961134
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/others.json
@@ -0,0 +1,297 @@
+[
+ {
+ "EventCode": "10016",
+ "EventName": "PM_VSU0_ISSUE",
+ "BriefDescription": "VSU instructions issued to VSU pipe 0."
+ },
+ {
+ "EventCode": "1001C",
+ "EventName": "PM_ULTRAVISOR_INST_CMPL",
+ "BriefDescription": "PowerPC instructions that completed while the thread was in ultravisor state."
+ },
+ {
+ "EventCode": "100F0",
+ "EventName": "PM_CYC",
+ "BriefDescription": "Processor cycles."
+ },
+ {
+ "EventCode": "10134",
+ "EventName": "PM_MRK_ST_DONE_L2",
+ "BriefDescription": "Marked stores completed in L2 (RC machine done)."
+ },
+ {
+ "EventCode": "1505E",
+ "EventName": "PM_LD_HIT_L1",
+ "BriefDescription": "Loads that finished without experiencing an L1 miss."
+ },
+ {
+ "EventCode": "1D05E",
+ "EventName": "PM_DISP_STALL_HELD_HALT_CYC",
+ "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of power management."
+ },
+ {
+ "EventCode": "1E054",
+ "EventName": "PM_EXEC_STALL_DMISS_L21_L31",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip."
+ },
+ {
+ "EventCode": "1E05A",
+ "EventName": "PM_CMPL_STALL_LWSYNC",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting to complete."
+ },
+ {
+ "EventCode": "1F056",
+ "EventName": "PM_DISP_SS0_2_INSTR_CYC",
+ "BriefDescription": "Cycles in which Superslice 0 dispatches either 1 or 2 instructions."
+ },
+ {
+ "EventCode": "1F15C",
+ "EventName": "PM_MRK_STCX_L2_CYC",
+ "BriefDescription": "Cycles spent in the nest portion of a marked Stcx instruction. It starts counting when the operation starts to drain to the L2 and it stops counting when the instruction retires from the Instruction Completion Table (ICT) in the Instruction Sequencing Unit (ISU)."
+ },
+ {
+ "EventCode": "10066",
+ "EventName": "PM_ADJUNCT_CYC",
+ "BriefDescription": "Cycles in which the thread is in Adjunct state. MSR[S HV PR] bits = 011."
+ },
+ {
+ "EventCode": "101E4",
+ "EventName": "PM_MRK_L1_ICACHE_MISS",
+ "BriefDescription": "Marked Instruction suffered an icache Miss."
+ },
+ {
+ "EventCode": "101EA",
+ "EventName": "PM_MRK_L1_RELOAD_VALID",
+ "BriefDescription": "Marked demand reload."
+ },
+ {
+ "EventCode": "100F4",
+ "EventName": "PM_FLOP_CMPL",
+ "BriefDescription": "Floating Point Operations Completed. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1|2|4|8_FLOP_CMPL events to count flops."
+ },
+ {
+ "EventCode": "100FA",
+ "EventName": "PM_RUN_LATCH_ANY_THREAD_CYC",
+ "BriefDescription": "Cycles when at least one thread has the run latch set."
+ },
+ {
+ "EventCode": "100FC",
+ "EventName": "PM_LD_REF_L1",
+ "BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included."
+ },
+ {
+ "EventCode": "20006",
+ "EventName": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC",
+ "BriefDescription": "Cycles in which the NTC instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue."
+ },
+ {
+ "EventCode": "2000C",
+ "EventName": "PM_RUN_LATCH_ALL_THREADS_CYC",
+ "BriefDescription": "Cycles when the run latch is set for all threads."
+ },
+ {
+ "EventCode": "2E010",
+ "EventName": "PM_ADJUNCT_INST_CMPL",
+ "BriefDescription": "PowerPC instructions that completed while the thread is in Adjunct state."
+ },
+ {
+ "EventCode": "2E014",
+ "EventName": "PM_STCX_FIN",
+ "BriefDescription": "Conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."
+ },
+ {
+ "EventCode": "20130",
+ "EventName": "PM_MRK_INST_DECODED",
+ "BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only."
+ },
+ {
+ "EventCode": "20132",
+ "EventName": "PM_MRK_DFU_ISSUE",
+ "BriefDescription": "The marked instruction was a decimal floating point operation issued to the VSU. Measured at issue time."
+ },
+ {
+ "EventCode": "20134",
+ "EventName": "PM_MRK_FXU_ISSUE",
+ "BriefDescription": "The marked instruction was a fixed point operation issued to the VSU. Measured at issue time."
+ },
+ {
+ "EventCode": "2505C",
+ "EventName": "PM_VSU_ISSUE",
+ "BriefDescription": "At least one VSU instruction was issued to one of the VSU pipes. Up to 4 per cycle. Includes fixed point operations."
+ },
+ {
+ "EventCode": "2F054",
+ "EventName": "PM_DISP_SS1_2_INSTR_CYC",
+ "BriefDescription": "Cycles in which Superslice 1 dispatches either 1 or 2 instructions."
+ },
+ {
+ "EventCode": "2F056",
+ "EventName": "PM_DISP_SS1_4_INSTR_CYC",
+ "BriefDescription": "Cycles in which Superslice 1 dispatches either 3 or 4 instructions."
+ },
+ {
+ "EventCode": "2006C",
+ "EventName": "PM_RUN_CYC_SMT4_MODE",
+ "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT4 mode."
+ },
+ {
+ "EventCode": "201E0",
+ "EventName": "PM_MRK_DATA_FROM_MEMORY",
+ "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked load."
+ },
+ {
+ "EventCode": "201E4",
+ "EventName": "PM_MRK_DATA_FROM_L3MISS",
+ "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked load."
+ },
+ {
+ "EventCode": "201E8",
+ "EventName": "PM_THRESH_EXC_512",
+ "BriefDescription": "Threshold counter exceeded a value of 512."
+ },
+ {
+ "EventCode": "200F2",
+ "EventName": "PM_INST_DISP",
+ "BriefDescription": "PowerPC instructions dispatched."
+ },
+ {
+ "EventCode": "30132",
+ "EventName": "PM_MRK_VSU_FIN",
+ "BriefDescription": "VSU marked instructions finished. Excludes simple FX instructions issued to the Store Unit."
+ },
+ {
+ "EventCode": "30038",
+ "EventName": "PM_EXEC_STALL_DMISS_LMEM",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCapp cache, or local OpenCapp memory."
+ },
+ {
+ "EventCode": "3F04A",
+ "EventName": "PM_LSU_ST5_FIN",
+ "BriefDescription": "LSU Finished an internal operation in ST2 port."
+ },
+ {
+ "EventCode": "34054",
+ "EventName": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict."
+ },
+ {
+ "EventCode": "3405A",
+ "EventName": "PM_PRIVILEGED_INST_CMPL",
+ "BriefDescription": "PowerPC Instructions that completed while the thread is in Privileged state."
+ },
+ {
+ "EventCode": "3F150",
+ "EventName": "PM_MRK_ST_DRAIN_CYC",
+ "BriefDescription": "cycles to drain st from core to L2."
+ },
+ {
+ "EventCode": "3F054",
+ "EventName": "PM_DISP_SS0_4_INSTR_CYC",
+ "BriefDescription": "Cycles in which Superslice 0 dispatches either 3 or 4 instructions."
+ },
+ {
+ "EventCode": "3F056",
+ "EventName": "PM_DISP_SS0_8_INSTR_CYC",
+ "BriefDescription": "Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions."
+ },
+ {
+ "EventCode": "30162",
+ "EventName": "PM_MRK_ISSUE_DEPENDENT_LOAD",
+ "BriefDescription": "The marked instruction was dependent on a load. It is eligible for issue kill."
+ },
+ {
+ "EventCode": "40114",
+ "EventName": "PM_MRK_START_PROBE_NOP_DISP",
+ "BriefDescription": "Marked Start probe nop dispatched. Instruction AND R0,R0,R0."
+ },
+ {
+ "EventCode": "4001C",
+ "EventName": "PM_VSU_FIN",
+ "BriefDescription": "VSU instructions finished."
+ },
+ {
+ "EventCode": "4C01A",
+ "EventName": "PM_EXEC_STALL_DMISS_OFF_NODE",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a distant chip."
+ },
+ {
+ "EventCode": "4D012",
+ "EventName": "PM_PMC3_SAVED",
+ "BriefDescription": "The conditions for the speculative event selected for PMC3 are met and PMC3 is charged."
+ },
+ {
+ "EventCode": "4D022",
+ "EventName": "PM_HYPERVISOR_INST_CMPL",
+ "BriefDescription": "PowerPC instructions that completed while the thread is in hypervisor state."
+ },
+ {
+ "EventCode": "4D026",
+ "EventName": "PM_ULTRAVISOR_CYC",
+ "BriefDescription": "Cycles when the thread is in Ultravisor state. MSR[S HV PR]=110."
+ },
+ {
+ "EventCode": "4D028",
+ "EventName": "PM_PRIVILEGED_CYC",
+ "BriefDescription": "Cycles when the thread is in Privileged state. MSR[S HV PR]=x00."
+ },
+ {
+ "EventCode": "40030",
+ "EventName": "PM_INST_FIN",
+ "BriefDescription": "Instructions finished."
+ },
+ {
+ "EventCode": "44146",
+ "EventName": "PM_MRK_STCX_CORE_CYC",
+ "BriefDescription": "Cycles spent in the core portion of a marked Stcx instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2."
+ },
+ {
+ "EventCode": "44054",
+ "EventName": "PM_VECTOR_LD_CMPL",
+ "BriefDescription": "Vector load instructions completed."
+ },
+ {
+ "EventCode": "45054",
+ "EventName": "PM_FMA_CMPL",
+ "BriefDescription": "Two floating point instructions completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only."
+ },
+ {
+ "EventCode": "45056",
+ "EventName": "PM_SCALAR_FLOP_CMPL",
+ "BriefDescription": "Scalar floating point instructions completed."
+ },
+ {
+ "EventCode": "4505C",
+ "EventName": "PM_MATH_FLOP_CMPL",
+ "BriefDescription": "Math floating point instructions completed."
+ },
+ {
+ "EventCode": "4D05E",
+ "EventName": "PM_BR_CMPL",
+ "BriefDescription": "A branch completed. All branches are included."
+ },
+ {
+ "EventCode": "4E15E",
+ "EventName": "PM_MRK_INST_FLUSHED",
+ "BriefDescription": "The marked instruction was flushed."
+ },
+ {
+ "EventCode": "401E6",
+ "EventName": "PM_MRK_INST_FROM_L3MISS",
+ "BriefDescription": "The processor's instruction cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked instruction."
+ },
+ {
+ "EventCode": "401E8",
+ "EventName": "PM_MRK_DATA_FROM_L2MISS",
+ "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1 or L2 due to a demand miss for a marked load."
+ },
+ {
+ "EventCode": "400F0",
+ "EventName": "PM_LD_DEMAND_MISS_L1_FIN",
+ "BriefDescription": "Load Missed L1, counted at finish time."
+ },
+ {
+ "EventCode": "400FA",
+ "EventName": "PM_RUN_INST_CMPL",
+ "BriefDescription": "Completed PowerPC instructions gated by the run latch."
+ }
+]
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json b/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
new file mode 100644
index 000000000000..33c1c39ea323
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
@@ -0,0 +1,297 @@
+[
+ {
+ "EventCode": "100FE",
+ "EventName": "PM_INST_CMPL",
+ "BriefDescription": "PowerPC instructions completed."
+ },
+ {
+ "EventCode": "10006",
+ "EventName": "PM_DISP_STALL_HELD_OTHER_CYC",
+ "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any other reason."
+ },
+ {
+ "EventCode": "1000C",
+ "EventName": "PM_LSU_LD0_FIN",
+ "BriefDescription": "LSU Finished an internal operation in LD0 port."
+ },
+ {
+ "EventCode": "1000E",
+ "EventName": "PM_MMA_ISSUED",
+ "BriefDescription": "MMA instructions issued."
+ },
+ {
+ "EventCode": "10012",
+ "EventName": "PM_LSU_ST0_FIN",
+ "BriefDescription": "LSU Finished an internal operation in ST0 port."
+ },
+ {
+ "EventCode": "10014",
+ "EventName": "PM_LSU_ST4_FIN",
+ "BriefDescription": "LSU Finished an internal operation in ST4 port."
+ },
+ {
+ "EventCode": "10018",
+ "EventName": "PM_IC_DEMAND_CYC",
+ "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss."
+ },
+ {
+ "EventCode": "10022",
+ "EventName": "PM_PMC2_SAVED",
+ "BriefDescription": "The conditions for the speculative event selected for PMC2 are met and PMC2 is charged."
+ },
+ {
+ "EventCode": "10024",
+ "EventName": "PM_PMC5_OVERFLOW",
+ "BriefDescription": "The event selected for PMC5 caused the event counter to overflow."
+ },
+ {
+ "EventCode": "10058",
+ "EventName": "PM_EXEC_STALL_FIN_AT_DISP",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch and did not require execution in the LSU, BRU or VSU."
+ },
+ {
+ "EventCode": "1005A",
+ "EventName": "PM_FLUSH_MPRED",
+ "BriefDescription": "A flush occurred due to a mispredicted branch. Includes target and direction."
+ },
+ {
+ "EventCode": "1C05A",
+ "EventName": "PM_DERAT_MISS_2M",
+ "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
+ },
+ {
+ "EventCode": "10064",
+ "EventName": "PM_DISP_STALL_IC_L2",
+ "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2."
+ },
+ {
+ "EventCode": "10068",
+ "EventName": "PM_BR_FIN",
+ "BriefDescription": "A branch instruction finished. Includes predicted/mispredicted/unconditional."
+ },
+ {
+ "EventCode": "1006A",
+ "EventName": "PM_FX_LSU_FIN",
+ "BriefDescription": "Simple fixed point instruction issued to the store unit. Measured at finish time."
+ },
+ {
+ "EventCode": "1006C",
+ "EventName": "PM_RUN_CYC_ST_MODE",
+ "BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
+ },
+ {
+ "EventCode": "20004",
+ "EventName": "PM_ISSUE_STALL",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not issued yet."
+ },
+ {
+ "EventCode": "2000A",
+ "EventName": "PM_HYPERVISOR_CYC",
+ "BriefDescription": "Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010."
+ },
+ {
+ "EventCode": "2000E",
+ "EventName": "PM_LSU_LD1_FIN",
+ "BriefDescription": "LSU Finished an internal operation in LD1 port."
+ },
+ {
+ "EventCode": "2C014",
+ "EventName": "PM_CMPL_STALL_SPECIAL",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handling before completing."
+ },
+ {
+ "EventCode": "2C018",
+ "EventName": "PM_EXEC_STALL_DMISS_L3MISS",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a source beyond the local L2 or local L3."
+ },
+ {
+ "EventCode": "2D010",
+ "EventName": "PM_LSU_ST1_FIN",
+ "BriefDescription": "LSU Finished an internal operation in ST1 port."
+ },
+ {
+ "EventCode": "2D012",
+ "EventName": "PM_VSU1_ISSUE",
+ "BriefDescription": "VSU instructions issued to VSU pipe 1."
+ },
+ {
+ "EventCode": "2D018",
+ "EventName": "PM_EXEC_STALL_VSU",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the VSU (includes FXU, VSU, CRU)."
+ },
+ {
+ "EventCode": "2E01E",
+ "EventName": "PM_EXEC_STALL_NTC_FLUSH",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in any unit before it was flushed. Note that if the flush of the oldest instruction happens after finish, the cycles from dispatch to issue will be included in PM_DISP_STALL and the cycles from issue to finish will be included in PM_EXEC_STALL and its corresponding children."
+ },
+ {
+ "EventCode": "2013C",
+ "EventName": "PM_MRK_FX_LSU_FIN",
+ "BriefDescription": "The marked instruction was simple fixed point that was issued to the store unit. Measured at finish time."
+ },
+ {
+ "EventCode": "2405A",
+ "EventName": "PM_NTC_FIN",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note that instructions can finish out of order, therefore not all the instructions that finish have a Next-to-complete status."
+ },
+ {
+ "EventCode": "201E2",
+ "EventName": "PM_MRK_LD_MISS_L1",
+ "BriefDescription": "Marked DL1 Demand Miss counted at finish time."
+ },
+ {
+ "EventCode": "200F4",
+ "EventName": "PM_RUN_CYC",
+ "BriefDescription": "Processor cycles gated by the run latch."
+ },
+ {
+ "EventCode": "30004",
+ "EventName": "PM_DISP_STALL_FLUSH",
+ "BriefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet NTC. PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC."
+ },
+ {
+ "EventCode": "30008",
+ "EventName": "PM_EXEC_STALL",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting to finish in one of the execution units (BRU, LSU, VSU). Only cycles between issue and finish are counted in this category."
+ },
+ {
+ "EventCode": "3001A",
+ "EventName": "PM_LSU_ST2_FIN",
+ "BriefDescription": "LSU Finished an internal operation in ST2 port."
+ },
+ {
+ "EventCode": "30020",
+ "EventName": "PM_PMC2_REWIND",
+ "BriefDescription": "The speculative event selected for PMC2 rewinds and the counter for PMC2 is not charged."
+ },
+ {
+ "EventCode": "30022",
+ "EventName": "PM_PMC4_SAVED",
+ "BriefDescription": "The conditions for the speculative event selected for PMC4 are met and PMC4 is charged."
+ },
+ {
+ "EventCode": "30024",
+ "EventName": "PM_PMC6_OVERFLOW",
+ "BriefDescription": "The event selected for PMC6 caused the event counter to overflow."
+ },
+ {
+ "EventCode": "30028",
+ "EventName": "PM_CMPL_STALL_MEM_ECC",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC."
+ },
+ {
+ "EventCode": "30036",
+ "EventName": "PM_EXEC_STALL_SIMPLE_FX",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a simple fixed point instruction executing in the Load Store Unit."
+ },
+ {
+ "EventCode": "3003A",
+ "EventName": "PM_CMPL_STALL_EXCEPTION",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete."
+ },
+ {
+ "EventCode": "3F044",
+ "EventName": "PM_VSU2_ISSUE",
+ "BriefDescription": "VSU instructions issued to VSU pipe 2."
+ },
+ {
+ "EventCode": "30058",
+ "EventName": "PM_TLBIE_FIN",
+ "BriefDescription": "TLBIE instructions finished in the LSU. Two TLBIEs can finish each cycle. All will be counted."
+ },
+ {
+ "EventCode": "3D058",
+ "EventName": "PM_SCALAR_FSQRT_FDIV_ISSUE",
+ "BriefDescription": "Scalar versions of four floating point operations: fdiv,fsqrt (xvdivdp, xvdivsp, xvsqrtdp, xvsqrtsp)."
+ },
+ {
+ "EventCode": "30066",
+ "EventName": "PM_LSU_FIN",
+ "BriefDescription": "LSU Finished an internal operation (up to 4 per cycle)."
+ },
+ {
+ "EventCode": "40004",
+ "EventName": "PM_FXU_ISSUE",
+ "BriefDescription": "A fixed point instruction was issued to the VSU."
+ },
+ {
+ "EventCode": "40008",
+ "EventName": "PM_NTC_ALL_FIN",
+ "BriefDescription": "Cycles in which both instructions in the ICT entry pair show as finished. These are the cycles between finish and completion for the oldest pair of instructions in the pipeline."
+ },
+ {
+ "EventCode": "40010",
+ "EventName": "PM_PMC3_OVERFLOW",
+ "BriefDescription": "The event selected for PMC3 caused the event counter to overflow."
+ },
+ {
+ "EventCode": "4C012",
+ "EventName": "PM_EXEC_STALL_DERAT_ONLY_MISS",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered an ERAT miss and waited for it resolve."
+ },
+ {
+ "EventCode": "4C018",
+ "EventName": "PM_CMPL_STALL",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline cannot complete because the thread was blocked for any reason."
+ },
+ {
+ "EventCode": "4C01E",
+ "EventName": "PM_LSU_ST3_FIN",
+ "BriefDescription": "LSU Finished an internal operation in ST3 port."
+ },
+ {
+ "EventCode": "4D018",
+ "EventName": "PM_EXEC_STALL_BRU",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Branch unit."
+ },
+ {
+ "EventCode": "4D01A",
+ "EventName": "PM_CMPL_STALL_HWSYNC",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a hwsync waiting for response from L2 before completing."
+ },
+ {
+ "EventCode": "4D01C",
+ "EventName": "PM_EXEC_STALL_TLBIEL",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIEL instruction executing in the Load Store Unit. TLBIEL instructions have lower overhead than TLBIE instructions because they don't get set to the nest."
+ },
+ {
+ "EventCode": "4E012",
+ "EventName": "PM_EXEC_STALL_UNKNOWN",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline completed without an ntf_type pulse. The ntf_pulse was missed by the ISU because the NTF finishes and completions came too close together."
+ },
+ {
+ "EventCode": "4D020",
+ "EventName": "PM_VSU3_ISSUE",
+ "BriefDescription": "VSU instruction was issued to VSU pipe 3."
+ },
+ {
+ "EventCode": "40132",
+ "EventName": "PM_MRK_LSU_FIN",
+ "BriefDescription": "LSU marked instruction finish."
+ },
+ {
+ "EventCode": "45058",
+ "EventName": "PM_IC_MISS_CMPL",
+ "BriefDescription": "Non-speculative icache miss, counted at completion."
+ },
+ {
+ "EventCode": "4D050",
+ "EventName": "PM_VSU_NON_FLOP_CMPL",
+ "BriefDescription": "Non-floating point VSU instructions completed."
+ },
+ {
+ "EventCode": "4D052",
+ "EventName": "PM_2FLOP_CMPL",
+ "BriefDescription": "Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg completed."
+ },
+ {
+ "EventCode": "400F2",
+ "EventName": "PM_1PLUS_PPC_DISP",
+ "BriefDescription": "Cycles at least one Instr Dispatched."
+ },
+ {
+ "EventCode": "400F8",
+ "EventName": "PM_FLUSH",
+ "BriefDescription": "Flush (any type)."
+ }
+]
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/pmc.json b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json
new file mode 100644
index 000000000000..60a0100ee996
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json
@@ -0,0 +1,22 @@
+[
+ {
+ "EventCode": "301E8",
+ "EventName": "PM_THRESH_EXC_64",
+ "BriefDescription": "Threshold counter exceeded a value of 64."
+ },
+ {
+ "EventCode": "45050",
+ "EventName": "PM_1FLOP_CMPL",
+ "BriefDescription": "One floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
+ },
+ {
+ "EventCode": "45052",
+ "EventName": "PM_4FLOP_CMPL",
+ "BriefDescription": "Four floating point instructions completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
+ },
+ {
+ "EventCode": "4D054",
+ "EventName": "PM_8FLOP_CMPL",
+ "BriefDescription": "Four Double Precision vector instructions completed."
+ }
+]
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/translation.json b/tools/perf/pmu-events/arch/powerpc/power10/translation.json
new file mode 100644
index 000000000000..da44d4ca6ef3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/translation.json
@@ -0,0 +1,57 @@
+[
+ {
+ "EventCode": "1F15E",
+ "EventName": "PM_MRK_START_PROBE_NOP_CMPL",
+ "BriefDescription": "Marked Start probe nop (AND R0,R0,R0) completed."
+ },
+ {
+ "EventCode": "20016",
+ "EventName": "PM_ST_FIN",
+ "BriefDescription": "Store finish count. Includes speculative activity."
+ },
+ {
+ "EventCode": "20018",
+ "EventName": "PM_ST_FWD",
+ "BriefDescription": "Store forwards that finished."
+ },
+ {
+ "EventCode": "2011C",
+ "EventName": "PM_MRK_NTF_CYC",
+ "BriefDescription": "Cycles during which the marked instruction is the oldest in the pipeline (NTF or NTC)."
+ },
+ {
+ "EventCode": "2E01C",
+ "EventName": "PM_EXEC_STALL_TLBIE",
+ "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIE instruction executing in the Load Store Unit."
+ },
+ {
+ "EventCode": "201E6",
+ "EventName": "PM_THRESH_EXC_32",
+ "BriefDescription": "Threshold counter exceeded a value of 32."
+ },
+ {
+ "EventCode": "200F0",
+ "EventName": "PM_ST_CMPL",
+ "BriefDescription": "Stores completed from S2Q (2nd-level store queue). This event includes regular stores, stcx and cache inhibited stores. The following operations are excluded (pteupdate, snoop tlbie complete, store atomics, miso, load atomic payloads, tlbie, tlbsync, slbieg, isync, msgsnd, slbiag, cpabort, copy, tcheck, tend, stsync, dcbst, icbi, dcbf, hwsync, lwsync, ptesync, eieio, msgsync)."
+ },
+ {
+ "EventCode": "200FE",
+ "EventName": "PM_DATA_FROM_L2MISS",
+ "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1 or L2 due to a demand miss."
+ },
+ {
+ "EventCode": "30010",
+ "EventName": "PM_PMC2_OVERFLOW",
+ "BriefDescription": "The event selected for PMC2 caused the event counter to overflow."
+ },
+ {
+ "EventCode": "4D010",
+ "EventName": "PM_PMC1_SAVED",
+ "BriefDescription": "The conditions for the speculative event selected for PMC1 are met and PMC1 is charged."
+ },
+ {
+ "EventCode": "4D05C",
+ "EventName": "PM_DPP_FLOP_CMPL",
+ "BriefDescription": "Double-Precision or Quad-Precision instructions completed."
+ }
+]
--
2.27.0
^ permalink raw reply related
* Re: [PATCH V2] mm/page_alloc: Ensure that HUGETLB_PAGE_ORDER is less than MAX_ORDER
From: Christoph Lameter @ 2021-04-19 10:48 UTC (permalink / raw)
To: Anshuman Khandual
Cc: linux-ia64@vger.kernel.org, David Hildenbrand, Mel Gorman,
linux-kernel, Michal Hocko, linux-mm, akpm,
linuxppc-dev @ lists . ozlabs . org, Vlastimil Babka
In-Reply-To: <ce4f9838-da4b-1423-4123-23c0941a2198@arm.com>
[-- Attachment #1: Type: text/plain, Size: 2460 bytes --]
On Mon, 19 Apr 2021, Anshuman Khandual wrote:
> >> Unfortunately the build test fails on both the platforms (powerpc and ia64)
> >> which subscribe HUGETLB_PAGE_SIZE_VARIABLE and where this check would make
> >> sense. I some how overlooked the cross compile build failure that actually
> >> detected this problem.
> >>
> >> But wondering why this assert is not holding true ? and how these platforms
> >> do not see the warning during boot (or do they ?) at mm/vmscan.c:1092 like
> >> arm64 did.
> >>
> >> static int __fragmentation_index(unsigned int order, struct contig_page_info *info)
> >> {
> >> unsigned long requested = 1UL << order;
> >>
> >> if (WARN_ON_ONCE(order >= MAX_ORDER))
> >> return 0;
> >> ....
> >>
> >> Can pageblock_order really exceed MAX_ORDER - 1 ?
You can have larger blocks but you would need to allocate multiple
contigous max order blocks or do it at boot time before the buddy
allocator is active.
What IA64 did was to do this at boot time thereby avoiding the buddy
lists. And it had a separate virtual address range and page table for the
huge pages.
Looks like the current code does these allocations via CMA which should
also bypass the buddy allocator.
> > }
> >
> >
> > But it's kind of weird, isn't it? Let's assume we have MAX_ORDER - 1 correspond to 4 MiB and pageblock_order correspond to 8 MiB.
> >
> > Sure, we'd be grouping pages in 8 MiB chunks, however, we cannot even
> > allocate 8 MiB chunks via the buddy. So only alloc_contig_range()
> > could really grab them (IOW: gigantic pages).
>
> Right.
But then you can avoid the buddy allocator.
> > Further, we have code like deferred_free_range(), where we end up
> > calling __free_pages_core()->...->__free_one_page() with
> > pageblock_order. Wouldn't we end up setting the buddy order to
> > something > MAX_ORDER -1 on that path?
>
> Agreed.
We would need to return the supersized block to the huge page pool and not
to the buddy allocator. There is a special callback in the compound page
sos that you can call an alternate free function that is not the buddy
allocator.
>
> >
> > Having pageblock_order > MAX_ORDER feels wrong and looks shaky.
> >
> Agreed, definitely does not look right. Lets see what other folks
> might have to say on this.
>
> + Christoph Lameter <cl@linux.com>
>
It was done for a long time successfully and is running in numerous
configurations.
^ permalink raw reply
* [PATCH v2 3/4] powerpc/mm: Properly coalesce pages in ptdump
From: Christophe Leroy @ 2021-04-19 10:47 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Steven Price, akpm, dja
Cc: linux-arch, linuxppc-dev, Oliver O'Halloran, linux-kernel,
linux-mm
In-Reply-To: <cover.1618828806.git.christophe.leroy@csgroup.eu>
Commit aaa229529244 ("powerpc/mm: Add physical address to Linux page
table dump") changed range coalescing to only combine ranges that are
both virtually and physically contiguous, in order to avoid erroneous
combination of unrelated mappings in IOREMAP space.
But in the VMALLOC space, mappings almost never have contiguous
physical pages, so the commit mentionned above leads to dumping one
line per page for vmalloc mappings.
Taking into account the vmalloc always leave a gap between two areas,
we never have two mappings dumped as a single combination even if they
have the exact same flags. The only space that may have encountered
such an issue was the early IOREMAP which is not using vmalloc engine.
But previous commits added gaps between early IO mappings, so it is
not an issue anymore.
That commit created some difficulties with KASAN mappings, see
commit cabe8138b23c ("powerpc: dump as a single line areas mapping a
single physical page.") and with huge page, see
commit b00ff6d8c1c3 ("powerpc/ptdump: Properly handle non standard
page size").
So, almost revert commit aaa229529244 to properly coalesce pages
mapped with the same flags as before, only keep the display of the
first physical address of the range, as it can be usefull especially
for IO mappings.
It brings back powerpc at the same level as other architectures and
simplifies the conversion to GENERIC PTDUMP.
With the patch:
---[ kasan shadow mem start ]---
0xf8000000-0xf8ffffff 0x07000000 16M huge rw present dirty accessed
0xf9000000-0xf91fffff 0x01434000 2M r present accessed
0xf9200000-0xf95affff 0x02104000 3776K rw present dirty accessed
0xfef5c000-0xfeffffff 0x01434000 656K r present accessed
---[ kasan shadow mem end ]---
Before:
---[ kasan shadow mem start ]---
0xf8000000-0xf8ffffff 0x07000000 16M huge rw present dirty accessed
0xf9000000-0xf91fffff 0x01434000 16K r present accessed
0xf9200000-0xf9203fff 0x02104000 16K rw present dirty accessed
0xf9204000-0xf9207fff 0x0213c000 16K rw present dirty accessed
0xf9208000-0xf920bfff 0x02174000 16K rw present dirty accessed
0xf920c000-0xf920ffff 0x02188000 16K rw present dirty accessed
0xf9210000-0xf9213fff 0x021dc000 16K rw present dirty accessed
0xf9214000-0xf9217fff 0x02220000 16K rw present dirty accessed
0xf9218000-0xf921bfff 0x023c0000 16K rw present dirty accessed
0xf921c000-0xf921ffff 0x023d4000 16K rw present dirty accessed
0xf9220000-0xf9227fff 0x023ec000 32K rw present dirty accessed
...
0xf93b8000-0xf93e3fff 0x02614000 176K rw present dirty accessed
0xf93e4000-0xf94c3fff 0x027c0000 896K rw present dirty accessed
0xf94c4000-0xf94c7fff 0x0236c000 16K rw present dirty accessed
0xf94c8000-0xf94cbfff 0x041f0000 16K rw present dirty accessed
0xf94cc000-0xf94cffff 0x029c0000 16K rw present dirty accessed
0xf94d0000-0xf94d3fff 0x041ec000 16K rw present dirty accessed
0xf94d4000-0xf94d7fff 0x0407c000 16K rw present dirty accessed
0xf94d8000-0xf94f7fff 0x041c0000 128K rw present dirty accessed
...
0xf95ac000-0xf95affff 0x042b0000 16K rw present dirty accessed
0xfef5c000-0xfeffffff 0x01434000 16K r present accessed
---[ kasan shadow mem end ]---
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Oliver O'Halloran <oohall@gmail.com>
---
arch/powerpc/mm/ptdump/ptdump.c | 22 +++-------------------
1 file changed, 3 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/ptdump.c b/arch/powerpc/mm/ptdump/ptdump.c
index aca354fb670b..5062c58b1e5b 100644
--- a/arch/powerpc/mm/ptdump/ptdump.c
+++ b/arch/powerpc/mm/ptdump/ptdump.c
@@ -58,8 +58,6 @@ struct pg_state {
const struct addr_marker *marker;
unsigned long start_address;
unsigned long start_pa;
- unsigned long last_pa;
- unsigned long page_size;
unsigned int level;
u64 current_flags;
bool check_wx;
@@ -163,8 +161,6 @@ static void dump_flag_info(struct pg_state *st, const struct flag_info
static void dump_addr(struct pg_state *st, unsigned long addr)
{
- unsigned long delta;
-
#ifdef CONFIG_PPC64
#define REG "0x%016lx"
#else
@@ -172,14 +168,8 @@ static void dump_addr(struct pg_state *st, unsigned long addr)
#endif
pt_dump_seq_printf(st->seq, REG "-" REG " ", st->start_address, addr - 1);
- if (st->start_pa == st->last_pa && st->start_address + st->page_size != addr) {
- pt_dump_seq_printf(st->seq, "[" REG "]", st->start_pa);
- delta = st->page_size >> 10;
- } else {
- pt_dump_seq_printf(st->seq, " " REG " ", st->start_pa);
- delta = (addr - st->start_address) >> 10;
- }
- pt_dump_size(st->seq, delta);
+ pt_dump_seq_printf(st->seq, " " REG " ", st->start_pa);
+ pt_dump_size(st->seq, (addr - st->start_address) >> 10);
}
static void note_prot_wx(struct pg_state *st, unsigned long addr)
@@ -208,7 +198,6 @@ static void note_page_update_state(struct pg_state *st, unsigned long addr,
st->current_flags = flag;
st->start_address = addr;
st->start_pa = pa;
- st->page_size = page_size;
while (addr >= st->marker[1].start_address) {
st->marker++;
@@ -220,7 +209,6 @@ static void note_page(struct pg_state *st, unsigned long addr,
unsigned int level, u64 val, unsigned long page_size)
{
u64 flag = val & pg_level[level].mask;
- u64 pa = val & PTE_RPN_MASK;
/* At first no level is set */
if (!st->level) {
@@ -232,12 +220,9 @@ static void note_page(struct pg_state *st, unsigned long addr,
* - we change levels in the tree.
* - the address is in a different section of memory and is thus
* used for a different purpose, regardless of the flags.
- * - the pa of this page is not adjacent to the last inspected page
*/
} else if (flag != st->current_flags || level != st->level ||
- addr >= st->marker[1].start_address ||
- (pa != st->last_pa + st->page_size &&
- (pa != st->start_pa || st->start_pa != st->last_pa))) {
+ addr >= st->marker[1].start_address) {
/* Check the PTE flags */
if (st->current_flags) {
@@ -259,7 +244,6 @@ static void note_page(struct pg_state *st, unsigned long addr,
*/
note_page_update_state(st, addr, level, val, page_size);
}
- st->last_pa = pa;
}
static void walk_pte(struct pg_state *st, pmd_t *pmd, unsigned long start)
--
2.25.0
^ permalink raw reply related
* [PATCH v2 4/4] powerpc/mm: Convert powerpc to GENERIC_PTDUMP
From: Christophe Leroy @ 2021-04-19 10:47 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Steven Price, akpm, dja
Cc: linux-arch, linuxppc-dev, Oliver O'Halloran, linux-kernel,
linux-mm
In-Reply-To: <cover.1618828806.git.christophe.leroy@csgroup.eu>
This patch converts powerpc to the generic PTDUMP implementation.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/Kconfig | 2 +
arch/powerpc/Kconfig.debug | 30 ------
arch/powerpc/mm/Makefile | 2 +-
arch/powerpc/mm/mmu_decl.h | 2 +-
arch/powerpc/mm/ptdump/8xx.c | 6 +-
arch/powerpc/mm/ptdump/Makefile | 9 +-
arch/powerpc/mm/ptdump/book3s64.c | 6 +-
arch/powerpc/mm/ptdump/ptdump.c | 165 ++++++++----------------------
arch/powerpc/mm/ptdump/shared.c | 6 +-
9 files changed, 68 insertions(+), 160 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 475d77a6ebbe..40259437a28f 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -120,6 +120,7 @@ config PPC
select ARCH_32BIT_OFF_T if PPC32
select ARCH_HAS_DEBUG_VIRTUAL
select ARCH_HAS_DEBUG_VM_PGTABLE
+ select ARCH_HAS_DEBUG_WX if STRICT_KERNEL_RWX
select ARCH_HAS_DEVMEM_IS_ALLOWED
select ARCH_HAS_ELF_RANDOMIZE
select ARCH_HAS_FORTIFY_SOURCE
@@ -177,6 +178,7 @@ config PPC
select GENERIC_IRQ_SHOW
select GENERIC_IRQ_SHOW_LEVEL
select GENERIC_PCI_IOMAP if PCI
+ select GENERIC_PTDUMP
select GENERIC_SMP_IDLE_THREAD
select GENERIC_STRNCPY_FROM_USER
select GENERIC_STRNLEN_USER
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 6342f9da4545..05b1180ea502 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -360,36 +360,6 @@ config FAIL_IOMMU
If you are unsure, say N.
-config PPC_PTDUMP
- bool "Export kernel pagetable layout to userspace via debugfs"
- depends on DEBUG_KERNEL && DEBUG_FS
- help
- This option exports the state of the kernel pagetables to a
- debugfs file. This is only useful for kernel developers who are
- working in architecture specific areas of the kernel - probably
- not a good idea to enable this feature in a production kernel.
-
- If you are unsure, say N.
-
-config PPC_DEBUG_WX
- bool "Warn on W+X mappings at boot"
- depends on PPC_PTDUMP && STRICT_KERNEL_RWX
- help
- Generate a warning if any W+X mappings are found at boot.
-
- This is useful for discovering cases where the kernel is leaving
- W+X mappings after applying NX, as such mappings are a security risk.
-
- Note that even if the check fails, your kernel is possibly
- still fine, as W+X mappings are not a security hole in
- themselves, what they do is that they make the exploitation
- of other unfixed kernel bugs easier.
-
- There is no runtime or memory usage effect of this option
- once the kernel has booted up - it's a one time check.
-
- If in doubt, say "Y".
-
config PPC_FAST_ENDIAN_SWITCH
bool "Deprecated fast endian-switch syscall"
depends on DEBUG_KERNEL && PPC_BOOK3S_64
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index c3df3a8501d4..c90d58aaebe2 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -18,5 +18,5 @@ obj-$(CONFIG_PPC_MM_SLICES) += slice.o
obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o
obj-$(CONFIG_PPC_COPRO_BASE) += copro_fault.o
-obj-$(CONFIG_PPC_PTDUMP) += ptdump/
+obj-$(CONFIG_PTDUMP_CORE) += ptdump/
obj-$(CONFIG_KASAN) += kasan/
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 7dac910c0b21..dd1cabc2ea0f 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -180,7 +180,7 @@ static inline void mmu_mark_rodata_ro(void) { }
void __init mmu_mapin_immr(void);
#endif
-#ifdef CONFIG_PPC_DEBUG_WX
+#ifdef CONFIG_DEBUG_WX
void ptdump_check_wx(void);
#else
static inline void ptdump_check_wx(void) { }
diff --git a/arch/powerpc/mm/ptdump/8xx.c b/arch/powerpc/mm/ptdump/8xx.c
index 86da2a669680..fac932eb8f9a 100644
--- a/arch/powerpc/mm/ptdump/8xx.c
+++ b/arch/powerpc/mm/ptdump/8xx.c
@@ -75,8 +75,10 @@ static const struct flag_info flag_array[] = {
};
struct pgtable_level pg_level[5] = {
- {
- }, { /* pgd */
+ { /* pgd */
+ .flag = flag_array,
+ .num = ARRAY_SIZE(flag_array),
+ }, { /* p4d */
.flag = flag_array,
.num = ARRAY_SIZE(flag_array),
}, { /* pud */
diff --git a/arch/powerpc/mm/ptdump/Makefile b/arch/powerpc/mm/ptdump/Makefile
index 712762be3cb1..4050cbb55acf 100644
--- a/arch/powerpc/mm/ptdump/Makefile
+++ b/arch/powerpc/mm/ptdump/Makefile
@@ -5,5 +5,10 @@ obj-y += ptdump.o
obj-$(CONFIG_4xx) += shared.o
obj-$(CONFIG_PPC_8xx) += 8xx.o
obj-$(CONFIG_PPC_BOOK3E_MMU) += shared.o
-obj-$(CONFIG_PPC_BOOK3S_32) += shared.o bats.o segment_regs.o
-obj-$(CONFIG_PPC_BOOK3S_64) += book3s64.o hashpagetable.o
+obj-$(CONFIG_PPC_BOOK3S_32) += shared.o
+obj-$(CONFIG_PPC_BOOK3S_64) += book3s64.o
+
+ifdef CONFIG_PTDUMP_DEBUGFS
+obj-$(CONFIG_PPC_BOOK3S_32) += bats.o segment_regs.o
+obj-$(CONFIG_PPC_BOOK3S_64) += hashpagetable.o
+endif
diff --git a/arch/powerpc/mm/ptdump/book3s64.c b/arch/powerpc/mm/ptdump/book3s64.c
index 14f73868db66..5ad92d9dc5d1 100644
--- a/arch/powerpc/mm/ptdump/book3s64.c
+++ b/arch/powerpc/mm/ptdump/book3s64.c
@@ -103,8 +103,10 @@ static const struct flag_info flag_array[] = {
};
struct pgtable_level pg_level[5] = {
- {
- }, { /* pgd */
+ { /* pgd */
+ .flag = flag_array,
+ .num = ARRAY_SIZE(flag_array),
+ }, { /* p4d */
.flag = flag_array,
.num = ARRAY_SIZE(flag_array),
}, { /* pud */
diff --git a/arch/powerpc/mm/ptdump/ptdump.c b/arch/powerpc/mm/ptdump/ptdump.c
index 5062c58b1e5b..57d1270689c6 100644
--- a/arch/powerpc/mm/ptdump/ptdump.c
+++ b/arch/powerpc/mm/ptdump/ptdump.c
@@ -16,6 +16,7 @@
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/highmem.h>
+#include <linux/ptdump.h>
#include <linux/sched.h>
#include <linux/seq_file.h>
#include <asm/fixmap.h>
@@ -54,11 +55,12 @@
*
*/
struct pg_state {
+ struct ptdump_state ptdump;
struct seq_file *seq;
const struct addr_marker *marker;
unsigned long start_address;
unsigned long start_pa;
- unsigned int level;
+ int level;
u64 current_flags;
bool check_wx;
unsigned long wx_pages;
@@ -189,9 +191,9 @@ static void note_prot_wx(struct pg_state *st, unsigned long addr)
}
static void note_page_update_state(struct pg_state *st, unsigned long addr,
- unsigned int level, u64 val, unsigned long page_size)
+ unsigned int level, u64 val)
{
- u64 flag = val & pg_level[level].mask;
+ u64 flag = level >= 0 ? val & pg_level[level].mask : 0;
u64 pa = val & PTE_RPN_MASK;
st->level = level;
@@ -205,15 +207,15 @@ static void note_page_update_state(struct pg_state *st, unsigned long addr,
}
}
-static void note_page(struct pg_state *st, unsigned long addr,
- unsigned int level, u64 val, unsigned long page_size)
+static void note_page(struct ptdump_state *pt_st, unsigned long addr, int level, u64 val)
{
- u64 flag = val & pg_level[level].mask;
+ u64 flag = level >= 0 ? val & pg_level[level].mask : 0;
+ struct pg_state *st = container_of(pt_st, struct pg_state, ptdump);
/* At first no level is set */
- if (!st->level) {
+ if (st->level == -1) {
pt_dump_seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
- note_page_update_state(st, addr, level, val, page_size);
+ note_page_update_state(st, addr, level, val);
/*
* Dump the section of virtual memory when:
* - the PTE flags from one entry to the next differs.
@@ -242,95 +244,7 @@ static void note_page(struct pg_state *st, unsigned long addr,
* Address indicates we have passed the end of the
* current section of virtual memory
*/
- note_page_update_state(st, addr, level, val, page_size);
- }
-}
-
-static void walk_pte(struct pg_state *st, pmd_t *pmd, unsigned long start)
-{
- pte_t *pte = pte_offset_kernel(pmd, 0);
- unsigned long addr;
- unsigned int i;
-
- for (i = 0; i < PTRS_PER_PTE; i++, pte++) {
- addr = start + i * PAGE_SIZE;
- note_page(st, addr, 4, pte_val(*pte), PAGE_SIZE);
-
- }
-}
-
-static void walk_hugepd(struct pg_state *st, hugepd_t *phpd, unsigned long start,
- int pdshift, int level)
-{
-#ifdef CONFIG_ARCH_HAS_HUGEPD
- unsigned int i;
- int shift = hugepd_shift(*phpd);
- int ptrs_per_hpd = pdshift - shift > 0 ? 1 << (pdshift - shift) : 1;
-
- if (start & ((1 << shift) - 1))
- return;
-
- for (i = 0; i < ptrs_per_hpd; i++) {
- unsigned long addr = start + (i << shift);
- pte_t *pte = hugepte_offset(*phpd, addr, pdshift);
-
- note_page(st, addr, level + 1, pte_val(*pte), 1 << shift);
- }
-#endif
-}
-
-static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start)
-{
- pmd_t *pmd = pmd_offset(pud, 0);
- unsigned long addr;
- unsigned int i;
-
- for (i = 0; i < PTRS_PER_PMD; i++, pmd++) {
- addr = start + i * PMD_SIZE;
- if (!pmd_none(*pmd) && !pmd_is_leaf(*pmd))
- /* pmd exists */
- walk_pte(st, pmd, addr);
- else
- note_page(st, addr, 3, pmd_val(*pmd), PMD_SIZE);
- }
-}
-
-static void walk_pud(struct pg_state *st, p4d_t *p4d, unsigned long start)
-{
- pud_t *pud = pud_offset(p4d, 0);
- unsigned long addr;
- unsigned int i;
-
- for (i = 0; i < PTRS_PER_PUD; i++, pud++) {
- addr = start + i * PUD_SIZE;
- if (!pud_none(*pud) && !pud_is_leaf(*pud))
- /* pud exists */
- walk_pmd(st, pud, addr);
- else
- note_page(st, addr, 2, pud_val(*pud), PUD_SIZE);
- }
-}
-
-static void walk_pagetables(struct pg_state *st)
-{
- unsigned int i;
- unsigned long addr = st->start_address & PGDIR_MASK;
- pgd_t *pgd = pgd_offset_k(addr);
-
- /*
- * Traverse the linux pagetable structure and dump pages that are in
- * the hash pagetable.
- */
- for (i = pgd_index(addr); i < PTRS_PER_PGD; i++, pgd++, addr += PGDIR_SIZE) {
- p4d_t *p4d = p4d_offset(pgd, 0);
-
- if (p4d_none(*p4d) || p4d_is_leaf(*p4d))
- note_page(st, addr, 1, p4d_val(*p4d), PGDIR_SIZE);
- else if (is_hugepd(__hugepd(p4d_val(*p4d))))
- walk_hugepd(st, (hugepd_t *)p4d, addr, PGDIR_SHIFT, 1);
- else
- /* p4d exists */
- walk_pud(st, p4d, addr);
+ note_page_update_state(st, addr, level, val);
}
}
@@ -383,32 +297,29 @@ static int ptdump_show(struct seq_file *m, void *v)
struct pg_state st = {
.seq = m,
.marker = address_markers,
- .start_address = IS_ENABLED(CONFIG_PPC64) ? PAGE_OFFSET : TASK_SIZE,
+ .level = -1,
+ .ptdump = {
+ .note_page = note_page,
+ .range = (struct ptdump_range[]){
+ {TASK_SIZE, ~0UL},
+ {0, 0}
+ }
+ }
};
#ifdef CONFIG_PPC64
if (!radix_enabled())
- st.start_address = KERN_VIRT_START;
+ st.ptdump.range.start = KERN_VIRT_START;
+ else
+ st.ptdump.range.start = PAGE_OFFSET;
#endif
/* Traverse kernel page tables */
- walk_pagetables(&st);
- note_page(&st, 0, 0, 0, 0);
+ ptdump_walk_pgd(&st.ptdump, &init_mm, NULL);
return 0;
}
-
-static int ptdump_open(struct inode *inode, struct file *file)
-{
- return single_open(file, ptdump_show, NULL);
-}
-
-static const struct file_operations ptdump_fops = {
- .open = ptdump_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
+DEFINE_SHOW_ATTRIBUTE(ptdump);
static void build_pgtable_complete_mask(void)
{
@@ -420,22 +331,34 @@ static void build_pgtable_complete_mask(void)
pg_level[i].mask |= pg_level[i].flag[j].mask;
}
-#ifdef CONFIG_PPC_DEBUG_WX
+#ifdef CONFIG_DEBUG_WX
void ptdump_check_wx(void)
{
struct pg_state st = {
.seq = NULL,
- .marker = address_markers,
+ .marker = (struct addr_marker[]) {
+ { 0, NULL},
+ { -1, NULL},
+ },
+ .level = -1,
.check_wx = true,
- .start_address = IS_ENABLED(CONFIG_PPC64) ? PAGE_OFFSET : TASK_SIZE,
+ .ptdump = {
+ .note_page = note_page,
+ .range = (struct ptdump_range[]){
+ {TASK_SIZE, ~0UL},
+ {0, 0}
+ }
+ }
};
#ifdef CONFIG_PPC64
if (!radix_enabled())
- st.start_address = KERN_VIRT_START;
+ st.ptdump.range.start = KERN_VIRT_START;
+ else
+ st.ptdump.range.start = PAGE_OFFSET;
#endif
- walk_pagetables(&st);
+ ptdump_walk_pgd(&st.ptdump, &init_mm, NULL);
if (st.wx_pages)
pr_warn("Checked W+X mappings: FAILED, %lu W+X pages found\n",
@@ -449,8 +372,10 @@ static int ptdump_init(void)
{
populate_markers();
build_pgtable_complete_mask();
- debugfs_create_file("kernel_page_tables", 0400, NULL, NULL,
- &ptdump_fops);
+
+ if (IS_ENABLED(CONFIG_PTDUMP_DEBUGFS))
+ debugfs_create_file("kernel_page_tables", 0400, NULL, NULL, &ptdump_fops);
+
return 0;
}
device_initcall(ptdump_init);
diff --git a/arch/powerpc/mm/ptdump/shared.c b/arch/powerpc/mm/ptdump/shared.c
index c005fe041c18..03607ab90c66 100644
--- a/arch/powerpc/mm/ptdump/shared.c
+++ b/arch/powerpc/mm/ptdump/shared.c
@@ -68,8 +68,10 @@ static const struct flag_info flag_array[] = {
};
struct pgtable_level pg_level[5] = {
- {
- }, { /* pgd */
+ { /* pgd */
+ .flag = flag_array,
+ .num = ARRAY_SIZE(flag_array),
+ }, { /* p4d */
.flag = flag_array,
.num = ARRAY_SIZE(flag_array),
}, { /* pud */
--
2.25.0
^ permalink raw reply related
* [PATCH v2 1/4] mm: pagewalk: Fix walk for hugepage tables
From: Christophe Leroy @ 2021-04-19 10:47 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Steven Price, akpm, dja
Cc: linux-arch, linuxppc-dev, Oliver O'Halloran, linux-kernel,
linux-mm
In-Reply-To: <cover.1618828806.git.christophe.leroy@csgroup.eu>
Pagewalk ignores hugepd entries and walk down the tables
as if it was traditionnal entries, leading to crazy result.
Add walk_hugepd_range() and use it to walk hugepage tables.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
v2:
- Add a guard for NULL ops->pte_entry
- Take mm->page_table_lock when walking hugepage table, as suggested by follow_huge_pd()
---
mm/pagewalk.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 53 insertions(+), 5 deletions(-)
diff --git a/mm/pagewalk.c b/mm/pagewalk.c
index e81640d9f177..9b3db11a4d1d 100644
--- a/mm/pagewalk.c
+++ b/mm/pagewalk.c
@@ -58,6 +58,45 @@ static int walk_pte_range(pmd_t *pmd, unsigned long addr, unsigned long end,
return err;
}
+#ifdef CONFIG_ARCH_HAS_HUGEPD
+static int walk_hugepd_range(hugepd_t *phpd, unsigned long addr,
+ unsigned long end, struct mm_walk *walk, int pdshift)
+{
+ int err = 0;
+ const struct mm_walk_ops *ops = walk->ops;
+ int shift = hugepd_shift(*phpd);
+ int page_size = 1 << shift;
+
+ if (!ops->pte_entry)
+ return 0;
+
+ if (addr & (page_size - 1))
+ return 0;
+
+ for (;;) {
+ pte_t *pte;
+
+ spin_lock(&walk->mm->page_table_lock);
+ pte = hugepte_offset(*phpd, addr, pdshift);
+ err = ops->pte_entry(pte, addr, addr + page_size, walk);
+ spin_unlock(&walk->mm->page_table_lock);
+
+ if (err)
+ break;
+ if (addr >= end - page_size)
+ break;
+ addr += page_size;
+ }
+ return err;
+}
+#else
+static int walk_hugepd_range(hugepd_t *phpd, unsigned long addr,
+ unsigned long end, struct mm_walk *walk, int pdshift)
+{
+ return 0;
+}
+#endif
+
static int walk_pmd_range(pud_t *pud, unsigned long addr, unsigned long end,
struct mm_walk *walk)
{
@@ -108,7 +147,10 @@ static int walk_pmd_range(pud_t *pud, unsigned long addr, unsigned long end,
goto again;
}
- err = walk_pte_range(pmd, addr, next, walk);
+ if (is_hugepd(__hugepd(pmd_val(*pmd))))
+ err = walk_hugepd_range((hugepd_t *)pmd, addr, next, walk, PMD_SHIFT);
+ else
+ err = walk_pte_range(pmd, addr, next, walk);
if (err)
break;
} while (pmd++, addr = next, addr != end);
@@ -157,7 +199,10 @@ static int walk_pud_range(p4d_t *p4d, unsigned long addr, unsigned long end,
if (pud_none(*pud))
goto again;
- err = walk_pmd_range(pud, addr, next, walk);
+ if (is_hugepd(__hugepd(pud_val(*pud))))
+ err = walk_hugepd_range((hugepd_t *)pud, addr, next, walk, PUD_SHIFT);
+ else
+ err = walk_pmd_range(pud, addr, next, walk);
if (err)
break;
} while (pud++, addr = next, addr != end);
@@ -189,7 +234,9 @@ static int walk_p4d_range(pgd_t *pgd, unsigned long addr, unsigned long end,
if (err)
break;
}
- if (ops->pud_entry || ops->pmd_entry || ops->pte_entry)
+ if (is_hugepd(__hugepd(p4d_val(*p4d))))
+ err = walk_hugepd_range((hugepd_t *)p4d, addr, next, walk, P4D_SHIFT);
+ else if (ops->pud_entry || ops->pmd_entry || ops->pte_entry)
err = walk_pud_range(p4d, addr, next, walk);
if (err)
break;
@@ -224,8 +271,9 @@ static int walk_pgd_range(unsigned long addr, unsigned long end,
if (err)
break;
}
- if (ops->p4d_entry || ops->pud_entry || ops->pmd_entry ||
- ops->pte_entry)
+ if (is_hugepd(__hugepd(pgd_val(*pgd))))
+ err = walk_hugepd_range((hugepd_t *)pgd, addr, next, walk, PGDIR_SHIFT);
+ else if (ops->p4d_entry || ops->pud_entry || ops->pmd_entry || ops->pte_entry)
err = walk_p4d_range(pgd, addr, next, walk);
if (err)
break;
--
2.25.0
^ permalink raw reply related
* [PATCH v2 0/4] Convert powerpc to GENERIC_PTDUMP
From: Christophe Leroy @ 2021-04-19 10:47 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Steven Price, akpm, dja
Cc: linux-arch, linuxppc-dev, Oliver O'Halloran, linux-kernel,
linux-mm
This series converts powerpc to generic PTDUMP.
For that, we first need to add missing hugepd support
to pagewalk and ptdump.
v2:
- Reworked the pagewalk modification to add locking and check ops->pte_entry
- Modified powerpc early IO mapping to have gaps between mappings
- Removed the logic that checked for contiguous physical memory
- Removed the articial level calculation in ptdump_pte_entry(), level 4 is ok for all.
- Removed page_size argument to note_page()
Christophe Leroy (4):
mm: pagewalk: Fix walk for hugepage tables
powerpc/mm: Leave a gap between early allocated IO areas
powerpc/mm: Properly coalesce pages in ptdump
powerpc/mm: Convert powerpc to GENERIC_PTDUMP
arch/powerpc/Kconfig | 2 +
arch/powerpc/Kconfig.debug | 30 -----
arch/powerpc/mm/Makefile | 2 +-
arch/powerpc/mm/ioremap_32.c | 4 +-
arch/powerpc/mm/ioremap_64.c | 2 +-
arch/powerpc/mm/mmu_decl.h | 2 +-
arch/powerpc/mm/ptdump/8xx.c | 6 +-
arch/powerpc/mm/ptdump/Makefile | 9 +-
arch/powerpc/mm/ptdump/book3s64.c | 6 +-
arch/powerpc/mm/ptdump/ptdump.c | 187 ++++++++----------------------
arch/powerpc/mm/ptdump/shared.c | 6 +-
mm/pagewalk.c | 58 ++++++++-
12 files changed, 127 insertions(+), 187 deletions(-)
--
2.25.0
^ permalink raw reply
* [PATCH v2 2/4] powerpc/mm: Leave a gap between early allocated IO areas
From: Christophe Leroy @ 2021-04-19 10:47 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Steven Price, akpm, dja
Cc: linux-arch, linuxppc-dev, Oliver O'Halloran, linux-kernel,
linux-mm
In-Reply-To: <cover.1618828806.git.christophe.leroy@csgroup.eu>
Vmalloc system leaves a gap between allocated areas. It helps catching
overflows.
Do the same for IO areas which are allocated with early_ioremap_range()
until slab_is_available().
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/mm/ioremap_32.c | 4 ++--
arch/powerpc/mm/ioremap_64.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/ioremap_32.c b/arch/powerpc/mm/ioremap_32.c
index 743e11384dea..9d13143b8be4 100644
--- a/arch/powerpc/mm/ioremap_32.c
+++ b/arch/powerpc/mm/ioremap_32.c
@@ -70,10 +70,10 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, pgprot_t prot, void *call
*/
pr_warn("ioremap() called early from %pS. Use early_ioremap() instead\n", caller);
- err = early_ioremap_range(ioremap_bot - size, p, size, prot);
+ err = early_ioremap_range(ioremap_bot - size - PAGE_SIZE, p, size, prot);
if (err)
return NULL;
- ioremap_bot -= size;
+ ioremap_bot -= size + PAGE_SIZE;
return (void __iomem *)ioremap_bot + offset;
}
diff --git a/arch/powerpc/mm/ioremap_64.c b/arch/powerpc/mm/ioremap_64.c
index ba5cbb0d66bd..3acece00b33e 100644
--- a/arch/powerpc/mm/ioremap_64.c
+++ b/arch/powerpc/mm/ioremap_64.c
@@ -38,7 +38,7 @@ void __iomem *__ioremap_caller(phys_addr_t addr, unsigned long size,
return NULL;
ret = (void __iomem *)ioremap_bot + offset;
- ioremap_bot += size;
+ ioremap_bot += size + PAGE_SIZE;
return ret;
}
--
2.25.0
^ permalink raw reply related
* Re: [PATCH] perf vendor events: Initial json/events list for power10 platform
From: kajoljain @ 2021-04-19 10:25 UTC (permalink / raw)
To: Paul A. Clarke
Cc: ravi.bangoria, atrajeev, linuxppc-dev, linux-kernel, acme,
linux-perf-users, maddy, jolsa
In-Reply-To: <20210418210838.GA1845018@li-24c3614c-2adc-11b2-a85c-85f334518bdb.ibm.com>
On 4/19/21 2:38 AM, Paul A. Clarke wrote:
> On Sat, Apr 17, 2021 at 02:48:50PM +0530, Kajol Jain wrote:
>> Patch adds initial json/events for POWER10.
>
> I was able to apply, build, and run perf with these changes,
> and every new event at least ran successfully with
> `perf stat`.
>
> Pedantically, there is a lot of inconsistency as to whether
> the `BriefDescription` ends with a period or not, and whether
> there is an extra space at the end.
Hi Paul,
Thanks for reviewing the patch. Sure I will remove this inconsistency
and send v2 patch for the same, with your Tested-by and Reviewed-by tag.
Thanks,
Kajol Jain
>
> Regardless, LGTM.
>
> Tested-by: Paul A. Clarke <pc@us.ibm.com>
> Reviewed-by: Paul A. Clarke <pc@us.ibm.com>
>
> PC
>
^ permalink raw reply
* Re: [RFC v1 PATCH 3/3] driver: update all the code that use soc_device_match
From: Dominique MARTINET @ 2021-04-19 9:33 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: ulf.hansson, aymen.sghaier, geert+renesas, rafael, airlied,
mturquette, dri-devel, linux-kernel, a.hajda, netdev, linux-phy,
peter.ujfalusi, linux-clk, linux-renesas-soc, wim, herbert,
horia.geanta, khilman, joro, narmstrong, linux-staging, iommu,
kishon, tony, linux-omap, stern, kuba, linus.walleij, linux,
linux-media, linux-watchdog, will, linux-pm, linuxppc-dev,
edubezval, linux-gpio, linux-mediatek, ssantosh, matthias.bgg,
linux-amlogic, mchehab, linux-arm-kernel, Alice Guo (OSS), balbi,
tomba, sboyd, gregkh, linux-usb, linux-mmc, adrian.hunter,
robert.foss, leoyang.li, linux, vkoul, Arnd Bergmann,
linux-crypto, daniel, j-keerthy, dmaengine, Roy.Pledge,
jyri.sarha, davem
In-Reply-To: <CAMuHMdVY1SLZ0K30T2pimyrR6Mm=VoSTO=L-xxCy2Bj7_kostw@mail.gmail.com>
Geert Uytterhoeven wrote on Mon, Apr 19, 2021 at 11:03:24AM +0200:
> > This is going to need quite some more work to be acceptable, in my
> > opinion, but I think it should be possible.
>
> In general, this is very hard to do, IMHO. Some drivers may be used on
> multiple platforms, some of them registering an SoC device, some of
> them not registering an SoC device. So there is no way to know the
> difference between "SoC device not registered, intentionally", and
> "SoC device not yet registered".
Hm, good point, I was probably a bit too optimistic if there are devices
which don't register any soc yet have drivers which want one; I don't
see how to make the difference indeed... And that does mean we can't
just defer all the time.
> soc_device_match() should only be used as a last resort, to identify
> systems that cannot be identified otherwise. Typically this is used for
> quirks, which should only be enabled on a very specific subset of
> systems. IMHO such systems should make sure soc_device_match()
> is available early, by registering their SoC device early.
I definitely agree there, my suggestion to defer was only because I know
of no other way to influence the ordering of drivers loading reliably
and gave up on soc being init'd early.
In this particular case the problem is that since 7d981405d0fd ("soc:
imx8m: change to use platform driver") the soc probe tries to use the
nvmem driver for ocotp fuses for imx8m devices, which isn't ready yet.
So soc loading gets pushed back to the end of the list because it gets
defered and other drivers relying on soc_device_match get confused
because they wrongly think a device doesn't match a quirk when it
actually does.
If there is a way to ensure the nvmem driver gets loaded before the soc,
that would also solve the problem nicely, and avoid the need to mess
with all the ~50 drivers which use it.
Is there a way to control in what order drivers get loaded? Something in
the dtb perhaps?
Thanks,
--
Dominique
^ permalink raw reply
* Re: linux-next: build failure after merge of the powerpc tree
From: Xiongwei Song @ 2021-04-19 9:59 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Linux Next Mailing List, PowerPC, Linux Kernel Mailing List
In-Reply-To: <20210419191425.281dc58a@canb.auug.org.au>
Thank you so much Stephen. Sorry for my negligence.
Should I fix this myself on powerpc tree?
Regards,
Xiongwei
On Mon, Apr 19, 2021 at 5:14 PM Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>
> Hi all,
>
> After merging the powerpc tree, today's linux-next build (powerpc
> allyesconfig) failed like this:
>
> arch/powerpc/kernel/fadump.c: In function 'crash_fadump':
> arch/powerpc/kernel/fadump.c:731:28: error: 'INTERRUPT_SYSTEM_RESET' undeclared (first use in this function)
> 731 | if (TRAP(&(fdh->regs)) == INTERRUPT_SYSTEM_RESET) {
> | ^~~~~~~~~~~~~~~~~~~~~~
> arch/powerpc/kernel/fadump.c:731:28: note: each undeclared identifier is reported only once for each function it appears in
>
> Caused by commit
>
> 7153d4bf0b37 ("powerpc/traps: Enhance readability for trap types")
>
> I have applied the following patch for today.
>
> From: Stephen Rothwell <sfr@canb.auug.org.au>
> Date: Mon, 19 Apr 2021 19:05:05 +1000
> Subject: [PATCH] fix up for "powerpc/traps: Enhance readability for trap types"
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
> ---
> arch/powerpc/kernel/fadump.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c
> index b55b4c23f3b6..000e3b7f3fca 100644
> --- a/arch/powerpc/kernel/fadump.c
> +++ b/arch/powerpc/kernel/fadump.c
> @@ -31,6 +31,7 @@
> #include <asm/fadump.h>
> #include <asm/fadump-internal.h>
> #include <asm/setup.h>
> +#include <asm/interrupt.h>
>
> /*
> * The CPU who acquired the lock to trigger the fadump crash should
> --
> 2.30.2
>
> --
> Cheers,
> Stephen Rothwell
^ permalink raw reply
* Re: [PATCH] ASoC: fsl: imx-pcm-dma: Don't request dma channel in probe
From: Lucas Stach @ 2021-04-19 9:46 UTC (permalink / raw)
To: Robin Gong, Shengjiu Wang
Cc: Nicolin Chen, Linux-ALSA, Liam Girdwood, s.hauer@pengutronix.de,
Timur Tabi, Xiubo Li, shawnguo@kernel.org, S.j. Wang,
linux-kernel, dri-devel@lists.freedesktop.org, Takashi Iwai,
linaro-mm-sig@lists.linaro.org, Mark Brown, dl-linux-imx,
kernel@pengutronix.de, Fabio Estevam, perex@perex.cz,
linuxppc-dev@lists.ozlabs.org, sumit.semwal@linaro.org,
linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org
In-Reply-To: <VE1PR04MB6638EE85485768351755557B89499@VE1PR04MB6638.eurprd04.prod.outlook.com>
Am Montag, dem 19.04.2021 um 07:17 +0000 schrieb Robin Gong:
> Hi Lucas,
>
> On 2021/04/14 Lucas Stach <l.stach@pengutronix.de> wrote:
> > Hi Robin,
> >
> > Am Mittwoch, dem 14.04.2021 um 14:33 +0000 schrieb Robin Gong:
> > > On 2020/05/20 17:43 Lucas Stach <l.stach@pengutronix.de> wrote:
> > > > Am Mittwoch, den 20.05.2020, 16:20 +0800 schrieb Shengjiu Wang:
> > > > > Hi
> > > > >
> > > > > On Tue, May 19, 2020 at 6:04 PM Lucas Stach
> > > > > <l.stach@pengutronix.de>
> > > > wrote:
> > > > > > Am Dienstag, den 19.05.2020, 17:41 +0800 schrieb Shengjiu Wang:
> > > > > > > There are two requirements that we need to move the request of
> > > > > > > dma channel from probe to open.
> > > > > >
> > > > > > How do you handle -EPROBE_DEFER return code from the channel
> > > > > > request if you don't do it in probe?
> > > > >
> > > > > I use the dma_request_slave_channel or dma_request_channel instead
> > > > > of dmaengine_pcm_request_chan_of. so there should be not
> > > > > -EPROBE_DEFER return code.
> > > >
> > > > This is a pretty weak argument. The dmaengine device might probe
> > > > after you try to get the channel. Using a function to request the
> > > > channel that doesn't allow you to handle probe deferral is IMHO a
> > > > bug and should be fixed, instead of building even more assumptions on top
> > of it.
> > > >
> > > > > > > - When dma device binds with power-domains, the power will be
> > > > > > > enabled when we request dma channel. If the request of dma
> > > > > > > channel happen on probe, then the power-domains will be always
> > > > > > > enabled after kernel boot up, which is not good for power
> > > > > > > saving, so we need to move the request of dma channel to
> > > > > > > .open();
> > > > > >
> > > > > > This is certainly something which could be fixed in the
> > > > > > dmaengine driver.
> > > > >
> > > > > Dma driver always call the pm_runtime_get_sync in
> > > > > device_alloc_chan_resources, the device_alloc_chan_resources is
> > > > > called when channel is requested. so power is enabled on channel
> > request.
> > > >
> > > > So why can't you fix the dmaengine driver to do that RPM call at a
> > > > later time when the channel is actually going to be used? This will
> > > > allow further power savings with other slave devices than the audio PCM.
> > > Hi Lucas,
> > > Thanks for your suggestion. I have tried to implement runtime
> > > autosuspend in fsl-edma driver on i.mx8qm/qxp with delay time (2 sec)
> > > for this feature as below (or you can refer to
> > > drivers/dma/qcom/hidma.c), and pm_runtime_get_sync/
> > > pm_runtime_put_autosuspend in all dmaengine driver interface like
> > > device_alloc_chan_resources/device_prep_slave_sg/device_prep_dma_cycli
> > > c/
> > > device_tx_status...
> > >
> > >
> > > pm_runtime_use_autosuspend(fsl_chan->dev);
> > > pm_runtime_set_autosuspend_delay(fsl_chan->dev,
> > 2000);
> > >
> > > That could resolve this audio case since the autosuspend could suspend
> > > runtime after
> > > 2 seconds if there is no further dma transfer but only channel
> > request(device_alloc_chan_resources).
> > > But unfortunately, it cause another issue. As you know, on our
> > > i.mx8qm/qxp, power domain done by scfw (drivers/firmware/imx/scu-pd.c)
> > over mailbox:
> > > imx_sc_pd_power()->imx_scu_call_rpc()->
> > > imx_scu_ipc_write()->mbox_send_message()
> > > which means have to 'waits for completion', meanwhile, some driver
> > > like tty will call dmaengine interfaces in non-atomic case as below,
> > >
> > > static int uart_write(struct tty_struct *tty, const unsigned char
> > > *buf, int count) {
> > > .......
> > > port = uart_port_lock(state, flags);
> > > ......
> > > __uart_start(tty); //call start_tx()->dmaengine_prep_slave_sg...
> > > uart_port_unlock(port, flags);
> > > return ret;
> > > }
> > >
> > > Thus dma runtime resume may happen in that timing window and cause
> > kernel alarm.
> > > I'm not sure whether there are similar limitations on other driver
> > > subsystem. But for me, It looks like the only way to resolve the
> > > contradiction between tty and scu-pd (hardware limitation on
> > > i.mx8qm/qxp) is to give up autosuspend and keep pm_runtime_get_sync
> > only in device_alloc_chan_resources because request channel is a safe
> > non-atomic phase.
> > > Do you have any idea? Thanks in advance.
> >
> > If you look closely at the driver you used as an example (hidma.c) it looks like
> > there is already something in there, which looks very much like what you need
> > here:
> >
> > In hidma_issue_pending() the driver tries to get the device to runtime resume.
> > If this doesn't work, maybe due to the power domain code not being able to
> > be called in atomic context, the actual work of waking up the dma hardware
> > and issuing the descriptor is shunted to a tasklet.
> >
> > If I'm reading this right, this is exactly what you need here to be able to call the
> > dmaengine code from atomic context: try the rpm get and issue immediately
> > when possible, otherwise shunt the work to a non- atomic context where you
> > can deal with the requirements of scu-pd.
> Yes, I can schedule_work to worker to runtime resume edma channel by calling scu-pd.
> But that means all dmaengine interfaces should be taken care, not only issue_pending()
> but also dmaengine_terminate_all()/dmaengine_pause()/dmaengine_resume()/
> dmaengine_tx_status(). Not sure why hidma only take care issue_pending. Maybe
> their user case is just for memcpy/memset so that no further complicate case as ALSA
> or TTY.
> Besides, for autosuspend in cyclic, we have to add pm_runtime_get_sync into interrupt
> handler as qcom/bam_dma.c. but how could resolve the scu-pd's non-atmoic limitation
> in interrupt handler?
Sure, this all needs some careful analysis on how those functions are
called and what to do about atomic callers, but it should be doable. I
don't see any fundamental issues here.
I don't see why you would ever need to wake the hardware in an
interrupt handler. Surely the hardware is already awake, as it wouldn't
signal an interrupt otherwise. And for the issue with scu-pd you only
care about the state transition of suspended->running. If the hardware
is already running/awake, the runtime pm state handling is nothing more
than bumping a refcount, which is atomic safe. Putting the HW in
suspend is already handled asynchronously in a worker, so this is also
atomic safe.
Regards,
Lucas
^ permalink raw reply
* Re: [PATCH] powerpc/pseries/mce: Fix a typo in error type assignment
From: Ganesh @ 2021-04-19 9:29 UTC (permalink / raw)
To: Michael Ellerman, linuxppc-dev; +Cc: mahesh, npiggin
In-Reply-To: <87fszpdr5m.fsf@mpe.ellerman.id.au>
On 4/17/21 6:06 PM, Michael Ellerman wrote:
> Ganesh Goudar <ganeshgr@linux.ibm.com> writes:
>> The error type is ICACHE and DCACHE, for case MCE_ERROR_TYPE_ICACHE.
> Do you mean "is ICACHE not DCACHE" ?
Right :), Should I send v2 ?
>
> cheers
>
>> Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com>
>> ---
>> arch/powerpc/platforms/pseries/ras.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
>> index f8b390a9d9fb..9d4ef65da7f3 100644
>> --- a/arch/powerpc/platforms/pseries/ras.c
>> +++ b/arch/powerpc/platforms/pseries/ras.c
>> @@ -699,7 +699,7 @@ static int mce_handle_err_virtmode(struct pt_regs *regs,
>> mce_err.error_type = MCE_ERROR_TYPE_DCACHE;
>> break;
>> case MC_ERROR_TYPE_I_CACHE:
>> - mce_err.error_type = MCE_ERROR_TYPE_DCACHE;
>> + mce_err.error_type = MCE_ERROR_TYPE_ICACHE;
>> break;
>> case MC_ERROR_TYPE_UNKNOWN:
>> default:
>> --
>> 2.26.2
^ permalink raw reply
* linux-next: build failure after merge of the powerpc tree
From: Stephen Rothwell @ 2021-04-19 9:14 UTC (permalink / raw)
To: Michael Ellerman, PowerPC
Cc: Xiongwei Song, Linux Next Mailing List, Linux Kernel Mailing List
[-- Attachment #1: Type: text/plain, Size: 1421 bytes --]
Hi all,
After merging the powerpc tree, today's linux-next build (powerpc
allyesconfig) failed like this:
arch/powerpc/kernel/fadump.c: In function 'crash_fadump':
arch/powerpc/kernel/fadump.c:731:28: error: 'INTERRUPT_SYSTEM_RESET' undeclared (first use in this function)
731 | if (TRAP(&(fdh->regs)) == INTERRUPT_SYSTEM_RESET) {
| ^~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/kernel/fadump.c:731:28: note: each undeclared identifier is reported only once for each function it appears in
Caused by commit
7153d4bf0b37 ("powerpc/traps: Enhance readability for trap types")
I have applied the following patch for today.
From: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Mon, 19 Apr 2021 19:05:05 +1000
Subject: [PATCH] fix up for "powerpc/traps: Enhance readability for trap types"
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/powerpc/kernel/fadump.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c
index b55b4c23f3b6..000e3b7f3fca 100644
--- a/arch/powerpc/kernel/fadump.c
+++ b/arch/powerpc/kernel/fadump.c
@@ -31,6 +31,7 @@
#include <asm/fadump.h>
#include <asm/fadump-internal.h>
#include <asm/setup.h>
+#include <asm/interrupt.h>
/*
* The CPU who acquired the lock to trigger the fadump crash should
--
2.30.2
--
Cheers,
Stephen Rothwell
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* Re: [RFC v1 PATCH 3/3] driver: update all the code that use soc_device_match
From: Geert Uytterhoeven @ 2021-04-19 9:03 UTC (permalink / raw)
To: Dominique MARTINET
Cc: ulf.hansson, aymen.sghaier, geert+renesas, rafael, airlied,
mturquette, dri-devel, linux-kernel, a.hajda, netdev, linux-phy,
peter.ujfalusi, linux-clk, linux-renesas-soc, wim, herbert,
horia.geanta, khilman, joro, narmstrong, linux-staging, iommu,
kishon, tony, linux-omap, stern, kuba, linus.walleij, linux,
linux-media, linux-watchdog, will, linux-pm, linuxppc-dev,
edubezval, linux-gpio, linux-mediatek, ssantosh, matthias.bgg,
linux-amlogic, mchehab, linux-arm-kernel, Alice Guo (OSS), balbi,
tomba, sboyd, gregkh, linux-usb, linux-mmc, adrian.hunter,
robert.foss, leoyang.li, linux, vkoul, Arnd Bergmann,
linux-crypto, daniel, j-keerthy, dmaengine, Roy.Pledge,
jyri.sarha, davem
In-Reply-To: <YH0O907dfGY9jQRZ@atmark-techno.com>
Hi Dominique,
CC Arnd (soc_device_match() author)
On Mon, Apr 19, 2021 at 7:03 AM Dominique MARTINET
<dominique.martinet@atmark-techno.com> wrote:
> Alice Guo (OSS) wrote on Mon, Apr 19, 2021 at 12:27:22PM +0800:
> > From: Alice Guo <alice.guo@nxp.com>
> > Update all the code that use soc_device_match
>
> A single patch might be difficult to accept for all components, a each
> maintainer will probably want to have a say on their subsystem?
>
> I would suggest to split these for a non-RFC version; a this will really
> need to be case-by-case handling.
>
> > because add support for soc_device_match returning -EPROBE_DEFER.
>
> (English does not parse here for me)
>
> I've only commented a couple of places in the code itself, but this
> doesn't seem to add much support for errors, just sweep the problem
> under the rug.
>
> > Signed-off-by: Alice Guo <alice.guo@nxp.com>
> > ---
> >
> > diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
> > index 5fae60f8c135..00c59aa217c1 100644
> > --- a/drivers/bus/ti-sysc.c
> > +++ b/drivers/bus/ti-sysc.c
> > @@ -2909,7 +2909,7 @@ static int sysc_init_soc(struct sysc *ddata)
> > }
> >
> > match = soc_device_match(sysc_soc_feat_match);
> > - if (!match)
> > + if (!match || IS_ERR(match))
> > return 0;
>
> This function handles errors, I would recommend returning the error as
> is if soc_device_match returned one so the probe can be retried later.
Depends...
> > --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> > @@ -439,6 +439,7 @@ static const unsigned int r8a7795es2_mod_nullify[] __initconst = {
> >
> > static int __init r8a7795_cpg_mssr_init(struct device *dev)
> > {
> > + const struct soc_device_attribute *match;
> > const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
> > u32 cpg_mode;
> > int error;
> > @@ -453,7 +454,8 @@ static int __init r8a7795_cpg_mssr_init(struct device *dev)
> > return -EINVAL;
> > }
> >
> > - if (soc_device_match(r8a7795es1)) {
> > + match = soc_device_match(r8a7795es1);
> > + if (!IS_ERR(match) && match) {
>
> Same, return the error.
> Assuming an error means no match will just lead to hard to debug
> problems because the driver potentially assumed the wrong device when
> it's just not ready yet.
When running on R-Car H3, there will always be a match device, as
the SoC device is registered early.
>
> > cpg_core_nullify_range(r8a7795_core_clks,
> > ARRAY_SIZE(r8a7795_core_clks),
> > R8A7795_CLK_S0D2, R8A7795_CLK_S0D12);
> > [...]
> > diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
> > index eaaec0a55cc6..13a06b613379 100644
> > --- a/drivers/iommu/ipmmu-vmsa.c
> > +++ b/drivers/iommu/ipmmu-vmsa.c
> > @@ -757,17 +757,20 @@ static const char * const devices_allowlist[] = {
> >
> > static bool ipmmu_device_is_allowed(struct device *dev)
> > {
> > + const struct soc_device_attribute *match1, *match2;
> > unsigned int i;
> >
> > /*
> > * R-Car Gen3 and RZ/G2 use the allow list to opt-in devices.
> > * For Other SoCs, this returns true anyway.
> > */
> > - if (!soc_device_match(soc_needs_opt_in))
> > + match1 = soc_device_match(soc_needs_opt_in);
> > + if (!IS_ERR(match1) && !match1)
>
> I'm not sure what you intended to do, but !match1 already means there is
> no error so the original code is identical.
>
> In this case ipmmu_device_is_allowed does not allow errors so this is
> one of the "difficult" drivers that require slightly more thinking.
> It is only called in ipmmu_of_xlate which does return errors properly,
> so in this case the most straightforward approach would be to make
> ipmmu_device_is_allowed return an int and forward errors as well.
>
> ...
> This is going to need quite some more work to be acceptable, in my
> opinion, but I think it should be possible.
In general, this is very hard to do, IMHO. Some drivers may be used on
multiple platforms, some of them registering an SoC device, some of
them not registering an SoC device. So there is no way to know the
difference between "SoC device not registered, intentionally", and
"SoC device not yet registered".
soc_device_match() should only be used as a last resort, to identify
systems that cannot be identified otherwise. Typically this is used for
quirks, which should only be enabled on a very specific subset of
systems. IMHO such systems should make sure soc_device_match()
is available early, by registering their SoC device early.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [RFC v1 PATCH 1/3] drivers: soc: add support for soc_device_match returning -EPROBE_DEFER
From: Geert Uytterhoeven @ 2021-04-19 8:20 UTC (permalink / raw)
To: Alice Guo (OSS)
Cc: ulf.hansson, aymen.sghaier, geert+renesas, rafael, airlied,
mturquette, dri-devel, linux-kernel, a.hajda, netdev, linux-phy,
will, linux-clk, linux-renesas-soc, wim, herbert, horia.geanta,
khilman, joro, narmstrong, linux-staging, iommu, peter.ujfalusi,
kishon, tony, linux-omap, stern, kuba, linus.walleij, linux,
linux-media, linux-watchdog, Roy.Pledge, linux-pm, linuxppc-dev,
edubezval, linux-gpio, linux-mediatek, ssantosh, matthias.bgg,
linux-amlogic, mchehab, linux-arm-kernel, balbi, tomba, sboyd,
gregkh, linux-usb, linux-mmc, adrian.hunter, robert.foss,
leoyang.li, linux, vkoul, Arnd Bergmann, linux-crypto, daniel,
j-keerthy, dmaengine, jyri.sarha, davem
In-Reply-To: <20210419042722.27554-2-alice.guo@oss.nxp.com>
Hi Alice,
CC Arnd (soc_device_match() author)
On Mon, Apr 19, 2021 at 6:28 AM Alice Guo (OSS) <alice.guo@oss.nxp.com> wrote:
> From: Alice Guo <alice.guo@nxp.com>
>
> In i.MX8M boards, the registration of SoC device is later than caam
> driver which needs it. Caam driver needs soc_device_match to provide
> -EPROBE_DEFER when no SoC device is registered and no
> early_soc_dev_attr.
I'm wondering if this is really a good idea: soc_device_match() is a
last-resort low-level check, and IMHO should be made available early on,
so there is no need for -EPROBE_DEFER.
>
> Signed-off-by: Alice Guo <alice.guo@nxp.com>
Thanks for your patch!
> --- a/drivers/base/soc.c
> +++ b/drivers/base/soc.c
> @@ -110,6 +110,7 @@ static void soc_release(struct device *dev)
> }
>
> static struct soc_device_attribute *early_soc_dev_attr;
> +static bool soc_dev_attr_init_done = false;
Do you need this variable?
>
> struct soc_device *soc_device_register(struct soc_device_attribute *soc_dev_attr)
> {
> @@ -157,6 +158,7 @@ struct soc_device *soc_device_register(struct soc_device_attribute *soc_dev_attr
> return ERR_PTR(ret);
> }
>
> + soc_dev_attr_init_done = true;
> return soc_dev;
>
> out3:
> @@ -246,6 +248,9 @@ const struct soc_device_attribute *soc_device_match(
> if (!matches)
> return NULL;
>
> + if (!soc_dev_attr_init_done && !early_soc_dev_attr)
if (!soc_bus_type.p && !early_soc_dev_attr)
> + return ERR_PTR(-EPROBE_DEFER);
> +
> while (!ret) {
> if (!(matches->machine || matches->family ||
> matches->revision || matches->soc_id))
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* RE: [RFC v1 PATCH 3/3] driver: update all the code that use soc_device_match
From: Alice Guo (OSS) @ 2021-04-19 7:09 UTC (permalink / raw)
To: Dominique MARTINET, Alice Guo (OSS)
Cc: ulf.hansson@linaro.org, Aymen Sghaier, geert+renesas@glider.be,
rafael@kernel.org, airlied@linux.ie, mturquette@baylibre.com,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
a.hajda@samsung.com, netdev@vger.kernel.org,
linux-phy@lists.infradead.org, will@kernel.org,
linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
wim@linux-watchdog.org, herbert@gondor.apana.org.au, Horia Geanta,
khilman@baylibre.com, joro@8bytes.org, narmstrong@baylibre.com,
linux-staging@lists.linux.dev, iommu@lists.linux-foundation.org,
peter.ujfalusi@gmail.com, kishon@ti.com, tony@atomide.com,
linux-omap@vger.kernel.org, stern@rowland.harvard.edu,
dl-linux-imx, kuba@kernel.org, linus.walleij@linaro.org,
linux@roeck-us.net, linux-media@vger.kernel.org,
linux-watchdog@vger.kernel.org, Roy Pledge,
linux-pm@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
edubezval@gmail.com, linux-gpio@vger.kernel.org,
linux-mediatek@lists.infradead.org, ssantosh@kernel.org,
matthias.bgg@gmail.com, linux-amlogic@lists.infradead.org,
mchehab@kernel.org, linux-arm-kernel@lists.infradead.org,
balbi@kernel.org, tomba@kernel.org, sboyd@kernel.org,
gregkh@linuxfoundation.org, linux-usb@vger.kernel.org,
linux-mmc@vger.kernel.org, adrian.hunter@intel.com,
robert.foss@linaro.org, Leo Li, linux@prisktech.co.nz,
vkoul@kernel.org, linux-crypto@vger.kernel.org, daniel@ffwll.ch,
j-keerthy@ti.com, dmaengine@vger.kernel.org, jyri.sarha@iki.fi,
davem@davemloft.net
In-Reply-To: <YH0O907dfGY9jQRZ@atmark-techno.com>
> -----Original Message-----
> From: Dominique MARTINET <dominique.martinet@atmark-techno.com>
> Sent: 2021年4月19日 13:03
> To: Alice Guo (OSS) <alice.guo@oss.nxp.com>
> Subject: Re: [RFC v1 PATCH 3/3] driver: update all the code that use
> soc_device_match
>
> Alice Guo (OSS) wrote on Mon, Apr 19, 2021 at 12:27:22PM +0800:
> > From: Alice Guo <alice.guo@nxp.com>
> >
> > Update all the code that use soc_device_match
>
> A single patch might be difficult to accept for all components, a each maintainer
> will probably want to have a say on their subsystem?
>
> I would suggest to split these for a non-RFC version; a this will really need to be
> case-by-case handling.
>
> > because add support for soc_device_match returning -EPROBE_DEFER.
>
> (English does not parse here for me)
>
> I've only commented a couple of places in the code itself, but this doesn't seem
> to add much support for errors, just sweep the problem under the rug.
>
> > Signed-off-by: Alice Guo <alice.guo@nxp.com>
> > ---
> >
> > diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index
> > 5fae60f8c135..00c59aa217c1 100644
> > --- a/drivers/bus/ti-sysc.c
> > +++ b/drivers/bus/ti-sysc.c
> > @@ -2909,7 +2909,7 @@ static int sysc_init_soc(struct sysc *ddata)
> > }
> >
> > match = soc_device_match(sysc_soc_feat_match);
> > - if (!match)
> > + if (!match || IS_ERR(match))
> > return 0;
>
> This function handles errors, I would recommend returning the error as is if
> soc_device_match returned one so the probe can be retried later.
>
> >
> > if (match->data)
> > diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> > b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> > index c32d2c678046..90a18336a4c3 100644
> > --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> > @@ -439,6 +439,7 @@ static const unsigned int r8a7795es2_mod_nullify[]
> > __initconst = {
> >
> > static int __init r8a7795_cpg_mssr_init(struct device *dev) {
> > + const struct soc_device_attribute *match;
> > const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
> > u32 cpg_mode;
> > int error;
> > @@ -453,7 +454,8 @@ static int __init r8a7795_cpg_mssr_init(struct device
> *dev)
> > return -EINVAL;
> > }
> >
> > - if (soc_device_match(r8a7795es1)) {
> > + match = soc_device_match(r8a7795es1);
> > + if (!IS_ERR(match) && match) {
>
> Same, return the error.
> Assuming an error means no match will just lead to hard to debug problems
> because the driver potentially assumed the wrong device when it's just not
> ready yet.
>
> > cpg_core_nullify_range(r8a7795_core_clks,
> > ARRAY_SIZE(r8a7795_core_clks),
> > R8A7795_CLK_S0D2, R8A7795_CLK_S0D12); [...]
> diff --git
> > a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index
> > eaaec0a55cc6..13a06b613379 100644
> > --- a/drivers/iommu/ipmmu-vmsa.c
> > +++ b/drivers/iommu/ipmmu-vmsa.c
> > @@ -757,17 +757,20 @@ static const char * const devices_allowlist[] =
> > {
> >
> > static bool ipmmu_device_is_allowed(struct device *dev) {
> > + const struct soc_device_attribute *match1, *match2;
> > unsigned int i;
> >
> > /*
> > * R-Car Gen3 and RZ/G2 use the allow list to opt-in devices.
> > * For Other SoCs, this returns true anyway.
> > */
> > - if (!soc_device_match(soc_needs_opt_in))
> > + match1 = soc_device_match(soc_needs_opt_in);
> > + if (!IS_ERR(match1) && !match1)
>
> I'm not sure what you intended to do, but !match1 already means there is no
> error so the original code is identical.
>
> In this case ipmmu_device_is_allowed does not allow errors so this is one of the
> "difficult" drivers that require slightly more thinking.
> It is only called in ipmmu_of_xlate which does return errors properly, so in this
> case the most straightforward approach would be to make
> ipmmu_device_is_allowed return an int and forward errors as well.
>
I will reconsider the existing problems. Thank you for your advice
>
> ...
> This is going to need quite some more work to be acceptable, in my opinion, but
> I think it should be possible.
>
> Thanks,
> --
> Dominique
^ permalink raw reply
* RE: [RFC v1 PATCH 3/3] driver: update all the code that use soc_device_match
From: Alice Guo (OSS) @ 2021-04-19 6:46 UTC (permalink / raw)
To: Leon Romanovsky, Alice Guo (OSS)
Cc: ulf.hansson@linaro.org, Aymen Sghaier, geert+renesas@glider.be,
rafael@kernel.org, airlied@linux.ie, mturquette@baylibre.com,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
a.hajda@samsung.com, netdev@vger.kernel.org,
linux-phy@lists.infradead.org, will@kernel.org,
linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
wim@linux-watchdog.org, herbert@gondor.apana.org.au, Horia Geanta,
khilman@baylibre.com, joro@8bytes.org, narmstrong@baylibre.com,
linux-staging@lists.linux.dev, iommu@lists.linux-foundation.org,
peter.ujfalusi@gmail.com, kishon@ti.com, tony@atomide.com,
linux-omap@vger.kernel.org, stern@rowland.harvard.edu,
dl-linux-imx, kuba@kernel.org, linus.walleij@linaro.org,
linux@roeck-us.net, linux-media@vger.kernel.org,
Dominique MARTINET, linux-watchdog@vger.kernel.org,
linux-pm@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
edubezval@gmail.com, linux-gpio@vger.kernel.org,
linux-mediatek@lists.infradead.org, ssantosh@kernel.org,
matthias.bgg@gmail.com, linux-amlogic@lists.infradead.org,
mchehab@kernel.org, linux-arm-kernel@lists.infradead.org,
balbi@kernel.org, tomba@kernel.org, sboyd@kernel.org,
gregkh@linuxfoundation.org, linux-usb@vger.kernel.org,
linux-mmc@vger.kernel.org, adrian.hunter@intel.com,
robert.foss@linaro.org, Leo Li, linux@prisktech.co.nz,
vkoul@kernel.org, linux-crypto@vger.kernel.org, daniel@ffwll.ch,
j-keerthy@ti.com, dmaengine@vger.kernel.org, jyri.sarha@iki.fi,
davem@davemloft.net
In-Reply-To: <YH0O1104YEdjY9mb@unreal>
> -----Original Message-----
> From: Leon Romanovsky <leon@kernel.org>
> Sent: 2021年4月19日 13:02
> To: Alice Guo (OSS) <alice.guo@oss.nxp.com>
> Cc: gregkh@linuxfoundation.org; rafael@kernel.org; Horia Geanta
> <horia.geanta@nxp.com>; Aymen Sghaier <aymen.sghaier@nxp.com>;
> herbert@gondor.apana.org.au; davem@davemloft.net; tony@atomide.com;
> geert+renesas@glider.be; mturquette@baylibre.com; sboyd@kernel.org;
> vkoul@kernel.org; peter.ujfalusi@gmail.com; a.hajda@samsung.com;
> narmstrong@baylibre.com; robert.foss@linaro.org; airlied@linux.ie;
> daniel@ffwll.ch; khilman@baylibre.com; tomba@kernel.org; jyri.sarha@iki.fi;
> joro@8bytes.org; will@kernel.org; mchehab@kernel.org;
> ulf.hansson@linaro.org; adrian.hunter@intel.com; kishon@ti.com;
> kuba@kernel.org; linus.walleij@linaro.org; Roy Pledge <roy.pledge@nxp.com>;
> Leo Li <leoyang.li@nxp.com>; ssantosh@kernel.org; matthias.bgg@gmail.com;
> edubezval@gmail.com; j-keerthy@ti.com; balbi@kernel.org;
> linux@prisktech.co.nz; stern@rowland.harvard.edu; wim@linux-watchdog.org;
> linux@roeck-us.net; linux-kernel@vger.kernel.org; linux-crypto@vger.kernel.org;
> linux-omap@vger.kernel.org; linux-renesas-soc@vger.kernel.org;
> linux-clk@vger.kernel.org; dmaengine@vger.kernel.org;
> dri-devel@lists.freedesktop.org; linux-amlogic@lists.infradead.org;
> linux-arm-kernel@lists.infradead.org; iommu@lists.linux-foundation.org;
> linux-media@vger.kernel.org; linux-mmc@vger.kernel.org;
> netdev@vger.kernel.org; linux-phy@lists.infradead.org;
> linux-gpio@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> linux-staging@lists.linux.dev; linux-mediatek@lists.infradead.org;
> linux-pm@vger.kernel.org; linux-usb@vger.kernel.org;
> linux-watchdog@vger.kernel.org
> Subject: Re: [RFC v1 PATCH 3/3] driver: update all the code that use
> soc_device_match
>
> On Mon, Apr 19, 2021 at 12:27:22PM +0800, Alice Guo (OSS) wrote:
> > From: Alice Guo <alice.guo@nxp.com>
> >
> > Update all the code that use soc_device_match because add support for
> > soc_device_match returning -EPROBE_DEFER.
> >
> > Signed-off-by: Alice Guo <alice.guo@nxp.com>
> > ---
> > drivers/bus/ti-sysc.c | 2 +-
> > drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 +++-
> > drivers/clk/renesas/rcar-gen2-cpg.c | 2 +-
> > drivers/clk/renesas/rcar-gen3-cpg.c | 2 +-
> > drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 7 ++++++-
> > drivers/dma/ti/k3-psil.c | 3 +++
> > drivers/dma/ti/k3-udma.c | 2 +-
> > drivers/gpu/drm/bridge/nwl-dsi.c | 2 +-
> > drivers/gpu/drm/meson/meson_drv.c | 4 +++-
> > drivers/gpu/drm/omapdrm/dss/dispc.c | 2 +-
> > drivers/gpu/drm/omapdrm/dss/dpi.c | 4 +++-
> > drivers/gpu/drm/omapdrm/dss/dsi.c | 3 +++
> > drivers/gpu/drm/omapdrm/dss/dss.c | 3 +++
> > drivers/gpu/drm/omapdrm/dss/hdmi4_core.c | 3 +++
> > drivers/gpu/drm/omapdrm/dss/venc.c | 4 +++-
> > drivers/gpu/drm/omapdrm/omap_drv.c | 3 +++
> > drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 4 +++-
> > drivers/gpu/drm/rcar-du/rcar_lvds.c | 2 +-
> > drivers/gpu/drm/tidss/tidss_dispc.c | 4 +++-
> > drivers/iommu/ipmmu-vmsa.c | 7 +++++--
> > drivers/media/platform/rcar-vin/rcar-core.c | 2 +-
> > drivers/media/platform/rcar-vin/rcar-csi2.c | 2 +-
> > drivers/media/platform/vsp1/vsp1_uif.c | 4 +++-
> > drivers/mmc/host/renesas_sdhi_core.c | 2 +-
> > drivers/mmc/host/renesas_sdhi_internal_dmac.c | 2 +-
> > drivers/mmc/host/sdhci-of-esdhc.c | 21
> ++++++++++++++-----
> > drivers/mmc/host/sdhci-omap.c | 2 +-
> > drivers/mmc/host/sdhci_am654.c | 2 +-
> > drivers/net/ethernet/renesas/ravb_main.c | 4 +++-
> > drivers/net/ethernet/ti/am65-cpsw-nuss.c | 2 +-
> > drivers/net/ethernet/ti/cpsw.c | 2 +-
> > drivers/net/ethernet/ti/cpsw_new.c | 2 +-
> > drivers/phy/ti/phy-omap-usb2.c | 4 +++-
> > drivers/pinctrl/renesas/core.c | 2 +-
> > drivers/pinctrl/renesas/pfc-r8a7790.c | 5 ++++-
> > drivers/pinctrl/renesas/pfc-r8a7794.c | 5 ++++-
> > drivers/soc/fsl/dpio/dpio-driver.c | 13 ++++++++----
> > drivers/soc/renesas/r8a774c0-sysc.c | 5 ++++-
> > drivers/soc/renesas/r8a7795-sysc.c | 2 +-
> > drivers/soc/renesas/r8a77990-sysc.c | 5 ++++-
> > drivers/soc/ti/k3-ringacc.c | 2 +-
> > drivers/staging/mt7621-pci/pci-mt7621.c | 2 +-
> > drivers/thermal/rcar_gen3_thermal.c | 4 +++-
> > drivers/thermal/ti-soc-thermal/ti-bandgap.c | 10 +++++++--
> > drivers/usb/gadget/udc/renesas_usb3.c | 2 +-
> > drivers/usb/host/ehci-platform.c | 4 +++-
> > drivers/usb/host/xhci-rcar.c | 2 +-
> > drivers/watchdog/renesas_wdt.c | 2 +-
> > 48 files changed, 131 insertions(+), 52 deletions(-)
> >
> > diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index
> > 5fae60f8c135..00c59aa217c1 100644
> > --- a/drivers/bus/ti-sysc.c
> > +++ b/drivers/bus/ti-sysc.c
> > @@ -2909,7 +2909,7 @@ static int sysc_init_soc(struct sysc *ddata)
> > }
> >
> > match = soc_device_match(sysc_soc_feat_match);
> > - if (!match)
> > + if (!match || IS_ERR(match))
> > return 0;
> >
> > if (match->data)
> > diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> > b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> > index c32d2c678046..90a18336a4c3 100644
> > --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> > @@ -439,6 +439,7 @@ static const unsigned int r8a7795es2_mod_nullify[]
> > __initconst = {
> >
> > static int __init r8a7795_cpg_mssr_init(struct device *dev) {
> > + const struct soc_device_attribute *match;
> > const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
> > u32 cpg_mode;
> > int error;
> > @@ -453,7 +454,8 @@ static int __init r8a7795_cpg_mssr_init(struct device
> *dev)
> > return -EINVAL;
> > }
> >
> > - if (soc_device_match(r8a7795es1)) {
> > + match = soc_device_match(r8a7795es1);
> > + if (!IS_ERR(match) && match) {
>
> "if (!IS_ERR_OR_NULL(match))" in all places.
Thank you for your suggestion. I will modify them.
Best Regards,
Alice Guo
> Thanks
^ permalink raw reply
* RE: [RFC v1 PATCH 1/3] drivers: soc: add support for soc_device_match returning -EPROBE_DEFER
From: Alice Guo (OSS) @ 2021-04-19 6:40 UTC (permalink / raw)
To: Dominique MARTINET, Alice Guo (OSS)
Cc: ulf.hansson@linaro.org, Aymen Sghaier, geert+renesas@glider.be,
rafael@kernel.org, airlied@linux.ie, mturquette@baylibre.com,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
a.hajda@samsung.com, netdev@vger.kernel.org,
linux-phy@lists.infradead.org, will@kernel.org,
linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
wim@linux-watchdog.org, herbert@gondor.apana.org.au, Horia Geanta,
khilman@baylibre.com, joro@8bytes.org, narmstrong@baylibre.com,
linux-staging@lists.linux.dev, iommu@lists.linux-foundation.org,
peter.ujfalusi@gmail.com, kishon@ti.com, tony@atomide.com,
linux-omap@vger.kernel.org, stern@rowland.harvard.edu,
dl-linux-imx, kuba@kernel.org, linus.walleij@linaro.org,
linux@roeck-us.net, linux-media@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-pm@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, edubezval@gmail.com,
linux-gpio@vger.kernel.org, linux-mediatek@lists.infradead.org,
ssantosh@kernel.org, matthias.bgg@gmail.com,
linux-amlogic@lists.infradead.org, mchehab@kernel.org,
linux-arm-kernel@lists.infradead.org, balbi@kernel.org,
tomba@kernel.org, sboyd@kernel.org, gregkh@linuxfoundation.org,
linux-usb@vger.kernel.org, linux-mmc@vger.kernel.org,
adrian.hunter@intel.com, robert.foss@linaro.org, Leo Li,
linux@prisktech.co.nz, vkoul@kernel.org,
linux-crypto@vger.kernel.org, daniel@ffwll.ch, j-keerthy@ti.com,
dmaengine@vger.kernel.org, jyri.sarha@iki.fi, davem@davemloft.net
In-Reply-To: <YH0Lwy2AYpXaJIex@atmark-techno.com>
> -----Original Message-----
> From: Dominique MARTINET <dominique.martinet@atmark-techno.com>
> Sent: 2021年4月19日 12:49
> To: Alice Guo (OSS) <alice.guo@oss.nxp.com>
> Cc: gregkh@linuxfoundation.org; rafael@kernel.org; Horia Geanta
> <horia.geanta@nxp.com>; Aymen Sghaier <aymen.sghaier@nxp.com>;
> herbert@gondor.apana.org.au; davem@davemloft.net; tony@atomide.com;
> geert+renesas@glider.be; mturquette@baylibre.com; sboyd@kernel.org;
> vkoul@kernel.org; peter.ujfalusi@gmail.com; a.hajda@samsung.com;
> narmstrong@baylibre.com; robert.foss@linaro.org; airlied@linux.ie;
> daniel@ffwll.ch; khilman@baylibre.com; tomba@kernel.org; jyri.sarha@iki.fi;
> joro@8bytes.org; will@kernel.org; mchehab@kernel.org;
> ulf.hansson@linaro.org; adrian.hunter@intel.com; kishon@ti.com;
> kuba@kernel.org; linus.walleij@linaro.org; Roy Pledge <roy.pledge@nxp.com>;
> Leo Li <leoyang.li@nxp.com>; ssantosh@kernel.org; matthias.bgg@gmail.com;
> edubezval@gmail.com; j-keerthy@ti.com; balbi@kernel.org;
> linux@prisktech.co.nz; stern@rowland.harvard.edu; wim@linux-watchdog.org;
> linux@roeck-us.net; linux-kernel@vger.kernel.org; linux-crypto@vger.kernel.org;
> linux-omap@vger.kernel.org; linux-renesas-soc@vger.kernel.org;
> linux-clk@vger.kernel.org; dmaengine@vger.kernel.org;
> dri-devel@lists.freedesktop.org; linux-amlogic@lists.infradead.org;
> linux-arm-kernel@lists.infradead.org; iommu@lists.linux-foundation.org;
> linux-media@vger.kernel.org; linux-mmc@vger.kernel.org;
> netdev@vger.kernel.org; linux-phy@lists.infradead.org;
> linux-gpio@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> linux-staging@lists.linux.dev; linux-mediatek@lists.infradead.org;
> linux-pm@vger.kernel.org; linux-usb@vger.kernel.org;
> linux-watchdog@vger.kernel.org
> Subject: Re: [RFC v1 PATCH 1/3] drivers: soc: add support for soc_device_match
> returning -EPROBE_DEFER
>
> First comment overall for the whole serie:
> Since it is the solution I had suggested when I reported the problem[1] I have no
> qualm on the approach, comments for individual patches follow.
>
> [1] http://lore.kernel.org/r/YGGZJjAxA1IO+/VU@atmark-techno.com
>
>
> Alice Guo (OSS) wrote on Mon, Apr 19, 2021 at 12:27:20PM +0800:
> > From: Alice Guo <alice.guo@nxp.com>
> >
> > In i.MX8M boards, the registration of SoC device is later than caam
> > driver which needs it. Caam driver needs soc_device_match to provide
> > -EPROBE_DEFER when no SoC device is registered and no
> > early_soc_dev_attr.
>
> This patch should be last in the set: you can't have soc_device_match return an
> error before its callers handle it.
>
> > Signed-off-by: Alice Guo <alice.guo@nxp.com>
>
> As the one who reported the problem I would have been appreciated being at
> least added to Ccs... I only happened to notice you posted this by chance.
Sorry. I will Cc you next time.
> There is also not a single Fixes tag -- I believe this commit should have Fixes:
> 7d981405d0fd ("soc: imx8m: change to use platform driver") but I'm not sure
> how such tags should be handled in case of multiple patches fixing something.
I only mentioned "soc: imx8m: change to use platform driver" in cover letter.
If it is acceptable to make such a modification, I will send non-RFC and add Fixes tag.
Best Regards,
Alice
> --
> Dominique
^ permalink raw reply
* [PATCH v4] powerpc/kexec_file: use current CPU info while setting up FDT
From: Sourabh Jain @ 2021-04-19 8:36 UTC (permalink / raw)
To: mpe; +Cc: mahesh, Sourabh Jain, linuxppc-dev, stable, hbathini, bauerman
kexec_file_load uses initial_boot_params in setting up the device-tree
for the kernel to be loaded. Though initial_boot_params holds info
about CPUs at the time of boot, it doesn't account for hot added CPUs.
So, kexec'ing with kexec_file_load syscall would leave the kexec'ed
kernel with inaccurate CPU info. Also, if kdump kernel is loaded with
kexec_file_load syscall and the system crashes on a hot added CPU,
capture kernel hangs failing to identify the boot CPU.
Kernel panic - not syncing: sysrq triggered crash
CPU: 24 PID: 6065 Comm: echo Kdump: loaded Not tainted 5.12.0-rc5upstream #54
Call Trace:
[c0000000e590fac0] [c0000000007b2400] dump_stack+0xc4/0x114 (unreliable)
[c0000000e590fb00] [c000000000145290] panic+0x16c/0x41c
[c0000000e590fba0] [c0000000008892e0] sysrq_handle_crash+0x30/0x40
[c0000000e590fc00] [c000000000889cdc] __handle_sysrq+0xcc/0x1f0
[c0000000e590fca0] [c00000000088a538] write_sysrq_trigger+0xd8/0x178
[c0000000e590fce0] [c0000000005e9b7c] proc_reg_write+0x10c/0x1b0
[c0000000e590fd10] [c0000000004f26d0] vfs_write+0xf0/0x330
[c0000000e590fd60] [c0000000004f2aec] ksys_write+0x7c/0x140
[c0000000e590fdb0] [c000000000031ee0] system_call_exception+0x150/0x290
[c0000000e590fe10] [c00000000000ca5c] system_call_common+0xec/0x278
--- interrupt: c00 at 0x7fff905b9664
NIP: 00007fff905b9664 LR: 00007fff905320c4 CTR: 0000000000000000
REGS: c0000000e590fe80 TRAP: 0c00 Not tainted (5.12.0-rc5upstream)
MSR: 800000000280f033 <SF,VEC,VSX,EE,PR,FP,ME,IR,DR,RI,LE> CR: 28000242
XER: 00000000
IRQMASK: 0
GPR00: 0000000000000004 00007ffff5fedf30 00007fff906a7300 0000000000000001
GPR04: 000001002a7355b0 0000000000000002 0000000000000001 00007ffff5fef616
GPR08: 0000000000000001 0000000000000000 0000000000000000 0000000000000000
GPR12: 0000000000000000 00007fff9073a160 0000000000000000 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 00007fff906a4ee0 0000000000000002 0000000000000001
GPR24: 00007fff906a0898 0000000000000000 0000000000000002 000001002a7355b0
GPR28: 0000000000000002 00007fff906a1790 000001002a7355b0 0000000000000002
NIP [00007fff905b9664] 0x7fff905b9664
LR [00007fff905320c4] 0x7fff905320c4
--- interrupt: c00
To avoid this from happening, extract current CPU info from of_root
device node and use it for setting up the fdt in kexec_file_load case.
Fixes: 6ecd0163d360 ("powerpc/kexec_file: Add appropriate regions for memory reserve map")
Signed-off-by: Sourabh Jain <sourabhjain@linux.ibm.com>
Reviewed-by: Hari Bathini <hbathini@linux.ibm.com>
Cc: <stable@vger.kernel.org>
---
arch/powerpc/kexec/file_load_64.c | 98 +++++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)
---
Changelog:
v1 -> v3
- https://lists.ozlabs.org/pipermail/linuxppc-dev/2021-April/227756.html
v3 -> v4
- Rearranged if-else statement in update_cpus_node function to avoid
redundant checks for positive cpus_offset.
---
diff --git a/arch/powerpc/kexec/file_load_64.c b/arch/powerpc/kexec/file_load_64.c
index 02b9e4d0dc40..195ef303d530 100644
--- a/arch/powerpc/kexec/file_load_64.c
+++ b/arch/powerpc/kexec/file_load_64.c
@@ -960,6 +960,99 @@ unsigned int kexec_fdt_totalsize_ppc64(struct kimage *image)
return fdt_size;
}
+/**
+ * add_node_prop - Read property from device node structure and add
+ * them to fdt.
+ * @fdt: Flattened device tree of the kernel
+ * @node_offset: offset of the node to add a property at
+ * np: device node pointer
+ *
+ * Returns 0 on success, negative errno on error.
+ */
+static int add_node_prop(void *fdt, int node_offset, const struct device_node *np)
+{
+ int ret = 0;
+ struct property *pp;
+ unsigned long flags;
+
+ if (!np)
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&devtree_lock, flags);
+ for (pp = np->properties; pp; pp = pp->next) {
+ ret = fdt_setprop(fdt, node_offset, pp->name,
+ pp->value, pp->length);
+ if (ret < 0) {
+ pr_err("Unable to add %s property: %s\n",
+ pp->name, fdt_strerror(ret));
+ goto out;
+ }
+ }
+out:
+ raw_spin_unlock_irqrestore(&devtree_lock, flags);
+ return ret;
+}
+
+/**
+ * update_cpus_node - Update cpus node of flattened device-tree using of_root
+ * device node.
+ * @fdt: Flattened device tree of the kernel.
+ *
+ * Returns 0 on success, negative errno on error.
+ */
+static int update_cpus_node(void *fdt)
+{
+ struct device_node *cpus_node, *dn;
+ int cpus_offset, cpus_subnode_off, ret = 0;
+
+ cpus_offset = fdt_path_offset(fdt, "/cpus");
+ if (cpus_offset < 0 && cpus_offset != -FDT_ERR_NOTFOUND) {
+ pr_err("Malformed device tree: error reading /cpus node: %s\n",
+ fdt_strerror(cpus_offset));
+ return cpus_offset;
+ } else {
+ if (cpus_offset > 0) {
+ ret = fdt_del_node(fdt, cpus_offset);
+ if (ret < 0) {
+ pr_err("Error deleting /cpus node: %s\n",
+ fdt_strerror(ret));
+ return -EINVAL;
+ }
+ }
+
+ /* Add cpus node to fdt */
+ cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
+ "cpus");
+ if (cpus_offset < 0) {
+ pr_err("Error creating /cpus node: %s\n",
+ fdt_strerror(cpus_offset));
+ return -EINVAL;
+ }
+
+ /* Add cpus node properties */
+ cpus_node = of_find_node_by_path("/cpus");
+ ret = add_node_prop(fdt, cpus_offset, cpus_node);
+ if (ret < 0)
+ return ret;
+
+ /* Loop through all subnodes of cpus and add them to fdt */
+ for_each_node_by_type(dn, "cpu") {
+ cpus_subnode_off = fdt_add_subnode(fdt,
+ cpus_offset,
+ dn->full_name);
+ if (cpus_subnode_off < 0) {
+ pr_err("Unable to add %s subnode: %s\n",
+ dn->full_name, fdt_strerror(cpus_subnode_off));
+ return cpus_subnode_off;
+ }
+ ret = add_node_prop(fdt, cpus_subnode_off, dn);
+ if (ret < 0)
+ return ret;
+ }
+ }
+ return ret;
+}
+
/**
* setup_new_fdt_ppc64 - Update the flattend device-tree of the kernel
* being loaded.
@@ -1020,6 +1113,11 @@ int setup_new_fdt_ppc64(const struct kimage *image, void *fdt,
}
}
+ /* Update cpus nodes information to account hotplug CPUs. */
+ ret = update_cpus_node(fdt);
+ if (ret < 0)
+ return ret;
+
/* Update memory reserve map */
ret = get_reserved_memory_ranges(&rmem);
if (ret)
--
2.26.3
^ permalink raw reply related
* RE: [PATCH] ASoC: fsl: imx-pcm-dma: Don't request dma channel in probe
From: Robin Gong @ 2021-04-19 7:17 UTC (permalink / raw)
To: Lucas Stach, Shengjiu Wang
Cc: Nicolin Chen, Linux-ALSA, Liam Girdwood, s.hauer@pengutronix.de,
Timur Tabi, Xiubo Li, shawnguo@kernel.org, S.j. Wang,
linux-kernel, dri-devel@lists.freedesktop.org, Takashi Iwai,
linaro-mm-sig@lists.linaro.org, Mark Brown, dl-linux-imx,
kernel@pengutronix.de, Fabio Estevam, perex@perex.cz,
linuxppc-dev@lists.ozlabs.org, sumit.semwal@linaro.org,
linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org
In-Reply-To: <50ef17a2d57b022c48bbca71fd4e074cc3ca9be5.camel@pengutronix.de>
Hi Lucas,
On 2021/04/14 Lucas Stach <l.stach@pengutronix.de> wrote:
> Hi Robin,
>
> Am Mittwoch, dem 14.04.2021 um 14:33 +0000 schrieb Robin Gong:
> > On 2020/05/20 17:43 Lucas Stach <l.stach@pengutronix.de> wrote:
> > > Am Mittwoch, den 20.05.2020, 16:20 +0800 schrieb Shengjiu Wang:
> > > > Hi
> > > >
> > > > On Tue, May 19, 2020 at 6:04 PM Lucas Stach
> > > > <l.stach@pengutronix.de>
> > > wrote:
> > > > > Am Dienstag, den 19.05.2020, 17:41 +0800 schrieb Shengjiu Wang:
> > > > > > There are two requirements that we need to move the request of
> > > > > > dma channel from probe to open.
> > > > >
> > > > > How do you handle -EPROBE_DEFER return code from the channel
> > > > > request if you don't do it in probe?
> > > >
> > > > I use the dma_request_slave_channel or dma_request_channel instead
> > > > of dmaengine_pcm_request_chan_of. so there should be not
> > > > -EPROBE_DEFER return code.
> > >
> > > This is a pretty weak argument. The dmaengine device might probe
> > > after you try to get the channel. Using a function to request the
> > > channel that doesn't allow you to handle probe deferral is IMHO a
> > > bug and should be fixed, instead of building even more assumptions on top
> of it.
> > >
> > > > > > - When dma device binds with power-domains, the power will be
> > > > > > enabled when we request dma channel. If the request of dma
> > > > > > channel happen on probe, then the power-domains will be always
> > > > > > enabled after kernel boot up, which is not good for power
> > > > > > saving, so we need to move the request of dma channel to
> > > > > > .open();
> > > > >
> > > > > This is certainly something which could be fixed in the
> > > > > dmaengine driver.
> > > >
> > > > Dma driver always call the pm_runtime_get_sync in
> > > > device_alloc_chan_resources, the device_alloc_chan_resources is
> > > > called when channel is requested. so power is enabled on channel
> request.
> > >
> > > So why can't you fix the dmaengine driver to do that RPM call at a
> > > later time when the channel is actually going to be used? This will
> > > allow further power savings with other slave devices than the audio PCM.
> > Hi Lucas,
> > Thanks for your suggestion. I have tried to implement runtime
> > autosuspend in fsl-edma driver on i.mx8qm/qxp with delay time (2 sec)
> > for this feature as below (or you can refer to
> > drivers/dma/qcom/hidma.c), and pm_runtime_get_sync/
> > pm_runtime_put_autosuspend in all dmaengine driver interface like
> > device_alloc_chan_resources/device_prep_slave_sg/device_prep_dma_cycli
> > c/
> > device_tx_status...
> >
> >
> > pm_runtime_use_autosuspend(fsl_chan->dev);
> > pm_runtime_set_autosuspend_delay(fsl_chan->dev,
> 2000);
> >
> > That could resolve this audio case since the autosuspend could suspend
> > runtime after
> > 2 seconds if there is no further dma transfer but only channel
> request(device_alloc_chan_resources).
> > But unfortunately, it cause another issue. As you know, on our
> > i.mx8qm/qxp, power domain done by scfw (drivers/firmware/imx/scu-pd.c)
> over mailbox:
> > imx_sc_pd_power()->imx_scu_call_rpc()->
> > imx_scu_ipc_write()->mbox_send_message()
> > which means have to 'waits for completion', meanwhile, some driver
> > like tty will call dmaengine interfaces in non-atomic case as below,
> >
> > static int uart_write(struct tty_struct *tty, const unsigned char
> > *buf, int count) {
> > .......
> > port = uart_port_lock(state, flags);
> > ......
> > __uart_start(tty); //call start_tx()->dmaengine_prep_slave_sg...
> > uart_port_unlock(port, flags);
> > return ret;
> > }
> >
> > Thus dma runtime resume may happen in that timing window and cause
> kernel alarm.
> > I'm not sure whether there are similar limitations on other driver
> > subsystem. But for me, It looks like the only way to resolve the
> > contradiction between tty and scu-pd (hardware limitation on
> > i.mx8qm/qxp) is to give up autosuspend and keep pm_runtime_get_sync
> only in device_alloc_chan_resources because request channel is a safe
> non-atomic phase.
> > Do you have any idea? Thanks in advance.
>
> If you look closely at the driver you used as an example (hidma.c) it looks like
> there is already something in there, which looks very much like what you need
> here:
>
> In hidma_issue_pending() the driver tries to get the device to runtime resume.
> If this doesn't work, maybe due to the power domain code not being able to
> be called in atomic context, the actual work of waking up the dma hardware
> and issuing the descriptor is shunted to a tasklet.
>
> If I'm reading this right, this is exactly what you need here to be able to call the
> dmaengine code from atomic context: try the rpm get and issue immediately
> when possible, otherwise shunt the work to a non- atomic context where you
> can deal with the requirements of scu-pd.
Yes, I can schedule_work to worker to runtime resume edma channel by calling scu-pd.
But that means all dmaengine interfaces should be taken care, not only issue_pending()
but also dmaengine_terminate_all()/dmaengine_pause()/dmaengine_resume()/
dmaengine_tx_status(). Not sure why hidma only take care issue_pending. Maybe
their user case is just for memcpy/memset so that no further complicate case as ALSA
or TTY.
Besides, for autosuspend in cyclic, we have to add pm_runtime_get_sync into interrupt
handler as qcom/bam_dma.c. but how could resolve the scu-pd's non-atmoic limitation
in interrupt handler?
>
> Also you don't need the runtime resume in all of the functions you mentioned.
> From a quick look into the edma driver it looks like for example the
> prep_slave_dma() function only touches data structures in memory, so you
> don't actually need the device to be awake at that point. Only later in the flow
> when you write registers in the dma hardware and actually issue the transfer
> you need to wake the device from sleep.
Yes, don't need add pm_runtime_get_sync into prep_slave_dma, only care where
HW indeed touched like issue_pending()/terminated_all()/pause()/resume..etc.
^ permalink raw reply
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