* Re: [PATCH v2] perf vendor events: Initial json/events list for power10 platform
From: Michael Ellerman @ 2021-04-19 12:38 UTC (permalink / raw)
To: Kajol Jain, acme
Cc: ravi.bangoria, atrajeev, kjain, linuxppc-dev, linux-kernel,
linux-perf-users, maddy, pc, jolsa
In-Reply-To: <20210419112001.71466-1-kjain@linux.ibm.com>
Kajol Jain <kjain@linux.ibm.com> writes:
> Patch adds initial json/events for POWER10.
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
cheers
> Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
> Tested-by: Paul A. Clarke <pc@us.ibm.com>
> Reviewed-by: Paul A. Clarke <pc@us.ibm.com>
> ---
> .../perf/pmu-events/arch/powerpc/mapfile.csv | 1 +
> .../arch/powerpc/power10/cache.json | 47 +++
> .../arch/powerpc/power10/floating_point.json | 7 +
> .../arch/powerpc/power10/frontend.json | 217 +++++++++++++
> .../arch/powerpc/power10/locks.json | 12 +
> .../arch/powerpc/power10/marked.json | 147 +++++++++
> .../arch/powerpc/power10/memory.json | 192 +++++++++++
> .../arch/powerpc/power10/others.json | 297 ++++++++++++++++++
> .../arch/powerpc/power10/pipeline.json | 297 ++++++++++++++++++
> .../pmu-events/arch/powerpc/power10/pmc.json | 22 ++
> .../arch/powerpc/power10/translation.json | 57 ++++
> 11 files changed, 1296 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/cache.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/frontend.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/locks.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/marked.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/memory.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/others.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/pmc.json
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/translation.json
>
> ---
> Changelog:
> v1 -> v2
> - Removed inconsistencies in "BriefDescription" field and make sure
> it will end with period without any space at the end.
> Suggested by : Paul A. Clarke
> - Added Tested-by and Reviewed-by tag.
> ---
> diff --git a/tools/perf/pmu-events/arch/powerpc/mapfile.csv b/tools/perf/pmu-events/arch/powerpc/mapfile.csv
> index 229150e7ab7d..4abdfc3f9692 100644
> --- a/tools/perf/pmu-events/arch/powerpc/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/powerpc/mapfile.csv
> @@ -15,3 +15,4 @@
> # Power8 entries
> 004[bcd][[:xdigit:]]{4},1,power8,core
> 004e[[:xdigit:]]{4},1,power9,core
> +0080[[:xdigit:]]{4},1,power10,core
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/cache.json b/tools/perf/pmu-events/arch/powerpc/power10/cache.json
> new file mode 100644
> index 000000000000..95e33531fbc6
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/cache.json
> @@ -0,0 +1,47 @@
> +[
> + {
> + "EventCode": "1003C",
> + "EventName": "PM_EXEC_STALL_DMISS_L2L3",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
> + },
> + {
> + "EventCode": "34056",
> + "EventName": "PM_EXEC_STALL_LOAD_FINISH",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the NTF instruction merged with another load in the LMQ."
> + },
> + {
> + "EventCode": "3006C",
> + "EventName": "PM_RUN_CYC_SMT2_MODE",
> + "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
> + },
> + {
> + "EventCode": "300F4",
> + "EventName": "PM_RUN_INST_CMPL_CONC",
> + "BriefDescription": "PowerPC instructions completed by this thread when all threads in the core had the run-latch set."
> + },
> + {
> + "EventCode": "4C016",
> + "EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."
> + },
> + {
> + "EventCode": "4D014",
> + "EventName": "PM_EXEC_STALL_LOAD",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit."
> + },
> + {
> + "EventCode": "4D016",
> + "EventName": "PM_EXEC_STALL_PTESYNC",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit."
> + },
> + {
> + "EventCode": "401EA",
> + "EventName": "PM_THRESH_EXC_128",
> + "BriefDescription": "Threshold counter exceeded a value of 128."
> + },
> + {
> + "EventCode": "400F6",
> + "EventName": "PM_BR_MPRED_CMPL",
> + "BriefDescription": "A mispredicted branch completed. Includes direction and target."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json b/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
> new file mode 100644
> index 000000000000..e9b92f282d3c
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
> @@ -0,0 +1,7 @@
> +[
> + {
> + "EventCode": "4016E",
> + "EventName": "PM_THRESH_NOT_MET",
> + "BriefDescription": "Threshold counter did not meet threshold."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/frontend.json b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json
> new file mode 100644
> index 000000000000..aebaf94bfdfe
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json
> @@ -0,0 +1,217 @@
> +[
> + {
> + "EventCode": "10004",
> + "EventName": "PM_EXEC_STALL_TRANSLATION",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or ERAT miss and waited for it to resolve."
> + },
> + {
> + "EventCode": "10010",
> + "EventName": "PM_PMC4_OVERFLOW",
> + "BriefDescription": "The event selected for PMC4 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "10020",
> + "EventName": "PM_PMC4_REWIND",
> + "BriefDescription": "The speculative event selected for PMC4 rewinds and the counter for PMC4 is not charged."
> + },
> + {
> + "EventCode": "10038",
> + "EventName": "PM_DISP_STALL_TRANSLATION",
> + "BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling a translation miss."
> + },
> + {
> + "EventCode": "1003A",
> + "EventName": "PM_DISP_STALL_BR_MPRED_IC_L2",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict."
> + },
> + {
> + "EventCode": "1E050",
> + "EventName": "PM_DISP_STALL_HELD_STF_MAPPER_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR."
> + },
> + {
> + "EventCode": "1F054",
> + "EventName": "PM_DTLB_HIT",
> + "BriefDescription": "The PTE required by the instruction was resident in the TLB (data TLB access). When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefetch. Applies to both HPT and RPT."
> + },
> + {
> + "EventCode": "101E8",
> + "EventName": "PM_THRESH_EXC_256",
> + "BriefDescription": "Threshold counter exceeded a count of 256."
> + },
> + {
> + "EventCode": "101EC",
> + "EventName": "PM_THRESH_MET",
> + "BriefDescription": "Threshold exceeded."
> + },
> + {
> + "EventCode": "100F2",
> + "EventName": "PM_1PLUS_PPC_CMPL",
> + "BriefDescription": "Cycles in which at least one instruction is completed by this thread."
> + },
> + {
> + "EventCode": "100F6",
> + "EventName": "PM_IERAT_MISS",
> + "BriefDescription": "IERAT Reloaded to satisfy an IERAT miss. All page sizes are counted by this event."
> + },
> + {
> + "EventCode": "100F8",
> + "EventName": "PM_DISP_STALL_CYC",
> + "BriefDescription": "Cycles the ICT has no itags assigned to this thread (no instructions were dispatched during these cycles)."
> + },
> + {
> + "EventCode": "20114",
> + "EventName": "PM_MRK_L2_RC_DISP",
> + "BriefDescription": "Marked instruction RC dispatched in L2."
> + },
> + {
> + "EventCode": "2C010",
> + "EventName": "PM_EXEC_STALL_LSU",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Load Store Unit. This does not include simple fixed point instructions."
> + },
> + {
> + "EventCode": "2C016",
> + "EventName": "PM_DISP_STALL_IERAT_ONLY_MISS",
> + "BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT miss."
> + },
> + {
> + "EventCode": "2C01E",
> + "EventName": "PM_DISP_STALL_BR_MPRED_IC_L3",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3 after suffering a branch mispredict."
> + },
> + {
> + "EventCode": "2D01A",
> + "EventName": "PM_DISP_STALL_IC_MISS",
> + "BriefDescription": "Cycles when dispatch was stalled for this thread due to an Icache Miss."
> + },
> + {
> + "EventCode": "2D01C",
> + "EventName": "PM_CMPL_STALL_STCX",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for resolution from the nest before completing."
> + },
> + {
> + "EventCode": "2E018",
> + "EventName": "PM_DISP_STALL_FETCH",
> + "BriefDescription": "Cycles when dispatch was stalled for this thread because Fetch was being held."
> + },
> + {
> + "EventCode": "2E01A",
> + "EventName": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the XVFC mapper/SRB was full."
> + },
> + {
> + "EventCode": "2C142",
> + "EventName": "PM_MRK_XFER_FROM_SRC_PMC2",
> + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "24050",
> + "EventName": "PM_IOPS_DISP",
> + "BriefDescription": "Internal Operations dispatched. PM_IOPS_DISP / PM_INST_DISP will show the average number of internal operations per PowerPC instruction."
> + },
> + {
> + "EventCode": "2405E",
> + "EventName": "PM_ISSUE_CANCEL",
> + "BriefDescription": "An instruction issued and the issue was later cancelled. Only one cancel per PowerPC instruction."
> + },
> + {
> + "EventCode": "200FA",
> + "EventName": "PM_BR_TAKEN_CMPL",
> + "BriefDescription": "Branch Taken instruction completed."
> + },
> + {
> + "EventCode": "30012",
> + "EventName": "PM_FLUSH_COMPLETION",
> + "BriefDescription": "The instruction that was next to complete (oldest in the pipeline) did not complete because it suffered a flush."
> + },
> + {
> + "EventCode": "30014",
> + "EventName": "PM_EXEC_STALL_STORE",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store instruction executing in the Load Store Unit."
> + },
> + {
> + "EventCode": "30018",
> + "EventName": "PM_DISP_STALL_HELD_SCOREBOARD_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."
> + },
> + {
> + "EventCode": "30026",
> + "EventName": "PM_EXEC_STALL_STORE_MISS",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store whose cache line was not resident in the L1 and was waiting for allocation of the missing line into the L1."
> + },
> + {
> + "EventCode": "3012A",
> + "EventName": "PM_MRK_L2_RC_DONE",
> + "BriefDescription": "L2 RC machine completed the transaction for the marked instruction."
> + },
> + {
> + "EventCode": "3F046",
> + "EventName": "PM_ITLB_HIT_1G",
> + "BriefDescription": "Instruction TLB hit (IERAT reload) page size 1G, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "34058",
> + "EventName": "PM_DISP_STALL_BR_MPRED_ICMISS",
> + "BriefDescription": "Cycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss."
> + },
> + {
> + "EventCode": "3D05C",
> + "EventName": "PM_DISP_STALL_HELD_RENAME_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC."
> + },
> + {
> + "EventCode": "3E052",
> + "EventName": "PM_DISP_STALL_IC_L3",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3."
> + },
> + {
> + "EventCode": "3E054",
> + "EventName": "PM_LD_MISS_L1",
> + "BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
> + },
> + {
> + "EventCode": "301EA",
> + "EventName": "PM_THRESH_EXC_1024",
> + "BriefDescription": "Threshold counter exceeded a value of 1024."
> + },
> + {
> + "EventCode": "300FA",
> + "EventName": "PM_INST_FROM_L3MISS",
> + "BriefDescription": "The processor's instruction cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."
> + },
> + {
> + "EventCode": "40006",
> + "EventName": "PM_ISSUE_KILL",
> + "BriefDescription": "Cycles in which an instruction or group of instructions were cancelled after being issued. This event increments once per occurrence, regardless of how many instructions are included in the issue group."
> + },
> + {
> + "EventCode": "40116",
> + "EventName": "PM_MRK_LARX_FIN",
> + "BriefDescription": "Marked load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "4C010",
> + "EventName": "PM_DISP_STALL_BR_MPRED_IC_L3MISS",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a mispredicted branch."
> + },
> + {
> + "EventCode": "4D01E",
> + "EventName": "PM_DISP_STALL_BR_MPRED",
> + "BriefDescription": "Cycles when dispatch was stalled for this thread due to a mispredicted branch."
> + },
> + {
> + "EventCode": "4E010",
> + "EventName": "PM_DISP_STALL_IC_L3MISS",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from any source beyond the local L3."
> + },
> + {
> + "EventCode": "4E01A",
> + "EventName": "PM_DISP_STALL_HELD_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any reason."
> + },
> + {
> + "EventCode": "44056",
> + "EventName": "PM_VECTOR_ST_CMPL",
> + "BriefDescription": "Vector store instructions completed."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/locks.json b/tools/perf/pmu-events/arch/powerpc/power10/locks.json
> new file mode 100644
> index 000000000000..fa81b470d21f
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/locks.json
> @@ -0,0 +1,12 @@
> +[
> + {
> + "EventCode": "1E058",
> + "EventName": "PM_STCX_FAIL_FIN",
> + "BriefDescription": "Conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "4E050",
> + "EventName": "PM_STCX_PASS_FIN",
> + "BriefDescription": "Conditional store instruction (STCX) passed. LARX and STCX are instructions used to acquire a lock."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/marked.json b/tools/perf/pmu-events/arch/powerpc/power10/marked.json
> new file mode 100644
> index 000000000000..ffe38525b18b
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/marked.json
> @@ -0,0 +1,147 @@
> +[
> + {
> + "EventCode": "1002C",
> + "EventName": "PM_LD_PREFETCH_CACHE_LINE_MISS",
> + "BriefDescription": "The L1 cache was reloaded with a line that fulfills a prefetch request."
> + },
> + {
> + "EventCode": "10132",
> + "EventName": "PM_MRK_INST_ISSUED",
> + "BriefDescription": "Marked instruction issued. Note that stores always get issued twice, the address gets issued to the LSU and the data gets issued to the VSU. Also, issues can sometimes get killed/cancelled and cause multiple sequential issues for the same instruction."
> + },
> + {
> + "EventCode": "101E0",
> + "EventName": "PM_MRK_INST_DISP",
> + "BriefDescription": "The thread has dispatched a randomly sampled marked instruction."
> + },
> + {
> + "EventCode": "101E2",
> + "EventName": "PM_MRK_BR_TAKEN_CMPL",
> + "BriefDescription": "Marked Branch Taken instruction completed."
> + },
> + {
> + "EventCode": "20112",
> + "EventName": "PM_MRK_NTF_FIN",
> + "BriefDescription": "The marked instruction became the oldest in the pipeline before it finished. It excludes instructions that finish at dispatch."
> + },
> + {
> + "EventCode": "2C01C",
> + "EventName": "PM_EXEC_STALL_DMISS_OFF_CHIP",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a remote chip."
> + },
> + {
> + "EventCode": "20138",
> + "EventName": "PM_MRK_ST_NEST",
> + "BriefDescription": "A store has been sampled/marked and is at the point of execution where it has completed in the core and can no longer be flushed. At this point the store is sent to the L2."
> + },
> + {
> + "EventCode": "2013A",
> + "EventName": "PM_MRK_BRU_FIN",
> + "BriefDescription": "Marked Branch instruction finished."
> + },
> + {
> + "EventCode": "2C144",
> + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC2",
> + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[15:27]."
> + },
> + {
> + "EventCode": "24156",
> + "EventName": "PM_MRK_STCX_FIN",
> + "BriefDescription": "Marked conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "24158",
> + "EventName": "PM_MRK_INST",
> + "BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens."
> + },
> + {
> + "EventCode": "2415C",
> + "EventName": "PM_MRK_BR_CMPL",
> + "BriefDescription": "A marked branch completed. All branches are included."
> + },
> + {
> + "EventCode": "200FD",
> + "EventName": "PM_L1_ICACHE_MISS",
> + "BriefDescription": "Demand iCache Miss."
> + },
> + {
> + "EventCode": "30130",
> + "EventName": "PM_MRK_INST_FIN",
> + "BriefDescription": "marked instruction finished. Excludes instructions that finish at dispatch. Note that stores always finish twice since the address gets issued to the LSU and the data gets issued to the VSU."
> + },
> + {
> + "EventCode": "34146",
> + "EventName": "PM_MRK_LD_CMPL",
> + "BriefDescription": "Marked loads completed."
> + },
> + {
> + "EventCode": "3E158",
> + "EventName": "PM_MRK_STCX_FAIL",
> + "BriefDescription": "Marked conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "3E15A",
> + "EventName": "PM_MRK_ST_FIN",
> + "BriefDescription": "The marked instruction was a store of any kind."
> + },
> + {
> + "EventCode": "30068",
> + "EventName": "PM_L1_ICACHE_RELOADED_PREF",
> + "BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)."
> + },
> + {
> + "EventCode": "301E4",
> + "EventName": "PM_MRK_BR_MPRED_CMPL",
> + "BriefDescription": "Marked Branch Mispredicted. Includes direction and target."
> + },
> + {
> + "EventCode": "300F6",
> + "EventName": "PM_LD_DEMAND_MISS_L1",
> + "BriefDescription": "The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish."
> + },
> + {
> + "EventCode": "300FE",
> + "EventName": "PM_DATA_FROM_L3MISS",
> + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."
> + },
> + {
> + "EventCode": "40012",
> + "EventName": "PM_L1_ICACHE_RELOADED_ALL",
> + "BriefDescription": "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch."
> + },
> + {
> + "EventCode": "40134",
> + "EventName": "PM_MRK_INST_TIMEO",
> + "BriefDescription": "Marked instruction finish timeout (instruction was lost)."
> + },
> + {
> + "EventCode": "4003C",
> + "EventName": "PM_DISP_STALL_HELD_SYNC_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch."
> + },
> + {
> + "EventCode": "4505A",
> + "EventName": "PM_SP_FLOP_CMPL",
> + "BriefDescription": "Single Precision floating point instructions completed."
> + },
> + {
> + "EventCode": "4D058",
> + "EventName": "PM_VECTOR_FLOP_CMPL",
> + "BriefDescription": "Vector floating point instructions completed."
> + },
> + {
> + "EventCode": "4D05A",
> + "EventName": "PM_NON_MATH_FLOP_CMPL",
> + "BriefDescription": "Non Math instructions completed."
> + },
> + {
> + "EventCode": "401E0",
> + "EventName": "PM_MRK_INST_CMPL",
> + "BriefDescription": "marked instruction completed."
> + },
> + {
> + "EventCode": "400FE",
> + "EventName": "PM_DATA_FROM_MEMORY",
> + "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/memory.json b/tools/perf/pmu-events/arch/powerpc/power10/memory.json
> new file mode 100644
> index 000000000000..6e47b96e2d66
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/memory.json
> @@ -0,0 +1,192 @@
> +[
> + {
> + "EventCode": "1000A",
> + "EventName": "PM_PMC3_REWIND",
> + "BriefDescription": "The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged."
> + },
> + {
> + "EventCode": "1C040",
> + "EventName": "PM_XFER_FROM_SRC_PMC1",
> + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "1C142",
> + "EventName": "PM_MRK_XFER_FROM_SRC_PMC1",
> + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "1C144",
> + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1",
> + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]."
> + },
> + {
> + "EventCode": "1C056",
> + "EventName": "PM_DERAT_MISS_4K",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "1C058",
> + "EventName": "PM_DTLB_MISS_16G",
> + "BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "1C05C",
> + "EventName": "PM_DTLB_MISS_2M",
> + "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "1E056",
> + "EventName": "PM_EXEC_STALL_STORE_PIPE",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions."
> + },
> + {
> + "EventCode": "1F150",
> + "EventName": "PM_MRK_ST_L2_CYC",
> + "BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion."
> + },
> + {
> + "EventCode": "10062",
> + "EventName": "PM_LD_L3MISS_PEND_CYC",
> + "BriefDescription": "Cycles L3 miss was pending for this thread."
> + },
> + {
> + "EventCode": "20010",
> + "EventName": "PM_PMC1_OVERFLOW",
> + "BriefDescription": "The event selected for PMC1 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "2001A",
> + "EventName": "PM_ITLB_HIT",
> + "BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "2003E",
> + "EventName": "PM_PTESYNC_FIN",
> + "BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time."
> + },
> + {
> + "EventCode": "2C040",
> + "EventName": "PM_XFER_FROM_SRC_PMC2",
> + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "2C054",
> + "EventName": "PM_DERAT_MISS_64K",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "2C056",
> + "EventName": "PM_DTLB_MISS_4K",
> + "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "2D154",
> + "EventName": "PM_MRK_DERAT_MISS_64K",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "200F6",
> + "EventName": "PM_DERAT_MISS",
> + "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "3000A",
> + "EventName": "PM_DISP_STALL_ITLB_MISS",
> + "BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction TLB miss."
> + },
> + {
> + "EventCode": "30016",
> + "EventName": "PM_EXEC_STALL_DERAT_DTLB_MISS",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve."
> + },
> + {
> + "EventCode": "3C040",
> + "EventName": "PM_XFER_FROM_SRC_PMC3",
> + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "3C142",
> + "EventName": "PM_MRK_XFER_FROM_SRC_PMC3",
> + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "3C144",
> + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC3",
> + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]."
> + },
> + {
> + "EventCode": "3C054",
> + "EventName": "PM_DERAT_MISS_16M",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "3C056",
> + "EventName": "PM_DTLB_MISS_64K",
> + "BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "3C058",
> + "EventName": "PM_LARX_FIN",
> + "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "301E2",
> + "EventName": "PM_MRK_ST_CMPL",
> + "BriefDescription": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores."
> + },
> + {
> + "EventCode": "300FC",
> + "EventName": "PM_DTLB_MISS",
> + "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity."
> + },
> + {
> + "EventCode": "4D02C",
> + "EventName": "PM_PMC1_REWIND",
> + "BriefDescription": "The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged."
> + },
> + {
> + "EventCode": "4003E",
> + "EventName": "PM_LD_CMPL",
> + "BriefDescription": "Loads completed."
> + },
> + {
> + "EventCode": "4C040",
> + "EventName": "PM_XFER_FROM_SRC_PMC4",
> + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "4C142",
> + "EventName": "PM_MRK_XFER_FROM_SRC_PMC4",
> + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> + },
> + {
> + "EventCode": "4C144",
> + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC4",
> + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]."
> + },
> + {
> + "EventCode": "4C056",
> + "EventName": "PM_DTLB_MISS_16M",
> + "BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "4C05A",
> + "EventName": "PM_DTLB_MISS_1G",
> + "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "4C15E",
> + "EventName": "PM_MRK_DTLB_MISS_64K",
> + "BriefDescription": "Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "4D056",
> + "EventName": "PM_NON_FMA_FLOP_CMPL",
> + "BriefDescription": "Non FMA instruction completed."
> + },
> + {
> + "EventCode": "40164",
> + "EventName": "PM_MRK_DERAT_MISS_2M",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/others.json b/tools/perf/pmu-events/arch/powerpc/power10/others.json
> new file mode 100644
> index 000000000000..2992f7961134
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/others.json
> @@ -0,0 +1,297 @@
> +[
> + {
> + "EventCode": "10016",
> + "EventName": "PM_VSU0_ISSUE",
> + "BriefDescription": "VSU instructions issued to VSU pipe 0."
> + },
> + {
> + "EventCode": "1001C",
> + "EventName": "PM_ULTRAVISOR_INST_CMPL",
> + "BriefDescription": "PowerPC instructions that completed while the thread was in ultravisor state."
> + },
> + {
> + "EventCode": "100F0",
> + "EventName": "PM_CYC",
> + "BriefDescription": "Processor cycles."
> + },
> + {
> + "EventCode": "10134",
> + "EventName": "PM_MRK_ST_DONE_L2",
> + "BriefDescription": "Marked stores completed in L2 (RC machine done)."
> + },
> + {
> + "EventCode": "1505E",
> + "EventName": "PM_LD_HIT_L1",
> + "BriefDescription": "Loads that finished without experiencing an L1 miss."
> + },
> + {
> + "EventCode": "1D05E",
> + "EventName": "PM_DISP_STALL_HELD_HALT_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of power management."
> + },
> + {
> + "EventCode": "1E054",
> + "EventName": "PM_EXEC_STALL_DMISS_L21_L31",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip."
> + },
> + {
> + "EventCode": "1E05A",
> + "EventName": "PM_CMPL_STALL_LWSYNC",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting to complete."
> + },
> + {
> + "EventCode": "1F056",
> + "EventName": "PM_DISP_SS0_2_INSTR_CYC",
> + "BriefDescription": "Cycles in which Superslice 0 dispatches either 1 or 2 instructions."
> + },
> + {
> + "EventCode": "1F15C",
> + "EventName": "PM_MRK_STCX_L2_CYC",
> + "BriefDescription": "Cycles spent in the nest portion of a marked Stcx instruction. It starts counting when the operation starts to drain to the L2 and it stops counting when the instruction retires from the Instruction Completion Table (ICT) in the Instruction Sequencing Unit (ISU)."
> + },
> + {
> + "EventCode": "10066",
> + "EventName": "PM_ADJUNCT_CYC",
> + "BriefDescription": "Cycles in which the thread is in Adjunct state. MSR[S HV PR] bits = 011."
> + },
> + {
> + "EventCode": "101E4",
> + "EventName": "PM_MRK_L1_ICACHE_MISS",
> + "BriefDescription": "Marked Instruction suffered an icache Miss."
> + },
> + {
> + "EventCode": "101EA",
> + "EventName": "PM_MRK_L1_RELOAD_VALID",
> + "BriefDescription": "Marked demand reload."
> + },
> + {
> + "EventCode": "100F4",
> + "EventName": "PM_FLOP_CMPL",
> + "BriefDescription": "Floating Point Operations Completed. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1|2|4|8_FLOP_CMPL events to count flops."
> + },
> + {
> + "EventCode": "100FA",
> + "EventName": "PM_RUN_LATCH_ANY_THREAD_CYC",
> + "BriefDescription": "Cycles when at least one thread has the run latch set."
> + },
> + {
> + "EventCode": "100FC",
> + "EventName": "PM_LD_REF_L1",
> + "BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included."
> + },
> + {
> + "EventCode": "20006",
> + "EventName": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue."
> + },
> + {
> + "EventCode": "2000C",
> + "EventName": "PM_RUN_LATCH_ALL_THREADS_CYC",
> + "BriefDescription": "Cycles when the run latch is set for all threads."
> + },
> + {
> + "EventCode": "2E010",
> + "EventName": "PM_ADJUNCT_INST_CMPL",
> + "BriefDescription": "PowerPC instructions that completed while the thread is in Adjunct state."
> + },
> + {
> + "EventCode": "2E014",
> + "EventName": "PM_STCX_FIN",
> + "BriefDescription": "Conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."
> + },
> + {
> + "EventCode": "20130",
> + "EventName": "PM_MRK_INST_DECODED",
> + "BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only."
> + },
> + {
> + "EventCode": "20132",
> + "EventName": "PM_MRK_DFU_ISSUE",
> + "BriefDescription": "The marked instruction was a decimal floating point operation issued to the VSU. Measured at issue time."
> + },
> + {
> + "EventCode": "20134",
> + "EventName": "PM_MRK_FXU_ISSUE",
> + "BriefDescription": "The marked instruction was a fixed point operation issued to the VSU. Measured at issue time."
> + },
> + {
> + "EventCode": "2505C",
> + "EventName": "PM_VSU_ISSUE",
> + "BriefDescription": "At least one VSU instruction was issued to one of the VSU pipes. Up to 4 per cycle. Includes fixed point operations."
> + },
> + {
> + "EventCode": "2F054",
> + "EventName": "PM_DISP_SS1_2_INSTR_CYC",
> + "BriefDescription": "Cycles in which Superslice 1 dispatches either 1 or 2 instructions."
> + },
> + {
> + "EventCode": "2F056",
> + "EventName": "PM_DISP_SS1_4_INSTR_CYC",
> + "BriefDescription": "Cycles in which Superslice 1 dispatches either 3 or 4 instructions."
> + },
> + {
> + "EventCode": "2006C",
> + "EventName": "PM_RUN_CYC_SMT4_MODE",
> + "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT4 mode."
> + },
> + {
> + "EventCode": "201E0",
> + "EventName": "PM_MRK_DATA_FROM_MEMORY",
> + "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked load."
> + },
> + {
> + "EventCode": "201E4",
> + "EventName": "PM_MRK_DATA_FROM_L3MISS",
> + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked load."
> + },
> + {
> + "EventCode": "201E8",
> + "EventName": "PM_THRESH_EXC_512",
> + "BriefDescription": "Threshold counter exceeded a value of 512."
> + },
> + {
> + "EventCode": "200F2",
> + "EventName": "PM_INST_DISP",
> + "BriefDescription": "PowerPC instructions dispatched."
> + },
> + {
> + "EventCode": "30132",
> + "EventName": "PM_MRK_VSU_FIN",
> + "BriefDescription": "VSU marked instructions finished. Excludes simple FX instructions issued to the Store Unit."
> + },
> + {
> + "EventCode": "30038",
> + "EventName": "PM_EXEC_STALL_DMISS_LMEM",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCapp cache, or local OpenCapp memory."
> + },
> + {
> + "EventCode": "3F04A",
> + "EventName": "PM_LSU_ST5_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST2 port."
> + },
> + {
> + "EventCode": "34054",
> + "EventName": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict."
> + },
> + {
> + "EventCode": "3405A",
> + "EventName": "PM_PRIVILEGED_INST_CMPL",
> + "BriefDescription": "PowerPC Instructions that completed while the thread is in Privileged state."
> + },
> + {
> + "EventCode": "3F150",
> + "EventName": "PM_MRK_ST_DRAIN_CYC",
> + "BriefDescription": "cycles to drain st from core to L2."
> + },
> + {
> + "EventCode": "3F054",
> + "EventName": "PM_DISP_SS0_4_INSTR_CYC",
> + "BriefDescription": "Cycles in which Superslice 0 dispatches either 3 or 4 instructions."
> + },
> + {
> + "EventCode": "3F056",
> + "EventName": "PM_DISP_SS0_8_INSTR_CYC",
> + "BriefDescription": "Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions."
> + },
> + {
> + "EventCode": "30162",
> + "EventName": "PM_MRK_ISSUE_DEPENDENT_LOAD",
> + "BriefDescription": "The marked instruction was dependent on a load. It is eligible for issue kill."
> + },
> + {
> + "EventCode": "40114",
> + "EventName": "PM_MRK_START_PROBE_NOP_DISP",
> + "BriefDescription": "Marked Start probe nop dispatched. Instruction AND R0,R0,R0."
> + },
> + {
> + "EventCode": "4001C",
> + "EventName": "PM_VSU_FIN",
> + "BriefDescription": "VSU instructions finished."
> + },
> + {
> + "EventCode": "4C01A",
> + "EventName": "PM_EXEC_STALL_DMISS_OFF_NODE",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a distant chip."
> + },
> + {
> + "EventCode": "4D012",
> + "EventName": "PM_PMC3_SAVED",
> + "BriefDescription": "The conditions for the speculative event selected for PMC3 are met and PMC3 is charged."
> + },
> + {
> + "EventCode": "4D022",
> + "EventName": "PM_HYPERVISOR_INST_CMPL",
> + "BriefDescription": "PowerPC instructions that completed while the thread is in hypervisor state."
> + },
> + {
> + "EventCode": "4D026",
> + "EventName": "PM_ULTRAVISOR_CYC",
> + "BriefDescription": "Cycles when the thread is in Ultravisor state. MSR[S HV PR]=110."
> + },
> + {
> + "EventCode": "4D028",
> + "EventName": "PM_PRIVILEGED_CYC",
> + "BriefDescription": "Cycles when the thread is in Privileged state. MSR[S HV PR]=x00."
> + },
> + {
> + "EventCode": "40030",
> + "EventName": "PM_INST_FIN",
> + "BriefDescription": "Instructions finished."
> + },
> + {
> + "EventCode": "44146",
> + "EventName": "PM_MRK_STCX_CORE_CYC",
> + "BriefDescription": "Cycles spent in the core portion of a marked Stcx instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2."
> + },
> + {
> + "EventCode": "44054",
> + "EventName": "PM_VECTOR_LD_CMPL",
> + "BriefDescription": "Vector load instructions completed."
> + },
> + {
> + "EventCode": "45054",
> + "EventName": "PM_FMA_CMPL",
> + "BriefDescription": "Two floating point instructions completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only."
> + },
> + {
> + "EventCode": "45056",
> + "EventName": "PM_SCALAR_FLOP_CMPL",
> + "BriefDescription": "Scalar floating point instructions completed."
> + },
> + {
> + "EventCode": "4505C",
> + "EventName": "PM_MATH_FLOP_CMPL",
> + "BriefDescription": "Math floating point instructions completed."
> + },
> + {
> + "EventCode": "4D05E",
> + "EventName": "PM_BR_CMPL",
> + "BriefDescription": "A branch completed. All branches are included."
> + },
> + {
> + "EventCode": "4E15E",
> + "EventName": "PM_MRK_INST_FLUSHED",
> + "BriefDescription": "The marked instruction was flushed."
> + },
> + {
> + "EventCode": "401E6",
> + "EventName": "PM_MRK_INST_FROM_L3MISS",
> + "BriefDescription": "The processor's instruction cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked instruction."
> + },
> + {
> + "EventCode": "401E8",
> + "EventName": "PM_MRK_DATA_FROM_L2MISS",
> + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1 or L2 due to a demand miss for a marked load."
> + },
> + {
> + "EventCode": "400F0",
> + "EventName": "PM_LD_DEMAND_MISS_L1_FIN",
> + "BriefDescription": "Load Missed L1, counted at finish time."
> + },
> + {
> + "EventCode": "400FA",
> + "EventName": "PM_RUN_INST_CMPL",
> + "BriefDescription": "Completed PowerPC instructions gated by the run latch."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json b/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
> new file mode 100644
> index 000000000000..33c1c39ea323
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
> @@ -0,0 +1,297 @@
> +[
> + {
> + "EventCode": "100FE",
> + "EventName": "PM_INST_CMPL",
> + "BriefDescription": "PowerPC instructions completed."
> + },
> + {
> + "EventCode": "10006",
> + "EventName": "PM_DISP_STALL_HELD_OTHER_CYC",
> + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any other reason."
> + },
> + {
> + "EventCode": "1000C",
> + "EventName": "PM_LSU_LD0_FIN",
> + "BriefDescription": "LSU Finished an internal operation in LD0 port."
> + },
> + {
> + "EventCode": "1000E",
> + "EventName": "PM_MMA_ISSUED",
> + "BriefDescription": "MMA instructions issued."
> + },
> + {
> + "EventCode": "10012",
> + "EventName": "PM_LSU_ST0_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST0 port."
> + },
> + {
> + "EventCode": "10014",
> + "EventName": "PM_LSU_ST4_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST4 port."
> + },
> + {
> + "EventCode": "10018",
> + "EventName": "PM_IC_DEMAND_CYC",
> + "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss."
> + },
> + {
> + "EventCode": "10022",
> + "EventName": "PM_PMC2_SAVED",
> + "BriefDescription": "The conditions for the speculative event selected for PMC2 are met and PMC2 is charged."
> + },
> + {
> + "EventCode": "10024",
> + "EventName": "PM_PMC5_OVERFLOW",
> + "BriefDescription": "The event selected for PMC5 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "10058",
> + "EventName": "PM_EXEC_STALL_FIN_AT_DISP",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch and did not require execution in the LSU, BRU or VSU."
> + },
> + {
> + "EventCode": "1005A",
> + "EventName": "PM_FLUSH_MPRED",
> + "BriefDescription": "A flush occurred due to a mispredicted branch. Includes target and direction."
> + },
> + {
> + "EventCode": "1C05A",
> + "EventName": "PM_DERAT_MISS_2M",
> + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> + },
> + {
> + "EventCode": "10064",
> + "EventName": "PM_DISP_STALL_IC_L2",
> + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2."
> + },
> + {
> + "EventCode": "10068",
> + "EventName": "PM_BR_FIN",
> + "BriefDescription": "A branch instruction finished. Includes predicted/mispredicted/unconditional."
> + },
> + {
> + "EventCode": "1006A",
> + "EventName": "PM_FX_LSU_FIN",
> + "BriefDescription": "Simple fixed point instruction issued to the store unit. Measured at finish time."
> + },
> + {
> + "EventCode": "1006C",
> + "EventName": "PM_RUN_CYC_ST_MODE",
> + "BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
> + },
> + {
> + "EventCode": "20004",
> + "EventName": "PM_ISSUE_STALL",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not issued yet."
> + },
> + {
> + "EventCode": "2000A",
> + "EventName": "PM_HYPERVISOR_CYC",
> + "BriefDescription": "Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010."
> + },
> + {
> + "EventCode": "2000E",
> + "EventName": "PM_LSU_LD1_FIN",
> + "BriefDescription": "LSU Finished an internal operation in LD1 port."
> + },
> + {
> + "EventCode": "2C014",
> + "EventName": "PM_CMPL_STALL_SPECIAL",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handling before completing."
> + },
> + {
> + "EventCode": "2C018",
> + "EventName": "PM_EXEC_STALL_DMISS_L3MISS",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a source beyond the local L2 or local L3."
> + },
> + {
> + "EventCode": "2D010",
> + "EventName": "PM_LSU_ST1_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST1 port."
> + },
> + {
> + "EventCode": "2D012",
> + "EventName": "PM_VSU1_ISSUE",
> + "BriefDescription": "VSU instructions issued to VSU pipe 1."
> + },
> + {
> + "EventCode": "2D018",
> + "EventName": "PM_EXEC_STALL_VSU",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the VSU (includes FXU, VSU, CRU)."
> + },
> + {
> + "EventCode": "2E01E",
> + "EventName": "PM_EXEC_STALL_NTC_FLUSH",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in any unit before it was flushed. Note that if the flush of the oldest instruction happens after finish, the cycles from dispatch to issue will be included in PM_DISP_STALL and the cycles from issue to finish will be included in PM_EXEC_STALL and its corresponding children."
> + },
> + {
> + "EventCode": "2013C",
> + "EventName": "PM_MRK_FX_LSU_FIN",
> + "BriefDescription": "The marked instruction was simple fixed point that was issued to the store unit. Measured at finish time."
> + },
> + {
> + "EventCode": "2405A",
> + "EventName": "PM_NTC_FIN",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note that instructions can finish out of order, therefore not all the instructions that finish have a Next-to-complete status."
> + },
> + {
> + "EventCode": "201E2",
> + "EventName": "PM_MRK_LD_MISS_L1",
> + "BriefDescription": "Marked DL1 Demand Miss counted at finish time."
> + },
> + {
> + "EventCode": "200F4",
> + "EventName": "PM_RUN_CYC",
> + "BriefDescription": "Processor cycles gated by the run latch."
> + },
> + {
> + "EventCode": "30004",
> + "EventName": "PM_DISP_STALL_FLUSH",
> + "BriefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet NTC. PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC."
> + },
> + {
> + "EventCode": "30008",
> + "EventName": "PM_EXEC_STALL",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting to finish in one of the execution units (BRU, LSU, VSU). Only cycles between issue and finish are counted in this category."
> + },
> + {
> + "EventCode": "3001A",
> + "EventName": "PM_LSU_ST2_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST2 port."
> + },
> + {
> + "EventCode": "30020",
> + "EventName": "PM_PMC2_REWIND",
> + "BriefDescription": "The speculative event selected for PMC2 rewinds and the counter for PMC2 is not charged."
> + },
> + {
> + "EventCode": "30022",
> + "EventName": "PM_PMC4_SAVED",
> + "BriefDescription": "The conditions for the speculative event selected for PMC4 are met and PMC4 is charged."
> + },
> + {
> + "EventCode": "30024",
> + "EventName": "PM_PMC6_OVERFLOW",
> + "BriefDescription": "The event selected for PMC6 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "30028",
> + "EventName": "PM_CMPL_STALL_MEM_ECC",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC."
> + },
> + {
> + "EventCode": "30036",
> + "EventName": "PM_EXEC_STALL_SIMPLE_FX",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a simple fixed point instruction executing in the Load Store Unit."
> + },
> + {
> + "EventCode": "3003A",
> + "EventName": "PM_CMPL_STALL_EXCEPTION",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete."
> + },
> + {
> + "EventCode": "3F044",
> + "EventName": "PM_VSU2_ISSUE",
> + "BriefDescription": "VSU instructions issued to VSU pipe 2."
> + },
> + {
> + "EventCode": "30058",
> + "EventName": "PM_TLBIE_FIN",
> + "BriefDescription": "TLBIE instructions finished in the LSU. Two TLBIEs can finish each cycle. All will be counted."
> + },
> + {
> + "EventCode": "3D058",
> + "EventName": "PM_SCALAR_FSQRT_FDIV_ISSUE",
> + "BriefDescription": "Scalar versions of four floating point operations: fdiv,fsqrt (xvdivdp, xvdivsp, xvsqrtdp, xvsqrtsp)."
> + },
> + {
> + "EventCode": "30066",
> + "EventName": "PM_LSU_FIN",
> + "BriefDescription": "LSU Finished an internal operation (up to 4 per cycle)."
> + },
> + {
> + "EventCode": "40004",
> + "EventName": "PM_FXU_ISSUE",
> + "BriefDescription": "A fixed point instruction was issued to the VSU."
> + },
> + {
> + "EventCode": "40008",
> + "EventName": "PM_NTC_ALL_FIN",
> + "BriefDescription": "Cycles in which both instructions in the ICT entry pair show as finished. These are the cycles between finish and completion for the oldest pair of instructions in the pipeline."
> + },
> + {
> + "EventCode": "40010",
> + "EventName": "PM_PMC3_OVERFLOW",
> + "BriefDescription": "The event selected for PMC3 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "4C012",
> + "EventName": "PM_EXEC_STALL_DERAT_ONLY_MISS",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered an ERAT miss and waited for it resolve."
> + },
> + {
> + "EventCode": "4C018",
> + "EventName": "PM_CMPL_STALL",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline cannot complete because the thread was blocked for any reason."
> + },
> + {
> + "EventCode": "4C01E",
> + "EventName": "PM_LSU_ST3_FIN",
> + "BriefDescription": "LSU Finished an internal operation in ST3 port."
> + },
> + {
> + "EventCode": "4D018",
> + "EventName": "PM_EXEC_STALL_BRU",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Branch unit."
> + },
> + {
> + "EventCode": "4D01A",
> + "EventName": "PM_CMPL_STALL_HWSYNC",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a hwsync waiting for response from L2 before completing."
> + },
> + {
> + "EventCode": "4D01C",
> + "EventName": "PM_EXEC_STALL_TLBIEL",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIEL instruction executing in the Load Store Unit. TLBIEL instructions have lower overhead than TLBIE instructions because they don't get set to the nest."
> + },
> + {
> + "EventCode": "4E012",
> + "EventName": "PM_EXEC_STALL_UNKNOWN",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline completed without an ntf_type pulse. The ntf_pulse was missed by the ISU because the NTF finishes and completions came too close together."
> + },
> + {
> + "EventCode": "4D020",
> + "EventName": "PM_VSU3_ISSUE",
> + "BriefDescription": "VSU instruction was issued to VSU pipe 3."
> + },
> + {
> + "EventCode": "40132",
> + "EventName": "PM_MRK_LSU_FIN",
> + "BriefDescription": "LSU marked instruction finish."
> + },
> + {
> + "EventCode": "45058",
> + "EventName": "PM_IC_MISS_CMPL",
> + "BriefDescription": "Non-speculative icache miss, counted at completion."
> + },
> + {
> + "EventCode": "4D050",
> + "EventName": "PM_VSU_NON_FLOP_CMPL",
> + "BriefDescription": "Non-floating point VSU instructions completed."
> + },
> + {
> + "EventCode": "4D052",
> + "EventName": "PM_2FLOP_CMPL",
> + "BriefDescription": "Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg completed."
> + },
> + {
> + "EventCode": "400F2",
> + "EventName": "PM_1PLUS_PPC_DISP",
> + "BriefDescription": "Cycles at least one Instr Dispatched."
> + },
> + {
> + "EventCode": "400F8",
> + "EventName": "PM_FLUSH",
> + "BriefDescription": "Flush (any type)."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/pmc.json b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json
> new file mode 100644
> index 000000000000..60a0100ee996
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json
> @@ -0,0 +1,22 @@
> +[
> + {
> + "EventCode": "301E8",
> + "EventName": "PM_THRESH_EXC_64",
> + "BriefDescription": "Threshold counter exceeded a value of 64."
> + },
> + {
> + "EventCode": "45050",
> + "EventName": "PM_1FLOP_CMPL",
> + "BriefDescription": "One floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
> + },
> + {
> + "EventCode": "45052",
> + "EventName": "PM_4FLOP_CMPL",
> + "BriefDescription": "Four floating point instructions completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
> + },
> + {
> + "EventCode": "4D054",
> + "EventName": "PM_8FLOP_CMPL",
> + "BriefDescription": "Four Double Precision vector instructions completed."
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/translation.json b/tools/perf/pmu-events/arch/powerpc/power10/translation.json
> new file mode 100644
> index 000000000000..da44d4ca6ef3
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/translation.json
> @@ -0,0 +1,57 @@
> +[
> + {
> + "EventCode": "1F15E",
> + "EventName": "PM_MRK_START_PROBE_NOP_CMPL",
> + "BriefDescription": "Marked Start probe nop (AND R0,R0,R0) completed."
> + },
> + {
> + "EventCode": "20016",
> + "EventName": "PM_ST_FIN",
> + "BriefDescription": "Store finish count. Includes speculative activity."
> + },
> + {
> + "EventCode": "20018",
> + "EventName": "PM_ST_FWD",
> + "BriefDescription": "Store forwards that finished."
> + },
> + {
> + "EventCode": "2011C",
> + "EventName": "PM_MRK_NTF_CYC",
> + "BriefDescription": "Cycles during which the marked instruction is the oldest in the pipeline (NTF or NTC)."
> + },
> + {
> + "EventCode": "2E01C",
> + "EventName": "PM_EXEC_STALL_TLBIE",
> + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIE instruction executing in the Load Store Unit."
> + },
> + {
> + "EventCode": "201E6",
> + "EventName": "PM_THRESH_EXC_32",
> + "BriefDescription": "Threshold counter exceeded a value of 32."
> + },
> + {
> + "EventCode": "200F0",
> + "EventName": "PM_ST_CMPL",
> + "BriefDescription": "Stores completed from S2Q (2nd-level store queue). This event includes regular stores, stcx and cache inhibited stores. The following operations are excluded (pteupdate, snoop tlbie complete, store atomics, miso, load atomic payloads, tlbie, tlbsync, slbieg, isync, msgsnd, slbiag, cpabort, copy, tcheck, tend, stsync, dcbst, icbi, dcbf, hwsync, lwsync, ptesync, eieio, msgsync)."
> + },
> + {
> + "EventCode": "200FE",
> + "EventName": "PM_DATA_FROM_L2MISS",
> + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1 or L2 due to a demand miss."
> + },
> + {
> + "EventCode": "30010",
> + "EventName": "PM_PMC2_OVERFLOW",
> + "BriefDescription": "The event selected for PMC2 caused the event counter to overflow."
> + },
> + {
> + "EventCode": "4D010",
> + "EventName": "PM_PMC1_SAVED",
> + "BriefDescription": "The conditions for the speculative event selected for PMC1 are met and PMC1 is charged."
> + },
> + {
> + "EventCode": "4D05C",
> + "EventName": "PM_DPP_FLOP_CMPL",
> + "BriefDescription": "Double-Precision or Quad-Precision instructions completed."
> + }
> +]
> --
> 2.27.0
^ permalink raw reply
* Re: [PATCH] powerpc/pseries/mce: Fix a typo in error type assignment
From: Michael Ellerman @ 2021-04-19 12:39 UTC (permalink / raw)
To: Ganesh, linuxppc-dev; +Cc: mahesh, npiggin
In-Reply-To: <4c45d421-ea8c-6243-ee15-ebc85dc733a6@linux.ibm.com>
Ganesh <ganeshgr@linux.ibm.com> writes:
> On 4/17/21 6:06 PM, Michael Ellerman wrote:
>
>> Ganesh Goudar <ganeshgr@linux.ibm.com> writes:
>>> The error type is ICACHE and DCACHE, for case MCE_ERROR_TYPE_ICACHE.
>> Do you mean "is ICACHE not DCACHE" ?
>
> Right :), Should I send v2 ?
No I can fix it up :)
cheers
>>> Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com>
>>> ---
>>> arch/powerpc/platforms/pseries/ras.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
>>> index f8b390a9d9fb..9d4ef65da7f3 100644
>>> --- a/arch/powerpc/platforms/pseries/ras.c
>>> +++ b/arch/powerpc/platforms/pseries/ras.c
>>> @@ -699,7 +699,7 @@ static int mce_handle_err_virtmode(struct pt_regs *regs,
>>> mce_err.error_type = MCE_ERROR_TYPE_DCACHE;
>>> break;
>>> case MC_ERROR_TYPE_I_CACHE:
>>> - mce_err.error_type = MCE_ERROR_TYPE_DCACHE;
>>> + mce_err.error_type = MCE_ERROR_TYPE_ICACHE;
>>> break;
>>> case MC_ERROR_TYPE_UNKNOWN:
>>> default:
>>> --
>>> 2.26.2
^ permalink raw reply
* Re: [PATCH 2/2] hotplug-cpu.c: set UNISOLATE on dlpar_cpu_remove() failure
From: Michael Ellerman @ 2021-04-19 12:48 UTC (permalink / raw)
To: Daniel Henrique Barboza, linuxppc-dev; +Cc: Daniel Henrique Barboza, david
In-Reply-To: <20210416210216.380291-3-danielhb413@gmail.com>
Daniel Henrique Barboza <danielhb413@gmail.com> writes:
> The RTAS set-indicator call, when attempting to UNISOLATE a DRC that is
> already UNISOLATED or CONFIGURED, returns RTAS_OK and does nothing else
> for both QEMU and phyp. This gives us an opportunity to use this
> behavior to signal the hypervisor layer when an error during device
> removal happens, allowing it to do a proper error handling, while not
> breaking QEMU/phyp implementations that don't have this support.
>
> This patch introduces this idea by unisolating all CPU DRCs that failed
> to be removed by dlpar_cpu_remove_by_index(), when handling the
> PSERIES_HP_ELOG_ID_DRC_INDEX event. This is being done for this event
> only because its the only CPU removal event QEMU uses, and there's no
> need at this moment to add this mechanism for phyp only code.
Have you also confirmed that phyp is not bothered by it? ie. everything
seems to continue working when you trigger this path on phyp.
cheers
> diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
> index 12cbffd3c2e3..ed66895c2f51 100644
> --- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
> +++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
> @@ -802,8 +802,15 @@ int dlpar_cpu(struct pseries_hp_errorlog *hp_elog)
> case PSERIES_HP_ELOG_ACTION_REMOVE:
> if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_COUNT)
> rc = dlpar_cpu_remove_by_count(count);
> - else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX)
> + else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX) {
> rc = dlpar_cpu_remove_by_index(drc_index);
> + /* Setting the isolation state of an UNISOLATED/CONFIGURED
> + * device to UNISOLATE is a no-op, but the hypervison can
> + * use it as a hint that the cpu removal failed.
> + */
> + if (rc)
> + dlpar_unisolate_drc(drc_index);
> + }
> else
> rc = -EINVAL;
> break;
> --
> 2.30.2
^ permalink raw reply
* Re: [RFC v1 PATCH 3/3] driver: update all the code that use soc_device_match
From: Arnd Bergmann @ 2021-04-19 12:16 UTC (permalink / raw)
To: Dominique MARTINET
Cc: Ulf Hansson, aymen.sghaier, Geert Uytterhoeven, Rafael Wysocki,
David Airlie, Michael Turquette, dri-devel,
Linux Kernel Mailing List, Andrzej Hajda, Networking, linux-phy,
peter.ujfalusi, linux-clk, Linux-Renesas, Wim Van Sebroeck,
Herbert Xu, Horia Geantă, Kevin Hilman, Joerg Roedel,
Neil Armstrong, linux-staging, open list:IOMMU DRIVERS, Kishon,
Tony Lindgren, linux-omap, Geert Uytterhoeven, Jakub Kicinski,
Linus Walleij, Guenter Roeck, Linux Media Mailing List,
LINUXWATCHDOG, Will Deacon, Linux PM list, linuxppc-dev,
Eduardo Valentin, open list:GPIO SUBSYSTEM,
moderated list:ARM/Mediatek SoC..., Santosh Shilimkar,
Matthias Brugger, open list:ARM/Amlogic Meson SoC support,
Mauro Carvalho Chehab, Linux ARM, Alice Guo (OSS), Felipe Balbi,
tomba, Stephen Boyd, gregkh, Alan Stern, USB list, linux-mmc,
Adrian Hunter, Robert Foss, Leo Li, Tony Prisk, Vinod Koul,
open list:HARDWARE RANDOM NUMBER GENERATOR CORE, Daniel Vetter,
Keerthy, dmaengine, Roy Pledge, jyri.sarha, David Miller
In-Reply-To: <YH1OeFy+SepIYYG0@atmark-techno.com>
On Mon, Apr 19, 2021 at 11:33 AM Dominique MARTINET
<dominique.martinet@atmark-techno.com> wrote:
> Geert Uytterhoeven wrote on Mon, Apr 19, 2021 at 11:03:24AM +0200:
>
> > soc_device_match() should only be used as a last resort, to identify
> > systems that cannot be identified otherwise. Typically this is used for
> > quirks, which should only be enabled on a very specific subset of
> > systems. IMHO such systems should make sure soc_device_match()
> > is available early, by registering their SoC device early.
>
> I definitely agree there, my suggestion to defer was only because I know
> of no other way to influence the ordering of drivers loading reliably
> and gave up on soc being init'd early.
In some cases, you can use the device_link infrastructure to deal
with dependencies between devices. Not sure if this would help
in your case, but have a look at device_link_add() etc in drivers/base/core.c
> In this particular case the problem is that since 7d981405d0fd ("soc:
> imx8m: change to use platform driver") the soc probe tries to use the
> nvmem driver for ocotp fuses for imx8m devices, which isn't ready yet.
> So soc loading gets pushed back to the end of the list because it gets
> defered and other drivers relying on soc_device_match get confused
> because they wrongly think a device doesn't match a quirk when it
> actually does.
>
> If there is a way to ensure the nvmem driver gets loaded before the soc,
> that would also solve the problem nicely, and avoid the need to mess
> with all the ~50 drivers which use it.
>
> Is there a way to control in what order drivers get loaded? Something in
> the dtb perhaps?
For built-in drivers, load order depends on the initcall level and
link order (how things are lined listed in the Makefile hierarchy).
For loadable modules, this is up to user space in the end.
Which of the drivers in this scenario are loadable modules?
Arnd
^ permalink raw reply
* Re: [PATCH 2/2] hotplug-cpu.c: set UNISOLATE on dlpar_cpu_remove() failure
From: Daniel Henrique Barboza @ 2021-04-19 13:13 UTC (permalink / raw)
To: Michael Ellerman, linuxppc-dev; +Cc: david
In-Reply-To: <87v98icuek.fsf@mpe.ellerman.id.au>
On 4/19/21 9:48 AM, Michael Ellerman wrote:
> Daniel Henrique Barboza <danielhb413@gmail.com> writes:
>> The RTAS set-indicator call, when attempting to UNISOLATE a DRC that is
>> already UNISOLATED or CONFIGURED, returns RTAS_OK and does nothing else
>> for both QEMU and phyp. This gives us an opportunity to use this
>> behavior to signal the hypervisor layer when an error during device
>> removal happens, allowing it to do a proper error handling, while not
>> breaking QEMU/phyp implementations that don't have this support.
>>
>> This patch introduces this idea by unisolating all CPU DRCs that failed
>> to be removed by dlpar_cpu_remove_by_index(), when handling the
>> PSERIES_HP_ELOG_ID_DRC_INDEX event. This is being done for this event
>> only because its the only CPU removal event QEMU uses, and there's no
>> need at this moment to add this mechanism for phyp only code.
>
> Have you also confirmed that phyp is not bothered by it? ie. everything
> seems to continue working when you trigger this path on phyp.
Yes. Daniel Bueso (dbuesom@us.ibm.com) from the partition firmware team
helped me with that. We confirmed that phyp returns RTAS_OK under these
conditions (Unisolating an unisolated/configured DRC).
Thanks,
DHB
>
> cheers
>
>> diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
>> index 12cbffd3c2e3..ed66895c2f51 100644
>> --- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
>> +++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
>> @@ -802,8 +802,15 @@ int dlpar_cpu(struct pseries_hp_errorlog *hp_elog)
>> case PSERIES_HP_ELOG_ACTION_REMOVE:
>> if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_COUNT)
>> rc = dlpar_cpu_remove_by_count(count);
>> - else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX)
>> + else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX) {
>> rc = dlpar_cpu_remove_by_index(drc_index);
>> + /* Setting the isolation state of an UNISOLATED/CONFIGURED
>> + * device to UNISOLATE is a no-op, but the hypervison can
>> + * use it as a hint that the cpu removal failed.
>> + */
>> + if (rc)
>> + dlpar_unisolate_drc(drc_index);
>> + }
>> else
>> rc = -EINVAL;
>> break;
>> --
>> 2.30.2
^ permalink raw reply
* Re: [PATCH v1 3/5] mm: ptdump: Provide page size to notepage()
From: Christophe Leroy @ 2021-04-19 13:14 UTC (permalink / raw)
To: Steven Price, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman, akpm
Cc: linux-arch, linux-s390, x86, linux-kernel, linux-mm, linux-riscv,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <1102cda1-b00f-b6ef-6bf3-22068cc11510@arm.com>
Le 16/04/2021 à 12:51, Steven Price a écrit :
> On 16/04/2021 11:38, Christophe Leroy wrote:
>>
>>
>> Le 16/04/2021 à 11:28, Steven Price a écrit :
>>> On 15/04/2021 18:18, Christophe Leroy wrote:
>>>
>>> To be honest I don't fully understand why powerpc requires the page_size - it appears to be using
>>> it purely to find "holes" in the calls to note_page(), but I haven't worked out why such holes
>>> would occur.
>>
>> I was indeed introduced for KASAN. We have a first commit
>> https://github.com/torvalds/linux/commit/cabe8138 which uses page size to detect whether it is a
>> KASAN like stuff.
>>
>> Then came https://github.com/torvalds/linux/commit/b00ff6d8c as a fix. I can't remember what the
>> problem was exactly, something around the use of hugepages for kernel memory, came as part of the
>> series
>> https://patchwork.ozlabs.org/project/linuxppc-dev/cover/cover.1589866984.git.christophe.leroy@csgroup.eu/
>
>
> Ah, that's useful context. So it looks like powerpc took a different route to reducing the KASAN
> output to x86.
>
> Given the generic ptdump code has handling for KASAN already it should be possible to drop that from
> the powerpc arch code, which I think means we don't actually need to provide page size to
> notepage(). Hopefully that means more code to delete ;)
>
Looking at how the generic ptdump code handles KASAN, I'm a bit sceptic.
IIUC, it is checking that kasan_early_shadow_pte is in the same page as the pgtable referred by the
PMD entry. But what happens if that PMD entry is referring another pgtable which is inside the same
page as kasan_early_shadow_pte ?
Shouldn't the test be
if (pmd_page_vaddr(val) == lm_alias(kasan_early_shadow_pte))
return note_kasan_page_table(walk, addr);
Christophe
^ permalink raw reply
* Re: PPC_FPU, ALTIVEC: enable_kernel_fp, put_vr, get_vr
From: Michael Ellerman @ 2021-04-19 13:16 UTC (permalink / raw)
To: Randy Dunlap, Segher Boessenkool, Christophe Leroy; +Cc: PowerPC, LKML
In-Reply-To: <bf119bfe-7db1-e7f3-d837-f910635eeebb@infradead.org>
Randy Dunlap <rdunlap@infradead.org> writes:
> On 4/18/21 10:46 AM, Segher Boessenkool wrote:
>> On Sun, Apr 18, 2021 at 06:24:29PM +0200, Christophe Leroy wrote:
>>> Le 17/04/2021 à 22:17, Randy Dunlap a écrit :
>>>> Should the code + Kconfigs/Makefiles handle that kind of
>>>> kernel config or should ALTIVEC always mean PPC_FPU as well?
>>>
>>> As far as I understand, Altivec is completely independant of FPU in Theory.
>>
>> And, as far as the hardware is concerned, in practice as well.
>>
>>> So it should be possible to use Altivec without using FPU.
>>
>> Yup.
>>
>>> However, until recently, it was not possible to de-activate FPU support on
>>> book3s/32. I made it possible in order to reduce unneccessary processing on
>>> processors like the 832x that has no FPU.
>>
>> The processor has to implement FP to be compliant to any version of
>> PowerPC, as far as I know? So that is all done by emulation, including
>> all the registers? Wow painful.
>>
>>> As far as I can see in cputable.h/.c, 832x is the only book3s/32 without
>>> FPU, and it doesn't have ALTIVEC either.
>>
>> 602 doesn't have double-precision hardware, also no 64-bit FP registers.
>> But that CPU was never any widely used :-)
>>
>>> So we can in the future ensure that Altivec can be used without FPU
>>> support, but for the time being I think it is OK to force selection of FPU
>>> when selecting ALTIVEC in order to avoid build failures.
>>
>> It is useful to allow MSR[VEC,FP]=1,0 but yeah there are no CPUs that
>> have VMX (aka AltiVec) but that do not have FP. I don't see how making
>> that artificial dependency buys anything, but maybe it does?
>>
>>>> I have patches to fix the build errors with the config as
>>>> reported but I don't know if that's the right thing to do...
>>
>> Neither do we, we cannot see those patches :-)
>
> Sure. I'll post them later today.
> They keep FPU and ALTIVEC as independent (build) features.
Those patches look OK.
But I don't think it makes sense to support that configuration, FPU=n
ALTVEC=y. No one is ever going to make a CPU like that. We have enough
testing surface due to configuration options, without adding artificial
combinations that no one is ever going to use.
IMHO :)
So I'd rather we just make ALTIVEC depend on FPU.
cheers
^ permalink raw reply
* Re: [PATCH 2/2] powerpc: add ALTIVEC support to lib/ when PPC_FPU not set
From: Segher Boessenkool @ 2021-04-19 13:32 UTC (permalink / raw)
To: Randy Dunlap; +Cc: linuxppc-dev, linux-kernel, kernel test robot
In-Reply-To: <20210418201726.32130-2-rdunlap@infradead.org>
Hi!
On Sun, Apr 18, 2021 at 01:17:26PM -0700, Randy Dunlap wrote:
> Add ldstfp.o to the Makefile for CONFIG_ALTIVEC and add
> externs for get_vr() and put_vr() in lib/sstep.c to fix the
> build errors.
> obj-$(CONFIG_PPC_FPU) += ldstfp.o
> +obj-$(CONFIG_ALTIVEC) += ldstfp.o
It is probably a good idea to split ldstfp.S into two, one for each of
the two configuration options?
Segher
^ permalink raw reply
* Re: [PATCH 2/2] powerpc: add ALTIVEC support to lib/ when PPC_FPU not set
From: Christophe Leroy @ 2021-04-19 13:38 UTC (permalink / raw)
To: Segher Boessenkool, Randy Dunlap
Cc: linuxppc-dev, linux-kernel, kernel test robot
In-Reply-To: <20210419133209.GR26583@gate.crashing.org>
Le 19/04/2021 à 15:32, Segher Boessenkool a écrit :
> Hi!
>
> On Sun, Apr 18, 2021 at 01:17:26PM -0700, Randy Dunlap wrote:
>> Add ldstfp.o to the Makefile for CONFIG_ALTIVEC and add
>> externs for get_vr() and put_vr() in lib/sstep.c to fix the
>> build errors.
>
>> obj-$(CONFIG_PPC_FPU) += ldstfp.o
>> +obj-$(CONFIG_ALTIVEC) += ldstfp.o
>
> It is probably a good idea to split ldstfp.S into two, one for each of
> the two configuration options?
>
Or we can build it all the time and #ifdef the FPU part.
Because it contains FPU, ALTIVEC and VSX stuff.
Christophe
^ permalink raw reply
* Re: [PATCH v1 3/5] mm: ptdump: Provide page size to notepage()
From: Steven Price @ 2021-04-19 14:00 UTC (permalink / raw)
To: Christophe Leroy, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman, akpm
Cc: linux-arch, linux-s390, x86, linux-kernel, linux-mm, linux-riscv,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <627ee414-2f78-94e3-b77b-1013f52e77e3@csgroup.eu>
On 19/04/2021 14:14, Christophe Leroy wrote:
>
>
> Le 16/04/2021 à 12:51, Steven Price a écrit :
>> On 16/04/2021 11:38, Christophe Leroy wrote:
>>>
>>>
>>> Le 16/04/2021 à 11:28, Steven Price a écrit :
>>>> On 15/04/2021 18:18, Christophe Leroy wrote:
>>>>
>>>> To be honest I don't fully understand why powerpc requires the
>>>> page_size - it appears to be using it purely to find "holes" in the
>>>> calls to note_page(), but I haven't worked out why such holes would
>>>> occur.
>>>
>>> I was indeed introduced for KASAN. We have a first commit
>>> https://github.com/torvalds/linux/commit/cabe8138 which uses page
>>> size to detect whether it is a KASAN like stuff.
>>>
>>> Then came https://github.com/torvalds/linux/commit/b00ff6d8c as a
>>> fix. I can't remember what the problem was exactly, something around
>>> the use of hugepages for kernel memory, came as part of the series
>>> https://patchwork.ozlabs.org/project/linuxppc-dev/cover/cover.1589866984.git.christophe.leroy@csgroup.eu/
>>
>>
>>
>> Ah, that's useful context. So it looks like powerpc took a different
>> route to reducing the KASAN output to x86.
>>
>> Given the generic ptdump code has handling for KASAN already it should
>> be possible to drop that from the powerpc arch code, which I think
>> means we don't actually need to provide page size to notepage().
>> Hopefully that means more code to delete ;)
>>
>
> Looking at how the generic ptdump code handles KASAN, I'm a bit sceptic.
>
> IIUC, it is checking that kasan_early_shadow_pte is in the same page as
> the pgtable referred by the PMD entry. But what happens if that PMD
> entry is referring another pgtable which is inside the same page as
> kasan_early_shadow_pte ?
>
> Shouldn't the test be
>
> if (pmd_page_vaddr(val) == lm_alias(kasan_early_shadow_pte))
> return note_kasan_page_table(walk, addr);
Now I come to look at this code again, I think you're right. On arm64
this doesn't cause a problem - page tables are page sized and page
aligned, so there couldn't be any non-KASAN pgtables sharing the page.
Obviously that's not necessarily true of other architectures.
Feel free to add a patch to your series ;)
Steve
^ permalink raw reply
* Re: [PATCH 2/2] powerpc: add ALTIVEC support to lib/ when PPC_FPU not set
From: Segher Boessenkool @ 2021-04-19 13:57 UTC (permalink / raw)
To: Christophe Leroy
Cc: Randy Dunlap, linuxppc-dev, linux-kernel, kernel test robot
In-Reply-To: <4f5aea37-f638-3fde-0680-ec456ad91141@csgroup.eu>
On Mon, Apr 19, 2021 at 03:38:02PM +0200, Christophe Leroy wrote:
> Le 19/04/2021 à 15:32, Segher Boessenkool a écrit :
> >On Sun, Apr 18, 2021 at 01:17:26PM -0700, Randy Dunlap wrote:
> >>Add ldstfp.o to the Makefile for CONFIG_ALTIVEC and add
> >>externs for get_vr() and put_vr() in lib/sstep.c to fix the
> >>build errors.
> >
> >> obj-$(CONFIG_PPC_FPU) += ldstfp.o
> >>+obj-$(CONFIG_ALTIVEC) += ldstfp.o
> >
> >It is probably a good idea to split ldstfp.S into two, one for each of
> >the two configuration options?
> >
>
> Or we can build it all the time and #ifdef the FPU part.
>
> Because it contains FPU, ALTIVEC and VSX stuff.
So it becomes an empty object file if none of the options are selected?
Good idea :-)
Segher
^ permalink raw reply
* Re: [PATCH v2 1/4] mm: pagewalk: Fix walk for hugepage tables
From: Steven Price @ 2021-04-19 14:07 UTC (permalink / raw)
To: Christophe Leroy, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman, akpm, dja
Cc: linux-arch, linuxppc-dev, Oliver O'Halloran, linux-kernel,
linux-mm
In-Reply-To: <db6981c69f96a8c9c6dcf688b7f485e15993ddef.1618828806.git.christophe.leroy@csgroup.eu>
On 19/04/2021 11:47, Christophe Leroy wrote:
> Pagewalk ignores hugepd entries and walk down the tables
> as if it was traditionnal entries, leading to crazy result.
>
> Add walk_hugepd_range() and use it to walk hugepage tables.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Looks correct to me, sadly I don't have a suitable system to test it.
Reviewed-by: Steven Price <steven.price@arm.com>
> ---
> v2:
> - Add a guard for NULL ops->pte_entry
> - Take mm->page_table_lock when walking hugepage table, as suggested by follow_huge_pd()
> ---
> mm/pagewalk.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 53 insertions(+), 5 deletions(-)
>
> diff --git a/mm/pagewalk.c b/mm/pagewalk.c
> index e81640d9f177..9b3db11a4d1d 100644
> --- a/mm/pagewalk.c
> +++ b/mm/pagewalk.c
> @@ -58,6 +58,45 @@ static int walk_pte_range(pmd_t *pmd, unsigned long addr, unsigned long end,
> return err;
> }
>
> +#ifdef CONFIG_ARCH_HAS_HUGEPD
> +static int walk_hugepd_range(hugepd_t *phpd, unsigned long addr,
> + unsigned long end, struct mm_walk *walk, int pdshift)
> +{
> + int err = 0;
> + const struct mm_walk_ops *ops = walk->ops;
> + int shift = hugepd_shift(*phpd);
> + int page_size = 1 << shift;
> +
> + if (!ops->pte_entry)
> + return 0;
> +
> + if (addr & (page_size - 1))
> + return 0;
> +
> + for (;;) {
> + pte_t *pte;
> +
> + spin_lock(&walk->mm->page_table_lock);
> + pte = hugepte_offset(*phpd, addr, pdshift);
> + err = ops->pte_entry(pte, addr, addr + page_size, walk);
> + spin_unlock(&walk->mm->page_table_lock);
> +
> + if (err)
> + break;
> + if (addr >= end - page_size)
> + break;
> + addr += page_size;
> + }
> + return err;
> +}
> +#else
> +static int walk_hugepd_range(hugepd_t *phpd, unsigned long addr,
> + unsigned long end, struct mm_walk *walk, int pdshift)
> +{
> + return 0;
> +}
> +#endif
> +
> static int walk_pmd_range(pud_t *pud, unsigned long addr, unsigned long end,
> struct mm_walk *walk)
> {
> @@ -108,7 +147,10 @@ static int walk_pmd_range(pud_t *pud, unsigned long addr, unsigned long end,
> goto again;
> }
>
> - err = walk_pte_range(pmd, addr, next, walk);
> + if (is_hugepd(__hugepd(pmd_val(*pmd))))
> + err = walk_hugepd_range((hugepd_t *)pmd, addr, next, walk, PMD_SHIFT);
> + else
> + err = walk_pte_range(pmd, addr, next, walk);
> if (err)
> break;
> } while (pmd++, addr = next, addr != end);
> @@ -157,7 +199,10 @@ static int walk_pud_range(p4d_t *p4d, unsigned long addr, unsigned long end,
> if (pud_none(*pud))
> goto again;
>
> - err = walk_pmd_range(pud, addr, next, walk);
> + if (is_hugepd(__hugepd(pud_val(*pud))))
> + err = walk_hugepd_range((hugepd_t *)pud, addr, next, walk, PUD_SHIFT);
> + else
> + err = walk_pmd_range(pud, addr, next, walk);
> if (err)
> break;
> } while (pud++, addr = next, addr != end);
> @@ -189,7 +234,9 @@ static int walk_p4d_range(pgd_t *pgd, unsigned long addr, unsigned long end,
> if (err)
> break;
> }
> - if (ops->pud_entry || ops->pmd_entry || ops->pte_entry)
> + if (is_hugepd(__hugepd(p4d_val(*p4d))))
> + err = walk_hugepd_range((hugepd_t *)p4d, addr, next, walk, P4D_SHIFT);
> + else if (ops->pud_entry || ops->pmd_entry || ops->pte_entry)
> err = walk_pud_range(p4d, addr, next, walk);
> if (err)
> break;
> @@ -224,8 +271,9 @@ static int walk_pgd_range(unsigned long addr, unsigned long end,
> if (err)
> break;
> }
> - if (ops->p4d_entry || ops->pud_entry || ops->pmd_entry ||
> - ops->pte_entry)
> + if (is_hugepd(__hugepd(pgd_val(*pgd))))
> + err = walk_hugepd_range((hugepd_t *)pgd, addr, next, walk, PGDIR_SHIFT);
> + else if (ops->p4d_entry || ops->pud_entry || ops->pmd_entry || ops->pte_entry)
> err = walk_p4d_range(pgd, addr, next, walk);
> if (err)
> break;
>
^ permalink raw reply
* Re: [PATCH 1/1] of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses
From: Rob Herring @ 2021-04-19 15:44 UTC (permalink / raw)
To: Leonardo Bras
Cc: devicetree, Alexey Kardashevskiy, Frank Rowand,
linux-kernel@vger.kernel.org, PCI, linuxppc-dev
In-Reply-To: <7b089cd48b90f2445c7cb80da1ce8638607c46fc.camel@gmail.com>
On Fri, Apr 16, 2021 at 3:58 PM Leonardo Bras <leobras.c@gmail.com> wrote:
>
> Hello Rob, thanks for this feedback!
>
> On Thu, 2021-04-15 at 13:59 -0500, Rob Herring wrote:
> > +PPC and PCI lists
> >
> > On Thu, Apr 15, 2021 at 1:01 PM Leonardo Bras <leobras.c@gmail.com> wrote:
> > >
> > > Many other resource flag parsers already add this flag when the input
> > > has bits 24 & 25 set, so update this one to do the same.
> >
> > Many others? Looks like sparc and powerpc to me.
> >
>
> s390 also does that, but it look like it comes from a device-tree.
I'm only looking at DT based platforms, and s390 doesn't use DT.
> > Those would be the
> > ones I worry about breaking. Sparc doesn't use of/address.c so it's
> > fine. Powerpc version of the flags code was only fixed in 2019, so I
> > don't think powerpc will care either.
>
> In powerpc I reach this function with this stack, while configuring a
> virtio-net device for a qemu/KVM pseries guest:
>
> pci_process_bridge_OF_ranges+0xac/0x2d4
> pSeries_discover_phbs+0xc4/0x158
> discover_phbs+0x40/0x60
> do_one_initcall+0x60/0x2d0
> kernel_init_freeable+0x308/0x3a8
> kernel_init+0x2c/0x168
> ret_from_kernel_thread+0x5c/0x70
>
> For this, both MMIO32 and MMIO64 resources will have flags 0x200.
Oh good, powerpc has 2 possible flags parsing functions. So in the
above path, do we need to set PCI_BASE_ADDRESS_MEM_TYPE_64?
Does pci_parse_of_flags() get called in your case?
> > I noticed both sparc and powerpc set PCI_BASE_ADDRESS_MEM_TYPE_64 in
> > the flags. AFAICT, that's not set anywhere outside of arch code. So
> > never for riscv, arm and arm64 at least. That leads me to
> > pci_std_update_resource() which is where the PCI code sets BARs and
> > just copies the flags in PCI_BASE_ADDRESS_MEM_MASK ignoring
> > IORESOURCE_* flags. So it seems like 64-bit is still not handled and
> > neither is prefetch.
> >
>
> I am not sure if you mean here:
> a) it's ok to add IORESOURCE_MEM_64 here, because it does not affect
> anything else, or
> b) it should be using PCI_BASE_ADDRESS_MEM_TYPE_64
> (or IORESOURCE_MEM_64 | PCI_BASE_ADDRESS_MEM_TYPE_64) instead, since
> it's how it's added in powerpc/sparc, and else there is no point.
I'm wondering if a) is incomplete and PCI_BASE_ADDRESS_MEM_TYPE_64
also needs to be set. The question is ultimately are BARs getting set
correctly for 64-bit? It looks to me like they aren't.
Rob
^ permalink raw reply
* [PATCH 1/3] powerpc/8xx: Enhance readability of trap types
From: Christophe Leroy @ 2021-04-19 15:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, sxwjean
Cc: linuxppc-dev, linux-kernel
This patch makes use of trap types in head_8xx.S
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/include/asm/interrupt.h | 29 ++++++++++++----
arch/powerpc/kernel/head_8xx.S | 49 ++++++++++++++--------------
2 files changed, 47 insertions(+), 31 deletions(-)
diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h
index ed2c4042c3d1..cf2c5c3ae716 100644
--- a/arch/powerpc/include/asm/interrupt.h
+++ b/arch/powerpc/include/asm/interrupt.h
@@ -2,13 +2,6 @@
#ifndef _ASM_POWERPC_INTERRUPT_H
#define _ASM_POWERPC_INTERRUPT_H
-#include <linux/context_tracking.h>
-#include <linux/hardirq.h>
-#include <asm/cputime.h>
-#include <asm/ftrace.h>
-#include <asm/kprobes.h>
-#include <asm/runlatch.h>
-
/* BookE/4xx */
#define INTERRUPT_CRITICAL_INPUT 0x100
@@ -39,9 +32,11 @@
/* BookE/BookS/4xx/8xx */
#define INTERRUPT_DATA_STORAGE 0x300
#define INTERRUPT_INST_STORAGE 0x400
+#define INTERRUPT_EXTERNAL 0x500
#define INTERRUPT_ALIGNMENT 0x600
#define INTERRUPT_PROGRAM 0x700
#define INTERRUPT_SYSCALL 0xc00
+#define INTERRUPT_TRACE 0xd00
/* BookE/BookS/44x */
#define INTERRUPT_FP_UNAVAIL 0x800
@@ -53,6 +48,24 @@
#define INTERRUPT_PERFMON 0x0
#endif
+/* 8xx */
+#define INTERRUPT_SOFT_EMU_8xx 0x1000
+#define INTERRUPT_INST_TLB_MISS_8xx 0x1100
+#define INTERRUPT_DATA_TLB_MISS_8xx 0x1200
+#define INTERRUPT_INST_TLB_ERROR_8xx 0x1300
+#define INTERRUPT_DATA_TLB_ERROR_8xx 0x1400
+#define INTERRUPT_DATA_BREAKPOINT_8xx 0x1c00
+#define INTERRUPT_INST_BREAKPOINT_8xx 0x1d00
+
+#ifndef __ASSEMBLY__
+
+#include <linux/context_tracking.h>
+#include <linux/hardirq.h>
+#include <asm/cputime.h>
+#include <asm/ftrace.h>
+#include <asm/kprobes.h>
+#include <asm/runlatch.h>
+
static inline void nap_adjust_return(struct pt_regs *regs)
{
#ifdef CONFIG_PPC_970_NAP
@@ -514,4 +527,6 @@ static inline void interrupt_cond_local_irq_enable(struct pt_regs *regs)
local_irq_enable();
}
+#endif /* __ASSEMBLY__ */
+
#endif /* _ASM_POWERPC_INTERRUPT_H */
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index e3b066703eab..7d445e4342c0 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -29,6 +29,7 @@
#include <asm/ptrace.h>
#include <asm/export.h>
#include <asm/code-patching-asm.h>
+#include <asm/interrupt.h>
/*
* Value for the bits that have fixed value in RPN entries.
@@ -118,49 +119,49 @@ instruction_counter:
#endif
/* System reset */
- EXCEPTION(0x100, Reset, system_reset_exception)
+ EXCEPTION(INTERRUPT_SYSTEM_RESET, Reset, system_reset_exception)
/* Machine check */
- START_EXCEPTION(0x200, MachineCheck)
- EXCEPTION_PROLOG 0x200 MachineCheck handle_dar_dsisr=1
+ START_EXCEPTION(INTERRUPT_MACHINE_CHECK, MachineCheck)
+ EXCEPTION_PROLOG INTERRUPT_MACHINE_CHECK MachineCheck handle_dar_dsisr=1
prepare_transfer_to_handler
bl machine_check_exception
b interrupt_return
/* External interrupt */
- EXCEPTION(0x500, HardwareInterrupt, do_IRQ)
+ EXCEPTION(INTERRUPT_EXTERNAL, HardwareInterrupt, do_IRQ)
/* Alignment exception */
- START_EXCEPTION(0x600, Alignment)
- EXCEPTION_PROLOG 0x600 Alignment handle_dar_dsisr=1
+ START_EXCEPTION(INTERRUPT_ALIGNMENT, Alignment)
+ EXCEPTION_PROLOG INTERRUPT_ALIGNMENT Alignment handle_dar_dsisr=1
prepare_transfer_to_handler
bl alignment_exception
REST_NVGPRS(r1)
b interrupt_return
/* Program check exception */
- START_EXCEPTION(0x700, ProgramCheck)
- EXCEPTION_PROLOG 0x700 ProgramCheck
+ START_EXCEPTION(INTERRUPT_PROGRAM, ProgramCheck)
+ EXCEPTION_PROLOG INTERRUPT_PROGRAM ProgramCheck
prepare_transfer_to_handler
bl program_check_exception
REST_NVGPRS(r1)
b interrupt_return
/* Decrementer */
- EXCEPTION(0x900, Decrementer, timer_interrupt)
+ EXCEPTION(INTERRUPT_DECREMENTER, Decrementer, timer_interrupt)
/* System call */
- START_EXCEPTION(0xc00, SystemCall)
- SYSCALL_ENTRY 0xc00
+ START_EXCEPTION(INTERRUPT_SYSCALL, SystemCall)
+ SYSCALL_ENTRY INTERRUPT_SYSCALL
/* Single step - not used on 601 */
- EXCEPTION(0xd00, SingleStep, single_step_exception)
+ EXCEPTION(INTERRUPT_TRACE, SingleStep, single_step_exception)
/* On the MPC8xx, this is a software emulation interrupt. It occurs
* for all unimplemented and illegal instructions.
*/
- START_EXCEPTION(0x1000, SoftEmu)
- EXCEPTION_PROLOG 0x1000 SoftEmu
+ START_EXCEPTION(INTERRUPT_SOFT_EMU_8xx, SoftEmu)
+ EXCEPTION_PROLOG INTERRUPT_SOFT_EMU_8xx SoftEmu
prepare_transfer_to_handler
bl emulation_assist_interrupt
REST_NVGPRS(r1)
@@ -187,7 +188,7 @@ instruction_counter:
#define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp)
#endif
- START_EXCEPTION(0x1100, InstructionTLBMiss)
+ START_EXCEPTION(INTERRUPT_INST_TLB_MISS_8xx, InstructionTLBMiss)
mtspr SPRN_SPRG_SCRATCH2, r10
mtspr SPRN_M_TW, r11
@@ -243,7 +244,7 @@ instruction_counter:
rfi
#endif
- START_EXCEPTION(0x1200, DataStoreTLBMiss)
+ START_EXCEPTION(INTERRUPT_DATA_TLB_MISS_8xx, DataStoreTLBMiss)
mtspr SPRN_SPRG_SCRATCH2, r10
mtspr SPRN_M_TW, r11
mfcr r11
@@ -306,9 +307,9 @@ instruction_counter:
* to many reasons, such as executing guarded memory or illegal instruction
* addresses. There is nothing to do but handle a big time error fault.
*/
- START_EXCEPTION(0x1300, InstructionTLBError)
+ START_EXCEPTION(INTERRUPT_INST_TLB_ERROR_8xx, InstructionTLBError)
/* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
- EXCEPTION_PROLOG 0x400 InstructionTLBError
+ EXCEPTION_PROLOG INTERRUPT_INST_STORAGE InstructionTLBError
andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
andis. r10,r9,SRR1_ISI_NOPT@h
beq+ .Litlbie
@@ -324,7 +325,7 @@ instruction_counter:
* many reasons, including a dirty update to a pte. We bail out to
* a higher level function that can handle it.
*/
- START_EXCEPTION(0x1400, DataTLBError)
+ START_EXCEPTION(INTERRUPT_DATA_TLB_ERROR_8xx, DataTLBError)
EXCEPTION_PROLOG_0 handle_dar_dsisr=1
mfspr r11, SPRN_DAR
cmpwi cr1, r11, RPN_PATTERN
@@ -332,7 +333,7 @@ instruction_counter:
DARFixed:/* Return from dcbx instruction bug workaround */
EXCEPTION_PROLOG_1
/* 0x300 is DataAccess exception, needed by bad_page_fault() */
- EXCEPTION_PROLOG_2 0x300 DataTLBError handle_dar_dsisr=1
+ EXCEPTION_PROLOG_2 INTERRUPT_DATA_STORAGE DataTLBError handle_dar_dsisr=1
lwz r4, _DAR(r11)
lwz r5, _DSISR(r11)
andis. r10,r5,DSISR_NOHPTE@h
@@ -351,7 +352,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
* support of breakpoints and such. Someday I will get around to
* using them.
*/
- START_EXCEPTION(0x1c00, DataBreakpoint)
+ START_EXCEPTION(INTERRUPT_DATA_BREAKPOINT_8xx, DataBreakpoint)
EXCEPTION_PROLOG_0 handle_dar_dsisr=1
mfspr r11, SPRN_SRR0
cmplwi cr1, r11, (.Ldtlbie - PAGE_OFFSET)@l
@@ -364,7 +365,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
rfi
1: EXCEPTION_PROLOG_1
- EXCEPTION_PROLOG_2 0x1c00 DataBreakpoint handle_dar_dsisr=1
+ EXCEPTION_PROLOG_2 INTERRUPT_DATA_BREAKPOINT_8xx DataBreakpoint handle_dar_dsisr=1
mfspr r4,SPRN_BAR
stw r4,_DAR(r11)
prepare_transfer_to_handler
@@ -373,7 +374,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
b interrupt_return
#ifdef CONFIG_PERF_EVENTS
- START_EXCEPTION(0x1d00, InstructionBreakpoint)
+ START_EXCEPTION(INTERRUPT_INST_BREAKPOINT_8xx, InstructionBreakpoint)
mtspr SPRN_SPRG_SCRATCH0, r10
lwz r10, (instruction_counter - PAGE_OFFSET)@l(0)
addi r10, r10, -1
@@ -384,7 +385,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
mfspr r10, SPRN_SPRG_SCRATCH0
rfi
#else
- EXCEPTION(0x1d00, Trap_1d, unknown_exception)
+ EXCEPTION(INTERRUPT_INST_BREAKPOINT_8xx, Trap_1d, unknown_exception)
#endif
EXCEPTION(0x1e00, Trap_1e, unknown_exception)
EXCEPTION(0x1f00, Trap_1f, unknown_exception)
--
2.25.0
^ permalink raw reply related
* [PATCH 3/3] powerpc/irq: Enhance readability of trap types
From: Christophe Leroy @ 2021-04-19 15:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, sxwjean
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <e1147287bf6f2fb0693048fe8db0298c7870e419.1618847273.git.christophe.leroy@csgroup.eu>
This patch makes use of trap types in irq.c
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/include/asm/interrupt.h | 1 +
arch/powerpc/kernel/irq.c | 13 +++++--------
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h
index 8970990e3b08..44cde2e129b8 100644
--- a/arch/powerpc/include/asm/interrupt.h
+++ b/arch/powerpc/include/asm/interrupt.h
@@ -23,6 +23,7 @@
#define INTERRUPT_INST_SEGMENT 0x480
#define INTERRUPT_TRACE 0xd00
#define INTERRUPT_H_DATA_STORAGE 0xe00
+#define INTERRUPT_HMI 0xe60
#define INTERRUPT_H_FAC_UNAVAIL 0xf80
#ifdef CONFIG_PPC_BOOK3S
#define INTERRUPT_DOORBELL 0xa00
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 893d3f8d6f47..72cb45393ef2 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -142,7 +142,7 @@ void replay_soft_interrupts(void)
*/
if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (local_paca->irq_happened & PACA_IRQ_HMI)) {
local_paca->irq_happened &= ~PACA_IRQ_HMI;
- regs.trap = 0xe60;
+ regs.trap = INTERRUPT_HMI;
handle_hmi_exception(®s);
if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
hard_irq_disable();
@@ -150,7 +150,7 @@ void replay_soft_interrupts(void)
if (local_paca->irq_happened & PACA_IRQ_DEC) {
local_paca->irq_happened &= ~PACA_IRQ_DEC;
- regs.trap = 0x900;
+ regs.trap = INTERRUPT_DECREMENTER;
timer_interrupt(®s);
if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
hard_irq_disable();
@@ -158,7 +158,7 @@ void replay_soft_interrupts(void)
if (local_paca->irq_happened & PACA_IRQ_EE) {
local_paca->irq_happened &= ~PACA_IRQ_EE;
- regs.trap = 0x500;
+ regs.trap = INTERRUPT_EXTERNAL;
do_IRQ(®s);
if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
hard_irq_disable();
@@ -166,10 +166,7 @@ void replay_soft_interrupts(void)
if (IS_ENABLED(CONFIG_PPC_DOORBELL) && (local_paca->irq_happened & PACA_IRQ_DBELL)) {
local_paca->irq_happened &= ~PACA_IRQ_DBELL;
- if (IS_ENABLED(CONFIG_PPC_BOOK3E))
- regs.trap = 0x280;
- else
- regs.trap = 0xa00;
+ regs.trap = INTERRUPT_DOORBELL;
doorbell_exception(®s);
if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
hard_irq_disable();
@@ -178,7 +175,7 @@ void replay_soft_interrupts(void)
/* Book3E does not support soft-masking PMI interrupts */
if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (local_paca->irq_happened & PACA_IRQ_PMI)) {
local_paca->irq_happened &= ~PACA_IRQ_PMI;
- regs.trap = 0xf00;
+ regs.trap = INTERRUPT_PERFMON;
performance_monitor_exception(®s);
if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
hard_irq_disable();
--
2.25.0
^ permalink raw reply related
* [PATCH 2/3] powerpc/32s: Enhance readability of trap types
From: Christophe Leroy @ 2021-04-19 15:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, sxwjean
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <e1147287bf6f2fb0693048fe8db0298c7870e419.1618847273.git.christophe.leroy@csgroup.eu>
This patch makes use of trap types in head_book3s_32.S
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/include/asm/interrupt.h | 6 ++++
arch/powerpc/kernel/head_book3s_32.S | 43 ++++++++++++++--------------
2 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h
index cf2c5c3ae716..8970990e3b08 100644
--- a/arch/powerpc/include/asm/interrupt.h
+++ b/arch/powerpc/include/asm/interrupt.h
@@ -27,6 +27,7 @@
#ifdef CONFIG_PPC_BOOK3S
#define INTERRUPT_DOORBELL 0xa00
#define INTERRUPT_PERFMON 0xf00
+#define INTERRUPT_ALTIVEC_UNAVAIL 0xf20
#endif
/* BookE/BookS/4xx/8xx */
@@ -57,6 +58,11 @@
#define INTERRUPT_DATA_BREAKPOINT_8xx 0x1c00
#define INTERRUPT_INST_BREAKPOINT_8xx 0x1d00
+/* 603 */
+#define INTERRUPT_INST_TLB_MISS_603 0x1000
+#define INTERRUPT_DATA_LOAD_TLB_MISS_603 0x1100
+#define INTERRUPT_DATA_STORE_TLB_MISS_603 0x1200
+
#ifndef __ASSEMBLY__
#include <linux/context_tracking.h>
diff --git a/arch/powerpc/kernel/head_book3s_32.S b/arch/powerpc/kernel/head_book3s_32.S
index 18f4ae163f34..065178f19a3d 100644
--- a/arch/powerpc/kernel/head_book3s_32.S
+++ b/arch/powerpc/kernel/head_book3s_32.S
@@ -31,6 +31,7 @@
#include <asm/kvm_book3s_asm.h>
#include <asm/export.h>
#include <asm/feature-fixups.h>
+#include <asm/interrupt.h>
#include "head_32.h"
@@ -239,7 +240,7 @@ __secondary_hold_acknowledge:
/* System reset */
/* core99 pmac starts the seconary here by changing the vector, and
putting it back to what it was (unknown_async_exception) when done. */
- EXCEPTION(0x100, Reset, unknown_async_exception)
+ EXCEPTION(INTERRUPT_SYSTEM_RESET, Reset, unknown_async_exception)
/* Machine check */
/*
@@ -255,7 +256,7 @@ __secondary_hold_acknowledge:
* pointer when we take an exception from supervisor mode.)
* -- paulus.
*/
- START_EXCEPTION(0x200, MachineCheck)
+ START_EXCEPTION(INTERRUPT_MACHINE_CHECK, MachineCheck)
EXCEPTION_PROLOG_0
#ifdef CONFIG_PPC_CHRP
mtspr SPRN_SPRG_SCRATCH2,r1
@@ -276,7 +277,7 @@ __secondary_hold_acknowledge:
b interrupt_return
/* Data access exception. */
- START_EXCEPTION(0x300, DataAccess)
+ START_EXCEPTION(INTERRUPT_DATA_STORAGE, DataAccess)
#ifdef CONFIG_PPC_BOOK3S_604
BEGIN_MMU_FTR_SECTION
mtspr SPRN_SPRG_SCRATCH2,r10
@@ -297,7 +298,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
#endif
1: EXCEPTION_PROLOG_0 handle_dar_dsisr=1
EXCEPTION_PROLOG_1
- EXCEPTION_PROLOG_2 0x300 DataAccess handle_dar_dsisr=1
+ EXCEPTION_PROLOG_2 INTERRUPT_DATA_STORAGE DataAccess handle_dar_dsisr=1
prepare_transfer_to_handler
lwz r5, _DSISR(r11)
andis. r0, r5, DSISR_DABRMATCH@h
@@ -310,7 +311,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
/* Instruction access exception. */
- START_EXCEPTION(0x400, InstructionAccess)
+ START_EXCEPTION(INTERRUPT_INST_STORAGE, InstructionAccess)
mtspr SPRN_SPRG_SCRATCH0,r10
mtspr SPRN_SPRG_SCRATCH1,r11
mfspr r10, SPRN_SPRG_THREAD
@@ -330,7 +331,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
andi. r11, r11, MSR_PR
EXCEPTION_PROLOG_1
- EXCEPTION_PROLOG_2 0x400 InstructionAccess
+ EXCEPTION_PROLOG_2 INTERRUPT_INST_STORAGE InstructionAccess
andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
stw r5, _DSISR(r11)
stw r12, _DAR(r11)
@@ -339,19 +340,19 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
b interrupt_return
/* External interrupt */
- EXCEPTION(0x500, HardwareInterrupt, do_IRQ)
+ EXCEPTION(INTERRUPT_EXTERNAL, HardwareInterrupt, do_IRQ)
/* Alignment exception */
- START_EXCEPTION(0x600, Alignment)
- EXCEPTION_PROLOG 0x600 Alignment handle_dar_dsisr=1
+ START_EXCEPTION(INTERRUPT_ALIGNMENT, Alignment)
+ EXCEPTION_PROLOG INTERRUPT_ALIGNMENT Alignment handle_dar_dsisr=1
prepare_transfer_to_handler
bl alignment_exception
REST_NVGPRS(r1)
b interrupt_return
/* Program check exception */
- START_EXCEPTION(0x700, ProgramCheck)
- EXCEPTION_PROLOG 0x700 ProgramCheck
+ START_EXCEPTION(INTERRUPT_PROGRAM, ProgramCheck)
+ EXCEPTION_PROLOG INTERRUPT_PROGRAM ProgramCheck
prepare_transfer_to_handler
bl program_check_exception
REST_NVGPRS(r1)
@@ -367,7 +368,7 @@ BEGIN_FTR_SECTION
*/
b ProgramCheck
END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
- EXCEPTION_PROLOG 0x800 FPUnavailable
+ EXCEPTION_PROLOG INTERRUPT_FP_UNAVAIL FPUnavailable
beq 1f
bl load_up_fpu /* if from user, just load it up */
b fast_exception_return
@@ -379,16 +380,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
#endif
/* Decrementer */
- EXCEPTION(0x900, Decrementer, timer_interrupt)
+ EXCEPTION(INTERRUPT_DECREMENTER, Decrementer, timer_interrupt)
EXCEPTION(0xa00, Trap_0a, unknown_exception)
EXCEPTION(0xb00, Trap_0b, unknown_exception)
/* System call */
- START_EXCEPTION(0xc00, SystemCall)
- SYSCALL_ENTRY 0xc00
+ START_EXCEPTION(INTERRUPT_SYSCALL, SystemCall)
+ SYSCALL_ENTRY INTERRUPT_SYSCALL
- EXCEPTION(0xd00, SingleStep, single_step_exception)
+ EXCEPTION(INTERRUPT_TRACE, SingleStep, single_step_exception)
EXCEPTION(0xe00, Trap_0e, unknown_exception)
/*
@@ -399,10 +400,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
* non-altivec kernel running on a machine with altivec just
* by executing an altivec instruction.
*/
- START_EXCEPTION(0xf00, PerformanceMonitorTrap)
+ START_EXCEPTION(INTERRUPT_PERFMON, PerformanceMonitorTrap)
b PerformanceMonitor
- START_EXCEPTION(0xf20, AltiVecUnavailableTrap)
+ START_EXCEPTION(INTERRUPT_ALTIVEC_UNAVAIL, AltiVecUnavailableTrap)
b AltiVecUnavailable
__HEAD
@@ -410,7 +411,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
* Handle TLB miss for instruction on 603/603e.
* Note: we get an alternate set of r0 - r3 to use automatically.
*/
- . = 0x1000
+ . = INTERRUPT_INST_TLB_MISS_603
InstructionTLBMiss:
/*
* r0: scratch
@@ -476,7 +477,7 @@ InstructionAddressInvalid:
/*
* Handle TLB miss for DATA Load operation on 603/603e
*/
- . = 0x1100
+ . = INTERRUPT_DATA_LOAD_TLB_MISS_603
DataLoadTLBMiss:
/*
* r0: scratch
@@ -554,7 +555,7 @@ DataAddressInvalid:
/*
* Handle TLB miss for DATA Store on 603/603e
*/
- . = 0x1200
+ . = INTERRUPT_DATA_STORE_TLB_MISS_603
DataStoreTLBMiss:
/*
* r0: scratch
--
2.25.0
^ permalink raw reply related
* Re: [PATCH v1 3/5] mm: ptdump: Provide page size to notepage()
From: Christophe Leroy @ 2021-04-19 16:41 UTC (permalink / raw)
To: Steven Price, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman, akpm
Cc: linux-arch, linux-s390, x86, linux-kernel, linux-mm, linux-riscv,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <4a76fbda-aa9d-867b-e2eb-a1951780aeec@arm.com>
Le 19/04/2021 à 16:00, Steven Price a écrit :
> On 19/04/2021 14:14, Christophe Leroy wrote:
>>
>>
>> Le 16/04/2021 à 12:51, Steven Price a écrit :
>>> On 16/04/2021 11:38, Christophe Leroy wrote:
>>>>
>>>>
>>>> Le 16/04/2021 à 11:28, Steven Price a écrit :
>>>>> On 15/04/2021 18:18, Christophe Leroy wrote:
>>>>>
>>>>> To be honest I don't fully understand why powerpc requires the page_size - it appears to be
>>>>> using it purely to find "holes" in the calls to note_page(), but I haven't worked out why such
>>>>> holes would occur.
>>>>
>>>> I was indeed introduced for KASAN. We have a first commit
>>>> https://github.com/torvalds/linux/commit/cabe8138 which uses page size to detect whether it is a
>>>> KASAN like stuff.
>>>>
>>>> Then came https://github.com/torvalds/linux/commit/b00ff6d8c as a fix. I can't remember what the
>>>> problem was exactly, something around the use of hugepages for kernel memory, came as part of
>>>> the series
>>>> https://patchwork.ozlabs.org/project/linuxppc-dev/cover/cover.1589866984.git.christophe.leroy@csgroup.eu/
>>>
>>>
>>>
>>>
>>> Ah, that's useful context. So it looks like powerpc took a different route to reducing the KASAN
>>> output to x86.
>>>
>>> Given the generic ptdump code has handling for KASAN already it should be possible to drop that
>>> from the powerpc arch code, which I think means we don't actually need to provide page size to
>>> notepage(). Hopefully that means more code to delete ;)
>>>
>>
>> Looking at how the generic ptdump code handles KASAN, I'm a bit sceptic.
>>
>> IIUC, it is checking that kasan_early_shadow_pte is in the same page as the pgtable referred by
>> the PMD entry. But what happens if that PMD entry is referring another pgtable which is inside the
>> same page as kasan_early_shadow_pte ?
>>
>> Shouldn't the test be
>>
>> if (pmd_page_vaddr(val) == lm_alias(kasan_early_shadow_pte))
>> return note_kasan_page_table(walk, addr);
>
> Now I come to look at this code again, I think you're right. On arm64 this doesn't cause a problem -
> page tables are page sized and page aligned, so there couldn't be any non-KASAN pgtables sharing the
> page. Obviously that's not necessarily true of other architectures.
>
> Feel free to add a patch to your series ;)
>
Ok.
I'll leave that outside of the series, it is not a show stopper because early shadow page
directories are all tagged __bss_page_aligned so we can't have two of them in the same page and it
is really unlikely that we'll have any other statically defined page directory in the same pages either.
And for the special case of powerpc 8xx which is the only one for which we have both KASAN and
HUGEPD at the time being, there are only two levels of page directories so no issue.
Christophe
^ permalink raw reply
* Re: [PATCH v2] perf vendor events: Initial json/events list for power10 platform
From: Arnaldo Carvalho de Melo @ 2021-04-19 16:57 UTC (permalink / raw)
To: Michael Ellerman
Cc: ravi.bangoria, atrajeev, Kajol Jain, linuxppc-dev, linux-kernel,
linux-perf-users, maddy, pc, jolsa
In-Reply-To: <871rb6e9ex.fsf@mpe.ellerman.id.au>
Em Mon, Apr 19, 2021 at 10:38:46PM +1000, Michael Ellerman escreveu:
> Kajol Jain <kjain@linux.ibm.com> writes:
> > Patch adds initial json/events for POWER10.
>
> Acked-by: Michael Ellerman <mpe@ellerman.id.au>
Thanks, applied.
- Arnaldo
> cheers
>
> > Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
> > Tested-by: Paul A. Clarke <pc@us.ibm.com>
> > Reviewed-by: Paul A. Clarke <pc@us.ibm.com>
> > ---
> > .../perf/pmu-events/arch/powerpc/mapfile.csv | 1 +
> > .../arch/powerpc/power10/cache.json | 47 +++
> > .../arch/powerpc/power10/floating_point.json | 7 +
> > .../arch/powerpc/power10/frontend.json | 217 +++++++++++++
> > .../arch/powerpc/power10/locks.json | 12 +
> > .../arch/powerpc/power10/marked.json | 147 +++++++++
> > .../arch/powerpc/power10/memory.json | 192 +++++++++++
> > .../arch/powerpc/power10/others.json | 297 ++++++++++++++++++
> > .../arch/powerpc/power10/pipeline.json | 297 ++++++++++++++++++
> > .../pmu-events/arch/powerpc/power10/pmc.json | 22 ++
> > .../arch/powerpc/power10/translation.json | 57 ++++
> > 11 files changed, 1296 insertions(+)
> > create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/cache.json
> > create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
> > create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/frontend.json
> > create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/locks.json
> > create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/marked.json
> > create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/memory.json
> > create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/others.json
> > create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
> > create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/pmc.json
> > create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/translation.json
> >
> > ---
> > Changelog:
> > v1 -> v2
> > - Removed inconsistencies in "BriefDescription" field and make sure
> > it will end with period without any space at the end.
> > Suggested by : Paul A. Clarke
> > - Added Tested-by and Reviewed-by tag.
> > ---
> > diff --git a/tools/perf/pmu-events/arch/powerpc/mapfile.csv b/tools/perf/pmu-events/arch/powerpc/mapfile.csv
> > index 229150e7ab7d..4abdfc3f9692 100644
> > --- a/tools/perf/pmu-events/arch/powerpc/mapfile.csv
> > +++ b/tools/perf/pmu-events/arch/powerpc/mapfile.csv
> > @@ -15,3 +15,4 @@
> > # Power8 entries
> > 004[bcd][[:xdigit:]]{4},1,power8,core
> > 004e[[:xdigit:]]{4},1,power9,core
> > +0080[[:xdigit:]]{4},1,power10,core
> > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/cache.json b/tools/perf/pmu-events/arch/powerpc/power10/cache.json
> > new file mode 100644
> > index 000000000000..95e33531fbc6
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/powerpc/power10/cache.json
> > @@ -0,0 +1,47 @@
> > +[
> > + {
> > + "EventCode": "1003C",
> > + "EventName": "PM_EXEC_STALL_DMISS_L2L3",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
> > + },
> > + {
> > + "EventCode": "34056",
> > + "EventName": "PM_EXEC_STALL_LOAD_FINISH",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the NTF instruction merged with another load in the LMQ."
> > + },
> > + {
> > + "EventCode": "3006C",
> > + "EventName": "PM_RUN_CYC_SMT2_MODE",
> > + "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
> > + },
> > + {
> > + "EventCode": "300F4",
> > + "EventName": "PM_RUN_INST_CMPL_CONC",
> > + "BriefDescription": "PowerPC instructions completed by this thread when all threads in the core had the run-latch set."
> > + },
> > + {
> > + "EventCode": "4C016",
> > + "EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."
> > + },
> > + {
> > + "EventCode": "4D014",
> > + "EventName": "PM_EXEC_STALL_LOAD",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit."
> > + },
> > + {
> > + "EventCode": "4D016",
> > + "EventName": "PM_EXEC_STALL_PTESYNC",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit."
> > + },
> > + {
> > + "EventCode": "401EA",
> > + "EventName": "PM_THRESH_EXC_128",
> > + "BriefDescription": "Threshold counter exceeded a value of 128."
> > + },
> > + {
> > + "EventCode": "400F6",
> > + "EventName": "PM_BR_MPRED_CMPL",
> > + "BriefDescription": "A mispredicted branch completed. Includes direction and target."
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json b/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
> > new file mode 100644
> > index 000000000000..e9b92f282d3c
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/powerpc/power10/floating_point.json
> > @@ -0,0 +1,7 @@
> > +[
> > + {
> > + "EventCode": "4016E",
> > + "EventName": "PM_THRESH_NOT_MET",
> > + "BriefDescription": "Threshold counter did not meet threshold."
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/frontend.json b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json
> > new file mode 100644
> > index 000000000000..aebaf94bfdfe
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json
> > @@ -0,0 +1,217 @@
> > +[
> > + {
> > + "EventCode": "10004",
> > + "EventName": "PM_EXEC_STALL_TRANSLATION",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or ERAT miss and waited for it to resolve."
> > + },
> > + {
> > + "EventCode": "10010",
> > + "EventName": "PM_PMC4_OVERFLOW",
> > + "BriefDescription": "The event selected for PMC4 caused the event counter to overflow."
> > + },
> > + {
> > + "EventCode": "10020",
> > + "EventName": "PM_PMC4_REWIND",
> > + "BriefDescription": "The speculative event selected for PMC4 rewinds and the counter for PMC4 is not charged."
> > + },
> > + {
> > + "EventCode": "10038",
> > + "EventName": "PM_DISP_STALL_TRANSLATION",
> > + "BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling a translation miss."
> > + },
> > + {
> > + "EventCode": "1003A",
> > + "EventName": "PM_DISP_STALL_BR_MPRED_IC_L2",
> > + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict."
> > + },
> > + {
> > + "EventCode": "1E050",
> > + "EventName": "PM_DISP_STALL_HELD_STF_MAPPER_CYC",
> > + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR."
> > + },
> > + {
> > + "EventCode": "1F054",
> > + "EventName": "PM_DTLB_HIT",
> > + "BriefDescription": "The PTE required by the instruction was resident in the TLB (data TLB access). When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefetch. Applies to both HPT and RPT."
> > + },
> > + {
> > + "EventCode": "101E8",
> > + "EventName": "PM_THRESH_EXC_256",
> > + "BriefDescription": "Threshold counter exceeded a count of 256."
> > + },
> > + {
> > + "EventCode": "101EC",
> > + "EventName": "PM_THRESH_MET",
> > + "BriefDescription": "Threshold exceeded."
> > + },
> > + {
> > + "EventCode": "100F2",
> > + "EventName": "PM_1PLUS_PPC_CMPL",
> > + "BriefDescription": "Cycles in which at least one instruction is completed by this thread."
> > + },
> > + {
> > + "EventCode": "100F6",
> > + "EventName": "PM_IERAT_MISS",
> > + "BriefDescription": "IERAT Reloaded to satisfy an IERAT miss. All page sizes are counted by this event."
> > + },
> > + {
> > + "EventCode": "100F8",
> > + "EventName": "PM_DISP_STALL_CYC",
> > + "BriefDescription": "Cycles the ICT has no itags assigned to this thread (no instructions were dispatched during these cycles)."
> > + },
> > + {
> > + "EventCode": "20114",
> > + "EventName": "PM_MRK_L2_RC_DISP",
> > + "BriefDescription": "Marked instruction RC dispatched in L2."
> > + },
> > + {
> > + "EventCode": "2C010",
> > + "EventName": "PM_EXEC_STALL_LSU",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Load Store Unit. This does not include simple fixed point instructions."
> > + },
> > + {
> > + "EventCode": "2C016",
> > + "EventName": "PM_DISP_STALL_IERAT_ONLY_MISS",
> > + "BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT miss."
> > + },
> > + {
> > + "EventCode": "2C01E",
> > + "EventName": "PM_DISP_STALL_BR_MPRED_IC_L3",
> > + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3 after suffering a branch mispredict."
> > + },
> > + {
> > + "EventCode": "2D01A",
> > + "EventName": "PM_DISP_STALL_IC_MISS",
> > + "BriefDescription": "Cycles when dispatch was stalled for this thread due to an Icache Miss."
> > + },
> > + {
> > + "EventCode": "2D01C",
> > + "EventName": "PM_CMPL_STALL_STCX",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for resolution from the nest before completing."
> > + },
> > + {
> > + "EventCode": "2E018",
> > + "EventName": "PM_DISP_STALL_FETCH",
> > + "BriefDescription": "Cycles when dispatch was stalled for this thread because Fetch was being held."
> > + },
> > + {
> > + "EventCode": "2E01A",
> > + "EventName": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC",
> > + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the XVFC mapper/SRB was full."
> > + },
> > + {
> > + "EventCode": "2C142",
> > + "EventName": "PM_MRK_XFER_FROM_SRC_PMC2",
> > + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> > + },
> > + {
> > + "EventCode": "24050",
> > + "EventName": "PM_IOPS_DISP",
> > + "BriefDescription": "Internal Operations dispatched. PM_IOPS_DISP / PM_INST_DISP will show the average number of internal operations per PowerPC instruction."
> > + },
> > + {
> > + "EventCode": "2405E",
> > + "EventName": "PM_ISSUE_CANCEL",
> > + "BriefDescription": "An instruction issued and the issue was later cancelled. Only one cancel per PowerPC instruction."
> > + },
> > + {
> > + "EventCode": "200FA",
> > + "EventName": "PM_BR_TAKEN_CMPL",
> > + "BriefDescription": "Branch Taken instruction completed."
> > + },
> > + {
> > + "EventCode": "30012",
> > + "EventName": "PM_FLUSH_COMPLETION",
> > + "BriefDescription": "The instruction that was next to complete (oldest in the pipeline) did not complete because it suffered a flush."
> > + },
> > + {
> > + "EventCode": "30014",
> > + "EventName": "PM_EXEC_STALL_STORE",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store instruction executing in the Load Store Unit."
> > + },
> > + {
> > + "EventCode": "30018",
> > + "EventName": "PM_DISP_STALL_HELD_SCOREBOARD_CYC",
> > + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."
> > + },
> > + {
> > + "EventCode": "30026",
> > + "EventName": "PM_EXEC_STALL_STORE_MISS",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store whose cache line was not resident in the L1 and was waiting for allocation of the missing line into the L1."
> > + },
> > + {
> > + "EventCode": "3012A",
> > + "EventName": "PM_MRK_L2_RC_DONE",
> > + "BriefDescription": "L2 RC machine completed the transaction for the marked instruction."
> > + },
> > + {
> > + "EventCode": "3F046",
> > + "EventName": "PM_ITLB_HIT_1G",
> > + "BriefDescription": "Instruction TLB hit (IERAT reload) page size 1G, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "34058",
> > + "EventName": "PM_DISP_STALL_BR_MPRED_ICMISS",
> > + "BriefDescription": "Cycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss."
> > + },
> > + {
> > + "EventCode": "3D05C",
> > + "EventName": "PM_DISP_STALL_HELD_RENAME_CYC",
> > + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC."
> > + },
> > + {
> > + "EventCode": "3E052",
> > + "EventName": "PM_DISP_STALL_IC_L3",
> > + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3."
> > + },
> > + {
> > + "EventCode": "3E054",
> > + "EventName": "PM_LD_MISS_L1",
> > + "BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
> > + },
> > + {
> > + "EventCode": "301EA",
> > + "EventName": "PM_THRESH_EXC_1024",
> > + "BriefDescription": "Threshold counter exceeded a value of 1024."
> > + },
> > + {
> > + "EventCode": "300FA",
> > + "EventName": "PM_INST_FROM_L3MISS",
> > + "BriefDescription": "The processor's instruction cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."
> > + },
> > + {
> > + "EventCode": "40006",
> > + "EventName": "PM_ISSUE_KILL",
> > + "BriefDescription": "Cycles in which an instruction or group of instructions were cancelled after being issued. This event increments once per occurrence, regardless of how many instructions are included in the issue group."
> > + },
> > + {
> > + "EventCode": "40116",
> > + "EventName": "PM_MRK_LARX_FIN",
> > + "BriefDescription": "Marked load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
> > + },
> > + {
> > + "EventCode": "4C010",
> > + "EventName": "PM_DISP_STALL_BR_MPRED_IC_L3MISS",
> > + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a mispredicted branch."
> > + },
> > + {
> > + "EventCode": "4D01E",
> > + "EventName": "PM_DISP_STALL_BR_MPRED",
> > + "BriefDescription": "Cycles when dispatch was stalled for this thread due to a mispredicted branch."
> > + },
> > + {
> > + "EventCode": "4E010",
> > + "EventName": "PM_DISP_STALL_IC_L3MISS",
> > + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from any source beyond the local L3."
> > + },
> > + {
> > + "EventCode": "4E01A",
> > + "EventName": "PM_DISP_STALL_HELD_CYC",
> > + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any reason."
> > + },
> > + {
> > + "EventCode": "44056",
> > + "EventName": "PM_VECTOR_ST_CMPL",
> > + "BriefDescription": "Vector store instructions completed."
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/locks.json b/tools/perf/pmu-events/arch/powerpc/power10/locks.json
> > new file mode 100644
> > index 000000000000..fa81b470d21f
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/powerpc/power10/locks.json
> > @@ -0,0 +1,12 @@
> > +[
> > + {
> > + "EventCode": "1E058",
> > + "EventName": "PM_STCX_FAIL_FIN",
> > + "BriefDescription": "Conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock."
> > + },
> > + {
> > + "EventCode": "4E050",
> > + "EventName": "PM_STCX_PASS_FIN",
> > + "BriefDescription": "Conditional store instruction (STCX) passed. LARX and STCX are instructions used to acquire a lock."
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/marked.json b/tools/perf/pmu-events/arch/powerpc/power10/marked.json
> > new file mode 100644
> > index 000000000000..ffe38525b18b
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/powerpc/power10/marked.json
> > @@ -0,0 +1,147 @@
> > +[
> > + {
> > + "EventCode": "1002C",
> > + "EventName": "PM_LD_PREFETCH_CACHE_LINE_MISS",
> > + "BriefDescription": "The L1 cache was reloaded with a line that fulfills a prefetch request."
> > + },
> > + {
> > + "EventCode": "10132",
> > + "EventName": "PM_MRK_INST_ISSUED",
> > + "BriefDescription": "Marked instruction issued. Note that stores always get issued twice, the address gets issued to the LSU and the data gets issued to the VSU. Also, issues can sometimes get killed/cancelled and cause multiple sequential issues for the same instruction."
> > + },
> > + {
> > + "EventCode": "101E0",
> > + "EventName": "PM_MRK_INST_DISP",
> > + "BriefDescription": "The thread has dispatched a randomly sampled marked instruction."
> > + },
> > + {
> > + "EventCode": "101E2",
> > + "EventName": "PM_MRK_BR_TAKEN_CMPL",
> > + "BriefDescription": "Marked Branch Taken instruction completed."
> > + },
> > + {
> > + "EventCode": "20112",
> > + "EventName": "PM_MRK_NTF_FIN",
> > + "BriefDescription": "The marked instruction became the oldest in the pipeline before it finished. It excludes instructions that finish at dispatch."
> > + },
> > + {
> > + "EventCode": "2C01C",
> > + "EventName": "PM_EXEC_STALL_DMISS_OFF_CHIP",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a remote chip."
> > + },
> > + {
> > + "EventCode": "20138",
> > + "EventName": "PM_MRK_ST_NEST",
> > + "BriefDescription": "A store has been sampled/marked and is at the point of execution where it has completed in the core and can no longer be flushed. At this point the store is sent to the L2."
> > + },
> > + {
> > + "EventCode": "2013A",
> > + "EventName": "PM_MRK_BRU_FIN",
> > + "BriefDescription": "Marked Branch instruction finished."
> > + },
> > + {
> > + "EventCode": "2C144",
> > + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC2",
> > + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[15:27]."
> > + },
> > + {
> > + "EventCode": "24156",
> > + "EventName": "PM_MRK_STCX_FIN",
> > + "BriefDescription": "Marked conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."
> > + },
> > + {
> > + "EventCode": "24158",
> > + "EventName": "PM_MRK_INST",
> > + "BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens."
> > + },
> > + {
> > + "EventCode": "2415C",
> > + "EventName": "PM_MRK_BR_CMPL",
> > + "BriefDescription": "A marked branch completed. All branches are included."
> > + },
> > + {
> > + "EventCode": "200FD",
> > + "EventName": "PM_L1_ICACHE_MISS",
> > + "BriefDescription": "Demand iCache Miss."
> > + },
> > + {
> > + "EventCode": "30130",
> > + "EventName": "PM_MRK_INST_FIN",
> > + "BriefDescription": "marked instruction finished. Excludes instructions that finish at dispatch. Note that stores always finish twice since the address gets issued to the LSU and the data gets issued to the VSU."
> > + },
> > + {
> > + "EventCode": "34146",
> > + "EventName": "PM_MRK_LD_CMPL",
> > + "BriefDescription": "Marked loads completed."
> > + },
> > + {
> > + "EventCode": "3E158",
> > + "EventName": "PM_MRK_STCX_FAIL",
> > + "BriefDescription": "Marked conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock."
> > + },
> > + {
> > + "EventCode": "3E15A",
> > + "EventName": "PM_MRK_ST_FIN",
> > + "BriefDescription": "The marked instruction was a store of any kind."
> > + },
> > + {
> > + "EventCode": "30068",
> > + "EventName": "PM_L1_ICACHE_RELOADED_PREF",
> > + "BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)."
> > + },
> > + {
> > + "EventCode": "301E4",
> > + "EventName": "PM_MRK_BR_MPRED_CMPL",
> > + "BriefDescription": "Marked Branch Mispredicted. Includes direction and target."
> > + },
> > + {
> > + "EventCode": "300F6",
> > + "EventName": "PM_LD_DEMAND_MISS_L1",
> > + "BriefDescription": "The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish."
> > + },
> > + {
> > + "EventCode": "300FE",
> > + "EventName": "PM_DATA_FROM_L3MISS",
> > + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."
> > + },
> > + {
> > + "EventCode": "40012",
> > + "EventName": "PM_L1_ICACHE_RELOADED_ALL",
> > + "BriefDescription": "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch."
> > + },
> > + {
> > + "EventCode": "40134",
> > + "EventName": "PM_MRK_INST_TIMEO",
> > + "BriefDescription": "Marked instruction finish timeout (instruction was lost)."
> > + },
> > + {
> > + "EventCode": "4003C",
> > + "EventName": "PM_DISP_STALL_HELD_SYNC_CYC",
> > + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch."
> > + },
> > + {
> > + "EventCode": "4505A",
> > + "EventName": "PM_SP_FLOP_CMPL",
> > + "BriefDescription": "Single Precision floating point instructions completed."
> > + },
> > + {
> > + "EventCode": "4D058",
> > + "EventName": "PM_VECTOR_FLOP_CMPL",
> > + "BriefDescription": "Vector floating point instructions completed."
> > + },
> > + {
> > + "EventCode": "4D05A",
> > + "EventName": "PM_NON_MATH_FLOP_CMPL",
> > + "BriefDescription": "Non Math instructions completed."
> > + },
> > + {
> > + "EventCode": "401E0",
> > + "EventName": "PM_MRK_INST_CMPL",
> > + "BriefDescription": "marked instruction completed."
> > + },
> > + {
> > + "EventCode": "400FE",
> > + "EventName": "PM_DATA_FROM_MEMORY",
> > + "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss."
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/memory.json b/tools/perf/pmu-events/arch/powerpc/power10/memory.json
> > new file mode 100644
> > index 000000000000..6e47b96e2d66
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/powerpc/power10/memory.json
> > @@ -0,0 +1,192 @@
> > +[
> > + {
> > + "EventCode": "1000A",
> > + "EventName": "PM_PMC3_REWIND",
> > + "BriefDescription": "The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged."
> > + },
> > + {
> > + "EventCode": "1C040",
> > + "EventName": "PM_XFER_FROM_SRC_PMC1",
> > + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> > + },
> > + {
> > + "EventCode": "1C142",
> > + "EventName": "PM_MRK_XFER_FROM_SRC_PMC1",
> > + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> > + },
> > + {
> > + "EventCode": "1C144",
> > + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1",
> > + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]."
> > + },
> > + {
> > + "EventCode": "1C056",
> > + "EventName": "PM_DERAT_MISS_4K",
> > + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "1C058",
> > + "EventName": "PM_DTLB_MISS_16G",
> > + "BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "1C05C",
> > + "EventName": "PM_DTLB_MISS_2M",
> > + "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "1E056",
> > + "EventName": "PM_EXEC_STALL_STORE_PIPE",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions."
> > + },
> > + {
> > + "EventCode": "1F150",
> > + "EventName": "PM_MRK_ST_L2_CYC",
> > + "BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion."
> > + },
> > + {
> > + "EventCode": "10062",
> > + "EventName": "PM_LD_L3MISS_PEND_CYC",
> > + "BriefDescription": "Cycles L3 miss was pending for this thread."
> > + },
> > + {
> > + "EventCode": "20010",
> > + "EventName": "PM_PMC1_OVERFLOW",
> > + "BriefDescription": "The event selected for PMC1 caused the event counter to overflow."
> > + },
> > + {
> > + "EventCode": "2001A",
> > + "EventName": "PM_ITLB_HIT",
> > + "BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "2003E",
> > + "EventName": "PM_PTESYNC_FIN",
> > + "BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time."
> > + },
> > + {
> > + "EventCode": "2C040",
> > + "EventName": "PM_XFER_FROM_SRC_PMC2",
> > + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> > + },
> > + {
> > + "EventCode": "2C054",
> > + "EventName": "PM_DERAT_MISS_64K",
> > + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "2C056",
> > + "EventName": "PM_DTLB_MISS_4K",
> > + "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "2D154",
> > + "EventName": "PM_MRK_DERAT_MISS_64K",
> > + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "200F6",
> > + "EventName": "PM_DERAT_MISS",
> > + "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "3000A",
> > + "EventName": "PM_DISP_STALL_ITLB_MISS",
> > + "BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction TLB miss."
> > + },
> > + {
> > + "EventCode": "30016",
> > + "EventName": "PM_EXEC_STALL_DERAT_DTLB_MISS",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve."
> > + },
> > + {
> > + "EventCode": "3C040",
> > + "EventName": "PM_XFER_FROM_SRC_PMC3",
> > + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> > + },
> > + {
> > + "EventCode": "3C142",
> > + "EventName": "PM_MRK_XFER_FROM_SRC_PMC3",
> > + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> > + },
> > + {
> > + "EventCode": "3C144",
> > + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC3",
> > + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]."
> > + },
> > + {
> > + "EventCode": "3C054",
> > + "EventName": "PM_DERAT_MISS_16M",
> > + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "3C056",
> > + "EventName": "PM_DTLB_MISS_64K",
> > + "BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "3C058",
> > + "EventName": "PM_LARX_FIN",
> > + "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
> > + },
> > + {
> > + "EventCode": "301E2",
> > + "EventName": "PM_MRK_ST_CMPL",
> > + "BriefDescription": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores."
> > + },
> > + {
> > + "EventCode": "300FC",
> > + "EventName": "PM_DTLB_MISS",
> > + "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity."
> > + },
> > + {
> > + "EventCode": "4D02C",
> > + "EventName": "PM_PMC1_REWIND",
> > + "BriefDescription": "The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged."
> > + },
> > + {
> > + "EventCode": "4003E",
> > + "EventName": "PM_LD_CMPL",
> > + "BriefDescription": "Loads completed."
> > + },
> > + {
> > + "EventCode": "4C040",
> > + "EventName": "PM_XFER_FROM_SRC_PMC4",
> > + "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> > + },
> > + {
> > + "EventCode": "4C142",
> > + "EventName": "PM_MRK_XFER_FROM_SRC_PMC4",
> > + "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
> > + },
> > + {
> > + "EventCode": "4C144",
> > + "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC4",
> > + "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]."
> > + },
> > + {
> > + "EventCode": "4C056",
> > + "EventName": "PM_DTLB_MISS_16M",
> > + "BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "4C05A",
> > + "EventName": "PM_DTLB_MISS_1G",
> > + "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "4C15E",
> > + "EventName": "PM_MRK_DTLB_MISS_64K",
> > + "BriefDescription": "Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "4D056",
> > + "EventName": "PM_NON_FMA_FLOP_CMPL",
> > + "BriefDescription": "Non FMA instruction completed."
> > + },
> > + {
> > + "EventCode": "40164",
> > + "EventName": "PM_MRK_DERAT_MISS_2M",
> > + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/others.json b/tools/perf/pmu-events/arch/powerpc/power10/others.json
> > new file mode 100644
> > index 000000000000..2992f7961134
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/powerpc/power10/others.json
> > @@ -0,0 +1,297 @@
> > +[
> > + {
> > + "EventCode": "10016",
> > + "EventName": "PM_VSU0_ISSUE",
> > + "BriefDescription": "VSU instructions issued to VSU pipe 0."
> > + },
> > + {
> > + "EventCode": "1001C",
> > + "EventName": "PM_ULTRAVISOR_INST_CMPL",
> > + "BriefDescription": "PowerPC instructions that completed while the thread was in ultravisor state."
> > + },
> > + {
> > + "EventCode": "100F0",
> > + "EventName": "PM_CYC",
> > + "BriefDescription": "Processor cycles."
> > + },
> > + {
> > + "EventCode": "10134",
> > + "EventName": "PM_MRK_ST_DONE_L2",
> > + "BriefDescription": "Marked stores completed in L2 (RC machine done)."
> > + },
> > + {
> > + "EventCode": "1505E",
> > + "EventName": "PM_LD_HIT_L1",
> > + "BriefDescription": "Loads that finished without experiencing an L1 miss."
> > + },
> > + {
> > + "EventCode": "1D05E",
> > + "EventName": "PM_DISP_STALL_HELD_HALT_CYC",
> > + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of power management."
> > + },
> > + {
> > + "EventCode": "1E054",
> > + "EventName": "PM_EXEC_STALL_DMISS_L21_L31",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip."
> > + },
> > + {
> > + "EventCode": "1E05A",
> > + "EventName": "PM_CMPL_STALL_LWSYNC",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting to complete."
> > + },
> > + {
> > + "EventCode": "1F056",
> > + "EventName": "PM_DISP_SS0_2_INSTR_CYC",
> > + "BriefDescription": "Cycles in which Superslice 0 dispatches either 1 or 2 instructions."
> > + },
> > + {
> > + "EventCode": "1F15C",
> > + "EventName": "PM_MRK_STCX_L2_CYC",
> > + "BriefDescription": "Cycles spent in the nest portion of a marked Stcx instruction. It starts counting when the operation starts to drain to the L2 and it stops counting when the instruction retires from the Instruction Completion Table (ICT) in the Instruction Sequencing Unit (ISU)."
> > + },
> > + {
> > + "EventCode": "10066",
> > + "EventName": "PM_ADJUNCT_CYC",
> > + "BriefDescription": "Cycles in which the thread is in Adjunct state. MSR[S HV PR] bits = 011."
> > + },
> > + {
> > + "EventCode": "101E4",
> > + "EventName": "PM_MRK_L1_ICACHE_MISS",
> > + "BriefDescription": "Marked Instruction suffered an icache Miss."
> > + },
> > + {
> > + "EventCode": "101EA",
> > + "EventName": "PM_MRK_L1_RELOAD_VALID",
> > + "BriefDescription": "Marked demand reload."
> > + },
> > + {
> > + "EventCode": "100F4",
> > + "EventName": "PM_FLOP_CMPL",
> > + "BriefDescription": "Floating Point Operations Completed. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1|2|4|8_FLOP_CMPL events to count flops."
> > + },
> > + {
> > + "EventCode": "100FA",
> > + "EventName": "PM_RUN_LATCH_ANY_THREAD_CYC",
> > + "BriefDescription": "Cycles when at least one thread has the run latch set."
> > + },
> > + {
> > + "EventCode": "100FC",
> > + "EventName": "PM_LD_REF_L1",
> > + "BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included."
> > + },
> > + {
> > + "EventCode": "20006",
> > + "EventName": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC",
> > + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue."
> > + },
> > + {
> > + "EventCode": "2000C",
> > + "EventName": "PM_RUN_LATCH_ALL_THREADS_CYC",
> > + "BriefDescription": "Cycles when the run latch is set for all threads."
> > + },
> > + {
> > + "EventCode": "2E010",
> > + "EventName": "PM_ADJUNCT_INST_CMPL",
> > + "BriefDescription": "PowerPC instructions that completed while the thread is in Adjunct state."
> > + },
> > + {
> > + "EventCode": "2E014",
> > + "EventName": "PM_STCX_FIN",
> > + "BriefDescription": "Conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."
> > + },
> > + {
> > + "EventCode": "20130",
> > + "EventName": "PM_MRK_INST_DECODED",
> > + "BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only."
> > + },
> > + {
> > + "EventCode": "20132",
> > + "EventName": "PM_MRK_DFU_ISSUE",
> > + "BriefDescription": "The marked instruction was a decimal floating point operation issued to the VSU. Measured at issue time."
> > + },
> > + {
> > + "EventCode": "20134",
> > + "EventName": "PM_MRK_FXU_ISSUE",
> > + "BriefDescription": "The marked instruction was a fixed point operation issued to the VSU. Measured at issue time."
> > + },
> > + {
> > + "EventCode": "2505C",
> > + "EventName": "PM_VSU_ISSUE",
> > + "BriefDescription": "At least one VSU instruction was issued to one of the VSU pipes. Up to 4 per cycle. Includes fixed point operations."
> > + },
> > + {
> > + "EventCode": "2F054",
> > + "EventName": "PM_DISP_SS1_2_INSTR_CYC",
> > + "BriefDescription": "Cycles in which Superslice 1 dispatches either 1 or 2 instructions."
> > + },
> > + {
> > + "EventCode": "2F056",
> > + "EventName": "PM_DISP_SS1_4_INSTR_CYC",
> > + "BriefDescription": "Cycles in which Superslice 1 dispatches either 3 or 4 instructions."
> > + },
> > + {
> > + "EventCode": "2006C",
> > + "EventName": "PM_RUN_CYC_SMT4_MODE",
> > + "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT4 mode."
> > + },
> > + {
> > + "EventCode": "201E0",
> > + "EventName": "PM_MRK_DATA_FROM_MEMORY",
> > + "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked load."
> > + },
> > + {
> > + "EventCode": "201E4",
> > + "EventName": "PM_MRK_DATA_FROM_L3MISS",
> > + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked load."
> > + },
> > + {
> > + "EventCode": "201E8",
> > + "EventName": "PM_THRESH_EXC_512",
> > + "BriefDescription": "Threshold counter exceeded a value of 512."
> > + },
> > + {
> > + "EventCode": "200F2",
> > + "EventName": "PM_INST_DISP",
> > + "BriefDescription": "PowerPC instructions dispatched."
> > + },
> > + {
> > + "EventCode": "30132",
> > + "EventName": "PM_MRK_VSU_FIN",
> > + "BriefDescription": "VSU marked instructions finished. Excludes simple FX instructions issued to the Store Unit."
> > + },
> > + {
> > + "EventCode": "30038",
> > + "EventName": "PM_EXEC_STALL_DMISS_LMEM",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCapp cache, or local OpenCapp memory."
> > + },
> > + {
> > + "EventCode": "3F04A",
> > + "EventName": "PM_LSU_ST5_FIN",
> > + "BriefDescription": "LSU Finished an internal operation in ST2 port."
> > + },
> > + {
> > + "EventCode": "34054",
> > + "EventName": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict."
> > + },
> > + {
> > + "EventCode": "3405A",
> > + "EventName": "PM_PRIVILEGED_INST_CMPL",
> > + "BriefDescription": "PowerPC Instructions that completed while the thread is in Privileged state."
> > + },
> > + {
> > + "EventCode": "3F150",
> > + "EventName": "PM_MRK_ST_DRAIN_CYC",
> > + "BriefDescription": "cycles to drain st from core to L2."
> > + },
> > + {
> > + "EventCode": "3F054",
> > + "EventName": "PM_DISP_SS0_4_INSTR_CYC",
> > + "BriefDescription": "Cycles in which Superslice 0 dispatches either 3 or 4 instructions."
> > + },
> > + {
> > + "EventCode": "3F056",
> > + "EventName": "PM_DISP_SS0_8_INSTR_CYC",
> > + "BriefDescription": "Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions."
> > + },
> > + {
> > + "EventCode": "30162",
> > + "EventName": "PM_MRK_ISSUE_DEPENDENT_LOAD",
> > + "BriefDescription": "The marked instruction was dependent on a load. It is eligible for issue kill."
> > + },
> > + {
> > + "EventCode": "40114",
> > + "EventName": "PM_MRK_START_PROBE_NOP_DISP",
> > + "BriefDescription": "Marked Start probe nop dispatched. Instruction AND R0,R0,R0."
> > + },
> > + {
> > + "EventCode": "4001C",
> > + "EventName": "PM_VSU_FIN",
> > + "BriefDescription": "VSU instructions finished."
> > + },
> > + {
> > + "EventCode": "4C01A",
> > + "EventName": "PM_EXEC_STALL_DMISS_OFF_NODE",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a distant chip."
> > + },
> > + {
> > + "EventCode": "4D012",
> > + "EventName": "PM_PMC3_SAVED",
> > + "BriefDescription": "The conditions for the speculative event selected for PMC3 are met and PMC3 is charged."
> > + },
> > + {
> > + "EventCode": "4D022",
> > + "EventName": "PM_HYPERVISOR_INST_CMPL",
> > + "BriefDescription": "PowerPC instructions that completed while the thread is in hypervisor state."
> > + },
> > + {
> > + "EventCode": "4D026",
> > + "EventName": "PM_ULTRAVISOR_CYC",
> > + "BriefDescription": "Cycles when the thread is in Ultravisor state. MSR[S HV PR]=110."
> > + },
> > + {
> > + "EventCode": "4D028",
> > + "EventName": "PM_PRIVILEGED_CYC",
> > + "BriefDescription": "Cycles when the thread is in Privileged state. MSR[S HV PR]=x00."
> > + },
> > + {
> > + "EventCode": "40030",
> > + "EventName": "PM_INST_FIN",
> > + "BriefDescription": "Instructions finished."
> > + },
> > + {
> > + "EventCode": "44146",
> > + "EventName": "PM_MRK_STCX_CORE_CYC",
> > + "BriefDescription": "Cycles spent in the core portion of a marked Stcx instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2."
> > + },
> > + {
> > + "EventCode": "44054",
> > + "EventName": "PM_VECTOR_LD_CMPL",
> > + "BriefDescription": "Vector load instructions completed."
> > + },
> > + {
> > + "EventCode": "45054",
> > + "EventName": "PM_FMA_CMPL",
> > + "BriefDescription": "Two floating point instructions completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only."
> > + },
> > + {
> > + "EventCode": "45056",
> > + "EventName": "PM_SCALAR_FLOP_CMPL",
> > + "BriefDescription": "Scalar floating point instructions completed."
> > + },
> > + {
> > + "EventCode": "4505C",
> > + "EventName": "PM_MATH_FLOP_CMPL",
> > + "BriefDescription": "Math floating point instructions completed."
> > + },
> > + {
> > + "EventCode": "4D05E",
> > + "EventName": "PM_BR_CMPL",
> > + "BriefDescription": "A branch completed. All branches are included."
> > + },
> > + {
> > + "EventCode": "4E15E",
> > + "EventName": "PM_MRK_INST_FLUSHED",
> > + "BriefDescription": "The marked instruction was flushed."
> > + },
> > + {
> > + "EventCode": "401E6",
> > + "EventName": "PM_MRK_INST_FROM_L3MISS",
> > + "BriefDescription": "The processor's instruction cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked instruction."
> > + },
> > + {
> > + "EventCode": "401E8",
> > + "EventName": "PM_MRK_DATA_FROM_L2MISS",
> > + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1 or L2 due to a demand miss for a marked load."
> > + },
> > + {
> > + "EventCode": "400F0",
> > + "EventName": "PM_LD_DEMAND_MISS_L1_FIN",
> > + "BriefDescription": "Load Missed L1, counted at finish time."
> > + },
> > + {
> > + "EventCode": "400FA",
> > + "EventName": "PM_RUN_INST_CMPL",
> > + "BriefDescription": "Completed PowerPC instructions gated by the run latch."
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json b/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
> > new file mode 100644
> > index 000000000000..33c1c39ea323
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
> > @@ -0,0 +1,297 @@
> > +[
> > + {
> > + "EventCode": "100FE",
> > + "EventName": "PM_INST_CMPL",
> > + "BriefDescription": "PowerPC instructions completed."
> > + },
> > + {
> > + "EventCode": "10006",
> > + "EventName": "PM_DISP_STALL_HELD_OTHER_CYC",
> > + "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any other reason."
> > + },
> > + {
> > + "EventCode": "1000C",
> > + "EventName": "PM_LSU_LD0_FIN",
> > + "BriefDescription": "LSU Finished an internal operation in LD0 port."
> > + },
> > + {
> > + "EventCode": "1000E",
> > + "EventName": "PM_MMA_ISSUED",
> > + "BriefDescription": "MMA instructions issued."
> > + },
> > + {
> > + "EventCode": "10012",
> > + "EventName": "PM_LSU_ST0_FIN",
> > + "BriefDescription": "LSU Finished an internal operation in ST0 port."
> > + },
> > + {
> > + "EventCode": "10014",
> > + "EventName": "PM_LSU_ST4_FIN",
> > + "BriefDescription": "LSU Finished an internal operation in ST4 port."
> > + },
> > + {
> > + "EventCode": "10018",
> > + "EventName": "PM_IC_DEMAND_CYC",
> > + "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss."
> > + },
> > + {
> > + "EventCode": "10022",
> > + "EventName": "PM_PMC2_SAVED",
> > + "BriefDescription": "The conditions for the speculative event selected for PMC2 are met and PMC2 is charged."
> > + },
> > + {
> > + "EventCode": "10024",
> > + "EventName": "PM_PMC5_OVERFLOW",
> > + "BriefDescription": "The event selected for PMC5 caused the event counter to overflow."
> > + },
> > + {
> > + "EventCode": "10058",
> > + "EventName": "PM_EXEC_STALL_FIN_AT_DISP",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch and did not require execution in the LSU, BRU or VSU."
> > + },
> > + {
> > + "EventCode": "1005A",
> > + "EventName": "PM_FLUSH_MPRED",
> > + "BriefDescription": "A flush occurred due to a mispredicted branch. Includes target and direction."
> > + },
> > + {
> > + "EventCode": "1C05A",
> > + "EventName": "PM_DERAT_MISS_2M",
> > + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
> > + },
> > + {
> > + "EventCode": "10064",
> > + "EventName": "PM_DISP_STALL_IC_L2",
> > + "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2."
> > + },
> > + {
> > + "EventCode": "10068",
> > + "EventName": "PM_BR_FIN",
> > + "BriefDescription": "A branch instruction finished. Includes predicted/mispredicted/unconditional."
> > + },
> > + {
> > + "EventCode": "1006A",
> > + "EventName": "PM_FX_LSU_FIN",
> > + "BriefDescription": "Simple fixed point instruction issued to the store unit. Measured at finish time."
> > + },
> > + {
> > + "EventCode": "1006C",
> > + "EventName": "PM_RUN_CYC_ST_MODE",
> > + "BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
> > + },
> > + {
> > + "EventCode": "20004",
> > + "EventName": "PM_ISSUE_STALL",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not issued yet."
> > + },
> > + {
> > + "EventCode": "2000A",
> > + "EventName": "PM_HYPERVISOR_CYC",
> > + "BriefDescription": "Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010."
> > + },
> > + {
> > + "EventCode": "2000E",
> > + "EventName": "PM_LSU_LD1_FIN",
> > + "BriefDescription": "LSU Finished an internal operation in LD1 port."
> > + },
> > + {
> > + "EventCode": "2C014",
> > + "EventName": "PM_CMPL_STALL_SPECIAL",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handling before completing."
> > + },
> > + {
> > + "EventCode": "2C018",
> > + "EventName": "PM_EXEC_STALL_DMISS_L3MISS",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a source beyond the local L2 or local L3."
> > + },
> > + {
> > + "EventCode": "2D010",
> > + "EventName": "PM_LSU_ST1_FIN",
> > + "BriefDescription": "LSU Finished an internal operation in ST1 port."
> > + },
> > + {
> > + "EventCode": "2D012",
> > + "EventName": "PM_VSU1_ISSUE",
> > + "BriefDescription": "VSU instructions issued to VSU pipe 1."
> > + },
> > + {
> > + "EventCode": "2D018",
> > + "EventName": "PM_EXEC_STALL_VSU",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the VSU (includes FXU, VSU, CRU)."
> > + },
> > + {
> > + "EventCode": "2E01E",
> > + "EventName": "PM_EXEC_STALL_NTC_FLUSH",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in any unit before it was flushed. Note that if the flush of the oldest instruction happens after finish, the cycles from dispatch to issue will be included in PM_DISP_STALL and the cycles from issue to finish will be included in PM_EXEC_STALL and its corresponding children."
> > + },
> > + {
> > + "EventCode": "2013C",
> > + "EventName": "PM_MRK_FX_LSU_FIN",
> > + "BriefDescription": "The marked instruction was simple fixed point that was issued to the store unit. Measured at finish time."
> > + },
> > + {
> > + "EventCode": "2405A",
> > + "EventName": "PM_NTC_FIN",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note that instructions can finish out of order, therefore not all the instructions that finish have a Next-to-complete status."
> > + },
> > + {
> > + "EventCode": "201E2",
> > + "EventName": "PM_MRK_LD_MISS_L1",
> > + "BriefDescription": "Marked DL1 Demand Miss counted at finish time."
> > + },
> > + {
> > + "EventCode": "200F4",
> > + "EventName": "PM_RUN_CYC",
> > + "BriefDescription": "Processor cycles gated by the run latch."
> > + },
> > + {
> > + "EventCode": "30004",
> > + "EventName": "PM_DISP_STALL_FLUSH",
> > + "BriefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet NTC. PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC."
> > + },
> > + {
> > + "EventCode": "30008",
> > + "EventName": "PM_EXEC_STALL",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting to finish in one of the execution units (BRU, LSU, VSU). Only cycles between issue and finish are counted in this category."
> > + },
> > + {
> > + "EventCode": "3001A",
> > + "EventName": "PM_LSU_ST2_FIN",
> > + "BriefDescription": "LSU Finished an internal operation in ST2 port."
> > + },
> > + {
> > + "EventCode": "30020",
> > + "EventName": "PM_PMC2_REWIND",
> > + "BriefDescription": "The speculative event selected for PMC2 rewinds and the counter for PMC2 is not charged."
> > + },
> > + {
> > + "EventCode": "30022",
> > + "EventName": "PM_PMC4_SAVED",
> > + "BriefDescription": "The conditions for the speculative event selected for PMC4 are met and PMC4 is charged."
> > + },
> > + {
> > + "EventCode": "30024",
> > + "EventName": "PM_PMC6_OVERFLOW",
> > + "BriefDescription": "The event selected for PMC6 caused the event counter to overflow."
> > + },
> > + {
> > + "EventCode": "30028",
> > + "EventName": "PM_CMPL_STALL_MEM_ECC",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC."
> > + },
> > + {
> > + "EventCode": "30036",
> > + "EventName": "PM_EXEC_STALL_SIMPLE_FX",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a simple fixed point instruction executing in the Load Store Unit."
> > + },
> > + {
> > + "EventCode": "3003A",
> > + "EventName": "PM_CMPL_STALL_EXCEPTION",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete."
> > + },
> > + {
> > + "EventCode": "3F044",
> > + "EventName": "PM_VSU2_ISSUE",
> > + "BriefDescription": "VSU instructions issued to VSU pipe 2."
> > + },
> > + {
> > + "EventCode": "30058",
> > + "EventName": "PM_TLBIE_FIN",
> > + "BriefDescription": "TLBIE instructions finished in the LSU. Two TLBIEs can finish each cycle. All will be counted."
> > + },
> > + {
> > + "EventCode": "3D058",
> > + "EventName": "PM_SCALAR_FSQRT_FDIV_ISSUE",
> > + "BriefDescription": "Scalar versions of four floating point operations: fdiv,fsqrt (xvdivdp, xvdivsp, xvsqrtdp, xvsqrtsp)."
> > + },
> > + {
> > + "EventCode": "30066",
> > + "EventName": "PM_LSU_FIN",
> > + "BriefDescription": "LSU Finished an internal operation (up to 4 per cycle)."
> > + },
> > + {
> > + "EventCode": "40004",
> > + "EventName": "PM_FXU_ISSUE",
> > + "BriefDescription": "A fixed point instruction was issued to the VSU."
> > + },
> > + {
> > + "EventCode": "40008",
> > + "EventName": "PM_NTC_ALL_FIN",
> > + "BriefDescription": "Cycles in which both instructions in the ICT entry pair show as finished. These are the cycles between finish and completion for the oldest pair of instructions in the pipeline."
> > + },
> > + {
> > + "EventCode": "40010",
> > + "EventName": "PM_PMC3_OVERFLOW",
> > + "BriefDescription": "The event selected for PMC3 caused the event counter to overflow."
> > + },
> > + {
> > + "EventCode": "4C012",
> > + "EventName": "PM_EXEC_STALL_DERAT_ONLY_MISS",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered an ERAT miss and waited for it resolve."
> > + },
> > + {
> > + "EventCode": "4C018",
> > + "EventName": "PM_CMPL_STALL",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline cannot complete because the thread was blocked for any reason."
> > + },
> > + {
> > + "EventCode": "4C01E",
> > + "EventName": "PM_LSU_ST3_FIN",
> > + "BriefDescription": "LSU Finished an internal operation in ST3 port."
> > + },
> > + {
> > + "EventCode": "4D018",
> > + "EventName": "PM_EXEC_STALL_BRU",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Branch unit."
> > + },
> > + {
> > + "EventCode": "4D01A",
> > + "EventName": "PM_CMPL_STALL_HWSYNC",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a hwsync waiting for response from L2 before completing."
> > + },
> > + {
> > + "EventCode": "4D01C",
> > + "EventName": "PM_EXEC_STALL_TLBIEL",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIEL instruction executing in the Load Store Unit. TLBIEL instructions have lower overhead than TLBIE instructions because they don't get set to the nest."
> > + },
> > + {
> > + "EventCode": "4E012",
> > + "EventName": "PM_EXEC_STALL_UNKNOWN",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline completed without an ntf_type pulse. The ntf_pulse was missed by the ISU because the NTF finishes and completions came too close together."
> > + },
> > + {
> > + "EventCode": "4D020",
> > + "EventName": "PM_VSU3_ISSUE",
> > + "BriefDescription": "VSU instruction was issued to VSU pipe 3."
> > + },
> > + {
> > + "EventCode": "40132",
> > + "EventName": "PM_MRK_LSU_FIN",
> > + "BriefDescription": "LSU marked instruction finish."
> > + },
> > + {
> > + "EventCode": "45058",
> > + "EventName": "PM_IC_MISS_CMPL",
> > + "BriefDescription": "Non-speculative icache miss, counted at completion."
> > + },
> > + {
> > + "EventCode": "4D050",
> > + "EventName": "PM_VSU_NON_FLOP_CMPL",
> > + "BriefDescription": "Non-floating point VSU instructions completed."
> > + },
> > + {
> > + "EventCode": "4D052",
> > + "EventName": "PM_2FLOP_CMPL",
> > + "BriefDescription": "Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg completed."
> > + },
> > + {
> > + "EventCode": "400F2",
> > + "EventName": "PM_1PLUS_PPC_DISP",
> > + "BriefDescription": "Cycles at least one Instr Dispatched."
> > + },
> > + {
> > + "EventCode": "400F8",
> > + "EventName": "PM_FLUSH",
> > + "BriefDescription": "Flush (any type)."
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/pmc.json b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json
> > new file mode 100644
> > index 000000000000..60a0100ee996
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json
> > @@ -0,0 +1,22 @@
> > +[
> > + {
> > + "EventCode": "301E8",
> > + "EventName": "PM_THRESH_EXC_64",
> > + "BriefDescription": "Threshold counter exceeded a value of 64."
> > + },
> > + {
> > + "EventCode": "45050",
> > + "EventName": "PM_1FLOP_CMPL",
> > + "BriefDescription": "One floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
> > + },
> > + {
> > + "EventCode": "45052",
> > + "EventName": "PM_4FLOP_CMPL",
> > + "BriefDescription": "Four floating point instructions completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."
> > + },
> > + {
> > + "EventCode": "4D054",
> > + "EventName": "PM_8FLOP_CMPL",
> > + "BriefDescription": "Four Double Precision vector instructions completed."
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/translation.json b/tools/perf/pmu-events/arch/powerpc/power10/translation.json
> > new file mode 100644
> > index 000000000000..da44d4ca6ef3
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/powerpc/power10/translation.json
> > @@ -0,0 +1,57 @@
> > +[
> > + {
> > + "EventCode": "1F15E",
> > + "EventName": "PM_MRK_START_PROBE_NOP_CMPL",
> > + "BriefDescription": "Marked Start probe nop (AND R0,R0,R0) completed."
> > + },
> > + {
> > + "EventCode": "20016",
> > + "EventName": "PM_ST_FIN",
> > + "BriefDescription": "Store finish count. Includes speculative activity."
> > + },
> > + {
> > + "EventCode": "20018",
> > + "EventName": "PM_ST_FWD",
> > + "BriefDescription": "Store forwards that finished."
> > + },
> > + {
> > + "EventCode": "2011C",
> > + "EventName": "PM_MRK_NTF_CYC",
> > + "BriefDescription": "Cycles during which the marked instruction is the oldest in the pipeline (NTF or NTC)."
> > + },
> > + {
> > + "EventCode": "2E01C",
> > + "EventName": "PM_EXEC_STALL_TLBIE",
> > + "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIE instruction executing in the Load Store Unit."
> > + },
> > + {
> > + "EventCode": "201E6",
> > + "EventName": "PM_THRESH_EXC_32",
> > + "BriefDescription": "Threshold counter exceeded a value of 32."
> > + },
> > + {
> > + "EventCode": "200F0",
> > + "EventName": "PM_ST_CMPL",
> > + "BriefDescription": "Stores completed from S2Q (2nd-level store queue). This event includes regular stores, stcx and cache inhibited stores. The following operations are excluded (pteupdate, snoop tlbie complete, store atomics, miso, load atomic payloads, tlbie, tlbsync, slbieg, isync, msgsnd, slbiag, cpabort, copy, tcheck, tend, stsync, dcbst, icbi, dcbf, hwsync, lwsync, ptesync, eieio, msgsync)."
> > + },
> > + {
> > + "EventCode": "200FE",
> > + "EventName": "PM_DATA_FROM_L2MISS",
> > + "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1 or L2 due to a demand miss."
> > + },
> > + {
> > + "EventCode": "30010",
> > + "EventName": "PM_PMC2_OVERFLOW",
> > + "BriefDescription": "The event selected for PMC2 caused the event counter to overflow."
> > + },
> > + {
> > + "EventCode": "4D010",
> > + "EventName": "PM_PMC1_SAVED",
> > + "BriefDescription": "The conditions for the speculative event selected for PMC1 are met and PMC1 is charged."
> > + },
> > + {
> > + "EventCode": "4D05C",
> > + "EventName": "PM_DPP_FLOP_CMPL",
> > + "BriefDescription": "Double-Precision or Quad-Precision instructions completed."
> > + }
> > +]
> > --
> > 2.27.0
--
- Arnaldo
^ permalink raw reply
* Re: PPC_FPU, ALTIVEC: enable_kernel_fp, put_vr, get_vr
From: Randy Dunlap @ 2021-04-19 17:59 UTC (permalink / raw)
To: Michael Ellerman, Segher Boessenkool, Christophe Leroy; +Cc: PowerPC, LKML
In-Reply-To: <87sg3mct3x.fsf@mpe.ellerman.id.au>
On 4/19/21 6:16 AM, Michael Ellerman wrote:
> Randy Dunlap <rdunlap@infradead.org> writes:
>> On 4/18/21 10:46 AM, Segher Boessenkool wrote:
>>> On Sun, Apr 18, 2021 at 06:24:29PM +0200, Christophe Leroy wrote:
>>>> Le 17/04/2021 à 22:17, Randy Dunlap a écrit :
>>>>> Should the code + Kconfigs/Makefiles handle that kind of
>>>>> kernel config or should ALTIVEC always mean PPC_FPU as well?
>>>>
>>>> As far as I understand, Altivec is completely independant of FPU in Theory.
>>>
>>> And, as far as the hardware is concerned, in practice as well.
>>>
>>>> So it should be possible to use Altivec without using FPU.
>>>
>>> Yup.
>>>
>>>> However, until recently, it was not possible to de-activate FPU support on
>>>> book3s/32. I made it possible in order to reduce unneccessary processing on
>>>> processors like the 832x that has no FPU.
>>>
>>> The processor has to implement FP to be compliant to any version of
>>> PowerPC, as far as I know? So that is all done by emulation, including
>>> all the registers? Wow painful.
>>>
>>>> As far as I can see in cputable.h/.c, 832x is the only book3s/32 without
>>>> FPU, and it doesn't have ALTIVEC either.
>>>
>>> 602 doesn't have double-precision hardware, also no 64-bit FP registers.
>>> But that CPU was never any widely used :-)
>>>
>>>> So we can in the future ensure that Altivec can be used without FPU
>>>> support, but for the time being I think it is OK to force selection of FPU
>>>> when selecting ALTIVEC in order to avoid build failures.
>>>
>>> It is useful to allow MSR[VEC,FP]=1,0 but yeah there are no CPUs that
>>> have VMX (aka AltiVec) but that do not have FP. I don't see how making
>>> that artificial dependency buys anything, but maybe it does?
>>>
>>>>> I have patches to fix the build errors with the config as
>>>>> reported but I don't know if that's the right thing to do...
>>>
>>> Neither do we, we cannot see those patches :-)
>>
>> Sure. I'll post them later today.
>> They keep FPU and ALTIVEC as independent (build) features.
>
> Those patches look OK.
>
> But I don't think it makes sense to support that configuration, FPU=n
> ALTVEC=y. No one is ever going to make a CPU like that. We have enough
Agreed.
> testing surface due to configuration options, without adding artificial
> combinations that no one is ever going to use.
>
> IMHO :)
>
> So I'd rather we just make ALTIVEC depend on FPU.
>
> cheers
Makes sense and sounds good to me.
thanks.
--
~Randy
^ permalink raw reply
* [powerpc:next 231/236] arch/powerpc/kernel/fadump.c:731:28: error: use of undeclared identifier 'INTERRUPT_SYSTEM_RESET'
From: kernel test robot @ 2021-04-19 18:28 UTC (permalink / raw)
To: Xiongwei Song; +Cc: clang-built-linux, kbuild-all, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 4201 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
head: cbd3d5ba46b68c033986a6087209930f001cbcca
commit: 7153d4bf0b373428d0393c001019da4d0483fddb [231/236] powerpc/traps: Enhance readability for trap types
config: powerpc-randconfig-r016-20210419 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 2b50f5a4343f8fb06acaa5c36355bcf58092c9cd)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install powerpc cross compiling tool for clang build
# apt-get install binutils-powerpc-linux-gnu
# https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id=7153d4bf0b373428d0393c001019da4d0483fddb
git remote add powerpc https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
git fetch --no-tags powerpc next
git checkout 7153d4bf0b373428d0393c001019da4d0483fddb
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Note: the powerpc/next HEAD cbd3d5ba46b68c033986a6087209930f001cbcca builds fine.
It only hurts bisectibility.
All errors (new ones prefixed by >>):
>> arch/powerpc/kernel/fadump.c:731:28: error: use of undeclared identifier 'INTERRUPT_SYSTEM_RESET'
if (TRAP(&(fdh->regs)) == INTERRUPT_SYSTEM_RESET) {
^
arch/powerpc/kernel/fadump.c:1703:22: error: no previous prototype for function 'arch_reserved_kernel_pages' [-Werror,-Wmissing-prototypes]
unsigned long __init arch_reserved_kernel_pages(void)
^
arch/powerpc/kernel/fadump.c:1703:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
unsigned long __init arch_reserved_kernel_pages(void)
^
static
2 errors generated.
vim +/INTERRUPT_SYSTEM_RESET +731 arch/powerpc/kernel/fadump.c
679
680 void crash_fadump(struct pt_regs *regs, const char *str)
681 {
682 unsigned int msecs;
683 struct fadump_crash_info_header *fdh = NULL;
684 int old_cpu, this_cpu;
685 /* Do not include first CPU */
686 unsigned int ncpus = num_online_cpus() - 1;
687
688 if (!should_fadump_crash())
689 return;
690
691 /*
692 * old_cpu == -1 means this is the first CPU which has come here,
693 * go ahead and trigger fadump.
694 *
695 * old_cpu != -1 means some other CPU has already on it's way
696 * to trigger fadump, just keep looping here.
697 */
698 this_cpu = smp_processor_id();
699 old_cpu = cmpxchg(&crashing_cpu, -1, this_cpu);
700
701 if (old_cpu != -1) {
702 atomic_inc(&cpus_in_fadump);
703
704 /*
705 * We can't loop here indefinitely. Wait as long as fadump
706 * is in force. If we race with fadump un-registration this
707 * loop will break and then we go down to normal panic path
708 * and reboot. If fadump is in force the first crashing
709 * cpu will definitely trigger fadump.
710 */
711 while (fw_dump.dump_registered)
712 cpu_relax();
713 return;
714 }
715
716 fdh = __va(fw_dump.fadumphdr_addr);
717 fdh->crashing_cpu = crashing_cpu;
718 crash_save_vmcoreinfo();
719
720 if (regs)
721 fdh->regs = *regs;
722 else
723 ppc_save_regs(&fdh->regs);
724
725 fdh->online_mask = *cpu_online_mask;
726
727 /*
728 * If we came in via system reset, wait a while for the secondary
729 * CPUs to enter.
730 */
> 731 if (TRAP(&(fdh->regs)) == INTERRUPT_SYSTEM_RESET) {
732 msecs = CRASH_TIMEOUT;
733 while ((atomic_read(&cpus_in_fadump) < ncpus) && (--msecs > 0))
734 mdelay(1);
735 }
736
737 fw_dump.ops->fadump_trigger(fdh, str);
738 }
739
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 38749 bytes --]
^ permalink raw reply
* Re: [PATCH] powerpc/pseries: Add shutdown() to vio_driver and vio_bus
From: Tyrel Datwyler @ 2021-04-19 18:30 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <87im4ldrft.fsf@mpe.ellerman.id.au>
On 4/17/21 5:30 AM, Michael Ellerman wrote:
> Tyrel Datwyler <tyreld@linux.ibm.com> writes:
>> On 4/1/21 5:13 PM, Tyrel Datwyler wrote:
>>> Currently, neither the vio_bus or vio_driver structures provide support
>>> for a shutdown() routine.
>>>
>>> Add support for shutdown() by allowing drivers to provide a
>>> implementation via function pointer in their vio_driver struct and
>>> provide a proper implementation in the driver template for the vio_bus
>>> that calls a vio drivers shutdown() if defined.
>>>
>>> In the case that no shutdown() is defined by a vio driver and a kexec is
>>> in progress we implement a big hammer that calls remove() to ensure no
>>> further DMA for the devices is possible.
>>>
>>> Signed-off-by: Tyrel Datwyler <tyreld@linux.ibm.com>
>>> ---
>>
>> Ping... any comments, problems with this approach?
>
> The kexec part seems like a bit of a hack.
>
> It also doesn't help for kdump, when none of the shutdown code is run.
If I understand correctly for kdump we have a reserved memory space where the
kdump kernel is loaded, but for kexec the memory region isn't reserved ahead of
time meaning we can try and load the kernel over potential memory used for DMA
by the current kernel. Please correct me if I've got that wrong.
>
> How many drivers do we have? Can we just implement a proper shutdown for
> them?
Well that is the end goal. I just don't currently have the bandwidth to do each
driver myself with a proper shutdown sequence, and thought this was a launching
off point to at least introduce the shutdown callback to the VIO bus.
Off the top of my head we have 3 storage drivers, 2 network drivers, vtpm, vmc,
pseries_rng, nx, nx842, hvcs, hvc_vio.
I can drop the kexec_in_progress hammer and just have each driver call remove()
themselves in their shutdown function. Leave it to each maintainer to decide if
remove() is enough or if there is a more lightweight quiesce sequence they
choose to implement.
-Tyrel
>
> cheers
>
^ permalink raw reply
* Re: PPC_FPU, ALTIVEC: enable_kernel_fp, put_vr, get_vr
From: Randy Dunlap @ 2021-04-19 21:39 UTC (permalink / raw)
To: Michael Ellerman, Segher Boessenkool, Christophe Leroy; +Cc: PowerPC, LKML
In-Reply-To: <87sg3mct3x.fsf@mpe.ellerman.id.au>
On 4/19/21 6:16 AM, Michael Ellerman wrote:
> Randy Dunlap <rdunlap@infradead.org> writes:
>> Sure. I'll post them later today.
>> They keep FPU and ALTIVEC as independent (build) features.
>
> Those patches look OK.
>
> But I don't think it makes sense to support that configuration, FPU=n
> ALTVEC=y. No one is ever going to make a CPU like that. We have enough
> testing surface due to configuration options, without adding artificial
> combinations that no one is ever going to use.
>
> IMHO :)
>
> So I'd rather we just make ALTIVEC depend on FPU.
That's rather simple. See below.
I'm doing a bunch of randconfig builds with it now.
---
From: Randy Dunlap <rdunlap@infradead.org>
Subject: [PATCH] powerpc: make ALTIVEC depend PPC_FPU
On a kernel config with ALTIVEC=y and PPC_FPU not set/enabled,
there are build errors:
drivers/cpufreq/pmac32-cpufreq.c:262:2: error: implicit declaration of function 'enable_kernel_fp' [-Werror,-Wimplicit-function-declaration]
enable_kernel_fp();
../arch/powerpc/lib/sstep.c: In function 'do_vec_load':
../arch/powerpc/lib/sstep.c:637:3: error: implicit declaration of function 'put_vr' [-Werror=implicit-function-declaration]
637 | put_vr(rn, &u.v);
| ^~~~~~
../arch/powerpc/lib/sstep.c: In function 'do_vec_store':
../arch/powerpc/lib/sstep.c:660:3: error: implicit declaration of function 'get_vr'; did you mean 'get_oc'? [-Werror=implicit-function-declaration]
660 | get_vr(rn, &u.v);
| ^~~~~~
In theory ALTIVEC is independent of PPC_FPU but in practice nobody
is going to build such a machine, so make ALTIVEC require PPC_FPU
by depending on PPC_FPU.
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: kernel test robot <lkp@intel.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Segher Boessenkool <segher@kernel.crashing.org>
Cc: lkp@intel.com
---
arch/powerpc/platforms/86xx/Kconfig | 1 +
arch/powerpc/platforms/Kconfig.cputype | 2 ++
2 files changed, 3 insertions(+)
--- linux-next-20210416.orig/arch/powerpc/platforms/86xx/Kconfig
+++ linux-next-20210416/arch/powerpc/platforms/86xx/Kconfig
@@ -4,6 +4,7 @@ menuconfig PPC_86xx
bool "86xx-based boards"
depends on PPC_BOOK3S_32
select FSL_SOC
+ select PPC_FPU
select ALTIVEC
help
The Freescale E600 SoCs have 74xx cores.
--- linux-next-20210416.orig/arch/powerpc/platforms/Kconfig.cputype
+++ linux-next-20210416/arch/powerpc/platforms/Kconfig.cputype
@@ -186,6 +186,7 @@ config E300C3_CPU
config G4_CPU
bool "G4 (74xx)"
depends on PPC_BOOK3S_32
+ select PPC_FPU
select ALTIVEC
endchoice
@@ -309,6 +310,7 @@ config PHYS_64BIT
config ALTIVEC
bool "AltiVec Support"
+ depends on PPC_FPU
depends on PPC_BOOK3S_32 || PPC_BOOK3S_64 || (PPC_E500MC && PPC64)
help
This option enables kernel support for the Altivec extensions to the
^ permalink raw reply
* Re: [RFC v1 PATCH 3/3] driver: update all the code that use soc_device_match
From: Guenter Roeck @ 2021-04-19 13:36 UTC (permalink / raw)
To: Alice Guo (OSS), gregkh, rafael, horia.geanta, aymen.sghaier,
herbert, davem, tony, geert+renesas, mturquette, sboyd, vkoul,
peter.ujfalusi, a.hajda, narmstrong, robert.foss, airlied, daniel,
khilman, tomba, jyri.sarha, joro, will, mchehab, ulf.hansson,
adrian.hunter, kishon, kuba, linus.walleij, Roy.Pledge,
leoyang.li, ssantosh, matthias.bgg, edubezval, j-keerthy, balbi,
linux, stern, wim
Cc: linux-usb, linux-watchdog, linux-gpio, netdev, linux-pm,
linux-staging, linux-mmc, linux-kernel, dri-devel,
linux-renesas-soc, linux-phy, iommu, linux-mediatek, linux-crypto,
dmaengine, linux-amlogic, linux-omap, linuxppc-dev, linux-clk,
linux-arm-kernel, linux-media
In-Reply-To: <20210419042722.27554-4-alice.guo@oss.nxp.com>
On 4/18/21 9:27 PM, Alice Guo (OSS) wrote:
> From: Alice Guo <alice.guo@nxp.com>
>
> Update all the code that use soc_device_match because add support for
> soc_device_match returning -EPROBE_DEFER.
>
> Signed-off-by: Alice Guo <alice.guo@nxp.com>
> ---
[ ... ]
> drivers/watchdog/renesas_wdt.c | 2 +-
> 48 files changed, 131 insertions(+), 52 deletions(-)
>
[ ... ]
> diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
> index 5791198960e6..fdc534dc4024 100644
> --- a/drivers/watchdog/renesas_wdt.c
> +++ b/drivers/watchdog/renesas_wdt.c
> @@ -197,7 +197,7 @@ static bool rwdt_blacklisted(struct device *dev)
> const struct soc_device_attribute *attr;
>
> attr = soc_device_match(rwdt_quirks_match);
> - if (attr && setup_max_cpus > (uintptr_t)attr->data) {
> + if (!IS_ERR(attr) && attr && setup_max_cpus > (uintptr_t)attr->data) {
This is wrong. We can not make the decision below without having access
to attr. The function may wrongly return false if soc_device_match()
returns an error.
Guenter
> dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
> attr->revision);
> return true;
>
^ permalink raw reply
* Re: [PATCH] powerpc/perf: Fix PMU callbacks to clear pending PMI before resetting an overflown PMC
From: Athira Rajeev @ 2021-04-19 13:52 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: nasastry@in.ibm.com, Madhavan Srinivasan, linuxppc-dev
In-Reply-To: <32461D84-098D-44EE-A782-6C7CC7DDEBCC@linux.vnet.ibm.com>
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^ permalink raw reply
* [powerpc:next 231/236] arch/powerpc/kernel/fadump.c:731:28: error: 'INTERRUPT_SYSTEM_RESET' undeclared
From: kernel test robot @ 2021-04-19 22:27 UTC (permalink / raw)
To: Xiongwei Song; +Cc: linuxppc-dev, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 3966 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
head: cbd3d5ba46b68c033986a6087209930f001cbcca
commit: 7153d4bf0b373428d0393c001019da4d0483fddb [231/236] powerpc/traps: Enhance readability for trap types
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id=7153d4bf0b373428d0393c001019da4d0483fddb
git remote add powerpc https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
git fetch --no-tags powerpc next
git checkout 7153d4bf0b373428d0393c001019da4d0483fddb
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross W=1 ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Note: the powerpc/next HEAD cbd3d5ba46b68c033986a6087209930f001cbcca builds fine.
It only hurts bisectibility.
All errors (new ones prefixed by >>):
arch/powerpc/kernel/fadump.c:82:12: warning: no previous prototype for 'fadump_cma_init' [-Wmissing-prototypes]
82 | int __init fadump_cma_init(void)
| ^~~~~~~~~~~~~~~
arch/powerpc/kernel/fadump.c: In function 'crash_fadump':
>> arch/powerpc/kernel/fadump.c:731:28: error: 'INTERRUPT_SYSTEM_RESET' undeclared (first use in this function)
731 | if (TRAP(&(fdh->regs)) == INTERRUPT_SYSTEM_RESET) {
| ^~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/kernel/fadump.c:731:28: note: each undeclared identifier is reported only once for each function it appears in
vim +/INTERRUPT_SYSTEM_RESET +731 arch/powerpc/kernel/fadump.c
679
680 void crash_fadump(struct pt_regs *regs, const char *str)
681 {
682 unsigned int msecs;
683 struct fadump_crash_info_header *fdh = NULL;
684 int old_cpu, this_cpu;
685 /* Do not include first CPU */
686 unsigned int ncpus = num_online_cpus() - 1;
687
688 if (!should_fadump_crash())
689 return;
690
691 /*
692 * old_cpu == -1 means this is the first CPU which has come here,
693 * go ahead and trigger fadump.
694 *
695 * old_cpu != -1 means some other CPU has already on it's way
696 * to trigger fadump, just keep looping here.
697 */
698 this_cpu = smp_processor_id();
699 old_cpu = cmpxchg(&crashing_cpu, -1, this_cpu);
700
701 if (old_cpu != -1) {
702 atomic_inc(&cpus_in_fadump);
703
704 /*
705 * We can't loop here indefinitely. Wait as long as fadump
706 * is in force. If we race with fadump un-registration this
707 * loop will break and then we go down to normal panic path
708 * and reboot. If fadump is in force the first crashing
709 * cpu will definitely trigger fadump.
710 */
711 while (fw_dump.dump_registered)
712 cpu_relax();
713 return;
714 }
715
716 fdh = __va(fw_dump.fadumphdr_addr);
717 fdh->crashing_cpu = crashing_cpu;
718 crash_save_vmcoreinfo();
719
720 if (regs)
721 fdh->regs = *regs;
722 else
723 ppc_save_regs(&fdh->regs);
724
725 fdh->online_mask = *cpu_online_mask;
726
727 /*
728 * If we came in via system reset, wait a while for the secondary
729 * CPUs to enter.
730 */
> 731 if (TRAP(&(fdh->regs)) == INTERRUPT_SYSTEM_RESET) {
732 msecs = CRASH_TIMEOUT;
733 while ((atomic_read(&cpus_in_fadump) < ncpus) && (--msecs > 0))
734 mdelay(1);
735 }
736
737 fw_dump.ops->fadump_trigger(fdh, str);
738 }
739
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 72728 bytes --]
^ permalink raw reply
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