* [PATCH 02/11] powerpc: Add Microwatt device tree
From: Paul Mackerras @ 2021-06-14 22:58 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <YMfeswgEHeXSLOUF@thinks.paulus.ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/boot/dts/microwatt.dts | 105 ++++++++++++++++++++++++++++
1 file changed, 105 insertions(+)
create mode 100644 arch/powerpc/boot/dts/microwatt.dts
diff --git a/arch/powerpc/boot/dts/microwatt.dts b/arch/powerpc/boot/dts/microwatt.dts
new file mode 100644
index 000000000000..9b2e64da9432
--- /dev/null
+++ b/arch/powerpc/boot/dts/microwatt.dts
@@ -0,0 +1,105 @@
+/dts-v1/;
+
+/ {
+ #size-cells = <0x02>;
+ #address-cells = <0x02>;
+ model-name = "microwatt";
+ compatible = "microwatt-soc";
+
+ reserved-memory {
+ #size-cells = <0x02>;
+ #address-cells = <0x02>;
+ ranges;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x10000000>;
+ };
+
+ cpus {
+ #size-cells = <0x00>;
+ #address-cells = <0x01>;
+
+ ibm,powerpc-cpu-features {
+ display-name = "Microwatt";
+ isa = <3000>;
+ device_type = "cpu-features";
+ compatible = "ibm,powerpc-cpu-features";
+
+ mmu-radix {
+ isa = <3000>;
+ usable-privilege = <2>;
+ os-support = <0x00>;
+ };
+
+ little-endian {
+ isa = <0>;
+ usable-privilege = <3>;
+ os-support = <0x00>;
+ };
+
+ cache-inhibited-large-page {
+ isa = <0x00>;
+ usable-privilege = <2>;
+ os-support = <0x00>;
+ };
+
+ fixed-point-v3 {
+ isa = <3000>;
+ usable-privilege = <3>;
+ };
+
+ no-execute {
+ isa = <0x00>;
+ usable-privilege = <2>;
+ os-support = <0x00>;
+ };
+
+ floating-point {
+ hfscr-bit-nr = <0x00>;
+ hwcap-bit-nr = <0x1b>;
+ isa = <0x00>;
+ usable-privilege = <0x07>;
+ hv-support = <0x00>;
+ os-support = <0x00>;
+ };
+ };
+
+ PowerPC,Microwatt@0 {
+ i-cache-sets = <2>;
+ ibm,dec-bits = <64>;
+ reservation-granule-size = <64>;
+ clock-frequency = <100000000>;
+ timebase-frequency = <100000000>;
+ i-tlb-sets = <1>;
+ ibm,ppc-interrupt-server#s = <0>;
+ i-cache-block-size = <64>;
+ d-cache-block-size = <64>;
+ ibm,pa-features = [40 00 c2 27 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00];
+ d-cache-sets = <2>;
+ ibm,pir = <0x3c>;
+ i-tlb-size = <64>;
+ cpu-version = <0x990000>;
+ status = "okay";
+ i-cache-size = <0x1000>;
+ ibm,processor-radix-AP-encodings = <0x0c 0xa0000010 0x20000015 0x4000001e>;
+ tlb-size = <0>;
+ tlb-sets = <0>;
+ device_type = "cpu";
+ d-tlb-size = <128>;
+ d-tlb-sets = <2>;
+ reg = <0>;
+ general-purpose;
+ 64-bit;
+ d-cache-size = <0x1000>;
+ ibm,chip-id = <0x00>;
+ };
+ };
+
+ chosen {
+ bootargs = "";
+ ibm,architecture-vec-5 = [19 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 40];
+ };
+
+};
--
2.31.1
^ permalink raw reply related
* [PATCH 08/11] powerpc/microwatt: Add microwatt_defconfig
From: Paul Mackerras @ 2021-06-14 23:02 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <YMfeswgEHeXSLOUF@thinks.paulus.ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/configs/microwatt_defconfig | 98 ++++++++++++++++++++++++
1 file changed, 98 insertions(+)
create mode 100644 arch/powerpc/configs/microwatt_defconfig
diff --git a/arch/powerpc/configs/microwatt_defconfig b/arch/powerpc/configs/microwatt_defconfig
new file mode 100644
index 000000000000..a08b739123da
--- /dev/null
+++ b/arch/powerpc/configs/microwatt_defconfig
@@ -0,0 +1,98 @@
+# CONFIG_SWAP is not set
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=12
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB_MERGE_DEFAULT is not set
+CONFIG_PPC64=y
+# CONFIG_PPC_KUEP is not set
+# CONFIG_PPC_KUAP is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NR_IRQS=64
+CONFIG_PANIC_TIMEOUT=10
+# CONFIG_PPC_POWERNV is not set
+# CONFIG_PPC_PSERIES is not set
+CONFIG_PPC_MICROWATT=y
+# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
+CONFIG_CPU_FREQ=y
+CONFIG_HZ_100=y
+# CONFIG_PPC_MEM_KEYS is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_MQ_IOSCHED_KYBER is not set
+# CONFIG_COREDUMP is not set
+# CONFIG_COMPACTION is not set
+# CONFIG_MIGRATION is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=y
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=y
+CONFIG_INET=y
+CONFIG_INET_UDP_DIAG=y
+CONFIG_INET_RAW_DIAG=y
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_PARTITIONED_MASTER=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_NETDEVICES=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_NVRAM is not set
+CONFIG_RANDOM_TRUST_CPU=y
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_NVMEM is not set
+CONFIG_EXT4_FS=y
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+CONFIG_PRINTK_TIME=y
+# CONFIG_SYMBOLIC_ERRNAME is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MISC is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_PPC_DISABLE_WERROR=y
+CONFIG_XMON=y
+CONFIG_XMON_DEFAULT=y
+# CONFIG_XMON_DEFAULT_RO_MODE is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
--
2.31.1
^ permalink raw reply related
* [PATCH 10/11] powerpc/microwatt: Add a boot wrapper for Microwatt
From: Paul Mackerras @ 2021-06-14 23:03 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <YMfeswgEHeXSLOUF@thinks.paulus.ozlabs.org>
From: Joel Stanley <joel@jms.id.au>
This allows microwatt's kernel to be built with an embedded device tree.
Load to arch/powerpc/boot/dtbImage.microwatt to 0x500000:
mw_debug -b fpga stop load arch/powerpc/boot/dtbImage.microwatt 500000 start
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/powerpc/boot/Makefile | 4 ++++
arch/powerpc/boot/microwatt.c | 18 ++++++++++++++++++
arch/powerpc/boot/wrapper | 5 +++++
3 files changed, 27 insertions(+)
create mode 100644 arch/powerpc/boot/microwatt.c
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 2b8da923ceca..dfaa4094fcae 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -163,6 +163,8 @@ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+
src-wlib := $(sort $(src-wlib-y))
src-plat := $(sort $(src-plat-y))
src-boot := $(src-wlib) $(src-plat) empty.c
@@ -355,6 +357,8 @@ image-$(CONFIG_MVME5100) += dtbImage.mvme5100
# Board port in arch/powerpc/platform/amigaone/Kconfig
image-$(CONFIG_AMIGAONE) += cuImage.amigaone
+image-$(CONFIG_PPC_MICROWATT) += dtbImage.microwatt
+
# For 32-bit powermacs, build the COFF and miboot images
# as well as the ELF images.
ifdef CONFIG_PPC32
diff --git a/arch/powerpc/boot/microwatt.c b/arch/powerpc/boot/microwatt.c
new file mode 100644
index 000000000000..ac922dd0aa4d
--- /dev/null
+++ b/arch/powerpc/boot/microwatt.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <stddef.h>
+#include "stdio.h"
+#include "types.h"
+#include "io.h"
+#include "ops.h"
+
+BSS_STACK(8192);
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
+{
+ unsigned long heapsize = 16*1024*1024 - (unsigned long)_end;
+
+ simple_alloc_init(_end, heapsize, 32, 64);
+ fdt_init(_dtb_start);
+ serial_console_init();
+}
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 41fa0a8715e3..ae48fffa1e13 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -342,6 +342,11 @@ gamecube|wii)
link_address='0x600000'
platformo="$object/$platform-head.o $object/$platform.o"
;;
+microwatt)
+ link_address='0x500000'
+ platformo="$object/fixed-head.o $object/$platform.o"
+ binary=y
+ ;;
treeboot-currituck)
link_address='0x1000000'
;;
--
2.31.1
^ permalink raw reply related
* [PATCH 01/11] powerpc: Add Microwatt platform
From: Paul Mackerras @ 2021-06-14 22:57 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <YMfeswgEHeXSLOUF@thinks.paulus.ozlabs.org>
Microwatt is a FPGA-based implementation of the Power ISA. It
currently only implements little-endian 64-bit mode, and does
not (yet) support SMP, VMX, VSX or transactional memory.
This adds a new machine type to support FPGA-based SoCs with a
Microwatt core.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/platforms/Kconfig | 1 +
arch/powerpc/platforms/Makefile | 1 +
arch/powerpc/platforms/microwatt/Kconfig | 9 +++++++++
arch/powerpc/platforms/microwatt/Makefile | 1 +
arch/powerpc/platforms/microwatt/setup.c | 23 +++++++++++++++++++++++
6 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/platforms/microwatt/Kconfig
create mode 100644 arch/powerpc/platforms/microwatt/Makefile
create mode 100644 arch/powerpc/platforms/microwatt/setup.c
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 386ae12d8523..5ce51c38a346 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -422,7 +422,7 @@ config HUGETLB_PAGE_SIZE_VARIABLE
config MATH_EMULATION
bool "Math emulation"
- depends on 4xx || PPC_8xx || PPC_MPC832x || BOOKE
+ depends on 4xx || PPC_8xx || PPC_MPC832x || BOOKE || PPC_MICROWATT
select PPC_FPU_REGS
help
Some PowerPC chips designed for embedded applications do not have
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 7a5e8f4541e3..74be4d06afbf 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -20,6 +20,7 @@ source "arch/powerpc/platforms/embedded6xx/Kconfig"
source "arch/powerpc/platforms/44x/Kconfig"
source "arch/powerpc/platforms/40x/Kconfig"
source "arch/powerpc/platforms/amigaone/Kconfig"
+source "arch/powerpc/platforms/microwatt/Kconfig"
config KVM_GUEST
bool "KVM Guest support"
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index 143d4417f6cc..edcb54cdb1a8 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_PPC_CELL) += cell/
obj-$(CONFIG_PPC_PS3) += ps3/
obj-$(CONFIG_EMBEDDED6xx) += embedded6xx/
obj-$(CONFIG_AMIGAONE) += amigaone/
+obj-$(CONFIG_PPC_MICROWATT) += microwatt/
diff --git a/arch/powerpc/platforms/microwatt/Kconfig b/arch/powerpc/platforms/microwatt/Kconfig
new file mode 100644
index 000000000000..3be01e78ce57
--- /dev/null
+++ b/arch/powerpc/platforms/microwatt/Kconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+config PPC_MICROWATT
+ depends on PPC_BOOK3S_64 && !SMP
+ bool "Microwatt SoC platform"
+ select PPC_XICS
+ select PPC_NATIVE
+ help
+ This option enables support for FPGA-based Microwatt implementations.
+
diff --git a/arch/powerpc/platforms/microwatt/Makefile b/arch/powerpc/platforms/microwatt/Makefile
new file mode 100644
index 000000000000..e6885b3b2ee7
--- /dev/null
+++ b/arch/powerpc/platforms/microwatt/Makefile
@@ -0,0 +1 @@
+obj-y += setup.o
diff --git a/arch/powerpc/platforms/microwatt/setup.c b/arch/powerpc/platforms/microwatt/setup.c
new file mode 100644
index 000000000000..d80d52612672
--- /dev/null
+++ b/arch/powerpc/platforms/microwatt/setup.c
@@ -0,0 +1,23 @@
+/*
+ * Microwatt FPGA-based SoC platform setup code.
+ *
+ * Copyright 2020 Paul Mackerras (paulus@ozlabs.org), IBM Corp.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <asm/machdep.h>
+#include <asm/time.h>
+
+static int __init microwatt_probe(void)
+{
+ return of_machine_is_compatible("microwatt-soc");
+}
+
+define_machine(microwatt) {
+ .name = "microwatt",
+ .probe = microwatt_probe,
+ .calibrate_decr = generic_calibrate_decr,
+};
--
2.31.1
^ permalink raw reply related
* [PATCH 09/11] powerpc: boot: Fixup device-tree on little endian
From: Paul Mackerras @ 2021-06-14 23:04 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <YMfeswgEHeXSLOUF@thinks.paulus.ozlabs.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This fixes the core devtree.c functions and the ns16550 UART backend.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/boot/devtree.c | 59 +++++++++++++++++++++----------------
arch/powerpc/boot/ns16550.c | 9 ++++--
2 files changed, 41 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/boot/devtree.c b/arch/powerpc/boot/devtree.c
index 5d91036ad626..58fbcfcc98c9 100644
--- a/arch/powerpc/boot/devtree.c
+++ b/arch/powerpc/boot/devtree.c
@@ -13,6 +13,7 @@
#include "string.h"
#include "stdio.h"
#include "ops.h"
+#include "of.h"
void dt_fixup_memory(u64 start, u64 size)
{
@@ -23,21 +24,25 @@ void dt_fixup_memory(u64 start, u64 size)
root = finddevice("/");
if (getprop(root, "#address-cells", &naddr, sizeof(naddr)) < 0)
naddr = 2;
+ else
+ naddr = be32_to_cpu(naddr);
if (naddr < 1 || naddr > 2)
fatal("Can't cope with #address-cells == %d in /\n\r", naddr);
if (getprop(root, "#size-cells", &nsize, sizeof(nsize)) < 0)
nsize = 1;
+ else
+ nsize = be32_to_cpu(nsize);
if (nsize < 1 || nsize > 2)
fatal("Can't cope with #size-cells == %d in /\n\r", nsize);
i = 0;
if (naddr == 2)
- memreg[i++] = start >> 32;
- memreg[i++] = start & 0xffffffff;
+ memreg[i++] = cpu_to_be32(start >> 32);
+ memreg[i++] = cpu_to_be32(start & 0xffffffff);
if (nsize == 2)
- memreg[i++] = size >> 32;
- memreg[i++] = size & 0xffffffff;
+ memreg[i++] = cpu_to_be32(size >> 32);
+ memreg[i++] = cpu_to_be32(size & 0xffffffff);
memory = finddevice("/memory");
if (! memory) {
@@ -45,9 +50,9 @@ void dt_fixup_memory(u64 start, u64 size)
setprop_str(memory, "device_type", "memory");
}
- printf("Memory <- <0x%x", memreg[0]);
+ printf("Memory <- <0x%x", be32_to_cpu(memreg[0]));
for (i = 1; i < (naddr + nsize); i++)
- printf(" 0x%x", memreg[i]);
+ printf(" 0x%x", be32_to_cpu(memreg[i]));
printf("> (%ldMB)\n\r", (unsigned long)(size >> 20));
setprop(memory, "reg", memreg, (naddr + nsize)*sizeof(u32));
@@ -65,10 +70,10 @@ void dt_fixup_cpu_clocks(u32 cpu, u32 tb, u32 bus)
printf("CPU bus-frequency <- 0x%x (%dMHz)\n\r", bus, MHZ(bus));
while ((devp = find_node_by_devtype(devp, "cpu"))) {
- setprop_val(devp, "clock-frequency", cpu);
- setprop_val(devp, "timebase-frequency", tb);
+ setprop_val(devp, "clock-frequency", cpu_to_be32(cpu));
+ setprop_val(devp, "timebase-frequency", cpu_to_be32(tb));
if (bus > 0)
- setprop_val(devp, "bus-frequency", bus);
+ setprop_val(devp, "bus-frequency", cpu_to_be32(bus));
}
timebase_period_ns = 1000000000 / tb;
@@ -80,7 +85,7 @@ void dt_fixup_clock(const char *path, u32 freq)
if (devp) {
printf("%s: clock-frequency <- %x (%dMHz)\n\r", path, freq, MHZ(freq));
- setprop_val(devp, "clock-frequency", freq);
+ setprop_val(devp, "clock-frequency", cpu_to_be32(freq));
}
}
@@ -133,8 +138,12 @@ void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize)
{
if (getprop(node, "#address-cells", naddr, 4) != 4)
*naddr = 2;
+ else
+ *naddr = be32_to_cpu(*naddr);
if (getprop(node, "#size-cells", nsize, 4) != 4)
*nsize = 1;
+ else
+ *nsize = be32_to_cpu(*nsize);
}
static void copy_val(u32 *dest, u32 *src, int naddr)
@@ -163,9 +172,9 @@ static int add_reg(u32 *reg, u32 *add, int naddr)
int i, carry = 0;
for (i = MAX_ADDR_CELLS - 1; i >= MAX_ADDR_CELLS - naddr; i--) {
- u64 tmp = (u64)reg[i] + add[i] + carry;
+ u64 tmp = (u64)be32_to_cpu(reg[i]) + be32_to_cpu(add[i]) + carry;
carry = tmp >> 32;
- reg[i] = (u32)tmp;
+ reg[i] = cpu_to_be32((u32)tmp);
}
return !carry;
@@ -180,18 +189,18 @@ static int compare_reg(u32 *reg, u32 *range, u32 *rangesize)
u32 end;
for (i = 0; i < MAX_ADDR_CELLS; i++) {
- if (reg[i] < range[i])
+ if (be32_to_cpu(reg[i]) < be32_to_cpu(range[i]))
return 0;
- if (reg[i] > range[i])
+ if (be32_to_cpu(reg[i]) > be32_to_cpu(range[i]))
break;
}
for (i = 0; i < MAX_ADDR_CELLS; i++) {
- end = range[i] + rangesize[i];
+ end = be32_to_cpu(range[i]) + be32_to_cpu(rangesize[i]);
- if (reg[i] < end)
+ if (be32_to_cpu(reg[i]) < end)
break;
- if (reg[i] > end)
+ if (be32_to_cpu(reg[i]) > end)
return 0;
}
@@ -240,7 +249,6 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
return 0;
dt_get_reg_format(parent, &naddr, &nsize);
-
if (nsize > 2)
return 0;
@@ -252,10 +260,10 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
copy_val(last_addr, prop_buf + offset, naddr);
- ret_size = prop_buf[offset + naddr];
+ ret_size = be32_to_cpu(prop_buf[offset + naddr]);
if (nsize == 2) {
ret_size <<= 32;
- ret_size |= prop_buf[offset + naddr + 1];
+ ret_size |= be32_to_cpu(prop_buf[offset + naddr + 1]);
}
for (;;) {
@@ -278,7 +286,6 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
offset = find_range(last_addr, prop_buf, prev_naddr,
naddr, prev_nsize, buflen / 4);
-
if (offset < 0)
return 0;
@@ -296,8 +303,7 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
if (naddr > 2)
return 0;
- ret_addr = ((u64)last_addr[2] << 32) | last_addr[3];
-
+ ret_addr = ((u64)be32_to_cpu(last_addr[2]) << 32) | be32_to_cpu(last_addr[3]);
if (sizeof(void *) == 4 &&
(ret_addr >= 0x100000000ULL || ret_size > 0x100000000ULL ||
ret_addr + ret_size > 0x100000000ULL))
@@ -350,11 +356,14 @@ int dt_is_compatible(void *node, const char *compat)
int dt_get_virtual_reg(void *node, void **addr, int nres)
{
unsigned long xaddr;
- int n;
+ int n, i;
n = getprop(node, "virtual-reg", addr, nres * 4);
- if (n > 0)
+ if (n > 0) {
+ for (i = 0; i < n/4; i ++)
+ ((u32 *)addr)[i] = be32_to_cpu(((u32 *)addr)[i]);
return n / 4;
+ }
for (n = 0; n < nres; n++) {
if (!dt_xlate_reg(node, n, &xaddr, NULL))
diff --git a/arch/powerpc/boot/ns16550.c b/arch/powerpc/boot/ns16550.c
index b0da4466d419..f16d2be1d0f3 100644
--- a/arch/powerpc/boot/ns16550.c
+++ b/arch/powerpc/boot/ns16550.c
@@ -15,6 +15,7 @@
#include "stdio.h"
#include "io.h"
#include "ops.h"
+#include "of.h"
#define UART_DLL 0 /* Out: Divisor Latch Low */
#define UART_DLM 1 /* Out: Divisor Latch High */
@@ -58,16 +59,20 @@ int ns16550_console_init(void *devp, struct serial_console_data *scdp)
int n;
u32 reg_offset;
- if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1)
+ if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) {
+ printf("virt reg parse fail...\r\n");
return -1;
+ }
n = getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset));
if (n == sizeof(reg_offset))
- reg_base += reg_offset;
+ reg_base += be32_to_cpu(reg_offset);
n = getprop(devp, "reg-shift", ®_shift, sizeof(reg_shift));
if (n != sizeof(reg_shift))
reg_shift = 0;
+ else
+ reg_shift = be32_to_cpu(reg_shift);
scdp->open = ns16550_open;
scdp->putc = ns16550_putc;
--
2.31.1
^ permalink raw reply related
* [PATCH 06/11] powerpc: microwatt: Use standard 16550 UART for console
From: Paul Mackerras @ 2021-06-14 23:01 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <YMfeswgEHeXSLOUF@thinks.paulus.ozlabs.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This adds support to the Microwatt platform to use the standard
1655-style UART which available in the standalone Microwatt FPGA.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/boot/dts/microwatt.dts | 25 ++++++++++++---
arch/powerpc/kernel/udbg_16550.c | 39 ++++++++++++++++++++++++
arch/powerpc/platforms/microwatt/Kconfig | 1 +
arch/powerpc/platforms/microwatt/setup.c | 2 ++
4 files changed, 62 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/boot/dts/microwatt.dts b/arch/powerpc/boot/dts/microwatt.dts
index 2e75600320e8..dbde200d4692 100644
--- a/arch/powerpc/boot/dts/microwatt.dts
+++ b/arch/powerpc/boot/dts/microwatt.dts
@@ -6,6 +6,10 @@ / {
model-name = "microwatt";
compatible = "microwatt-soc";
+ aliases {
+ serial0 = &UART0;
+ };
+
reserved-memory {
#size-cells = <0x02>;
#address-cells = <0x02>;
@@ -97,11 +101,6 @@ PowerPC,Microwatt@0 {
};
};
- chosen {
- bootargs = "";
- ibm,architecture-vec-5 = [19 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 40];
- };
-
soc@c0000000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -126,5 +125,21 @@ ICS: interrupt-controller@5000 {
#interrupt-cells = <2>;
};
+ UART0: serial@2000 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x2000 0x8>;
+ clock-frequency = <100000000>;
+ current-speed = <115200>;
+ reg-shift = <2>;
+ fifo-size = <16>;
+ interrupts = <0x10 0x1>;
+ };
+ };
+
+ chosen {
+ bootargs = "";
+ ibm,architecture-vec-5 = [19 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 40];
+ stdout-path = &UART0;
};
};
diff --git a/arch/powerpc/kernel/udbg_16550.c b/arch/powerpc/kernel/udbg_16550.c
index 9356b60d6030..8513aa49614e 100644
--- a/arch/powerpc/kernel/udbg_16550.c
+++ b/arch/powerpc/kernel/udbg_16550.c
@@ -296,3 +296,42 @@ void __init udbg_init_40x_realmode(void)
}
#endif /* CONFIG_PPC_EARLY_DEBUG_40x */
+
+#ifdef CONFIG_PPC_EARLY_DEBUG_MICROWATT
+
+#define UDBG_UART_MW_ADDR ((void __iomem *)0xc0002000)
+
+static u8 udbg_uart_in_isa300_rm(unsigned int reg)
+{
+ uint64_t msr = mfmsr();
+ uint8_t c;
+
+ mtmsr(msr & ~(MSR_EE|MSR_DR));
+ isync();
+ eieio();
+ c = __raw_rm_readb(UDBG_UART_MW_ADDR + (reg << 2));
+ mtmsr(msr);
+ isync();
+ return c;
+}
+
+static void udbg_uart_out_isa300_rm(unsigned int reg, u8 val)
+{
+ uint64_t msr = mfmsr();
+
+ mtmsr(msr & ~(MSR_EE|MSR_DR));
+ isync();
+ eieio();
+ __raw_rm_writeb(val, UDBG_UART_MW_ADDR + (reg << 2));
+ mtmsr(msr);
+ isync();
+}
+
+void __init udbg_init_debug_microwatt(void)
+{
+ udbg_uart_in = udbg_uart_in_isa300_rm;
+ udbg_uart_out = udbg_uart_out_isa300_rm;
+ udbg_use_uart();
+}
+
+#endif /* CONFIG_PPC_EARLY_DEBUG_MICROWATT */
diff --git a/arch/powerpc/platforms/microwatt/Kconfig b/arch/powerpc/platforms/microwatt/Kconfig
index b52c869c0eb8..50ed0cedb5f1 100644
--- a/arch/powerpc/platforms/microwatt/Kconfig
+++ b/arch/powerpc/platforms/microwatt/Kconfig
@@ -6,6 +6,7 @@ config PPC_MICROWATT
select PPC_ICS_NATIVE
select PPC_ICP_NATIVE
select PPC_NATIVE
+ select PPC_UDBG_16550
help
This option enables support for FPGA-based Microwatt implementations.
diff --git a/arch/powerpc/platforms/microwatt/setup.c b/arch/powerpc/platforms/microwatt/setup.c
index 1c1b7791fa57..0b02603bdb74 100644
--- a/arch/powerpc/platforms/microwatt/setup.c
+++ b/arch/powerpc/platforms/microwatt/setup.c
@@ -14,6 +14,7 @@
#include <asm/machdep.h>
#include <asm/time.h>
#include <asm/xics.h>
+#include <asm/udbg.h>
static void __init microwatt_init_IRQ(void)
{
@@ -35,5 +36,6 @@ define_machine(microwatt) {
.name = "microwatt",
.probe = microwatt_probe,
.init_IRQ = microwatt_init_IRQ,
+ .progress = udbg_progress,
.calibrate_decr = generic_calibrate_decr,
};
--
2.31.1
^ permalink raw reply related
* [PATCH 07/11] powerpc: Add support for microwatt's hardware random number generator
From: Paul Mackerras @ 2021-06-14 23:02 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <YMfeswgEHeXSLOUF@thinks.paulus.ozlabs.org>
This is accessed using the DARN instruction and should probably be
done more generically.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/include/asm/archrandom.h | 12 +++++-
arch/powerpc/platforms/microwatt/Kconfig | 1 +
arch/powerpc/platforms/microwatt/Makefile | 2 +-
arch/powerpc/platforms/microwatt/rng.c | 48 +++++++++++++++++++++++
4 files changed, 61 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/platforms/microwatt/rng.c
diff --git a/arch/powerpc/include/asm/archrandom.h b/arch/powerpc/include/asm/archrandom.h
index 9a53e29680f4..e8ae0f7740f9 100644
--- a/arch/powerpc/include/asm/archrandom.h
+++ b/arch/powerpc/include/asm/archrandom.h
@@ -8,12 +8,22 @@
static inline bool __must_check arch_get_random_long(unsigned long *v)
{
+ if (ppc_md.get_random_seed)
+ return ppc_md.get_random_seed(v);
+
return false;
}
static inline bool __must_check arch_get_random_int(unsigned int *v)
{
- return false;
+ unsigned long val;
+ bool rc;
+
+ rc = arch_get_random_long(&val);
+ if (rc)
+ *v = val;
+
+ return rc;
}
static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
diff --git a/arch/powerpc/platforms/microwatt/Kconfig b/arch/powerpc/platforms/microwatt/Kconfig
index 50ed0cedb5f1..8f6a81978461 100644
--- a/arch/powerpc/platforms/microwatt/Kconfig
+++ b/arch/powerpc/platforms/microwatt/Kconfig
@@ -7,6 +7,7 @@ config PPC_MICROWATT
select PPC_ICP_NATIVE
select PPC_NATIVE
select PPC_UDBG_16550
+ select ARCH_RANDOM
help
This option enables support for FPGA-based Microwatt implementations.
diff --git a/arch/powerpc/platforms/microwatt/Makefile b/arch/powerpc/platforms/microwatt/Makefile
index e6885b3b2ee7..116d6d3ad3f0 100644
--- a/arch/powerpc/platforms/microwatt/Makefile
+++ b/arch/powerpc/platforms/microwatt/Makefile
@@ -1 +1 @@
-obj-y += setup.o
+obj-y += setup.o rng.o
diff --git a/arch/powerpc/platforms/microwatt/rng.c b/arch/powerpc/platforms/microwatt/rng.c
new file mode 100644
index 000000000000..3d8ee6eb7dad
--- /dev/null
+++ b/arch/powerpc/platforms/microwatt/rng.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Derived from arch/powerpc/platforms/powernv/rng.c, which is:
+ * Copyright 2013, Michael Ellerman, IBM Corporation.
+ */
+
+#define pr_fmt(fmt) "microwatt-rng: " fmt
+
+#include <linux/kernel.h>
+#include <linux/smp.h>
+#include <asm/archrandom.h>
+#include <asm/cputable.h>
+#include <asm/machdep.h>
+
+#define DARN_ERR 0xFFFFFFFFFFFFFFFFul
+
+int microwatt_get_random_darn(unsigned long *v)
+{
+ unsigned long val;
+
+ /* Using DARN with L=1 - 64-bit conditioned random number */
+ asm volatile(PPC_DARN(%0, 1) : "=r"(val));
+
+ if (val == DARN_ERR)
+ return 0;
+
+ *v = val;
+
+ return 1;
+}
+
+static __init int rng_init(void)
+{
+ unsigned long val;
+ int i;
+
+ for (i = 0; i < 10; i++) {
+ if (microwatt_get_random_darn(&val)) {
+ ppc_md.get_random_seed = microwatt_get_random_darn;
+ return 0;
+ }
+ }
+
+ pr_warn("Unable to use DARN for get_random_seed()\n");
+
+ return -EIO;
+}
+machine_subsys_initcall(, rng_init);
--
2.31.1
^ permalink raw reply related
* [PATCH 00/11] powerpc: Add support for Microwatt soft-core
From: Paul Mackerras @ 2021-06-14 22:56 UTC (permalink / raw)
To: linuxppc-dev
This series of patches adds support for the Microwatt soft-core.
Microwatt is an open-source 64-bit Power ISA processor written in VHDL
which targets medium-sized FPGAs such as the Xilinx Artix-7 or the
Lattice ECP5. Microwatt currently implements the scalar fixed plus
floating-point subset of Power ISA v3.0B plus the radix MMU, but not
logical partitioning (i.e. it does not have hypervisor mode, the
partition table or nested radix translation).
Paul.
arch/powerpc/Kconfig | 2 +-
arch/powerpc/boot/Makefile | 4 +
arch/powerpc/boot/devtree.c | 59 ++++---
arch/powerpc/boot/dts/microwatt.dts | 145 +++++++++++++++++
arch/powerpc/boot/microwatt.c | 19 +++
arch/powerpc/boot/ns16550.c | 9 +-
arch/powerpc/boot/wrapper | 5 +
arch/powerpc/configs/microwatt_defconfig | 98 ++++++++++++
arch/powerpc/include/asm/archrandom.h | 12 +-
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/kernel/udbg_16550.c | 39 +++++
arch/powerpc/mm/book3s64/radix_pgtable.c | 13 +-
arch/powerpc/platforms/Kconfig | 1 +
arch/powerpc/platforms/Makefile | 1 +
arch/powerpc/platforms/microwatt/Kconfig | 13 ++
arch/powerpc/platforms/microwatt/Makefile | 1 +
arch/powerpc/platforms/microwatt/rng.c | 48 ++++++
arch/powerpc/platforms/microwatt/setup.c | 41 +++++
arch/powerpc/sysdev/xics/Kconfig | 3 +
arch/powerpc/sysdev/xics/Makefile | 1 +
arch/powerpc/sysdev/xics/ics-native.c | 257 ++++++++++++++++++++++++++++++
arch/powerpc/sysdev/xics/xics-common.c | 2 +
22 files changed, 741 insertions(+), 33 deletions(-)
^ permalink raw reply
* [PATCH 04/11] powerpc/microwatt: Populate platform bus from device-tree
From: Paul Mackerras @ 2021-06-14 23:00 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <YMfeswgEHeXSLOUF@thinks.paulus.ozlabs.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Just like any other embedded platform.
Add an empty soc node.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/boot/dts/microwatt.dts | 7 +++++++
arch/powerpc/platforms/microwatt/setup.c | 8 ++++++++
2 files changed, 15 insertions(+)
diff --git a/arch/powerpc/boot/dts/microwatt.dts b/arch/powerpc/boot/dts/microwatt.dts
index 9b2e64da9432..a72177e5041d 100644
--- a/arch/powerpc/boot/dts/microwatt.dts
+++ b/arch/powerpc/boot/dts/microwatt.dts
@@ -102,4 +102,11 @@ chosen {
ibm,architecture-vec-5 = [19 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 40];
};
+ soc@c0000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0xc0000000 0x40000000>;
+ };
};
diff --git a/arch/powerpc/platforms/microwatt/setup.c b/arch/powerpc/platforms/microwatt/setup.c
index d80d52612672..5af4adf881bc 100644
--- a/arch/powerpc/platforms/microwatt/setup.c
+++ b/arch/powerpc/platforms/microwatt/setup.c
@@ -8,6 +8,8 @@
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
#include <asm/machdep.h>
#include <asm/time.h>
@@ -16,6 +18,12 @@ static int __init microwatt_probe(void)
return of_machine_is_compatible("microwatt-soc");
}
+static int __init microwatt_populate(void)
+{
+ return of_platform_default_populate(NULL, NULL, NULL);
+}
+machine_arch_initcall(microwatt, microwatt_populate);
+
define_machine(microwatt) {
.name = "microwatt",
.probe = microwatt_probe,
--
2.31.1
^ permalink raw reply related
* [PATCH 03/11] powerpc/radix: Add support for microwatt's PRTBL SPR
From: Paul Mackerras @ 2021-06-14 22:59 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <YMfeswgEHeXSLOUF@thinks.paulus.ozlabs.org>
Microwatt currently doesn't implement hypervisor mode and therefore
doesn't implement the partition table. It does implement the process
table and radix page table walks.
This adds code to write the base address of the process table to the
PRTBL SPR, which has been assigned SPR 720 for now, as that is in the
range of SPR numbers assigned for experimental use. PRTBL is only
written when we have neither the FW_FEATURE_LPAR feature nor the
CPU_FTR_HVMODE feature.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/mm/book3s64/radix_pgtable.c | 13 +++++++++----
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index da103e92c112..3200a2522d6c 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -729,6 +729,7 @@
#endif
#define SPRN_TIR 0x1BE /* Thread Identification Register */
#define SPRN_PTCR 0x1D0 /* Partition table control Register */
+#define SPRN_PRTBL 0x2D0 /* Process table pointer */
#define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */
#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c b/arch/powerpc/mm/book3s64/radix_pgtable.c
index 98f0b243c1ab..6595859173a7 100644
--- a/arch/powerpc/mm/book3s64/radix_pgtable.c
+++ b/arch/powerpc/mm/book3s64/radix_pgtable.c
@@ -646,10 +646,15 @@ void __init radix__early_init_mmu(void)
radix_init_pgtable();
if (!firmware_has_feature(FW_FEATURE_LPAR)) {
- lpcr = mfspr(SPRN_LPCR);
- mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
- radix_init_partition_table();
- radix_init_amor();
+ if (cpu_has_feature(CPU_FTR_HVMODE)) {
+ lpcr = mfspr(SPRN_LPCR);
+ mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
+ radix_init_partition_table();
+ radix_init_amor();
+ } else {
+ mtspr(SPRN_PRTBL, (__pa(process_tb) |
+ (PRTB_SIZE_SHIFT - 12)));
+ }
} else {
radix_init_pseries();
}
--
2.31.1
^ permalink raw reply related
* [PATCH 05/11] powerpc/xics: Add a native ICS backend for microwatt
From: Paul Mackerras @ 2021-06-14 23:00 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <YMfeswgEHeXSLOUF@thinks.paulus.ozlabs.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This is a simple native ICS backend that matches the layout of
the Microwatt implementation of ICS.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/boot/dts/microwatt.dts | 18 ++
arch/powerpc/platforms/microwatt/Kconfig | 2 +
arch/powerpc/platforms/microwatt/setup.c | 8 +
arch/powerpc/sysdev/xics/Kconfig | 3 +
arch/powerpc/sysdev/xics/Makefile | 1 +
arch/powerpc/sysdev/xics/ics-native.c | 257 +++++++++++++++++++++++
arch/powerpc/sysdev/xics/xics-common.c | 2 +
7 files changed, 291 insertions(+)
create mode 100644 arch/powerpc/sysdev/xics/ics-native.c
diff --git a/arch/powerpc/boot/dts/microwatt.dts b/arch/powerpc/boot/dts/microwatt.dts
index a72177e5041d..2e75600320e8 100644
--- a/arch/powerpc/boot/dts/microwatt.dts
+++ b/arch/powerpc/boot/dts/microwatt.dts
@@ -106,7 +106,25 @@ soc@c0000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
+ interrupt-parent = <&ICS>;
ranges = <0 0 0xc0000000 0x40000000>;
+
+ interrupt-controller@4000 {
+ compatible = "openpower,xics-presentation", "ibm,ppc-xicp";
+ ibm,interrupt-server-ranges = <0x0 0x1>;
+ reg = <0x4000 0x100>;
+ };
+
+ ICS: interrupt-controller@5000 {
+ compatible = "openpower,xics-sources";
+ interrupt-controller;
+ interrupt-ranges = <0x10 0x10>;
+ reg = <0x5000 0x100>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
};
};
diff --git a/arch/powerpc/platforms/microwatt/Kconfig b/arch/powerpc/platforms/microwatt/Kconfig
index 3be01e78ce57..b52c869c0eb8 100644
--- a/arch/powerpc/platforms/microwatt/Kconfig
+++ b/arch/powerpc/platforms/microwatt/Kconfig
@@ -3,6 +3,8 @@ config PPC_MICROWATT
depends on PPC_BOOK3S_64 && !SMP
bool "Microwatt SoC platform"
select PPC_XICS
+ select PPC_ICS_NATIVE
+ select PPC_ICP_NATIVE
select PPC_NATIVE
help
This option enables support for FPGA-based Microwatt implementations.
diff --git a/arch/powerpc/platforms/microwatt/setup.c b/arch/powerpc/platforms/microwatt/setup.c
index 5af4adf881bc..1c1b7791fa57 100644
--- a/arch/powerpc/platforms/microwatt/setup.c
+++ b/arch/powerpc/platforms/microwatt/setup.c
@@ -10,8 +10,15 @@
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_platform.h>
+
#include <asm/machdep.h>
#include <asm/time.h>
+#include <asm/xics.h>
+
+static void __init microwatt_init_IRQ(void)
+{
+ xics_init();
+}
static int __init microwatt_probe(void)
{
@@ -27,5 +34,6 @@ machine_arch_initcall(microwatt, microwatt_populate);
define_machine(microwatt) {
.name = "microwatt",
.probe = microwatt_probe,
+ .init_IRQ = microwatt_init_IRQ,
.calibrate_decr = generic_calibrate_decr,
};
diff --git a/arch/powerpc/sysdev/xics/Kconfig b/arch/powerpc/sysdev/xics/Kconfig
index 304614c920aa..063d9195891f 100644
--- a/arch/powerpc/sysdev/xics/Kconfig
+++ b/arch/powerpc/sysdev/xics/Kconfig
@@ -12,3 +12,6 @@ config PPC_ICP_HV
config PPC_ICS_RTAS
def_bool n
+
+config PPC_ICS_NATIVE
+ def_bool n
diff --git a/arch/powerpc/sysdev/xics/Makefile b/arch/powerpc/sysdev/xics/Makefile
index ba1e3117b1c0..747063927c6c 100644
--- a/arch/powerpc/sysdev/xics/Makefile
+++ b/arch/powerpc/sysdev/xics/Makefile
@@ -4,4 +4,5 @@ obj-y += xics-common.o
obj-$(CONFIG_PPC_ICP_NATIVE) += icp-native.o
obj-$(CONFIG_PPC_ICP_HV) += icp-hv.o
obj-$(CONFIG_PPC_ICS_RTAS) += ics-rtas.o
+obj-$(CONFIG_PPC_ICS_NATIVE) += ics-native.o
obj-$(CONFIG_PPC_POWERNV) += ics-opal.o icp-opal.o
diff --git a/arch/powerpc/sysdev/xics/ics-native.c b/arch/powerpc/sysdev/xics/ics-native.c
new file mode 100644
index 000000000000..d450502f4053
--- /dev/null
+++ b/arch/powerpc/sysdev/xics/ics-native.c
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * ICS backend for OPAL managed interrupts.
+ *
+ * Copyright 2011 IBM Corp.
+ */
+
+//#define DEBUG
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/cpu.h>
+#include <linux/of.h>
+#include <linux/spinlock.h>
+#include <linux/msi.h>
+#include <linux/list.h>
+
+#include <asm/prom.h>
+#include <asm/smp.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <asm/errno.h>
+#include <asm/xics.h>
+#include <asm/opal.h>
+#include <asm/firmware.h>
+
+struct ics_native {
+ struct ics ics;
+ struct device_node *node;
+ void __iomem *base;
+ u32 ibase;
+ u32 icount;
+};
+#define to_ics_native(_ics) container_of(_ics, struct ics_native, ics)
+
+static void __iomem *ics_native_xive(struct ics_native *in, unsigned int vec)
+{
+ return in->base + 0x800 + ((vec - in->ibase) << 2);
+}
+
+static void ics_native_unmask_irq(struct irq_data *d)
+{
+ unsigned int vec = (unsigned int)irqd_to_hwirq(d);
+ struct ics *ics = irq_data_get_irq_chip_data(d);
+ struct ics_native *in = to_ics_native(ics);
+ unsigned int server;
+
+ pr_devel("ics-native: unmask virq %d [hw 0x%x]\n", d->irq, vec);
+
+ if (vec < in->ibase || vec >= (in->ibase + in->icount))
+ return;
+
+ server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0);
+ out_be32(ics_native_xive(in, vec), (server << 8) | DEFAULT_PRIORITY);
+}
+
+static unsigned int ics_native_startup(struct irq_data *d)
+{
+#ifdef CONFIG_PCI_MSI
+ /*
+ * The generic MSI code returns with the interrupt disabled on the
+ * card, using the MSI mask bits. Firmware doesn't appear to unmask
+ * at that level, so we do it here by hand.
+ */
+ if (irq_data_get_msi_desc(d))
+ pci_msi_unmask_irq(d);
+#endif
+
+ /* unmask it */
+ ics_native_unmask_irq(d);
+ return 0;
+}
+
+static void ics_native_do_mask(struct ics_native *in, unsigned int vec)
+{
+ out_be32(ics_native_xive(in, vec), 0xff);
+}
+
+static void ics_native_mask_irq(struct irq_data *d)
+{
+ unsigned int vec = (unsigned int)irqd_to_hwirq(d);
+ struct ics *ics = irq_data_get_irq_chip_data(d);
+ struct ics_native *in = to_ics_native(ics);
+
+ pr_devel("ics-native: mask virq %d [hw 0x%x]\n", d->irq, vec);
+
+ if (vec < in->ibase || vec >= (in->ibase + in->icount))
+ return;
+ ics_native_do_mask(in, vec);
+}
+
+static int ics_native_set_affinity(struct irq_data *d,
+ const struct cpumask *cpumask,
+ bool force)
+{
+ unsigned int vec = (unsigned int)irqd_to_hwirq(d);
+ struct ics *ics = irq_data_get_irq_chip_data(d);
+ struct ics_native *in = to_ics_native(ics);
+ int server;
+ u32 xive;
+
+ if (vec < in->ibase || vec >= (in->ibase + in->icount))
+ return -EINVAL;
+
+ server = xics_get_irq_server(d->irq, cpumask, 1);
+ if (server == -1) {
+ pr_warn("%s: No online cpus in the mask %*pb for irq %d\n",
+ __func__, cpumask_pr_args(cpumask), d->irq);
+ return -1;
+ }
+
+ xive = in_be32(ics_native_xive(in, vec));
+ xive = (xive & 0xff) | (server << 8);
+ out_be32(ics_native_xive(in, vec), xive);
+
+ return IRQ_SET_MASK_OK;
+}
+
+static struct irq_chip ics_native_irq_chip = {
+ .name = "ICS",
+ .irq_startup = ics_native_startup,
+ .irq_mask = ics_native_mask_irq,
+ .irq_unmask = ics_native_unmask_irq,
+ .irq_eoi = NULL, /* Patched at init time */
+ .irq_set_affinity = ics_native_set_affinity,
+ .irq_set_type = xics_set_irq_type,
+ .irq_retrigger = xics_retrigger,
+};
+
+static int ics_native_map(struct ics *ics, unsigned int virq)
+{
+ unsigned int vec = (unsigned int)virq_to_hw(virq);
+ struct ics_native *in = to_ics_native(ics);
+
+ pr_devel("%s: vec=0x%x\n", __func__, vec);
+
+ if (vec < in->ibase || vec >= (in->ibase + in->icount))
+ return -EINVAL;
+
+ irq_set_chip_and_handler(virq, &ics_native_irq_chip, handle_fasteoi_irq);
+ irq_set_chip_data(virq, ics);
+
+ return 0;
+}
+
+static void ics_native_mask_unknown(struct ics *ics, unsigned long vec)
+{
+ struct ics_native *in = to_ics_native(ics);
+
+ if (vec < in->ibase || vec >= (in->ibase + in->icount))
+ return;
+
+ ics_native_do_mask(in, vec);
+}
+
+static long ics_native_get_server(struct ics *ics, unsigned long vec)
+{
+ struct ics_native *in = to_ics_native(ics);
+ u32 xive;
+
+ if (vec < in->ibase || vec >= (in->ibase + in->icount))
+ return -EINVAL;
+
+ xive = in_be32(ics_native_xive(in, vec));
+ return (xive >> 8) & 0xfff;
+}
+
+static int ics_native_host_match(struct ics *ics, struct device_node *node)
+{
+ struct ics_native *in = to_ics_native(ics);
+
+ return in->node == node;
+}
+
+static struct ics ics_native_template = {
+ .map = ics_native_map,
+ .mask_unknown = ics_native_mask_unknown,
+ .get_server = ics_native_get_server,
+ .host_match = ics_native_host_match,
+};
+
+static int __init ics_native_add_one(struct device_node *np)
+{
+ struct ics_native *ics;
+ u32 ranges[2];
+ int rc, count;
+
+ ics = kzalloc(sizeof(struct ics_native), GFP_KERNEL);
+ if (!ics)
+ return -ENOMEM;
+ ics->node = of_node_get(np);
+ memcpy(&ics->ics, &ics_native_template, sizeof(struct ics));
+
+ ics->base = of_iomap(np, 0);
+ if (!ics->base) {
+ pr_err("Failed to map %pOFP\n", np);
+ rc = -ENOMEM;
+ goto fail;
+ }
+
+ count = of_property_count_u32_elems(np, "interrupt-ranges");
+ if (count < 2 || count & 1) {
+ pr_err("Failed to read interrupt-ranges of %pOFP\n", np);
+ rc = -EINVAL;
+ goto fail;
+ }
+ if (count > 2) {
+ pr_warn("ICS %pOFP has %d ranges, only one supported\n",
+ np, count >> 1);
+ }
+ rc = of_property_read_u32_array(np, "interrupt-ranges",
+ ranges, 2);
+ if (rc) {
+ pr_err("Failed to read interrupt-ranges of %pOFP\n", np);
+ goto fail;
+ }
+ ics->ibase = ranges[0];
+ ics->icount = ranges[1];
+
+ pr_info("ICS native initialized for sources %d..%d\n",
+ ics->ibase, ics->ibase + ics->icount - 1);
+
+ /* Register ourselves */
+ xics_register_ics(&ics->ics);
+
+ return 0;
+fail:
+ of_node_put(ics->node);
+ kfree(ics);
+ return rc;
+}
+
+int __init ics_native_init(void)
+{
+ struct device_node *ics;
+ bool found_one = false;
+
+ /* We need to patch our irq chip's EOI to point to the
+ * right ICP
+ */
+ ics_native_irq_chip.irq_eoi = icp_ops->eoi;
+
+ /* Find native ICS in the device-tree */
+ for_each_compatible_node(ics, NULL, "openpower,xics-sources") {
+ if (ics_native_add_one(ics) == 0)
+ found_one = true;
+ }
+
+ if (found_one)
+ pr_info("ICS native backend registered\n");
+
+ return found_one ? 0 : -ENODEV;
+}
diff --git a/arch/powerpc/sysdev/xics/xics-common.c b/arch/powerpc/sysdev/xics/xics-common.c
index 7e4305c01bac..de41ab91f793 100644
--- a/arch/powerpc/sysdev/xics/xics-common.c
+++ b/arch/powerpc/sysdev/xics/xics-common.c
@@ -476,6 +476,8 @@ void __init xics_init(void)
rc = ics_rtas_init();
if (rc < 0)
rc = ics_opal_init();
+ if (rc < 0)
+ rc = ics_native_init();
if (rc < 0)
pr_warn("XICS: Cannot find a Source Controller !\n");
--
2.31.1
^ permalink raw reply related
* [PATCH 11/11] powerpc/microwatt: Disable interrupts in boot wrapper main program
From: Paul Mackerras @ 2021-06-14 23:05 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <YMfeswgEHeXSLOUF@thinks.paulus.ozlabs.org>
This ensures that we don't get a decrementer interrupt arriving before
we have set up a handler for it.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/boot/microwatt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/boot/microwatt.c b/arch/powerpc/boot/microwatt.c
index ac922dd0aa4d..86a07bceaadf 100644
--- a/arch/powerpc/boot/microwatt.c
+++ b/arch/powerpc/boot/microwatt.c
@@ -12,6 +12,7 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
{
unsigned long heapsize = 16*1024*1024 - (unsigned long)_end;
+ __asm__ volatile("mtmsrd %0,1" : : "r" (0));
simple_alloc_init(_end, heapsize, 32, 64);
fdt_init(_dtb_start);
serial_console_init();
--
2.31.1
^ permalink raw reply related
* Re: [PATCH v5 16/17] crypto/nx: Get NX capabilities for GZIP coprocessor type
From: Haren Myneni @ 2021-06-15 0:01 UTC (permalink / raw)
To: Nicholas Piggin, herbert, linux-crypto, linuxppc-dev, mpe
In-Reply-To: <1623641787.0rdwnv3k4u.astroid@bobo.none>
On Mon, 2021-06-14 at 13:39 +1000, Nicholas Piggin wrote:
> Excerpts from Haren Myneni's message of June 13, 2021 9:04 pm:
> > The hypervisor provides different capabilities that it supports
> > to define the user space NX request. These capabilities are
> > recommended minimum compression / decompression lengths and the
> > maximum request buffer size in bytes.
> >
> > Changes to get NX overall capabilities which points to the
> > specific features that the hypervisor supports. Then retrieve
> > the capabilities for the specific feature (available only
> > for NXGZIP).
>
> So what does this give you which you didn't have before? Should
> this go before the previous patch that enables the interface for
> guests,
> or is there some functional-yet-degraded mode that is available
> without
> this patch?
>
> I would suggest even if this is the case to switch ordering of the
> patches so as to reduce the matrix of functionality that userspace
> sees
> when bisecting. Unless you specifically want this kind of
> bisectability,
> in which case make that explicit in the changelog.
Thanks for your suggestions. I will incorporate them and post next
revision.
The user space request buffer length should not be more than
req_max_processed_len (available through sysfs). Otherwise NX will
return the request with RMA_Reject. Whereasas min_compress_len and
min_decompress_len are recommended values.
We can add this patch and the last one (crypto/nx: Add sysfs interface
to export NX capabilities) before the actual enablement ("crypto/nx:
Register and unregisterVAS interface on PowerVM""
Thanks
Haren
>
> Thanks,
> Nick
>
> > Signed-off-by: Haren Myneni <haren@linux.ibm.com>
> > Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
> > ---
> > drivers/crypto/nx/nx-common-pseries.c | 86
> > +++++++++++++++++++++++++++
> > 1 file changed, 86 insertions(+)
> >
> > diff --git a/drivers/crypto/nx/nx-common-pseries.c
> > b/drivers/crypto/nx/nx-common-pseries.c
> > index 9a40fca8a9e6..60b5049ec9f7 100644
> > --- a/drivers/crypto/nx/nx-common-pseries.c
> > +++ b/drivers/crypto/nx/nx-common-pseries.c
> > @@ -9,6 +9,7 @@
> > */
> >
> > #include <asm/vio.h>
> > +#include <asm/hvcall.h>
> > #include <asm/vas.h>
> >
> > #include "nx-842.h"
> > @@ -20,6 +21,29 @@ MODULE_DESCRIPTION("842 H/W Compression driver
> > for IBM Power processors");
> > MODULE_ALIAS_CRYPTO("842");
> > MODULE_ALIAS_CRYPTO("842-nx");
> >
> > +/*
> > + * Coprocessor type specific capabilities from the hypervisor.
> > + */
> > +struct hv_nx_ct_caps {
> > + __be64 descriptor;
> > + __be64 req_max_processed_len; /* Max bytes in one GZIP
> > request */
> > + __be64 min_compress_len; /* Min compression size in
> > bytes */
> > + __be64 min_decompress_len; /* Min decompression size
> > in bytes */
> > +} __packed __aligned(0x1000);
> > +
> > +/*
> > + * Coprocessor type specific capabilities.
> > + */
> > +struct nx_ct_caps {
> > + u64 descriptor;
> > + u64 req_max_processed_len; /* Max bytes in one GZIP request */
> > + u64 min_compress_len; /* Min compression in bytes */
> > + u64 min_decompress_len; /* Min decompression in bytes */
> > +};
> > +
> > +static u64 caps_feat;
> > +static struct nx_ct_caps nx_ct_caps;
> > +
> > static struct nx842_constraints nx842_pseries_constraints = {
> > .alignment = DDE_BUFFER_ALIGN,
> > .multiple = DDE_BUFFER_LAST_MULT,
> > @@ -1066,6 +1090,64 @@ static void nx842_remove(struct vio_dev
> > *viodev)
> > kfree(old_devdata);
> > }
> >
> > +/*
> > + * Get NX capabilities from the hypervisor.
> > + * Only NXGZIP capabilities are provided by the hypersvisor right
> > + * now and these values are available to user space with sysfs.
> > + */
> > +static void __init nxct_get_capabilities(void)
> > +{
> > + struct hv_vas_all_caps *hv_caps;
> > + struct hv_nx_ct_caps *hv_nxc;
> > + int rc;
> > +
> > + hv_caps = kmalloc(sizeof(*hv_caps), GFP_KERNEL);
> > + if (!hv_caps)
> > + return;
> > + /*
> > + * Get NX overall capabilities with feature type=0
> > + */
> > + rc = h_query_vas_capabilities(H_QUERY_NX_CAPABILITIES, 0,
> > + (u64)virt_to_phys(hv_caps));
> > + if (rc)
> > + goto out;
> > +
> > + caps_feat = be64_to_cpu(hv_caps->feat_type);
> > + /*
> > + * NX-GZIP feature available
> > + */
> > + if (caps_feat & VAS_NX_GZIP_FEAT_BIT) {
> > + hv_nxc = kmalloc(sizeof(*hv_nxc), GFP_KERNEL);
> > + if (!hv_nxc)
> > + goto out;
> > + /*
> > + * Get capabilities for NX-GZIP feature
> > + */
> > + rc = h_query_vas_capabilities(H_QUERY_NX_CAPABILITIES,
> > + VAS_NX_GZIP_FEAT,
> > + (u64)virt_to_phys(hv_
> > nxc));
> > + } else {
> > + pr_err("NX-GZIP feature is not available\n");
> > + rc = -EINVAL;
> > + }
> > +
> > + if (!rc) {
> > + nx_ct_caps.descriptor = be64_to_cpu(hv_nxc-
> > >descriptor);
> > + nx_ct_caps.req_max_processed_len =
> > + be64_to_cpu(hv_nxc-
> > >req_max_processed_len);
> > + nx_ct_caps.min_compress_len =
> > + be64_to_cpu(hv_nxc->min_compress_len);
> > + nx_ct_caps.min_decompress_len =
> > + be64_to_cpu(hv_nxc-
> > >min_decompress_len);
> > + } else {
> > + caps_feat = 0;
> > + }
> > +
> > + kfree(hv_nxc);
> > +out:
> > + kfree(hv_caps);
> > +}
> > +
> > static const struct vio_device_id nx842_vio_driver_ids[] = {
> > {"ibm,compression-v1", "ibm,compression"},
> > {"", ""},
> > @@ -1093,6 +1175,10 @@ static int __init nx842_pseries_init(void)
> > return -ENOMEM;
> >
> > RCU_INIT_POINTER(devdata, new_devdata);
> > + /*
> > + * Get NX capabilities from the hypervisor.
> > + */
> > + nxct_get_capabilities();
> >
> > ret = vio_register_driver(&nx842_vio_driver);
> > if (ret) {
> > --
> > 2.18.2
> >
> >
> >
^ permalink raw reply
* Re: [PATCH v4 2/4] lazy tlb: allow lazy tlb mm refcounting to be configurable
From: Nicholas Piggin @ 2021-06-15 0:55 UTC (permalink / raw)
To: Andrew Morton, Andy Lutomirski
Cc: linux-arch, Rik van Riel, Linus Torvalds, Randy Dunlap,
linux-kernel, linux-mm, linuxppc-dev
In-Reply-To: <aecf5bc8-9018-c021-287d-6a975b7a6235@kernel.org>
Excerpts from Andy Lutomirski's message of June 15, 2021 2:20 am:
> Replying to several emails at once...
>
>
> On 6/13/21 10:21 PM, Nicholas Piggin wrote:
>> Excerpts from Nicholas Piggin's message of June 14, 2021 2:47 pm:
>>> Excerpts from Nicholas Piggin's message of June 14, 2021 2:14 pm:
>>>> Excerpts from Andy Lutomirski's message of June 14, 2021 1:52 pm:
>>>>> On 6/13/21 5:45 PM, Nicholas Piggin wrote:
>>>>>> Excerpts from Andy Lutomirski's message of June 9, 2021 2:20 am:
>>>>>>> On 6/4/21 6:42 PM, Nicholas Piggin wrote:
>>>>>>>> Add CONFIG_MMU_TLB_REFCOUNT which enables refcounting of the lazy tlb mm
>>>>>>>> when it is context switched. This can be disabled by architectures that
>>>>>>>> don't require this refcounting if they clean up lazy tlb mms when the
>>>>>>>> last refcount is dropped. Currently this is always enabled, which is
>>>>>>>> what existing code does, so the patch is effectively a no-op.
>>>>>>>>
>>>>>>>> Rename rq->prev_mm to rq->prev_lazy_mm, because that's what it is.
>>>>>>>
>>>>>>> I am in favor of this approach, but I would be a lot more comfortable
>>>>>>> with the resulting code if task->active_mm were at least better
>>>>>>> documented and possibly even guarded by ifdefs.
>>>>>>
>>>>>> active_mm is fairly well documented in Documentation/active_mm.rst IMO.
>>>>>> I don't think anything has changed in 20 years, I don't know what more
>>>>>> is needed, but if you can add to documentation that would be nice. Maybe
>>>>>> moving a bit of that into .c and .h files?
>>>>>>
>>>>>
>>>>> Quoting from that file:
>>>>>
>>>>> - however, we obviously need to keep track of which address space we
>>>>> "stole" for such an anonymous user. For that, we have "tsk->active_mm",
>>>>> which shows what the currently active address space is.
>>>>>
>>>>> This isn't even true right now on x86.
>>>>
>>>> From the perspective of core code, it is. x86 might do something crazy
>>>> with it, but it has to make it appear this way to non-arch code that
>>>> uses active_mm.
>>>>
>>>> Is x86's scheme documented?
>
> arch/x86/include/asm/tlbflush.h documents it a bit:
>
> /*
> * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
> * are on. This means that it may not match current->active_mm,
> * which will contain the previous user mm when we're in lazy TLB
> * mode even if we've already switched back to swapper_pg_dir.
> *
> * During switch_mm_irqs_off(), loaded_mm will be set to
> * LOADED_MM_SWITCHING during the brief interrupts-off window
> * when CR3 and loaded_mm would otherwise be inconsistent. This
> * is for nmi_uaccess_okay()'s benefit.
> */
So the only documentation relating to the current active_mm value or
refcounting is that it may not match what the x86 specific code is
doing?
All this complexity you accuse me of adding is entirely in x86 code.
On other architectures, it's very simple and understandable, and
documented. I don't know how else to explain this.
>>>>
>>>>> With your patch applied:
>>>>>
>>>>> To support all that, the "struct mm_struct" now has two counters: a
>>>>> "mm_users" counter that is how many "real address space users" there are,
>>>>> and a "mm_count" counter that is the number of "lazy" users (ie anonymous
>>>>> users) plus one if there are any real users.
>>>>>
>>>>> isn't even true any more.
>>>>
>>>> Well yeah but the active_mm concept hasn't changed. The refcounting
>>>> change is hopefully reasonably documented?
>
> active_mm is *only* refcounting in the core code. See below.
It's just not. It's passed in to switch_mm. Most architectures except
for x86 require this.
>>>>>
>>>>> I looked through all active_mm references in core code. We have:
>>>>>
>>>>> kernel/sched/core.c: it's all refcounting, although it's a bit tangled
>>>>> with membarrier.
>>>>>
>>>>> kernel/kthread.c: same. refcounting and membarrier stuff.
>>>>>
>>>>> kernel/exit.c: exit_mm() a BUG_ON().
>>>>>
>>>>> kernel/fork.c: initialization code and a warning.
>>>>>
>>>>> kernel/cpu.c: cpu offline stuff. wouldn't be needed if active_mm went away.
>>>>>
>>>>> fs/exec.c: nothing of interest
>>>>
>>>> I might not have been clear. Core code doesn't need active_mm if
>>>> active_mm somehow goes away. I'm saying active_mm can't go away because
>>>> it's needed to support (most) archs that do lazy tlb mm switching.
>>>>
>>>> The part I don't understand is when you say it can just go away. How?
>
> #ifdef CONFIG_MMU_TLB_REFCOUNT
> struct mm_struct *active_mm;
> #endif
Thanks for returning the snark.
>>>>
>>>>> I didn't go through drivers, but I maintain my point. active_mm is
>>>>> there for refcounting. So please don't just make it even more confusing
>>>>> -- do your performance improvement, but improve the code at the same
>>>>> time: get rid of active_mm, at least on architectures that opt out of
>>>>> the refcounting.
>>>>
>>>> powerpc opts out of the refcounting and can not "get rid of active_mm".
>>>> Not even in theory.
>>>
>>> That is to say, it does do a type of reference management that requires
>>> active_mm so you can argue it has not entirely opted out of refcounting.
>>> But we're not just doing refcounting for the sake of refcounting! That
>>> would make no sense.
>>>
>>> active_mm is required because that's the mm that we have switched to
>>> (from core code's perspective), and it is integral to know when to
>>> switch to a different mm. See how active_mm is a fundamental concept
>>> in core code? It's part of the contract between core code and the
>>> arch mm context management calls. reference counting follows from there
>>> but it's not the _reason_ for this code.
>
> I don't understand what contract you're talking about. The core code
> maintains an active_mm counter and keeps that mm_struct from
> disappearing. That's *it*. The core code does not care that active_mm
> is active, and x86 provides evidence of that -- on x86,
> current->active_mm may well be completely unused.
I already acknowledged archs can do their own thing under the covers if
they want.
>
>>>
>>> Pretend the reference problem does not exit (whether by refcounting or
>>> shootdown or garbage collection or whatever). We still can't remove
>>> active_mm! We need it to know how to call into arch functions like
>>> switch_mm.
>
> static inline void do_switch_mm(struct task_struct *prev_task, ...)
> {
> #ifdef CONFIG_MMU_TLB_REFCOUNT
> switch_mm(...);
> #else
> switch_mm(fewer parameters);
> /* or pass NULL or whatever. */
> #endif
> }
And prev_task comes from active_mm, ergo core code requires the concept
of active_mm.
I already said I'm quite happy for wrappers to be added so those can
compile out of an arch like x86. That's not doing anything for
complexity of core code, because it still needs to maintain the active
mm wrappers.
>>> I don't know if you just forgot that critical requirement in your above
>>> list, or you actually are entirely using x86's mental model for this
>>> code which is doing something entirely different that does not need it
>>> at all. If that is the case I really don't mind some cleanup or wrapper
>>> functions for x86 do entirely do its own thing, but if that's the case
>>> you can't criticize core code's use of active_mm due to the current
>>> state of x86. It's x86 that needs documentation and cleaning up.
>>
>> Ah, that must be where your confusion is coming from: x86's switch_mm
>> doesn't use prev anywhere, and the reference scheme it is using appears
>> to be under-documented, although vague references in changelogs suggest
>> it has not actually "opted out" of active_mm refcounting.
>
> All of this is true, except I don't believe I'm confused.
Well someone is. My patches don't change any of the fundamental
complexity of core code's maintaining of active_mm, nor alleviate the
requirement to keep active_mm around under the new config introduced,
and yet you are saying:
I am in favor of this approach, but I would be a lot more comfortable
with the resulting code if task->active_mm were at least better
documented and possibly even guarded by ifdefs.
It doesn't make sense. It can't be guarded by ifdefs even if we took
away the shootdown IPI's use of it as part of reference / lifetime
management.
And that you don't like the state of the code but I'm trying to wrangle
specifics out of you on that and it's difficult.
>>
>> That's understandable, but please redirect your objections to the proper
>> place. git blame suggests 3d28ebceaffab.
>
> Thanks for the snark.
Is it not true? I don't mean that one patch causing all the x86
complexity or even making the situation worse itself. But you seem to be
asking my series to do things that really apply to the x86 changes over
the past few years that got us here.
>
> Here's the situation.
>
> Before that patch, x86 more or less fully used the core scheme. With
> that patch, x86 has the property that loaded_mm (which is used) either
> points to init_mm (which is permanently live) or to active_mm (which the
> core code keeps alive, which is the whole point). x86 still uses the
> core active_mm refcounting scheme. The result is a bit overcomplicated,
> but it works, and it enabled massive improvements to the x86 arch code.
>
> You are proposing a whole new simplification in which an arch can opt in
> to telling the core code that it doesn't need to keep active_mm alive.
> Great! But now it's possible to get quite confused -- either an
> elaborate dance is needed or current->active_mm could point to freed
> memory. This is poor design.
powerpc still needs active_mm, there's zero point to configuring it away
and maintaining exactly the same thing in a per-cpu variable in the arch
code because the code has to be there in the core for all other archs
anyway so that would be stupid.
I would be more than happy to try help review a patch that helps the
x86 situation, but my patch is not intended to do what x86 code wants.
> I'm entirely in favor of allowing arches to opt out of active_mm
> refcounting. As you've noticed, it's quite expensive on large systems.
> x86 would opt out, too, if given the opportunity [1]. But I think you
> should do it right. If an arch opts out of active_mm refcounting, then
> keeping a lazy mm (if any!) alive becomes entirely the arch code's
> responsibility.
>
> Once that happens, task->active_mm is not just a waste
> of 4-8 bytes of memory per task, it's actively harmful -- some code,
> somewhere in the kernel, might dereference it and access freed memory!
That's not an accurate description of my patches. powerpc still requires
active_mm exactly the same, and the "elaborate dance" amounts to having
CPUs stop using the mm as a lazy tlb when the last user goes away.
>
> So please do your patches right. By all means add a new config option,
> but make that config option make active_mm go away entirely. Then it
> can't be misused.
I already have a patch that's halfway there I pulled out of the series
for the last submission. As I said, feel free to build on it.
>
> NAK to the current set.
I propose instead we do take the series, and write some patches on top
of that which helps x86. Here's 1/n
2/n is to make wrappers for active_mm maintenance in core code.
3/n is adjust context_switch_nolazy() to just use init_mm (or NULL) directly
and put ifdefs around active_mm.
Is that what x86 wants?
Thanks,
Nick
commit 99f90520821b9717d4447872354c2933894a1100
Author: Nicholas Piggin <npiggin@gmail.com>
Date: Thu Jul 9 15:01:25 2020 +1000
lazy tlb: allow lazy tlb mm switching to be configurable
Add CONFIG_MMU_LAZY_TLB which can be configured out to disable the lazy
tlb mechanism entirely, and switches to init_mm when switching to a
kernel thread.
NOMMU systems could easily go without this and save a bit of code and
the refcount atomics, because their mm switch is a no-op. They have not
been switched over by default because the arch code needs to be audited
and tested for lazy tlb mm refcounting and converted to _lazy_tlb
refcounting if necessary.
CONFIG_MMU_LAZY_TLB_REFCOUNT is also added, but it must always be
enabled if CONFIG_MMU_LAZY_TLB is enabled until the next patch which
provides an alternate scheme.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
diff --git a/arch/Kconfig b/arch/Kconfig
index cf468c9777d8..3b80042bd0c2 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -418,6 +418,26 @@ config ARCH_WANT_IRQS_OFF_ACTIVATE_MM
irqs disabled over activate_mm. Architectures that do IPI based TLB
shootdowns should enable this.
+# Enable "lazy TLB", which means a user->kernel thread context switch does not
+# switch the mm to init_mm and the kernel thread takes a reference to the user
+# mm to provide its kernel mapping. This is how Linux has traditionally worked
+# (see Documentation/vm/active_mm.rst), for performance. Switching to and from
+# idle thread is a performance-critical case.
+#
+# If mm context switches are inexpensive or free (in the case of NOMMU) then
+# this could be disabled.
+#
+# It would make sense to have this depend on MMU, but need to audit and test
+# the NOMMU architectures for lazy mm refcounting first.
+config MMU_LAZY_TLB
+ def_bool y
+ depends on !NO_MMU_LAZY_TLB
+
+# This allows archs to disable MMU_LAZY_TLB. mmgrab/mmdrop in arch/ code has
+# to be audited and switched to _lazy_tlb postfix as necessary.
+config NO_MMU_LAZY_TLB
+ def_bool n
+
# Use normal mm refcounting for MMU_LAZY_TLB kernel thread references.
# MMU_LAZY_TLB_REFCOUNT=n can improve the scalability of context switching
# to/from kernel threads when the same mm is running on a lot of CPUs (a large
@@ -431,6 +451,7 @@ config ARCH_WANT_IRQS_OFF_ACTIVATE_MM
# to a kthread ->active_mm (non-arch code has been converted already).
config MMU_LAZY_TLB_REFCOUNT
def_bool y
+ depends on MMU_LAZY_TLB
depends on !MMU_LAZY_TLB_SHOOTDOWN
# This option allows MMU_LAZY_TLB_REFCOUNT=n. It ensures no CPUs are using an
@@ -445,6 +466,7 @@ config MMU_LAZY_TLB_REFCOUNT
# MMU_LAZY_TLB_REFCOUNT=n (see above).
config MMU_LAZY_TLB_SHOOTDOWN
bool
+ depends on MMU_LAZY_TLB
config ARCH_HAVE_NMI_SAFE_CMPXCHG
bool
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index 5e10cb712be3..5cb039c686a6 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -4285,22 +4285,10 @@ asmlinkage __visible void schedule_tail(struct task_struct *prev)
calculate_sigpending();
}
-/*
- * context_switch - switch to the new MM and the new thread's register state.
- */
-static __always_inline struct rq *
-context_switch(struct rq *rq, struct task_struct *prev,
- struct task_struct *next, struct rq_flags *rf)
+static __always_inline void
+context_switch_mm(struct rq *rq, struct task_struct *prev,
+ struct task_struct *next)
{
- prepare_task_switch(rq, prev, next);
-
- /*
- * For paravirt, this is coupled with an exit in switch_to to
- * combine the page table reload and the switch backend into
- * one hypercall.
- */
- arch_start_context_switch(prev);
-
/*
* kernel -> kernel lazy + transfer active
* user -> kernel lazy + mmgrab_lazy_tlb() active
@@ -4345,6 +4333,40 @@ context_switch(struct rq *rq, struct task_struct *prev,
#endif
}
}
+}
+
+static __always_inline void
+context_switch_mm_nolazy(struct rq *rq, struct task_struct *prev,
+ struct task_struct *next)
+{
+ if (!next->mm)
+ next->active_mm = &init_mm;
+ membarrier_switch_mm(rq, prev->active_mm, next->active_mm);
+ switch_mm_irqs_off(prev->active_mm, next->active_mm, next);
+ if (!prev->mm)
+ prev->active_mm = NULL;
+}
+
+/*
+ * context_switch - switch to the new MM and the new thread's register state.
+ */
+static __always_inline struct rq *
+context_switch(struct rq *rq, struct task_struct *prev,
+ struct task_struct *next, struct rq_flags *rf)
+{
+ prepare_task_switch(rq, prev, next);
+
+ /*
+ * For paravirt, this is coupled with an exit in switch_to to
+ * combine the page table reload and the switch backend into
+ * one hypercall.
+ */
+ arch_start_context_switch(prev);
+
+ if (IS_ENABLED(CONFIG_MMU_LAZY_TLB))
+ context_switch_mm(rq, prev, next);
+ else
+ context_switch_mm_nolazy(rq, prev, next);
rq->clock_update_flags &= ~(RQCF_ACT_SKIP|RQCF_REQ_SKIP);
^ permalink raw reply related
* Re: [PATCH 03/11] powerpc/radix: Add support for microwatt's PRTBL SPR
From: Nicholas Piggin @ 2021-06-15 1:12 UTC (permalink / raw)
To: linuxppc-dev, Paul Mackerras
In-Reply-To: <YMffP+s93uYSaU3J@thinks.paulus.ozlabs.org>
Excerpts from Paul Mackerras's message of June 15, 2021 8:59 am:
> Microwatt currently doesn't implement hypervisor mode and therefore
> doesn't implement the partition table. It does implement the process
> table and radix page table walks.
>
> This adds code to write the base address of the process table to the
> PRTBL SPR,
Is there a particular reason you haven't called it PRTCR or similar to
match PTCR?
> which has been assigned SPR 720 for now, as that is in the
> range of SPR numbers assigned for experimental use. PRTBL is only
> written when we have neither the FW_FEATURE_LPAR feature nor the
> CPU_FTR_HVMODE feature.
Seems like reasonable architecture for a non-HV platform.
Could it have a comment to say it's not architected, and a microwatt
ifdef until that changes?
The patch also does avoid touching LPCR or initing amor...
Thanks,
Nick
>
> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
> ---
> arch/powerpc/include/asm/reg.h | 1 +
> arch/powerpc/mm/book3s64/radix_pgtable.c | 13 +++++++++----
> 2 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index da103e92c112..3200a2522d6c 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -729,6 +729,7 @@
> #endif
> #define SPRN_TIR 0x1BE /* Thread Identification Register */
> #define SPRN_PTCR 0x1D0 /* Partition table control Register */
> +#define SPRN_PRTBL 0x2D0 /* Process table pointer */
> #define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */
> #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
> #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
> diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c b/arch/powerpc/mm/book3s64/radix_pgtable.c
> index 98f0b243c1ab..6595859173a7 100644
> --- a/arch/powerpc/mm/book3s64/radix_pgtable.c
> +++ b/arch/powerpc/mm/book3s64/radix_pgtable.c
> @@ -646,10 +646,15 @@ void __init radix__early_init_mmu(void)
> radix_init_pgtable();
>
> if (!firmware_has_feature(FW_FEATURE_LPAR)) {
> - lpcr = mfspr(SPRN_LPCR);
> - mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
> - radix_init_partition_table();
> - radix_init_amor();
> + if (cpu_has_feature(CPU_FTR_HVMODE)) {
> + lpcr = mfspr(SPRN_LPCR);
> + mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
> + radix_init_partition_table();
> + radix_init_amor();
> + } else {
> + mtspr(SPRN_PRTBL, (__pa(process_tb) |
> + (PRTB_SIZE_SHIFT - 12)));
> + }
> } else {
> radix_init_pseries();
> }
> --
> 2.31.1
>
>
^ permalink raw reply
* Re: [PATCH] powerpc: Fix initrd corruption with relative jump labels
From: Daniel Axtens @ 2021-06-15 1:15 UTC (permalink / raw)
To: Michael Ellerman, linuxppc-dev; +Cc: r.bolshakov, a.kovaleva, groug
In-Reply-To: <20210614131440.312360-1-mpe@ellerman.id.au>
Hi Michael,
> The fix is simply to make the key value relative to the jump_entry
> struct in the ARCH_STATIC_BRANCH macro.
This fixes the boot issues I observed. Thank you very much!!
Tested-by: Daniel Axtens <dja@axtens.net>
Kind regards,
Daniel
^ permalink raw reply
* Re: [PATCH 11/11] powerpc/microwatt: Disable interrupts in boot wrapper main program
From: Nicholas Piggin @ 2021-06-15 1:21 UTC (permalink / raw)
To: linuxppc-dev, Paul Mackerras
In-Reply-To: <YMfgt4ndMrtYwWYY@thinks.paulus.ozlabs.org>
Excerpts from Paul Mackerras's message of June 15, 2021 9:05 am:
> This ensures that we don't get a decrementer interrupt arriving before
> we have set up a handler for it.
Would this be better off merged in the previous patch (maybe with
comment)? Why don't other platform_init()s seem to require this?
Thanks,
Nick
>
> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
> ---
> arch/powerpc/boot/microwatt.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/powerpc/boot/microwatt.c b/arch/powerpc/boot/microwatt.c
> index ac922dd0aa4d..86a07bceaadf 100644
> --- a/arch/powerpc/boot/microwatt.c
> +++ b/arch/powerpc/boot/microwatt.c
> @@ -12,6 +12,7 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
> {
> unsigned long heapsize = 16*1024*1024 - (unsigned long)_end;
>
> + __asm__ volatile("mtmsrd %0,1" : : "r" (0));
> simple_alloc_init(_end, heapsize, 32, 64);
> fdt_init(_dtb_start);
> serial_console_init();
> --
> 2.31.1
>
>
^ permalink raw reply
* [PATCH -next v2 8/9] ASoC: fsl_ssi: Use devm_platform_get_and_ioremap_resource()
From: Yang Yingliang @ 2021-06-15 1:39 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev, alsa-devel; +Cc: broonie, timur
In-Reply-To: <20210615013922.784296-1-yangyingliang@huawei.com>
Use devm_platform_get_and_ioremap_resource() to simplify
code.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
sound/soc/fsl/fsl_ssi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 2b57b60431bb..ecbc1c365d5b 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -1503,8 +1503,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
}
ssi->cpu_dai_drv.name = dev_name(dev);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- iomem = devm_ioremap_resource(dev, res);
+ iomem = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(iomem))
return PTR_ERR(iomem);
ssi->ssi_phys = res->start;
--
2.25.1
^ permalink raw reply related
* [PATCH -next v2 1/9] ASoC: fsl_asrc: Use devm_platform_get_and_ioremap_resource()
From: Yang Yingliang @ 2021-06-15 1:39 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev, alsa-devel; +Cc: broonie, timur
In-Reply-To: <20210615013922.784296-1-yangyingliang@huawei.com>
Use devm_platform_get_and_ioremap_resource() to simplify
code.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
sound/soc/fsl/fsl_asrc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c
index 0e1ad8efebd3..24b41881a68f 100644
--- a/sound/soc/fsl/fsl_asrc.c
+++ b/sound/soc/fsl/fsl_asrc.c
@@ -1035,8 +1035,7 @@ static int fsl_asrc_probe(struct platform_device *pdev)
asrc->private = asrc_priv;
/* Get the addresses and IRQ */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(&pdev->dev, res);
+ regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
--
2.25.1
^ permalink raw reply related
* [PATCH -next v2 7/9] ASoC: fsl_spdif: Use devm_platform_get_and_ioremap_resource()
From: Yang Yingliang @ 2021-06-15 1:39 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev, alsa-devel; +Cc: broonie, timur
In-Reply-To: <20210615013922.784296-1-yangyingliang@huawei.com>
Use devm_platform_get_and_ioremap_resource() to simplify
code.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
sound/soc/fsl/fsl_spdif.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index 2a76714eb8e6..d812a3ff5845 100644
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -1355,8 +1355,7 @@ static int fsl_spdif_probe(struct platform_device *pdev)
spdif_priv->soc->tx_formats;
/* Get the addresses and IRQ */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(&pdev->dev, res);
+ regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
--
2.25.1
^ permalink raw reply related
* [PATCH -next v2 5/9] ASoC: fsl_micfil: Use devm_platform_get_and_ioremap_resource()
From: Yang Yingliang @ 2021-06-15 1:39 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev, alsa-devel; +Cc: broonie, timur
In-Reply-To: <20210615013922.784296-1-yangyingliang@huawei.com>
Use devm_platform_get_and_ioremap_resource() to simplify
code.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
sound/soc/fsl/fsl_micfil.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 3cf789ed6cbe..8c0c75ce9490 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -669,8 +669,7 @@ static int fsl_micfil_probe(struct platform_device *pdev)
}
/* init regmap */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(&pdev->dev, res);
+ regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
--
2.25.1
^ permalink raw reply related
* [PATCH -next v2 4/9] ASoC: fsl_esai: Use devm_platform_get_and_ioremap_resource()
From: Yang Yingliang @ 2021-06-15 1:39 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev, alsa-devel; +Cc: broonie, timur
In-Reply-To: <20210615013922.784296-1-yangyingliang@huawei.com>
Use devm_platform_get_and_ioremap_resource() to simplify
code.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
sound/soc/fsl/fsl_esai.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index f356ae5925af..a961f837cd09 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -969,8 +969,7 @@ static int fsl_esai_probe(struct platform_device *pdev)
esai_priv->soc = of_device_get_match_data(&pdev->dev);
/* Get the addresses and IRQ */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(&pdev->dev, res);
+ regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
--
2.25.1
^ permalink raw reply related
* [PATCH -next v2 0/9] ASoC: fsl: Use devm_platform_get_and_ioremap_resource()
From: Yang Yingliang @ 2021-06-15 1:39 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev, alsa-devel; +Cc: broonie, timur
patch #1 ~ #8:
Use devm_platform_get_and_ioremap_resource()
patch #9
check return value of platform_get_resource_byname()
v2:
change error message in patch #9
Yang Yingliang (9):
ASoC: fsl_asrc: Use devm_platform_get_and_ioremap_resource()
ASoC: fsl_aud2htx: Use devm_platform_get_and_ioremap_resource()
ASoC: fsl_easrc: Use devm_platform_get_and_ioremap_resource()
ASoC: fsl_esai: Use devm_platform_get_and_ioremap_resource()
ASoC: fsl_micfil: Use devm_platform_get_and_ioremap_resource()
ASoC: fsl_sai: Use devm_platform_get_and_ioremap_resource()
ASoC: fsl_spdif: Use devm_platform_get_and_ioremap_resource()
ASoC: fsl_ssi: Use devm_platform_get_and_ioremap_resource()
ASoC: fsl_xcvr: check return value after calling
platform_get_resource_byname()
sound/soc/fsl/fsl_asrc.c | 3 +--
sound/soc/fsl/fsl_aud2htx.c | 3 +--
sound/soc/fsl/fsl_easrc.c | 3 +--
sound/soc/fsl/fsl_esai.c | 3 +--
sound/soc/fsl/fsl_micfil.c | 3 +--
sound/soc/fsl/fsl_sai.c | 3 +--
sound/soc/fsl/fsl_spdif.c | 3 +--
sound/soc/fsl/fsl_ssi.c | 3 +--
sound/soc/fsl/fsl_xcvr.c | 4 ++++
9 files changed, 12 insertions(+), 16 deletions(-)
--
2.25.1
^ permalink raw reply
* [PATCH -next v2 3/9] ASoC: fsl_easrc: Use devm_platform_get_and_ioremap_resource()
From: Yang Yingliang @ 2021-06-15 1:39 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev, alsa-devel; +Cc: broonie, timur
In-Reply-To: <20210615013922.784296-1-yangyingliang@huawei.com>
Use devm_platform_get_and_ioremap_resource() to simplify
code.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
sound/soc/fsl/fsl_easrc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_easrc.c b/sound/soc/fsl/fsl_easrc.c
index b1765c7d3bcd..19c3c3b5939e 100644
--- a/sound/soc/fsl/fsl_easrc.c
+++ b/sound/soc/fsl/fsl_easrc.c
@@ -1887,8 +1887,7 @@ static int fsl_easrc_probe(struct platform_device *pdev)
easrc->private = easrc_priv;
np = dev->of_node;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(dev, res);
+ regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
--
2.25.1
^ permalink raw reply related
* [PATCH -next v2 2/9] ASoC: fsl_aud2htx: Use devm_platform_get_and_ioremap_resource()
From: Yang Yingliang @ 2021-06-15 1:39 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev, alsa-devel; +Cc: broonie, timur
In-Reply-To: <20210615013922.784296-1-yangyingliang@huawei.com>
Use devm_platform_get_and_ioremap_resource() to simplify
code.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
sound/soc/fsl/fsl_aud2htx.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_aud2htx.c b/sound/soc/fsl/fsl_aud2htx.c
index a328697511f7..99ab7f0241cf 100644
--- a/sound/soc/fsl/fsl_aud2htx.c
+++ b/sound/soc/fsl/fsl_aud2htx.c
@@ -196,8 +196,7 @@ static int fsl_aud2htx_probe(struct platform_device *pdev)
aud2htx->pdev = pdev;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(&pdev->dev, res);
+ regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
--
2.25.1
^ permalink raw reply related
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