* Re: [PATCH v4 2/5] dt-bindings: nintendo-otp: Document the Wii and Wii U OTP support
From: Rob Herring @ 2021-08-06 21:07 UTC (permalink / raw)
To: Emmanuel Gil Peyrot
Cc: devicetree, linux-kernel, Rob Herring, Paul Mackerras, Ash Logan,
Srinivas Kandagatla, linuxppc-dev, Jonathan Neuschäfer
In-Reply-To: <20210801073822.12452-3-linkmauve@linkmauve.fr>
On Sun, 01 Aug 2021 09:38:19 +0200, Emmanuel Gil Peyrot wrote:
> Both of these consoles use the exact same two registers, even at the
> same address, but the Wii U has eight banks of 128 bytes memory while
> the Wii only has one, hence the two compatible strings.
>
> Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
> ---
> .../bindings/nvmem/nintendo-otp.yaml | 44 +++++++++++++++++++
> 1 file changed, 44 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/nvmem/nintendo-otp.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v1 32/55] KVM: PPC: Book3S HV P9: Move vcpu register save/restore into functions
From: Fabiano Rosas @ 2021-08-06 20:49 UTC (permalink / raw)
To: Nicholas Piggin, kvm-ppc; +Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20210726035036.739609-33-npiggin@gmail.com>
Nicholas Piggin <npiggin@gmail.com> writes:
> This should be no functional difference but makes the caller easier
> to read.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> arch/powerpc/kvm/book3s_hv.c | 65 +++++++++++++++++++++++-------------
> 1 file changed, 41 insertions(+), 24 deletions(-)
>
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index c2c72875fca9..45211458ac05 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -4062,6 +4062,44 @@ static void store_spr_state(struct kvm_vcpu *vcpu)
> vcpu->arch.ctrl = mfspr(SPRN_CTRLF);
> }
>
> +/* Returns true if current MSR and/or guest MSR may have changed */
> +static bool load_vcpu_state(struct kvm_vcpu *vcpu,
> + struct p9_host_os_sprs *host_os_sprs)
> +{
> + bool ret = false;
> +
> + if (cpu_has_feature(CPU_FTR_TM) ||
> + cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST)) {
> + kvmppc_restore_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
> + ret = true;
> + }
> +
> + load_spr_state(vcpu, host_os_sprs);
> +
> + load_fp_state(&vcpu->arch.fp);
> +#ifdef CONFIG_ALTIVEC
> + load_vr_state(&vcpu->arch.vr);
> +#endif
> + mtspr(SPRN_VRSAVE, vcpu->arch.vrsave);
> +
> + return ret;
> +}
> +
> +static void store_vcpu_state(struct kvm_vcpu *vcpu)
> +{
> + store_spr_state(vcpu);
> +
> + store_fp_state(&vcpu->arch.fp);
> +#ifdef CONFIG_ALTIVEC
> + store_vr_state(&vcpu->arch.vr);
> +#endif
> + vcpu->arch.vrsave = mfspr(SPRN_VRSAVE);
> +
> + if (cpu_has_feature(CPU_FTR_TM) ||
> + cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
> + kvmppc_save_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
> +}
> +
> static void save_p9_host_os_sprs(struct p9_host_os_sprs *host_os_sprs)
> {
> if (!cpu_has_feature(CPU_FTR_ARCH_31))
> @@ -4169,19 +4207,8 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
>
> vcpu_vpa_increment_dispatch(vcpu);
>
> - if (cpu_has_feature(CPU_FTR_TM) ||
> - cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST)) {
> - kvmppc_restore_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
> - msr = mfmsr(); /* TM restore can update msr */
> - }
> -
> - load_spr_state(vcpu, &host_os_sprs);
> -
> - load_fp_state(&vcpu->arch.fp);
> -#ifdef CONFIG_ALTIVEC
> - load_vr_state(&vcpu->arch.vr);
> -#endif
> - mtspr(SPRN_VRSAVE, vcpu->arch.vrsave);
> + if (unlikely(load_vcpu_state(vcpu, &host_os_sprs)))
> + msr = mfmsr(); /* MSR may have been updated */
>
> switch_pmu_to_guest(vcpu, &host_os_sprs);
>
> @@ -4285,17 +4312,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
>
> switch_pmu_to_host(vcpu, &host_os_sprs);
>
> - store_spr_state(vcpu);
> -
> - store_fp_state(&vcpu->arch.fp);
> -#ifdef CONFIG_ALTIVEC
> - store_vr_state(&vcpu->arch.vr);
> -#endif
> - vcpu->arch.vrsave = mfspr(SPRN_VRSAVE);
> -
> - if (cpu_has_feature(CPU_FTR_TM) ||
> - cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
> - kvmppc_save_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
> + store_vcpu_state(vcpu);
>
> vcpu_vpa_increment_dispatch(vcpu);
^ permalink raw reply
* Re: [PATCH v1 31/55] KVM: PPC: Book3S HV P9: Juggle SPR switching around
From: Fabiano Rosas @ 2021-08-06 20:46 UTC (permalink / raw)
To: Nicholas Piggin, kvm-ppc; +Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20210726035036.739609-32-npiggin@gmail.com>
Nicholas Piggin <npiggin@gmail.com> writes:
> This juggles SPR switching on the entry and exit sides to be more
> symmetric, which makes the next refactoring patch possible with no
> functional change.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> arch/powerpc/kvm/book3s_hv.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index 56429b53f4dc..c2c72875fca9 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -4175,7 +4175,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
> msr = mfmsr(); /* TM restore can update msr */
> }
>
> - switch_pmu_to_guest(vcpu, &host_os_sprs);
> + load_spr_state(vcpu, &host_os_sprs);
>
> load_fp_state(&vcpu->arch.fp);
> #ifdef CONFIG_ALTIVEC
> @@ -4183,7 +4183,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
> #endif
> mtspr(SPRN_VRSAVE, vcpu->arch.vrsave);
>
> - load_spr_state(vcpu, &host_os_sprs);
> + switch_pmu_to_guest(vcpu, &host_os_sprs);
>
> if (kvmhv_on_pseries()) {
> /*
> @@ -4283,6 +4283,8 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
> vcpu->arch.slb_max = 0;
> }
>
> + switch_pmu_to_host(vcpu, &host_os_sprs);
> +
> store_spr_state(vcpu);
>
> store_fp_state(&vcpu->arch.fp);
> @@ -4297,8 +4299,6 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
>
> vcpu_vpa_increment_dispatch(vcpu);
>
> - switch_pmu_to_host(vcpu, &host_os_sprs);
> -
> timer_rearm_host_dec(*tb);
>
> restore_p9_host_os_sprs(vcpu, &host_os_sprs);
^ permalink raw reply
* Re: [PATCH v1 30/55] KVM: PPC: Book3S HV P9: Only execute mtSPR if the value changed
From: Fabiano Rosas @ 2021-08-06 20:45 UTC (permalink / raw)
To: Nicholas Piggin, kvm-ppc; +Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20210726035036.739609-31-npiggin@gmail.com>
Nicholas Piggin <npiggin@gmail.com> writes:
> Keep better track of the current SPR value in places where
> they are to be loaded with a new context, to reduce expensive
> mtSPR operations.
>
> -73 cycles (7354) POWER9 virt-mode NULL hcall
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> arch/powerpc/kvm/book3s_hv.c | 64 ++++++++++++++++++++++--------------
> 1 file changed, 39 insertions(+), 25 deletions(-)
>
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index 0d97138e6fa4..56429b53f4dc 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -4009,19 +4009,28 @@ static void switch_pmu_to_host(struct kvm_vcpu *vcpu,
> }
> }
>
> -static void load_spr_state(struct kvm_vcpu *vcpu)
> +static void load_spr_state(struct kvm_vcpu *vcpu,
> + struct p9_host_os_sprs *host_os_sprs)
> {
> - mtspr(SPRN_DSCR, vcpu->arch.dscr);
> - mtspr(SPRN_IAMR, vcpu->arch.iamr);
> - mtspr(SPRN_PSPB, vcpu->arch.pspb);
> - mtspr(SPRN_FSCR, vcpu->arch.fscr);
> mtspr(SPRN_TAR, vcpu->arch.tar);
> mtspr(SPRN_EBBHR, vcpu->arch.ebbhr);
> mtspr(SPRN_EBBRR, vcpu->arch.ebbrr);
> mtspr(SPRN_BESCR, vcpu->arch.bescr);
> - mtspr(SPRN_TIDR, vcpu->arch.tid);
> - mtspr(SPRN_AMR, vcpu->arch.amr);
> - mtspr(SPRN_UAMOR, vcpu->arch.uamor);
> +
> + if (!cpu_has_feature(CPU_FTR_ARCH_31))
> + mtspr(SPRN_TIDR, vcpu->arch.tid);
> + if (host_os_sprs->iamr != vcpu->arch.iamr)
> + mtspr(SPRN_IAMR, vcpu->arch.iamr);
> + if (host_os_sprs->amr != vcpu->arch.amr)
> + mtspr(SPRN_AMR, vcpu->arch.amr);
> + if (vcpu->arch.uamor != 0)
> + mtspr(SPRN_UAMOR, vcpu->arch.uamor);
> + if (host_os_sprs->fscr != vcpu->arch.fscr)
> + mtspr(SPRN_FSCR, vcpu->arch.fscr);
> + if (host_os_sprs->dscr != vcpu->arch.dscr)
> + mtspr(SPRN_DSCR, vcpu->arch.dscr);
> + if (vcpu->arch.pspb != 0)
> + mtspr(SPRN_PSPB, vcpu->arch.pspb);
>
> /*
> * DAR, DSISR, and for nested HV, SPRGs must be set with MSR[RI]
> @@ -4036,28 +4045,31 @@ static void load_spr_state(struct kvm_vcpu *vcpu)
>
> static void store_spr_state(struct kvm_vcpu *vcpu)
> {
> - vcpu->arch.ctrl = mfspr(SPRN_CTRLF);
> -
> - vcpu->arch.iamr = mfspr(SPRN_IAMR);
> - vcpu->arch.pspb = mfspr(SPRN_PSPB);
> - vcpu->arch.fscr = mfspr(SPRN_FSCR);
> vcpu->arch.tar = mfspr(SPRN_TAR);
> vcpu->arch.ebbhr = mfspr(SPRN_EBBHR);
> vcpu->arch.ebbrr = mfspr(SPRN_EBBRR);
> vcpu->arch.bescr = mfspr(SPRN_BESCR);
> - vcpu->arch.tid = mfspr(SPRN_TIDR);
> +
> + if (!cpu_has_feature(CPU_FTR_ARCH_31))
> + vcpu->arch.tid = mfspr(SPRN_TIDR);
> + vcpu->arch.iamr = mfspr(SPRN_IAMR);
> vcpu->arch.amr = mfspr(SPRN_AMR);
> vcpu->arch.uamor = mfspr(SPRN_UAMOR);
> + vcpu->arch.fscr = mfspr(SPRN_FSCR);
> vcpu->arch.dscr = mfspr(SPRN_DSCR);
> + vcpu->arch.pspb = mfspr(SPRN_PSPB);
> +
> + vcpu->arch.ctrl = mfspr(SPRN_CTRLF);
> }
>
> static void save_p9_host_os_sprs(struct p9_host_os_sprs *host_os_sprs)
> {
> - host_os_sprs->dscr = mfspr(SPRN_DSCR);
> - host_os_sprs->tidr = mfspr(SPRN_TIDR);
> + if (!cpu_has_feature(CPU_FTR_ARCH_31))
> + host_os_sprs->tidr = mfspr(SPRN_TIDR);
> host_os_sprs->iamr = mfspr(SPRN_IAMR);
> host_os_sprs->amr = mfspr(SPRN_AMR);
> host_os_sprs->fscr = mfspr(SPRN_FSCR);
> + host_os_sprs->dscr = mfspr(SPRN_DSCR);
> }
>
> /* vcpu guest regs must already be saved */
> @@ -4066,18 +4078,20 @@ static void restore_p9_host_os_sprs(struct kvm_vcpu *vcpu,
> {
> mtspr(SPRN_SPRG_VDSO_WRITE, local_paca->sprg_vdso);
>
> - mtspr(SPRN_PSPB, 0);
> - mtspr(SPRN_UAMOR, 0);
> -
> - mtspr(SPRN_DSCR, host_os_sprs->dscr);
> - mtspr(SPRN_TIDR, host_os_sprs->tidr);
> - mtspr(SPRN_IAMR, host_os_sprs->iamr);
> -
> + if (!cpu_has_feature(CPU_FTR_ARCH_31))
> + mtspr(SPRN_TIDR, host_os_sprs->tidr);
> + if (host_os_sprs->iamr != vcpu->arch.iamr)
> + mtspr(SPRN_IAMR, host_os_sprs->iamr);
> + if (vcpu->arch.uamor != 0)
> + mtspr(SPRN_UAMOR, 0);
> if (host_os_sprs->amr != vcpu->arch.amr)
> mtspr(SPRN_AMR, host_os_sprs->amr);
> -
> if (host_os_sprs->fscr != vcpu->arch.fscr)
> mtspr(SPRN_FSCR, host_os_sprs->fscr);
> + if (host_os_sprs->dscr != vcpu->arch.dscr)
> + mtspr(SPRN_DSCR, host_os_sprs->dscr);
> + if (vcpu->arch.pspb != 0)
> + mtspr(SPRN_PSPB, 0);
>
> /* Save guest CTRL register, set runlatch to 1 */
> if (!(vcpu->arch.ctrl & 1))
> @@ -4169,7 +4183,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
> #endif
> mtspr(SPRN_VRSAVE, vcpu->arch.vrsave);
>
> - load_spr_state(vcpu);
> + load_spr_state(vcpu, &host_os_sprs);
>
> if (kvmhv_on_pseries()) {
> /*
^ permalink raw reply
* Re: [PATCH v2] scripts/Makefile.clang: default to LLVM_IAS=1
From: Nathan Chancellor @ 2021-08-06 19:52 UTC (permalink / raw)
To: Nick Desaulniers
Cc: linux-s390, Michal Marek, Vasily Gorbik, Jonathan Corbet,
Masahiro Yamada, linux-kbuild, linux-doc, Khem Raj,
Matthew Wilcox, linux-kernel, clang-built-linux,
Christian Borntraeger, Albert Ou, Palmer Dabbelt, Paul Walmsley,
linux-riscv, linuxppc-dev, Heiko Carstens
In-Reply-To: <20210806172701.3993843-1-ndesaulniers@google.com>
On Fri, Aug 06, 2021 at 10:27:01AM -0700, Nick Desaulniers wrote:
> LLVM_IAS=1 controls enabling clang's integrated assembler via
> -integrated-as. This was an explicit opt in until we could enable
> assembler support in Clang for more architecures. Now we have support
> and CI coverage of LLVM_IAS=1 for all architecures except a few more
> bugs affecting s390 and powerpc.
The powerpc and s390 folks have been testing with clang, I think they
should have been on CC for this change (done now).
> This commit flips the default from opt in via LLVM_IAS=1 to opt out via
> LLVM_IAS=0. CI systems or developers that were previously doing builds
> with CC=clang or LLVM=1 without explicitly setting LLVM_IAS must now
> explicitly opt out via LLVM_IAS=0, otherwise they will be implicitly
> opted-in.
>
> This finally shortens the command line invocation when cross compiling
> with LLVM to simply:
>
> $ make ARCH=arm64 LLVM=1
>
> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
I am still not really sure how I feel about this. I would prefer not to
break people's builds but I suppose this is inevitabile eventually.
A little support matrix that I drafted up where based on ARCH and clang
version for LLVM_IAS=1 support:
| 10.x | 11.x | 12.x | 13.x | 14.x |
ARCH=arm | NO | NO | NO | YES | YES |
ARCH=arm64 | NO | YES | YES | YES | YES |
ARCH=i386 | YES | YES | YES | YES | YES |
ARCH=mips* | YES | YES | YES | YES | YES |
ARCH=powerpc | NO | NO | NO | NO | NO |
ARCH=s390 | NO | NO | NO | NO | NO |
ARCH=x86_64 | NO | YES | YES | YES | YES |
The main issue that I have with this change is that all of these
architectures work fine with CC=clang and their build commands that used
to work fine will not with this change, as they will have to specify
LLVM_IAS=0. I think that making this change for LLVM=1 makes sense but
changing the default for just CC=clang feels like a bit much at this
point in time. I would love to hear from others on this though, I am not
going to object much further than this.
Regardless of that concern, this patch does what it says so:
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
> ---
> Changes v1 -> v2:
> * Drop "Currently" from Documentation/, as per Matthew.
> * Drop Makefile and riscv Makefile, rebase on
> https://lore.kernel.org/lkml/20210805150102.131008-1-masahiroy@kernel.org/
> as per Masahiro.
> * Base is kbuild/for-next, plus
> https://lore.kernel.org/lkml/20210802183910.1802120-1-ndesaulniers@google.com/
> https://lore.kernel.org/lkml/20210805150102.131008-1-masahiroy@kernel.org/.
>
> Documentation/kbuild/llvm.rst | 14 ++++++++------
> scripts/Makefile.clang | 6 +++---
> 2 files changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/kbuild/llvm.rst b/Documentation/kbuild/llvm.rst
> index f8a360958f4c..e87ed5479963 100644
> --- a/Documentation/kbuild/llvm.rst
> +++ b/Documentation/kbuild/llvm.rst
> @@ -60,17 +60,14 @@ They can be enabled individually. The full list of the parameters: ::
> OBJCOPY=llvm-objcopy OBJDUMP=llvm-objdump READELF=llvm-readelf \
> HOSTCC=clang HOSTCXX=clang++ HOSTAR=llvm-ar HOSTLD=ld.lld
>
> -Currently, the integrated assembler is disabled by default. You can pass
> -``LLVM_IAS=1`` to enable it.
> +The integrated assembler is enabled by default. You can pass ``LLVM_IAS=0`` to
> +disable it.
>
> Omitting CROSS_COMPILE
> ----------------------
>
> As explained above, ``CROSS_COMPILE`` is used to set ``--target=<triple>``.
>
> -Unless ``LLVM_IAS=1`` is specified, ``CROSS_COMPILE`` is also used to derive
> -``--prefix=<path>`` to search for the GNU assembler and linker.
> -
> If ``CROSS_COMPILE`` is not specified, the ``--target=<triple>`` is inferred
> from ``ARCH``.
>
> @@ -78,7 +75,12 @@ That means if you use only LLVM tools, ``CROSS_COMPILE`` becomes unnecessary.
>
> For example, to cross-compile the arm64 kernel::
>
> - make ARCH=arm64 LLVM=1 LLVM_IAS=1
> + make ARCH=arm64 LLVM=1
> +
> +If ``LLVM_IAS=0`` is specified, ``CROSS_COMPILE`` is also used to derive
> +``--prefix=<path>`` to search for the GNU assembler and linker. ::
> +
> + make ARCH=arm64 LLVM=1 LLVM_IAS=0 CROSS_COMPILE=aarch64-linux-gnu-
>
> Supported Architectures
> -----------------------
> diff --git a/scripts/Makefile.clang b/scripts/Makefile.clang
> index 1f4e3eb70f88..3ae63bd35582 100644
> --- a/scripts/Makefile.clang
> +++ b/scripts/Makefile.clang
> @@ -22,12 +22,12 @@ else
> CLANG_FLAGS += --target=$(notdir $(CROSS_COMPILE:%-=%))
> endif # CROSS_COMPILE
>
> -ifeq ($(LLVM_IAS),1)
> -CLANG_FLAGS += -integrated-as
> -else
> +ifeq ($(LLVM_IAS),0)
> CLANG_FLAGS += -no-integrated-as
> GCC_TOOLCHAIN_DIR := $(dir $(shell which $(CROSS_COMPILE)elfedit))
> CLANG_FLAGS += --prefix=$(GCC_TOOLCHAIN_DIR)$(notdir $(CROSS_COMPILE))
> +else
> +CLANG_FLAGS += -integrated-as
> endif
> CLANG_FLAGS += -Werror=unknown-warning-option
> KBUILD_CFLAGS += $(CLANG_FLAGS)
>
> base-commit: d7a86429dbc691bf540688fcc8542cc20246a85b
> prerequisite-patch-id: 0d3072ecb5fd06ff6fd6ea81fe601f6c54c23910
> prerequisite-patch-id: 2654829756eb8a094a0ffad1679caa75a4d86619
> prerequisite-patch-id: a51e7885ca2376d008bbf146a5589da247806f7b
> prerequisite-patch-id: 6a0342755115ec459610657edac1075f069faa3d
> --
> 2.32.0.605.g8dce9f2422-goog
>
^ permalink raw reply
* Re: [PATCH v6 6/6] powerpc/pseries: Consolidate form1 distance initialization into a helper
From: Aneesh Kumar K.V @ 2021-08-06 16:23 UTC (permalink / raw)
To: David Gibson; +Cc: Nathan Lynch, Daniel Henrique Barboza, linuxppc-dev
In-Reply-To: <YQzbCxwfEdE3CQZw@yekko>
On 8/6/21 12:17 PM, David Gibson wrote:
> On Tue, Jul 27, 2021 at 03:33:11PM +0530, Aneesh Kumar K.V wrote:
>> Currently, we duplicate parsing code for ibm,associativity and
>> ibm,associativity-lookup-arrays in the kernel. The associativity array provided
>> by these device tree properties are very similar and hence can use
>> a helper to parse the node id and numa distance details.
>
> Oh... sorry.. comments on the earlier patch were from before I read
> and saw you adjusted things here.
>
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
>> ---
>> arch/powerpc/mm/numa.c | 83 ++++++++++++++++++++++++++----------------
>> 1 file changed, 51 insertions(+), 32 deletions(-)
>>
>> diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
>> index fffb3c40f595..7506251e17f2 100644
>> --- a/arch/powerpc/mm/numa.c
>> +++ b/arch/powerpc/mm/numa.c
>> @@ -171,19 +171,19 @@ static void unmap_cpu_from_node(unsigned long cpu)
>> }
>> #endif /* CONFIG_HOTPLUG_CPU || CONFIG_PPC_SPLPAR */
>>
>> -/*
>> - * Returns nid in the range [0..nr_node_ids], or -1 if no useful NUMA
>> - * info is found.
>> - */
>> -static int associativity_to_nid(const __be32 *associativity)
>> +static int __associativity_to_nid(const __be32 *associativity,
>> + int max_array_sz)
>> {
>> int nid = NUMA_NO_NODE;
>> + /*
>> + * primary_domain_index is 1 based array index.
>> + */
>> + int index = primary_domain_index - 1;
>>
>> - if (!numa_enabled)
>> + if (!numa_enabled || index >= max_array_sz)
>> goto out;
>
> You don't need a goto, you can just return NUMA_NO_NODE.
updated
>
>>
>> - if (of_read_number(associativity, 1) >= primary_domain_index)
>> - nid = of_read_number(&associativity[primary_domain_index], 1);
>> + nid = of_read_number(&associativity[index], 1);
>>
>> /* POWER4 LPAR uses 0xffff as invalid node */
>> if (nid == 0xffff || nid >= nr_node_ids)
>> @@ -191,6 +191,17 @@ static int associativity_to_nid(const __be32 *associativity)
>> out:
>> return nid;
>> }
>> +/*
>> + * Returns nid in the range [0..nr_node_ids], or -1 if no useful NUMA
>> + * info is found.
>> + */
>> +static int associativity_to_nid(const __be32 *associativity)
>> +{
>> + int array_sz = of_read_number(associativity, 1);
>> +
>> + /* Skip the first element in the associativity array */
>> + return __associativity_to_nid((associativity + 1), array_sz);
>> +}
>>
>> static int __cpu_form2_relative_distance(__be32 *cpu1_assoc, __be32 *cpu2_assoc)
>> {
>> @@ -295,24 +306,41 @@ int of_node_to_nid(struct device_node *device)
>> }
>> EXPORT_SYMBOL(of_node_to_nid);
>>
>> -static void __initialize_form1_numa_distance(const __be32 *associativity)
>> +static void ___initialize_form1_numa_distance(const __be32 *associativity,
>> + int max_array_sz)
>> {
>> int i, nid;
>>
>> if (affinity_form != FORM1_AFFINITY)
>> return;
>>
>> - nid = associativity_to_nid(associativity);
>> + nid = __associativity_to_nid(associativity, max_array_sz);
>> if (nid != NUMA_NO_NODE) {
>> for (i = 0; i < distance_ref_points_depth; i++) {
>> const __be32 *entry;
>> + int index = be32_to_cpu(distance_ref_points[i]) - 1;
>> +
>> + /*
>> + * broken hierarchy, return with broken distance table
>
> WARN_ON, maybe?
updated
>
>> + */
>> + if (index >= max_array_sz)
>> + return;
>>
>> - entry = &associativity[be32_to_cpu(distance_ref_points[i])];
>> + entry = &associativity[index];
>> distance_lookup_table[nid][i] = of_read_number(entry, 1);
>> }
>> }
>> }
>>
>> +static void __initialize_form1_numa_distance(const __be32 *associativity)
>
> Do you actually use this in-between wrapper?
yes used in
static void initialize_form1_numa_distance(struct device_node *node)
{
const __be32 *associativity;
associativity = of_get_associativity(node);
if (!associativity)
return;
__initialize_form1_numa_distance(associativity);
}
>
>> +{
>> + int array_sz;
>> +
>> + array_sz = of_read_number(associativity, 1);
>> + /* Skip the first element in the associativity array */
>> + ___initialize_form1_numa_distance(associativity + 1, array_sz);
>> +}
>> +
>> static void initialize_form1_numa_distance(struct device_node *node)
>> {
>> const __be32 *associativity;
>> @@ -586,27 +614,18 @@ static int get_nid_and_numa_distance(struct drmem_lmb *lmb)
>>
>> if (primary_domain_index <= aa.array_sz &&
>> !(lmb->flags & DRCONF_MEM_AI_INVALID) && lmb->aa_index < aa.n_arrays) {
>> - index = lmb->aa_index * aa.array_sz + primary_domain_index - 1;
>> - nid = of_read_number(&aa.arrays[index], 1);
>> + const __be32 *associativity;
>>
>> - if (nid == 0xffff || nid >= nr_node_ids)
>> - nid = default_nid;
>> + index = lmb->aa_index * aa.array_sz;
>> + associativity = &aa.arrays[index];
>> + nid = __associativity_to_nid(associativity, aa.array_sz);
>> if (nid > 0 && affinity_form == FORM1_AFFINITY) {
>> - int i;
>> - const __be32 *associativity;
>> -
>> - index = lmb->aa_index * aa.array_sz;
>> - associativity = &aa.arrays[index];
>> /*
>> - * lookup array associativity entries have different format
>> - * There is no length of the array as the first element.
>> + * lookup array associativity entries have
>> + * no length of the array as the first element.
>> */
>> - for (i = 0; i < distance_ref_points_depth; i++) {
>> - const __be32 *entry;
>> -
>> - entry = &associativity[be32_to_cpu(distance_ref_points[i]) - 1];
>> - distance_lookup_table[nid][i] = of_read_number(entry, 1);
>> - }
>> + ___initialize_form1_numa_distance(associativity,
>> + aa.array_sz);
>
> Better, thanks.
>
>> }
>> }
>> return nid;
>> @@ -632,11 +651,11 @@ int of_drconf_to_nid_single(struct drmem_lmb *lmb)
>>
>> if (primary_domain_index <= aa.array_sz &&
>> !(lmb->flags & DRCONF_MEM_AI_INVALID) && lmb->aa_index < aa.n_arrays) {
>> - index = lmb->aa_index * aa.array_sz + primary_domain_index - 1;
>> - nid = of_read_number(&aa.arrays[index], 1);
>> + const __be32 *associativity;
>>
>> - if (nid == 0xffff || nid >= nr_node_ids)
>> - nid = default_nid;
>> + index = lmb->aa_index * aa.array_sz;
>> + associativity = &aa.arrays[index];
>> + nid = __associativity_to_nid(associativity, aa.array_sz);
>> }
>> return nid;
>> }
>
-aneesh
^ permalink raw reply
* Re: [PATCH kernel v2] KVM: PPC: Use arch_get_random_seed_long instead of powernv variant
From: Fabiano Rosas @ 2021-08-06 14:53 UTC (permalink / raw)
To: Alexey Kardashevskiy, linuxppc-dev; +Cc: Alexey Kardashevskiy, kvm, kvm-ppc
In-Reply-To: <20210805075649.2086567-1-aik@ozlabs.ru>
Alexey Kardashevskiy <aik@ozlabs.ru> writes:
> The powernv_get_random_long() does not work in nested KVM (which is
> pseries) and produces a crash when accessing in_be64(rng->regs) in
> powernv_get_random_long().
>
> This replaces powernv_get_random_long with the ppc_md machine hook
> wrapper.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
>
> Changes:
> v2:
> * replaces [PATCH kernel] powerpc/powernv: Check if powernv_rng is initialized
>
> ---
> arch/powerpc/kvm/book3s_hv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index be0cde26f156..ecfd133e0ca8 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -1165,7 +1165,7 @@ int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
> break;
> #endif
> case H_RANDOM:
> - if (!powernv_get_random_long(&vcpu->arch.regs.gpr[4]))
> + if (!arch_get_random_seed_long(&vcpu->arch.regs.gpr[4]))
> ret = H_HARDWARE;
> break;
> case H_RPT_INVALIDATE:
^ permalink raw reply
* Re: [PATCH v4 1/2] tty: hvc: pass DMA capable memory to put_chars()
From: Arnd Bergmann @ 2021-08-06 14:51 UTC (permalink / raw)
To: Xianting Tian
Cc: Arnd Bergmann, Jiri Slaby, Amit Shah, gregkh,
Linux Kernel Mailing List,
open list:DRM DRIVER FOR QEMU'S CIRRUS DEVICE, Guo Ren,
linuxppc-dev, Omar Sandoval
In-Reply-To: <20210806030138.123479-2-xianting.tian@linux.alibaba.com>
On Fri, Aug 6, 2021 at 5:01 AM Xianting Tian
<xianting.tian@linux.alibaba.com> wrote:
> @@ -163,6 +155,13 @@ static void hvc_console_print(struct console *co, const char *b,
> if (vtermnos[index] == -1)
> return;
>
> + list_for_each_entry(hp, &hvc_structs, next)
> + if (hp->vtermno == vtermnos[index])
> + break;
> +
> + c = hp->c;
> +
> + spin_lock_irqsave(&hp->c_lock, flags);
The loop looks like it might race against changes to the list. It seems strange
that the print function has to actually search for the structure here.
It may be better to have yet another array for the buffer pointers next to
the cons_ops[] and vtermnos[] arrays.
> +/*
> + * These sizes are most efficient for vio, because they are the
> + * native transfer size. We could make them selectable in the
> + * future to better deal with backends that want other buffer sizes.
> + */
> +#define N_OUTBUF 16
> +#define N_INBUF 16
> +
> +#define __ALIGNED__ __attribute__((__aligned__(sizeof(long))))
I think you need a higher alignment for DMA buffers, instead of sizeof(long),
I would suggest ARCH_DMA_MINALIGN.
Arnd
^ permalink raw reply
* Re: [RFC PATCH 1/4] powerpc: Optimize register usage for esr register
From: Segher Boessenkool @ 2021-08-06 14:26 UTC (permalink / raw)
To: Michael Ellerman
Cc: ravi.bangoria, sxwjean, Xiongwei Song, aneesh.kumar, oleg,
npiggin, linux-kernel, peterx, paulus, efremov, akpm,
linuxppc-dev, sandipan
In-Reply-To: <874kc3njxh.fsf@mpe.ellerman.id.au>
On Fri, Aug 06, 2021 at 04:53:14PM +1000, Michael Ellerman wrote:
> But I'm not sure about the use of anonymous unions in UAPI headers. Old
> compilers don't support them, so there's a risk of breakage.
More precisely, it exists only since C11, so even with all not-so-ancient
compilers it will not work if the user uses (say) -std=c99, which still
is popular.
> I'd rather we didn't touch the uapi version.
Yeah.
> > - err = ___do_page_fault(regs, regs->dar, regs->dsisr);
> > + if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE))
> > + err = ___do_page_fault(regs, regs->dar, regs->esr);
> > + else
> > + err = ___do_page_fault(regs, regs->dar, regs->dsisr);
>
> As Christophe said, I don't thinks this is an improvement.
>
> It makes the code less readable. If anyone is confused about what is
> passed to ___do_page_fault() they can either read the comment above it,
> or look at the definition of pt_regs to see that esr and dsisr share
> storage.
Esp. since the affected platforms are legacy, yup.
Segher
^ permalink raw reply
* [PATCH v6 1/2] KVM: PPC: Book3S HV: Sanitise vcpu registers in nested path
From: Fabiano Rosas @ 2021-08-06 13:45 UTC (permalink / raw)
To: kvm-ppc; +Cc: linuxppc-dev, npiggin
In-Reply-To: <20210806134506.2649735-1-farosas@linux.ibm.com>
As one of the arguments of the H_ENTER_NESTED hypercall, the nested
hypervisor (L1) prepares a structure containing the values of various
hypervisor-privileged registers with which it wants the nested guest
(L2) to run. Since the nested HV runs in supervisor mode it needs the
host to write to these registers.
To stop a nested HV manipulating this mechanism and using a nested
guest as a proxy to access a facility that has been made unavailable
to it, we have a routine that sanitises the values of the HV registers
before copying them into the nested guest's vcpu struct.
However, when coming out of the guest the values are copied as they
were back into L1 memory, which means that any sanitisation we did
during guest entry will be exposed to L1 after H_ENTER_NESTED returns.
This patch alters this sanitisation to have effect on the vcpu->arch
registers directly before entering and after exiting the guest,
leaving the structure that is copied back into L1 unchanged (except
when we really want L1 to access the value, e.g the Cause bits of
HFSCR).
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv_nested.c | 94 ++++++++++++++---------------
1 file changed, 46 insertions(+), 48 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c
index 898f942eb198..1823674d46ef 100644
--- a/arch/powerpc/kvm/book3s_hv_nested.c
+++ b/arch/powerpc/kvm/book3s_hv_nested.c
@@ -105,7 +105,6 @@ static void save_hv_return_state(struct kvm_vcpu *vcpu, int trap,
struct kvmppc_vcore *vc = vcpu->arch.vcore;
hr->dpdes = vc->dpdes;
- hr->hfscr = vcpu->arch.hfscr;
hr->purr = vcpu->arch.purr;
hr->spurr = vcpu->arch.spurr;
hr->ic = vcpu->arch.ic;
@@ -128,55 +127,17 @@ static void save_hv_return_state(struct kvm_vcpu *vcpu, int trap,
case BOOK3S_INTERRUPT_H_INST_STORAGE:
hr->asdr = vcpu->arch.fault_gpa;
break;
+ case BOOK3S_INTERRUPT_H_FAC_UNAVAIL:
+ hr->hfscr = ((~HFSCR_INTR_CAUSE & hr->hfscr) |
+ (HFSCR_INTR_CAUSE & vcpu->arch.hfscr));
+ break;
case BOOK3S_INTERRUPT_H_EMUL_ASSIST:
hr->heir = vcpu->arch.emul_inst;
break;
}
}
-/*
- * This can result in some L0 HV register state being leaked to an L1
- * hypervisor when the hv_guest_state is copied back to the guest after
- * being modified here.
- *
- * There is no known problem with such a leak, and in many cases these
- * register settings could be derived by the guest by observing behaviour
- * and timing, interrupts, etc., but it is an issue to consider.
- */
-static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)
-{
- struct kvmppc_vcore *vc = vcpu->arch.vcore;
- u64 mask;
-
- /*
- * Don't let L1 change LPCR bits for the L2 except these:
- */
- mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD |
- LPCR_LPES | LPCR_MER;
-
- /*
- * Additional filtering is required depending on hardware
- * and configuration.
- */
- hr->lpcr = kvmppc_filter_lpcr_hv(vcpu->kvm,
- (vc->lpcr & ~mask) | (hr->lpcr & mask));
-
- /*
- * Don't let L1 enable features for L2 which we've disabled for L1,
- * but preserve the interrupt cause field.
- */
- hr->hfscr &= (HFSCR_INTR_CAUSE | vcpu->arch.hfscr);
-
- /* Don't let data address watchpoint match in hypervisor state */
- hr->dawrx0 &= ~DAWRX_HYP;
- hr->dawrx1 &= ~DAWRX_HYP;
-
- /* Don't let completed instruction address breakpt match in HV state */
- if ((hr->ciabr & CIABR_PRIV) == CIABR_PRIV_HYPER)
- hr->ciabr &= ~CIABR_PRIV;
-}
-
-static void restore_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)
+static void restore_hv_regs(struct kvm_vcpu *vcpu, const struct hv_guest_state *hr)
{
struct kvmppc_vcore *vc = vcpu->arch.vcore;
@@ -288,6 +249,43 @@ static int kvmhv_write_guest_state_and_regs(struct kvm_vcpu *vcpu,
sizeof(struct pt_regs));
}
+static void load_l2_hv_regs(struct kvm_vcpu *vcpu,
+ const struct hv_guest_state *l2_hv,
+ const struct hv_guest_state *l1_hv, u64 *lpcr)
+{
+ struct kvmppc_vcore *vc = vcpu->arch.vcore;
+ u64 mask;
+
+ restore_hv_regs(vcpu, l2_hv);
+
+ /*
+ * Don't let L1 change LPCR bits for the L2 except these:
+ */
+ mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD |
+ LPCR_LPES | LPCR_MER;
+
+ /*
+ * Additional filtering is required depending on hardware
+ * and configuration.
+ */
+ *lpcr = kvmppc_filter_lpcr_hv(vcpu->kvm,
+ (vc->lpcr & ~mask) | (*lpcr & mask));
+
+ /*
+ * Don't let L1 enable features for L2 which we've disabled for L1,
+ * but preserve the interrupt cause field.
+ */
+ vcpu->arch.hfscr = l2_hv->hfscr & (HFSCR_INTR_CAUSE | l1_hv->hfscr);
+
+ /* Don't let data address watchpoint match in hypervisor state */
+ vcpu->arch.dawrx0 = l2_hv->dawrx0 & ~DAWRX_HYP;
+ vcpu->arch.dawrx1 = l2_hv->dawrx1 & ~DAWRX_HYP;
+
+ /* Don't let completed instruction address breakpt match in HV state */
+ if ((l2_hv->ciabr & CIABR_PRIV) == CIABR_PRIV_HYPER)
+ vcpu->arch.ciabr = l2_hv->ciabr & ~CIABR_PRIV;
+}
+
long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
{
long int err, r;
@@ -296,7 +294,7 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
struct hv_guest_state l2_hv = {0}, saved_l1_hv;
struct kvmppc_vcore *vc = vcpu->arch.vcore;
u64 hv_ptr, regs_ptr;
- u64 hdec_exp;
+ u64 hdec_exp, lpcr;
s64 delta_purr, delta_spurr, delta_ic, delta_vtb;
if (vcpu->kvm->arch.l1_ptcr == 0)
@@ -369,8 +367,8 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
/* Guest must always run with ME enabled, HV disabled. */
vcpu->arch.shregs.msr = (vcpu->arch.regs.msr | MSR_ME) & ~MSR_HV;
- sanitise_hv_regs(vcpu, &l2_hv);
- restore_hv_regs(vcpu, &l2_hv);
+ lpcr = l2_hv.lpcr;
+ load_l2_hv_regs(vcpu, &l2_hv, &saved_l1_hv, &lpcr);
vcpu->arch.ret = RESUME_GUEST;
vcpu->arch.trap = 0;
@@ -380,7 +378,7 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
r = RESUME_HOST;
break;
}
- r = kvmhv_run_single_vcpu(vcpu, hdec_exp, l2_hv.lpcr);
+ r = kvmhv_run_single_vcpu(vcpu, hdec_exp, lpcr);
} while (is_kvmppc_resume_guest(r));
/* save L2 state for return */
--
2.29.2
^ permalink raw reply related
* [PATCH v6 2/2] KVM: PPC: Book3S HV: Stop forwarding all HFUs to L1
From: Fabiano Rosas @ 2021-08-06 13:45 UTC (permalink / raw)
To: kvm-ppc; +Cc: linuxppc-dev, npiggin
In-Reply-To: <20210806134506.2649735-1-farosas@linux.ibm.com>
If the nested hypervisor has no access to a facility because it has
been disabled by the host, it should also not be able to see the
Hypervisor Facility Unavailable that arises from one of its guests
trying to access the facility.
This patch turns a HFU that happened in L2 into a Hypervisor Emulation
Assistance interrupt and forwards it to L1 for handling. The ones that
happened because L1 explicitly disabled the facility for L2 are still
let through, along with the corresponding Cause bits in the HFSCR.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
arch/powerpc/kvm/book3s_hv.c | 13 +++++++++++++
arch/powerpc/kvm/book3s_hv_nested.c | 29 +++++++++++++++++++++++------
2 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 085fb8ecbf68..9123b493c79e 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -1837,6 +1837,19 @@ static int kvmppc_handle_nested_exit(struct kvm_vcpu *vcpu)
r = RESUME_HOST;
break;
}
+ case BOOK3S_INTERRUPT_H_FAC_UNAVAIL:
+ /*
+ * We might decide later to turn this interrupt into a
+ * HEAI. Load the last instruction now that we can go
+ * back into the guest to retry if needed.
+ */
+ r = kvmppc_get_last_inst(vcpu, INST_GENERIC,
+ &vcpu->arch.emul_inst);
+ if (r != EMULATE_DONE)
+ r = RESUME_GUEST;
+ else
+ r = RESUME_HOST;
+ break;
default:
r = RESUME_HOST;
break;
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c
index 1823674d46ef..1904697a3132 100644
--- a/arch/powerpc/kvm/book3s_hv_nested.c
+++ b/arch/powerpc/kvm/book3s_hv_nested.c
@@ -99,7 +99,7 @@ static void byteswap_hv_regs(struct hv_guest_state *hr)
hr->dawrx1 = swab64(hr->dawrx1);
}
-static void save_hv_return_state(struct kvm_vcpu *vcpu, int trap,
+static void save_hv_return_state(struct kvm_vcpu *vcpu,
struct hv_guest_state *hr)
{
struct kvmppc_vcore *vc = vcpu->arch.vcore;
@@ -118,7 +118,7 @@ static void save_hv_return_state(struct kvm_vcpu *vcpu, int trap,
hr->pidr = vcpu->arch.pid;
hr->cfar = vcpu->arch.cfar;
hr->ppr = vcpu->arch.ppr;
- switch (trap) {
+ switch (vcpu->arch.trap) {
case BOOK3S_INTERRUPT_H_DATA_STORAGE:
hr->hdar = vcpu->arch.fault_dar;
hr->hdsisr = vcpu->arch.fault_dsisr;
@@ -128,9 +128,26 @@ static void save_hv_return_state(struct kvm_vcpu *vcpu, int trap,
hr->asdr = vcpu->arch.fault_gpa;
break;
case BOOK3S_INTERRUPT_H_FAC_UNAVAIL:
- hr->hfscr = ((~HFSCR_INTR_CAUSE & hr->hfscr) |
- (HFSCR_INTR_CAUSE & vcpu->arch.hfscr));
- break;
+ {
+ u64 cause = vcpu->arch.hfscr >> 56;
+
+ WARN_ON_ONCE(cause >= BITS_PER_LONG);
+
+ if (!(hr->hfscr & (1UL << cause))) {
+ hr->hfscr = ((~HFSCR_INTR_CAUSE & hr->hfscr) |
+ (HFSCR_INTR_CAUSE & vcpu->arch.hfscr));
+ break;
+ }
+
+ /*
+ * We have disabled this facility, so it does not
+ * exist from L1's perspective. Turn it into a
+ * HEAI. The instruction was already loaded at
+ * kvmppc_handle_nested_exit().
+ */
+ vcpu->arch.trap = BOOK3S_INTERRUPT_H_EMUL_ASSIST;
+ fallthrough;
+ }
case BOOK3S_INTERRUPT_H_EMUL_ASSIST:
hr->heir = vcpu->arch.emul_inst;
break;
@@ -388,7 +405,7 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
delta_spurr = vcpu->arch.spurr - l2_hv.spurr;
delta_ic = vcpu->arch.ic - l2_hv.ic;
delta_vtb = vc->vtb - l2_hv.vtb;
- save_hv_return_state(vcpu, vcpu->arch.trap, &l2_hv);
+ save_hv_return_state(vcpu, &l2_hv);
/* restore L1 state */
vcpu->arch.nested = NULL;
--
2.29.2
^ permalink raw reply related
* [PATCH v6 0/2] KVM: PPC: Book3S HV: Nested guest state sanitising changes
From: Fabiano Rosas @ 2021-08-06 13:45 UTC (permalink / raw)
To: kvm-ppc; +Cc: linuxppc-dev, npiggin
This series aims to stop contaminating the l2_hv structure with bits
that might have come from L1 state.
Patch 1 makes l2_hv read-only (mostly). It is now only changed when we
explicitly want to pass information to L1.
Patch 2 makes sure that L1 is not forwarded HFU interrupts when the
host has decided to disable any facilities (theoretical for now, since
HFSCR bits are always the same between L1/Ln).
Changes since v5:
- patch 2 now reads the instruction earlier at the nested exit handler
to allow the guest to retry if the load fails.
v5:
- moved setting of the Cause bits under BOOK3S_INTERRUPT_H_FAC_UNAVAIL.
https://lkml.kernel.org/r/20210726201710.2432874-1-farosas@linux.ibm.com
v4:
- now passing lpcr separately into load_l2_hv_regs to solve the
conflict with commit a19b70abc69a ("KVM: PPC: Book3S HV: Nested move
LPCR sanitising to sanitise_hv_regs");
- patch 2 now forwards a HEAI instead of injecting a Program.
https://lkml.kernel.org/r/20210722221240.2384655-1-farosas@linux.ibm.com
v3:
- removed the sanitise functions;
- moved the entry code into a new load_l2_hv_regs and the exit code
into the existing save_hv_return_state;
- new patch: removes the cause bits when L0 has disabled the
corresponding facility.
https://lkml.kernel.org/r/20210415230948.3563415-1-farosas@linux.ibm.com
v2:
- made the change more generic, not only applies to hfscr anymore;
- sanitisation is now done directly on the vcpu struct, l2_hv is left
unchanged.
https://lkml.kernel.org/r/20210406214645.3315819-1-farosas@linux.ibm.com
v1:
https://lkml.kernel.org/r/20210305231055.2913892-1-farosas@linux.ibm.com
Fabiano Rosas (2):
KVM: PPC: Book3S HV: Sanitise vcpu registers in nested path
KVM: PPC: Book3S HV: Stop forwarding all HFUs to L1
arch/powerpc/kvm/book3s_hv.c | 13 ++++
arch/powerpc/kvm/book3s_hv_nested.c | 117 ++++++++++++++++------------
2 files changed, 79 insertions(+), 51 deletions(-)
--
2.29.2
^ permalink raw reply
* [PATCH] powerpc/mce: check if event info is valid
From: Ganesh Goudar @ 2021-08-06 13:23 UTC (permalink / raw)
To: linuxppc-dev, mpe; +Cc: Ganesh Goudar, mahesh, npiggin
Check if the event info is valid before printing the
event information. When a fwnmi enabled nested kvm guest
hits a machine check exception L0 and L2 would generate
machine check event info, But L1 would not generate any
machine check event info as it won't go through 0x200
vector and prints some unwanted message.
To fix this, 'in_use' variable in machine check event info is
no more in use, rename it to 'valid' and check if the event
information is valid before logging the event information.
without this patch L1 would print following message for
exceptions encountered in L2, as event structure will be
empty in L1.
"Machine Check Exception, Unknown event version 0".
Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com>
---
arch/powerpc/include/asm/mce.h | 2 +-
arch/powerpc/kernel/mce.c | 7 +++++--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
index 331d944280b8..3646f53f228f 100644
--- a/arch/powerpc/include/asm/mce.h
+++ b/arch/powerpc/include/asm/mce.h
@@ -113,7 +113,7 @@ enum MCE_LinkErrorType {
struct machine_check_event {
enum MCE_Version version:8;
- u8 in_use;
+ u8 valid;
enum MCE_Severity severity:8;
enum MCE_Initiator initiator:8;
enum MCE_ErrorType error_type:8;
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
index 47a683cd00d2..b778394a06b5 100644
--- a/arch/powerpc/kernel/mce.c
+++ b/arch/powerpc/kernel/mce.c
@@ -114,7 +114,7 @@ void save_mce_event(struct pt_regs *regs, long handled,
mce->srr0 = nip;
mce->srr1 = regs->msr;
mce->gpr3 = regs->gpr[3];
- mce->in_use = 1;
+ mce->valid = 1;
mce->cpu = get_paca()->paca_index;
/* Mark it recovered if we have handled it and MSR(RI=1). */
@@ -202,7 +202,7 @@ int get_mce_event(struct machine_check_event *mce, bool release)
if (mce)
*mce = *mc_evt;
if (release)
- mc_evt->in_use = 0;
+ mc_evt->valid = 0;
ret = 1;
}
/* Decrement the count to free the slot. */
@@ -413,6 +413,9 @@ void machine_check_print_event_info(struct machine_check_event *evt,
"Probable Software error (some chance of hardware cause)",
};
+ if (!evt->valid)
+ return;
+
/* Print things out */
if (evt->version != MCE_V1) {
pr_err("Machine Check Exception, Unknown event version %d !\n",
--
2.31.1
^ permalink raw reply related
* Re: [RFC PATCH 1/4] powerpc: Optimize register usage for esr register
From: Xiongwei Song @ 2021-08-06 13:22 UTC (permalink / raw)
To: Christophe Leroy
Cc: ravi.bangoria, Xiongwei Song, oleg, npiggin,
Linux Kernel Mailing List, efremov, Paul Mackerras, aneesh.kumar,
peterx, PowerPC, akpm, sandipan
In-Reply-To: <26814448-c30a-1de1-bad4-79e2bffc3054@csgroup.eu>
On Fri, Aug 6, 2021 at 3:32 PM Christophe Leroy
<christophe.leroy@csgroup.eu> wrote:
>
>
>
> Le 06/08/2021 à 05:16, Xiongwei Song a écrit :
> > On Thu, Aug 5, 2021 at 6:06 PM Christophe Leroy
> > <christophe.leroy@csgroup.eu> wrote:
> >>
> >>
> >>
> >> Le 26/07/2021 à 16:30, sxwjean@me.com a écrit :
> >>> From: Xiongwei Song <sxwjean@gmail.com>
> >>>
> >>> Create an anonymous union for dsisr and esr regsiters, we can reference
> >>> esr to get the exception detail when CONFIG_4xx=y or CONFIG_BOOKE=y.
> >>> Otherwise, reference dsisr. This makes code more clear.
> >>
> >> I'm not sure it is worth doing that.
> > Why don't we use "esr" as reference manauls mentioned?
> >
> >>
> >> What is the point in doing the following when you know that regs->esr and regs->dsisr are exactly
> >> the same:
> >>
> >> > - err = ___do_page_fault(regs, regs->dar, regs->dsisr);
> >> > + if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE))
> >> > + err = ___do_page_fault(regs, regs->dar, regs->esr);
> >> > + else
> >> > + err = ___do_page_fault(regs, regs->dar, regs->dsisr);
> >> > +
> > Yes, we can drop this. But it's a bit vague.
> >
> >> Or even
> >>
> >> > - int is_write = page_fault_is_write(regs->dsisr);
> >> > + unsigned long err_reg;
> >> > + int is_write;
> >> > +
> >> > + if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE))
> >> > + err_reg = regs->esr;
> >> > + else
> >> > + err_reg = regs->dsisr;
> >> > +
> >> > + is_write = page_fault_is_write(err_reg);
> >>
> >>
> >> Artificially growing the code for that makes no sense to me.
> >
> > We can drop this too.
> >>
> >>
> >> To avoid anbiguity, maybe the best would be to rename regs->dsisr to something like regs->sr , so
> >> that we know it represents the status register, which is DSISR or ESR depending on the platform.
> >
> > If so, this would make other people more confused. My consideration is
> > to follow what the reference
> > manuals represent.
>
> Maybe then we could rename the fields as regs->dsisr_esr and regs->dar_dear
I still prefer my method.
>
> That would be more explicit for everyone.
>
> The UAPI header however should remain as is because anonymous unions are not supported by old
> compilers as mentioned by Michael.
Sure. Will update in v2.
>
> But nevertheless, there are also situations where was is stored in regs->dsisr is not what we have
> in DSISR register. For instance on an ISI exception, we store a subset of the content of SRR1
> register into regs->dsisr.
Can I think my method has better expansibility here;-)?
Let me finish esr and dear first. Thank you for the reminder.
Regards,
Xiongwei
>
> Christophe
^ permalink raw reply
* Re: [RFC PATCH 1/4] powerpc: Optimize register usage for esr register
From: Xiongwei Song @ 2021-08-06 13:14 UTC (permalink / raw)
To: Michael Ellerman
Cc: ravi.bangoria, Xiongwei Song, oleg, Linux Kernel Mailing List,
efremov, Paul Mackerras, npiggin, aneesh.kumar, peterx, PowerPC,
akpm, sandipan
In-Reply-To: <874kc3njxh.fsf@mpe.ellerman.id.au>
On Fri, Aug 6, 2021 at 2:53 PM Michael Ellerman <mpe@ellerman.id.au> wrote:
>
> sxwjean@me.com writes:
> > From: Xiongwei Song <sxwjean@gmail.com>
> >
> > Create an anonymous union for dsisr and esr regsiters, we can reference
> > esr to get the exception detail when CONFIG_4xx=y or CONFIG_BOOKE=y.
> > Otherwise, reference dsisr. This makes code more clear.
> >
> > Signed-off-by: Xiongwei Song <sxwjean@gmail.com>
> > ---
> > arch/powerpc/include/asm/ptrace.h | 5 ++++-
> > arch/powerpc/include/uapi/asm/ptrace.h | 5 ++++-
> > arch/powerpc/kernel/process.c | 2 +-
> > arch/powerpc/kernel/ptrace/ptrace.c | 2 ++
> > arch/powerpc/kernel/traps.c | 2 +-
> > arch/powerpc/mm/fault.c | 16 ++++++++++++++--
> > arch/powerpc/platforms/44x/machine_check.c | 4 ++--
> > arch/powerpc/platforms/4xx/machine_check.c | 2 +-
> > 8 files changed, 29 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
> > index 3e5d470a6155..c252d04b1206 100644
> > --- a/arch/powerpc/include/asm/ptrace.h
> > +++ b/arch/powerpc/include/asm/ptrace.h
> > @@ -44,7 +44,10 @@ struct pt_regs
> > #endif
> > unsigned long trap;
> > unsigned long dar;
> > - unsigned long dsisr;
> > + union {
> > + unsigned long dsisr;
> > + unsigned long esr;
> > + };
>
> I don't mind doing that.
>
> > unsigned long result;
> > };
> > };
> > diff --git a/arch/powerpc/include/uapi/asm/ptrace.h b/arch/powerpc/include/uapi/asm/ptrace.h
> > index 7004cfea3f5f..e357288b5f34 100644
> > --- a/arch/powerpc/include/uapi/asm/ptrace.h
> > +++ b/arch/powerpc/include/uapi/asm/ptrace.h
> > @@ -53,7 +53,10 @@ struct pt_regs
> > /* N.B. for critical exceptions on 4xx, the dar and dsisr
> > fields are overloaded to hold srr0 and srr1. */
> > unsigned long dar; /* Fault registers */
> > - unsigned long dsisr; /* on 4xx/Book-E used for ESR */
> > + union {
> > + unsigned long dsisr; /* on Book-S used for DSISR */
> > + unsigned long esr; /* on 4xx/Book-E used for ESR */
> > + };
> > unsigned long result; /* Result of a system call */
> > };
>
> But I'm not sure about the use of anonymous unions in UAPI headers. Old
> compilers don't support them, so there's a risk of breakage.
>
> I'd rather we didn't touch the uapi version.
Ok. Will discard the change.
>
>
> > diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
> > index 185beb290580..f74af8f9133c 100644
> > --- a/arch/powerpc/kernel/process.c
> > +++ b/arch/powerpc/kernel/process.c
> > @@ -1499,7 +1499,7 @@ static void __show_regs(struct pt_regs *regs)
> > trap == INTERRUPT_DATA_STORAGE ||
> > trap == INTERRUPT_ALIGNMENT) {
> > if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE))
> > - pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
> > + pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->esr);
> > else
> > pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
> > }
> > diff --git a/arch/powerpc/kernel/ptrace/ptrace.c b/arch/powerpc/kernel/ptrace/ptrace.c
> > index 0a0a33eb0d28..00789ad2c4a3 100644
> > --- a/arch/powerpc/kernel/ptrace/ptrace.c
> > +++ b/arch/powerpc/kernel/ptrace/ptrace.c
> > @@ -375,6 +375,8 @@ void __init pt_regs_check(void)
> > offsetof(struct user_pt_regs, dar));
> > BUILD_BUG_ON(offsetof(struct pt_regs, dsisr) !=
> > offsetof(struct user_pt_regs, dsisr));
> > + BUILD_BUG_ON(offsetof(struct pt_regs, esr) !=
> > + offsetof(struct user_pt_regs, esr));
> > BUILD_BUG_ON(offsetof(struct pt_regs, result) !=
> > offsetof(struct user_pt_regs, result));
> >
> > diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
> > index dfbce527c98e..2164f5705a0b 100644
> > --- a/arch/powerpc/kernel/traps.c
> > +++ b/arch/powerpc/kernel/traps.c
> > @@ -562,7 +562,7 @@ static inline int check_io_access(struct pt_regs *regs)
> > #ifdef CONFIG_PPC_ADV_DEBUG_REGS
> > /* On 4xx, the reason for the machine check or program exception
> > is in the ESR. */
> > -#define get_reason(regs) ((regs)->dsisr)
> > +#define get_reason(regs) ((regs)->esr)
> > #define REASON_FP ESR_FP
> > #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
> > #define REASON_PRIVILEGED ESR_PPR
> > diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
> > index a8d0ce85d39a..62953d4e7c93 100644
> > --- a/arch/powerpc/mm/fault.c
> > +++ b/arch/powerpc/mm/fault.c
> > @@ -541,7 +541,11 @@ static __always_inline void __do_page_fault(struct pt_regs *regs)
> > {
> > long err;
> >
> > - err = ___do_page_fault(regs, regs->dar, regs->dsisr);
> > + if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE))
> > + err = ___do_page_fault(regs, regs->dar, regs->esr);
> > + else
> > + err = ___do_page_fault(regs, regs->dar, regs->dsisr);
>
> As Christophe said, I don't thinks this is an improvement.
>
> It makes the code less readable. If anyone is confused about what is
> passed to ___do_page_fault() they can either read the comment above it,
> or look at the definition of pt_regs to see that esr and dsisr share
> storage.
Ok, thanks a lot. Will send v2.
Regards,
Xiongwei
>
> cheers
^ permalink raw reply
* Re: [PATCH] powerpc/xive: Do not skip CPU-less nodes when creating the IPIs
From: Cédric Le Goater @ 2021-08-06 11:50 UTC (permalink / raw)
To: linuxppc-dev
Cc: Laurent Vivier, Srikar Dronamraju, Geetika Moolchandani, stable,
David Gibson
In-Reply-To: <20210629131542.743888-1-clg@kaod.org>
On 6/29/21 3:15 PM, Cédric Le Goater wrote:
> On PowerVM, CPU-less nodes can be populated with hot-plugged CPUs at
> runtime. Today, the IPI is not created for such nodes, and hot-plugged
> CPUs use a bogus IPI, which leads to soft lockups.
>
> We could create the node IPI on demand but it is a bit complex because
> this code would be called under bringup_up() and some IRQ locking is
> being done. The simplest solution is to create the IPIs for all nodes
> at startup.
>
> Fixes: 7dcc37b3eff9 ("powerpc/xive: Map one IPI interrupt per node")
> Cc: stable@vger.kernel.org # v5.13
> Reported-by: Geetika Moolchandani <Geetika.Moolchandani1@ibm.com>
> Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>
> This patch breaks old versions of irqbalance (<= v1.4). Possible nodes
> are collected from /sys/devices/system/node/ but CPU-less nodes are
> not listed there. When interrupts are scanned, the link representing
> the node structure is NULL and segfault occurs.
This is an irqbalance regression due to :
https://github.com/Irqbalance/irqbalance/pull/172
I will report through an issue.
Anyhow, there is a better approach which is to allocate IPIs for all
nodes at boot time and do the mapping on demand. Removing the mapping
on last use seems more complex though.
I will send a v2 after some tests.
Thanks,
C.
> Version 1.7 seems immune.
>
> ---
> arch/powerpc/sysdev/xive/common.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
> index f3b16ed48b05..5d2c58dba57e 100644
> --- a/arch/powerpc/sysdev/xive/common.c
> +++ b/arch/powerpc/sysdev/xive/common.c
> @@ -1143,10 +1143,6 @@ static int __init xive_request_ipi(void)
> struct xive_ipi_desc *xid = &xive_ipis[node];
> struct xive_ipi_alloc_info info = { node };
>
> - /* Skip nodes without CPUs */
> - if (cpumask_empty(cpumask_of_node(node)))
> - continue;
> -
> /*
> * Map one IPI interrupt per node for all cpus of that node.
> * Since the HW interrupt number doesn't have any meaning,
>
^ permalink raw reply
* Re: [PATCH printk v1 03/10] kgdb: delay roundup if holding printk cpulock
From: Daniel Thompson @ 2021-08-06 12:06 UTC (permalink / raw)
To: John Ogness
Cc: Gautham R. Shenoy, Douglas Anderson, Srikar Dronamraju,
Peter Zijlstra, linux-kernel, Paul Mackerras, H. Peter Anvin,
Chengyang Fan, Bhaskar Chowdhury, x86, Ingo Molnar,
kgdb-bugreport, Petr Mladek, Nicholas Piggin, Borislav Petkov,
Steven Rostedt, Thomas Gleixner, Gustavo A. R. Silva,
Sergey Senozhatsky, Jason Wessel, linuxppc-dev,
Cédric Le Goater
In-Reply-To: <87tuk4lfj0.fsf@jogness.linutronix.de>
On Thu, Aug 05, 2021 at 05:52:43AM +0206, John Ogness wrote:
> On 2021-08-04, Daniel Thompson <daniel.thompson@linaro.org> wrote:
> > On Wed, Aug 04, 2021 at 02:12:22PM +0200, Petr Mladek wrote:
> >> On Wed 2021-08-04 12:31:59, Daniel Thompson wrote:
> >> > On Tue, Aug 03, 2021 at 05:36:32PM +0206, John Ogness wrote:
> >> > > On 2021-08-03, Daniel Thompson <daniel.thompson@linaro.org> wrote:
> >> > > > On Tue, Aug 03, 2021 at 03:18:54PM +0206, John Ogness wrote:
> >> > > >> kgdb makes use of its own cpulock (@dbg_master_lock, @kgdb_active)
> >> > > >> during cpu roundup. This will conflict with the printk cpulock.
> >> > > >
> >> > > > When the full vision is realized what will be the purpose of the printk
> >> > > > cpulock?
> >> > > >
> >> > > > I'm asking largely because it's current role is actively unhelpful
> >> > > > w.r.t. kdb. It is possible that cautious use of in_dbg_master() might
> >> > > > be a better (and safer) solution. However it sounds like there is a
> >> > > > larger role planned for the printk cpulock...
> >> > >
> >> > > The printk cpulock is used as a synchronization mechanism for
> >> > > implementing atomic consoles, which need to be able to safely interrupt
> >> > > the console write() activity at any time and immediately continue with
> >> > > their own printing. The ultimate goal is to move all console printing
> >> > > into per-console dedicated kthreads, so the primary function of the
> >> > > printk cpulock is really to immediately _stop_ the CPU/kthread
> >> > > performing write() in order to allow write_atomic() (from any context on
> >> > > any CPU) to safely and reliably take over.
> >> >
> >> > I see.
> >> >
> >> > Is there any mileage in allowing in_dbg_master() to suppress taking
> >> > the console lock?
> >> >
> >> > There's a couple of reasons to worry about the current approach.
> >> >
> >> > The first is that we don't want this code to trigger in the case when
> >> > kgdb is enabled and kdb is not since it is only kdb (a self-hosted
> >> > debugger) than uses the consoles. This case is relatively trivial to
> >> > address since we can rename it kdb_roundup_delay() and alter the way it
> >> > is conditionally compiled.
>
> Well, _I_ want this code to trigger even without kdb. The printk cpulock
> is meant to be the innermost locking for the entire kernel. No code is
> allowed to block/spin on any kind of lock if holding the printk
> cpulock. This is the only way to guarantee the functionality of the
> atomic consoles.
>
> For example, if the kernel were to crash while inside kgdb code, we want
> to see the backtrace.
That would certainly help me debug any such problems in kgdb ;-) .
> Since kgdb _does_ take locks (spinning on @dbg_slave_lock during roundup
> and the master's own cpu lock as a retry loop on @dbg_master_lock),
> clearly it is not allowed to hold the printk cpulock. The simplest
> solution I could find was just to make sure kgdb_cpu_enter() isn't
> called while holding the printk cpulock.
We might have to come back to this. I'm pretty certain your patch
does not currently achieve this goal.
> >> > The second is more of a problem however. kdb will only call into the
> >> > console code from the debug master. By default this is the CPU that
> >> > takes the debug trap so initial prints will work fine. However it is
> >> > possible to switch to a different master (so we can read per-CPU
> >> > registers and things like that). This will result in one of the CPUs
> >> > that did the IPI round up calling into console code and this is unsafe
> >> > in that instance.
>
> It is only unsafe if a CPU enters "kgdb/kdb context" while holding the
> printk cpulock. That is what I want to prevent.
Currently you can preventing this only for CPUs that enter the debugger
via an IPI. CPUs that enter due to a breakpoint (and there can be more
than one at a time) cannot just continue until the lock is dropped
since they would end up re-executing the breakpoint instruction.
> >> > There are a couple of tricks we could adopt to work around this but
> >> > given the slightly odd calling context for kdb (all CPUs quiesced, no
> >> > log interleaving possible) it sounds like it would remain safe to
> >> > bypass the lock if in_dbg_master() is true.
> >> >
> >> > Bypassing an inconvenient lock might sound icky but:
> >> >
> >> > 1. If the lock is not owned by any CPU then what kdb will do is safe.
>
> No. The printk cpulock exists for low-level synchronization. The atomic
> consoles need this synchronization. (For example, the 8250 needs this
> for correct tracking of its interrupt register, even for
> serial8250_put_poll_char().)
What I mean is that because kdb is mono-threaded (even on SMP systems
due to the quiescing of other CPUs) then if the lock is not taken when
we enter kdb then it is safe for kdb to contend for the lock in the
normal way since it cannot deadlock.
BTW the synchronization in question is the need for strict nesting, is
that right? (e.g. that each context that recursively acquires the lock
will release it in strict reverse order?).
> >> > 2. If the lock is owned by any CPU then we have quiesced it anyway
> >> > and this makes is safe for the owning CPU to share its ownership
> >> > (since it isn't much different to recursive acquisition on a single
> >> > CPU)
>
> Quiescing the printk cpulock is not permitted.
Sorry I wasn't quite clear in phrasing here. I don't think of it as
quiescing the lock, I think of it as quiescing the CPU that owns the
lock.
If any CPU that owns the lock *and* all CPUs except the debug master are
quiesced then allowing the debug master to take the lock is essentially
a special case of recursive acquisition and it will nest correctly.
> Just because it is kdb, does not mean that the atomic consoles were
> interrupted in a convenient place. The whole purpose of the atomic
> consoles is so that we can have guaranteed console output from _any_
> context and _any_ line of code in the kernel.
>
> >> I think about the following:
> >>
> >> void kgdb_roundup_cpus(void)
> >> {
> >> __printk_cpu_lock();
> >> __kgdb_roundup_cpus();
> >> }
> >>
> >> , where __printk_cpu_lock() waits/takes printk_cpu_lock()
> >> __kgdb_roundup_cpus() is the original kgdb_roundup_cpus();
> >>
> >>
> >> The idea is that kgdb_roundup_cpus() caller takes the printk_cpu lock.
> >> The owner will be well defined.
> >>
> >> As a result any other CPU will not be able to take the printk_cpu lock
> >> as long as it is owned by the kgdb lock. But as you say, kgdb will
> >> make sure that everything is serialized at this stage. So that
> >> the original raw_printk_cpu_lock_irqsave() might just disable
> >> IRQs when called under debugger.
> >>
> >> Does it make any sense?
> >
> > Yes but I think it is still has problems.
> >
> > Primarily is doesn't solve the issue I raised. It would still be unsafe
> > to change debug master: we can guarantee the initial master owns the
> > lock but if it has been multiply acquired we cannot transfer ownership
> > when we want to change master.
> >
> > Additionally it will delay the round up of cores that do not own the
> > lock. The quiescing is never atomic and the operator needs to know
> > that but the longer CPUs are allows to execute for the more confusing
> > things can become for the operator.
> >
> > Finally on machines without an NMI this could cause trouble with the
> > interrupt disable in raw_printk_cpu_lock_irqsave() (or any outer level
> > interrupt disable). If the master get the lock then the other processes
> > will become incapable of being rounded up if they are waiting for the
> > printk lock).
>
> I am also not happy with such a solution. Aside from Daniel's comments,
> it also violates the basic principle of the printk cpulock by allowing
> further locking while holding the print cpulock. That is a recipe for
> deadlock.
>
> >> I have to say that it is a bit hairy. But it looks slightly better
> >> than the delayed/repeated IPI proposed by this patch.
> >
> > I'd like to reserve judgement for now which one is least worst...
> > largely because if the purpose of the lock simply to prevent interleaving
> > of console output then the debugger quiescing code should already have
> > this covered.
> >
> > It leaves me wondering if a change like the one below is sufficient
> > (based on code without John's patches but hopefully still clear enough).
> > I've given the new code it's own branch which it doesn't, strictly
> > speaking, need but it is easier to comment this way... and perhaps also
> > just a little easier for people who have not set CONFIG_KGDB to
> > ignore ;-).
> >
> > ~~~
> > diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
> > index 142a58d124d9..41a7e103bb66 100644
> > --- a/kernel/printk/printk.c
> > +++ b/kernel/printk/printk.c
> > @@ -3599,6 +3599,18 @@ int __printk_cpu_trylock(void)
> > /* This CPU is already the owner. */
> > atomic_inc(&printk_cpulock_nested);
> > return 1;
> > + } else if (in_dbg_master()) {
> > + /*
> > + * If we are executing as the primary CPU and with the debugger
> > + * active than all other CPUs in the system are quiesced by
> > + * the time kdb winds up calling this function. To execute this
> > + * branch then the lock must be owned by one of the quiesced CPUs.
> > + * Happily, because it is quiesced and cannot release it, it is
> > + * safe for us to allow the lock to be taken from a different CPU!
> > + * The lock will be released prior to resuming the real owner.
> > + */
> > + atomic_inc(&printk_cpulock_nested);
> > + return 1;
> > }
> >
> > return 0;
> > ~~~
>
> Being in kgdb/kdb context is similar to being in atomic console
> context. (Of course, they are both using cpu locks.) But the contexts
> are not the same. It is incorrect to handle them as the same.
>
> We need to decide who is inside of who. Either printk is the innermost,
> in which case the printk cpulock cannot be held when calling
> kgdb_cpu_enter().
It is difficult to prevent this for the breakpoint cases... although
since everything about your current work is difficult I don't expect
that to be a sufficient argument on its own!
> Or kgdb is the innermost, meaning that the atomic
> consoles are no longer atomic/reliable while in kgdb.
>
> I prefer and am pushing for the first, but am willing to accept the
> second (i.e. that kgdb is the innermost function of the kernel).
I think it will always be the case that we might execute breakpoints in
an NMI context since the collateral damage from forbidding breakpoints
on all API that *might* be called from NMI is likely to constrain the
not-NMI debugging experience too much. However it *is* possible to defer
breakpoints: we could defer them by calling into the
out-of-line-single-step logic that is needed to support kprobes. I
dislike this approach since there is no way to fixup the PC so when
we eventually stop then gdb would have trouble figuring out
why the system has stopped.
However taking on board what you are saying about innermost functions
I think there might be a we could look into that is much nicer from an
analysis point of view than relying in in_dbg_master() to implicitly
borrow the printk lock.
Would you consider a means for kgdb to *explicitly* allow a slave CPU
to donate ownership to the debug master as part of it's spin loop (e.g.
explicitly transfer ownership if and only if we are quiesced). This
has a number of nice properties:
1. The ownership transfer happens *after* we have decided who the
master actually is and before that point everything works as
normal!
2. Safe-nesting is guaranteed by the slave CPUs exception stack.
3. We can print (and expect it to be seen) pretty much anywhere in the
master code path (including the ones before we find out who will be
master since that happens before the IPIs) with no trouble.
3. Handling change of master is easy... we can re-donate the lock
to the new master using the same or similar API.
4. We can print anywhere in the slave code *except* for the tight
loop we run after donating ownership to the master and the code
after an former master CPU donates the lock to the next master
and before the former master drops into the slave loop.
5. Apart from the function to donate ownership all the nasty code
to handle it ends up in kgdb where is belongs rather than smeared
in your lock code.
I can't decide if this makes a tiny piece of kgdb inner-most or not
but it is certainly much easier to analyse how kgdb and atomic consoles
interact.
> > PS In the interested of full disclosure there is a special case
> > in the debugger to allow it to try to cope if it fails to
> > quiesce a CPU and I deliberately omitted this from the long
> > comment above. That special case is expected to be unstable
> > but since the alternative is likely to be a permanent deadlock
> > without any indication of why we choose to take the risk of
> > continuing. Personally I don't recommend reasoning about
> > console safety based on this emergency case hence omitting the
> > comment.
The above idea of explicitly transferring lock ownership also allows us
to analyse this case (where as the in_dbg_master() approach meant it was
too hard). If the CPU cannot be rounded up (will not react to the NMI
IPI) *and* it owns the printk lock and won't give it back then kdb will
deadlock. Given your goals w.r.t. reliability of atomic consoles then I
am more than happy to live with this!
Daniel.
^ permalink raw reply
* Re: [PATCH v1 16/55] powerpc/64s: Implement PMU override command line option
From: Nicholas Piggin @ 2021-08-06 10:42 UTC (permalink / raw)
To: Athira Rajeev; +Cc: linuxppc-dev, kvm-ppc
In-Reply-To: <4600EC62-5505-4856-AE23-939ED62287B3@linux.vnet.ibm.com>
Excerpts from Athira Rajeev's message of August 6, 2021 7:28 pm:
>
>
>> On 26-Jul-2021, at 9:19 AM, Nicholas Piggin <npiggin@gmail.com> wrote:
>>
>> It can be useful in simulators (with very constrained environments)
>> to allow some PMCs to run from boot so they can be sampled directly
>> by a test harness, rather than having to run perf.
>>
>> A previous change freezes counters at boot by default, so provide
>> a boot time option to un-freeze (plus a bit more flexibility).
>>
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>> ---
>> .../admin-guide/kernel-parameters.txt | 7 ++++
>> arch/powerpc/perf/core-book3s.c | 35 +++++++++++++++++++
>> 2 files changed, 42 insertions(+)
>>
>> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
>> index bdb22006f713..96b7d0ebaa40 100644
>> --- a/Documentation/admin-guide/kernel-parameters.txt
>> +++ b/Documentation/admin-guide/kernel-parameters.txt
>> @@ -4089,6 +4089,13 @@
>> Override pmtimer IOPort with a hex value.
>> e.g. pmtmr=0x508
>>
>> + pmu= [PPC] Manually enable the PMU.
>> + Enable the PMU by setting MMCR0 to 0 (clear FC bit).
>> + This option is implemented for Book3S processors.
>> + If a number is given, then MMCR1 is set to that number,
>> + otherwise (e.g., 'pmu=on'), it is left 0. The perf
>> + subsystem is disabled if this option is used.
>> +
>> pm_debug_messages [SUSPEND,KNL]
>> Enable suspend/resume debug messages during boot up.
>>
>> diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
>> index 65795cadb475..e7cef4fe17d7 100644
>> --- a/arch/powerpc/perf/core-book3s.c
>> +++ b/arch/powerpc/perf/core-book3s.c
>> @@ -2428,8 +2428,24 @@ int register_power_pmu(struct power_pmu *pmu)
>> }
>>
>> #ifdef CONFIG_PPC64
>> +static bool pmu_override = false;
>> +static unsigned long pmu_override_val;
>> +static void do_pmu_override(void *data)
>> +{
>> + ppc_set_pmu_inuse(1);
>> + if (pmu_override_val)
>> + mtspr(SPRN_MMCR1, pmu_override_val);
>> + mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_FC);
>
> Hi Nick
>
> Here, we are not doing any validity check for the value used to set MMCR1.
> For advanced users, the option to pass value for MMCR1 is fine. But other cases, it could result in
> invalid event getting used. Do we need to restrict this boot time option for only PMC5/6 ?
Depends what would be useful. We don't have to prevent the admin shooting
themselves in the foot with options like this, but if we can make it
safer without making it less useful then that's always a good option.
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v1 16/55] powerpc/64s: Implement PMU override command line option
From: Nicholas Piggin @ 2021-08-06 10:38 UTC (permalink / raw)
To: kvm-ppc, Madhavan Srinivasan; +Cc: linuxppc-dev
In-Reply-To: <e7bb1311-3b50-dcc2-7fb0-1773558e9abc@linux.ibm.com>
Excerpts from Madhavan Srinivasan's message of August 6, 2021 5:33 pm:
>
> On 7/26/21 9:19 AM, Nicholas Piggin wrote:
>> It can be useful in simulators (with very constrained environments)
>> to allow some PMCs to run from boot so they can be sampled directly
>> by a test harness, rather than having to run perf.
>>
>> A previous change freezes counters at boot by default, so provide
>> a boot time option to un-freeze (plus a bit more flexibility).
>>
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>> ---
>> .../admin-guide/kernel-parameters.txt | 7 ++++
>> arch/powerpc/perf/core-book3s.c | 35 +++++++++++++++++++
>> 2 files changed, 42 insertions(+)
>>
>> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
>> index bdb22006f713..96b7d0ebaa40 100644
>> --- a/Documentation/admin-guide/kernel-parameters.txt
>> +++ b/Documentation/admin-guide/kernel-parameters.txt
>> @@ -4089,6 +4089,13 @@
>> Override pmtimer IOPort with a hex value.
>> e.g. pmtmr=0x508
>>
>> + pmu= [PPC] Manually enable the PMU.
>
>
> This is bit confusing, IIUC, we are manually disabling the perf
> registration
> with this option and not pmu.
> If this option is used, we will unfreeze the
> MMCR0_FC (only in the HV_mode) and not register perf subsystem.
With the previous patch, this option un-freezes the PMU
(and disables perf).
> Since this option is valid only for HV_mode, canwe call it
> kvm_disable_perf or kvm_dis_perf.
It's only disabled for guests because it would require a bit
of logic to set pmcregs_in_use when we register our lppaca. We could
add that if needed, but the intention is for use on BML, not exactly
KVM specific.
I can add HV restriction to the help text. And we could rename the
option. free_run_pmu= or something?
Thanks,
Nick
>
>
>> + Enable the PMU by setting MMCR0 to 0 (clear FC bit).
>> + This option is implemented for Book3S processors.
>> + If a number is given, then MMCR1 is set to that number,
>> + otherwise (e.g., 'pmu=on'), it is left 0. The perf
>> + subsystem is disabled if this option is used.
>> +
>> pm_debug_messages [SUSPEND,KNL]
>> Enable suspend/resume debug messages during boot up.
>>
>> diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
>> index 65795cadb475..e7cef4fe17d7 100644
>> --- a/arch/powerpc/perf/core-book3s.c
>> +++ b/arch/powerpc/perf/core-book3s.c
>> @@ -2428,8 +2428,24 @@ int register_power_pmu(struct power_pmu *pmu)
>> }
>>
>> #ifdef CONFIG_PPC64
>> +static bool pmu_override = false;
>> +static unsigned long pmu_override_val;
>> +static void do_pmu_override(void *data)
>> +{
>> + ppc_set_pmu_inuse(1);
>> + if (pmu_override_val)
>> + mtspr(SPRN_MMCR1, pmu_override_val);
>> + mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_FC);
>> +}
>> +
>> static int __init init_ppc64_pmu(void)
>> {
>> + if (cpu_has_feature(CPU_FTR_HVMODE) && pmu_override) {
>> + printk(KERN_WARNING "perf: disabling perf due to pmu= command line option.\n");
>> + on_each_cpu(do_pmu_override, NULL, 1);
>> + return 0;
>> + }
>> +
>> /* run through all the pmu drivers one at a time */
>> if (!init_power5_pmu())
>> return 0;
>> @@ -2451,4 +2467,23 @@ static int __init init_ppc64_pmu(void)
>> return init_generic_compat_pmu();
>> }
>> early_initcall(init_ppc64_pmu);
>> +
>> +static int __init pmu_setup(char *str)
>> +{
>> + unsigned long val;
>> +
>> + if (!early_cpu_has_feature(CPU_FTR_HVMODE))
>> + return 0;
>> +
>> + pmu_override = true;
>> +
>> + if (kstrtoul(str, 0, &val))
>> + val = 0;
>> +
>> + pmu_override_val = val;
>> +
>> + return 1;
>> +}
>> +__setup("pmu=", pmu_setup);
>> +
>> #endif
>
^ permalink raw reply
* Re: [PATCH v1 14/55] KVM: PPC: Book3S HV: Don't always save PMU for guest capable of nesting
From: Nicholas Piggin @ 2021-08-06 10:32 UTC (permalink / raw)
To: kvm-ppc, Michael Ellerman; +Cc: linuxppc-dev
In-Reply-To: <871r77ni1g.fsf@mpe.ellerman.id.au>
Excerpts from Michael Ellerman's message of August 6, 2021 5:34 pm:
> Nicholas Piggin <npiggin@gmail.com> writes:
>> Revert the workaround added by commit 63279eeb7f93a ("KVM: PPC: Book3S
>> HV: Always save guest pmu for guest capable of nesting").
>>
>> Nested capable guests running with the earlier commit ("KVM: PPC: Book3S
>> HV Nested: Indicate guest PMU in-use in VPA") will now indicate the PMU
>> in-use status of their guests, which means the parent does not need to
>> unconditionally save the PMU for nested capable guests.
>>
>> This will cause the PMU to break for nested guests when running older
>> nested hypervisor guests under a kernel with this change. It's unclear
>> there's an easy way to avoid that, so this could wait for a release or
>> so for the fix to filter into stable kernels.
>
> I'm not sure PMU inside nested guests is getting much use, but I don't
> think we can break this quite so casually :)
>
> Especially as the failure mode will be PMU counts that don't match
> reality, which is hard to diagnose. It took nearly a year for us to find
> the original bug.
>
> I think we need to hold this back for a while.
>
> We could put it under a CONFIG option, and then flip that option to off
> at some point in the future.
Okay that might be a good compromise, I'll do that.
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v1 11/55] powerpc/time: add API for KVM to re-arm the host timer/decrementer
From: Nicholas Piggin @ 2021-08-06 10:30 UTC (permalink / raw)
To: Christophe Leroy, kvm-ppc; +Cc: linuxppc-dev
In-Reply-To: <370398a9-4429-285e-4a0f-33759f39b2fc@csgroup.eu>
Excerpts from Christophe Leroy's message of August 5, 2021 5:22 pm:
>
>
> Le 26/07/2021 à 05:49, Nicholas Piggin a écrit :
>> Rather than have KVM look up the host timer and fiddle with the
>> irq-work internal details, have the powerpc/time.c code provide a
>> function for KVM to re-arm the Linux timer code when exiting a
>> guest.
>>
>> This is implementation has an improvement over existing code of
>> marking a decrementer interrupt as soft-pending if a timer has
>> expired, rather than setting DEC to a -ve value, which tended to
>> cause host timers to take two interrupts (first hdec to exit the
>> guest, then the immediate dec).
>>
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>> ---
>> arch/powerpc/include/asm/time.h | 16 +++-------
>> arch/powerpc/kernel/time.c | 52 +++++++++++++++++++++++++++------
>> arch/powerpc/kvm/book3s_hv.c | 7 ++---
>> 3 files changed, 49 insertions(+), 26 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
>> index 69b6be617772..924b2157882f 100644
>> --- a/arch/powerpc/include/asm/time.h
>> +++ b/arch/powerpc/include/asm/time.h
>> @@ -99,18 +99,6 @@ extern void div128_by_32(u64 dividend_high, u64 dividend_low,
>> extern void secondary_cpu_time_init(void);
>> extern void __init time_init(void);
>>
>> -#ifdef CONFIG_PPC64
>> -static inline unsigned long test_irq_work_pending(void)
>> -{
>> - unsigned long x;
>> -
>> - asm volatile("lbz %0,%1(13)"
>> - : "=r" (x)
>> - : "i" (offsetof(struct paca_struct, irq_work_pending)));
>> - return x;
>> -}
>> -#endif
>> -
>> DECLARE_PER_CPU(u64, decrementers_next_tb);
>>
>> static inline u64 timer_get_next_tb(void)
>> @@ -118,6 +106,10 @@ static inline u64 timer_get_next_tb(void)
>> return __this_cpu_read(decrementers_next_tb);
>> }
>>
>> +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
>> +void timer_rearm_host_dec(u64 now);
>> +#endif
>> +
>> /* Convert timebase ticks to nanoseconds */
>> unsigned long long tb_to_ns(unsigned long long tb_ticks);
>>
>> diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
>> index 72d872b49167..016828b7401b 100644
>> --- a/arch/powerpc/kernel/time.c
>> +++ b/arch/powerpc/kernel/time.c
>> @@ -499,6 +499,16 @@ EXPORT_SYMBOL(profile_pc);
>> * 64-bit uses a byte in the PACA, 32-bit uses a per-cpu variable...
>> */
>> #ifdef CONFIG_PPC64
>> +static inline unsigned long test_irq_work_pending(void)
>> +{
>> + unsigned long x;
>> +
>> + asm volatile("lbz %0,%1(13)"
>> + : "=r" (x)
>> + : "i" (offsetof(struct paca_struct, irq_work_pending)));
>
> Can we just use READ_ONCE() instead of hard coding the read ?
Good question, probably yes. Probably calls for its own patch series,
e.g., hw_irq.h has all similar paca accesses.
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v1 02/55] KVM: PPC: Book3S HV P9: Fixes for TM softpatch interrupt
From: Nicholas Piggin @ 2021-08-06 10:25 UTC (permalink / raw)
To: kvm-ppc, Michael Ellerman; +Cc: linuxppc-dev
In-Reply-To: <87a6lvnzin.fsf@mpe.ellerman.id.au>
Excerpts from Michael Ellerman's message of August 6, 2021 11:16 am:
> Nicholas Piggin <npiggin@gmail.com> writes:
>> The softpatch interrupt sets HSRR0 to the faulting instruction +4, so
>> it should subtract 4 for the faulting instruction address. Also have it
>> emulate and deliver HFAC interrupts correctly, which is important for
>> nested HV and facility demand-faulting in future.
>
> The nip being off by 4 sounds bad. But I guess it's not that big a deal
> because it's only used for reporting the instruction address?
Yeah currently I think so. It's not that bad of a bug.
>
> Would also be good to have some more explanation of why it's OK to
> change from illegal to HFAC, which is a guest visible change.
Good point. Again for now it doesn't really matter because the HFAC
handler turns everything (except msgsndp) into a sigill anyway, so
becomes important when we start using HFACs. Put that way I'll probably
split it out.
>
>> diff --git a/arch/powerpc/kvm/book3s_hv_tm.c b/arch/powerpc/kvm/book3s_hv_tm.c
>> index cc90b8b82329..e4fd4a9dee08 100644
>> --- a/arch/powerpc/kvm/book3s_hv_tm.c
>> +++ b/arch/powerpc/kvm/book3s_hv_tm.c
>> @@ -74,19 +74,23 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
>> case PPC_INST_RFEBB:
>> if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
>> /* generate an illegal instruction interrupt */
>> + vcpu->arch.regs.nip -= 4;
>> kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
>> return RESUME_GUEST;
>> }
>> /* check EBB facility is available */
>> if (!(vcpu->arch.hfscr & HFSCR_EBB)) {
>> - /* generate an illegal instruction interrupt */
>> - kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
>> - return RESUME_GUEST;
>> + vcpu->arch.regs.nip -= 4;
>> + vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;
>> + vcpu->arch.hfscr |= (u64)FSCR_EBB_LG << 56;
>> + vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;
>> + return -1; /* rerun host interrupt handler */
>
> This is EBB not TM. Probably OK to leave it in this patch as long as
> it's mentioned in the change log?
It is, but you can get a softpatch interrupt on rfebb changing TM state.
Although I haven't actually tested to see if you get a softpatch when
HFSCR disables EBB or the hardware just gives you the HFAC. For that
matter, same for all the other facility tests.
Thanks,
Nick
>
>> }
>> if ((msr & MSR_PR) && !(vcpu->arch.fscr & FSCR_EBB)) {
>> /* generate a facility unavailable interrupt */
>> - vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
>> - ((u64)FSCR_EBB_LG << 56);
>> + vcpu->arch.regs.nip -= 4;
>> + vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;
>> + vcpu->arch.fscr |= (u64)FSCR_EBB_LG << 56;
>
> Same.
>
>
> cheers
>
^ permalink raw reply
* Re: [PATCH v2 2/3] KVM: PPC: Book3S HV: Add sanity check to copy_tofrom_guest
From: Nicholas Piggin @ 2021-08-06 10:10 UTC (permalink / raw)
To: Fabiano Rosas, kvm-ppc; +Cc: christophe.leroy, linuxppc-dev
In-Reply-To: <20210805212616.2641017-3-farosas@linux.ibm.com>
Excerpts from Fabiano Rosas's message of August 6, 2021 7:26 am:
> Both paths into __kvmhv_copy_tofrom_guest_radix ensure that we arrive
> with an effective address that is smaller than our total addressable
> space and addresses quadrant 0.
>
> - The H_COPY_TOFROM_GUEST hypercall path rejects the call with
> H_PARAMETER if the effective address has any of the twelve most
> significant bits set.
>
> - The kvmhv_copy_tofrom_guest_radix path clears the top twelve bits
> before calling the internal function.
>
> Although the callers make sure that the effective address is sane, any
> future use of the function is exposed to a programming error, so add a
> sanity check.
We possibly should put these into #defines in radix pgtable headers
somewhere but KVM already open codes them so this is good for now.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>
> Suggested-by: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> arch/powerpc/kvm/book3s_64_mmu_radix.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c b/arch/powerpc/kvm/book3s_64_mmu_radix.c
> index 44eb7b1ef289..1b1c9e9e539b 100644
> --- a/arch/powerpc/kvm/book3s_64_mmu_radix.c
> +++ b/arch/powerpc/kvm/book3s_64_mmu_radix.c
> @@ -44,6 +44,9 @@ unsigned long __kvmhv_copy_tofrom_guest_radix(int lpid, int pid,
> (to != NULL) ? __pa(to): 0,
> (from != NULL) ? __pa(from): 0, n);
>
> + if (eaddr & (0xFFFUL << 52))
> + return ret;
> +
> quadrant = 1;
> if (!pid)
> quadrant = 2;
> --
> 2.29.2
>
>
^ permalink raw reply
* Re: [PATCH v2 1/3] KVM: PPC: Book3S HV: Fix copy_tofrom_guest routines
From: Nicholas Piggin @ 2021-08-06 10:09 UTC (permalink / raw)
To: Fabiano Rosas, kvm-ppc; +Cc: christophe.leroy, linuxppc-dev
In-Reply-To: <20210805212616.2641017-2-farosas@linux.ibm.com>
Excerpts from Fabiano Rosas's message of August 6, 2021 7:26 am:
> The __kvmhv_copy_tofrom_guest_radix function was introduced along with
> nested HV guest support. It uses the platform's Radix MMU quadrants to
> provide a nested hypervisor with fast access to its nested guests
> memory (H_COPY_TOFROM_GUEST hypercall). It has also since been added
> as a fast path for the kvmppc_ld/st routines which are used during
> instruction emulation.
>
> The commit def0bfdbd603 ("powerpc: use probe_user_read() and
> probe_user_write()") changed the low level copy function from
> raw_copy_from_user to probe_user_read, which adds a check to
> access_ok. In powerpc that is:
>
> static inline bool __access_ok(unsigned long addr, unsigned long size)
> {
> return addr < TASK_SIZE_MAX && size <= TASK_SIZE_MAX - addr;
> }
>
> and TASK_SIZE_MAX is 0x0010000000000000UL for 64-bit, which means that
> setting the two MSBs of the effective address (which correspond to the
> quadrant) now cause access_ok to reject the access.
>
> This was not caught earlier because the most common code path via
> kvmppc_ld/st contains a fallback (kvm_read_guest) that is likely to
> succeed for L1 guests. For nested guests there is no fallback.
>
> Another issue is that probe_user_read (now __copy_from_user_nofault)
> does not return the number of bytes not copied in case of failure, so
> the destination memory is not being cleared anymore in
> kvmhv_copy_from_guest_radix:
>
> ret = kvmhv_copy_tofrom_guest_radix(vcpu, eaddr, to, NULL, n);
> if (ret > 0) <-- always false!
> memset(to + (n - ret), 0, ret);
>
> This patch fixes both issues by skipping access_ok and open-coding the
> low level __copy_to/from_user_inatomic.
>
> Fixes: def0bfdbd603 ("powerpc: use probe_user_read() and probe_user_write()")
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> arch/powerpc/kvm/book3s_64_mmu_radix.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c b/arch/powerpc/kvm/book3s_64_mmu_radix.c
> index b5905ae4377c..44eb7b1ef289 100644
> --- a/arch/powerpc/kvm/book3s_64_mmu_radix.c
> +++ b/arch/powerpc/kvm/book3s_64_mmu_radix.c
> @@ -65,10 +65,12 @@ unsigned long __kvmhv_copy_tofrom_guest_radix(int lpid, int pid,
> }
> isync();
>
> + pagefault_disable();
> if (is_load)
> - ret = copy_from_user_nofault(to, (const void __user *)from, n);
> + ret = __copy_from_user_inatomic(to, (const void __user *)from, n);
> else
> - ret = copy_to_user_nofault((void __user *)to, from, n);
> + ret = __copy_to_user_inatomic((void __user *)to, from, n);
> + pagefault_enable();
>
> /* switch the pid first to avoid running host with unallocated pid */
> if (quadrant == 1 && pid != old_pid)
> --
> 2.29.2
>
>
^ permalink raw reply
* Re: Debian SID kernel doesn't boot on PowerBook 3400c
From: Christophe Leroy @ 2021-08-06 9:58 UTC (permalink / raw)
To: Finn Thain; +Cc: debian-powerpc, linuxppc-dev, Stan Johnson, Nicholas Piggin
In-Reply-To: <c031a1e7-fde7-7c39-d9ff-404157cfc0df@linux-m68k.org>
Le 06/08/2021 à 11:43, Finn Thain a écrit :
> On Fri, 6 Aug 2021, Christophe Leroy wrote:
>
>>>>>>
>>>>>> Can you check if they DO NOT happen at preceding commit c16728835~
>>>>>>
>>>>
>>>> $ git checkout c16728835~
>>>> Previous HEAD position was c16728835eec powerpc/32: Manage KUAP in C
>>>> HEAD is now at 0b45359aa2df powerpc/8xx: Create C version of kuap
>>>> save/restore/check helpers
>>>> $ git am ../message.mbox
>>>> warning: Patch sent with format=flowed; space at the end of lines might be
>>>> lost.
>>>> Applying: powerpc/32: Dismantle EXC_XFER_STD/LITE/TEMPLATE
>>>> $ cp ../dot-config-powermac-5.13 .config
>>>> $ make ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- -j4 clean
>>>> olddefconfig vmlinux
>>>>
>>>> Linux version 5.12.0-rc3-pmac-00077-gc9f6e8dd045
>>>>
>>>> 3) PB 3400c
>>>> Hangs at boot (Mac OS screen)
>>>>
>>>> 4) Wallstreet
>>>> X fails, errors in console log (different than test 2), see
>>>> Wallstreet_console-2.txt.
>>>>
>>>
>>> This log shows that the errors "xfce4-session[1775]: bus error (7)" and
>>> "kernel BUG at arch/powerpc/kernel/interrupt.c:49!" happen prior to commit
>>> c16728835eec ("powerpc/32: Manage KUAP in C").
>>
>> As mentionned by Nic, this is due to r11 being cloberred. For the time being
>> the only r11 clobber identified is the one I have provided a fix for. I'm
>> wondering whether it was applied for all further tests or not.
>>
>
> Your fix was applied to this build with "git am ../message.mbox".
Ok good.
>
>> ...
>>>>
>>>>>
>>>>>> Could you test with CONFIG_PPC_KUAP and CONFIG_PPC_KUAP_DEBUG
>>>> ...
>>>>
>>>> $scripts/config -e CONFIG_PPC_KUAP
>>>> $ scripts/config -e CONFIG_PPC_KUAP_DEBUG
>>>> $ make ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- -j4 clean
>>>> olddefconfig vmlinux
>>>> $ grep CONFIG_PPC_KUAP .config
>>>> CONFIG_PPC_KUAP=y
>>>> CONFIG_PPC_KUAP_DEBUG=y
>>>>
>>>> Linux version 5.12.0-rc3-pmac-00078-g5cac2bc3752
>>>>
>>>> 9) PB 3400c
>>>> Hangs at boot (Mac OS screen)
>>>>
>>>> 10) Wallstreet
>>>> X failed at first login, worked at second login, one error in console
>>>> log ("BUG: Unable to handle kernel instruction fetch"), see
>>>> Wallstreet_console-5.txt.
>>>>
>>>
>>> One might expect to see "Kernel attempted to write user page (b3399774) -
>>> exploit attempt?" again here (see c16728835eec build above) but instead
>>> this log says "Oops: Kernel access of bad area, sig: 11".
>>
>> Maybe the test should be done a second time. As r11 is garbage it may or
>> may not be a user address. If it is a user address the we get "Kernel
>> attempted to write user page". If it is a random kernel address, we
>> likely get "Kernel access of bad area" instead.
>>
>
> Your fix was applied here also.
>
Anyway, it would be worth trying to boot a few times more with the same kernel, because as I said
the value is random, so it may or may not hit userspace, hence the possible difference of message,
either "Kernel attempted to write user page" or "Kernel access of bad area" depending on whether the
address is a user address or not.
I have cooked a tentative fix for that KUAP stuff.
Could you try the branch 'bugtest' at https://github.com/chleroy/linux.git
Thanks
Christophe
^ permalink raw reply
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