* [PATCH v3 0/4] Add mem_hops field in perf_mem_data_src structure
From: Kajol Jain @ 2021-10-06 14:06 UTC (permalink / raw)
To: mpe, linuxppc-dev, linux-kernel, peterz, mingo, acme, jolsa,
namhyung, ak
Cc: mark.rutland, songliubraving, atrajeev, daniel, rnsastry,
alexander.shishkin, kjain, ast, linux-perf-users, yao.jin, maddy,
paulus, kan.liang
Patch set adds a new field called 'mem_hops' in the perf_mem_data_src structure
which can be used to represent intra-node/package or inter-node/off-package
details. This field is of size 3 bits where PERF_MEM_HOPS_{NA, 0..6} value
can be used to present different hop levels data.
Patch 1 of the patch-set adds a comment about current state of
PERF_MEM_LVL_* namespace and remove an extra line present in
perf_mem__lvl_scnprintf function.
Patch 2 & 3 adds tool and kernel side changes to add mem_hops field.
Patch 4 of the patch-set fix the data source encodings to represent
L2.1/L3.1 cache access data for powerpc platform.
Changelog:
v2 -> v3
- Since added field HOPS related to NUMA, update the data presented
by HOPS_0 to denotes accesses from 'remote core, same node' as
suggested by Peter Zijlstra.
- Link to the patchset v2: https://lkml.org/lkml/2021/10/5/271
v1 -> v2:
- Rather then adding new macros for L2.1/L3.1 (same chip, different
core) entries as part of field lvlnum, we are introducing new field
called 'mem_hops' which can be used to get hops
level data(intra-chip/package or inter-chip/off-package details).
As suggested by Peter Zijlstra.
- Using OnChip to denote data accesses from 'another core of same chip'
is not too clear. Update it to 'remote core, same chip' as pointed by
Michael Ellerman.
- Update the fix patch of correcting data source encodings to use new
added field 'mem_hops'
- Link to the patchset v1: https://lkml.org/lkml/2021/9/4/37
Kajol Jain (4):
perf: Add comment about current state of PERF_MEM_LVL_* namespace and
remove an extra line
perf: Add mem_hops field in perf_mem_data_src structure
tools/perf: Add mem_hops field in perf_mem_data_src structure
powerpc/perf: Fix data source encodings for L2.1 and L3.1 accesses
arch/powerpc/perf/isa207-common.c | 26 +++++++++++++++++++++-----
arch/powerpc/perf/isa207-common.h | 2 ++
include/uapi/linux/perf_event.h | 19 ++++++++++++++++---
tools/include/uapi/linux/perf_event.h | 19 ++++++++++++++++---
tools/perf/util/mem-events.c | 20 ++++++++++++++++++--
5 files changed, 73 insertions(+), 13 deletions(-)
--
2.26.2
^ permalink raw reply
* [PATCH v3 1/4] perf: Add comment about current state of PERF_MEM_LVL_* namespace and remove an extra line
From: Kajol Jain @ 2021-10-06 14:06 UTC (permalink / raw)
To: mpe, linuxppc-dev, linux-kernel, peterz, mingo, acme, jolsa,
namhyung, ak
Cc: mark.rutland, songliubraving, atrajeev, daniel, rnsastry,
alexander.shishkin, kjain, ast, linux-perf-users, yao.jin, maddy,
paulus, kan.liang
In-Reply-To: <20211006140654.298352-1-kjain@linux.ibm.com>
Add a comment about PERF_MEM_LVL_* namespace being depricated
to some extent in favour of added PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_}
fields.
Remove an extra line present in perf_mem__lvl_scnprintf function.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
include/uapi/linux/perf_event.h | 8 +++++++-
tools/include/uapi/linux/perf_event.h | 8 +++++++-
tools/perf/util/mem-events.c | 1 -
3 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index f92880a15645..e1701e9c7858 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -1241,7 +1241,13 @@ union perf_mem_data_src {
#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
#define PERF_MEM_OP_SHIFT 0
-/* memory hierarchy (memory level, hit or miss) */
+/*
+ * PERF_MEM_LVL_* namespace being depricated to some extent in the
+ * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields.
+ * Supporting this namespace inorder to not break defined ABIs.
+ *
+ * memory hierarchy (memory level, hit or miss)
+ */
#define PERF_MEM_LVL_NA 0x01 /* not available */
#define PERF_MEM_LVL_HIT 0x02 /* hit level */
#define PERF_MEM_LVL_MISS 0x04 /* miss level */
diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h
index f92880a15645..e1701e9c7858 100644
--- a/tools/include/uapi/linux/perf_event.h
+++ b/tools/include/uapi/linux/perf_event.h
@@ -1241,7 +1241,13 @@ union perf_mem_data_src {
#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
#define PERF_MEM_OP_SHIFT 0
-/* memory hierarchy (memory level, hit or miss) */
+/*
+ * PERF_MEM_LVL_* namespace being depricated to some extent in the
+ * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields.
+ * Supporting this namespace inorder to not break defined ABIs.
+ *
+ * memory hierarchy (memory level, hit or miss)
+ */
#define PERF_MEM_LVL_NA 0x01 /* not available */
#define PERF_MEM_LVL_HIT 0x02 /* hit level */
#define PERF_MEM_LVL_MISS 0x04 /* miss level */
diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c
index f0e75df72b80..ff7289e28192 100644
--- a/tools/perf/util/mem-events.c
+++ b/tools/perf/util/mem-events.c
@@ -320,7 +320,6 @@ int perf_mem__lvl_scnprintf(char *out, size_t sz, struct mem_info *mem_info)
/* already taken care of */
m &= ~(PERF_MEM_LVL_HIT|PERF_MEM_LVL_MISS);
-
if (mem_info && mem_info->data_src.mem_remote) {
strcat(out, "Remote ");
l += 7;
--
2.26.2
^ permalink raw reply related
* [PATCH v3 2/4] perf: Add mem_hops field in perf_mem_data_src structure
From: Kajol Jain @ 2021-10-06 14:06 UTC (permalink / raw)
To: mpe, linuxppc-dev, linux-kernel, peterz, mingo, acme, jolsa,
namhyung, ak
Cc: mark.rutland, songliubraving, atrajeev, daniel, rnsastry,
alexander.shishkin, kjain, ast, linux-perf-users, yao.jin, maddy,
paulus, kan.liang
In-Reply-To: <20211006140654.298352-1-kjain@linux.ibm.com>
Going forward, future generation systems can have more hierarchy
within the node/package level but currently we don't have any data source
encoding field in perf, which can be used to represent this level of data.
Add a new field called 'mem_hops' in the perf_mem_data_src structure
which can be used to represent intra-node/package or inter-node/off-package
details. This field is of size 3 bits where PERF_MEM_HOPS_{NA, 0..6} value
can be used to present different hop levels data.
Also add corresponding macros to define mem_hop field values
and shift value.
Currently we define macro for HOPS_0 which corresponds
to data coming from another core but same node.
For ex: Encodings for mem_hops fields with L2 cache:
L2 - local L2
L2 | REMOTE | HOPS_0 - remote core, same node L2
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
include/uapi/linux/perf_event.h | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index e1701e9c7858..2fc09579e24a 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -1210,14 +1210,16 @@ union perf_mem_data_src {
mem_remote:1, /* remote */
mem_snoopx:2, /* snoop mode, ext */
mem_blk:3, /* access blocked */
- mem_rsvd:21;
+ mem_hops:3, /* hop level */
+ mem_rsvd:18;
};
};
#elif defined(__BIG_ENDIAN_BITFIELD)
union perf_mem_data_src {
__u64 val;
struct {
- __u64 mem_rsvd:21,
+ __u64 mem_rsvd:18,
+ mem_hops:3, /* hop level */
mem_blk:3, /* access blocked */
mem_snoopx:2, /* snoop mode, ext */
mem_remote:1, /* remote */
@@ -1313,6 +1315,11 @@ union perf_mem_data_src {
#define PERF_MEM_BLK_ADDR 0x04 /* address conflict */
#define PERF_MEM_BLK_SHIFT 40
+/* hop level */
+#define PERF_MEM_HOPS_0 0x01 /* remote core, same node */
+/* 2-7 available */
+#define PERF_MEM_HOPS_SHIFT 43
+
#define PERF_MEM_S(a, s) \
(((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
--
2.26.2
^ permalink raw reply related
* [PATCH v3 3/4] tools/perf: Add mem_hops field in perf_mem_data_src structure
From: Kajol Jain @ 2021-10-06 14:06 UTC (permalink / raw)
To: mpe, linuxppc-dev, linux-kernel, peterz, mingo, acme, jolsa,
namhyung, ak
Cc: mark.rutland, songliubraving, atrajeev, daniel, rnsastry,
alexander.shishkin, kjain, ast, linux-perf-users, yao.jin, maddy,
paulus, kan.liang
In-Reply-To: <20211006140654.298352-1-kjain@linux.ibm.com>
Going forward, future generation systems can have more hierarchy
within the node/package level but currently we don't have any data source
encoding field in perf, which can be used to represent this level of data.
Add a new field called 'mem_hops' in the perf_mem_data_src structure
which can be used to represent intra-node/package or inter-node/off-package
details. This field is of size 3 bits where PERF_MEM_HOPS_{NA, 0..6} value
can be used to present different hop levels data.
Also add corresponding macros to define mem_hop field values
and shift value.
Currently we define macro for HOPS_0 which corresponds
to data coming from another core but same node.
Add functionality to represent mem_hop field data in
perf_mem__lvl_scnprintf function with the help of added string
array called mem_hops.
For ex: Encodings for mem_hops fields with L2 cache:
L2 - local L2
L2 | REMOTE | HOPS_0 - remote core, same node L2
Since with the addition of HOPS field, now remote can be used to
denote cache access from the same node but different core, a check
is added in the c2c_decode_stats function to set mrem only when HOPS
is zero along with set remote field.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
tools/include/uapi/linux/perf_event.h | 11 +++++++++--
tools/perf/util/mem-events.c | 19 ++++++++++++++++++-
2 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h
index e1701e9c7858..2fc09579e24a 100644
--- a/tools/include/uapi/linux/perf_event.h
+++ b/tools/include/uapi/linux/perf_event.h
@@ -1210,14 +1210,16 @@ union perf_mem_data_src {
mem_remote:1, /* remote */
mem_snoopx:2, /* snoop mode, ext */
mem_blk:3, /* access blocked */
- mem_rsvd:21;
+ mem_hops:3, /* hop level */
+ mem_rsvd:18;
};
};
#elif defined(__BIG_ENDIAN_BITFIELD)
union perf_mem_data_src {
__u64 val;
struct {
- __u64 mem_rsvd:21,
+ __u64 mem_rsvd:18,
+ mem_hops:3, /* hop level */
mem_blk:3, /* access blocked */
mem_snoopx:2, /* snoop mode, ext */
mem_remote:1, /* remote */
@@ -1313,6 +1315,11 @@ union perf_mem_data_src {
#define PERF_MEM_BLK_ADDR 0x04 /* address conflict */
#define PERF_MEM_BLK_SHIFT 40
+/* hop level */
+#define PERF_MEM_HOPS_0 0x01 /* remote core, same node */
+/* 2-7 available */
+#define PERF_MEM_HOPS_SHIFT 43
+
#define PERF_MEM_S(a, s) \
(((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c
index ff7289e28192..3167b4628b6d 100644
--- a/tools/perf/util/mem-events.c
+++ b/tools/perf/util/mem-events.c
@@ -301,6 +301,16 @@ static const char * const mem_lvlnum[] = {
[PERF_MEM_LVLNUM_NA] = "N/A",
};
+static const char * const mem_hops[] = {
+ "N/A",
+ /*
+ * While printing, 'Remote' will be added to represent
+ * 'Remote core, same node' accesses as remote field need
+ * to be set with mem_hops field.
+ */
+ "core, same node",
+};
+
int perf_mem__lvl_scnprintf(char *out, size_t sz, struct mem_info *mem_info)
{
size_t i, l = 0;
@@ -325,6 +335,9 @@ int perf_mem__lvl_scnprintf(char *out, size_t sz, struct mem_info *mem_info)
l += 7;
}
+ if (mem_info && mem_info->data_src.mem_hops)
+ l += scnprintf(out + l, sz - l, "%s ", mem_hops[mem_info->data_src.mem_hops]);
+
printed = 0;
for (i = 0; m && i < ARRAY_SIZE(mem_lvl); i++, m >>= 1) {
if (!(m & 0x1))
@@ -471,8 +484,12 @@ int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi)
/*
* Skylake might report unknown remote level via this
* bit, consider it when evaluating remote HITMs.
+ *
+ * Incase of power, remote field can also be used to denote cache
+ * accesses from the another core of same node. Hence, setting
+ * mrem only when HOPS is zero along with set remote field.
*/
- bool mrem = data_src->mem_remote;
+ bool mrem = (data_src->mem_remote && !data_src->mem_hops);
int err = 0;
#define HITM_INC(__f) \
--
2.26.2
^ permalink raw reply related
* [PATCH v3 4/4] powerpc/perf: Fix data source encodings for L2.1 and L3.1 accesses
From: Kajol Jain @ 2021-10-06 14:06 UTC (permalink / raw)
To: mpe, linuxppc-dev, linux-kernel, peterz, mingo, acme, jolsa,
namhyung, ak
Cc: mark.rutland, songliubraving, atrajeev, daniel, rnsastry,
alexander.shishkin, kjain, ast, linux-perf-users, yao.jin, maddy,
paulus, kan.liang
In-Reply-To: <20211006140654.298352-1-kjain@linux.ibm.com>
Fix the data source encodings to represent L2.1/L3.1(another core's
L2/L3 on the same node) accesses properly for power10 and older
plaforms.
Add new macros(LEVEL/REM) which can be used to add mem_lvl_num and remote
field data inside perf_mem_data_src structure.
Result in power9 system with patch changes:
localhost:~/linux/tools/perf # ./perf mem report | grep Remote
0.01% 1 252 Remote core, same node L3 or L3 hit [.] 0x0000000000002dd0 producer_consumer [.] 0x00007fff7f25eb90
anon HitM N/A No N/A 0 0
0.01% 1 220 Remote core, same node L3 or L3 hit [.] 0x0000000000002dd0 producer_consumer [.] 0x00007fff77776d90
anon HitM N/A No N/A 0 0
0.01% 1 220 Remote core, same node L3 or L3 hit [.] 0x0000000000002dd0 producer_consumer [.] 0x00007fff817d9410
anon HitM N/A No N/A 0 0
Fixes: 79e96f8f930d ("powerpc/perf: Export memory hierarchy info to user
space")
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
arch/powerpc/perf/isa207-common.c | 26 +++++++++++++++++++++-----
arch/powerpc/perf/isa207-common.h | 2 ++
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index f92bf5f6b74f..7ea873ab2e6f 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -238,11 +238,27 @@ static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
ret |= P(SNOOP, HIT);
break;
case 5:
- ret = PH(LVL, REM_CCE1);
- if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))
- ret |= P(SNOOP, HIT);
- else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))
- ret |= P(SNOOP, HITM);
+ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+ ret = REM | P(HOPS, 0);
+
+ if (sub_idx == 0 || sub_idx == 4)
+ ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT);
+ else if (sub_idx == 1 || sub_idx == 5)
+ ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM);
+ else if (sub_idx == 2 || sub_idx == 6)
+ ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
+ else if (sub_idx == 3 || sub_idx == 7)
+ ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
+ } else {
+ if (sub_idx == 0)
+ ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0);
+ else if (sub_idx == 1)
+ ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0);
+ else if (sub_idx == 2 || sub_idx == 4)
+ ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HIT) | P(HOPS, 0);
+ else if (sub_idx == 3 || sub_idx == 5)
+ ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HITM) | P(HOPS, 0);
+ }
break;
case 6:
ret = PH(LVL, REM_CCE2);
diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h
index 4a2cbc3dc047..ff122603989b 100644
--- a/arch/powerpc/perf/isa207-common.h
+++ b/arch/powerpc/perf/isa207-common.h
@@ -273,6 +273,8 @@
#define P(a, b) PERF_MEM_S(a, b)
#define PH(a, b) (P(LVL, HIT) | P(a, b))
#define PM(a, b) (P(LVL, MISS) | P(a, b))
+#define LEVEL(x) P(LVLNUM, x)
+#define REM P(REMOTE, REMOTE)
int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1);
int isa207_compute_mmcr(u64 event[], int n_ev,
--
2.26.2
^ permalink raw reply related
* [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
The first 10 patches add a new function, of_get_cpu_hwid(), which parses
CPU DT node 'reg' property, and then use it to replace all the open
coded versions of parsing CPU node 'reg' properties.
The last 2 patches add support for populating the cacheinfo 'id' on DT
platforms. The minimum associated CPU hwid is used for the id. The id is
optional, but necessary for resctrl which is being adapted for Arm MPAM.
Tested on arm64. Compile tested on arm, x86 and powerpc.
Rob
Rob Herring (12):
of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes
ARM: Use of_get_cpu_hwid()
ARM: broadcom: Use of_get_cpu_hwid()
arm64: Use of_get_cpu_hwid()
csky: Use of_get_cpu_hwid()
openrisc: Use of_get_cpu_hwid()
powerpc: Use of_get_cpu_hwid()
riscv: Use of_get_cpu_hwid()
sh: Use of_get_cpu_hwid()
x86: dt: Use of_get_cpu_hwid()
cacheinfo: Allow for >32-bit cache 'id'
cacheinfo: Set cache 'id' based on DT data
arch/arm/kernel/devtree.c | 22 ++-------------------
arch/arm/mach-bcm/bcm63xx_pmb.c | 6 +++---
arch/arm64/kernel/smp.c | 31 ++----------------------------
arch/csky/kernel/smp.c | 6 ++----
arch/openrisc/kernel/smp.c | 6 +-----
arch/powerpc/kernel/smp.c | 7 +------
arch/riscv/kernel/cpu.c | 3 ++-
arch/sh/boards/of-generic.c | 5 ++---
arch/x86/kernel/devicetree.c | 5 ++---
drivers/base/cacheinfo.c | 34 ++++++++++++++++++++++++++++++++-
drivers/of/base.c | 22 +++++++++++++++++++++
include/linux/cacheinfo.h | 2 +-
include/linux/of.h | 1 +
13 files changed, 74 insertions(+), 76 deletions(-)
--
2.30.2
^ permalink raw reply
* [PATCH 03/12] ARM: broadcom: Use of_get_cpu_hwid()
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Replace open coded parsing of CPU nodes 'reg' property with
of_get_cpu_hwid().
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Rob Herring <robh@kernel.org>
---
arch/arm/mach-bcm/bcm63xx_pmb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-bcm/bcm63xx_pmb.c b/arch/arm/mach-bcm/bcm63xx_pmb.c
index 0e5a05bac3ea..003f1472ab45 100644
--- a/arch/arm/mach-bcm/bcm63xx_pmb.c
+++ b/arch/arm/mach-bcm/bcm63xx_pmb.c
@@ -91,10 +91,10 @@ static int bcm63xx_pmb_get_resources(struct device_node *dn,
struct of_phandle_args args;
int ret;
- ret = of_property_read_u32(dn, "reg", cpu);
- if (ret) {
+ *cpu = of_get_cpu_hwid(dn, 0);
+ if (*cpu == ~0U) {
pr_err("CPU is missing a reg node\n");
- return ret;
+ return -ENODEV;
}
ret = of_parse_phandle_with_args(dn, "resets", "#reset-cells",
--
2.30.2
^ permalink raw reply related
* [PATCH 01/12] of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
There are various open coded implementions parsing the CPU node 'reg'
property which contains the CPU's hardware ID. Introduce a new function,
of_get_cpu_hwid(), to read the hardware ID.
All the callers should be DT only code, so no need for an empty
function.
Cc: Frank Rowand <frowand.list@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
drivers/of/base.c | 22 ++++++++++++++++++++++
include/linux/of.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index f720c0d246f2..e587ab44be22 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -286,6 +286,28 @@ const void *of_get_property(const struct device_node *np, const char *name,
}
EXPORT_SYMBOL(of_get_property);
+/**
+ * of_get_cpu_hwid - Get the hardware ID from a CPU device node
+ *
+ * @cpun: CPU number(logical index) for which device node is required
+ * @thread: The local thread number to get the hardware ID for.
+ *
+ * Return: The hardware ID for the CPU node or ~0ULL if not found.
+ */
+u64 of_get_cpu_hwid(struct device_node *cpun, unsigned int thread)
+{
+ const __be32 *cell;
+ int ac, len;
+
+ ac = of_n_addr_cells(cpun);
+ cell = of_get_property(cpun, "reg", &len);
+ if (!cell || !ac || ((sizeof(*cell) * ac * (thread + 1)) > len))
+ return ~0ULL;
+
+ cell += ac * thread;
+ return of_read_number(cell, ac);
+}
+
/*
* arch_match_cpu_phys_id - Match the given logical CPU and physical id
*
diff --git a/include/linux/of.h b/include/linux/of.h
index 6f1c41f109bb..807f8168dad9 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -353,6 +353,7 @@ extern struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
extern struct device_node *of_get_next_cpu_node(struct device_node *prev);
extern struct device_node *of_get_cpu_state_node(struct device_node *cpu_node,
int index);
+extern u64 of_get_cpu_hwid(struct device_node *cpun, unsigned int thread);
#define for_each_property_of_node(dn, pp) \
for (pp = dn->properties; pp != NULL; pp = pp->next)
--
2.30.2
^ permalink raw reply related
* [PATCH 05/12] csky: Use of_get_cpu_hwid()
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Replace open coded parsing of CPU nodes 'reg' property with
of_get_cpu_hwid().
Cc: Guo Ren <guoren@kernel.org>
Cc: linux-csky@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
arch/csky/kernel/smp.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c
index e2993539af8e..6bb38bc2f39b 100644
--- a/arch/csky/kernel/smp.c
+++ b/arch/csky/kernel/smp.c
@@ -180,15 +180,13 @@ void __init setup_smp_ipi(void)
void __init setup_smp(void)
{
struct device_node *node = NULL;
- int cpu;
+ unsigned int cpu;
for_each_of_cpu_node(node) {
if (!of_device_is_available(node))
continue;
- if (of_property_read_u32(node, "reg", &cpu))
- continue;
-
+ cpu = of_get_cpu_hwid(node, 0);
if (cpu >= NR_CPUS)
continue;
--
2.30.2
^ permalink raw reply related
* [PATCH 04/12] arm64: Use of_get_cpu_hwid()
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Replace the open coded parsing of CPU nodes' 'reg' property with
of_get_cpu_hwid().
This change drops an error message for missing 'reg' property, but that
should not be necessary as the DT tools will ensure 'reg' is present.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
---
arch/arm64/kernel/smp.c | 31 ++-----------------------------
1 file changed, 2 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 6f6ff072acbd..c5cebc406d24 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -466,33 +466,6 @@ void __init smp_prepare_boot_cpu(void)
kasan_init_hw_tags();
}
-static u64 __init of_get_cpu_mpidr(struct device_node *dn)
-{
- const __be32 *cell;
- u64 hwid;
-
- /*
- * A cpu node with missing "reg" property is
- * considered invalid to build a cpu_logical_map
- * entry.
- */
- cell = of_get_property(dn, "reg", NULL);
- if (!cell) {
- pr_err("%pOF: missing reg property\n", dn);
- return INVALID_HWID;
- }
-
- hwid = of_read_number(cell, of_n_addr_cells(dn));
- /*
- * Non affinity bits must be set to 0 in the DT
- */
- if (hwid & ~MPIDR_HWID_BITMASK) {
- pr_err("%pOF: invalid reg property\n", dn);
- return INVALID_HWID;
- }
- return hwid;
-}
-
/*
* Duplicate MPIDRs are a recipe for disaster. Scan all initialized
* entries and check for duplicates. If any is found just ignore the
@@ -656,9 +629,9 @@ static void __init of_parse_and_init_cpus(void)
struct device_node *dn;
for_each_of_cpu_node(dn) {
- u64 hwid = of_get_cpu_mpidr(dn);
+ u64 hwid = of_get_cpu_hwid(dn, 0);
- if (hwid == INVALID_HWID)
+ if (hwid & ~MPIDR_HWID_BITMASK)
goto next;
if (is_mpidr_duplicate(cpu_count, hwid)) {
--
2.30.2
^ permalink raw reply related
* [PATCH 02/12] ARM: Use of_get_cpu_hwid()
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Replace the open coded parsing of CPU nodes' 'reg' property with
of_get_cpu_hwid().
This change drops an error message for missing 'reg' property, but that
should not be necessary as the DT tools will ensure 'reg' is present.
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Rob Herring <robh@kernel.org>
---
arch/arm/kernel/devtree.c | 22 ++--------------------
1 file changed, 2 insertions(+), 20 deletions(-)
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 28311dd0fee6..02839d8b6202 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -84,33 +84,15 @@ void __init arm_dt_init_cpu_maps(void)
return;
for_each_of_cpu_node(cpu) {
- const __be32 *cell;
- int prop_bytes;
- u32 hwid;
+ u32 hwid = of_get_cpu_hwid(cpu, 0);
pr_debug(" * %pOF...\n", cpu);
- /*
- * A device tree containing CPU nodes with missing "reg"
- * properties is considered invalid to build the
- * cpu_logical_map.
- */
- cell = of_get_property(cpu, "reg", &prop_bytes);
- if (!cell || prop_bytes < sizeof(*cell)) {
- pr_debug(" * %pOF missing reg property\n", cpu);
- of_node_put(cpu);
- return;
- }
/*
* Bits n:24 must be set to 0 in the DT since the reg property
* defines the MPIDR[23:0].
*/
- do {
- hwid = be32_to_cpu(*cell++);
- prop_bytes -= sizeof(*cell);
- } while (!hwid && prop_bytes > 0);
-
- if (prop_bytes || (hwid & ~MPIDR_HWID_BITMASK)) {
+ if (hwid & ~MPIDR_HWID_BITMASK) {
of_node_put(cpu);
return;
}
--
2.30.2
^ permalink raw reply related
* [PATCH 06/12] openrisc: Use of_get_cpu_hwid()
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Replace open coded parsing of CPU nodes' 'reg' property with
of_get_cpu_hwid().
Cc: Jonas Bonn <jonas@southpole.se>
Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Cc: Stafford Horne <shorne@gmail.com>
Cc: openrisc@lists.librecores.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
arch/openrisc/kernel/smp.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index 415e209732a3..7d5a4f303a5a 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -65,11 +65,7 @@ void __init smp_init_cpus(void)
u32 cpu_id;
for_each_of_cpu_node(cpu) {
- if (of_property_read_u32(cpu, "reg", &cpu_id)) {
- pr_warn("%s missing reg property", cpu->full_name);
- continue;
- }
-
+ cpu_id = of_get_cpu_hwid(cpu);
if (cpu_id < NR_CPUS)
set_cpu_possible(cpu_id, true);
}
--
2.30.2
^ permalink raw reply related
* [PATCH 07/12] powerpc: Use of_get_cpu_hwid()
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Replace open coded parsing of CPU nodes' 'reg' property with
of_get_cpu_hwid().
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
arch/powerpc/kernel/smp.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 9cc7d3dbf439..d96b0e361a73 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -1313,18 +1313,13 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle)
int cpu_to_core_id(int cpu)
{
struct device_node *np;
- const __be32 *reg;
int id = -1;
np = of_get_cpu_node(cpu, NULL);
if (!np)
goto out;
- reg = of_get_property(np, "reg", NULL);
- if (!reg)
- goto out;
-
- id = be32_to_cpup(reg);
+ id = of_get_cpu_hwid(np, 0);
out:
of_node_put(np);
return id;
--
2.30.2
^ permalink raw reply related
* [PATCH 08/12] riscv: Use of_get_cpu_hwid()
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Replace open coded parsing of CPU nodes' 'reg' property with
of_get_cpu_hwid().
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
arch/riscv/kernel/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 6d59e6906fdd..f13b2c9ea912 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -22,7 +22,8 @@ int riscv_of_processor_hartid(struct device_node *node)
return -ENODEV;
}
- if (of_property_read_u32(node, "reg", &hart)) {
+ hart = of_get_cpu_hwid(node, 0);
+ if (hart == ~0U) {
pr_warn("Found CPU without hart ID\n");
return -ENODEV;
}
--
2.30.2
^ permalink raw reply related
* [PATCH 09/12] sh: Use of_get_cpu_hwid()
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Replace open coded parsing of CPU nodes' 'reg' property with
of_get_cpu_hwid().
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Rich Felker <dalias@libc.org>
Cc: linux-sh@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
arch/sh/boards/of-generic.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
index 921d76fc3358..f7f3e618e85b 100644
--- a/arch/sh/boards/of-generic.c
+++ b/arch/sh/boards/of-generic.c
@@ -62,9 +62,8 @@ static void sh_of_smp_probe(void)
init_cpu_possible(cpumask_of(0));
for_each_of_cpu_node(np) {
- const __be32 *cell = of_get_property(np, "reg", NULL);
- u64 id = -1;
- if (cell) id = of_read_number(cell, of_n_addr_cells(np));
+ u64 id = of_get_cpu_hwid(np, 0);
+
if (id < NR_CPUS) {
if (!method)
of_property_read_string(np, "enable-method", &method);
--
2.30.2
^ permalink raw reply related
* [PATCH 10/12] x86: dt: Use of_get_cpu_hwid()
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Replace open coded parsing of CPU nodes' 'reg' property with
of_get_cpu_hwid().
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: x86@kernel.org
Cc: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
arch/x86/kernel/devicetree.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 6a4cb71c2498..3aa1e99df2a9 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -139,12 +139,11 @@ static void __init dtb_cpu_setup(void)
{
struct device_node *dn;
u32 apic_id, version;
- int ret;
version = GET_APIC_VERSION(apic_read(APIC_LVR));
for_each_of_cpu_node(dn) {
- ret = of_property_read_u32(dn, "reg", &apic_id);
- if (ret < 0) {
+ apic_id = of_get_cpu_hwid(dn, 0);
+ if (apic_id == ~0U) {
pr_warn("%pOF: missing local APIC ID\n", dn);
continue;
}
--
2.30.2
^ permalink raw reply related
* [PATCH 11/12] cacheinfo: Allow for >32-bit cache 'id'
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
In preparation to set the cache 'id' based on the CPU h/w ids, allow for
64-bit bit 'id' value. The only case that needs this is arm64, so
unsigned long is sufficient.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
---
drivers/base/cacheinfo.c | 8 +++++++-
include/linux/cacheinfo.h | 2 +-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index dad296229161..66d10bdb863b 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -366,13 +366,19 @@ static ssize_t file_name##_show(struct device *dev, \
return sysfs_emit(buf, "%u\n", this_leaf->object); \
}
-show_one(id, id);
show_one(level, level);
show_one(coherency_line_size, coherency_line_size);
show_one(number_of_sets, number_of_sets);
show_one(physical_line_partition, physical_line_partition);
show_one(ways_of_associativity, ways_of_associativity);
+static ssize_t id_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct cacheinfo *this_leaf = dev_get_drvdata(dev);
+
+ return sysfs_emit(buf, "%lu\n", this_leaf->id);
+}
+
static ssize_t size_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 2f909ed084c6..b2e7f3e40204 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -48,7 +48,7 @@ extern unsigned int coherency_max_size;
* keeping, the remaining members form the core properties of the cache
*/
struct cacheinfo {
- unsigned int id;
+ unsigned long id;
enum cache_type type;
unsigned int level;
unsigned int coherency_line_size;
--
2.30.2
^ permalink raw reply related
* [PATCH 12/12] cacheinfo: Set cache 'id' based on DT data
From: Rob Herring @ 2021-10-06 16:43 UTC (permalink / raw)
To: Russell King, James Morse, Catalin Marinas, Will Deacon, Guo Ren,
Jonas Bonn, Stefan Kristiansson, Stafford Horne, Michael Ellerman,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yoshinori Sato,
Rich Felker, x86, Greg Kroah-Hartman
Cc: devicetree, Florian Fainelli, Scott Branden, Rafael J. Wysocki,
linux-sh, Ray Jui, H. Peter Anvin, linux-kernel, linux-csky,
openrisc, linuxppc-dev, Ingo Molnar, Paul Mackerras,
Borislav Petkov, bcm-kernel-feedback-list, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Use the minimum CPU h/w id of the CPUs associated with the cache for the
cache 'id'. This will provide a stable id value for a given system. As
we need to check all possible CPUs, we can't use the shared_cpu_map
which is just online CPUs. As there's not a cache to CPUs mapping in DT,
we have to walk all CPU nodes and then walk cache levels.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
---
drivers/base/cacheinfo.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 66d10bdb863b..44547fd96f72 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -136,6 +136,31 @@ static bool cache_node_is_unified(struct cacheinfo *this_leaf,
return of_property_read_bool(np, "cache-unified");
}
+static void cache_of_set_id(struct cacheinfo *this_leaf, struct device_node *np)
+{
+ struct device_node *cpu;
+ unsigned long min_id = ~0UL;
+
+ for_each_of_cpu_node(cpu) {
+ struct device_node *cache_node = cpu;
+ u64 id = of_get_cpu_hwid(cache_node, 0);
+
+ while ((cache_node = of_find_next_cache_node(cache_node))) {
+ if ((cache_node == np) && (id < min_id)) {
+ min_id = id;
+ of_node_put(cache_node);
+ break;
+ }
+ of_node_put(cache_node);
+ }
+ }
+
+ if (min_id != ~0UL) {
+ this_leaf->id = min_id;
+ this_leaf->attributes |= CACHE_ID;
+ }
+}
+
static void cache_of_set_props(struct cacheinfo *this_leaf,
struct device_node *np)
{
@@ -151,6 +176,7 @@ static void cache_of_set_props(struct cacheinfo *this_leaf,
cache_get_line_size(this_leaf, np);
cache_nr_sets(this_leaf, np);
cache_associativity(this_leaf);
+ cache_of_set_id(this_leaf, np);
}
static int cache_setup_of_node(unsigned int cpu)
--
2.30.2
^ permalink raw reply related
* Re: [PATCH] perf vendor events power10: Add metric events json file for power10 platform
From: Paul A. Clarke @ 2021-10-06 17:32 UTC (permalink / raw)
To: Kajol Jain
Cc: maddy, rnsastry, linuxppc-dev, linux-kernel, acme,
linux-perf-users, atrajeev, jolsa
In-Reply-To: <20211006073119.276340-1-kjain@linux.ibm.com>
Kajol,
On Wed, Oct 06, 2021 at 01:01:19PM +0530, Kajol Jain wrote:
> Add pmu metric json file for power10 platform.
Thanks for producing this! A few minor corrections, plus a number of
stylistic comments below...
> Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
> ---
> .../arch/powerpc/power10/metrics.json | 772 ++++++++++++++++++
> 1 file changed, 772 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/metrics.json
>
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/metrics.json b/tools/perf/pmu-events/arch/powerpc/power10/metrics.json
> new file mode 100644
> index 000000000000..028c9777a516
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/metrics.json
> @@ -0,0 +1,772 @@
> +[
> + {
> + "BriefDescription": "Percentage of cycles that are run cycles",
> + "MetricExpr": "PM_RUN_CYC / PM_CYC * 100",
> + "MetricGroup": "General",
> + "MetricName": "RUN_CYCLES_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Average cycles per completed instruction",
> + "MetricExpr": "PM_CYC / PM_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "CYCLES_PER_INSTRUCTION"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled for any reason",
> + "MetricExpr": "PM_DISP_STALL_CYC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled because there was a flush",
> + "MetricExpr": "PM_DISP_STALL_FLUSH / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_FLUSH_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled because the MMU was handling a translation miss",
> + "MetricExpr": "PM_DISP_STALL_TRANSLATION / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_TRANSLATION_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled waiting to resolve an instruction ERAT miss",
> + "MetricExpr": "PM_DISP_STALL_IERAT_ONLY_MISS / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_IERAT_ONLY_MISS_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled waiting to resolve an instruction TLB miss",
> + "MetricExpr": "PM_DISP_STALL_ITLB_MISS / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_ITLB_MISS_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled due to an icache miss",
> + "MetricExpr": "PM_DISP_STALL_IC_MISS / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_IC_MISS_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled while the instruction was fetched form the local L2",
s/form/from/
> + "MetricExpr": "PM_DISP_STALL_IC_L2 / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_IC_L2_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled while the instruction was fetched form the local L3",
s/form/from/
> + "MetricExpr": "PM_DISP_STALL_IC_L3 / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_IC_L3_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled while the instruction was fetched from any source beyond the local L3",
> + "MetricExpr": "PM_DISP_STALL_IC_L3MISS / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_IC_L3MISS_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled due to an icache miss after a branch mispredict",
> + "MetricExpr": "PM_DISP_STALL_BR_MPRED_ICMISS / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_BR_MPRED_ICMISS_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled while instruction was fetched from the local L2 after suffering a branch mispredict",
> + "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L2 / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_BR_MPRED_IC_L2_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled while instruction was fetched from the local L3 after suffering a branch mispredict",
> + "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L3 / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_BR_MPRED_IC_L3_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled while instruction was fetched from any source beyond the local L3 after suffering a branch mispredict",
extra space after "beyond"
> + "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L3MISS / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_BR_MPRED_IC_L3MISS_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled due to a branch mispredict",
> + "MetricExpr": "PM_DISP_STALL_BR_MPRED / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_BR_MPRED_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch for any reason",
s/ntc/NTC/ or "next-to-complete"
I do see uses of "NTC" below.
Same comment for other instances of "ntc", below...
> + "MetricExpr": "PM_DISP_STALL_HELD_CYC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_HELD_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch",
> + "MetricExpr": "PM_DISP_STALL_HELD_SYNC_CYC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISP_HELD_STALL_SYNC_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch while waiting on the scoreboard",
> + "MetricExpr": "PM_DISP_STALL_HELD_SCOREBOARD_CYC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISP_HELD_STALL_SCOREBOARD_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch due to issue q full",
s/q/queue/
> + "MetricExpr": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISP_HELD_STALL_ISSQ_FULL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch because the mapper/SRB was full",
> + "MetricExpr": "PM_DISP_STALL_HELD_RENAME_CYC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_HELD_RENAME_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch because the STF mapper/SRB was full",
> + "MetricExpr": "PM_DISP_STALL_HELD_STF_MAPPER_CYC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_HELD_STF_MAPPER_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch because the XVFC mapper/SRB was full",
> + "MetricExpr": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_HELD_XVFC_MAPPER_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch for any other reason",
> + "MetricExpr": "PM_DISP_STALL_HELD_OTHER_CYC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_HELD_OTHER_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction has been dispatched but not issued for any reason",
> + "MetricExpr": "PM_ISSUE_STALL / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "ISSUE_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting to be finished in one of the execution units",
> + "MetricExpr": "PM_EXEC_STALL / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "EXECUTION_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction spent executing an NTC instruction that gets flushed some time after dispatch",
> + "MetricExpr": "PM_EXEC_STALL_NTC_FLUSH / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "NTC_FLUSH_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the instruction finishes at dispatch",
I'm not sure what that means.
> + "MetricExpr": "PM_EXEC_STALL_FIN_AT_DISP / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "FIN_AT_DISP_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is executing in the branch unit",
> + "MetricExpr": "PM_EXEC_STALL_BRU / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "BRU_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is a simple fixed point instr that is executing in the lsu unit",
s/instr/instruction/
s/lsu unit/LSU/
> + "MetricExpr": "PM_EXEC_STALL_SIMPLE_FX / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "SIMPLE_FX_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is executing in the vsu unit",
s/vsu unit/VSU/
> + "MetricExpr": "PM_EXEC_STALL_VSU / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "VSU_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting to be finished in one of the execution units",
> + "MetricExpr": "PM_EXEC_STALL_TRANSLATION / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "TRANSLATION_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is a load or store that suffered a translation miss",
> + "MetricExpr": "PM_EXEC_STALL_DERAT_ONLY_MISS / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DERAT_ONLY_MISS_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is recovering from a TLB miss",
> + "MetricExpr": "PM_EXEC_STALL_DERAT_DTLB_MISS / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DERAT_DTLB_MISS_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is executing in the lsu unit",
s/lsu unit/LSU/
> + "MetricExpr": "PM_EXEC_STALL_LSU / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "LSU_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is a load that is executing in the lsu unit",
s/lsu unit/LSU/
> + "MetricExpr": "PM_EXEC_STALL_LOAD / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "LOAD_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from either the local L2 or local L3",
> + "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3 / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DMISS_L2L3_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from either the local L2 or local L3, with an RC dispatch conflict",
> + "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DMISS_L2L3_CONFLICT_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from either the local L2 or local L3, without an RC dispatch conflict",
> + "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DMISS_L2L3_NOCONFLICT_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from a source beyond the local L2 and local L3",
> + "MetricExpr": "PM_EXEC_STALL_DMISS_L3MISS / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DMISS_L3MISS_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from a neighbor chiplet's L2 or L3 in the same chip",
> + "MetricExpr": "PM_EXEC_STALL_DMISS_L21_L31 / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DMISS_L21_L31_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from local memory, L4 or OpenCapp chip",
Most descriptions put L4 before memory.
(My preference is to use an "Oxford comma", as in "memory, L4, or ..."
(comma after "L4"), but acknowledge there are those who prefer otherwise.)
> + "MetricExpr": "PM_EXEC_STALL_DMISS_LMEM / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DMISS_LMEM_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from a remote chip (cache, L4, memory or CAPP) in the same group",
Is there a distinction between "OpenCapp" and "CAPP"? If not, pick one throughout.
Is this supposed to be "OpenCAPI"?
> + "MetricExpr": "PM_EXEC_STALL_DMISS_OFF_CHIP / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DMISS_OFF_CHIP_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from a distant chip (cache, L4, memory or CAPP chip)",
> + "MetricExpr": "PM_EXEC_STALL_DMISS_OFF_NODE / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DMISS_OFF_NODE_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is executing a TLBIEL instruction",
> + "MetricExpr": "PM_EXEC_STALL_TLBIEL / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "TLBIEL_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is finishing a load after its data has been reloaded from a data source beyond the local L1, OR when the LSU is processing an L1-hit, OR when the NTF instruction merged with another load in the LMQ",
> + "MetricExpr": "PM_EXEC_STALL_LOAD_FINISH / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "LOAD_FINISH_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is a store that is executing in the lsu unit",
s/lsu unit/LSU/
> + "MetricExpr": "PM_EXEC_STALL_STORE / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "STORE_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is in the store unit outside of handling store misses or other special store operations",
s/store unit/LSU/ ?
> + "MetricExpr": "PM_EXEC_STALL_STORE_PIPE / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "STORE_PIPE_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is a store whose cache line was not resident in the L1 and had to wait for allocation of the missing line into the L1",
> + "MetricExpr": "PM_EXEC_STALL_STORE_MISS / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "STORE_MISS_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is a TLBIE instruction waiting for a response from the L2",
> + "MetricExpr": "PM_EXEC_STALL_TLBIE / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "TLBIE_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is executing a PTESYNC instruction",
> + "MetricExpr": "PM_EXEC_STALL_PTESYNC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "PTESYNC_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction cannot complete because the thread was blocked",
> + "MetricExpr": "PM_CMPL_STALL / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "COMPLETION_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction cannot complete because it was interrupted by ANY exception",
> + "MetricExpr": "PM_CMPL_STALL_EXCEPTION / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "EXCEPTION_COMPLETION_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is stuck at finish waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC",
> + "MetricExpr": "PM_CMPL_STALL_MEM_ECC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "MEM_ECC_COMPLETION_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction cannot complete the instruction is a stcx waiting for resolution from the nest",
> + "MetricExpr": "PM_CMPL_STALL_STCX / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "STCX_COMPLETION_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is a LWSYNC instruction waiting to complete",
Sometimes instruction mnemonics are ALL CAPS, like here, and sometimes not,
like "stcx", above. Pick one style. Also pick whether the mnemonic is
followed by "instruction" or not. I prefer including "instruction" for
clarity.
> + "MetricExpr": "PM_CMPL_STALL_LWSYNC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "LWSYNC_COMPLETION_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction is a HWSYNC instruction stuck at finish waiting for a response from the L2",
> + "MetricExpr": "PM_CMPL_STALL_HWSYNC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "HWSYNC_COMPLETION_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction required special handling before completion",
> + "MetricExpr": "PM_CMPL_STALL_SPECIAL / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "SPECIAL_COMPLETION_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, disp_stall_translation or children are miscounting",
Are these "Should equal 0" metrics generally useful?
> + "MetricExpr": "DISPATCHED_TRANSLATION_CPI - (DISPATCHED_IERAT_ONLY_MISS_CPI + DISPATCHED_ITLB_MISS_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_DISPATCHED_TRANSLATION_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, disp_stall_ic_miss or children are miscounting",
> + "MetricExpr": "DISPATCHED_IC_MISS_CPI - (DISPATCHED_IC_L2_CPI + DISPATCHED_IC_L3_CPI + DISPATCHED_IC_L3MISS_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_DISPATCHED_IC_MISS_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, disp_stall_br_mpred_icmiss or children are miscounting",
> + "MetricExpr": "DISPATCHED_BR_MPRED_ICMISS_CPI - (DISPATCHED_BR_MPRED_IC_L2_CPI + DISPATCHED_BR_MPRED_IC_L3_CPI + DISPATCHED_BR_MPRED_IC_L3MISS_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_DISPATCHED_BR_MPRED_ICMISS_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, disp_stall_held_rename or children are miscounting",
> + "MetricExpr": "DISPATCHED_HELD_RENAME_CPI - (DISPATCHED_HELD_STF_MAPPER_CPI + DISPATCHED_HELD_XVFC_MAPPER_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_DISPATCHED_HELD_RENAME_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, disp_stall_held or children are miscounting",
> + "MetricExpr": "DISPATCHED_HELD_CPI - (DISP_HELD_STALL_SYNC_CPI + DISP_HELD_STALL_SCOREBOARD_CPI + DISP_HELD_STALL_ISSQ_FULL_CPI + DISPATCHED_HELD_RENAME_CPI + DISPATCHED_HELD_OTHER_CPI + DISPATCHED_HELD_HALT_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_DISPATCHED_HELD_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, disp_stall or children are miscounting",
> + "MetricExpr": "DISPATCHED_CPI - (DISPATCHED_FLUSH_CPI + DISPATCHED_TRANSLATION_CPI + DISPATCHED_IC_MISS_CPI + DISPATCHED_BR_MPRED_ICMISS_CPI + DISPATCHED_BR_MPRED_CPI + DISPATCHED_HELD_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_DISPATCHED_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, exec_stall_translation or children are miscounting",
> + "MetricExpr": "TRANSLATION_STALL_CPI - (DERAT_ONLY_MISS_STALL_CPI + DERAT_DTLB_MISS_STALL_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_TRANSLATION_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, exec_stall_dmiss_l2l3 or children are miscounting",
> + "MetricExpr": "DMISS_L2L3_STALL_CPI - (DMISS_L2L3_CONFLICT_STALL_CPI + DMISS_L2L3_NOCONFLICT_STALL_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_DMISS_L2L3_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, exec_stall_dmiss_l3miss or children are miscounting",
> + "MetricExpr": "DMISS_L3MISS_STALL_CPI - (DMISS_L21_L31_STALL_CPI + DMISS_LMEM_STALL_CPI + DMISS_OFF_CHIP_STALL_CPI + DMISS_OFF_NODE_STALL_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_DMISS_L3MISS_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, exec_stall_load or children are miscounting",
> + "MetricExpr": "LOAD_STALL_CPI - (DMISS_L2L3_STALL_CPI + DMISS_L3MISS_STALL_CPI + TLBIEL_STALL_CPI + LOAD_FINISH_STALL_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_LOAD_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, exec_stall_store or children are miscounting",
> + "MetricExpr": "STORE_STALL_CPI - (STORE_PIPE_STALL_CPI + STORE_MISS_STALL_CPI + TLBIE_STALL_CPI + PTESYNC_STALL_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_STORE_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, exec_stall_lsu or children are miscounting",
> + "MetricExpr": "LSU_STALL_CPI - (LOAD_STALL_CPI + STORE_STALL_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_LSU_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, cmpl_stall or children are miscounting",
> + "MetricExpr": "COMPLETION_STALL_CPI - (EXCEPTION_COMPLETION_STALL_CPI + MEM_ECC_COMPLETION_STALL_CPI + STCX_COMPLETION_STALL_CPI + LWSYNC_COMPLETION_STALL_CPI + HWSYNC_COMPLETION_STALL_CPI + SPECIAL_COMPLETION_STALL_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_COMPLETION_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, exec_stall or children are miscounting",
> + "MetricExpr": "EXECUTION_STALL_CPI - (NTC_FLUSH_STALL_CPI + FIN_AT_DISP_STALL_CPI + BRU_STALL_CPI + SIMPLE_FX_STALL_CPI + VSU_STALL_CPI + TRANSLATION_STALL_CPI + LSU_STALL_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_STALL_CPI"
> + },
> + {
> + "BriefDescription": "Should equal 0. If not, pm_cyc or children are miscounting",
> + "MetricExpr": "CYCLES_PER_INSTRUCTION - (DISPATCHED_CPI + ISSUE_STALL_CPI + EXECUTION_STALL_CPI + COMPLETION_STALL_CPI)",
> + "MetricGroup": "CPI",
> + "MetricName": "OTHER_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when dispatch was stalled because Fetch was being held, so there was nothing in the pipeline for this thread",
s/Fetch/fetch/
extra space after "held,"
> + "MetricExpr": "PM_DISP_STALL_FETCH / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_FETCH_CPI"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch because of power management",
> + "MetricExpr": "PM_DISP_STALL_HELD_HALT_CYC / PM_RUN_INST_CMPL",
> + "MetricGroup": "CPI",
> + "MetricName": "DISPATCHED_HELD_HALT_CPI"
> + },
> + {
> + "BriefDescription": "Percentage of flushes per completed instruction",
> + "MetricExpr": "PM_FLUSH / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "Others",
> + "MetricName": "FLUSH_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of flushes due to a branch mispredict per instruction",
> + "MetricExpr": "PM_FLUSH_MPRED / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "Others",
> + "MetricName": "BR_MPRED_FLUSH_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of branch mispredictions per completed instruction",
> + "MetricExpr": "PM_BR_MPRED_CMPL / PM_RUN_INST_CMPL",
> + "MetricGroup": "Others",
> + "MetricName": "BRANCH_MISPREDICTION_RATE"
> + },
> + {
> + "BriefDescription": "Percentage of finished loads that missed in the L1",
> + "MetricExpr": "PM_LD_MISS_L1 / PM_LD_REF_L1 * 100",
> + "MetricGroup": "Others",
> + "MetricName": "L1_LD_MISS_RATIO",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of completed instructions that were loads that missed the L1",
> + "MetricExpr": "PM_LD_MISS_L1 / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "Others",
> + "MetricName": "L1_LD_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of instructions when the DPTEG required for the load/store instruction in execution was missing from the TLB",
> + "MetricExpr": "PM_DTLB_MISS / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "Others",
> + "MetricName": "DTLB_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Average number of instruction dispatched per instruction completed",
s/instruction/instrucions/
> + "MetricExpr": "PM_INST_DISP / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "DISPATCH_PER_INST_CMPL"
> + },
> + {
> + "BriefDescription": "Percentage of completed instructions that were a demand load that did not hit in the L1 or L2",
> + "MetricExpr": "PM_DATA_FROM_L2MISS / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "General",
> + "MetricName": "L2_LD_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of completed instructions that were demand fetches that missed the L1 instruction cache",
> + "MetricExpr": "PM_L1_ICACHE_MISS / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "Instruction_Misses",
> + "MetricName": "L1_INST_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of completed instructions that were demand fetches that reloaded from beyond the L3 instruction cache",
> + "MetricExpr": "PM_INST_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "General",
> + "MetricName": "L3_INST_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Average number of completed instructions per cycle",
> + "MetricExpr": "PM_INST_CMPL / PM_CYC",
> + "MetricGroup": "General",
> + "MetricName": "IPC"
> + },
> + {
> + "BriefDescription": "Average number of cycles per completed instruction group",
> + "MetricExpr": "PM_CYC / PM_1PLUS_PPC_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "CYCLES_PER_COMPLETED_INSTRUCTIONS_SET"
> + },
> + {
> + "BriefDescription": "Percentage of cycles when at least 1 instruction dispatched",
> + "MetricExpr": "PM_1PLUS_PPC_DISP / PM_RUN_CYC * 100",
> + "MetricGroup": "General",
> + "MetricName": "CYCLES_ATLEAST_ONE_INST_DISPATCHED",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Rate of finished loads per completed instruction",
Most similar "rate" metrics are using the phrase "average number of".
Do we want to use that here as well? (Applies to all "rate" metrics.)
> + "MetricExpr": "PM_LD_REF_L1 / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "LOADS_PER_INST"
> + },
> + {
> + "BriefDescription": "Rate of finished stores per completed instruction",
> + "MetricExpr": "PM_ST_FIN / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "STORES_PER_INST"
> + },
> + {
> + "BriefDescription": "Percentage of demand loads that reloaded from beyond the L2 per completed instruction",
> + "MetricExpr": "PM_DATA_FROM_L2MISS / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "dL1_Reloads",
> + "MetricName": "DL1_RELOAD_FROM_L2_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of demand loads that reloaded from beyond the L3 per completed instruction",
> + "MetricExpr": "PM_DATA_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "dL1_Reloads",
> + "MetricName": "DL1_RELOAD_FROM_L3_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of DERAT misses with 4k page size per completed run instruction",
When PM_RUN_INST_CMPL is used, sometimes we say "run instruction",
and sometimes we say "completed instruction". Let's pick one.
> + "MetricExpr": "PM_DERAT_MISS_4K / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "Translation",
> + "MetricName": "DERAT_4K_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of DERAT misses with 64k page size per completed run instruction",
> + "MetricExpr": "PM_DERAT_MISS_64K / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "Translation",
> + "MetricName": "DERAT_64K_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Average number of run cycles per completed run instruction",
Here we cover our bases and say "completed run instruction". ;-)
Let's convert this one to whichever phrase is chosen for PM_RUN_INST_CMPL.
Seen below, too.
> + "MetricExpr": "PM_RUN_CYC / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "RUN_CPI"
> + },
> + {
> + "BriefDescription": "Total number of run cycles",
> + "MetricExpr": "PM_RUN_CYC",
Isn't this more an event than a metric?
Does it need to be included here?
> + "MetricGroup": "General",
> + "MetricName": "TOTAL_RUN_CYCLES"
> + },
> + {
> + "BriefDescription": "Percentage of DERAT misses per completed run instruction",
> + "MetricExpr": "PM_DERAT_MISS / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "Translation",
> + "MetricName": "DERAT_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Average number of completed run instructions per run cycle",
> + "MetricExpr": "PM_RUN_INST_CMPL / PM_RUN_CYC",
> + "MetricGroup": "General",
> + "MetricName": "RUN_IPC"
> + },
> + {
> + "BriefDescription": "Average number of instruction completed per instruction group",
s/instruction/instructions/
> + "MetricExpr": "PM_RUN_INST_CMPL / PM_1PLUS_PPC_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "AVERAGE_COMPLETED_INSTRUCTION_SET_SIZE"
> + },
> + {
> + "BriefDescription": "Rate of finished instructions per completed instructions",
> + "MetricExpr": "PM_INST_FIN / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "INST_FIN_PER_CMPL"
> + },
> + {
> + "BriefDescription": "Average cycles per instruction when the ntf instruction is completing and the finish was overlooked",
s/ntf/NTF/
"overlooked" seems like an odd term.
> + "MetricExpr": "PM_EXEC_STALL_UNKNOWN / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "EXEC_STALL_UNKOWN_CPI"
> + },
> + {
> + "BriefDescription": "Percentage of finished branches that were taken",
> + "MetricExpr": "PM_BR_TAKEN_CMPL / PM_BR_FIN * 100",
> + "MetricGroup": "General",
> + "MetricName": "TAKEN_BRANCHES",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of completed instructions that were a demand load that did not hit in the L1, L2, or the L3",
> + "MetricExpr": "PM_DATA_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "General",
> + "MetricName": "L3_LD_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Rate of finished branches per completed instruction",
> + "MetricExpr": "PM_BR_FIN / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "BRANCHES_PER_INST"
> + },
> + {
> + "BriefDescription": "Rate of instructions finished in the LSU per completed instruction",
> + "MetricExpr": "PM_LSU_FIN / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "LSU_PER_INST"
> + },
> + {
> + "BriefDescription": "Rate of instructions finished in the VSU per completed instruction",
> + "MetricExpr": "PM_VSU_FIN / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "VSU_PER_INST"
> + },
> + {
> + "BriefDescription": "Rate of TLBIE instructions finished in the LSU per completed instruction",
> + "MetricExpr": "PM_TLBIE_FIN / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "TLBIE_PER_INST"
> + },
> + {
> + "BriefDescription": "Rate of STCX instructions finshed per completed instruction",
> + "MetricExpr": "PM_STCX_FIN / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "STXC_PER_INST"
> + },
> + {
> + "BriefDescription": "Rate of LARX instructions finshed per completed instruction",
> + "MetricExpr": "PM_LARX_FIN / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "LARX_PER_INST"
> + },
> + {
> + "BriefDescription": "Rate of ptesync instructions finshed per completed instruction",
> + "MetricExpr": "PM_PTESYNC_FIN / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "PTESYNC_PER_INST"
> + },
> + {
> + "BriefDescription": "Rate of simple fixed-point instructions finshed in the store unit per completed instruction",
s/store unit/LSU/ ?
> + "MetricExpr": "PM_FX_LSU_FIN / PM_RUN_INST_CMPL",
> + "MetricGroup": "General",
> + "MetricName": "FX_PER_INST"
> + },
> + {
> + "BriefDescription": "Percentage of demand load misses that reloaded the L1 cache",
> + "MetricExpr": "PM_LD_DEMAND_MISS_L1 / PM_LD_MISS_L1 * 100",
> + "MetricGroup": "General",
> + "MetricName": "DL1_MISS_RELOADS",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of demand load misses that reloaded from beyond the local L2",
> + "MetricExpr": "PM_DATA_FROM_L2MISS / PM_LD_DEMAND_MISS_L1 * 100",
> + "MetricGroup": "dL1_Reloads",
> + "MetricName": "DL1_RELOAD_FROM_L2_MISS",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of demand load misses that reloaded from beyond the local L3",
> + "MetricExpr": "PM_DATA_FROM_L3MISS / PM_LD_DEMAND_MISS_L1 * 100",
> + "MetricGroup": "dL1_Reloads",
> + "MetricName": "DL1_RELOAD_FROM_L3_MISS",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of cycles stalled due to the ntc instruction waiting for a load miss to resolve from a source beyond the local L2 and local L3",
> + "MetricExpr": "DMISS_L3MISS_STALL_CPI / RUN_CPI * 100",
> + "MetricGroup": "General",
> + "MetricName": "DCACHE_MISS_CPI",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of DERAT misses with 2M page size per completed run instruction",
> + "MetricExpr": "PM_DERAT_MISS_2M / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "Translation",
> + "MetricName": "DERAT_2M_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of DERAT misses with 16M page size per completed run instruction",
> + "MetricExpr": "PM_DERAT_MISS_16M / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "Translation",
> + "MetricName": "DERAT_16M_MISS_RATE",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "DERAT miss ratio for 4K page size",
> + "MetricExpr": "PM_DERAT_MISS_4K / PM_DERAT_MISS",
> + "MetricGroup": "Translation",
> + "MetricName": "DERAT_4K_MISS_RATIO"
> + },
> + {
> + "BriefDescription": "DERAT miss ratio for 2M page size",
> + "MetricExpr": "PM_DERAT_MISS_2M / PM_DERAT_MISS",
> + "MetricGroup": "Translation",
> + "MetricName": "DERAT_2M_MISS_RATIO"
> + },
> + {
> + "BriefDescription": "DERAT miss ratio for 16M page size",
> + "MetricExpr": "PM_DERAT_MISS_16M / PM_DERAT_MISS",
> + "MetricGroup": "Translation",
> + "MetricName": "DERAT_16M_MISS_RATIO"
> + },
> + {
> + "BriefDescription": "DERAT miss ratio for 64K page size",
> + "MetricExpr": "PM_DERAT_MISS_64K / PM_DERAT_MISS",
> + "MetricGroup": "Translation",
> + "MetricName": "DERAT_64K_MISS_RATIO"
> + },
> + {
> + "BriefDescription": "Percentage of DERAT misses that resulted in TLB reloads",
> + "MetricExpr": "PM_DTLB_MISS / PM_DERAT_MISS * 100",
> + "MetricGroup": "Translation",
> + "MetricName": "DERAT_MISS_RELOAD",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of ICache misses that were reloaded from beyond the local L3",
Sometimes we use "ICache" and sometimes "icache". Pick one.
> + "MetricExpr": "PM_INST_FROM_L3MISS / PM_L1_ICACHE_MISS * 100",
> + "MetricGroup": "Instruction_Misses",
> + "MetricName": "INST_FROM_L3_MISS",
> + "ScaleUnit": "1%"
> + },
> + {
> + "BriefDescription": "Percentage of ICache reloads from the beyond the L3 per completed run instruction",
> + "MetricExpr": "PM_INST_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
> + "MetricGroup": "Instruction_Misses",
> + "MetricName": "INST_FROM_L3_MISS_RATE",
> + "ScaleUnit": "1%"
> + }
> +]
PC
^ permalink raw reply
* Re: [PATCH 06/12] openrisc: Use of_get_cpu_hwid()
From: Stafford Horne @ 2021-10-06 20:44 UTC (permalink / raw)
To: Rob Herring
Cc: Rich Felker, Rafael J. Wysocki, linux-kernel, Guo Ren,
H. Peter Anvin, linux-riscv, Will Deacon, Jonas Bonn,
Florian Fainelli, Yoshinori Sato, linux-sh, x86, Russell King,
linux-csky, Ingo Molnar, bcm-kernel-feedback-list,
Catalin Marinas, Palmer Dabbelt, devicetree, Albert Ou, Ray Jui,
Stefan Kristiansson, openrisc, Borislav Petkov, Paul Walmsley,
Thomas Gleixner, linux-arm-kernel, Scott Branden,
Greg Kroah-Hartman, Frank Rowand, James Morse, Paul Mackerras,
linuxppc-dev
In-Reply-To: <20211006164332.1981454-7-robh@kernel.org>
On Wed, Oct 06, 2021 at 11:43:26AM -0500, Rob Herring wrote:
> Replace open coded parsing of CPU nodes' 'reg' property with
> of_get_cpu_hwid().
>
> Cc: Jonas Bonn <jonas@southpole.se>
> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> Cc: Stafford Horne <shorne@gmail.com>
> Cc: openrisc@lists.librecores.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> arch/openrisc/kernel/smp.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
> index 415e209732a3..7d5a4f303a5a 100644
> --- a/arch/openrisc/kernel/smp.c
> +++ b/arch/openrisc/kernel/smp.c
> @@ -65,11 +65,7 @@ void __init smp_init_cpus(void)
> u32 cpu_id;
>
> for_each_of_cpu_node(cpu) {
> - if (of_property_read_u32(cpu, "reg", &cpu_id)) {
> - pr_warn("%s missing reg property", cpu->full_name);
> - continue;
> - }
> -
> + cpu_id = of_get_cpu_hwid(cpu);
You have defined of_get_cpu_hwid to return u64, will this create compiler
warnings when since we are storing a u64 into a u32?
It seems only if we make with W=3.
I thought we usually warned on this. Oh well, for the openrisc bits.
Acked-by: Stafford Horne <shorne@gmail.com>
> if (cpu_id < NR_CPUS)
> set_cpu_possible(cpu_id, true);
> }
> --
> 2.30.2
>
^ permalink raw reply
* Re: [PATCH 06/12] openrisc: Use of_get_cpu_hwid()
From: Rob Herring @ 2021-10-06 21:08 UTC (permalink / raw)
To: Stafford Horne
Cc: Rich Felker, Rafael J. Wysocki, linux-kernel@vger.kernel.org,
Guo Ren, H. Peter Anvin, linux-riscv, Will Deacon, Jonas Bonn,
Florian Fainelli, Yoshinori Sato, SH-Linux, X86 ML, Russell King,
linux-csky, Ingo Molnar,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Catalin Marinas,
Palmer Dabbelt, devicetree, Albert Ou, Ray Jui,
Stefan Kristiansson, Openrisc, Borislav Petkov, Paul Walmsley,
Thomas Gleixner, linux-arm-kernel, Scott Branden,
Greg Kroah-Hartman, Frank Rowand, James Morse, Paul Mackerras,
linuxppc-dev
In-Reply-To: <YV4KkAC2p9D4yCnH@antec>
On Wed, Oct 6, 2021 at 3:44 PM Stafford Horne <shorne@gmail.com> wrote:
>
> On Wed, Oct 06, 2021 at 11:43:26AM -0500, Rob Herring wrote:
> > Replace open coded parsing of CPU nodes' 'reg' property with
> > of_get_cpu_hwid().
> >
> > Cc: Jonas Bonn <jonas@southpole.se>
> > Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > Cc: Stafford Horne <shorne@gmail.com>
> > Cc: openrisc@lists.librecores.org
> > Signed-off-by: Rob Herring <robh@kernel.org>
> > ---
> > arch/openrisc/kernel/smp.c | 6 +-----
> > 1 file changed, 1 insertion(+), 5 deletions(-)
> >
> > diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
> > index 415e209732a3..7d5a4f303a5a 100644
> > --- a/arch/openrisc/kernel/smp.c
> > +++ b/arch/openrisc/kernel/smp.c
> > @@ -65,11 +65,7 @@ void __init smp_init_cpus(void)
> > u32 cpu_id;
> >
> > for_each_of_cpu_node(cpu) {
> > - if (of_property_read_u32(cpu, "reg", &cpu_id)) {
> > - pr_warn("%s missing reg property", cpu->full_name);
> > - continue;
> > - }
> > -
> > + cpu_id = of_get_cpu_hwid(cpu);
Oops, that should be: of_get_cpu_hwid(cpu, 0);
I thought I double checked all those...
> You have defined of_get_cpu_hwid to return u64, will this create compiler
> warnings when since we are storing a u64 into a u32?
I'm counting on the caller to know the max size for their platform.
>
> It seems only if we make with W=3.
>
> I thought we usually warned on this. Oh well, for the openrisc bits.
That's only on ptr truncation I think.
> Acked-by: Stafford Horne <shorne@gmail.com>
>
> > if (cpu_id < NR_CPUS)
> > set_cpu_possible(cpu_id, true);
> > }
> > --
> > 2.30.2
> >
^ permalink raw reply
* [PATCH] docs: typo fixes in Documentation/ABI/
From: Sohaib Mohamed @ 2021-10-06 12:13 UTC (permalink / raw)
To: sohaib.amhmd
Cc: Daejun Park, Adrian Hunter, Can Guo, Bean Huo, Jonathan Corbet,
Mauro Carvalho Chehab, Jason Gunthorpe, Lukas Bulwahn,
Ilya Dryomov, Jack Wang, Andrew Donnellan, Avri Altman,
Jonathan Cameron, Fabrice Gasnier, Zhang Rui, Jens Axboe,
Martin K. Petersen, Greg Kroah-Hartman, Gioh Kim, linux-kernel,
Frederic Barrat, linuxppc-dev
Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com>
---
Documentation/ABI/stable/sysfs-module | 2 +-
Documentation/ABI/testing/sysfs-bus-rapidio | 2 +-
Documentation/ABI/testing/sysfs-class-cxl | 4 ++--
Documentation/ABI/testing/sysfs-class-rnbd-client | 2 +-
Documentation/ABI/testing/sysfs-class-rtrs-client | 2 +-
Documentation/ABI/testing/sysfs-class-rtrs-server | 2 +-
Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD | 2 +-
Documentation/ABI/testing/sysfs-devices-power | 2 +-
Documentation/ABI/testing/sysfs-driver-ufs | 2 +-
Documentation/ABI/testing/sysfs-firmware-acpi | 2 +-
10 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/Documentation/ABI/stable/sysfs-module b/Documentation/ABI/stable/sysfs-module
index 560b4a3278df..41b1f16e8795 100644
--- a/Documentation/ABI/stable/sysfs-module
+++ b/Documentation/ABI/stable/sysfs-module
@@ -38,7 +38,7 @@ What: /sys/module/<MODULENAME>/srcversion
Date: Jun 2005
Description:
If the module source has MODULE_VERSION, this file will contain
- the checksum of the the source code.
+ the checksum of the source code.
What: /sys/module/<MODULENAME>/version
Date: Jun 2005
diff --git a/Documentation/ABI/testing/sysfs-bus-rapidio b/Documentation/ABI/testing/sysfs-bus-rapidio
index f8b6728dac10..9e8fbff99b75 100644
--- a/Documentation/ABI/testing/sysfs-bus-rapidio
+++ b/Documentation/ABI/testing/sysfs-bus-rapidio
@@ -95,7 +95,7 @@ Contact: Matt Porter <mporter@kernel.crashing.org>,
Alexandre Bounine <alexandre.bounine@idt.com>
Description:
(RO) returns name of previous device (switch) on the path to the
- device that that owns this attribute
+ device that owns this attribute
What: /sys/bus/rapidio/devices/<nn>:<d>:<iiii>/modalias
Date: Jul, 2013
diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation/ABI/testing/sysfs-class-cxl
index 3c77677e0ca7..594fda254130 100644
--- a/Documentation/ABI/testing/sysfs-class-cxl
+++ b/Documentation/ABI/testing/sysfs-class-cxl
@@ -103,8 +103,8 @@ What: /sys/class/cxl/<afu>/api_version_compatible
Date: September 2014
Contact: linuxppc-dev@lists.ozlabs.org
Description: read only
- Decimal value of the the lowest version of the userspace API
- this this kernel supports.
+ Decimal value of the lowest version of the userspace API
+ this kernel supports.
Users: https://github.com/ibm-capi/libcxl
diff --git a/Documentation/ABI/testing/sysfs-class-rnbd-client b/Documentation/ABI/testing/sysfs-class-rnbd-client
index 0b5997ab3365..e6cdc851952c 100644
--- a/Documentation/ABI/testing/sysfs-class-rnbd-client
+++ b/Documentation/ABI/testing/sysfs-class-rnbd-client
@@ -128,6 +128,6 @@ Description: For each device mapped on the client a new symbolic link is created
The <device_id> of each device is created as follows:
- If the 'device_path' provided during mapping contains slashes ("/"),
- they are replaced by exclamation mark ("!") and used as as the
+ they are replaced by exclamation mark ("!") and used as the
<device_id>. Otherwise, the <device_id> will be the same as the
"device_path" provided.
diff --git a/Documentation/ABI/testing/sysfs-class-rtrs-client b/Documentation/ABI/testing/sysfs-class-rtrs-client
index 49a4157c7bf1..fecc59d1b96f 100644
--- a/Documentation/ABI/testing/sysfs-class-rtrs-client
+++ b/Documentation/ABI/testing/sysfs-class-rtrs-client
@@ -78,7 +78,7 @@ What: /sys/class/rtrs-client/<session-name>/paths/<src@dst>/hca_name
Date: Feb 2020
KernelVersion: 5.7
Contact: Jack Wang <jinpu.wang@cloud.ionos.com> Danil Kipnis <danil.kipnis@cloud.ionos.com>
-Description: RO, Contains the the name of HCA the connection established on.
+Description: RO, Contains the name of HCA the connection established on.
What: /sys/class/rtrs-client/<session-name>/paths/<src@dst>/hca_port
Date: Feb 2020
diff --git a/Documentation/ABI/testing/sysfs-class-rtrs-server b/Documentation/ABI/testing/sysfs-class-rtrs-server
index 3b6d5b067df0..b08601d80409 100644
--- a/Documentation/ABI/testing/sysfs-class-rtrs-server
+++ b/Documentation/ABI/testing/sysfs-class-rtrs-server
@@ -24,7 +24,7 @@ What: /sys/class/rtrs-server/<session-name>/paths/<src@dst>/hca_name
Date: Feb 2020
KernelVersion: 5.7
Contact: Jack Wang <jinpu.wang@cloud.ionos.com> Danil Kipnis <danil.kipnis@cloud.ionos.com>
-Description: RO, Contains the the name of HCA the connection established on.
+Description: RO, Contains the name of HCA the connection established on.
What: /sys/class/rtrs-server/<session-name>/paths/<src@dst>/hca_port
Date: Feb 2020
diff --git a/Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD b/Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD
index f7b360a61b21..bc44bc903bc8 100644
--- a/Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD
+++ b/Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD
@@ -74,7 +74,7 @@ Description:
Reads also cause the AC alarm timer status to be reset.
- Another way to reset the the status of the AC alarm timer is to
+ Another way to reset the status of the AC alarm timer is to
write (the number) 0 to this file.
If the status return value indicates that the timer has expired,
diff --git a/Documentation/ABI/testing/sysfs-devices-power b/Documentation/ABI/testing/sysfs-devices-power
index 1b2a2d41ff80..54195530e97a 100644
--- a/Documentation/ABI/testing/sysfs-devices-power
+++ b/Documentation/ABI/testing/sysfs-devices-power
@@ -303,5 +303,5 @@ Date: Apr 2010
Contact: Dominik Brodowski <linux@dominikbrodowski.net>
Description:
Reports the runtime PM children usage count of a device, or
- 0 if the the children will be ignored.
+ 0 if the children will be ignored.
diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI/testing/sysfs-driver-ufs
index 863cc4897277..57aec11a573f 100644
--- a/Documentation/ABI/testing/sysfs-driver-ufs
+++ b/Documentation/ABI/testing/sysfs-driver-ufs
@@ -983,7 +983,7 @@ Description: This file shows the amount of data that the host plans to
What: /sys/class/scsi_device/*/device/dyn_cap_needed
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
-Description: This file shows the The amount of physical memory needed
+Description: This file shows The amount of physical memory needed
to be removed from the physical memory resources pool of
the particular logical unit. The full information about
the attribute could be found at UFS specifications 2.1.
diff --git a/Documentation/ABI/testing/sysfs-firmware-acpi b/Documentation/ABI/testing/sysfs-firmware-acpi
index 819939d858c9..39173375c53a 100644
--- a/Documentation/ABI/testing/sysfs-firmware-acpi
+++ b/Documentation/ABI/testing/sysfs-firmware-acpi
@@ -112,7 +112,7 @@ Description:
OS context. GPE 0x12, for example, would vector
to a level or edge handler called _L12 or _E12.
The handler may do its business and return.
- Or the handler may send send a Notify event
+ Or the handler may send a Notify event
to a Linux device driver registered on an ACPI device,
such as a battery, or a processor.
--
2.25.1
^ permalink raw reply related
* [PATCH] docs: typo fixes in Documentation/ABI/
From: Sohaib Mohamed @ 2021-10-06 13:20 UTC (permalink / raw)
To: sohaib.amhmd
Cc: Daejun Park, Gioh Kim, Can Guo, Bean Huo, Fabrice Gasnier,
Jonathan Corbet, Mauro Carvalho Chehab, Jason Gunthorpe,
Lukas Bulwahn, Zhang Rui, Jack Wang, Andrew Donnellan,
Avri Altman, Jonathan Cameron, Adrian Hunter, Carlos Bilbao,
Jens Axboe, Martin K. Petersen, Greg Kroah-Hartman, linux-kernel,
Frederic Barrat, linuxppc-dev
All these changes are about to remove repeated words from severals place in the Documentation/ABI/ directory:
- In file stable/sysfs-module:41: "the the source"
- In file testing/sysfs-bus-rapidio:98: "that that owns"
- In file testing/sysfs-class-cxl:106: "the the lowest"
- In file testing/sysfs-class-cxl:107: "this this kernel"
- In file testing/sysfs-class-rnbd-client:131: "as as the"
- In file testing/sysfs-class-rtrs-client:81: "the the name"
- In file testing/sysfs-class-rtrs-server:27: "the the name"
- In file testing/sysfs-devices-platform-ACPI-TAD:77: "the the status"
- In file testing/sysfs-devices-power:306: "the the children"
- In file testing/sysfs-driver-ufs:986: "the The amount"
- In file testing/sysfs-firmware-acpi:115: "send send a Notify"
Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com>
---
Documentation/ABI/stable/sysfs-module | 2 +-
Documentation/ABI/testing/sysfs-bus-rapidio | 2 +-
Documentation/ABI/testing/sysfs-class-cxl | 4 ++--
Documentation/ABI/testing/sysfs-class-rnbd-client | 2 +-
Documentation/ABI/testing/sysfs-class-rtrs-client | 2 +-
Documentation/ABI/testing/sysfs-class-rtrs-server | 2 +-
Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD | 2 +-
Documentation/ABI/testing/sysfs-devices-power | 2 +-
Documentation/ABI/testing/sysfs-driver-ufs | 2 +-
Documentation/ABI/testing/sysfs-firmware-acpi | 2 +-
10 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/Documentation/ABI/stable/sysfs-module b/Documentation/ABI/stable/sysfs-module
index 560b4a3278df..41b1f16e8795 100644
--- a/Documentation/ABI/stable/sysfs-module
+++ b/Documentation/ABI/stable/sysfs-module
@@ -38,7 +38,7 @@ What: /sys/module/<MODULENAME>/srcversion
Date: Jun 2005
Description:
If the module source has MODULE_VERSION, this file will contain
- the checksum of the the source code.
+ the checksum of the source code.
What: /sys/module/<MODULENAME>/version
Date: Jun 2005
diff --git a/Documentation/ABI/testing/sysfs-bus-rapidio b/Documentation/ABI/testing/sysfs-bus-rapidio
index f8b6728dac10..9e8fbff99b75 100644
--- a/Documentation/ABI/testing/sysfs-bus-rapidio
+++ b/Documentation/ABI/testing/sysfs-bus-rapidio
@@ -95,7 +95,7 @@ Contact: Matt Porter <mporter@kernel.crashing.org>,
Alexandre Bounine <alexandre.bounine@idt.com>
Description:
(RO) returns name of previous device (switch) on the path to the
- device that that owns this attribute
+ device that owns this attribute
What: /sys/bus/rapidio/devices/<nn>:<d>:<iiii>/modalias
Date: Jul, 2013
diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation/ABI/testing/sysfs-class-cxl
index 3c77677e0ca7..594fda254130 100644
--- a/Documentation/ABI/testing/sysfs-class-cxl
+++ b/Documentation/ABI/testing/sysfs-class-cxl
@@ -103,8 +103,8 @@ What: /sys/class/cxl/<afu>/api_version_compatible
Date: September 2014
Contact: linuxppc-dev@lists.ozlabs.org
Description: read only
- Decimal value of the the lowest version of the userspace API
- this this kernel supports.
+ Decimal value of the lowest version of the userspace API
+ this kernel supports.
Users: https://github.com/ibm-capi/libcxl
diff --git a/Documentation/ABI/testing/sysfs-class-rnbd-client b/Documentation/ABI/testing/sysfs-class-rnbd-client
index 0b5997ab3365..e6cdc851952c 100644
--- a/Documentation/ABI/testing/sysfs-class-rnbd-client
+++ b/Documentation/ABI/testing/sysfs-class-rnbd-client
@@ -128,6 +128,6 @@ Description: For each device mapped on the client a new symbolic link is created
The <device_id> of each device is created as follows:
- If the 'device_path' provided during mapping contains slashes ("/"),
- they are replaced by exclamation mark ("!") and used as as the
+ they are replaced by exclamation mark ("!") and used as the
<device_id>. Otherwise, the <device_id> will be the same as the
"device_path" provided.
diff --git a/Documentation/ABI/testing/sysfs-class-rtrs-client b/Documentation/ABI/testing/sysfs-class-rtrs-client
index 49a4157c7bf1..fecc59d1b96f 100644
--- a/Documentation/ABI/testing/sysfs-class-rtrs-client
+++ b/Documentation/ABI/testing/sysfs-class-rtrs-client
@@ -78,7 +78,7 @@ What: /sys/class/rtrs-client/<session-name>/paths/<src@dst>/hca_name
Date: Feb 2020
KernelVersion: 5.7
Contact: Jack Wang <jinpu.wang@cloud.ionos.com> Danil Kipnis <danil.kipnis@cloud.ionos.com>
-Description: RO, Contains the the name of HCA the connection established on.
+Description: RO, Contains the name of HCA the connection established on.
What: /sys/class/rtrs-client/<session-name>/paths/<src@dst>/hca_port
Date: Feb 2020
diff --git a/Documentation/ABI/testing/sysfs-class-rtrs-server b/Documentation/ABI/testing/sysfs-class-rtrs-server
index 3b6d5b067df0..b08601d80409 100644
--- a/Documentation/ABI/testing/sysfs-class-rtrs-server
+++ b/Documentation/ABI/testing/sysfs-class-rtrs-server
@@ -24,7 +24,7 @@ What: /sys/class/rtrs-server/<session-name>/paths/<src@dst>/hca_name
Date: Feb 2020
KernelVersion: 5.7
Contact: Jack Wang <jinpu.wang@cloud.ionos.com> Danil Kipnis <danil.kipnis@cloud.ionos.com>
-Description: RO, Contains the the name of HCA the connection established on.
+Description: RO, Contains the name of HCA the connection established on.
What: /sys/class/rtrs-server/<session-name>/paths/<src@dst>/hca_port
Date: Feb 2020
diff --git a/Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD b/Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD
index f7b360a61b21..bc44bc903bc8 100644
--- a/Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD
+++ b/Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD
@@ -74,7 +74,7 @@ Description:
Reads also cause the AC alarm timer status to be reset.
- Another way to reset the the status of the AC alarm timer is to
+ Another way to reset the status of the AC alarm timer is to
write (the number) 0 to this file.
If the status return value indicates that the timer has expired,
diff --git a/Documentation/ABI/testing/sysfs-devices-power b/Documentation/ABI/testing/sysfs-devices-power
index 1b2a2d41ff80..54195530e97a 100644
--- a/Documentation/ABI/testing/sysfs-devices-power
+++ b/Documentation/ABI/testing/sysfs-devices-power
@@ -303,5 +303,5 @@ Date: Apr 2010
Contact: Dominik Brodowski <linux@dominikbrodowski.net>
Description:
Reports the runtime PM children usage count of a device, or
- 0 if the the children will be ignored.
+ 0 if the children will be ignored.
diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI/testing/sysfs-driver-ufs
index 863cc4897277..57aec11a573f 100644
--- a/Documentation/ABI/testing/sysfs-driver-ufs
+++ b/Documentation/ABI/testing/sysfs-driver-ufs
@@ -983,7 +983,7 @@ Description: This file shows the amount of data that the host plans to
What: /sys/class/scsi_device/*/device/dyn_cap_needed
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
-Description: This file shows the The amount of physical memory needed
+Description: This file shows The amount of physical memory needed
to be removed from the physical memory resources pool of
the particular logical unit. The full information about
the attribute could be found at UFS specifications 2.1.
diff --git a/Documentation/ABI/testing/sysfs-firmware-acpi b/Documentation/ABI/testing/sysfs-firmware-acpi
index 819939d858c9..39173375c53a 100644
--- a/Documentation/ABI/testing/sysfs-firmware-acpi
+++ b/Documentation/ABI/testing/sysfs-firmware-acpi
@@ -112,7 +112,7 @@ Description:
OS context. GPE 0x12, for example, would vector
to a level or edge handler called _L12 or _E12.
The handler may do its business and return.
- Or the handler may send send a Notify event
+ Or the handler may send a Notify event
to a Linux device driver registered on an ACPI device,
such as a battery, or a processor.
--
2.25.1
^ permalink raw reply related
* [PATCH] Documentation: Fix typo in testing/sysfs-class-cxl
From: Sohaib Mohamed @ 2021-10-06 14:39 UTC (permalink / raw)
To: sohaib.amhmd
Cc: Frederic Barrat, linuxppc-dev, Andrew Donnellan, linux-kernel
Remove repeated worlds: "the the lowest" and "this this kernel"
Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com>
---
Documentation/ABI/testing/sysfs-class-cxl | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation/ABI/testing/sysfs-class-cxl
index 3c77677e0ca7..594fda254130 100644
--- a/Documentation/ABI/testing/sysfs-class-cxl
+++ b/Documentation/ABI/testing/sysfs-class-cxl
@@ -103,8 +103,8 @@ What: /sys/class/cxl/<afu>/api_version_compatible
Date: September 2014
Contact: linuxppc-dev@lists.ozlabs.org
Description: read only
- Decimal value of the the lowest version of the userspace API
- this this kernel supports.
+ Decimal value of the lowest version of the userspace API
+ this kernel supports.
Users: https://github.com/ibm-capi/libcxl
--
2.25.1
^ permalink raw reply related
* [PATCH] Documentation: Fix typo in testing/sysfs-class-cxl
From: Sohaib Mohamed @ 2021-10-06 15:50 UTC (permalink / raw)
To: sohaib.amhmd
Cc: Frederic Barrat, linuxppc-dev, Andrew Donnellan, linux-kernel
Remove repeated words: "the the lowest" and "this this kernel"
Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com>
---
Documentation/ABI/testing/sysfs-class-cxl | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation/ABI/testing/sysfs-class-cxl
index 3c77677e0ca7..594fda254130 100644
--- a/Documentation/ABI/testing/sysfs-class-cxl
+++ b/Documentation/ABI/testing/sysfs-class-cxl
@@ -103,8 +103,8 @@ What: /sys/class/cxl/<afu>/api_version_compatible
Date: September 2014
Contact: linuxppc-dev@lists.ozlabs.org
Description: read only
- Decimal value of the the lowest version of the userspace API
- this this kernel supports.
+ Decimal value of the lowest version of the userspace API
+ this kernel supports.
Users: https://github.com/ibm-capi/libcxl
--
2.25.1
^ permalink raw reply related
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