* RE: [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz()
2024-05-23 12:21 ` [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz() Seongsu Park
@ 2024-06-03 11:02 ` Seongsu Park
2024-06-24 12:37 ` Seongsu Park
2024-06-24 18:12 ` Catalin Marinas
2 siblings, 0 replies; 4+ messages in thread
From: Seongsu Park @ 2024-06-03 11:02 UTC (permalink / raw)
To: catalin.marinas, will, ardb, mark.rutland
Cc: linux-arm-kernel, linux-kernel, infinite.run, sgsu.park
Dear All,
Please check this patch.
I think this patch is appropriate.
Thanks.
Seongsu Park.
> -----Original Message-----
> From: Seongsu Park <sgsu.park@samsung.com>
> Sent: Thursday, May 23, 2024 9:22 PM
> To: catalin.marinas@arm.com; will@kernel.org; ardb@kernel.org;
> mark.rutland@arm.com
> Cc: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> infinite.run@gmail.com; sgsu.park@samsung.com
> Subject: [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz()
>
> The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and encode the
> virtual address space translated by TTBR0_EL1. When updating the field,
> for example because we are switching to/from the idmap page-table,
> __cpu_set_tcr_t0sz() erroneously treats its 't0sz' argument as unshifted,
> resulting in harmless but confusing double shifts by 0 in the code.
>
> Co-developed-by: Leem ChaeHoon <infinite.run@gmail.com>
> Signed-off-by: Leem ChaeHoon <infinite.run@gmail.com>
> Signed-off-by: Seongsu Park <sgsu.park@samsung.com>
> ---
> arch/arm64/include/asm/mmu_context.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/mmu_context.h
> b/arch/arm64/include/asm/mmu_context.h
> index c768d16b81a4..bd19f4c758b7 100644
> --- a/arch/arm64/include/asm/mmu_context.h
> +++ b/arch/arm64/include/asm/mmu_context.h
> @@ -72,11 +72,11 @@ static inline void __cpu_set_tcr_t0sz(unsigned long
> t0sz) {
> unsigned long tcr = read_sysreg(tcr_el1);
>
> - if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz)
> + if ((tcr & TCR_T0SZ_MASK) == t0sz)
> return;
>
> tcr &= ~TCR_T0SZ_MASK;
> - tcr |= t0sz << TCR_T0SZ_OFFSET;
> + tcr |= t0sz;
> write_sysreg(tcr, tcr_el1);
> isb();
> }
> --
> 2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread* RE: [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz()
2024-05-23 12:21 ` [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz() Seongsu Park
2024-06-03 11:02 ` Seongsu Park
@ 2024-06-24 12:37 ` Seongsu Park
2024-06-24 18:12 ` Catalin Marinas
2 siblings, 0 replies; 4+ messages in thread
From: Seongsu Park @ 2024-06-24 12:37 UTC (permalink / raw)
To: catalin.marinas, will, ardb, mark.rutland
Cc: linux-arm-kernel, linux-kernel, infinite.run, 'sgsu.park
Dear Will,
Could you check this patch?
This patch will make the code more stable.
Thanks.
Seongsu Park.
> -----Original Message-----
> From: Seongsu Park <sgsu.park@samsung.com>
> Sent: Monday, June 3, 2024 8:03 PM
> To: 'catalin.marinas@arm.com' <catalin.marinas@arm.com>; 'will@kernel.org'
> <will@kernel.org>; 'ardb@kernel.org' <ardb@kernel.org>;
> 'mark.rutland@arm.com' <mark.rutland@arm.com>
> Cc: 'linux-arm-kernel@lists.infradead.org' <linux-arm-
> kernel@lists.infradead.org>; 'linux-kernel@vger.kernel.org' <linux-
> kernel@vger.kernel.org>; 'infinite.run@gmail.com' <infinite.run@gmail.com>;
> 'sgsu.park@samsung.com' <sgsu.park@samsung.com>
> Subject: RE: [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz()
>
> Dear All,
>
> Please check this patch.
> I think this patch is appropriate.
>
> Thanks.
> Seongsu Park.
>
> > -----Original Message-----
> > From: Seongsu Park <sgsu.park@samsung.com>
> > Sent: Thursday, May 23, 2024 9:22 PM
> > To: catalin.marinas@arm.com; will@kernel.org; ardb@kernel.org;
> > mark.rutland@arm.com
> > Cc: linux-arm-kernel@lists.infradead.org;
> > linux-kernel@vger.kernel.org; infinite.run@gmail.com;
> > sgsu.park@samsung.com
> > Subject: [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz()
> >
> > The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and encode
> > the virtual address space translated by TTBR0_EL1. When updating the
> > field, for example because we are switching to/from the idmap
> > page-table,
> > __cpu_set_tcr_t0sz() erroneously treats its 't0sz' argument as
> > unshifted, resulting in harmless but confusing double shifts by 0 in the
> code.
> >
> > Co-developed-by: Leem ChaeHoon <infinite.run@gmail.com>
> > Signed-off-by: Leem ChaeHoon <infinite.run@gmail.com>
> > Signed-off-by: Seongsu Park <sgsu.park@samsung.com>
> > ---
> > arch/arm64/include/asm/mmu_context.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/include/asm/mmu_context.h
> > b/arch/arm64/include/asm/mmu_context.h
> > index c768d16b81a4..bd19f4c758b7 100644
> > --- a/arch/arm64/include/asm/mmu_context.h
> > +++ b/arch/arm64/include/asm/mmu_context.h
> > @@ -72,11 +72,11 @@ static inline void __cpu_set_tcr_t0sz(unsigned
> > long
> > t0sz) {
> > unsigned long tcr = read_sysreg(tcr_el1);
> >
> > - if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz)
> > + if ((tcr & TCR_T0SZ_MASK) == t0sz)
> > return;
> >
> > tcr &= ~TCR_T0SZ_MASK;
> > - tcr |= t0sz << TCR_T0SZ_OFFSET;
> > + tcr |= t0sz;
> > write_sysreg(tcr, tcr_el1);
> > isb();
> > }
> > --
> > 2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz()
2024-05-23 12:21 ` [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz() Seongsu Park
2024-06-03 11:02 ` Seongsu Park
2024-06-24 12:37 ` Seongsu Park
@ 2024-06-24 18:12 ` Catalin Marinas
2 siblings, 0 replies; 4+ messages in thread
From: Catalin Marinas @ 2024-06-24 18:12 UTC (permalink / raw)
To: will, ardb, mark.rutland, Seongsu Park
Cc: linux-arm-kernel, linux-kernel, infinite.run
On Thu, 23 May 2024 21:21:46 +0900, Seongsu Park wrote:
> The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and encode
> the virtual address space translated by TTBR0_EL1. When updating the
> field, for example because we are switching to/from the idmap page-table,
> __cpu_set_tcr_t0sz() erroneously treats its 't0sz' argument as unshifted,
> resulting in harmless but confusing double shifts by 0 in the code.
>
>
> [...]
Applied to arm64 (for-next/misc), thanks!
[1/1] arm64: Cleanup __cpu_set_tcr_t0sz()
https://git.kernel.org/arm64/c/cf938f91784f
--
Catalin
^ permalink raw reply [flat|nested] 4+ messages in thread